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IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 18  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [228 journals]
  • IEEE Electron Devices Society Information

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • IEEE Transactions on Electron Devices Information for Authors

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      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
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      Abstract: This page or pages intentionally left blank.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Rigorous Modeling and Investigation of Low-Field Hole Mobility in Silicon
           and Germanium Gate-All-Around Nanosheet Transistors

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      Authors: Shuo Zhang;Hao Xie;Jun Z. Huang;Wenchao Chen;Jie Liao;Wen-Yan Yin;
      Pages: 4777 - 4785
      Abstract: The low-field hole mobility in p-type inversion-mode silicon (Si) and germanium (Ge) nanosheet (NS) transistors is rigorously calculated by a physics-based theoretical model, where momentum scatterings from phonons, charged impurities, and surface roughness are all considered. With a holistic physical picture of carrier scattering mechanisms, the effects of material, crystal orientation, channel width, strain/stress, and temperature are investigated comprehensively by the in-house developed numerical simulator. This sound and prospective theoretical work paves the way for clarifying the physics of achieving high hole mobility in ultrascaled NS channels, presenting some valuable insights and guidelines about the device design and fabrication for the next-generation CMOS technology.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Three-Dimensional Simulation Study of the Novel Comb-Like-Channel
           Field-Effect Transistors for the 5-nm Technology Node and Beyond

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      Authors: Xinhao Li;Huilong Zhu;Weizhuo Gan;Weixing Huang;Zhenhua Wu;
      Pages: 4786 - 4790
      Abstract: A novel comb-like-channel field-effect transistor (CombFET), which is the combination of the fin field-effect transistor (FinFET) and nanosheet FET (NshFET) geometries in the channel region, is proposed and evaluated numerically for the first time. Our simulations show that: 1) with the same footprint, CombFET ON-current is 43% higher than FinFET and 53% higher than gate-all-around FET (GAAFET) due to its larger effective channel width and relieved channel quantum confinement and 2) CombFETs have great advantages in performance optimization through surface orientation over FinFETs and NshFETs. Thanks to the unique structural design, CombFET can also be used to improve or eliminate the bending or adhesion effects between nanosheets/comb teeth.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Extraction Method for Equivalent Oxide Thickness of a Thin High-κ Gate
           Insulator and Estimation of Field-Effect Mobility in Amorphous Oxide
           Semiconductor Nano-Sheet Junctionless Transistors

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      Authors: Po-Yi Kuo;Zhen-Hao Li;Chien-Min Chang;Po-Tsun Liu;
      Pages: 4791 - 4795
      Abstract: In this work, we have proposed an extraction method for equivalent oxide thickness (EOT) of a thin high-dielectric-constant ( $kappa $ ) gate insulator (GI) through direct capacitance–voltage ( ${C}$ – ${V}$ ) measurements in amorphous indium tungsten oxide (a-IWO) nano-sheet (NS) junctionless (JL) transistors (a-IWO NS-JLTs). Without additional metal/insulator/Si-substrate (MIS) ${C}$ – ${V}$ measurements, the proposed extraction method can directly extract EOT (or equivalent $kappa $ values) of a thin HfO2GI at different ON-state gate voltages ( ${V}_{G}$ ) in a-IWO NS-JLTs. Results of ${C}$ – ${V}$ measurements show that the extracted EOT varies with ON-state ${V}_{G}$ owing to the gate-controllable conductance of the amorphous oxide semiconductor (AOS) NS channel. Finally, the extracted EOT can be used to estimate the field-effect mobility ( $mu _{text{FE}}$ ) of a-IWO NS-JLTs at different ON-state ${V}_{G}$ .
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Experimental Validation of a Compact Pinhole Latent Defect Model for MOS
           Transistors

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      Authors: Jhon Gomez;Nektar Xama;Dirk Lootens;Anthony Coyette;Ronny Vanhooren;Wim Dobbelaere;Georges Gielen;
      Pages: 4796 - 4802
      Abstract: Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $mu text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Microscopic Simulation of the RF Performance of SiGe HBTs With Additional
           Uniaxial Mechanical Stress

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      Authors: Oliver Dieball;Holger Rücker;Bernd Heinemann;Christoph Jungemann;
      Pages: 4803 - 4809
      Abstract: A very detailed investigation of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) showed an underestimation of the measured peak cutoff frequency by simulations with a hydrodynamic (HD) model. It was speculated that this might be due to a breakdown of the HD approximation or unknown additional mechanical stress. We repeated those simulations with the more fundamental Boltzmann transport equation (BTE) based on the same device model (doping profiles, 2-D geometry, parasitics, and so on) and obtained almost similar results showing that this failure was not due to a breakdown of the HD approximation. Since additional uniaxial stress along the direction of the lateral base has been shown to increase the cutoff frequency, we investigated this effect. We found by 2-D device simulations that the increase in the peak cutoff frequency is rather small, and at high stress levels, it even decreases, if the uniaxial stress is applied homogenously. This is due to the reduction of the conductivity of the highly doped collector layer by the stress. If the stress is limited to the intrinsic transistor, the increase in the cutoff frequency is monotonic with growing stress. On the other hand, the collector current for a given base–emitter voltage also increases with stress leading to an overestimation of the collector current compared with the measurements. If this increase is corrected by a slight decrease in the germanium profile, the gain in the peak cutoff frequency is lost. Thus, the underestimation of the peak cutoff frequency cannot be explained by an additional homogeneous uniaxial stress in the intrinsic transistor.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Influence of Capping Layer on Threshold Voltage for HKMG FinFET With Short
           Channel

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      Authors: Han-Lun Cai;Run-Ling Li;Zhao-Yang Li;Zhong-Hua Li;Yu-Long Jiang;Fang Lu;
      Pages: 4810 - 4814
      Abstract: The influence of SiO2 and SiNx capping layer on threshold voltage ( ${V}_{t}$ ) for FinFET with TiAl-based metal gate (MG) is studied. After metal gate-stack formation, SiNx capping is revealed to be able to serve as a new N source, resulting in the diffusion of N into the effective work function (EWF) TiNx layer. Correspondingly, the accumulation of N in the TiNx layer is demonstrated to be able to lower the EWF for both n- and p-FinFETs. Compared to SiO2 capping, SiNx capping can induce $sim 100$ –150 mV ${V}_{t}$ lowering for short n- and p-FinFETs. No obvious ${V}_{t}$ shift is found for long-channel devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage
           (GIDL) Current of Nanowire GAA MOSFETs

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      Authors: Ashraf Maniyar;P. S. T. N. Srinivas;Pramod Kumar Tiwari;Kuei-Shu Chang-Liao;
      Pages: 4815 - 4820
      Abstract: The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • High-Temperature HEMT Model

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      Authors: Nika Sahebghalam;Majid Shalchian;Amirali Chalechale;Farzan Jazaeri;
      Pages: 4821 - 4827
      Abstract: Taking into account the impact of self-heating and temperature rise effects, this work presents a physics-based analytical model for HEMTs, operating continuously from room temperature to high temperatures in linear and saturation regimes. Relying on the core École Polytechnique Fédérale de Lausanne (EPFL) HEMT model, the temperature dependence of various parameters including mobility, saturation velocity, critical electric fields, access region resistance, threshold voltage, and subthreshold slope was taken into account in the model. The accuracy of the developed model is validated by the TCAD simulation results and experimental data over a wide range of ambient temperatures from −20 °C to 500 °C.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • The Modulation Effect of LPCVD-Si x N y Stoichiometry on 2-DEG
           Characteristic of UTB AlGaN/GaN Heterostructure

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      Authors: Liyang Zhu;Qi Zhou;Kuangli Chen;Wei Gao;Yong Cai;Kai Cheng;Zhaoji Li;Bo Zhang;
      Pages: 4828 - 4834
      Abstract: In this work, the impact of low-pressure chemical vapor deposition (LPCVD)-SixNy stoichiometry on 2-D electron gas (2-DEG) transport characteristics of the AlGaN (3.9 nm)/GaN heterostructure and the underlying mechanism of increased 2-DEG density are studied, which reveals a new perspective of improving AlGaN/GaN performance by dielectric engineering. Among the AlGaN/GaN passivated by the LPCVD-SixNy with tailored stoichiometry, the 2-DEG density and mobility in the Si-rich sample were significantly improved by 25% and 16.3% compared with the N-rich sample, respectively. Accordingly, 30% reduction in sheet resistance of AlGaN/GaN heterostructure is obtained. The potentially strained-induced enhancement of piezoelectric polarization and corresponding 2-DEG variation by the SixNy passivation layer was excluded by the negligible change in Raman spectra among the different samples. Alternatively, the X-ray photoelectron spectroscopy (XPS) showed that the varied stoichiometry of the SixNy enables a discernible modulation effect of heterostructure energy-band. The reduced surface potential in the sample passivated by Si-rich SixNy attributes to the pronounced Ga dangling bonds (DBs) at the LPCVD-SixNy/AlGaN interfaces, which provides the near-conduction band (NCB) states and leads to enhanced 2-DEG accumulation.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Modeling Electrostatics and Low-Field Electron Mobility of GaN FinFETs

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      Authors: Viswanathan Naveen Kumar;Michael Povolotskyi;Dragica Vasileska;
      Pages: 4835 - 4842
      Abstract: Gallium nitride (GaN) high electron mobility transistors (HEMTs) are currently being used for RF applications due to the intrinsically high saturation velocity and high mobility of GaN compared to both Silicon and SiC. However, GaN HEMTs suffer from a variety of issues, such as a lack of E-Mode operation and non-linearity, which impacts their widespread adoption in the RF and low-voltage switching devices. Recent advances in material processing, high aspect ratio epitaxial growth, and etching methods has led to an increased interest in 3-D GaN nanostructures such as AlGaN/GaN MIS FinFET wherein a layer of Al2O3 surrounds the AlGaN/GaN fin. Theoretical calculations of transport properties of AlGaN/GaN FinFETs are scarce compared to those of their planar HEMT counterparts. This work employs for the first time self-consistent solution of the coupled 1-D Boltzmann – 2-D Schrödinger – 3-D Poisson problem to yield the channel electrostatics and the transport characteristics of AlGaN/GaN MIS FinFETs. The low field electron mobility in the quasi-1-D region is calculated, using 1-D ensemble Monte Carlo method, as a function of temperature and fin width. Acoustic, piezoelectric and polar optical phonon scattering, and interface roughness scattering at the AlGaN/GaN interface, are incorporated in the theoretical model. Our simulations suggest that E-mode FinFETs can be achieved in ultranarrow fin channels. As suggested experimentally, we confirm via simulation experiments that strain relaxation increases the sheet resistance of the channel.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • High-Efficiency D-Band Monolithically Integrated GaN SBD-Based Frequency
           Doubler With High Power Handling Capability

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      Authors: Ning An;Li Li;Weiguang Wang;Xiaoyu Xu;Jianping Zeng;
      Pages: 4843 - 4847
      Abstract: A high-efficiency ${D}$ -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Semi-Analytical Method for Determination of Air Bridge Interconnect for
           GaAs-Based p-i-n Diode

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      Authors: Ao Zhang;Jianjun Gao;
      Pages: 4848 - 4852
      Abstract: Semi-analytical method for the determination of extrinsic and intrinsic model parameters for GaAs-based p-i-n diode is presented in this article. The main advantage is that the air-bridge interconnect inductance is regarded as an independent element and can be distinguished from the feedline effect. The detail model parameters extraction procedure is proposed, and the corresponding closed-form expressions are derived. Good agreement is obtained between the simulated and measured S-parameters up to 110 GHz to verify the validity of the approach.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Study on Schottky Al x Ga1-x N/GaN IMPATT Diodes for Millimeter-Wave
           Application

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      Authors: Yang Dai;Jiangtao Dang;Xiaoyi Lei;Yunyao Zhang;Junfeng Yan;Wu Zhao;Xiaojiang Chen;Shenglei Zhao;
      Pages: 4853 - 4858
      Abstract: This article proposes a Schottky aluminum gallium nitride (AlGaN)/GaN single-drift-region (SDR) IMPATT diode that uses AlGaN as the avalanche active layer. Compared with GaN, AlGaN has a wider bandgap and better breakdown characteristics. These features can significantly improve the device performance. We simulated the direct current (DC) and radio frequency (RF) performances of the new structure for the 0.2–0.6 Al composition under the millimeter-wave band and compared the results with the conventional GaN avalanche layer IMPATT. The results indicate that the AlGaN avalanche layer IMPATT significantly improves the breakdown voltage, RF voltage, and RF current performances. Furthermore, the application of AlGaN avalanche layer increases the RF efficiency from 18.16% to 21.98% and increases the RF power from 1.56 to 2.67 MW/cm2. As this structure has greater potential for the millimeter wave, even terahertz application, this article brings a new reference for the design of GaN-based IMPATT diodes.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • High-Performance Normally-Off Operation p-GaN Gate HEMT on Free-Standing
           GaN Substrate

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      Authors: Hsiang-Chun Wang;Taofei Pu;Xiaobo Li;Chia-Hao Liu;JunYe Wu;Jiaying Yang;Ziyue Zhang;Youming Lu;Qi Wang;Lijun Song;Hsien-Chin Chiu;Jin-Ping Ao;Xinke Liu;
      Pages: 4859 - 4863
      Abstract: A normally- OFF AlGaN/GaN high-electron-mobility transistor (HEMT) with p-GaN gate was fabricated on free-standing GaN substrate. The self-terminated etching technology was achieved by combining with AlN stop layer and SF6-based etching gas. Compared with HEMT on Si substrate (Si-HEMT), the HEMT on GaN substrate (GaN-HEMT) demonstrated the higher current density, lower subthreshold swing (SS), lower drain leakage current, and lower static and dynamic ON-resistance that were ascribed to the lower dislocation and less defect on free-standing GaN substrate. Meanwhile, the excellent ${V}_{mathrm{th}}$ stability up to 175 °C and uniformity was demonstrated. Also, higher breakdown voltage (BV) of 683 V was measured, which was higher than 507 V for Si-HEMT. Hence, a normally- OFF AlGaN/GaN HEMT on free-standing GaN substrate shows good potential in power application.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Estimation of Trapping Induced Dynamic Reduction in 2DEG Density of
           GaN-Based HEMTs by Gate-Lag DCT Technique

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      Authors: P. Vigneshwara Raja;Emmanuel Dupouy;Mohamed Bouslama;Raphael Sommet;Jean-Christophe Nallatamby;
      Pages: 4864 - 4869
      Abstract: We derived a simplified analytical expression to estimate the dynamic reduction in the 2DEG density due to the buffer trapping ( ${n}_{T}$ ) in GaN-based high-electron-mobility transistors (HEMTs). To compute ${n}_{T}$ , gate-lag drain current transient (DCT) measurements are carried out at a fixed temperature for different ${V}_{GS}$ points. The dynamic decrease in the 2DEG due to the Fe-related trap at ${E}_{C}$ -0.5 eV is found to be ~ $3.4times10$ 11 cm−2 in AlGaN/GaN HEMT; thus, ${n}_{T}$ is an essential quantity to evaluate the current collapse effects in HEMT. The validity of the expression is further demonstrated in the C-doped HEMTs. The calculated ${n}_{T}$ for the trap at ${E}_{C}$ -0.14 eV is about $9times10$ 12 cm−0 in InAlN/GaN HEMT with C-doped buffer, and the calculated ${n}_{T}$ for the trap at ${E}_{C}$ -0.33 eV is ~ $1.2times10$ 13 cm−2 in AlN/GaN HEMT with C-doped buffer. These values reveal that current collapse effects are-more pronounced in the C-doped HEMTs than the Fe-doped HEMTs. Thus, this work is an important first step before further improvements in the model for computing buffer trap concentration.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Study of β-Ga2O3-Based Thin-Channel MODFET Devices Using a Coupled
           Drift-Diffusion/Multisubband BTE Solver

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      Authors: Suhyeong Cha;Sung-Min Hong;
      Pages: 4870 - 4876
      Abstract: Gallium-oxide-based modulation-doped field-effect transistors (MODFETs) are theoretically investigated. In order to properly consider the electrical characteristics of the two-dimensional electron gases (2DEGs) in thin-channel devices, a coupled drift-diffusion (DD)/multisubband Boltzmann transport equation (MS-BTE) solver is implemented. Parameters adopted in the simulation are determined by referring to the experimental results of existing long-channel devices. The impact of the channel length, the channel thickness, the ungated region length, and contact resistance on the cutoff frequency is rigorously calculated. It is found that the cutoff frequency can have about 90 GHz with a contact resistance of $0.4~Omega ~cdot $ mm and a channel whose length and thickness are 30 and 5 nm, respectively.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Identification of Traps in p-GaN Gate HEMTs During OFF-State Stress by
           Current Transient Method

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      Authors: Shijie Pan;Shiwei Feng;Xuan Li;Kun Bai;Xiaozhuang Lu;Jiayu Zhu;Yamin Zhang;Lixing Zhou;
      Pages: 4877 - 4882
      Abstract: In this work, the current transient method was conducted for trap analysis in the p-GaN gate high-electron-mobility transistors (HEMTs) in the OFF-state. Based on the traditional detrapping transient measurements, the pure recovery transients can be isolated by subtracting the undetected part caused by the measurement conditions. A comparison of the measured and actual recovery transients under different drain filling voltages was presented. It suggested that this method can be effective to analyze the unregular transient curves and distinguish the charge trapping type preliminarily. In addition, three traps were identified based on the time constant spectra and the hidden absolute amplitudes of traps can be corrected using the differential amplitude spectra. The information of trap levels in the buffer layer and AlGaN barrier layer was revealed, consisting of three electron traps with energy levels of 0.313, 0.265, and 0.467 eV. The identification of the traps may provide a physical foundation for better understanding of the drain-induced trapping effect during the OFF-state in p-GaN HEMTs.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Innovative Structure to Improve Erase Speed in 3-D nand Flash Memory With
           Cell-on-Peri (COP) Applied

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      Authors: Seonjun Choi;Changhwan Choi;Jae Kyeong Jeong;Yun-Heub Song;
      Pages: 4883 - 4888
      Abstract: In this article, we propose silicon-nitride-pillar (SNP) and silicon-pillar (SP) structures that can be applied to a COP structure, which is the mainstay of the recent 3-D nand flash structure, by applying the IGZO-nitride-pillar (INP) and IGZO-pillar (IP) structures that showed very good erase performance announced in previous studies and verify them through device simulation. The proposed structure can supply holes through pillars formed by epitaxial growth in the P+ crystal silicon subregion, which is generally used in the existing semiconductor manufacturing process. As a result of simulation, the proposed structure showed a fast erase speed of 10 $mu text{s}$ , and the SNP structure could prevent breakdown by appropriately controlling the thickness of the silicon nitride barrier. In addition, the SP structure with the silicon nitride barrier removed was able to maintain a fast erase speed even when the thickness of the pillar was reduced to 5 nm. Therefore, it was confirmed that the proposed structure can operate more than 100 times faster than the existing GIDL erasing structure if proper structure and operating conditions are secured.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Integrate-and-Fire Neuron With Li-Based Electrochemical Random Access
           Memory Using Native Linear Current Integration Characteristics

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      Authors: Donguk Lee;Jongwon Lee;Chuljun Lee;Seyoung Kim;Hyunsang Hwang;
      Pages: 4889 - 4893
      Abstract: Neuromorphic computing has gained a considerable research interest due to its potential in realizing highly efficient parallel computations. However, the existing neuromorphic architectures face various drawbacks. In this study, we present an integrate-and-fire (I&F) neuron using a Li-based electrochemical random access memory (Li-ECRAM) to achieve exceptional area efficiency and low-power neuromorphic computing. The proposed Li-ECRAM neuron employs a significantly reduced number of transistors when compared to other novel nonvolatile memory-based I&F neurons due to linear current integration characteristics and a high linear conductance response to the input current. As the integration-type Li-ECRAM is linear, it eliminates the requirement of a nonlinear compensating circuit. Therefore, a Li-ECRAM-based neuron has a simple structure comprising Li-ECRAM, reset transistor, inverter, and pulse generator. Furthermore, we also evaluate the operation speed and energy consumption of the proposed neuron, demonstrating the potential for high-speed and low-power operation. The proposed neuron can be applied in large-scale neuromorphic hardware applications due to the scalability and low energy consumption of Li-ECRAM.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • First Principle Study of Spin Tunneling Current Under Field Effect in
           Magnetic Tunnel Junction for Possible Application in STT-RAM

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      Authors: Manoj Kumar Yadav;Santosh Kumar Gupta;
      Pages: 4894 - 4899
      Abstract: A first principle analysis of Fe/MgO/Fe magnetic tunnel junction (MTJ) having gate voltage over insulated barrier region (MgO) is presented. Because of different work functions of gate and barrier materials, transfer of density of states (DOS) in forbidden energy gap of MgO is found above Fermi energy due to Schottky effect. It is reported that diffused DOS allows high tunneling of majority channel current because of less interference of ${Delta _{{1}}}$ symmetry of Bloch states with evanescent states in barrier. It shows high spin injection efficiency 0.9928, 0.9959, and 0.9871 with tunnel magneto resistance (TMR) ratios 1743.30%, 1450.06%, and 572.62% at gate voltages 1–3 V, respectively, with left and right electrodes at 0.5 V. Present work gives a basis for using MTJs as three terminal devices in magnetic random access memory (MRAM) applications.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Critical Importance of Nonuniform Polarization and Fringe Field Effects
           for Scaled Ferroelectric FinFET Memory

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      Authors: Girish Pahwa;Sayeef Salahuddin;Chenming Hu;
      Pages: 4900 - 4908
      Abstract: The ferroelectric field-effect transistor (FEFET) is an emerging nonvolatile memory technology that can offer ultra-scalability, fast operation, and reduced power consumption. However, a limited understanding of FEFET physics poses challenges for optimum device design. In this article, we provide physical insights into the operation of FinFET-based FEFETs (FEFinFETs) using a phase-field framework built on time-dependent Landau–Ginzburg (TDGL) thermodynamic theory. We exploit the source–drain fringing field to stabilize a monodomain configuration in the OFF state of short channel FEFinFETs. Based on recent experiments, we first analyze the switching dynamics of FEFinFETs with low remnant polarization ( ${P}_{r}$ ) and high coercive field ( ${E}_{c}$ ) hafnium zirconium oxide (HZO) FE. We find that the switching in these FEFinFETs occurs via domain nucleation and growth from the gate metal edges at the source–drain spacers. We also show that a non-zero drain bias can be used for dynamically modulating the memory window (MW) of FEFinFET to lower its power consumption. Furthermore, we find the spacer permittivity to be a crucial design parameter to control the MW and show that a lower spacer permittivity can significantly increase the MW. Finally, we show that the commonly held idea that a large ${P}_{r}$ leads to a large MW is not always valid. For a large ${P}_{r}$ , the formation of multiple domains in the FE layer can lead to a significant reduction in the MW. In addition, these devices can suffer from low write endurance due to exposure of the interfacial oxide layer to high electric fields.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p+/i/n+
           Silicon Nanowire

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      Authors: Sung Hwan Jang;Tae Whan Kim;
      Pages: 4909 - 4913
      Abstract: In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p+/i/n+ nanowire via well-calibrated TCAD simulations. The 4F2-like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (106 at 25 °C and 1-ns read duration) of state “1” to state “0,” and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of ~3 s at 25 °C. The long RT, considering a severe WL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (~3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Coexistence of Nonvolatile WORM, Bipolar, Unipolar, and Volatile Resistive
           

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      Authors: Wun-Ciang Jhang;Chih-Chieh Hsu;
      Pages: 4914 - 4919
      Abstract: In this study, we demonstrate multimemory functions of anAg/SiOx/n+-Si device, including nonvolatile (NV) write-once-read-many-times (WORM), NV bipolar, NV unipolar, and volatile resistive switching (RS) characteristics. The SiOx layer is grown using a dry oxidation process. Different RS features are obtained by modulating the compliance current during device operation. The resistance switch from the OFF to ON state, corresponding to a set process, is observed in the positive voltage region, which indicates that the Ag cations are responsible for the RS process. When the Ag/SiOx/n+-Si memory switches to the ON state, an Ag conductive bridge (CB) in the SiOx layer is indeed observed under transmission electron microscopy (TEM) examination. A CB-based model is used to explain the different RS behaviors of the Ag/SiOx/n+-Si resistive memory.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Hamming Weight Calculation of Binary String in One nMOS Transistor–One
           Ag/HfO2/Black Phosphorus/Pt Memristor

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      Authors: Hui He;Yifei Pei;Jingjuan Wang;Zichang Zhang;Jing Liu;Lei Yan;Ying Zhao;Xiaoyu Li;Yongxin Wei;Jingsheng Chen;Xiaobing Yan;
      Pages: 4920 - 4923
      Abstract: Memristors hold promise for efficient digital computing and information storage due to their nanoscale size and nonvolatile storage capability. However, the randomness of the area formed by the conductive filaments (CFs) causes unstable switching parameters of the memristor. In this study, a new double-layer structure with Ag/HfO2/black phosphorus/Pt was designed on a silicon substrate to improve the performance of the memristor. The results show that the devices have highly stable state switching and concentrated resistance distribution characteristics, better retention capacity, and better endurance. In addition, we designed one transistor–one memristor (1T–1M) structure based on the performance of the memristor and used it to calculate the Hamming weight (HW) of the binary string. The results show that the average error of the current values is only 1.04% and 1.01% for the 4- and 8-bit binary strings, respectively, and that there is an excellent linear fit between the output current and the HWs. The error rate and calculation stability are better than the existing calculation methods. This work provides new ideas in efficient physical computing and applications in areas such as information coding.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Effect of Biaxial Bending Strains on the Electrical Characteristics of
           Flexible Low-Temperature Polysilicon Thin-Film Transistors

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      Authors: Hui Zhu;Zhixuan Fang;Na Xie;Zeng Huang;Zheng Liu;Dong Li;Shiwei Feng;Chunsheng Guo;Yamin Zhang;Lixing Zhou;Bo Liu;
      Pages: 4924 - 4929
      Abstract: The change of electrical properties of flexible low-temperature polysilicon (LTPS) thin-film transistors (TFTs) under biaxial bending strains was studied. Biaxial strains were applied using a ring-on-ring bending test rig. The magnitude of the strain was determined by theoretical calculations and finite-element simulations. With an increase in strain, the transfer curve shifted to a negative bias. At a biaxial strain level of 12%, the threshold voltage decreased by 27%, the field-effect mobility decreased by 13%, and the subthreshold slope increased by 25%. It had a more significant effect on the property changes than the uniaxial strain; this difference may be attributed to additional trap states generated by the biaxial strain. The analysis showed that the trap density increased when the strain level increased. The contributions of the increases in the grain-boundary trap state density and the interface trap state density to the degradation in the electrical properties were derived to be 10% and 90%, respectively. After removal of the biaxial bending strains, the electrical performance showed recovery behavior, but the performance could not return fully to its original state.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • AC Performance of Flexible Transparent InGaZnO Thin-Film Transistors and
           Circuits

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      Authors: Federica Catania;Mukhtar Ahmad;Dianne Corsino;Niloofar Saeedzadeh Khaanghah;Luisa Petti;Niko Münzenrieder;Giuseppe Cantarella;
      Pages: 4930 - 4935
      Abstract: Transparent transistors are mainly investigated in view of their integration in displays and their employment in wearable electronics where the integration of flexible and imperceptible systems is an important requirement. Here, the fabrication and ac performance of flexible InGaZnO thin-film transistors (TFTs) and circuits are presented to evaluate their suitability for analog sensor conditioning applications. Functional oxides are employed to guarantee the transparency of the device, while their fabrication processes are suitable to directly realize electronics on a flexible polyimide substrate. The TFTs show state-of-the-art performance with a field-effect mobility $mu _{text {eff}},,= {19}.{39},, text {cm}^{{2}} text {V}^{-1} text {s}^{-1}$ and functionality while bent to radii as low as 5 mm. Reliable scattering parameters measurements confirm transit frequencies as high as $f_{t}~approx ~7.84$ MHz. Simultaneously, nMOS ring oscillators (ROs) show functionality at supply voltage ${V} _{text {DD}}$ ranging from 1.75 to 12.25 V with a maximum oscillation frequency ${f} _{text {osc}},,=132.9$ kHz. Finally, common-source amplifiers (CSAs) exhibit the voltage gains up to 10.7 dB, the cutoff frequencies up to 10.8 kHz, and a power consumption down to $4.4~mu text{W}$ .
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Improved Modulation Bandwidth of Blue Mini-LEDs by Atomic-Layer Deposition
           Sidewall Passivation

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      Authors: Shou-Qiang Lai;Ting-Wei Lu;Su-Hui Lin;Yi Lin;Guo-Chun Lin;Jian-Hua Pan;Yue-Long Zhuang;Yi-Jun Lu;Yue Lin;Hao-Chung Kuo;Zhong Chen;Ting-Zhu Wu;
      Pages: 4936 - 4943
      Abstract: By adopting atomic layer deposition (ALD) sidewall passivation, the electroluminescence (EL) and communication performances of mini-light emitting diodes (mini-LEDs) of different sizes were improved. In particular, the most significant improvement in the electroluminescence properties of the external quantum efficiency (EQE) (a 7.2% increase), leakage current, and the communication properties of the modulation bandwidth (a 20% increase) transmission rate and bit error rate (BER) was found in the smallest mini-LEDs (80 $mu text{m},,times $ 120 $mu text{m}$ ). According to the results of time-resolved photoluminescence (TRPL) measurements, the carrier lifetime of the samples can be affected by both the size and ALD sidewall passivation. In addition, the effects of ALD sidewall passivation for visible-light communication (VLC) were demonstrated.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Material Defects and Dark Currents in InGaAs/InP Avalanche Photodiode
           Devices

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      Authors: Zilu Guo;Wenjuan Wang;Yangjun Li;Huidan Qu;Liuyan Fan;Xiren Chen;Yicheng Zhu;Yue Gu;Yajie Wang;Changlin Zheng;Pingping Chen;Wei Lu;
      Pages: 4944 - 4949
      Abstract: An In0.53Ga0.47As/indium phosphide (InP) avalanche photodiode (APD) with a separate absorption, grading, charge, and multiplication (SAGCM) structure is epitaxially grown by molecular beam epitaxy (MBE). The resulting material is studied using X-ray diffraction (XRD), photoluminescence (PL), and scanning transmission electron microscopy. The activation energy extracted from the dark current of the APD indicates that it is dominated by the generation–recombination (G–R) process. Deep low-temperature PL peaks reveal the existence of an ${E}_{v} + 0.42$ -eV deep energy level defect in the indium–gallium–arsenide (InGaAs) absorber layer, which is considered to be a result of point defects caused by Ga-poor or In-poor MBE growth conditions. The effect of the defect on the dark current is confirmed using numerical calculation methods.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • LTPS Pixel Driving Scheme to Improve Motion Blur for AMOLED Displays

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      Authors: Jung-Min Lee;Chang H. Kang;Juhn S. Yoo;Han W. Hwang;Soon K. Hong;Yong M. Ha;Hyean C. Choi;Byeong-Kwon Ju;
      Pages: 4950 - 4957
      Abstract: This article proposes a new driving scheme based on an n-type low-temperature polycrystalline silicon (LTPS) four-transistor-two-capacitor (4T2C) pixel circuit to improve the quality of motion images of active matrix organic light-emitting diode (AMOLED) displays. The proposed driving scheme can prevent the effect of the lateral leakage current flowing through the OLED common layer by keeping the pixels in the upper and lower row lines in a nonemitting hold period during the program period. The simulation results show that all RGB colors maintain a shooting amount ratio (SAR) below 1% from the first frame when the image is switched from black to white, even for a concentration of the high p-doped hole transport layer (p-HTL). In addition, the parasitic capacitances of the 4T2C pixel circuit that causes OLED current errors are thoroughly analyzed for high luminance uniformity. A 1.5-in 326 pixels per inch (PPI) AMOLED panel based on the proposed driving scheme was fabricated. The results of our measurements show that the SARs of RGB colors are 0.8%, 0.2%, and 0.9%, respectively, and the average ${x}$ -coordinate shift of the color is 0.007 during the transition between black and white images due to the effective suppression of the lateral leakage current. Therefore, we demonstrate that the proposed driving scheme is suitable for AMOLED displays that require high-quality motion images.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Study on Residual Image in Low-Temperature Poly-Si Oxide TFT-Based OLED
           Display on Polyimide Substrate

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      Authors: Chang Hoon Jeon;Kyung Joon Kwon;Soon Kwang Hong;Yong Min Ha;Hyunho Kim;Jin Jang;
      Pages: 4958 - 4961
      Abstract: We study the reduction in residual image in low-temperature poly-Si oxide (LTPO) thin-film transistor (TFT)-based flexible organic light-emitting diode (OLED) displays on polyimide (PI) substrate. Conventional voltage compensation circuit (seven TFTs plus one capacitor) is used with modification of driving and some switching TFTs. The measurement results on the threshold-voltage ( ${V}_{text{TH}}$ ) shift and SPICE simulation data on the pixel circuits indicate that the residual image is due to the PI charging effect when a single-gate coplanar poly-Si TFT is used as driving one. It is shown here that adding a bottom electrode to the coplanar poly-Si driving TFT (D-TFT) eliminates the residual image by shielding the poly-Si active layer from the PI charging effect.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Dark Current and Gain Modeling of Mid-Wave and Short-Wave Infrared
           Compositionally Graded HgCdTe Avalanche Photodiodes

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      Authors: Mike Zhu;Ilya Prighozhin;Pradip Mitra;Richard Scritchfield;Chris Schaake;Joanna Martin;Jin Hwan Park;Fikri Aqariden;Enrico Bellotti;
      Pages: 4962 - 4969
      Abstract: We present a detailed methodology for drift-diffusion (DD) modeling of gain and dark currents in mid-wave infrared (MWIR) and short-wave infrared (SWIR) ${mathrm {Hg}}_{{1}-{x}}$ CdxTe p-around-n avalanche photodiodes (APDs) based on a comprehensive analysis of experimentally obtained data from three different sets of devices. These devices are fabricated on homogeneous and compositionally-graded films with cadmium composition ranging from ${x},,=0.37$ to 0.45, each with differing geometrical dimensions, and tested at operating temperatures ranging from 140 to 240 K. The temperature, composition, and electric-field dependent impact ionization (ImI) coefficients are calibrated first according to the given experimental gain data. The gain-normalized dark current (GNDC) curve, along with the presumption of electron-only multiplication, is then used to thoroughly understand and model the behavior of diffusion and generation currents. At high biases, the GNDC curve reveals contributions from tunneling, which are classified as either trap-assisted or band-to-band based on their temperature dependence. The tunneling mechanisms are modeled accordingly: trap-assisted tunneling (TAT) is scaled inversely with Shockley–Read–Hall (SRH) lifetime, while band-to-band tunneling (BTBT) is scaled with bandgap, effective mass, and an additional empirical temperature term. Finally, the comprehensive model is applied to all three experimental devices across the operating temperature range with good agreement.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Junction Engineering-Based Modeling and Optimization of Deep Junction
           Silicon Single-Photon Avalanche Diodes for Device Scaling

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      Authors: Haewon Lee;Hyejeong Choi;Ilgu Yun;
      Pages: 4970 - 4975
      Abstract: A silicon single-photon avalanche diode (Si-SPAD) with a deep multiplication zone was fabricated using 0.11- $mu text{m}$ -CMOS technology. Deep n-well (DNW) implantation with three energy levels was performed to prepare a deep junction, and the highest breakdown voltage ( ${V}_{text {BR}}$ ) and lowest dark count rate (DCR) were obtained at the highest DNW implantation energy. In addition, devices with different structures were manufactured: a shallow junction, deep junction with mask DNW, deep junction with mask DNW without shallow trench isolation (STI), and deep junction with blank DNW. The blank DNW structure exhibited a lower edge breakdown risk and less deviation between samples compared to those of mask DNW structure in terms of the ${V}_{text {BR}}$ and DCR. Moreover, a new edge breakdown risk was observed between DNW and p-well (PW) in the DNW blank structure, which could be alleviated by adjusting the PW sizes. According to the measurement results, the STI structure was preferable in terms of fill factor. Measurements were obtained from real fabricated test device structures, and technology computer-aided design (TCAD) for various factors associated with Si-SPADs with deep multiplication structures was performed.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Floating Source/Drain Enabled Linear–Linear–Logarithmic Self-Adaptive
           One-Transistor Active Pixel Sensor

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      Authors: J. Liu;Xue-Jiao Wang;Yu-Long Jiang;J. Wan;
      Pages: 4976 - 4980
      Abstract: In this work, a novel one-transistor active pixel sensor (1T-APS) with adjustable self-adaptive sensitivity enabled by floating source/drain (S/D) is demonstrated on 22-nm fully depleted Si-on-insulator (FD-SOI) platform. Additional control gates (CGs) with floating S/Ds are incorporated into the sensor, which are parallel to the sensing gate (SG). For weak illumination, the CG channel keeps closed so that the photoresponse is only active for SG controlled region, resulting in high linear sensitivity, while the CG channel will automatically turn on when the illumination is strong enough. Correspondingly, the CG controlled region is connected with SG controlled region for photoresponse together, resulting in a relatively lower linear sensitivity. For very strong illumination, the 1T-APS will automatically switch to logarithmic response mode due to the activated virtual photodiode in the FD-SOI substrate. The sensitivity transition points in the linear–linear region and the linear–logarithmic region can be further adjusted by the bias of CG and back gate, respectively. The adjustable self-adaptive sensitivity indicates the great potential of the proposed 1T-APS for high-quality image sensing.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Luminescence-Tunable High-Power White Light-Emitting Diodes Through
           Dam-Adjusted Ceramic Substrate

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      Authors: Zhe Wang;Yongtong Wang;Qing Wang;Jinglong Liu;Yun Mou;Yang Peng;Mingxiang Chen;
      Pages: 4981 - 4986
      Abstract: In this work, luminescence-tunable high-power white light-emitting diodes (WLEDs) were fabricated by printing phosphor-in-silicone on 3-D ceramic substrates with adjusted dam structure. The 3-D ceramic substrate was prepared by a simple and efficient magnetic field-oriented grouting method in which silicate ceramic dam with adjusted height and angle was reliably bonded on a planar direct plating ceramic (DPC) substrate. The phosphor concentration of WLEDs was optimized to realize white light. At the phosphor concentration of 12 wt%, the packaged WLEDs achieve cool white light and high optical consistency. The influence of dam height and angle on the optothermal performances of WLEDs was investigated. As the dam height increases from 0.5 to 1.0 mm, the luminous efficiency (LE) of WLEDs first increases and then decreases, and the correlated color temperature (CCT) gradually decreases. At the dam height of 0.7 mm, the WLED achieves a high LE of 122 lm/W and a suitable CCT of 5008 K. Furthermore, the LE increases from 122 to 132 lm/W and the CCT decreases from 5006 to 4458 K when the dam angle changes from 0° to 40°. Importantly, the dam height and angle have no obvious influence on the surface temperature of WLEDs, and the WLEDs still display a low surface temperature even at high input current due to the effective heat dissipation of dam structure. The results indicate that the fabricated WLEDs achieve the tunable luminescence and low working temperature, which can be treated as an efficient and reliable high-power white source.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • High-Quality White Laser Diode Fabricated by Laser-Driven Tricolor PiG
           Film-on-Sapphire

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      Authors: Feng Xie;Wei Zeng;Zhijia Hu;Guofeng Yang;Benli Yu;
      Pages: 4987 - 4991
      Abstract: Phosphor-converted white laser diode (WLD) is considered as a promising light source in next-generation high-brightness lighting. However, the WLD suffers from low optical quality in luminous efficacy and color rendering. In this work, we fabricated a high-quality WLD by a blue laser-driven a tricolor phosphor-in-glass (PiG) film-on-sapphire (PIGS). The tricolor PiGS was prepared by sintering a green/yellow/red phosphor glass film on a sapphire substrate. The optical quality of tricolor PiGS-WLDs were optimized by adjusting the phosphor ratio. At the phosphor ratio of 9:6:1, the PiGS-WLD achieves high optical quality with a luminous flux of 362.1 lm, a color rendering index (CRI) of 80.3, and a correlated color temperature (CCT) of 4590 K at a laser power of 2.4 W. The PiGS-WLD has the highest luminous efficacy of 154.5 lm/W at 3.15 W. Furthermore, the PiGS-WLD displays excellent color stability with small CCT and CRI deviation under various laser powers and continuous excitation. The surface temperature of PiGS-WLD is stable at 104 °C due to the high thermal conductivity of sapphire substrate. Therefore, this study provides a stable and high-quality laser-driven white light source for high-brightness lighting and display.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Extrinsic Parasitics and Design Considerations on Modulation Bandwidth of
           850-nm Vertical Cavity Surface Emitting Lasers

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      Authors: Guanzhong Pan;Yun Sun;Meng Xun;Zhuangzhuang Zhao;Jingtao Zhou;Wenjing Jiang;Runze Zhang;Weichao Wu;Dexin Wu;
      Pages: 4992 - 4997
      Abstract: The extrinsic parasitics generally limit the modulation bandwidth of vertical cavity surface emitting lasers (VCSELs) for optical data links and interconnects. In this article, the extrinsic parasitics of 850-nm VCSELs are investigated by three different designs: oxide-only (design A), oxide-implant (design B), and oxide-implant with benzocyclobutene (BCB) (design C). The static and dynamic characteristics of all the designs with~7- $mu text{m}$ aperture are measured and compared. The maximum modulation bandwidth of design A is only about 12 GHz mainly limited by the large parasitic capacitances. With a proper proton implantation, a thick nonconducting layer is created inside the device with design B, which dramatically reduces the parasitic capacitances, and thus the bandwidth is increased to about 18 GHz. Based on design B, a 4- $mu text{m}$ -thick BCB layer with low dielectric constant is employed underneath the bond pad of design C to further reduce the pad capacitance, leading to the highest bandwidth about 24 GHz and the highest modulation current efficiency factor (MCEF) of 10.8 GHz/mA1/2. The microwave reflection coefficient ( ${S}_{{11}}$ ) parameters of the three designs are measured and compared. Results indicate that design C has the lowest parasitic capacitances and the highest modulation bandwidth, which is preferred for high-speed VCSELs to obtain good static and dynamic performance.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Optimization of the Anti-Solvent Method for the Fabrication of Cu
           Electrode-Based High-Efficiency Perovskite Solar Cell

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      Authors: Naba K. Rana;Arun Kumar;Manas Ranjan Samantaray;Nikhil Chander;Dhriti S. Ghosh;
      Pages: 4998 - 5003
      Abstract: Organic–inorganic lead halide perovskite is promising photovoltaic energy harvesting material to fabricate high-efficiency solar cells. To enhance the power conversion efficiency (PCE) and stability of the fabricated device, a high-quality, pinhole-free, and larger grain size perovskite film is essential. Anti-solvent-assisted crystallization is a popular technique to deposit perovskite thin film. With the help of this technique, perovskite layer can be deposited with smooth surface morphology, low surface defect density, and excellent carrier transport. However, choosing a proper anti-solvent is essential for highly efficient perovskite solar cells (PvSCs). Here, we qualitatively evaluate the impacts of different anti-solvent on methylammonium lead iodide (MAPbI3) perovskite film. We used chlorobenzene (CB), diethyl ether (Eth), toluene (TL), and isopropyl alcohol (IPA) as an anti-solvent. Our result demonstrates that the anti-solvent with a relatively higher boiling point and lower polarity contributes to superior efficiency, low hysteresis, and better reproducibility of MAPbI3 active layer-based PvSCs. The device fabricated with CB anti-solvent exhibits the best PCE of 8.16% with a Cu-based electrode. This work provides a promising approach to controlling the growth and morphology of perovskite films and paves the way for further optimizing the fabrication process of large-area low-cost electrode-based high-efficiency devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Increasing the Photovoltaic Performance of Dye-Sensitized Solar Cells by
           Zinc Oxide Film as a Recombination Blocking Layer

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      Authors: Jung-Chuan Chou;Ruei-Hong Syu;Po-Hui Yang;Po-Yu Kuo;Yu-Hsun Nien;Chih-Hsien Lai;Po-Feng Chen;Yi-Ting Wu;Shang-Wen Zhuang;
      Pages: 5004 - 5011
      Abstract: Dye-sensitized solar cells (DSSCs) have great potential in solar power generation due to their advantages of easy fabrication and low fabrication cost. One of the main problems of DSSCs is the loss of recombination between the fluorine-doped tin oxide (FTO) substrate/electrolyte. This is mainly due to the mesoporous nature of the TiO2 film. The recombination effect can be reduced by introducing compact layers (CLs) on the photosensitive layer to prevent the direct contact between the transparent conductive oxide substrate and the redox electrolyte. When compared with TiO2, zinc oxide (ZnO) tends to have more negative conduction band edges. This helps to prevent, electronic recombination reactions and so improves the open-circuit voltage ( ${V}_{{text {OC}}}$ ). ZnO blocking layers (ZBLs) were deposited on the FTO substrate by RF sputtering and used for DSSCs. We employed a field emission scanning electron microscope (FE-SEM) and X-ray diffraction (XRD) to characterize ZBL. Photovoltaic (PV) parameters were measured on the DSSCs samples fabricated in this study under solar simulator illumination at AM 1.5 (100 mW/cm2). Compared with the DSSCs without ZBL, DSSCs with ZBL (31 nm) exhibit higher short-circuit current density ( ${J}_{{text {SC}}}$ ) and photovoltaic conversion efficiency (PCE), which is 21.82% higher than that of the DSSCs without ZBL.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Comparative Analysis and Performance Optimization of Low-Cost
           Solution-Processed Hybrid Perovskite-Based Solar Cells With Different
           Organic HTLs

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      Authors: Deepak Kumar Jarwal;Chandani Dubey;Kamalaksha Baral;Anuradha Bera;Gopal Rawat;
      Pages: 5012 - 5020
      Abstract: In this work, we have investigated perovskite-based solar cells (PSCs) with seven different organic hole transport layers (HTLs), which include spiro-2,2’,7,7’-Tetr-akis-(N, N-di-4-methoxyphenylamino) -9,9’-spirobifluorene (OMeTAD), poly(triaryl amine) (PTAA), poly (3,3”’-dialkyl-quaterthiophene) (PQT), poly (3, 4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), poly (3-hexylthioph-ene-2,5-diyl) (P3HT), Poly 2-methoxy-5-(2’-ethylhexyloxy)-1,4-phenylene vinylene (MEH-PPV), and n-Propyl Bromide (nPB). This article reports the impact of several device parameters, such as perovskite layer defect density, and thickness, on the solar cell performance. We examined the device performance for the PSC device architecture, i.e., fluorine-doped tin oxide (FTO)/TiO $_{text{2}}$ /CH $_{text{3}}$ NH $_{text{3}}$ PbI $_{text{3}}$ /HTLs/Au. For this study, numerical simulation has been performed and optimized for optimum absorber layer thickness and defect density. In this study, we report the power conversion efficiency (PCE) with various HTLs, such as 10.01% for MEH-PPV, 13.94% for PEDOT:PSS, 14.75% for P3HT, 15.42% for PQT, 15.74% for NPB, 17.08% for PTAA, and 17.11% for spiro-OMeTAD at an optimized thickness of 300 nm. It is asserted that there is an enhancement in the photovoltaic performance observed while using spiro-OMeTAD and PTAA as HTL. PSC using spiro-OMeTAD as HTL shows exceptional performance compared to other HTLs. Other parameters obtained for PSC using spiro-OMeTAD are $textit{V}_{text{OC}}$ of 1.10 V, $textit{J}_{text{SC}}$ of 20.772 mA/cm $^{text{2}}$ , FF of 0.74%, and PCE of 17.11%. The elicited simulation results suggest that spiro-OMeTAD is the most promising candidate for HTL to fabricate low-cost, highly efficient, and low-temperature processed hybrid PSC.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • New Concepts in All-Metal-Oxide-Based Ultraviolet Transparent
           Photovoltaics

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      Authors: Sadanand;Malkeshkumar Patel;Naveen Kumar;Woochan Lee;Joondong Kim;
      Pages: 5021 - 5027
      Abstract: The performance of photovoltaic systems is mostly determined by the materials used in their construction, regardless of the kind of application. We report on transparent broadband photodetectors based on p-Co3O4 and a heterojunction of n-ZnO, n-TiO2, or n-SnO2 that fits the needs of transparent optoelectronic devices. The heterojunction devices are fabricated by sputtering method. The energy band alignments are investigated with the aim of developing an efficient photodetector. The average transmittance values in the visible light range (400–800 nm) for TiO2, ZnO, and SnO2 are observed to be approximately 80%, 74%, and 66%, respectively. The current–voltage characteristics of the devices are also investigated and non-Ohmic characteristics are observed. Furthermore, a photovoltage study with post-rapid thermal processing (RTP) is carried out. It is found that enhancing the carrier lifetime is an efficient way to improve the performance of the devices. With an increased minority carrier lifetime, the transient photovoltage of the RTP-treated TiO2/Co3O4 device shows slow decay.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Vertical SiC Photoconductive Switch With Axial Optical Internal Reflection
           Trap

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      Authors: Langning Wang;Xu Chu;Muyu Yi;Jinmei Yao;Tao Xun;Hanwu Yang;
      Pages: 5028 - 5034
      Abstract: The SiC vertical photoconductive switch with an axial optical internal reflection trap to improve the ON-state performance is presented. The extrinsic light absorption of vanadium (V)-doped SiC photoconductive switch is low. As such an axial optical reflection trap is used to increase the optical path and total optical absorption. The trap consists of a convex lens, a silver mirror electrode with a hole, and a transparent electrode to create a quasi-total internal reflection structure. Simulation and experimental evaluation reveal that both the device’s light absorption and output current have been improved significantly. Compared with regular axial illumination without the reflective trapping arrangement, the structure fabricated on a V-doped 4H-SiC device demonstrates a $2.5times $ improvement in photoelectric conversion responsivity.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • On-Substrate Grown MAPbBr3 Single Crystal Diodes for Large-Area and
           Low-Dark-Current X-Ray Detection

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      Authors: Xu Yangbing;Yuqing Luo;Yicong Pang;Bin Wen;Chaohua Dai;Tian Chen;Jiangsheng Xie;Lun Cai;Zhiya Dang;Pingqi Gao;
      Pages: 5035 - 5040
      Abstract: Lead-based organic–inorganic hybrid perovskite single crystals (OIHP SCs) offer promising opportunity for X-ray detection and imaging owing to their high X-ray attenuation coefficient, excellent optoelectronic properties, and simple fabrication processes. Nevertheless, it remains a key challenge to reduce its dark current and meanwhile maintain a high sensitivity. Herein, we developed an on-substrate method for growing methylamine lead bromide (MAPbBr3) SCs on aluminum oxide (Al2O3) layer coated indium tin oxide (ITO) glass. The photodiode based on this approach exhibits an ultralow-dark-current density of 1 nA cm−2 at an operative voltage of −5 V, a signal-to-noise ratio (SNR) more than 80 dB, and meanwhile retaining a high X-ray sensitivity of 2.02 $times 10^{{3}},, mu text{C}cdot $ ${mathrm {Gy}}_{text {air}}^{-1} cdot $ cm−2. Our further investigation reveals that the dark current was reduced due to two beneficial effects of the Al2O3 layer in tandem, including the interfacial defect passivation and blocking of hole injection by increased interfacial energy barrier. Our approach sheds light on advancing the fabrication of high-performance OIHP SCs-based X-ray sensors that can be potentially integrated with large-area readout panel at low temperature.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Wide Spectral Response Single Photon Avalanche Diode for
           Backside-Illumination in 55-nm CMOS Process

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      Authors: Yang Liu;Maliang Liu;Rui Ma;Jin Hu;Dong Li;Xiayu Wang;Zhangming Zhu;
      Pages: 5041 - 5047
      Abstract: This article presents a wide-spectral response single photon avalanche diode (SPAD) designed and fabricated in advanced 55-nm CMOS image sensor technology. SPADs with different active areas and doping profiles are simulated by Sentaurus-TCAD to optimize their electrical and optical performances. A global well-sharing technique is employed to deliver a pixel pitch of $16.4 ~mu text{m}$ and a fill factor of 50.96% for a device with a $6 ~mu text{m}$ radius. The proposed structure is based on a p+/deep n-well (DNW) multiplication junction, extending its spectral response as much as possible. Compared to the existing BSI SPADs, a triple protection method is innovatively used to suppress premature edge breakdown and to reduce the dark count rate (DCR) through a combination of a virtual retrograde DNW, p-well guard ring, and a poly gate ring located above the shallow trench isolation. Furthermore, deep trench isolation is employed to suppress crosstalk. Samples of different radii from 2 to $6 ~mu text{m}$ are manufactured. The SPADs exhibit a low DCR below 20 cps/ $mu text{m}$ 2 at room temperature and with a 2-V excess bias. The peak photon detection probability is 20.3% at 660 nm and is maintained at a high value, more than 10%, in the spectral range of 550–820 nm.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Experimental Investigation on Threshold Voltage Instability for β-Ga2O3
           MOSFET Under Electrical and Thermal Stress

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      Authors: Zhuolin Jiang;Yuxi Wei;Yuanjie Lv;Jie Wei;Yuangang Wang;Juan Lu;Hongyu Liu;Zhihong Feng;Hong Zhou;Jincheng Zhang;Guangwei Xu;Shibing Long;Xiaorong Luo;
      Pages: 5048 - 5054
      Abstract: A $beta $ -Ga2O3 MOSFET is fabricated and its threshold voltage $({V}_{mathrm{TH}})$ instability mechanisms are experimentally investigated under different gate-biased voltages and ambient temperatures. Under the condition of the positive bias stress (PBS) of ${V}_{mathrm{GS}} = 4$ V for 1000 s at room temperature, the ${V}_{mathrm{TH}}$ positive shift of 0.61 V is mainly caused by the electrons trapped by border traps in Al2O3. Combining the hysteresis with temperature-dependent performance analysis, the clockwise to anticlockwise hysteresis inversion at 125 °C is discovered in $beta $ -Ga2O3 MOSFET for the first time, which is probably caused by the activation of deep-level acceptor-type interface states. The deep-level acceptor-type interface states with a fitting activation energy of 114 meV are found, and they also affect the ${V}_{mathrm{TH}}$ instability at high temperature. With the stress of ${V}_{mathrm{GS}} =4$ V at 125 °C for 1000 s, ${V}_{mathrm{TH}}$ is increased by 0.9 V. Analyzing electrical parameters, such as ${V}_{mathrm{TH}}$ , subthreshold slope (SS), and hysteresis width, can distinguish the quantitative contributions of interface states and border traps to -tex-math notation="LaTeX">${V}_{mathrm{TH}}$ instability under electrical stress and thermal stress (TS). This work reveals an important indication for investigating the ${V}_{mathrm{TH}}$ instability of $beta $ -Ga2O3 MOSFET in high-power applications.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Bulk Field Effect Diode

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      Authors: Iraj Sheikhian;
      Pages: 5055 - 5058
      Abstract: The field effect diode (FED) is an attractive device to use in various digital and analog applications, but all previously proposed FEDs are based on the silicon-on-insulator (SOI) technology. In this article, a bulk version of FED (BFED) is proposed for the first time. Both SOI-FED and BFED are simulated using TCAD tools as a semiconductor drift-diffusion solver. The proposed bulk FED can operate as well as a regular SOI-FED. Most sensitive parameters in the design of the BFED are doping and thickness of $text{p}^{+}$ -drain and $text{n}^{+}$ -source. The effect of these parameters is investigated on the output characteristics of the BFED.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Deciphering the Effect of Corrugated p-Base on Reverse Blocking IGCT

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      Authors: Chunpin Ren;Jiapeng Liu;Jinpeng Wu;Biao Zhao;Zhanqing Yu;Fengying Wang;Weifeng Ji;Meng Li;Rong Zeng;
      Pages: 5059 - 5067
      Abstract: The corrugated p-base (CB) structure has been acknowledged as an effective method to improve the maximum controllable current (MCC) of asymmetric integrated gate-commutated thyristor (IGCT), but never clarified in symmetrical devices such as reverse blocking IGCT (RB-IGCT). This study focuses on the influence of the CB structure on the MCC and the failure mechanism of RB-IGCT. First of all, by employing the CB structure in the RB-IGCT samples, it is verified that the CB structure can improve MCC of the symmetrical devices by more than 50%, no matter under high or low dc-link voltages. Moreover, regarding the scenario under the high dc-link voltage, the effect of the CB structure on the dynamic avalanche is analyzed via simulation, and the improvement of MCC and the positive trend of MCC upon temperature are further clarified. As to the scenario under the low dc-link voltage, distinct failure phenomenon and negative temperature dependence of MCC are observed evidentially on the symmetric devices with CB structure. To explain these failure characteristics that are conflicting with the well-acknowledged dynamic avalanche failure, a novel failure mode named cathode retrigger failure is proposed in this study. It is believed that this study not only deciphers the fundamental mechanisms of the CB structure in RB-IGCT, but also provides practical strategy to optimize the symmetric IGCT devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • AC-Stress Degradation and Its Anneal in SiC MOSFETs

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      Authors: Daniel B. Habersat;Aivars J. Lelis;
      Pages: 5068 - 5073
      Abstract: Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve
           Multifold Transient Frequency Enhancement

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      Authors: Shreeniwas Daulatabad;Peeyusha Saurabha Swain;Harald Gossner;Maryam Shojaei Baghini;
      Pages: 5074 - 5081
      Abstract: Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device’s RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • High-Performance GaN Vertical Schottky Barrier Diode With Self-Alignment
           Trench Structure

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      Authors: Jiang Liu;Chuanyu Han;Mingchao Yang;Weihua Liu;Li Geng;Yue Hao;
      Pages: 5082 - 5087
      Abstract: In this work, high-performance GaN vertical Schottky barrier diodes (SBDs) are successfully fabricated on the GaN-on-GaN substrate by using the self-alignment trench structure and argon (Ar) ion implantation. The fabricated diodes achieve a high current ON/ OFF ratio of 108 and high breakdown voltage (BV) of 656 V due to the reduced surface electric field effect. Besides, the temperature-dependent reverse leakage characteristics show that two Poole–Frenkel emission (PFE) processes dominate the carrier transport. This work shows great potential of the self-alignment trench structure in fabricating GaN vertical SBDs to improve the BV with simply fabrication process.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Simulation Aided Hardening of Power Diodes to Prevent Single Event Burnout

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      Authors: Xinfang Liao;Yintang Yang;Yi Liu;Changqing Xu;
      Pages: 5088 - 5095
      Abstract: This article presents the coupled electrothermal simulation results of single event burnout (SEB) in power diode with field limiting rings termination structure. Two different hardening techniques of low carrier lifetime control and introducing the buffer layer are investigated comparatively in both the radiation tolerance improvement and the electrical performance degradation. Our simulations reveal that a significant reduction in the carrier lifetime is needed for the hardening of the power diode using only the carrier lifetime control method. However, the sharp increases in the forward voltage drop and the leakage current at the lower carrier lifetime make this hardening technique unacceptable. On the contrary, the addition of the buffer layer is able to improve the safe operating area under the heavy ion irradiation even up to the breakdown voltage, while the breakdown characteristics and the leakage current are kept unchanged and the increases in the forward voltage drop and the reverse recovery charge can be well controlled. In conclusion, adding a buffer layer is considered a superior and promising hardening technique.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Simple Edge Termination Design for Vertical GaN P-N Diodes

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      Authors: Prakash Pandey;Tolen M. Nelson;William M. Collings;Michael R. Hontz;Daniel G. Georgiev;Andrew D. Koehler;Travis J. Anderson;James C. Gallagher;Geoffrey M. Foster;Alan Jacobs;Mona A. Ebrish;Brendan P. Gunning;Robert J. Kaplar;Karl D. Hobart;Raghav Khanna;
      Pages: 5096 - 5103
      Abstract: Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped ${p} +!+$ contact layer. A TCAD model of the device is developed, and removal of the portions of ${p}$ ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the ${p}$ ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Novel 4H-SiC JBS-Integrated MOSFET With Self-Pinching Structure for
           Improved Short-Circuit Capability

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      Authors: Hengyu Yu;Jun Wang;Gaoqiang Deng;Shiwei Liang;Hangzhi Liu;Z. John Shen;
      Pages: 5104 - 5109
      Abstract: Monolithic integration of junction barrier-controlled Schottky (JBS) diode with SiC MOSFET (termed JMOS) offers unique advantages. However, the short-circuit (SC) ruggedness issue stands in the way of the development of the conventional JMOS. The purpose of this numerical study is to investigate a new 4H-SiC JMOS with a self-pinching (SP) structure formed in the JFET region (termed SP-JMOS). The SP structure features that an N-type current spread layer is sandwiched between the P+ layer and the buried P-shield layer, forming a lateral JFET channel. In the forward conduction state, the lateral JFET channel self-pinches off and clamps the potential, thus limiting the saturation current of the device. In the blocking state, both the P+ layer and the buried P-shield layer collaboratively shield the Schottky contact and the SiC/SiO2 interface from a high electric field for long-term reliable operation. Numerical simulation results show that the proposed SP-JMOS not only withstands a roughly $2.6times $ longer SC withstanding time than that of the conventional JMOS, but also shows an ultralow oxide electric field in the SP-JMOS.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Resistivity Scaling in Epitaxial CuAl2(001) Layers

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      Authors: Minghua Zhang;Daniel Gall;
      Pages: 5110 - 5115
      Abstract: Epitaxial CuAl2(001) layers with thickness ${d}$ = 10.2–141 nm are deposited by co-sputtering onto MgO(001) substrates at 300 °C and their resistivity $rho $ is measured in situ to quantify the CuAl2 resistivity scaling. A combination of X-ray diffraction $theta $ - $2theta $ scans, $omega $ rocking curves, and $varphi $ -scans confirms the single-crystal microstructure with a 45°-rotated epitaxy with CuAl2(001) $vert vert $ MgO(001) and CuAl2(100) $vert vert $ MgO(110). The measured $rho $ increases with decreasing ${d}$ , which is well described by the Fuchs–Sondheimer model, yielding a room-temperature electron mean free path $lambda $ = 15.6 nm with a bulk resistivity $rho _{o}$ = $7.7 ~mu Omega cdot cm$ . The latter value is 18% above the previously reported $rho _{o-$ , which is attributed to electron scattering at Al vacancies with a concentration of 6.4% per site, as quantified by Rutherford backscattering and X-ray reflectivity. Transport measurements at 77 K confirm that $rho _{o}lambda $ = (12 ± 1) $times 10^{-16} Omega text{m}$ 2 is temperature-independent. This value is 79% larger than for Cu, indicating a more pronounced resistivity size effect in CuAl2. Thus, CuAl2 is promising only as Cu-replacement interconnect metal if its low melting point facilitates large grains and its high cohesive energy provides reliability benefits and an associated reduction in liner thickness.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Embedded Magnetic Solenoid Inductor Into Organic Packaging Substrate Using
           Lithographic Via Technology for Power Supply Module Integration

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      Authors: Weihao Zhang;Guoyun Zhou;Qi Gao;Wei Jia;Xianming Chen;Benxia Huang;Lei Feng;Wei He;Chong Wang;Yongkang Zhu;
      Pages: 5116 - 5122
      Abstract: In this article, an embedded magnetic solenoid inductor into an organic packaging substrate is implemented based on lithographically defined vias with a semiadditive process flow. In this solenoid inductor, the solid vertical interconnects and magnetic composite core are simultaneously utilized, both significantly reducing dc resistance and boosting inductance per unit area. A small-signal electrical test of the microinductor shows greatly improved performance including a flat dc inductance of 41.9 nH, low dc resistance of 60 $text{m}Omega $ , a peak quality of 42.7 at 92.8 MHz, and a high 10% saturation current of 3.81 A with a footprint area of 5.7 mm2. Consequently, the microinductor fabricated achieves a high inductance to resistance ratio of 0.7 nH/ $text{m}Omega $ . Therefore, the proposed inductor achieves a superior ${Q}$ -factor of 42.7 that is the highest reported value for a solenoid magnetic power inductor with this prior art. The calculated peak effective inductor efficiency is 98.11% for 3.6- to 1-V, 100-MHz dc–dc conversion.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Physics-Based Model for Understanding Electromigration-Induced Cavity
           Evolution in Advanced Narrow Line Copper Interconnects

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      Authors: Shizhao Wang;Chunmin Cheng;Tianjian Liu;Hehui Zhang;Lianghao Xue;Yameng Sun;Xu Han;Sheng Liu;
      Pages: 5123 - 5129
      Abstract: In the interconnects of microelectronic package with high current density and high-frequency fluctuation, electromigration (EM) events cause the cavities nucleation at the metal lines cathode and hillock pile-up at anode, which further lead to short circuit/open circuit and influence the overall device reliability substantially. In this work, mechanical modeling of EM-induced cavity failure was investigated and a modeling theory of efficient EM cavity morphology evolution based on physics was comprehensively introduced. According to mass diffusion theory, a dynamic model of elliptical cavity shape evolution with velocity and shape parameters was established. Meanwhile, kinetic equations of shape evolution expansion connected to cavity velocity and shape were proposed to explain the cavity expansion and cavity collapse processes, respectively. Based on the surface morphology analysis, it is obvious that cavity evolution form is determined by the competition between surface tension and electron wind. It is revealed that both them encourage cavity stretching in the direction of electric field intensity while compressing in the opposite. In addition, the mismatch of matter concentration between the left and right ends of the cavity will drive the cavity to migrate against the electric field intensity.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Ab Initio Study of HfO2/Ti Interface VO/Oi Frenkel Pair Formation Barrier
           and VO Interaction With Filament

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      Authors: Hiu Yung Wong;
      Pages: 5130 - 5137
      Abstract: Frenkel pair (FP) formation at HfO2/Ti interface and oxygen vacancy interaction with the filament in HfO2/Ti-based resistive random access memory (ReRAM) are the important mechanisms in the ReRAM operations. In this article, the formation barriers, ${E}_{A}$ , and formation energies of ${V}_{O}/{O}_{i}$ FP across the HfO2/Ti interface with and without preexisting vacancy are calculated using the ab initio tool under zero external electric field. It is found that both the formation barrier and energy can be increased or decreased due to a preexisting oxygen vacancy. The spread of the effect increases inversely with the distance between the FP and the preexisting vacancy. A compact model is then proposed. The parallel migration barrier of an oxygen vacancy at the nearest and the second nearest neighbors (NNs) of a filament is also studied. It is found that the second NN has the lowest barrier due to its ability to retain a +2 charge state. The merging and dissolution of an oxygen vacancy with a filament (equivalent to perpendicular migration) is found to have a similar behavior that +2 states enhance the interaction. It is found that the fourfold coordinated oxygens (4C) and threefold coordinated oxygens (3C) filaments behave similarly during dissolution. However, 4C and 3C filaments prefer merging with 4C and 3C vacancy, respectively. The barrier of merging a +2 4C vacancy with a 4C filament is only 0.56 eV. The data and model obtained from this study may be used to implement device-level simulators, such as kinetic Monte Carlo (KMC) simulators, for ReRAM.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Optimization of Cross-Linked Polyvinyl Alcohol Dielectrics for
           High-Performance Ultraflexible Organic Field-Effect Transistors

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      Authors: Hang Ren;Yanhong Tong;Mingzhao Ouyang;Jiake Wang;Lei Zhang;Yuegang Fu;Qingxin Tang;
      Pages: 5138 - 5143
      Abstract: Cross-linking polymer gate dielectric is an efficient strategy to improve its intrinsic properties for high-performance flexible organic field-effect transistors (OFETs). However, the detail optimization process of the polymer films with the various cross-linking degrees is often ignored, which can bring a significant effect on the electrical performance of OFETs. In this work, the cross-linked poly (vinylalcohol) (CPVA) is introduced as the gate dielectrics for the high-performance ultraflexible OFETs. The dielectric property and the surface property of CPVA thin films with various cross-linking degrees are investigated in detail. The OFETs with a high average mobility of 7.3 cm $^{2}cdot V^{-1}cdot s^{-1}$ , a current ON/ OFF ratio of over 107, and a lower density of trap states of $8.7times10$ 11 eV $^{-1}cdot cm^{-2}$ are achieved successfully. Moreover, the ultraflexible OFET presents a high mobility of over 5.1 cm $^{2}cdot V^{-1}cdot s^{-1}$ even bending around a copper wire with a small radius of $400 ~mu text{m}$ , due to the ultrathin thickness of the device. These results demonstrate that the CPVA thin film is a promising candidate dielectric material for flexible organic transistors, presenting huge potential for the next-generation flexible electronic devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Lamination of Flexible Organic Transistors on Fabric for E-Textile

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      Authors: Sachin Rahi;Vivek Raghuwanshi;Pulkit Saxena;Gargi Konwar;Shree Prakash Tiwari;
      Pages: 5144 - 5148
      Abstract: Flexible organic field-effect transistors (OFETs) based on solution-processed TIPS-Pentacene as semiconductor and high- ${k}$ P(VDF-TrFE) gate dielectric are successfully demonstrated on fabric for future electronic textile (e-textile) applications. These devices exhibited very high electrical performance with maximum ( $mu _{{mathrm {max}}}$ ) and average ( $mu _{{mathrm {avg}}}$ ) field-effect mobility values of ~1.2 and ~0.5(±0.3) ${mathrm {cm}}^{2}cdot {mathrm {V}}^{-1}cdot {mathrm {s}}^{-1}$ , respectively, in the saturation regime and ${I}_{ mathrm{scriptscriptstyle ON}}/{I}_{ mathrm{scriptscriptstyle OFF}}$ of ~103 for a low operating voltage of −5 V, along with excellent electromechanical stability. Furthermore, these devices showed excellent environmental stability with almost unchanged electrical characteristics for 26 weeks. Moreover, devices showed high cyclic stability with stable ON/ OFF switching characterized up to 500 cycles.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Revealing Three-in-One Nature of Organic Negative Transconductance
           Transistors

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      Authors: Hye-Su Shin;Hocheon Yoo;Chang-Hyun Kim;
      Pages: 5149 - 5154
      Abstract: Introducing a negative transconductance (NTC) regime into a switching curve of a field-effect transistor is a promising approach to overcome the fundamental limit of traditional digital logic circuits. However, the operation of NTC devices is only weakly conceptualized up to the present. This study proposes a drastically new way of regarding an NTC transistor as a functional equivalent of three interconnected normal field-effect transistors. The electrical model is directly inspired by the structural and materials characteristics of high-performance organic devices, and it is fully confirmed by measured experimental data. This finding, therefore, rationalizes that the NTC transistors have a unique potential to greatly reduce the transistor count in an integrated circuit, and offers a simple yet universal tool for systematic design and optimization of NTC transistor circuits through simulation-driven engineering.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Effect of Proton Radiation on Mechanical Structure of Silicon MEMS
           Inertial Devices

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      Authors: Shaoquan Chen;Qiancheng Zhao;Jian Cui;
      Pages: 5155 - 5161
      Abstract: This article investigates the effect of proton radiation on the mechanical structure of microelectromechanical systems (MEMS) inertial devices, including gyroscopes and accelerometers. To distinguish the effect of radiation on MEMS element and the circuit, the mechanical part and electronics are shielded by an aluminum barrier separately in the experiments where 7-Mev protons with a dose rate of $1times10$ 7– $1times10$ 9 p/(cm $^{2}cdot s$ ) are utilized. The results show that proton radiation on the MEMS mechanical structure may not cause device function failure or output drift but increase the white noise. The angle random walk and bias stability of the MEMS gyroscopes exhibit a linear relationship with the proton dose rate. Based on these observations, we propose a particle collision model to describe this effect for the first time. The radiation noise can dominate the output noise when the dose rate is more than $3.1times10$ 7 p/(cm $^{2}cdot s$ ) for the custom-designed gyroscopes. However, this phenomenon is not found in the accelerometers since the radiation noise did not exceed the inherent device noise level. Finally, in order to evaluate the effects of proton radiation caused by the application-specific integrated circuit (ASIC), the ASIC is exposed alone to protons, which makes the device’s output abnormal such as spikes, drift, and even failure. These findings discriminate the different effects of MEMS structure and circuit on device performance under irradiation and also give guidance to determine the radiation failure mechani-m of MEMS inertial devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Stable Deflection in Ferroelectric Negative-Capacitance Hybrid MEMS
           Actuator With Cubic Nonlinear Spring

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      Authors: Raghuram Tattamangalam Raman;Revathy Padmanabhan;Arvind Ajoy;
      Pages: 5162 - 5169
      Abstract: Electrostaticmicroelectromechanicalsystems (MEMS) actuators suffer from an instability called pull-in, wherein the movable electrode snaps onto the fixed electrode beyond a certain applied voltage. Thus, the entire allowed range is not utilized for stable operation. We propose pull-in free, low-voltage operation by using a cubic nonlinear spring with a ferroelectric negative-capacitance hybrid MEMS actuator. We use a physics-based framework based on the energy landscape to illustrate stability improvement. This framework uses energy–displacement and voltage–displacement plots for analysis. We predict that the actuator can operate in three distinct modes: 1) monostable; 2) bistable; and 3) always-stable, based on the value of the cubic spring constant. We also estimate the threshold values of the cubic spring constant that demarcate the three modes of operation. By proper choice of the cubic spring constant, we predict pull-in free, low-voltage operation of the hybrid actuator, when compared to the standalone MEMS actuator. The results obtained are in agreement with the numerical simulations. This work will aid in the design of electrostatic MEMS actuators for low-voltage applications without pull-in instability.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Vertical Tunneling Field-Effect Transistor With Germanium Source and
           T-Shaped Silicon Channel for Switching and Biosensing Applications: A
           Simulation Study

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      Authors: Iman Chahardah Cherik;Saeed Mohammadi;
      Pages: 5170 - 5176
      Abstract: In this article, we introduce a novel vertical tunneling transistor that uses two germanium source regions and a T-shaped silicon channel and investigate its performance for low-voltage digital/analog and biosensing applications, by using numerical simulations. The switching performance of the device is improved by employing two highly doped N+ pocket regions next to the germanium source regions. To increase the validity and accuracy of the obtained results, calibration with the results of an experimental report is carried out. As a biosensor, the performance of the device in detection and separation of different biomolecules is studied, too. Some of the main achievements among the various digital/analog and biosensing performance metrics are $I_{on} = 88.9 ~mu text{A}/mu text{m}$ , SS $_{mathrm{avg}} =25.28$ mV/dec, ${f}_{T} =192.64$ GHz, and ${S}_{I_{D}}= 6.95times10$ 5.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Microfluidic Platform for Characterizing Single-Cell Intrinsic
           Bioelectrical Properties With Large Sample Size

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      Authors: Yi Zhang;Minruihong Wang;Yu Zheng;Deyong Chen;Wei Wang;Junbo Wang;Jian Chen;
      Pages: 5177 - 5184
      Abstract: As the golden instrument of blood-cell phenotyping, hematology analyzers still cannot quantify intrinsic bioelectrical parameters of single cells due to limitations in sensitive structures and models. In this article, a microfluidic impedance platform composed of multiple paralleled double T-type constriction microchannels was developed, where raw impedance of traveling cells can be converted into intrinsic bioelectrical parameters of specific membrane capacitance ${C}_{textit {sm}}$ , cytoplasmic conductivity $sigma _{textit {cy}}$ , and cell diameter ${D}_{c}$ leveraging the newly developed bioelectrical model. In order to solve the problem of channel blockage, pathways for impedance measurement and cellular passing through were decoupled, and thus the microfluidic platform was capable of characterizing 1906 ± 909 K562 cells/sample ( ${n}_{sample} =$ ~50) and 2010 ± 1218 HL-60 cells/sample ( ${n}_{sample} =$ ~30), effectively meeting the requirements of hematology analyzers (~1000 cells/sample). Based on this microfluidic platform: 1) ${C}_{textit {sm}}$ , $sigma _{textit {cy}}$ , and ${D}_{c}$ from ~100000 K562 and HL-60 cells were quantified, producing a high successful rate of ~100% in classifying K562 versus HL-60 cells and 2) ${C}_{textit {sm}}$ , $sigma _{textit {cy}}$ , and ${D}_{c}$ from ~1000 cells of granulocytes, lymphocytes, and monocytes were quantified, producing a high successful rate of ~80% in classifying these three types. In conclusion, the presented microfluidic platform has the potential to be used as an indispensable sensing unit in hematology analyzers in the future.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • GaSb/GaAs Type-II Heterojunction TFET on SELBOX Substrate for Dielectric
           Modulated Label-Free Biosensing Application

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      Authors: Ashish Kumar Singh;Manas Ranjan Tripathy;Kamalaksha Baral;Satyabrata Jit;
      Pages: 5185 - 5192
      Abstract: A novel GaSb/GaAs type-II heterojunction TFET on SELBOX substrate (HJ-STFET)-based dielectric-modulated ultrasensitive label-free biosensor has been demonstrated in this article. The SELBOX substrate has been used in the proposed TFET-based sensor to reduce the lattice heat and improve the ${I}_{mathrm {ON}}/{I}_{{mathrm {OFF}}}$ ratio. Cavities in the gate oxide of the TFET are created to form dual-cavity (DC) HJ-STFET structure. These cavities contain the biomolecules to be sensed through the principle of gate-dielectric modulation. To validate the results, the analytical modeling of surface potential has been compared to simulated outcomes for different dielectric constant values of biomolecules. The threshold voltage sensitivity ( ${S}_{VT}$ ) and ${I}_{mathrm{ON}}/{I}_{mathrm{OFF}}$ sensitivity parameters of the proposed DC-HJ-STFET structure have been thoroughly investigated considering different biomolecules. The proposed DC-HJ-TFET structure is shown to have a higher current sensitivity ( $sim 6.67times10$ 11) and threshold voltage sensitivity (0.37 V) values over some recently reported TFET-based biosensors. Finally, we have verified the drain and back gate biasing, as well as linearity fit verification, on the proposed biosensor’s performance.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Thioglycolic Acid-Functionalized Water-Soluble MoS2-Based
           Sensor for Toxic Ion Detection

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      Authors: Santanab Majumder;Avik Sett;Dipak Kumar Goswami;Tarun Kanti Bhattacharyya;
      Pages: 5193 - 5198
      Abstract: This work demonstrates the implementation of thioglycolic acid (TGA) functionalized water-soluble NH2–molybdenum disulfide (MoS2) nanosheets as sensitive layers for toxic heavy metal ion sensing in drinking water. The sensor device was tested for several ions commonly found in drinking water, e.g., As (III), Pd (II), Hg (II), and Cd (II). When the sensor was exposed to individual ions, it showed negligible response toward elements such as As (III), Pd (II), and other commonly present metal ions. However, at 25 ppb, some cross sensitivity was observed between Cd (II) and Hg (II) ions. The mathematical analysis was performed to investigate the cross-sensitive behavior, and a model was put forward. It was evident from the higher attachment factor ( ${N}$ ) for Cd concerning Hg (II), derived from the model which supported Cd’s higher response when exposed individually ( ${N}_{text {Cd}}= 4times 10^{{16}}$ cm−3/ppb and ${N}_{text {Hg}}= 1.6times 10^{{14}}$ cm−3/ppb). Furthermore, the band structure and electron concentration were plotted for individual Cd (II) and Hg (II) ions. Compared to Hg (II), Cd (II) efficiently depleted the amine–MoS2 and TGA junction. To better understand selectivity and response, the device was exposed to Cd (II) and Hg (II) ions simultaneously at different concentrations, which looked into the effect of the two interacting ions. A mathematical model was hence established. It was found that the absorption coefficient ( ${K}_{text {Hg}}$ ) was much higher (63 ppb−1) than Cd ( ${K}_{text {Cd}}$ ) (0.38 ppb−1). The interaction factor ( ${K}_{text {Hg-Cd}}$ ), i.e., the absorption coefficient of Cd in the presence of Hg, was calculated as −0.086 ppb−2, which is lower than ${K}_{text {Cd-Hg}}{(}-0.013$ ppb−2), which indicated that Hg is more active toward adsorption in competition to the Cd ions. This competitive dominance for Hg (II) adsorption may be attributed to the affinity of thiol groups present in the TGA molecules for Hg (II) over Cd (II) ions. The device was repeatable after testing with five different devices with a standard deviation of 0f 0.5322 and stable up to 50 days with ±3% response variation. Thus, the proposed sensor may be a suitable candidate for low-cost water quality monitors.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Small-Signal Theory of the Gyro-BWO With the Zigzag Quasi-Optical System

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      Authors: Ekaterina M. Novak;Sergey V. Samsonov;Andrei V. Savilov;
      Pages: 5199 - 5205
      Abstract: We describe the small-signal theory of a backward-wave gyro-oscillator with a sectioned quasi-optical system with the zigzag path of the operating wave beam. This theory explains peculiarities (namely, a piecewise character) of changing the operating frequency and power of the output signal in the process of the broadband frequency tuning provided by changing the operating magnetic field.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Quantitative Analysis on the Field Strength in the Addressable Gated ZnO
           Nanowire Field Emitter Arrays: Model and Experiment

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      Authors: Yicong Chen;Xuqi Wang;Libin Wang;Chengyun Wang;Guofu Zhang;Juncong She;Shaozhi Deng;Jun Chen;
      Pages: 5206 - 5210
      Abstract: Addressable gated field emitter arrays (FEAs) have important applications in vacuum microelectronic devices. To fabricate high-performance device, a comprehensive understanding on the field emission characteristics of gated FEAs is necessary, which requires a quantitative analysis method. In this work, a general model based on Fowler-Nordheim (FN) theory has been established to fulfill this blank. It is found that nonlinear FN plot with positive and negative slopes could occur in gated FEAs, which its turning point is related to the proportion of anode and gate field. This provides a way for obtaining the field strengths applied by the anode and gate structures. Besides, the transconductance of the gated FEAs increases exponentially with the total surface field, which indicates that both the anode and gate field need to be increased for achieving a high transconductance device. As a demonstration, the addressable gated ZnO nanowire FEAs using multimicrosize pattern with radius as small as $2.5 ~mu text{m}$ have been designed and fabricated. The relationship between the transconductance and anode voltage can be well fitted by using the model, which deduces the proportion of anode and gate field in the device to be about 3:1.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Theoretical and Experimental Study of Gyro-TWT Solenoids With Displacement
           and Tilt

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      Authors: Bo Guan;Yelei Yao;Wei Jiang;Guo Liu;Hao Li;Jianxun Wang;Yong Luo;
      Pages: 5211 - 5215
      Abstract: Axis coincidence consideration is necessary in the design of gyrotron solenoids; besides, radial field component strongly affects the performance of gyrodevices owing to the transverse particle–wave interaction mechanism in it, especially for high-frequency operation. In this article, the theory of multiple eccentric coils is derived. It is capable of calculating the off-axis field inside the solenoid with specified displacement and tilt. Numerical calculations are validated by 3-D electromagnetic simulation methods. Based on the measured magnet field, the displacement and tilt of a three-coil magnet system are successfully predicted with a global optimization algorithm, and then, the magnet system is well calibrated using a pair of flanges.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • A Sub-THz High-Order Mode Backward Wave Oscillator Driven by Pseudospark
           Sourced Multiple Sheet Electron Beams

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      Authors: Guoxiang Shu;Jiacai Liao;Jingcong He;Junchen Ren;Jujian Lin;Guangxin Lin;Qi Li;Cunjun Ruan;Wenlong He;
      Pages: 5216 - 5222
      Abstract: A novel concept of combining the advantages of pseudospark (PS)-sourced electron beam (high beam current density), multiple-sheet-electron-beams (large total beam cross-sectional area), and high-order mode (HOM) slow wave structure (SWS) (high power capacity) to produce high-power terahertz signals is presented in this article. As an example, a sub-terahertz backward wave oscillator (BEO) driven by PS-sourced dual-sheet-electron-beams is designed. Measured results of the interaction circuit, including transmission/reflection coefficients and the dispersion relation, were in good agreement with simulation predictions. Beam-wave interaction simulations having considered the plasma effect and conductor loss predicted stable output signals with radiation power of 167.4–255.4 W over a tunable bandwidth of 234.4–241.0 GHz.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Exploration of a Kilowatt-Level Terahertz Amplifier Based on Higher-Order
           Mode Interaction

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      Authors: Changqing Zhang;Suye Lü;Jun Cai;Pan Pan;Jinjun Feng;
      Pages: 5223 - 5228
      Abstract: The parameters for a kilowatt-level high-power terahertz amplifier were explored based on the higher-order mode and extended-interaction mechanism. It has been demonstrated that the antisymmetric electrical field mode (TM21) has a unique advantage in achieving high power. Physical factors on power extraction were studied. In particular, the heavily reduced ${Q}_{{0}}$ has a great effect on the coupling characteristic as well as the output power. It is found that the critical coupling state, i.e., ${Q}_{e} = {Q}_{{0}}$ , defines an upper limit of the power that can be extracted from the output circuit. The design of a complete interaction circuit was accomplished. The particle-in-cell (PIC) simulations showed that a saturated power of 1.2 kW can be achieved at 220 GHz with a voltage of 45 kV and a total current of $2times0.6$ A where two beams were used. The saturated gain is over 30 dB with a 3-dB bandwidth of $sim 400$ MHz.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Investigation and Fabrication of the Printed Microstrip Meander-Line
           Slow-Wave Structures for D-Band Traveling Wave Tubes

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      Authors: Guo Guo;Tianzhong Zhang;Jing Zeng;Zongyao Yang;Lingna Yue;Yanyu Wei;
      Pages: 5229 - 5234
      Abstract: Two typical topology shapes of the microstrip meander line (MML) including round U-shaped and V-shaped slow-wave structure (SWS) for ${D}$ -band traveling wave tubes (TWTs) are comparatively investigated, fabricated, and tested in this article. As a critical factor applied in millimeter-wave frequency, the high-frequency losses of the MML SWS are emphatically discussed. The two types of golden SWSs are both fabricated with the thin-film circuit technology on quartz substrates. After the surface roughness test and the cavity fabrication, the SWS samples are assembled and tested. According to the experimental test results, the ${S}_{11}$ parameters of the U-shaped and V-shaped transmission models are below −13.5 dB versus −15 dB, and the “cold” ${S}_{21}$ parameters are over −6.4 dB versus −4.9 dB, which are approached to the simulation results with the consideration of the silver conductive paste (SCP). At 140 GHz, the tested transmission losses for the U-shaped SWS and V-shaped SWS are about 0.35 and 0.29 dB/mm, respectively. Although particle-in-cell (PIC) simulations for the two SWSs both predict more than 100-W output power, the V-shaped MML TWT shows better bandwidth and loss performances than the U-shaped MML TWT.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Particle-in-Cell Simulations of Ten-Vane Microwave-Oven Free-Running
           2.45-GHz “Cooker” Magnetron: Microwave Power Increase up to 6 kW in a
           Pulsed Mode (3 kW With 50% Duty Cycle)

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      Authors: Andrey D. Andreev;Edl Schamiloglu;Brendan E. Nunan;Sean M. Torrez;
      Pages: 5235 - 5241
      Abstract: Standard operation of a conventional microwave oven 2.45-GHz “cooker” magnetron with 4.0–4.3 kV of pulsed applied voltages at 0.17–0.19-T magnetic fields results in generation of pulsed microwave power 1.8–2.8 kW, which is recalculated to an average microwave power 0.9–1.9 kW when the “cooker” magnetron operates with 50% duty cycle while driven by a “rectified” ac voltage from the wall-plug. It has been shown in many experimental studies of “cold-start” operation of a standard ten-vane 2.45-GHz “cooker” magnetron that it readily sustains, when properly conditioned, up to ~10-kV dc and up to ~14 kV of peak-to-peak ac applied voltage with just a few microamphere cold (field emission) leakage (anode) current. The latter suggests that a standard 2.45-GHz “cooker” magnetron may successfully operate in the desired, lowest $pi $ -mode with much more output microwave power at even higher magnetic fields when driven by up to ~10 kV of dc or quasi-dc appropriate, synchronous applied voltage. Results of improved concurrent electromagnetic particle-in-cell (ICEPIC) simulations of magnetron operation at different magnetic fields with synchronous applied voltages show that, for example, with 8.0-kV applied voltage at 0.35-T magnetic field, the 2.45-GHz “cooker” magnetron is able to generate up to 6.0 kW of pulsed microwave power with an anode current of ~0.9 A.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Development and Initial Experimental Results of a Terahertz Pulsed Field
           Gyrotron in the WHMFC

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      Authors: Houxiu Xiao;Yu Huang;Xiaotao Han;Xianfei Chen;Pengbo Wang;Xin Qi;Zhenglei Wang;Zhaolun Deng;Hanqing Zhou;Zhiyu Qiu;Zhaochang He;Gang Zhu;Alexei Kuleshov;Eduard Khutoryan;Sergey Ponomarenko;
      Pages: 5242 - 5247
      Abstract: We report the design and initial experimental results of an 800-GHz second harmonic gyrotron prototype, in which a 15-T pulsed magnet is applied. This gyrotron prototype is developed at the Wuhan National High Magnetic Field Center (WHMFC). An in-house software for analyzing and designing terahertz gyrotrons and an experimental research platform are developed. In addition, alignment adjustments, eddy current effects, and radiation tests are discussed. The initial experimental results show that the prototype gyrotron can irradiate ~40 W at fundamental harmonic 383.7-GHz (TE1,4) waves at 14.14 T and a few milliwatts at second harmonic 0.8-THz (TE8,5) waves at 14.86 T.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • 100-MW-Level Experiments of a Gyromagnetic Nonlinear Transmission Line
           System

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      Authors: Yancheng Cui;Jin Meng;Liyang Huang;Danni Zhu;
      Pages: 5248 - 5255
      Abstract: The wideband high-power microwave systems have the advantages of wide energy spectrum, electron beam independence, compactness, and low cost. The gyromagnetic nonlinear transmission line (GNLTL) has drawn much attention for its potential as a novel solid-state, frequency-agile, and compact wideband source. The working mechanism of GNLTL is different from that of the traditional electric vacuum tubes, and the strong dispersion and nonlinear characteristics make it difficult to be accurately theoretically calculated and simulated. In this article, a 100-MW-level GNLTL system based on a Tesla-type driver was designed and constructed. A series of test experiments were then carried out to investigate the effects of different configurations, including delay line length, ferrite cores’ assembly orientation, transmission line length, bias magnetic field magnitude, and excitation voltage. The changing laws of the key parameters of the output microwaves including the peak power, modulation depth, center frequency, and percentage band are summarized and the underlying physical mechanisms are analyzed. The results may be instructive for the predesign of GNLTLs, especially for the devices operating at high power. In addition, a multiple center frequency points’ phenomenon was discovered in the output signal, which may bring new application possibilities for GNLTL.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Experimental Investigations on Effects of Operation Parameters on a
           263-GHz Gyrotron

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      Authors: Tao Song;Jie Huang;Chen Zhang;Peisheng Liang;Xu Qi;Da Ran;Zheng Yan;Zhenhua Wu;Kaichun Zhang;Tao Zhao;Min Hu;Yanyu Wei;Yubin Gong;Wei Wang;Diwei Liu;
      Pages: 5256 - 5261
      Abstract: In this article, the experimental investigations on a 263-GHz gyrotron are presented. With the change of the operating magnetic field and the beam energy, the operating frequency is adjusted and the output power is also varied. It is found that when the operating magnetic field changes from 9.59 to 9.82 T at a fixed operating voltage of 20 kV and a beam current of 0.8 A, the operating frequency increases from 263.39 to 264.84 GHz, the frequency-tuning range is about 1.45 GHz, and the output power is from 26 to 463 W. When the operating voltage increases from 14.4 to 22.2 kV at a fixed operating magnetic field of 9.65 T, the operating frequency decreases from 263.68 to 263.40 GHz, the frequency-tuning range is 0.28 GHz, and the output power changes from 52 to 424 W. When the operating magnetic field is fixed at 9.65 T and the operating voltage is fixed at 20 kV, but the beam current increases from 120 to 880 mA, the output power increases from 21 to 277 W, the operating frequency increases from 263.396 to 263.425 GHz, and the frequency-tunable range is 0.029 GHz. The effects of the axial position of the gyrotron in the superconducting magnet system on the operating frequency, the frequency-tuning range, and the output power are also investigated experimentally. When the beam current is increased, the nonstationary phenomenon is observed.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Highly Scaled InGaZnO Ferroelectric Field-Effect Transistors and Ternary
           Content-Addressable Memory

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      Authors: Chen Sun;Kaizhen Han;Subhranu Samanta;Qiwen Kong;Jishen Zhang;Haiwen Xu;Xinke Wang;Annie Kumar;Chengkuan Wang;Zijie Zheng;Xunzhao Yin;Kai Ni;Xiao Gong;
      Pages: 5262 - 5269
      Abstract: We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ( $I_{ mathrm{scriptscriptstyle ON}}/I_{ mathrm{scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{text {1-x}}text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer ( ${A}_{Fe}$ ) and the metal–oxide–semiconductor layer ( ${A}_{MOS}$ ), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~mu text{A}/ mu text{m}$ ( ${V}_{mathrm{GS}} - {V}_{mathrm{TH}}$ = 5 V and ${V}_{mathrm{DS}}$ = 2 V) and ${I}_{ mathrm{scriptscriptstyle ON}} / {I}_{ mathrm{scriptscri-tstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Explaining Steep-Slope Switching in Carbon Nanotube Dirac-Source
           Field-Effect Transistors

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      Authors: Peng Wu;Joerg Appenzeller;
      Pages: 5270 - 5275
      Abstract: Dirac-source field-effect transistors (DS-FETs) have been proposed as steep-slope transistors for low-power switching. The steep-slope switching of a DS-FET originates from the “low-pass” energy filtering effect of the graphene Dirac source, which requires the number of modes in the graphene source to be lower than the ones in the channel. However, despite the fact that this requirement is not satisfied in a DS-FET with a carbon nanotube (CNT) channel, steep-slope switching has been experimentally demonstrated in such devices. In this article, we propose a mechanism of switching in CNT DS-FETs that is consistent with the small number of modes in a CNT. We argue that the CNT acts as a transverse momentum selector, which effectively introduces a bandgap in the graphene source, and thus, the Klein tunneling in the graphene n-p junction becomes band-to-band tunneling (BTBT). This makes the CNT DS-FET essentially a new type of tunneling field-effect transistor (TFET), which we call momentum-selector TFET (MS-TFET). Moreover, we study the impact of misorientation between graphene and CNT on the performance of a CNT MS-TFET. Finally, we show that scattering may actually be beneficial in such a device and could potentially enhance the on-current of a CNT MS-TFET.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Multilevel 3-D Device Simulation Approach Applied to Deeply Scaled
           Nanowire Field Effect Transistors

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      Authors: Natalia Seoane;Karol Kalna;Xavier Cartoixà;Antonio García-Loureiro;
      Pages: 5276 - 5282
      Abstract: Three silicon nanowire (SiNW) field effect transistors (FETs) with 15-, 12.5- and 10.6-nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental ${I}_{D}$ – ${V}_{G}$ characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in $mathit {k}$ -space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed ${I}_{D}$ – ${V}_{G}$ characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Impact of Contact Configuration on Contact Resistance in Ultranarrow
           Graphene Nanoribbon Devices

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      Authors: Mirko Poljak;Mislav Matić;Ante Zeljko;
      Pages: 5283 - 5288
      Abstract: Contact resistance strongly deteriorates the performance of devices based on 2-D materials and their nanostructures, masking their exceptional electronic and transport properties. This work explores the dependence of contact resistance ( ${R}_{C}$ ) of graphene nanoribbon (GNR) devices on contact geometry using atomistic quantum transport simulations. The influence and contributions of edge and top contacts and GNR width scaling on ${R}_{C}$ is studied in detail. Metallization effects on the density of states, transmission, and GNR field-effect transistor (GNR FET) driving current are investigated. We show that wider GNRs (~4 nm) exhibit edge-dominated transport and lower ${R}_{C}$ than the ultranarrow GNRs (~0.4 nm) that exhibit much higher contact resistance which is also dependent on the contact area.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Charge Pumping Technique to Measure Polarization Switching Charges of
           FeFETs

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      Authors: Kab-Jin Nam;Jung-Min Park;Byoung-Deog Choi;Kee-Won Kwon;
      Pages: 5289 - 5296
      Abstract: This study proposes a new method to measure the polarization charge of ferroelectric field-effect transistors (FeFETs) using a pulse generator and source measurement unit (SMU) and exploiting the charge pumping (CP) principle, which is widely followed to measure the interface trap charge density ( ${D}_{text{it}}$ ) of MOSFETs. Although the pulse waveforms applied to the gate electrode were equal to that of conventional polarization charge measurement methods, the response current was measured using the SMU similar to that in CP. As the proposed method measured the average dc current on the well or source/drain terminal, it provided a reliable quantification of polarization charges with low noises even at lower applied voltages. This measurement is possible because the ferroelectric (FE) dipole-induced charge is immovable, similar to an interface charge that is not moved by an interface trap until it recombines with a movable opposite carrier. This method conveniently measured the switching charge even for < 50 ns of rising/falling time of the applied pulse. Moreover, as the read current resolution of the SMU is $ < 5times10$ −12 A, the switching charge can be measured with a device area $ < 1 boldsymbol {mu }text{m}$ 2. Thus, the proposed CP-based method proved to be a highly effective method of polarization charge measurement for three- or four-terminal devices, such as FeFETs, unless the measurement requires the hysteresis curve along with polarization charges.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Impact of Oxygen Vacancy on Ferroelectric Characteristics and Its
           Implication for Wake-Up and Fatigue of HfO2-Based Thin Films

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      Authors: Jiajia Chen;Chengji Jin;Xiao Yu;Xiaole Jia;Yue Peng;Yan Liu;Bing Chen;Ran Cheng;Genquan Han;
      Pages: 5297 - 5301
      Abstract: In this article, a phase-field polarization switching model for ferroelectric HfO2-based thin films considering oxygen vacancies ( ${V}_{o}$ ) has been developed based on the 2-D time-dependent Ginzburg–Landau (TDGL) equation coupling with Poisson’s equation. The impacts of nonuniform ${V}_{o}$ distributions induced by the monolayer grains in ultra-scaled Hf0.5Zr0.5O2 (HZO) films and ${V}_{o}$ concentrations on ferroelectric characteristics are investigated in detail by the developed model which is verified and calibrated by measurement results of HZO. Furthermore, possible mechanisms of wake-up and fatigue are revealed by the simulation with the proposed model. It is clarified that the redistribution of nonuniform ${V}_{o}$ in the in-plane direction leads to the transition from a pinched polarization-voltage curve to a conventional one at the early stage of wake-up, while the generation of ${V}_{o}$ within a ferroelectric film results in ferroelectricity enhancement and reduction in wake-up and fatigue processes, respectively.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

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      Authors: Carlo Gilardi;Robert K. A. Bennett;Youngki Yoon;Eric Pop;H.-S. Philip Wong;Subhasish Mitra;
      Pages: 5302 - 5309
      Abstract: Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • New Insights Into Memory Window of Ferroelectric FET Impacted by Read
           Operations With Awareness of Polarization Switching Dynamics

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      Authors: Chang Su;Qianqian Huang;Kaifeng Wang;Zhiyuan Fu;Ru Huang;
      Pages: 5310 - 5315
      Abstract: In this article, the impacts of read operation under transient gate voltage sweep on the memory window (MW) of ferroelectric field-effect transistor (FeFET) are systematically investigated. By taking into consideration the polarization switching dynamics, it reveals a significant dependence on the sweep range and rate of gate voltage. With increasing sweep range, the increase of polarization switching leads to the monotonically increasing MW. However, different from sweep range, the MW of FeFET nonmonotonically varies with the increasing sweep rate, which is caused by the competition between decreased polarization switching and increased voltage drop on ferroelectric (FE) layer during forward sweep. Besides, compared with the MW obtained by pulsed gate voltage, it is found that the MW obtained by swept gate voltage can be the smaller one even without the consideration of charge trapping contribution. Furthermore, the impacts of FE switching time on MW are also discussed, indicating that the MW may not always be a constant even under quasi-static sweeping with low sweep rate, and the relationship between sweep rate of gate voltage and switching speed of FE plays a critical role in MW evaluation.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Comprehensive Variability Analysis in Dual-Port FeFET for Reliable
           Multi-Level-Cell Storage

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      Authors: Swetaki Chatterjee;Simon Thomann;Kai Ni;Yogesh Singh Chauhan;Hussam Amrouch;
      Pages: 5316 - 5323
      Abstract: HfO2-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of HfO2 degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage (VTH) states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of VTH states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness (tFE) from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing tFE makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in VTH are reduced for BG read on reducing tFE, which allows us to hold the same number of states even at such a scaled thickness. Finall-, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled tFE. We demonstrate that dual-port FeFET with BG read and scaled tFE offers MLC storage of 3 bits.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Effect of Graphite as Electrodes on Electrical and Photoelectrical
           Behavior of Multilayer MoS2 and WS2 FETs

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      Authors: Jie You;Yichi Zhang;Maolong Yang;Ningning Zhang;Maliang Liu;Zhangming Zhu;Huiyong Hu;Liming Wang;
      Pages: 5324 - 5329
      Abstract: Transition-metal dichalcogenide materials have attracted considerable attention due to their outstanding properties, and however, the carrier collection efficiency remains a major problem for achieving high-performance electronic and optoelectronic devices. In this research, we compared the carrier transport properties of graphite and Au in contact with MoS2 (WS2) materials. The use of graphite for the drain–source electrodes significantly improves carrier collection efficiency, thus enhancing the overall electronic and optoelectronic performance of MoS2 and WS2 FETs. The device’s ON/ OFF current ratio with two graphite contact electrodes increased by about two orders of magnitude (120 and 207 for MoS2 and WS2 FETs, respectively) than that with conventional Au electrodes. Furthermore, the Gr-MoS2-Gr FET shows ultrahigh responsivity (3869 A/W), detectivity ( $4.6times10$ 12 Jones), and extraordinary short photoresponse fall time ( $60 ~mu text{s}$ ). Compared with the Au-MoS2-Au FET, the fall time is reduced by about six orders of magnitude. Interestingly, the Gr-MoS2-Gr and Gr-WS2-Gr FETs demonstrate different detection mechanisms. The Gr-MoS2-Gr photodetector shows a photoconduction mechanism under the gate voltage of −10 to −6 V and a photogate mechanism under −4 to 2 V, whereas the Gr-WS2-Gr photodetector is only driven by a photoconduction mechanism. The Gr-TMDs-Gr’s outstanding electronic and photoelectrical properties hold great potential for various applications in advanced optoelectronic devices.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Investigation of Source Region’s Random Doping Fluctuation Effects on
           Analog and RF Performance in All-Si DG-TFET

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      Authors: Ashish Maurya;Kalyan Koley;Bhubon C. Mech;Jitendra Kumar;Pankaj Kumar;
      Pages: 5330 - 5336
      Abstract: In this work, we report the impact of source region’s random dopant fluctuations (RDFs) induced variability on n-type silicon double gate (DG)-TFETs via 3D-device simulation. We have observed that source region’s RDF induces strong variability in the analog and RF figures of merit (FOMs) of the devices. This is the first report showing detailed impact of RDF on DG-TFET device and based circuit. The impact of RDF is analyzed by taking RDF only in source region as tunneling barrier width depends mostly on source doping and so does the ON-state current. The variation of analog and RF FOMs, such as transconductance $({g}_{m})$ , transconductance generation factor $({g}_{m}/{I}_{d})$ , output resistance $({R}_{o})$ , intrinsic gain $({g}_{m}{R}_{o})$ , capacitances $({C}_{{gs}}$ , ${C}_{{gd}}$ ), gate delay $({T}_{m})$ , cutoff frequency $({f}_{T})$ , and subthreshold swing (SS), is reported. We benchmark the device analog and RF performance of the RDF sample with respect to continuum one. On the basis of observed effective deviation in characteristics, common-source amplifier circuit is simulated to analyze the deviation in voltage-transfer characteristic (VTC) and gain–bandwidth product (GBWP).
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Analysis and Modeling of Current Mismatch in Negative Capacitance
           Field-Effect Transistor

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      Authors: Ravi Goel;Ayushi Sharma;Yogesh Singh Chahuan;
      Pages: 5337 - 5344
      Abstract: In this work, we analyze the impact of random dopant fluctuations (RDFs) on the mismatch behavior of the negative capacitance field-effect transistor (NCFET). We observe that the drain current mismatch decreases in the NCFET compared to conventional MOSFET, and it further decreases with an increase in the thickness of the ferroelectric layer ( ${t}_{text {fe}}$ ). Metal–ferroelectric–metal–insulator–semiconductor (MFMIS)-type NCFET shows 24% and 22% improvement in mismatch power in comparison to baseline FET at $vert {V}_{text {GS}}vert = {0.2}$ and 1 V, respectively. We show that the mismatch in NCFET is directly proportional to channel doping concentration, similar to baseline MOSFET. For the first time, we demonstrate that mismatch power varies nonmonotonically with the variation in the Landau coefficient $alpha $ , and the other Landau coefficient $beta $ has an impact on mismatch at higher ${t}_{text {fe}}$ only. We also present a compact model, under the industry standard Berkeley Short-channel IGFET Model for Bulk MOSFET (BSIM-BULK) MOS model’s framework, which can accurately capture drain current mismatch from subthreshold to strong inversion region for NCFET. The model is extensively validated with the experimentally calibrated technology computer-aided design (TCAD) simulations across different biases and temperatures.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Dielectric Response in Ferroelectrics Near Polarization Switching:
           Analytical Calculations, First-Principles Modeling, and Experimental
           Verification

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      Authors: Sergiu Clima;Anne S. Verhulst;Pratik Bagul;Brecht Truijen;Sean R. C. McMitchell;Ingrid De Wolf;Geoffrey Pourtois;Jan Van Houdt;
      Pages: 5345 - 5350
      Abstract: Ferroelectrics (FEs) are increasingly used in nonvolatile memory applications. However, the impact of the electric dipole switching on its material parameters, in particular on the dielectric response, is not fully understood. In this work, an analytical model, linking the dielectric response to the potential energy curve, is first used to qualitatively illustrate the nonconstant evolution of the dielectric response with applied electric field. Increasing precision, we then show from first-principles density functional theory simulations that defect-free FE materials undergo changes in potential energy near the FE switching that lead to vibrational modes softening, which impacts the dielectric response. In particular, we observe that the dielectric response $varepsilon $ of an FE material with antialigned polarization increases as the applied electric field increases toward the coercive field. We incorporate this new insight in the time-dependent NLS-based predictions and demonstrate that this evolution of the dielectric response right before polarization reversal is required for a proper match between experiment and prediction of the capacitance–voltage (CV) characteristics of the metal–ferroelectric–metal (MFM) capacitor.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • The Ubiquitous Memristive Response in Solids

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      Authors: Rafael Schio Wengenroth Silva;Fabian Hartmann;Victor Lopez-Richard;
      Pages: 5351 - 5356
      Abstract: Basic ingredients universally available in the carrier transport of conductive solids are proved to be sufficient (not necessary) conditions for the formation of memory while symmetry, or the lack of it, plays a decisive role in the nature of this response. It suffices that the input driving frequency is of the order of the inverse relaxation time and that the nonequilibrium carrier densities are in the order of the quasi-equilibrium ones. Thus, memristive response with ON and OFF states at zero voltage, Type I, and vanishing ON– OFF ratio, Type II, arise naturally according to simple symmetry constraints and are contrasted here in a fully analytical picture. Figures of merit for the conductance and the robustness of the memory response are presented in the form of concise correlations between general intrinsic microscopic parameters such as relaxation times, activation energies, and efficiencies with external drives: voltage pulses, temperature, and illumination. Explicit analytical expressions unveil the mimicry of inductive- and capacitive-like leaning impedances without the need of relaxing the interpretation of flux that has been used for more stringent definitions of memristors.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy

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      Authors: Wen-Chieh Chen;Shih-Hung Chen;Thomas Chiarella;Geert Hellings;Dimitri Linten;Guido Groeseneken;
      Pages: 5357 - 5362
      Abstract: In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length ( ${L}_{g}$ ) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Flexible and Compatible Synaptic Transistor Based on Electrospun In2O3
           Nanofibers

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      Authors: Hui Li;Yanan Ding;Haiyang Qiu;Yixin Zhu;Chengzhe Han;Guoxia Liu;Fukai Shan;
      Pages: 5363 - 5367
      Abstract: Emulating synaptic behavior using the three-terminal and ion-coupled transistors is considered as a promising strategy for the realization of neuromorphic devices. Meanwhile, one-dimensional (1-D) nanostructures show great potential for the fabrication of flexible electronic devices. In this work, 1-D indium oxide (In2O3) nanofibers were fabricated by the electrospinning (ES), and the flexible and compatible synaptic transistor based on In2O3 nanofibers was integrated on polyimide (PI) substrate. The synaptic behaviors, such as the short-term plasticity (STP) and long-term plasticity (LTP), are simulated by the synaptic transistor with chitosan solution as the gate dielectric. The fabricated synaptic transistor exhibits good biocompatibility and environmental compatibility, and the pattern recognition rate of the simulated device array by the Mixed National Institute of Standards and Technology (MNIST) database of the handwritten digits is confirmed to be as high as 92%.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • DDDMOSFET Performance Improvement by Gate Oxide Removal Followed by
           Silicided Source/Drain Formation in Gate Slots

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      Authors: Xue-Jiao Wang;Zhao-Yang Li;Zhao-Zhang Yan;Lei-Gang Chen;Zhong-Hua Li;Yu-Long Jiang;Jing Wan;
      Pages: 5368 - 5372
      Abstract: In this work, the intentional insertion of slots in metal gate (MG) is introduced to solve the dishing issue for the double-diffused drain MOSFET (DDDMOSFET) fabrication. For traditional DDDMOSFET, the gate oxide layer in slots will be reserved to improve the device reliability, which requires an additional photomask to screen the gate/slot regions during the following sidewall formation and source/drain (S/D) implantation. This makes the process more complicated with increased cost. Without that additional photomask, it is proposed that the removal of gate oxide layer in slots can directly allow the floating S/D formation and the followed Ni silicidation there. It is demonstrated that such a novel process can not only relieve the MG dishing issue but can also effectively result in ~16% higher ON current and comparable OFF current for both N- and P-DDDMOSFETs without threshold voltage shift after applying electrical stress on gates. It is also revealed that the floating silicided S/Ds in slots have negligible influence on device breakdown characteristics. By saving one photomask, this work proposes a novel solution for the effective integration of core devices with very small feature sizes and high-voltage (HV) devices with large feature sizes in the same die, which is a common challenge for display driver chip fabrication using high- ${k}$ /MG (HK/MG) technology.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Compact Modeling of Nanocluster Functionality as a Higher-Order Neuron

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      Authors: Celestine P. Lawrence;
      Pages: 5373 - 5376
      Abstract: Disordered nanoclusters with multielectrode input–output functionality had recently been experimentally realized with energy-efficient and emergent computational capacity, and thus an interconnected network of several such nanoclusters had been proposed to realize artificial neural networks. To aid that end, here we show that nanocluster functionality can be fit to the simplest dendritic neuron model (DNM), where the only form of nonlinearity is due to multiplicative interactions. This work brings into the spotlight higher-order neural networks (known for their efficient encoding of geometric invariances) to serve as an explainable baseline model of nano-networks against which experimentalists can compare more sophisticated models (deep neural networks or physics-based models such as the lin-min network introduced here) and provides ground for designing novel approximate hardware and a statistical mechanics analysis of the learning performance of interconnected nanoclusters versus perceptrons (where neurons output a nonlinear function of the weighted sum of their inputs). A network with just ten higher-order neurons is shown to achieve a classification accuracy of more than 96% on the MNIST benchmark for handwritten digit recognition (which required 100 times more neurons in three-layer perceptrons).
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Electrically Self-Aligned, Reconfigurable Test Structure Using WSe2/SnSe2
           Heterojunction for TFET and MOSFET

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      Authors: Pushkar Dasika;Kenji Watanabe;Takashi Taniguchi;Kausik Majumdar;
      Pages: 5377 - 5381
      Abstract: Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe2/SnSe2 van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe2/metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Impact of Externally Induced Local Mechanical Stress on Electrical
           Performance of Decananometer MOSFETs

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      Authors: Kookjin Lee;Ben Kaczer;Anastasiia Kruv;Mario Gonzalez;Geert Eneman;Oguzhan Orkut Okudur;Alexander Grill;Ingrid De Wolf;
      Pages: 5382 - 5385
      Abstract: Vertical, gigapascal-level mechanical stress (MS) is induced at different locations along the channel of 40-nm effective gate length planar CMOS field-effect transistor (FET) devices and electrical parameter variations are investigated. In both p-and n-channel devices, the threshold voltage, mobility, and ON-current are seen to change proportionally with the additional MS, while gate-induced drain-leakage current increases exponentially. A clear effect of the location of the applied force along the source–drain direction is observed on the transistor parameters. Simulations show that a mechanical load located closer to the FET source induces a stronger asymmetry between the source and drain stresses. This leads to asymmetric subband splitting/warping, which reduces the backscattering rate at the source, in line with theoretical predictions on the importance of the channel barrier near the source for current in quasi-ballistic transistors.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • The Investigation of Electrical Characteristics for Carbon Nano-Tubes as
           Through Silicon Via in Multi-Layer Stacking Scheme With an Optimized
           Structure

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      Authors: K. -C. Chen;Nilabh Basu;S. -C. Chen;M. -H. Lee;M. -H. Liao;
      Pages: 5386 - 5390
      Abstract: Through silicon via (TSV) is the key technology for 3-D integrated circuits (3-DICs) which could vertically stack homogeneous or heterogeneous dies with the high performance and density. To evaluate the electrical characteristics of TSV at the high-frequency transmission, the skin effect and surface roughness effect are necessary to be considered. However, these effects would significantly result in the TSV equivalent resistance under the high operating frequency. Thus, it is important to investigate the carbon nano tubes (CNTs) TSV which has less skin effect intrinsically. In this work, we analyze the advantage of CNTs as TSV compared to the conventional filling materials such as copper (Cu). Furtherly, we also propose the equivalent circuit model of TSV and its multi-layer structure to simulate the electrical behaviors with different TSV pitch, height, diameter, and stacking layers by using ANSYS designer and high-frequency structure simulator (HFSS). Based on the frequency-domain analysis, it can be found that CNTs TSV has the lower frequency-dependent loss than Cu due to the lower equivalent resistance. In a summary, CNTs could be a promising TSV filling material at the high-speed transmission frequency based on our study.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Forming-Free NbO x -Based Memristor Enabling Low-Energy-Consumption
           Artificial Spiking Afferent Nerves

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      Authors: Yaxin Ding;Peng Yuan;Jie Yu;Yuting Chen;Pengfei Jiang;Yuan Wang;Yannan Xu;Shuxian Lv;Zhiwei Dang;Boping Wang;Xiaoxin Xu;Tiancheng Gong;Qing Luo;
      Pages: 5391 - 5394
      Abstract: Two-terminal volatile NbOx-based threshold switching memristor devices with electrical self-oscillation behavior have attracted tremendous interest for applications in both oscillators and neural networks. However, the forming process of NbOx devices can be a burden and limit their application. In this study, a forming-free NbOx-based threshold switching device is obtained by reducing the oxygen content of the NbOx film, which simplifies the circuit design of the NbOx device array and improves the device-to-device (D2D) uniformity due to the removal of the forming step. Furthermore, a low-threshold switching voltage is achieved in the forming-free device, indicating a low-power consumption operation. Finally, we demonstrate a low-energy-consumption artificial spiking afferent nerve based on a forming-free NbOx device for spiking neural network (SNN) applications.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • An Optically-Reconfigurable PUF Based on Logarithmic Photoreceptor of CMOS
           Dynamic Vision Sensors

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      Authors: Haibiao Zuo;Qian Li;Hongxia Zheng;Yatao Yang;Xiaojin Zhao;
      Pages: 5395 - 5398
      Abstract: In this brief, a novel optically-reconfigurable physical unclonable function (OR-PUF) is presented for CMOS dynamic vision sensor (DVS). By utilizing the in-pixel logarithmic photoreceptor’s spatial photoresponse nonuniformity (PRNU) as the entropy source, raw physical unclonable function (PUF) bits having high reliability and randomness can be generated with monochromatic illumination in visible spectrum. In addition, the proposed OR-PUF can be reconfigured to new challenge-response-pair (CRP) spaces under the illumination with different visible wavelengths. Moreover, the proposed implementation is validated by prototype chips fabricated using a 0.18- $mu text{m}$ standard CMOS process. Featuring excellent randomness by passing the widely-adopted National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools, the fabricated PUF chips exhibit a uniqueness of 49.37% and a worst case bit error rate (BER) of 1.93% under the voltage–temperature (VT) range of 0 °C–80 °C and 1.65–2.2 V.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Trench Split Gate MOSFET’s Inductive Switching

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      Authors: H. Kang;
      Pages: 5399 - 5403
      Abstract: A trench split gate metal-oxide-semiconductor field-effect transistor (MOSFET) inductive switching is analyzed by adopting six-terminal method. Owing to the buried source terminal in the trench oxide, conventional three-terminal (gate, source, and drain) analysis has a limitation for investigating the detailed time-dependent current flow in the drift region, channel, as well as each terminal. However, a mixed-mode simulation tools enable us to look into the complicated current flow mechanisms in the device by dividing the gate terminal into the gate-to-source and the gate-to-drain terminals and the source terminal into the ${n} +$ , the ${p} +$ , and the shielded source terminals. The six-terminal method enables us to understand the fundamental turn-on and turn-off switching mechanisms that we have not found out so far from the measurement.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • From Mega to nano: Beyond one Century of Vacuum Electronics

    • Free pre-print version: Loading...

      Pages: 5404 - 5405
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Materials, processing and integration for neuromorphic devices and
           in-memory computing

    • Free pre-print version: Loading...

      Pages: 5406 - 5407
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power
           Applications

    • Free pre-print version: Loading...

      Pages: 5408 - 5409
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • TechRxiv: Share Your Preprint Research with the World!

    • Free pre-print version: Loading...

      Pages: 5410 - 5410
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • IEEE Open Access Publishing

    • Free pre-print version: Loading...

      Pages: 5411 - 5411
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
  • Introducing IEEE Collabratec

    • Free pre-print version: Loading...

      Pages: 5412 - 5412
      Abstract: Advertisement.
      PubDate: Sept. 2022
      Issue No: Vol. 69, No. 9 (2022)
       
 
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