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IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 18  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [228 journals]
  • IEEE ELECTRON DEVICES SOCIETY

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • IEEE Transactions on Electron Devices information for authors

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      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
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      Abstract: This page or pages intentionally left blank.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Changes to the Editorial Board

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      Authors: Giovanni Ghione;
      Pages: 4062 - 4063
      Abstract: After six years on the IEEE Transactions on Electron Devices (T-ED) Editorial Board, Prof. Siddharth Rajan, Ohio State University, Columbus, OH, USA (compound semiconductor devices) has stepped down from his Editor position.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Methods for Extracting the Temperature- and Power-Dependent Thermal
           Resistance for SiGe and III-V HBTs From DC Measurements: A Review and
           Comparison Across Technologies

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      Authors: Markus Müller;Vincenzo d’Alessandro;Sophia Falk;Christoph Weimer;Xiaodi Jin;Mario Krattenmacher;Pascal Kuthe;Martin Claus;Michael Schröter;
      Pages: 4064 - 4074
      Abstract: Many different methods have been proposed in the literature for the extraction of the thermal resistance of heterojunction bipolar transistors (HBTs). This review presents a detailed evaluation and discussion of several widely used methods. Special emphasis is put on a generalized analysis of the underlying assumptions, suitable operating point range, and necessary measurement effort of each method. The accuracy of each method is determined by applying it to data based on circuit simulations of advanced SiGe and III-V HBT technologies. Experimental data from those technologies are used to highlight practical issues. A guideline for the selection of the most suitable method in practice is also given.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • High Gain Pseudo-Inverter Based on Silicon-on-Insulator With Ambipolar
           Transport

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      Authors: Sherzod Khaydarov;Kai Xiao;Yajie Qin;Fanyu Liu;Jing Wan;
      Pages: 4075 - 4080
      Abstract: The purpose of this article is to provide insight into ambipolar transport properties of the CMOS-like pseudo-inverter ( $Psi $ -inverter) in silicon-on-insulator (SOI) substrate. The $Psi $ -inverter demonstrated in this work simply uses three probes instead of metal contact. The channel is controlled by the bottom gate and shows ambipolar conduction. The ambipolar voltage transfer characteristics (VTC) from the Si thin-film layer of the SOI device is extracted. The $Psi $ -inverter operates both in the first and third quadrants, achieving remarkable gains as high as 25.8 and 936.1 at drain voltages ${V}_{{mathrm {DD}}}$ = 3 and 7 V, respectively. Moreover, TCAD simulated results are approximated to the experimental data considering top Si interface traps to reveal the electrostatic potential and carrier concentration profiles. Exceptionally sensitive surface properties and high gain of the $Psi $ -inverter demonstrated in our work enable it a promising candidate for sensor applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Novel Design of a Ternary-CMOS With Vertical-Channel Double-Gate
           Field-Effect Transistors

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      Authors: Jiho Kim;Sangwoo Kim;Jinyoung Hwang;
      Pages: 4081 - 4087
      Abstract: A tunneling-based ternary CMOS (T-CMOS) offering a low standby current and fast switching speed is developed using a novel device structure for field-effect transistors (FETs). In the new transistor devices, referred to as vertical-channel double-gate (VCDG)-FETs, a vertical current path from drain to source is formed on the drain, and a body placed below the drain is electrically isolated, except for the tunneling junction appearing at the drain and body interface. At the junction, most of the OFF-state current flows, which is independent of the gate voltage. Furthermore, the OFF-state current can be further reduced to the order of 10−17 A by employing a drain with a retrograded doping profile. In this profile, the channel–drain junction tunneling current, which varies with the gate voltage, is substantially suppressed to less than the body–drain junction tunneling current in the OFF state. In addition, an electrostatic channel controlled using double gates facilitates a small subthreshold swing (SSW) of 65 mV/dec. With p- and n-channel VCDG-FETs, a T-CMOS exhibiting three logic states is developed with a standby current on the order of 1 pA and transfer characteristics with a very narrow transition width.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at
           3-nm Technology Node: Impact of Unique Boosters

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      Authors: Krishna K. Bhuwalka;Hao Wu;Wenbo Zhao;Gerhard Rzepa;Oskar Baumgartner;Francis Benistant;Yijian Chen;Changze Liu;
      Pages: 4088 - 4094
      Abstract: Using a full design-technology cooptimization (DTCO) framework, we benchmark gate-all-around (GAA) nanosheet (NS) FETs against FinFETs at 3-nm logic technology relevant dimensions. First, to understand the intrinsic gain from NS, both device architectures are simulated using fixed technology ground rules [contact poly pitch (CPP), metal pitch ${M}_{x}$ , and cell height] and process assumptions (PAs), including stress, doping, junctions, and oxide thickness. Full geometry optimization along the CPP direction (gate length ${L}_{text {G}}$ , spacer thickness ${T}_{text {SP}}$ , and contact length ${L}_{text {CNT}}$ ) is done to self-consistently account for tradeoff between short-channel effects (SCE), intrinsic and extrinsic resistances, and capacitances (device and parasitic). This leads to independent optimum design specifications for each Fin and NS architectures. Impact of Fin tapering and NS width and stack number are further investigated, showing additional design flexibility of GAA NS devices at scaled dimensions.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Scalable Substrate Current Model for LDMOS Transistors Based on Internal
           Drain Voltage

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      Authors: Kumari Neeraj Kaushal;Virender Dan;Nihar R. Mohapatra;
      Pages: 4095 - 4101
      Abstract: In this work, a scalable robust substrate current model for laterally diffused MOS (LDMOS) transistors is presented. The model is created in two stages. First, a model for intrinsic drain voltage, which accurately captures the modulation of intrinsic drain voltage with applied gate and drain voltages, is developed. This model is then used to derive an expression for the substrate current. The accuracy of the substrate current model is verified by comparing it with the data measured from LDMOS transistors with different device dimensions. The model accurately captures the modulation of substrate current with bias voltages and shows excellent scalability. Different LDMOS designs are also suggested to reduce the substrate current at the same OFF-state breakdown voltage.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Co-Optimization Between Static and Switching Characteristics of LDMOS With
           p-Type Trapezoidal Gate Embedded in Drift Region

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      Authors: Zhangjun Shi;Xiaojin Li;Yabin Sun;Bo Zhang;Yanling Shi;
      Pages: 4102 - 4108
      Abstract: In this article, a novel p-type trapezoidal gate (PTG) lateral double-diffused MOSFET (LDMOS) is proposed and investigated by the 3-D TCAD simulation. The results reveal that the PTG LDMOS boasts a reduced gate-to-drain charge ( ${Q}_{text {GD}}$ ) while maintaining an acceptable breakdown voltage (BV) and specific ON-resistance ( ${R}_{ text{ON},text {sp}}$ ). Compared with conventional LDMOS, a better tradeoff between the static figure of merit (FOMS, FOM $_{text {S}},,=$ BV2/ ${R}_{ text{ON},text {sp}}$ ) and the dynamic figure of merit (FOMD, FOM $_{text {D}} = {R}_{ text{ON},text {sp}} cdot {Q}_{text {GD}}$ ) is realized. In the ON-state, the p-type polysilicon gate embedded in the drift region induces multiple plane majority-carrier accumulation layers, leading to a decrease in ${R}_{ text{ON},text {sp}}$ . In the OFF-state, the metal–insulator–semiconductor (MIS) capacitor, which is composed of extended trench gate, gradual trapezoidal oxide, and N-drift. assists in depleting the drift region. Therefore, the doping concentration of drift region can be significantly lifted, and the BV is increased. Besides, the p-n junction capacitor composed of p-type and n-type polysilicon isolates the field coupling between gate and drain, and the gate-to-drain capacitor ( ${C}_{text {GD}}$ ) is thus reduced. Compared with multiple-plane electron accumulation layer LDMOS (MAL LDMOS) and split tripl--gate LDMOS (STG-LDMOS), ${Q}_{text {GD}}$ and ${R}_{ mathrm{scriptscriptstyle ON},text {sp}}$ of our proposed PTG LDMOS are shrunk by 34.3% and 54.4%, respectively. In general, the proposed PTG LDMOS achieves a better tradeoff between the static and switching characteristics.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Leakage Optimization of the Buried Oxide Substrate of Nanosheet
           Field-Effect Transistors

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      Authors: Songkil Yoo;Soyoung Kim;
      Pages: 4109 - 4114
      Abstract: In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet field-effect transistors (NSFETs) by locally inserting an oxide material only under the gate region. NSFETs with punchthrough stoppers (PTSs) doping of the substrate region have been widely adopted to reduce substrate leakage; however, band-to-band tunneling (BTBT) under negative bias remains a serious problem in such devices. By only inserting the oxide material under the gate region, the electric field from the gate to the drain–substrate junction is dispersed. Furthermore, since there is no oxide material under the source and drain (S/D) region, there is no stress reduction along the channel direction coming from the silicon-on-insulator (SOI) structure. We performed technology computer-aided design (TCAD) simulations, and the results show that the proposed structure effectively reduces both the tunneling current in the NSFET with PTS structure and the OFF-current in the NSFET without PTS structure, compared with those of conventional NSFETs.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm
           Technology Node

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      Authors: V. Bharath Sreenivasulu;Vadthiya Narendar;
      Pages: 4115 - 4122
      Abstract: In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and nanosheet (NS) FETs performance are estimated with equal effective channel widths ( ${W}_{eff}$ ) at the 5-nm technology node (N5). The comparison reveals that NS FET exhibits the highest ON current ( ${I}_{ mathrm{scriptscriptstyle ON}}$ ), the lowest OFF current ( ${I}_{ mathrm{scriptscriptstyle OFF}}$ ), and the largest ${I}_{ mathrm{scriptscriptstyle ON}}/{I}_{ mathrm{scriptscriptstyle OFF}}$ ratio with better subthreshold performance. We also explore the geometrical variation of the NS FET toward better dc and analog/RF applications and outlined the necessary design guidelines. Moreover, the robustness of NS FET for temperature variations is also performed and analyzed. Finally, the effect of NS width ( $text{NS}_{W}$ ) on common source (CS) amplifier, CMOS inverter, and ring oscillator circuits is performed by the Verilog-A model in the CADENCE simulator. An increment of 45.11% in oscillation frequency ( $f_{osc}$ ), 155.5% rise in CS amplifier gain, $2.5times $ increment in energy-delay product (EDP), and marginal reduction in inverter noise margin (NM) is noticed with larger $text{NS}_{W}$ . From the result analysis, it is noticed that for sub-5-nm technological nodes, NS FETs exhibit superior performance and ensure fundamental scaling.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Self-Heating Mitigation of TreeFETs by Interbridges

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      Authors: Chia-Jung Tsen;Chia-Che Chung;C. W. Liu;
      Pages: 4123 - 4128
      Abstract: Adding interbridges (IBs) as additional channels between nanosheets (NSs) can reduce not only the maximum temperature in local hotspot of device but also the junction temperature difference among channels. The Si0.98Ge0.02 IBs added into pSi NSs reduce the maximum device temperature by 9 °C and the maximum junction temperature difference among channels by 5 °C. This is attributed to the higher thermal conductivity of IBs than internal spacer (7 versus 2 W/K/m) to increase heat exchange between NSs. Further increasing the width of Si0.98Ge0.02 IBs from 5 to 10 nm can cause 14 °C reduction in the maximum device temperature and 6 °C reduction in the junction temperature difference due to 1.1X enhancement of heat exchange between NSs. Increasing the height of Si0.98Ge0.02 IBs from 20 to 30 nm can reduce the maximum device temperature by 22 °C but slightly increase the junction temperature difference by 1 °C due to 30% decrease in the heat exchange between NSs.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Investigation of Self-Heating Effects in UTBB FD-SOI MOSFETs by a Modified
           Thermal Conductivity Model

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      Authors: Qian Xing;Yali Su;Junhua Lai;Bo Li;Binghong Li;Jianhui Bu;Guohe Zhang;
      Pages: 4129 - 4137
      Abstract: In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS).
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Temperature-Dependent Characteristics and Electrostatic Threshold Voltage
           Tuning of Accumulated Body MOSFETs

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      Authors: A. B. M. Hasan Talukder;Brittany Smith;Mustafa Akbulut;Faruk Dirisaglik;Helena Silva;Ali Gokirmak;
      Pages: 4138 - 4143
      Abstract: Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing ( ${V}_{text {side}}$ ). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage ( ${V}_{t}$ ) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm $times $ 78 nm (width $times $ length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and ${V}_{t}$ increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. ${V}_{t}$ can be adjusted from ~0.3 to ~1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using ${V}_{text {side}}$ . This high level of tunability allows electronic control of ${V}_{t}$ and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Normally-Off Oxidized Si-Terminated (111) Diamond MOSFETs via ALD-Al2O3
           Gate Insulator With Drain Current Density Over 300 mA/mm

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      Authors: Yu Fu;Yuhao Chang;Xiaohua Zhu;Ruimin Xu;Yuehang Xu;Hiroshi Kawarada;
      Pages: 4144 - 4152
      Abstract: A novel method to fabricate the oxidized silicon-terminated (C–Si–O) diamond metal-oxide-semi-conductor field-effect transistors (MOSFETs) by replacing the retained SiO $_{text{2}}$ masks with an atomic layer deposition (ALD)-Al $_{text{2}}$ O $_{text{3}}$ film as the main gate insulator was proposed for the first time. Compositional analysis across the SiO $_{text{2}}$ masks and on the air-exposed C–Si–O (111) diamond surface has been carried out by utilizing secondary ion mass spectroscopy (SIMS) and Auger electron spectroscopy (AES) techniques, respectively. Furthermore, we revealed that, under selectively epitaxial growth of diamond through a SiO $_{text{2}}$ mask, a carbon-rich film was formed on SiO $_{text{2}}$ and C–Si bonding was realized at the SiO $_{text{2}}$ /(111) diamond interface. The fabricated device with a source and drain distance ( $textit{L}_{text{SD}}$ ) of 3 $mu $ m exhibits a distinct threshold voltage ( $textit{V}_{text{TH}}$ ) of $-$ 5.6 V and a maximum drain current density ( $textit{I}_{textit{D}_text{MAX}}$ ) up to $-$ 311 mA/mm, which is a record value among normally-off single-crystalline diamond MOSFETs to date. In the case of having ALD-Al $_{text{2}}$ O $_{text{3}}$ as the main gate insulator, normally-off operation of the C–Si–O diamond MOSFETs has a stark contrast with the typically normally-on performance of the hydrogen-terminated (C–H) diamond MOSFETs, which is mainly due to the smaller negative electron affinity of C–Si–O diamond compared with that of C–H diamond. These results indicate that the proposed C–Si–O (111) diamond MOSFETs with excellent normally-off operation and large drain current density are promising to fulfill the requirements of fail-safe and current drive capabilities in power device applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Potential Enhancement of fT and gₘfT /ID via the Use of NCFETs to
           Mitigate the Impact of Extrinsic Parasitics

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      Authors: Ji Kai Wang;Collin VanEssen;Thomas Cam;Keith Ferrer;Zhi Cheng Yuan;Prasad S. Gudem;Diego Kienle;Mani Vaidyanathan;
      Pages: 4153 - 4161
      Abstract: The potential for negative-capacitance field-effect transistors (NCFETs) to enhance the unity-current-gain cutoff frequency ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ ratio through a technique that mitigates the impacts of extrinsic parasitic capacitances is investigated, where ${g}_{m}$ is the transconductance and ${I}_{D}$ is the dc drain current and where “extrinsic” refers to elements arising outside an “intrinsic” or core transistor structure. We explain the technique and show that NCFETs can provide significant gains in extrinsic ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ from this mitigation effect. However, an inherent degradation of intrinsic ${f}_{T}$ needs to be addressed to maximize these benefits, and this degradation can be alleviated through channel-length scaling as well as supply- and threshold-voltage tuning. The relative influences of different extrinsic parasitic elements are also evaluated, and it is found that improvements to ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ increase as extrinsic parasitic capacitance increases and decrease as extrinsic parasitic resistance increases. Overall, this work finds that NCFET structures are promising candidates to mitigate the impacts of extrinsic parasitics in aggressively scaled transistors for th- next-generation RF applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • GaN on Engineered Bulk Si (GaN-on-EBUS) Substrate for Monolithic
           Integration of High-/Low-Side Switches in Bridge Circuits

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      Authors: Gang Lyu;Jin Wei;Wenjie Song;Zheyang Zheng;Li Zhang;Jie Zhang;Sirui Feng;Kevin J. Chen;
      Pages: 4162 - 4169
      Abstract: A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • The DC Performance and RF Characteristics of GaN-Based HEMTs Improvement
           Using Graded AlGaN Back Barrier and Fe/C Co-Doped Buffer

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      Authors: Ling Yang;Bin Hou;Fuchun Jia;Meng Zhang;Mei Wu;Xuerui Niu;Hao Lu;Chunzhou Shi;Minhan Mi;Qing Zhu;Yang Lu;Xiaohua Ma;Yue Hao;
      Pages: 4170 - 4174
      Abstract: In this article, the impact of the graded AlGaN back barrier and FeC co-doping buffer structure on the AlGaN $/$ GaN high electron mobility transistors (HEMTs) is proposed and systematically investigated. Due to effective suppression of Fe tail in unintentionally doped GaN (uid-GaN) layer by the insertion of the thick graded AlGaN back barrier layer, a large maximum drain current density and a transconductance peak are achieved. Meanwhile, the breakdown voltage is significantly improved by the use of FeC co-doping GaN buffer design. More importantly, it is revealed that the graded-AlGaN design can reduce the range and intensity of the electrical potential distribution in uid-GaN layer and then effectively suppress the acceptor-induced trappingdetrapping effect under high drain voltage. The RF small-signal performance of Fe-doped GaN (GaN:Fe)C co-doping buffer HEMT exhibits significant improvement. In addition, load-pull measurement at 8 GHz revealed that a saturation power increases from 38.04 to 41.07 dB, a power gain increases from 9.06 to 10.58 dB, and an associate power-added-efficiency (PAE) increased from 40.27% to 50.18%. Our proposed GaN-based epitaxial structure can not only suppress the gate lag by reduce AlGaN surface electric field, but it can also suppress the drain lag by reduce the amplitude and range of potential distribution. It indicates that our proposed device has great potential for future high-voltage RF power amplifier application.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Monolithically Cointegrated Tensile Strained Germanium and InxGa1-xAs
           FinFETs for Tunable CMOS Logic

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      Authors: Rutwik Joshi;Sengunthar Karthikeyan;Mantu K. Hudait;
      Pages: 4175 - 4182
      Abstract: In this article, we have evaluated the merits of monolithically cointegrated alternate channel complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile strained germanium ( $boldsymbol {varepsilon }$ -Ge) for the p-channel FinFET and variable indium (In) compositional InxGa1-xAs ( $0.10le {x} le0.53$ ) for the n- channel FinFET. The device simulation models were calibrated using the experimental results of Ge and InGaAs FinFETs and subsequently transferred to the cointegrated Ge and InxGa1-x As structure while keeping the device simulation parameters fixed. The device parameters, such as ${V}_{text {T}}$ , ${I}_{text {on}}$ , ${I}_{text {off}}$ , and subthreshold-swing (SS), were determined for identical fin dimensions for n- and p-channel FinFETs as a function of In composition that alters the tensile strain in Ge. These parameters are controllable during the heteroepitaxial growth by varying In composition in InxGa1-xAs. $boldsymbol {varepsilon }$ -Ge p-FinFET is shown to be superior in terms of SS and ${I}_{text {on}}/{I}_{text {off}}$ ratio compared with other competing architectures. The cointegrated architecture of CMOS inverter exhibited an optimum performance over a range of In compositions from 20% to 40% while driving fa--out fan-out 1 (FO-1) and FO-4 load configurations. In addition, the CMOS inverter with symmetric rise and fall times as well as noise-immune functionality demonstrated 150 GHz of operating frequency with 30-nW total power dissipation at 20% In composition, and hence a superior power-delay-product comparable with International Technology Roadmap for Semiconductors (ITRS) standards. Moreover, the three-stage CMOS ring oscillator performance was evaluated with various In compositions to be stable and power efficient. Thus, the cointegrated approach has a potential to: 1) simplify large-scale CMOS integration and 2) be compatible with optoelectronic materials.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Electrical Characteristics of In0.53Ga0.47As Gate-All-Around MOSFETs With
           Different Nanowire Shapes

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      Authors: Hua-Lun Ko;Quang Ho Luc;Ping Huang;Si-Meng Chen;Jing-Yuan Wu;Nhan-Ai Tran;Edward Yi Chang;
      Pages: 4183 - 4187
      Abstract: In this article, we investigate the electrical properties of In0.53Ga0.47As gate-all-around (GAA) MOSFETs with different nanowire shapes. InGaAs GAA MOSFETs with trapezoid and triangle nanowire shapes have been fabricated and characterized. Improved output performance was observed as the nanowire top width reduces from 20 to 11 nm. It was found that the electrical characteristics degraded as the nanowire top width was decreased to nearly 0 nm. To explain the carrier transport mechanism in ultralow-scale devices, TCAD simulation has been performed to study the electron density distribution for different nanowire widths and explain the transport mechanism in these ultralow-scale transistor devices.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • High-Performance AlGaN/GaN HEMTs With Hybrid Schottky–Ohmic Drain for
           Ka-Band Applications

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      Authors: Jielong Liu;Minhan Mi;Jiejie Zhu;Pengfei Wang;Yuwei Zhou;Siyu Liu;Qing Zhu;Meng Zhang;Bin Hou;Hong Wang;Ling Yang;Xiaohua Ma;Yue Hao;
      Pages: 4188 - 4193
      Abstract: A hybrid Schottky–ohmic drain technology for millimeter-wave (mmW) AlGaN/GaN high-electron-mobility transistors (HEMTs) is proposed. The Schottky metal extension in the ohmic region of drain reduces the actual source–drain spacing, resulting in a smaller ON-resistance and a higher maximum current. Extended Schottky metal in the drain region modulates the electric-field distribution, thereby leading to an improved breakdown voltage, suppressed current collapse, and high reliability. Compared with the ohmic drain, the current gain cutoff frequency ( ${f}_{T}$ ) was improved from 64 to 76 GHz, and the maximum oscillation frequency ( ${f}_{text {max}}$ ) was improved from 125 to 157 GHz, resulting from the decreased parasitic drain resistance ( ${R}_{d}$ ). Moreover, large-signal measurements in continuous wave (CW) at 30 GHz demonstrated a peak power-added efficiency (PAE) of 45.5% and a saturated output power density ( ${P}_{text {sat}}$ ) of 8.5 W/mm at ${V}_{text {ds}}= {30}$ V. In addition, the direct current (DC) and radio frequency (RF) characteristics showed a negligible degradation after large-signal measurements at 30 GHz.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Amplifier Based on 4H-SiC MOSFET Operation at 500 °C for Harsh
           Environment Applications

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      Authors: Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki;
      Pages: 4194 - 4199
      Abstract: Successful operation of 4H-silicon carbide (SiC) MOSFET and integrated electronic circuit based on 4H-SiC MOSFET is reported at temperature up to $500~^{circ }text{C}$ in air. The high-temperature operation of the integrated circuit (IC) based on 4H-SiC MOSFET strongly depends on the reliability of metal/SiC contact. Based on the transfer length method (TLM), the Ni/Nb/n-type 4H-SiC junction exhibits ohmic behavior with specific contact resistance of $1.86times 10^{-{4}},, Omega cdot $ cm2 when operating at $500~^{circ }text{C}$ . In contrast, the voltage gain of the amplifier is strongly governed by the variation of carrier mobility of the 4H-SiC MOSFET when temperature varies from room temperature to $500~^{circ }text{C}$ . The experimental results show that, when the temperature is increased from $20~^{circ }text{C}$ to $300~^{circ }text{C}$ , the amplifier gain of the IC increased from 23.8 to 153.0. Though the voltage gain decreases when the temperature increases above $300~^{circ }text{C}$ , it is still higher than 50 at $500~^{circ }text{C}$ . These results indicate that integrated electronic circuits based on this 4H-SiC MOSFET technology could be potentially used for harsh environment applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Fabrication and Characterization of a Novel Varistor Based on AlInGaN/GaN
           Heterojunction Epitaxy on High Resistance Silicon (111) Substrates

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      Authors: He Guan;Liyi He;Jingbo Wu;Ziqiang Zeng;Yunshuo Li;Borui Deng;Guiyu Shen;Wentao Li;Yucheng Wang;
      Pages: 4200 - 4205
      Abstract: A high-resistance Si-based AlInGaN/GaN heterojunction epitaxy specifying AlN/AlGaN laminated buffer layers and AlInGaN barrier layer with 45% Al composition was successfully produced to show a high electron density of $1.93times10$ 13 cm−2 and mobility of 2829.24 cm2/Vs and based on which a novel varistor is proposed in this work. The varistor is composed with a narrow groove etched into the GaN channel and Ti/Al/Ni/Au (20/130/50/50 nm) metal electrodes attached to the epitaxy surface. The processes to fabricate the varistor were investigated in-depth, including a narrow groove etching based on dry-wet hybrid cyclic etching technology employing oxygen plasma and hydrochloric acid and an optimized metal electrodes ohmic contact process based on HCl:H2O = 1:10 liquid surface treatment and annealing at 875 °C to achieve a low contact resistance of $0.45 Omega cdot $ mm. The device with a groove width of $3 ~mu text{m}$ and length of $600 ~mu text{m}$ exhibits typical varistor characteristics with opening voltage ( $V_{{mathrm {ON}}}$ ) of 33.8 V and a high nonlinear coefficient of 82.97 in the current range from 1 to 10 mA. The $V_{{mathrm {ON}}}$ value of the varistors is directly proportional to the narrow groove width with a scaling coefficient of 10.18 V/ $mu text{m}$ , which means $V_{{mathrm {-N}}}$ can be adjusted by altering the width of the groove. The varistor with a simple structure could be used in GaN on-chip integrated switches, electro-static discharge (ESD) protection, and other applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Study on the Impact of Dislocation Density on Leakage Current in
           Vertical GaN-on-GaN p-n Diodes

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      Authors: Siwei Li;Burcu Ercan;Chenhao Ren;Hirotaka Ikeda;Srabanti Chowdhury;
      Pages: 4206 - 4211
      Abstract: The impact of dislocation density on off-state leakage current in avalanche-capable gallium nitride (GaN)-on-GaN vertical p-n diodes is experimentally demonstrated and studied. At first, the presence of avalanche breakdown was confirmed on p-n diodes grown on bulk GaN substrates with dislocation density ranging from 1e4 to 1e6 cm−2. The impact of dislocation density on off-state leakage current was then compared and analyzed on devices with confirmed stable avalanche behavior. The devices in the 1e6-cm−2 region show higher leakage current and a more variable-range-hopping-dominated leakage process, while the Poole–Frenkel effect starts showing more influence on the devices in the 1e4-cm−2 region, especially under medium and high average electric field beyond 1.0 MV $cdot $ cm−1.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Au-Free AlGaN/GaN HEMT on Flexible Kapton Substrate

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      Authors: S Niranjan;R. Muralidharan;Prosenjit Sen;Digbijoy N. Nath;
      Pages: 4212 - 4217
      Abstract: In this article, we report on the electrical performance of AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using gold (Au)-free process, after being transferred onto flexible Kapton tape. The transfer process followed in this work can be easily scaled-up to wafer level and involves a relatively simple process of epoxy bonding of the thin device layer onto the Kapton substrate. Electrical characteristics of the flexible HEMT indicate 5%–10% higher ON-current when bent with a radius of curvature of 2.1 cm (at low drain bias voltages), while the OFF-state performance remains unaffected. Initially, 2-DEG properties such as field-effect mobility and carrier concentration have been extracted. While FATFET measurements indicate negligible change in field-effect mobility, ${C}$ – ${V}$ measurements indicate $sim 10$ % reduction in 2-DEG concentration after transfer. The comparison of the electrical characteristics of Au-free HEMTs indicates $sim 50$ % reduction in the ON-current of the transferred devices. This is attributed to heating of the transistor channel caused due to low thermal conductivity of the polymer Kapton tape. Electrical characteristics of the flexible HEMT carried out under drain pulsing further support the above observation. This work is among one of the few reports on Au-free AlGaN/GaN HEMT operation on flexible Kapton tape.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Analysis of Abnormal Current Rise Mechanism in GaN-MIS HEMT With
           Al2O3/Si3N4 Gate Insulator Under Hot Switching

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      Authors: Pei-Yu Wu;Xin-Ying Tsai;Ting-Chang Chang;Yu-Hsuan Yeh;Wei-Chen Huang;Kai-Chun Chang;Tsung-Ming Tsai;Jen-Wei Huang;
      Pages: 4218 - 4223
      Abstract: As a transmitter power amplifier (PA), the electrical output characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs) are closely related to the drain current versus drain voltage ( ${I}_{d}$ – ${V}_{d}$ ) characteristics. Any abnormalities in the ${I}_{d}$ – ${V}_{d}$ characteristics will seriously affect device performance. Therefore, many groups have investigated the kink effect of GaN HEMTs. One of the commonly used measurement methods of the kink effect is the ${I}_{d}$ – ${V}_{d}$ forward and reverse sweep. In this study, we used the same method for Al2O3/Si3N4–AlGaN/GaN metal–insulator–semiconductor HEMT (MIS HEMT) devices. We found that not only did the kink effect occurred but ${I}_{d}$ also increased abnormally during the reverse sweep and after a series of electrical measurements. At the end of the forward sweep, impact ionization caused by a high ${V}_{d}$ generated electron–hole pairs and some holes accumulated under the gate region, which caused the negative shift of the threshold voltage ( ${V}_{text{Th}}$ ), leading to an abnormal increase in ${I}_{d}$ during the reverse sweep.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Activating Thick Buried p-GaN for Device Applications

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      Authors: Yunwei Ma;Ming Xiao;Zhonghao Du;Lei Wang;Eric Carlson;Louis Guido;Han Wang;Lai Wang;Yi Luo;Yuhao Zhang;
      Pages: 4224 - 4230
      Abstract: Many emerging GaN electronic and optoelectronic devices comprise p-GaN layers buried below n-GaN or AlGaN. The activation of these buried p-GaN layers usually relies on the lateral hydrogen diffusion through the etched mesa sidewalls, which is known to induce nonuniform acceptor distributions. However, the acceptor profile, electric field ( ${E}$ -field) blocking capability, and leakage current mechanisms of the sidewall activated p-GaN layer have not been fully understood. This work addresses these knowledge gaps by fabricating vertical GaN p-n diodes with a thick ( $3.8~mu text{m}$ ) p-GaN. Two activation schemes were performed to allow the hydrogen diffusion through sidewalls and the top surface. For the sidewall activation, an analytical model was developed to depict the spatial distribution of the activated acceptor and the temporal evolution of this distribution with the increased annealing time. This model was validated using the ${C}$ – ${V}$ characteristics of the fabricated diodes with various radii. Under reverse biases, the breakdown ${E}$ -field and leakage current of the sidewall-activated diodes were found to be determined only by the edge area with the highest activation efficiency. The leakage mechanism agrees with the trap-assisted tunneling (TAT) model, and the peak junction ${E}$ -field can exceed 3 MV/cm, both being similar to those of surface-activated diodes. These results provide critical information for the design and processing of advanced GaN devices with the buried p-GaN.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Tunable and Reconfigurable Logic Gates With Electrolyte-Gated Transistor
           Array Co-Integrated With Neuromorphic Synapses

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      Authors: Ji-Man Yu;Chungryeol Lee;Joon-Kyu Han;Sang-Won Lee;Moon-Seok Kim;Sung Gap Im;Yang-Kyu Choi;
      Pages: 4231 - 4235
      Abstract: A tunable and reconfigurable logic gates based on an electrolyte-gated transistor (EGT) array are co-integrated with neuromorphic synapses. The tunable and reconfigurable operations of the various logic gates are controlled by analog conductance modulation with nonvolatility of the fabricated EGT. The EGT array was uniformly fabricated on an entire 4-in wafer with the aid of CMOS compatible processes. Initiated-chemical vapor deposition (i-CVD) method was adopted for the deposition of the ultrathin polyethylene glycol dimethacrylate (pEGDMA) electrolyte layer. Therefore, the logic gates could be co-integrated with synaptic devices on the same in-plane substrate for integrability. Basic inverter operation with switching threshold tunability ranging from −1 to +1 V was demonstrated with good operational stability. In addition, NAND and NOR gate operations were realized by modulating the conductance level of a specified cell in the array configuration.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • ReWORM Memory Effect in PET-Metal Fiber-Based Electroconductive Yarn

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      Authors: Suraj P. Khanna;Satish Singh;C. K. Suman;Nandan Kumar;
      Pages: 4236 - 4240
      Abstract: Write-once-read-many (WORM) memory effect is reported in the 19.68 Tex, 80:20 ratio polyethylene terephthalate (PET)-metal fiber spun electroconductive yarn. The yarn sample displayed a typical WORM memory behavior having electrical bistability with an OFF/ ON resistance ratio up to $10^{{9}}$ and a long retention period. As the polyester fibers transform from amorphous (resistive state) to semicrystalline (conductive state) upon the application of bias voltage, the charge conduction changes from electronic to ionic, above the glass transition temperature. Furthermore, ${I}-{V}$ curves were fit to explain the charge carrier transport mechanisms in the WORM behavior. Additionally, upon intentional mechanical perturbation, the sample could reset to its native high-resistive state (the phenomenon is termed as Reset WORM or ReWORM), ready for another WORM storage cycle.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Bi-Directional Long Short-Term Memory Neural Network Modeling of Data
           Retention Characterization in 3-D Triple-Level Cell NAND Flash Memory

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      Authors: Hyundong Jang;Chanyang Park;Kihoon Nam;Hyeok Yun;Kyeongrae Cho;Jun-Sik Yoon;Hyun-Chul Choi;Ho-Jung Kang;Min Sang Park;Jaesung Sim;Rock-Hyun Baek;
      Pages: 4241 - 4247
      Abstract: Data retention (a time-variant characteristic of 3-D- NAND flash memory) is predicted through a bi-directional long short-term memory (LSTM) neural network (NN) model that learns sequential data obtained from chip measurements of a triple-level cell (TLC). The predicted results for all time points of each program (PGM) state are accurately predicted by the threshold voltage ( ${V}_{text {th}}$ ) distribution. Thus, the predicted ${V}_{text {th}}$ can be used to analyze the cause of retention failure. When the ${V}_{text {th}}$ of the target cell is high or when that of the adjacent cell is small, the ${V}_{text {th}}$ loss of the target cell is large. In addition, the ${V}_{text {th}}$ loss increases as the ${V}_{text {th}}$ of the adjacent cell decreases. Using a fully calibrated TCAD simulation, we verify the NN-based ${V}_{text {th}}$ prediction by checking the change in the electron concentration in the nitride layer. Furthermore, the NN model predicts the ${V}_{text {th}}$ for cells existing in other blocks, showing that they are consistent with the measured ${V}_{text {th}}$ . The prediction times were 5 $times ,,10^{{5}}$ s, 5 $times ,,10^{{6}}$ s, and 2 $times ,,10^{{6}}$ s, but using machine learning (ML), we reduced the time required to predict the ${V}_{text {th}}$ to only 2 s. Therefore, the proposed ML method enables fast, accurate, and effective predictive modeling of the time-variant ${V}_{text {th}}$ of 3-D TLC NAND flash memory. Finally, the predicted ${V}_{text {th}}$ can be included in the read retry table or included in the lookup table of the compensation circuit in NAND solutions. This can save a significant amount of time that would otherwise be spent on actual long-term measurements.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Multilayered Sb-Rich GeSbTe Phase-Change Memory for Best Endurance and
           Reduced Variability

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      Authors: Giusy Lama;Mathieu Bernard;Guillaume Bourgeois;Julien Garrione;Valentina Meli;Niccolò Castellani;Chiara Sabbione;Lucie Prazakova;Diana-Stephany Fernandez Rodas;Emmanuel Nolot;Marie Claire Cyrille;François Andrieu;Gabriele Navarro;
      Pages: 4248 - 4253
      Abstract: Sb-rich GeSbTe-based phase-change memories (PCMs) were studied in the past years for their high switching speed to target storage class memory (SCM) applications. In this work, we show the advantages of an engineered multilayered Sb-rich GeSbTe stack compared with standard bulk reference materials. The studied multilayer-based PCM devices feature a lower programming current with respect to the equivalent bulk ones, preserving a high programming speed. Furthermore, multilayered Sb-rich GeSbTe brings better endurance performances for a wide programming current range and extremely reduced cycle-to-cycle (C2C) and device-to-device (D2D) variability along cycling verified in 4 kb PCM arrays. These results confirm improved yield and reliability obtained, thanks to multilayered PCM solution.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • The Impact of Thermal Enhance Layers on the Relaxation Effect in Analog
           RRAM

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      Authors: Yue Xi;Jianshi Tang;Bin Gao;Feng Xu;Xinyi Li;Yuyao Lu;He Qian;Huaqiang Wu;
      Pages: 4254 - 4258
      Abstract: Computing-in-memory (CIM) with analog resistive random access memory (RRAM) has recently shown great potential in building energy-efficient hardware for artificial intelligence (AI). However, the relaxation effect of analog RRAM featuring post-programming conductance drift has become a key performance-limiting factor. In this work, a comprehensive study of the relaxation effect is presented from the analysis of its causes to the strategy for device optimization as well as the impact on CIM applications. An application-oriented quantitative indicator (relative deviation [RD]) is proposed to fairly evaluate the relaxation effect of different devices. In particular, the influence of oxygen content in different thermal enhanced layers (TELs) on the relaxation and maximum conductance value ${G}_{max}$ of analog RRAM is studied. A theory of ternary oxide TEL is proposed to mitigate relaxation while maintaining low ${G}_{max}$ , which is experimentally validated by TaTiOx as TEL. Furthermore, neural network simulation is carried out to analyze the requirement for RRAM relaxation for CIM applications. This work provides a useful strategy for device optimization to suppress the relaxation effect by engineering the TEL.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Highly Compact Nonvolatile Ternary Content Addressable Memory (TCAM)
           With Ultralow Power and 200-ps Search Operation

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      Authors: Xianggao Wang;Yiming Qu;Fan Yang;Liang Zhao;Choonghyun Lee;Yi Zhao;
      Pages: 4259 - 4264
      Abstract: In this work, we developed a nonvolatile ternary content addressable memory (TCAM) with a cell size of $0.01~mu text{m}^{{2}}$ utilizing the Ge-based memory diode (MD), which has the most area-efficient TCAM design reported. The MDs have a high current ratio between ON and OFF states and a large rectifying ratio, showing the potential usage in large-dimension TCAM arrays. Besides, the functionality of parallel search was demonstrated with a 2-bit MD-TCAM array by experiment, and the electrical characterization showed expected results. With the help of the sub-ns ultrafast measurement system, it is confirmed that the search energy of MD-TCAM could reach as low as 1.0 fJ/bit/mismatch, and one search operation can be performed within 200 ps. Furthermore, the circuit-level simulation results verified that the MD-TCAM developed in this study shows good performance in 128-bit parallel searching, which is promising for the ultrafast and low-power data search applications in the coming IoT era.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Single Germanium MOSFET-Based Low Energy and Controllable Leaky
           Integrate-and-Fire Neuron for Spiking Neural Networks

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      Authors: Mudasir A. Khanday;Faisal Bashir;Farooq A. Khanday;
      Pages: 4265 - 4270
      Abstract: In this work, a single transistor based on germanium (Ge) is used to construct a leaky integrate-and-fire (LIF) neuron with significant improvement in energy efficiency, area efficiency, and reduction in cost. Using 2-D calibrated simulation, we validated that Ge-MOSFET LIF neuron is able to imitate the neuron behavior accurately. The Ge-MOSFET shows low breakdown voltage, high impact ionization coefficient, and sharp breakdown. All these factors are responsible for achieving low energy per spike and higher spiking current. The proposed Ge-MOSFET-based spiking LIF neuron needs only 8 pJ/spike of energy as compared to recently reported silicon-based silicon-on-insulator (SOI) MOSFET, which needs 45 pJ/spike of energy. The use of gate voltage makes Ge-MOSFET LIF neuron firing controllable, which can improve the energy efficiency of the spiking neural network (SNN) by inducing sparse action.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Effect of Nitrogen Doping on Elevated-Metal Metal-Oxide (EMMO) Thin-Film
           Transistors

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      Authors: Nannan Lv;Zening Wang;Mengjun Du;Huaisheng Wang;Dongli Zhang;Man Wong;Mingxiang Wang;
      Pages: 4271 - 4276
      Abstract: Nitrogen doping is introduced in elevated-metal metal-oxide (EMMO) thin-film transistors (TFTs) by sputtering amorphous indium gallium zinc oxide (a-IGZO) channel in Ar and N2 gas mixture. The electrical characteristic and reliability of TFTs under negative/positive bias illumination stress (N/PBIS) are systematically investigated on TFTs of different channel lengths ( ${L}text{s}$ ). Compared with undoped TFTs, the short-channel effect (SCE) of the N-doped TFTs is significantly suppressed, the persistent photoconductivity (PPC) effect is weakened, and N/PBIS reliability is largely improved. Short- and long-channel N-doped TFTs have about the same reliability performance. X-ray photoelectron spectroscopy (XPS) analysis shows that N-doping forms Zn=N bonds in the channel and oxygen vacancies ( ${V}_{O}$ ) are reduced. Based on a group of TFTs with different ${L}text{s}$ , channel mobility ( $mu _{{mathrm {ch}}}$ ) and source–drain series resistance ( ${R}_{{mathrm {sd}}}$ ) are correctly extracted. In N-doped TFTs, $mu _{{mathrm {ch}}}$ has a limited decrease owing to the increase in ${R}_{{mathrm {sd}}}$ . N-doped TFTs with different Ar/N2 gas-flow ratios show similar electrical and reliability performance, indicating a wide process window.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Improvement of Electrical Performance in Solution-Processed InZnO
           Thin-Film Transistor With a Radio Frequency O2 Triggered Multistacked
           Architecture

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      Authors: Fei Shan;Jae-Yun Lee;Hao-Zhou Sun;Han-Lin Zhao;Xiao-Lin Wang;Sung-Jin Kim;
      Pages: 4277 - 4282
      Abstract: A method for radio frequency oxygen (O2) plasma-assisted treatment of indium zinc oxide (IZO) films with a multistacked architecture fabricated by a low-temperature (200 °C) solution process is investigated. We demonstrate that radio frequency O2 plasma-assisted posttreatment technology can improve the mobility and stability of IZO thin-film transistors (TFTs). The activity layers were formed by spin coating and subsequently thermally annealed at a low temperature of 200 °C, followed by O2-plasma posttreatment process, to form the O2 triggered multistacked architecture. The TFT devices plasma-treated for 3 min exhibit improved electrical characteristics, with a mobility of 7.09 ± 0.24 cm2/Vs, an ON OFF ratio of (1.21 ± 1.22) $times 10^{{6}}$ , a threshold voltage of $-0.22,,pm ,,0.35$ V, and a subthreshold swing of 0.34 ± 0.02 V/dec. The improved results offered by the O2 plasma treatment led to a higher mobility and ON/ OFF ratio compared to sample device without this process. The successful fabrication of radio frequency O2 triggered multistacked architecture-based IZO TFTs showing the practical potential of high-performance low-temperature solution-processed preparation technology and radio frequency O2 plasma-assisted treatment for electrical device application.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Investigation on Stability in Solution-Processed In-Zn-Sn-O TFT Array
           Under Various Intensity of Illumination

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      Authors: Bin Jing;Cong Peng;Meng Xu;Huixue Huang;Xifeng Li;Jianhua Zhang;
      Pages: 4283 - 4287
      Abstract: The effect of light illumination intensity on the stability of In-Zn-Sn-O (IZTO) thin-film transistors (TFTs) array fabricated by solution processed is investigated. Comparison with positive bias stress, the light illumination suppresses the ${V}_{text {th}}$ shift under positive bias illumination stress because of the increase in the free electrons induced by the ionized oxygen vacancies in the IZTO channel layer, but transfer characteristics show two-stage degradation under negative bias illumination stress (NBIS). The hump phenomenon is induced after NBIS, and the light illumination intensity is higher, the hump phenomenon becomes more serious. The hump phenomenon is relevant to ionized oxygen vacancies, which act as shallow donor-like states near the conduction-band minimum in IZTO.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Abnormal Hump and Two-Step Degradation of Top Gate a-InGaZnO TFTs Under
           Positive Bias Stress

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      Authors: Bo-Shen Huang;Ting-Chang Chang;Mao-Chou Tai;Han-Yu Chang;Kuan-Ju Zhou;Li-Chuan Sun;Jen-Wei Huang;Ming-Chen Chen;Hui-Chun Huang;
      Pages: 4288 - 4292
      Abstract: In this study, the electrical characteristics of top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress (PBS) are investigated. Abnormal two-step degradation and hump effects are observed under PBS. When the self-aligned process is applied during the interlayer dielectric (ILD) deposition, $text{n}^{+}$ IGZO is formed by hydrogen doping to define the source and drain, which is accompanied by hydrogen diffusion not only into the channel to influence the initial electrical performance but also into the gate insulator (GI), which leads to the degradation under PBS. The diffusion distance in the length and width directions is calculated. Also, the differences in the diffusion distance in the width and length directions can be ascribed to the geometric structure of the top-gate a-IGZO TFTs. The hump occurs after PBS because of the impact of hydrogen diffusion in the width direction. The two-step degradation and its sequences can be ascribed to two mechanisms, including electron trapping and hydrogen diffusion.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Al2O3/HfO2 Bilayer Dielectric for Ambipolar SnO Thin-Film Transistors With
           Superior Operational Stability

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      Authors: Ruohao Hong;Qianlei Tian;Jun Lin;Liming Wang;Tong Bu;Hao Huang;Wenjing Qin;Lei Liao;Xuming Zou;
      Pages: 4293 - 4297
      Abstract: In the past few years, ambipolar tin monoxide (SnO) thin-film transistors (TFTs) have been widely studied because of ever-increasing demands for simplifying CMOS circuit and fabrication of more compact CMOS devices. However, in view of the serious decline in device performance upon gate-bias stress and environmental exposure, it is urgent to develop an effective passivation strategy for improving the operational stability of SnO TFTs. Here, aluminum oxide (Al2O3)/hafnium oxide (HfO2) bilayer dielectric is employed as a passivation layer for achieving ambipolar SnO TFTs with greatly enhanced operational stability, in which the Al2O3 dielectric is used to reduce the interfacial trap states, while HfO2 dielectric can prevent the diffusion of water/oxygen. Furthermore, a complementary-like inverter is presented by simply connecting two identical ambipolar SnO TFTs, which can be maintained in ambient condition for more than four months with a voltage gain exceeding 30. The capacity to synchronously achieve field-effect conversion, operational stability, as well as logic function in ambipolar SnO TFTs opens up a rational avenue to the realization of compact logic circuits.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Investigation of Modulation Bandwidth of InGaN Green Micro-LEDs by Varying
           Quantum Barrier Thickness

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      Authors: Zexing Yuan;Yanzhe Li;Xinyi Lu;Zhou Wang;Pengjiang Qiu;Xugao Cui;Pengfei Tian;Qi Wang;Guoyi Zhang;
      Pages: 4298 - 4305
      Abstract: InGaN-based micro light-emitting diodes (micro-LEDs) with 5, 10, and 13 nm quantum barrier (QB) thickness were fabricated by metal-organic chemical vapor deposition (MOCVD) to investigate the influence of quantum-confined Stark effect (QCSE) on modulation bandwidth and luminous performance of devices. The room-temperature photoluminescence (PL), low-temperature time-resolved PL (TRPL), and electroluminescence (EL) results show that the decrease of QB thickness is beneficial to reduce QCSE of the device. The thinner QB thickness is good for improving the modulation bandwidth because the thinner QB is more beneficial to increase the total carrier recombination rate, but it is not conducive to the improvement of external quantum efficiency (EQE) due to degraded crystal quality. In addition, the modulation bandwidth of the device was calculated by using ABC model in combination with simulation. The calculation is in good agreement with the measured value. What is more, an optical link using an orthogonal-frequency division multiplexing (OFDM) modulation scheme was demonstrated. The transmission data rate increases with the increase of QB thickness from 1.309 to 1.773 Gbps, even though the modulation bandwidth decreases from 245 to 169 MHz. This work provides a way to balance the quantum efficiency and communication performance of green micro-LEDs.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A New Analog PWM Pixel Circuit With Metal Oxide TFTs for Micro-LED
           Displays

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      Authors: Pei-An Zou;Yan-Gang Xu;Chun Liu;Li-Rong Zhang;Jin-Hui Zhang;Yi-Kai Yuan;Wei Cai;Shao-Hu Han;Lei Zhou;Miao Xu;Lei Wang;Wei-Jing Wu;Jun-Biao Peng;
      Pages: 4306 - 4311
      Abstract: This article presents a new uncompensated analog pulsewidth modulation (PWM) pixel circuit employing pull-up control for micro-light-emitting diode (LED) display. The time of emitting light for the micro-LED working at the constant current is modulated by the analog data voltage. A compensated pixel circuit is also further developed to improve the display uniformity by compensating the threshold voltage shift of PWM thin-film transistor (TFT) and driving TFT. Based on the back-channel etch (BCE) metal oxide TFTs process, $16times $ GGG $times29$ LED array with the uncompensated pixel circuit and 16 $times {G},,times15$ LED array with the compensated pixel circuit are simultaneously fabricated on the same glass substrate. Compared with the uncompensated pixel circuit array, the display uniformity of the compensated pixel circuit array is improved from 74% to 88%.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Heterosynapse-Inspired Photodetector for Spatiotemporal Feature Fusion

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      Authors: Wen Du;Caihong Li;Yuxuan Hu;Yisen Yao;Yixuan Huang;Jihua Zou;Hao Xu;Jiang Wu;Zhiming Wang;
      Pages: 4312 - 4316
      Abstract: The increasing amount of data puts enormous pressure on data center. Therefore, the edge visual system is required to extract and process information more efficiently. Despite the development of neuromorphic visual systems, it has remained a challenge to process spatiotemporal information in the hardware-implemented visual system. Here, a heterosynapse-inspired photodetector is proposed for the intelligent edge visual system to process spatiotemporal information. The persistent photoconductivity (PPC) effect enables the photodetector to process temporal information, and the heterosynapse-inspired structure allows the visual system based on this photodetector to deal with spatial patterns. The proposed bionic photodetector provides a strategy for spatiotemporal feature fusion, which enables the target with spatiotemporal features recognized by the classifier composed of voltage comparators. Moreover, it is demonstrated that the visual system based on this design is able to conduct spatiotemporal pattern recognition and motion direction recognition tasks. This design within pixels paves a novel route for the intelligent edge visual system to extract, fuse, and recognize spatiotemporal information.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Size-Dependent Metal-Embedded Packaging for Performance Enhancement in
           Quantum-Dot-Converted Light-Emitting Diodes

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      Authors: Chung-Ping Huang;Guan-Teng Lin;Jhen-Jia Yang;Chien-Chung Lin;
      Pages: 4317 - 4324
      Abstract: A colloidal quantum dot (CQD) package with convex-surface solder reflectors of various diameters exhibited more favorable thermal characteristics and optical reliability performance than did the traditional in-chip package. The results indicated that solder balls provided a direct cooling path on the top of the LED chip to accelerate heat dissipation, and blue photons were reflected by the ball surfaces to enhance their recycling. The areal temperature results decreased from 88.4 °C (in-chip) to < 70 °C (solder ball) at a current of 180 mA. By contrast, continuous aging tests indicated that the devices with metal structures exhibited lifetimes four to six times longer than that of the in-chip device. The metal embedded structures not only provided a relatively low operating temperature but also extended the operating time of the packaged CQDs. This study pushes the envelope in the endeavor to integrate high-thermal-conductivity components into quantum dot photonic devices.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Avalanche Multiplication Image Sensor Bonded With Crystalline Se
           Photoconversion Layer Using Se–Se Bonding Process

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      Authors: Keitada Mineo;Shigeyuki Imura;Kazunori Miyakawa;Toshiki Arai;Satoshi Aihara;Mutsumi Sugiyama;Masakazu Nanba;
      Pages: 4325 - 4330
      Abstract: We have developed a bonded CMOS image sensor using a gallium oxide (Ga2O3)/polycrystalline selenium (c-Se)/nickel oxide photodiode and a Se–Se bonding process. These photodiodes can amplify the signal by avalanche amplification when a high electric field is applied, thus realizing a high-sensitivity image sensor. The Se–Se bonding process has many advantages, including the ability to handle high-temperature processing, no sputtering damage to the p-n junction interface, and no need for high-precision alignment. In this study, we have shown that the application of a high-temperature process to crystallize Ga2O3 improves the orientation of the c-Se, which is the photosensitive layer, and reduces the dark current. In addition, the Se–Se bonding process reduces the sputtering damage at the Ga2O3/c-Se interface, improving film quality. By applying the developed bonding process, we successfully realized a high-sensitivity CMOS image sensor with a threefold increase in magnification.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Graphene/GaAs Schottky Junction Near-Infrared Photodetector With a MoS2
           Quantum Dots Absorption Layer

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      Authors: Jiaqi Qu;Jun Chen;
      Pages: 4331 - 4336
      Abstract: MoS2, as a new generation of 2-D materials after graphene, shows excellent properties and has attracted extensive attention. More importantly, it can be combined with graphene devices to improve their performance. In this work, a MoS2/graphene/GaAs Schottky junction near-infrared (NIR) photodetector is investigated. A MoS2 quantum dot (QD) absorption layer is added on the traditional graphene/GaAs structure, and the QDs are used to enhance the absorption rate of graphene for NIR light, thereby improving the device performance. In subsequent tests, it is found that the photodetector has a responsivity of 19.9 mA/W under the 808-nm incident light at zero bias, which is much higher than that of ordinary graphene/GaAs photodetectors. Furthermore, the detection rate of the device can reach $4.86times10$ 10 cm $cdot $ Hz $^{1/2}cdot text{W}$ −1, and the response/recovery times are 46.8 and $557 ~mu text{s}$ , respectively; it is also found that the response wavelengths of the device have been extended, and it has a certain response in the 1064-nm wavelength. The excellent performance of MoS2/graphene/GaAs structure indicates that it has good application prospects in the field of NIR photodetectors.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Effect of C₄₄H₃₀N₄O₄ Surface Modification on the Performance
           of Al0.6Ga0.4N MSM Photodetectors

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      Authors: Feng Xie;Yuhang Li;Yushen Liu;Xifeng Yang;Xiumei Zhang;Guofeng Yang;
      Pages: 4337 - 4341
      Abstract: The high defect density on the surface of AlGaN material with high Al composition limits its application in the field of solar-blind ultraviolet (UV) detection. In this work, a surface modification method for AlGaN has been proposed to enhance the performance of AlGaN metal–semiconductor–metal (MSM) solar-blind UV photodetectors (PDs). The 5,10,15,20-T(4-OH P)P (C44H30N4O4) organic molecules are chemically adsorbed on the surface of high-Al-content Al0.6Ga0.4N MSM PD, which can reduce the interface potential caused by material defects and increase the photogenerated carriers of the device. Compared with the control unmodified PD, the C44H30N4O4 modification method significantly increases the photocurrent and responsivity of the PD, which is beneficial to improve the optoelectronic performances of III-nitride-based PDs.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Performance of Topological Insulator (Sb2Te3)-Based Vertical Stacking
           Photodetector on n-Si Substrate

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      Authors: Sandeep Kumar Verma;Kavindra Kandpal;Pramod Kumar;Arun Kumar;Claudia Wiemer;
      Pages: 4342 - 4348
      Abstract: In this work, we report the photodetector properties of a vertically stacked heterostructure based on topological insulator Sb2Te3/n-Si. The high-quality Sb2Te3 thin films were grown on an n-Si substrate by the metal–organic chemical vapor deposition (MOCVD) technique. The fabricated Sb2Te3/n-Si heterostructure devices promise to work as an excellent rectification diode with an excellent rectification ratio (RR) (351.4 at ±3 V), under dark condition. The device shows remarkable photoresponse at a broad spectral near-infrared range of between 700 and 1100 nm. The maximum responsivity and detectivity of Sb2Te3/n-Si heterojunction diode 1600 mA/W and $7.48times10$ 10 Jones $vphantom {^{int }}$ (at +3 V) were observed at 900-nm wavelength of incident light. The electronic and optical properties of the Sb2Te3 are evaluated using first-principle calculations based on density functional theory (DFT). The bandgap of Sb2Te3 was found to be 0.12 eV. The optical properties of Sb2Te3 were calculated based on DFT and random phase approximation. The absorption coefficient shows that Sb2Te3 absorbed the light in a broadband spectral region and maximum absorption at 905 nm, which is in good agreement with the experimental results.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Efficiency and Reproducibility Enhancement in Perovskite Solar Cell With
           MoS₂ as Electron Transport Layer: A Computational Finding

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      Authors: Rushi Jani;Kshitij Bhargava;
      Pages: 4349 - 4354
      Abstract: The formamidinium lead triiodide (FAPbI3)-based perovskite solar cell (FPSC) is perceived as a potential replacement of conventionally exploited methylammonium lead triiodide (MAPbI3)-based PSC owing to its better stability. In this work, we explore the possibility of utilizing molybdenum disulfide (MoS2) as a prospective replacement of conventional titanium dioxide (TiO2) (requires high processing temperature) as an electron transport layer (ETL) in FPSC using SCAPS-1D. The results are quantitatively compared in terms of the performance metrics of simulated baseline models. Furthermore, the performance variations are also compared with respect to varying absorber layer defect density. Moreover, the reproducibility aspect of cells is compared with respect to varying carrier mobility of the absorber layer. We observe an outstanding improvement in efficiency and reproducibility of FPSCs with MoS2 as ETL. The results highlight the vitality of ETL material properties toward efficiency and reproducibility enhancement of FPSCs. These findings serve as an important benchmark for improving the commercialization prospects of FPSCs.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Enhancement of Photoresponsivity of β-In2S3/Si Broadband Photodetector by
           Decorating With Reduced-Graphene Oxide

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      Authors: Basanta Roul;Deependra Kumar Singh;Arun Malla Chowdhury;Malti Kumari;Kishan Lal Kumawat;K. K. Nanda;S. B. Krupanidhi;
      Pages: 4355 - 4361
      Abstract: Silicon-based conventional photodetectors have always been a vital part of many electronic and optoelectronic circuits because of their low fabrication cost, high device performance, and simple configuration. However, due to the relatively poor light–matter interaction and narrow bandgap in Si, these photodetectors generally suffer from a certain compromise in their photoresponsivity as well as broadband photoresponse. Here, a novel approach of coupling reduced-graphene oxide (rGO) decorated $beta $ -In2S3 with Si has been demonstrated. $beta $ -In2S3 thin film has been grown by a direct and transfer-free method on Si substrate and rGO has been drop-casted on $beta $ -In2S3. This introduction of a double-heterojunction architecture results in a photoresponsivity of ~30.41 A/W at 625 nm at an applied voltage of −4 V with the response and recovery times of 60 and $40 ~mu text{s}$ , respectively, along with a broadband response in the wavelength range of 400–1200 nm. The rGO acts as an efficient hole transporting layer, which readily reduces the recombination of the photogenerated electrons and holes, leading to high photoresponse. These results highlight a simple and cost-effective strategy to construct high-performance broadband photodetectors, which can be useful in future optoelectronic devices.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • High Detectivity of Metal–Semiconductor–Metal Ga2O3 Solar-Blind
           Photodetector Through Thickness-Regulated Gain

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      Authors: Zhiyao Zheng;Baoshi Qiao;Zhenzhong Zhang;Xiaoqian Huang;Xiuhua Xie;Binghui Li;Xing Chen;Kewei Liu;Lei Liu;Dezhen Shen;
      Pages: 4362 - 4365
      Abstract: Detectivity is the most key parameter in weak-signal photodetection, which depends on high photoresponse and low noise simultaneously. In this work, metal–semiconductor–metal solar-blind UV detectors with internal gain were fabricated based on high resistant and a certain oxygen vacancy density Ga2O3 thin films. Electrical measurements and electric field simulation indicated that thickening the active layer is helpful for high responsivity. The gain is dominated by the tunneling effect in high electric field under the electrodes. A high photoresponse of 371 A/W and a normalized detectivity up to $6.6times10$ 16 Jones were obtained.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Optical Crosstalk Among Mini-LEDs Packaged in a Four-in-One Integrated
           Matrix Device

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      Authors: Pei-Xin Zeng;Wei-Jie Guo;Chang-Dong Tong;Ren-Zhu Zhang;Li-Li Zheng;Guo-Long Chen;Ya-Yong Chen;Wei-Ping Zhu;Yu-Lin Gao;Yi-Jun Lu;Zhong Chen;
      Pages: 4366 - 4370
      Abstract: Optical crosstalk is of paramount importance in mini-light-emitting diode (mini-LED) displays. The influence of the current crowding of mini-LEDs on the optical crosstalk among neighboring pixels of a four-in-one integrated matrix device was determined. The results indicate that when a single mini-LED is powered on, the optical crosstalk decreases as the driving current increases due to the reduction in the ratio of photons emitted from the sidewalls of the mini-LED of interest. The encapsulation over mini-LEDs can enhance optical crosstalk due to the reduction of total reflection at the sidewalls and the effect of the light guide. Furthermore, optical crosstalk at the pixels in the direction perpendicular to the longer edge of the mini-LED of interest is stronger than that at the pixels in the direction perpendicular to the shorter edge. This work also suggests that comprehensive information about optical crosstalk can be obtained by capturing spatially resolved light emission from the upper surfaces of pixels.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • The α-In2Se3 THz Photodetector

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      Authors: Jing Chen;Fan Wu;Ping Li;Jianguo Hu;He Tian;Xiao-Ming Wu;Yi Yang;Tian-Ling Ren;
      Pages: 4371 - 4376
      Abstract: Terahertz (THz) photodetectors are widely used for applications related to security measurements and medicine due to their noninvasive properties; they are also used in the sixth-generation (6G) communication standard. High-performance THz photodetectors are in high demand; 2-D materials with intriguing ultrafast charge transport characteristics are promising candidates for preparing high-performance THz photodetectors. However, only graphene and black phosphorus (BP), which have a high carrier mobility, have been extensively used for fabricating THz photodetectors. THz photodetectors based on other 2-D materials are extremely rare. This work focuses on the 2-D material $alpha $ -In2Se3, which has a high carrier mobility, comparable to that of BP. An $alpha $ -In2Se3 transistor based on the plasma-wave-rectification effect was fabricated as a THz photodetector. The photocurrent of the $alpha $ -In2Se3 transistor under 0.12-THz illumination is smaller than that measured in dark conditions. Our THz photoresponse result is unusual compared with that of conventional THz devices. Two main factors contribute to this result. When the $alpha $ -In2Se3 transistor is under 0.12-THz illumination, first, a higher order recombination occurs, and the net carrier concentration then decreases; second, the carrier movement changes from being temperature-activated to being band-like transport, and the carrier mobility then decreases. Therefore, the photocurrent of the $alpha $ -In2Se3 transistor is smaller than the dark current. Furthermore, the $alpha $ -In2Se3 transistor has potential uses in memory applications due to the ferroelectricity of $alpha $ -In2Se3. Thus, the $alpha $ -In2Se3 transistor can be developed for use as an artificial photoinhibitory synaptic device in all-optical neural network simulations and low-energy-consumption THz photodetectors.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Light Efficiency Investigation of Ultraviolet Light-Emitting Diodes
           Combined With Polarized Emission and Packaging Structure

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      Authors: Renli Liang;Yang Peng;Yun Mou;Qiuquan Guo;Tao Hu;Xinzhong Wang;Jun Yang;
      Pages: 4377 - 4381
      Abstract: Ultraviolet light-emitting diodes (UV-LEDs) have attracted extensive applications in resin curing, medical treatment, biochemical inspection, and disinfection. However, the UV-LEDs suffer from the main bottleneck of low light efficiency, which depends on the polarized emission and packaging structure of UV-LEDs simultaneously. In this work, we investigated the light efficiency of UV-LEDs combined with polarized emission and packaging structure. Four types of UV-LEDs (UVC-A, UVC-B, UVB, and UVC) without a lens (UV-Ref.), with a flat lens (UV-FL), and with a hemispherical lens (UV-HL) were fabricated, respectively. Through investigating the light output power, far-field emission pattern, and electrical field intensity distribution of UV-LEDs, the UV-HL packaging structure displays the highest emission intensity and light output power in the whole UV band. Compared with the UVC-A-Ref. and UVC-A-FL structures, the enhancement ratios of the light output power of UVC-A-HL structure are 28.9% and 46.5%, respectively. Furthermore, the light extraction efficiency of the TM-polarized mode in the UVC-A-HL structure is enhanced by 29.6% compared with the UVC-A-Ref. structure. The results indicate that the light extraction of UV-LEDs is greatly affected by the polarized emission and packaging structure. Our work opens an efficient guidance to enhance the light efficiency of various UV-LEDs with appropriate packaging structure.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Fully Optical-Driving Ionotronic InGaZnO4 Phototransistor for Gate-Tunable
           Bidirectional Photofiltering and Visual Perception

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      Authors: Lijuan Gu;Yanran Li;Dingdong Xie;Jie Jiang;
      Pages: 4382 - 4385
      Abstract: Recently, fully optical-driving neuromorphic devices have attracted growing interest. However, the current device faces great challenges due to the lack of negative photoconductivity materials, which seriously hinders the further development of the visual perceptual applications using photosensitive device. Here, we propose an ionotronic neuromorphic InGaZnO4 phototransistor to establish a fully optical-driving artificial neural network. Optical neuronal paired-pulse facilitation can be switched to optical depression characteristics by tuning the gate bias more negatively through the ion-coupling bioelectrolyte. Moreover, the biological high-pass, low-pass, and band-stop photofilter behaviors can be successfully mimicked in such an all-in-one phototransistor. Finally, a fully optical-driving artificial neural network is constructed to perform artificial visual perception with an accuracy of ~90%. This device may open new avenues for the fascinating applications, such as artificial visual system, intelligent bionic robots, and smart photoelectric devices.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Pre-diagnosis of Failure Spots in Orange AlInGaP Light-Emitting Diodes
           Soaked in Liquid Nitrogen Using Machine Vision and Multiple Optical,
           Electrical, and Material Characterizations

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      Authors: Chyuan-Haur Kao;Yu-Chang Zang;Jia-Jie Jhang;Pin-En Chiu;Chun-Yen Yang;Hai-Wen Hsu;Yaw-Wen Kuo;Chia-Feng Lin;Ming-Yu Kuo;Yung-Hui Li;Ming-Hsien Li;Hsiang Chen;Jung Han;
      Pages: 4386 - 4391
      Abstract: In this study, Pre-diagnosis of degraded aluminum indium gallium phosphide (AlInGaP) light-emitting diodes (LEDs) that were soaked in liquid nitrogen (LN2) was performed. To visualize the early deterioration of LED emission, a combination of material, electrical, optical, and computer-aided machine-vision analysis of LED failure spots on the surface was examined. Results indicate that several small failure spots, which can be identified by the MATLAB processed emission images and surface roughness variation, can be found. Furthermore, LN2 soaking induced some local damages inside the device that penetrate the multiple-quantum well. The decrease of current and luminescence intensity also reflects the gradual degradation of the device after being soaked in LN2. This integrated analysis and Pre-diagnosis of the degraded device provided early screening of LED failure spots and real-time inspection during operations.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Mid-Wavelength InAs/InAsSb Superlattice Photodetector With Background
           Limited Performance Temperature Higher Than 160 K

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      Authors: Jianliang Huang;Shaolong Yan;Ting Xue;Yanhua Zhang;Wenquan Ma;
      Pages: 4392 - 4395
      Abstract: We report on a mid-wavelength (MW) type II superlattice (T2SL) photodetector using Ga-free InAs/InAsSb SL structure. X-ray diffraction (XRD) measurements indicate that the strained SL material is of very high quality. It is demonstrated that the background limited performance (BLIP) temperature of the detector is above 160 K and the dark current is dominated by the diffusion mechanism when temperature is above 160 K. At 77, 160, and 280 K, the 50% cutoff wavelength of the detector is 4.54, 4.89, and 5.56 $mu text{m}$ , respectively. The responsivity at the peak wavelength is 2.13 A/W at 77 K and is 2.16 A/W at 160 K. We also extract the Varshni parameters of the SL structure. The results indicate that the Ga-free SL structure is similar to InAs bulk material in terms of the Varshni parameters.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Pulsewidth Control of Nonlinear GaAs Photoconductive Semiconductor Switch

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      Authors: Wei Shi;Meilin Wu;Cheng Ma;Zhiyuan Chen;
      Pages: 4396 - 4400
      Abstract: The nonlinear gallium arsenide photoconductivity semiconductor switch (GaAs PCSS) can generate high-voltage and strong current electrical pulses with low light triggering at the order of microjoule. Due to the lock-on effect of the GaAs PCSS, the output pulsewidth is usually on the order of hundreds of nanoseconds or even tens of microseconds. This severely limits the application of nonlinear GaAs PCSS. This article presents the output pulsewidth modulation of nonlinear GaAs PCSS through the dual regulation of energy-storage capacitance and current-limiting resistance. When triggered by a pulse laser with a width of 10 ns and a single pulse energy of 200 $mu text{J}$ , the switch can output the minimum pulsewidth of 6.3 ns and the maximum pulsewidth of 196 ns. In the meantime, combined with the theoretical analysis of photon-activated charge domain (PACD), the electric field intensity of nonlinear GaAs PCSS is less than the threshold electric field of PACD, and the switch will be turned off quickly so that different pulsewidths can be output. The experimental results indicate that adding different current-limiting resistances and energy-storage capacitance in the circuit can control the electric field intensity so that different pulsewidths can be output.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Novel Step Field Plate RF LDMOS Transistor for Improved BVDS-R on Tradeoff
           and RF Performance

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      Authors: Rutu Patel;Nihar R. Mohapatra;
      Pages: 4401 - 4407
      Abstract: In this article, a novel step field plate (SFP) laterally diffused metal–oxide–semiconductor (LDMOS) structure is proposed for improved breakdown voltage- ON resistance tradeoff and better RF performance. The proposed structure could be easily integrated into the CMOS process flow using four additional noncritical masks. The known materials like fully silicided polysilicon and silicon nitride (SiN) are used as FP and dielectric, respectively. The proposed design improves the device performance by uniformly distributing the electric field in the drift region. The higher drift doping for the same OFF-state breakdown voltage improves the ON resistance by $sim 2.5times $ and ON-state breakdown voltage by $sim 2times $ . Significant improvements in frequency behavior and flat power response are also observed. The device physics behind different observations are explained using detailed TCAD simulations.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Near-Ideal Subthreshold Swing in InAlN/GaN Schottky Gate High Electron
           Mobility Transistor Using Carbon-Doped GaN Buffer

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      Authors: Sujan Sarkar;Ramdas P. Khade;Ajay Shanbhag;Nandita DasGupta;Amitava DasGupta;
      Pages: 4408 - 4413
      Abstract: This work presents a comparative study of the subthreshold swing (SS) in InAlN/GaN-based high electron mobility transistor (HEMT), with and without carbon doping in the buffer layer. It is observed that devices with carbon-doped (C-doped) buffer exhibit near-ideal SS of close to 60-mV/decade over a wide range of drain voltage for both up and downsweep. The C-doped buffer layer reduces the OFF-state drain leakage current and increases the drain current ON/OFF ratio. TCAD simulation of the vertical electric field under the gate shows that the sample with a C-doped buffer layer has a much lower value of the peak electric field at the drain side edge of the gate, resulting in lower reverse-biased gate leakage current and smaller SS compared to that of the undoped buffer. Moreover, the junction capacitance at the interface of the unintentionally doped GaN (UID:GAN) and the C-doped buffer layer, in series with the depletion capacitance, reduces the overall capacitance, which further improves the SS in the C-doped wafer.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Novel Backside Structure for Reverse Conducting Insulated-Gate Bipolar
           Transistor With Two Different Collector Trench

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      Authors: Zeyu Wu;Yitao He;Dan Liu;Chen Zhang;Xinglai Ge;Dong Liu;
      Pages: 4414 - 4420
      Abstract: A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with two different collector trench (DCT) is proposed. One of the collector trenches is filled with heavily doped N-type polysilicon (N-poly) and the other is filled with heavily doped N- and P-poly. An electron accumulation layer is formed along the sidewall of trench owing to built-in potential difference between the N-poly and the N-drift region. The electron accumulation layer and collector trenches block the electric field, which behaves just like the N-buffer layer of the conventional RC-IGBT (Con. RC-IGBT). Similarly, due to potential difference between the P-poly and N-drift region, a high-density hole inversion layer is formed to narrow the electron current path as a high resistance. The DCT RC-IGBT achieves snapback-free in a small cell pitch without additional control. Moreover, the DCT RC-IGBT shows better tradeoff between turn-off loss and ON-state voltage drop than that of con. RC-IGBT. For the same forward voltage drop, the turn-off loss is reduced by 26%.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Hybrid-Channel Injection Enhanced Modulation 4H-SiC IGBT Transistors
           With Improved Performance

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      Authors: Xiaochuan Deng;Zhijie Cheng;Zhiyu Chen;Hao Wu;Song Bai;Xu Li;Xuan Li;Wanjun Chen;Bo Zhang;
      Pages: 4421 - 4426
      Abstract: Conventional planar- and trench-gate silicon carbide insulated-gate bipolar transistors (SiC C-IGBT and T-IGBT) suffer from higher turn- OFF loss ( ${E}_{text {off}}$ ) and ON-state voltage drop [ ${V}_{text {ce(sat)}}$ ]. An improved hybrid-channel injection enhanced modulation 4H-SiC IGBT (HC-IGBT) is proposed and investigated to overcome these shortcomings in this article. The proposed IGBT structure is considered 3-D because the gate wraps around a raised emitter-to-collector channel, instead of residing on top of the channel in the conventional 2-D planar-gate structure. Therefore, multiple gates are ganged together through the same gate electrode to enable more electrons in the “ON” state and provide more path to remove extra holes in the “OFF” state. Comparing with C-IGBT and T-IGBT structure, HC-IGBT gains an improvement of 108% and 21% in a differential specific ON-resistance as well as a turn- OFF loss reduction of 11% and 16%. The industrial figure of merit (IFOM $= {V}_{text {ce(sat)}},,times ,,{E}_{text {off}}$ ) of HC-IGBT is reduced by 21% and 22% compared with C-IGBT and T-IGBT, respectively. Meanwhile, the Baliga’s figure of merit (BFOM $= {V}_{text {BR}}^{{2}}/{R}_{text {on,sp}}$ ) shows about 63% and 15% larger than that of C-IGBT and T-IGBT. These results show that HC-IGBT structure has much superior tradeoff between the ON-state voltage drop and turn- OFF loss, indicating the potential for ultrahigh-voltage pow-r electronic of the future.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Small Subthreshold Swing Diamond Field Effect Transistors With
           SnO2 Gate Dielectric

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      Authors: Shi He;Wei Wang;Genqiang Chen;Shumiao Zhang;Qi Li;Qianwen Zhang;Xiaohui Chang;Yan-Feng Wang;Minghui Zhang;Hong-Xing Wang;
      Pages: 4427 - 4431
      Abstract: A small subthreshold swing (SS) hydrogen-terminated diamond field-effect transistor is realized by using a wide bandgap material (SnO2). Results showed an SS of 106.4 mV/dec, which should be ascribed to the low interface state density (1.05 $times10$ 12 cm $^{-2}cdot $ eV−1) between SnO2 and diamond. The fixed charge density and trapped charge density are $1.1times10$ 12 cm−2 and $8.6times10$ 11 cm−2, respectively. Leakage current between source and gate is less than $2.1times10$ −8 A at gate voltages from −5.0 to 1.0 V and the breakdown voltage is measured to be −180 V. In addition, the devices exhibit normally- OFF characteristics, whose threshold voltage and maximum drain current density are −0.12 V and −21.6 mA/mm with 4- $mu text{m}$ gate at ${V}_{GS} = -3$ V. The ON/OFF ratio is around 107 and the maximum effective mobility is extracted to be 165 cm2/(Vs). This work indicates that SnO2 dielectric could form low interface state density with hydrogen-terminated diamond surface and it also provides a simple method to realize normally- OFF devices.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power
           Devices

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      Authors: N. Modolo;C. De Santi;G. Baratella;A. Bettini;M. Borga;N. Posthuma;B. Bakeroot;S. You;S. Decoutere;A. Bevilacqua;A. Neviani;G. Meneghesso;E. Zanoni;M. Meneghini;
      Pages: 4432 - 4437
      Abstract: Compact modeling of charge trapping processes in GaN transistors is of fundamental importance for advanced circuit design. The goal of this article is to propose a methodology for modeling the dynamic characteristics of GaN power HEMTs in the realistic case where trapping/detrapping kinetics are described by stretched exponentials, contrary to ideal pure exponentials, thus significantly improving the state of the art. The analysis is based on: 1) an accurate methodology for describing stretched-exponential transients and extracting the related parameters and 2) a novel compact modeling approach, where the stretched exponential behavior is reproduced via multiple RC networks, whose parameters are specifically tuned based on the results of 1). The developed compact model is then used to simulate the transient performance of the HEMT devices as a function of duty cycle and frequency, thus providing insight on the impact of traps during the realistic switching operation.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Novel SiC MOSFET With a Fully Depleted P-Base MOS-Channel Diode for
           Enhanced Third Quadrant Performance

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      Authors: Ping Li;Rongyao Ma;Jingyu Shen;Liang Jing;Jingwei Guo;Zhi Lin;Shengdong Hu;Cong Shi;Fang Tang;
      Pages: 4438 - 4443
      Abstract: In this article, a novel silicon carbide double-trench MOSFET with an integrated fully depleted P-base MOS-channel diode is proposed and investigated by calibrated TCAD simulations. The proposed silicon carbide (SiC) MOSFET features a fully depleted P-base region achieved by shrinking the source trench mesa in the ${z}$ -direction. Due to the significantly reduced conduction band energy in the fully depleted P-base region, a low potential barrier for electrons to flow through the JFET region to the N+ source region is formed. As a result, the proposed SiC MOSFET not only exhibits more than three times lower diode cut-in voltage than the body p-i-n diode but also successfully eliminates the bipolar degradation issues. Besides, a compact model based on Poisson’s law is developed to understand the origin of the barrier lowering effect. Calibrated TCAD simulation results indicate that the enhanced third quadrant performance would not comprise the other electric characteristics, which makes the proposed SiC MOSFET a highly promising candidate for high-frequency power applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Temperature-Dependent Physical Thermal Network Model Including Thermal
           Boundary Conditions for SiC MOSFET Module

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      Authors: Ke Heng;Xin Yang;Xinlong Wu;Junjie Ye;Guoyou Liu;
      Pages: 4444 - 4452
      Abstract: SiC MOSFETs have received great attention due to their excellent electrothermal properties. Accurate junction temperature information of SiC MOSFETs ensures safe operation and helps effective thermal management. However, the existing thermal models have limits to correctly predict the thermal behaviors, whose parameter extraction processes are normally complicated. Most of the thermal models generally omit the temperature effects, which greatly impairs their usefulness and effectiveness. Here, a temperature-dependent physical resistor–capacitor (RC) network model is proposed, which can accurately characterize the thermal behavior of SiC MOSFETs particularly under high-temperature conditions. Meanwhile, the boundary conditions are fully investigated and modeled, which guarantees the adaptation of the proposed model for different real-field applications. The proposed method can remarkably simplify the process of parameter extraction since only the steady-state temperature distribution information is required with the assistance of finite-element method (FEM). Finally, the effectiveness and the robustness of the proposed model are validated by FEM simulation and experiments.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5
           nm Technology Nodes

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      Authors: S. S. Teja Nibhanupudi;Divya Prasad;Shidhartha Das;Odysseas Zografos;Alex Robinson;Anshul Gupta;Alessio Spessot;Peter Debacker;Diederik Verkest;Julien Ryckaert;Geert Hellings;James Myers;Brian Cline;Jaydeep P. Kulkarni;
      Pages: 4453 - 4459
      Abstract: Buried power rail (BPR) and back-side power delivery grid have been proposed as solutions to scaling challenges that arise beyond the 5-nm technology node, mainly to lower IR drop and further shrink area. This article demonstrates a holistic evaluation of this technology and its variants at the microprocessor level. This is carried out by taking an Arm Cortex-A53 design through the standard-VLSI physical design implementation flow on Imec’s iN6 node, equivalent to the industry 3-nm technology node, which features the buried power technology. The power, performance, area, on-chip IR drop, and off-chip voltage droop metrics are benchmarked, and implications on power gating are explored. An extensive Design-Technology-Co-Optimization (DTCO) study of the back-side power grid is presented to enhance the decoupling capacitance by sweeping associated technology parameters showcasing further optimization opportunities in manufacturing. The conclusions of this work highlight that the front-side (FS) power delivery network (PDN) with buried rails achieves a 25% lower on-chip IR drop and 17% lower off-chip voltage droop (power supply noise) resulting in 21% lower guard band voltage. On the other hand, the back-side power grid with BPRs achieves 85% lower on-chip IR drop and 30% off-chip voltage droop resulting in 60% lower guard band voltage. In addition, the impact of BPRs, and back-side power grids on power gated designs are evaluated.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Space Charge Limited Current and Induced Particle Reflection With a
           Time-Varying Current Injection

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      Authors: Ying Bin Zhu;Mei Yan Liao;Ruo He Yao;
      Pages: 4460 - 4468
      Abstract: Properties of space charge limited current and induced particle reflection with a time-varying current injection are investigated by an efficient grid-free numerical approach. Considering a planar diode with a single-frequency current emitted parallel to the upstream electrode surface, we study the current transmission characteristics between two dc biased electrodes and the influence of current frequency and magnitude on the limiting current first leading to electrons reflection. It is found that on account of the time-varying current injection, the limiting current strongly depends on the current frequency and magnitude, as well as the emission velocity of electrons. For the low-frequency limit, the dc component of the limiting current is approximately equal to half of that obtained from the time-independent model. The limiting current increases monotonically with increasing the frequency, and the dc component has a maximum equal to the limiting current obtained from the time-independent model.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Current Transient Spectroscopic Study of Vacancy Complexes in Diamond
           Schottky p-i-n Diode

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      Authors: Sandeep K. Chaudhuri;Mohamadali Malakoutian;Joshua W. Kleppinger;Maitreya Dutta;Franz A. Koeck;Robert J. Nemanich;Srabanti Chowdhury;Krishna C. Mandal;
      Pages: 4469 - 4473
      Abstract: The present state-of-the-art of junction-based diamond electronic devices is limited by the challenges inherent to the synthesis of n-type layers, where the dopant itself forms defect complexes that are donor compensating centers. Recently, the fabrication of diamond Schottky p-i-n diodes (SPINDs) by chemical vapor deposition (CVD) of intrinsic diamond films followed by an n-type layer on p-type diamond substrates has been reported to demonstrate excellent diode-like behavior with high rectification factors and surface barrier height at elevated temperatures. However, due to the ultrawide bandgap of diamond and small contact area of the devices, it is challenging to characterize the defect centers that limit the performance of the SPINDs using conventional capacitance transient spectroscopy. In this article, we report the characterization of defect centers in the diamond SPINDs with a contact area of 280 $mu text{m},,times ,,280,,mu text{m}$ using current transient spectroscopy (CTS), which measures thermally induced emission rates from trap centers through change in device current instead of junction capacitance. The CTS scans in the temperature range 80–800 K revealed the presence of five trap-related peaks. Results from density functional theory (DFT) calculations were used to identify the nature of the traps. While most of the detected traps were identified to be vacancy complexes coupled to phosphorus and hydrogen impurities, one trap has been identified as single carbon vacancy. Most of the phosphorus-related defect complexes were observed to be in neutral and/or negative charge states and were identified as acceptor-like states.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Performance Regulation of Near-Field Electroluminescent Cooling Device
           Based on 2-D Material

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      Authors: Tianjun Liao;Jianying Du;Jincan Chen;
      Pages: 4474 - 4478
      Abstract: We establish a conceptual model of the graphene-assisted near-field electroluminescent refrigerator (GANER), which is composed of an emitter and a receiver. The two basic components are formed by a homojunction structure using III–V group semiconductors as materials. The cooling rate density (CRD) and coefficient of performance (COP) of the GANER are derived based on fluctuation electrodynamics and thermodynamics. The electrical–optical–thermal coupling properties and parametric optimum designs of the GANER and the near-field electroluminescent refrigerator (NER) are studied. The performances of the GANER and the NER are compared. By making tradeoff between the CRD and the COP, the selective criteria of several key parameters are provided. The effects of graphene’s chemical potential and finite-rate heat transfer between the refrigerator and the environment on the optimum performances of the GANER are discussed. It is found that for an arbitrary value of the chemical potential, the performance of the GANER is superior to that of the NER. The advantages of the GANER are more prominent for a large chemical potential. The results obtained here may provide some guidance for optimally designing solid-state refrigerators.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part I:
           Theory

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      Authors: Christian Schleich;Dominic Waldhör;Theresia Knobloch;Weifeng Zhou;Bernhard Stampfer;Jakob Michl;Michael Waltl;Tibor Grasser;
      Pages: 4479 - 4485
      Abstract: Leakage currents through dielectrics in modern logic, memory, and power devices, and back-end interlevel layers can severely increase the time-zero power dissipation and shorten the lifetime of the material structure. Depending on thickness, material properties, and fabrication quality, different conduction mechanisms through the insulating layer, such as band-to-band and trap-assisted tunneling (TAT) are observed. These leakage currents can be distinguished by their dependence on electric field strength, temperature, and their transient characteristics. The identification of the underlying mechanisms is of utmost importance for the selection of suitable dielectrics and optimization of device processing. In this work, we present a nonradiative multiphonon model which extends our compact physics (Comphy) reliability framework to also account for TAT. The model is based on a single physical defect parameter set from which charge transfer kinetics between charge carrier reservoirs and oxide defects (single-TAT) as well as between the defects (multi-TAT) can be derived. We thereby demonstrate that the thermal barrier for inelastic defect–defect carrier tunneling is approximately twice as large in comparison to reservoir-defect interaction and further show in which parameter regime multi-TAT plays a role. Our results show that multi-TAT currents are a less important contribution to the overall tunnel current than previously assumed.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part II:
           The Role of Polarons

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      Authors: Christian Schleich;Dominic Waldhör;Al-Moatasem El-Sayed;Konstantinos Tselios;Ben Kaczer;Tibor Grasser;Michael Waltl;
      Pages: 4486 - 4493
      Abstract: Using the framework developed in the first part of this work, we demonstrate the capabilities of the extended two-state nonradiative multi-phonon (NMP) model by reproducing leakage current characteristics of two selected technologies. First, we identify the temperature-activated leakage mechanism in SiC / SiO2 stacks using a tens of nanometer thick thermally grown oxide as trap-assisted tunneling (TAT) through defects. Interestingly, this effect can be reproduced with the same parameters in a SiC / SiO2 stack with deposited oxide. Our simulations demonstrate that these charge transition centers are distributed within only a few nanometers from the SiC / SiO2 interface. The low thermal activation of the leakage current is linked to the low relaxation energies of the involved traps compared with those typically involved in bias temperature instability (BTI) and Random Telegraph Noise (RTN). Second, a similar mechanism can explain TAT characteristics and transient charge trapping currents in Metal–Insulator–Metal (MIM) capacitors with a ZrO2 insulating layer. By comparison of our model parameters to theoretical density functional theory (DFT) calculations, we identify self-trapped electrons (polarons) as a likely cause for these effects, as they have the required low relaxation energies.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • DFT Analysis of Hydrogenated Zigzag Aluminum Nitride Nanoribbons for
           Spintronic Devices

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      Authors: Saurabh Kharwar;Sangeeta Singh;Brajesh Kumar Kaushik;
      Pages: 4494 - 4500
      Abstract: Density functional theory (DFT) and nonequilibrium Green’s function (NEGF) framework are used to explore the structural, spin-polarized electronic, and spin-based transport properties of edge-hydrogenated zigzag aluminum nitride nanoribbons (ZAlNNRs). The proposed ZAlNNR is observed to be structurally stable and exhibits half-metallic nature in the magnetic state. The quantum transport property of the proposed two-terminal device model of 1H-AlN-1H demonstrates the bipolar spin-filter characteristics along with giant magnetoresistance (GMR), spin-based peak to valley current ratio (spin-PVCR), and spin-based rectification ratio (spin-RR) of the order of 1015, 1012, and 108, respectively. The calculated GMR and spin-RR of the 1H-AlN-1H device are 107 and 102 times higher than zigzag silicene nanoribbon (ZSiNR) and doped-zigzag graphene nanoribbon (doped ZGNR), respectively. The observed GMR, spin-PVCR, and spin-rectifying behavior of the reported ZAlNNR device could be deployed for multifunctional spintronic device applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • High-Performance Monolayer BeN2 Transistors With Ultrahigh On-State
           Current: A DFT Coupled With NEGF Study

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      Authors: Wenhan Zhou;Shiying Guo;Haibo Zeng;Shengli Zhang;
      Pages: 4501 - 4506
      Abstract: Conventional field-effect transistors (FETs) based on silicon downscaling are approaching physical limits, and thus, it is urgent to explore additional novel solutions to address this issue. The 2-D semiconductors have unique advantages as the channel material and provide a promising prospect for high-performance FETs in the post-Moore era. In this work, a new 2-D semiconductor, monolayer BeN2, is studied for the FET performance limits through first-principle quantum-transport simulations. Monolayer BeN2 exhibits a graphene-like planar structure with a direct bandgap of 1.3 eV. Transfer characteristics of sub-10-nm BeN2 FETs are thoroughly assessed through scaling gate length. In particular, 2-D BeN2 FETs with 10-nm gate present the ultrahigh ON-state current above $4500,, mu text{A}/mu text{m}$ for high-performance applications. Also, we realize the significant reduction of gate length (only 2.5 nm) against the International Technology Roadmap for Semiconductors (ITRS) requirements through introducing underlap structures. In addition, the performance of single devices based on monolayer BeN2 is evaluated and compared with some of the recently proposed 2-D devices.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Unified Distribution Form of the Density of States in Disordered Organic
           Semiconductors

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      Authors: Dong Qin;Kaifei Chen;Jiezhi Chen;Nianduan Lu;
      Pages: 4507 - 4513
      Abstract: An accurate density of states (DOS) is essential for understanding charge carrier transport properties and then better developing the electronic and optoelectronic devices. Currently, Gaussian and exponential forms are the two most general DOS, which can be unified in the tail state of the state. However, Gaussian DOS at high concentrations is not applicable, as well as exponential DOS at low concentrations. To avoid the disadvantage of Gaussian and exponential form, based on the Poisson flow, a unified distribution form of the DOS have been developed to discuss the charge carrier transport. The proposed DOS is more consistent with the actual situation and exhibits better rationality under the whole range of carrier density. Otherwise, we for the first time introduced the entropy to analyze the disorder parameters. Based on the proposed DOS, the concentration and temperature dependence of mobility has been discussed in detail.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Programmable Nanoarchitectonics of Pore Array for Electronic-Nose-Based
           Early Disease Diagnose

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      Authors: Xiaofang Pan;Xiaojin Zhao;Wei Xu;Zhiyong Fan;Amine Bermak;
      Pages: 4514 - 4520
      Abstract: In this article, we present a novel electronic nose fabrication process based on highly programmable anodic aluminum oxide (AAO) nanoarchitectonics and ultrasonic spray pyrolysis (USP) deposition. Featuring an ultralow manufacturing cost, the deposited material’s morphology can be accurately controlled with fabricated general-purpose AAO template. Compared with nonstandard lithography-based template fabrication method, the need of complicated Bosch etching process and its associated complex process parameter tuning is eliminated. As a result, the cost-effective mass production of 3-D nanotemplate-based material and devices can be enabled. In addition, the target material’s limited coverage and time efficiency issues widely existing in the previous deposition methods are well-addressed by our customized USP deposition, especially for the 3-D nanotemplate with large surface-to-volume ratio, leading to significantly improved gas-sensing performance. Moreover, the proposed fabrication recipe, together with the adopted gas recognition algorithms based on linear discriminant analysis (LDA), is validated based on the reported extensive measurement results for five gas biomarkers widely exploited for patients’ exhaled gas-sensing and recognition applications. This shows great potential for the early disease diagnose of diabetes, breast cancer, acute lung injury, colon diseases, lung cancer, and so on.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Highly Sensitive Pressure Sensor Based on h-BN/Graphene/h-BN
           Heterojunction and Cu–Sn Solid–Liquid Interdiffusion Bonding

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      Authors: Junqiang Wang;Changzheng Xie;Mengwei Li;Jingyu Bai;
      Pages: 4521 - 4526
      Abstract: Graphene with atomic layer thickness has excellent mechanical properties and provides tremendous potential for developing high-performance pressure sensors. However, bare graphene is sensitive to humidity, and oxygen in the air also significantly affects the stability of graphene pressure sensor. In this work, a highly sensitive pressure sensor was fabricated through the MEMS process and nanofilm transferring. The graphene sensing element is entirely isolated from the external environment by the initial protection of h-BN, followed by the secondary protection of Cu–Sn solid–liquid interdiffusion bonding. After the static test, an average sensitivity of $2.9times10$ −4 kPa−1 was achieved over a pressure range from −80 to 0 kPa. Also, it exhibited excellent repeatability and minimal hysteresis. As graphene pressure sensor was exposed to ambient air for 30 days, the relative resistance change was just 2.3%. The resistance of graphene pressure sensor can also keep stable even if the device was stored in a high-temperature or high-humidity environment. Thus, this work provides a promising approach for the practical application of high-performance graphene pressure sensors.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • AlGaN/GaN HEMT Based Biosensor for Detection of the HER2 Antigen Spiked in
           Human Serum

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      Authors: Shivanshu Mishra;Pharyanshu Kachhawa;Prasenjit Mondal;Surajit Ghosh;Chaturvedula Tripura;Nidhi Chaturvedi;
      Pages: 4527 - 4533
      Abstract: This work reports the development of a gallium nitride-based high electronic mobility transistor (GaN HEMT)-based biosensor to detect human epidermal growth factor receptor-2 (HER2) antigen in spiked human serum. The platform devices have been fabricated with a source to drain distance, gate length, and unit gate width of 25, 3, and $100 ~mu text{m}$ , respectively. The cysteine methyl ester (CME)-based chemistry has been utilized to immobilize the antiHER2 antibody on the sensing region of the sensor. The formation of the CME layer was confirmed through Raman spectroscopy, which shows a peak around a wavelength of 262 cm−1. The antibody immobilization on the gold surface has been confirmed through enzyme-linked immunosorbent assay (ELISA). The sensor has been electrically characterized before and after each step of the functionalization process. The sensor shows a significant change in the drain current of 0.95 and 1.7 mA at a ${V}_{{mathrm {ds}}} $ of +5 V for 50- and 200-ng/ml concentration of HER2 in spiked human serum. A minor change in the drain current of the sensor, when tested with a nonspecific antigen, suggested the high specificity of the sensor for HER2. The sensor has been tested for a broad range concentration of HER2 antigen from 0.7 pg/ml to 200 ng/ml.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Detection of Glucose Using Diamond Solution-Gate Field-Effect Transistor

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      Authors: Qianwen Zhang;Xiaohui Chang;Bangqiang Xu;Yanfeng Wang;Dan Zhang;Yangmeng Feng;Shi He;Genqiang Chen;Qi Li;Juan Wang;Hong-Xing Wang;
      Pages: 4534 - 4539
      Abstract: The concentration of glucose was detected using an H-terminated diamond solution-gate field-effect transistor (H-diamond SGFET). The linker molecular 1-pyrenebutyric acid–N-hydroxy succinimide ester (Pyr-NHS) was introduced to modify the H-diamond surface. Then, glucose oxidase (GOD) was immobilized on the diamond surface by linker Pyr-NHS. Atomic force microscope and scanning electron microscope measurements confirmed the successful immobilization of Pyr-NHS and GOD enzyme on the H-diamond surface. The concentration of glucose was determined by the shift of gate voltage ( ${V}_{text {GS}}$ ) in transfer characteristics of H-diamond SGFET. Also, the sensitivity of sensor for glucose detection was obtained as −58.69 mV/ ${text {log}}_{{10}}$ (glucose concentration) by the slope of fitting curve, which represented the relationship between ${Delta {V}}_{text {GS}}$ and logarithmic of glucose with concentration increasing from 1 $times 10^{-{3}}$ to 1 M. The reusability of device was characterized by the transfer properties and small standard deviation (SD) of maximum output current ( ${I}_{text {DS(max)}}$ ) in four tests, indicating excellent reusability for detection of glucose.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Research and Experiment of a W-Band High-Power Extended Interaction
           Oscillator With High Voltage

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      Authors: Tianzhong Zhang;Xinjian Niu;Jie Qing;Yinghui Liu;Guo Guo;Hongfu Li;Yanyu Wei;
      Pages: 4540 - 4545
      Abstract: In order to obtain a high-power radiation source in the W-band, a 95-GHz extended interaction oscillator (EIO) with high voltage was designed and tested in this article. The overall structure of the designed EIO is introduced, and the simulation results of the slow wave structure are shown. Experimental test results show that, at a high duty cycle of 50%, the 95.1-GHz radiation peak power of 3.5 kW is achieved when an electron beam with 2 A and 42.8 kV is injected. The experimental test of the designed EIO has guiding significance for miniaturized vacuum devices to obtain high-power radiation source.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Time-Domain Simulation of Helical Gyro-TWTs With Coupled Modes Method and
           3-D Particle Beam

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      Authors: Alexander Marek;Konstantinos A. Avramidis;Lukas Feuerstein;Stefan Illy;Manfred Thumm;Chuanren Wu;John Jelonnek;
      Pages: 4546 - 4552
      Abstract: A new self-consistent time-domain model for the simulation of gyrotron traveling-wave tubes with a helically corrugated interaction space (helical gyro-TWTs) is presented. The new model links classical methods using the approach of slowly varying variables together with an expansion of the electromagnetic field in eigenmodes and advanced full-wave particle-in-cell (PIC) solvers. The aim is to significantly reduce the required calculation time compared to full-wave PIC solvers, while less strict assumptions are introduced as in the classical approaches of slowly varying variables. For the first time, the classical theory of coupled circular waveguide modes for the description of the operating electromagnetic eigenmode in the helical interaction space is combined with a 3-D PIC representation of the electron beam. This allows the simulation of the beam–wave interaction over a broad bandwidth and at arbitrary harmonics of the cyclotron frequency. In addition, arbitrary electron beams (with spreads, offsets of the guiding center from the symmetry axis, and so on) can be investigated. The new approach is compared with the full-wave 3-D PIC code CST Microwave Studio. A good agreement of the simulation results is achieved, while the computing time is significantly reduced.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Design and PIC Simulation of Ka-Band Periodically Loaded High Gain
           Gyro-Twystron

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      Authors: Vangalla Veera Babu;M. Thottappan;Smrity Dwivedi;
      Pages: 4553 - 4562
      Abstract: In this article, the design and multimode analysis of a Ka -band, single cavity followed by a periodically dielectric-loaded (PDL) waveguide-based gyro-twystron operating in the fundamental TE01 mode have been presented. The present amplifier has been studied for its stability against the backward wave oscillations (BWOs) and the beam–wave interaction by using the linear and nonlinear multimode theory, respectively. Furthermore, the design of the present gyro-twystron has been validated by using a commercially available 3-D particle-in-cell (PIC) code. Moreover, a few key subassemblies, including a ${Y}$ -shaped input coupler, triode-type magnetron injection gun (MIG) with $sim 4$ % velocity spread, a curved collector, and a double-disk RF window, have been designed and studied for their performance behavior. The 3-D PIC simulation of the present gyro-twystron predicted $sim 260$ -kW RF output power in the TE01 mode at $sim 35$ GHz. The gain, efficiency, and bandwidth are calculated as $sim 54$ dB, 40%, and 1.3 GHz, respectively.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Beam Optics Study on a Two-Stage Multibeam Klystron for the Future
           Circular Collider

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      Authors: Jinchi Cai;Zaib un Nisa;Igor Syratchev;Graeme Burt;
      Pages: 4563 - 4571
      Abstract: The two-stage (TS) multibeam klystron (MBK) technology has recently attracted significant research attention due to its compactness and high-efficiency (HE) performance. However, there is still a lack of scientific research on the beam optics for such microwave power sources integrated with a postacceleration (PA) gap. In this article, a comprehensive optics study based on the newly developed 2-D optics code CGUN is conducted for the first time to demonstrate the most critical steps in the optics design process, by adopting the 400-MHz TS MBK for the future circular collider (FCC) as an example. Two specific challenges arise in this TS MBK, which are studied in this article, and solutions are given. First, due to the combination of slow electrons, impedance change from individual beamtubes into common volume, and the mild decay of the magnetic field, there are possible reflected electrons at the collector entrance. This requires an increase in the beam voltage to 80 kV, beyond the requirements from considering the output gap alone, as well as tighter control on bouncing electrons. The beam scalloping is also found to be highly sensitive to the position of the PA gap and magnetic field, which later demonstrates that large gap length and magnetic field are required. Final all-in-one particle-in-cell (PIC) simulations of this klystron equipped with this special optics design demonstrate that the specification of 1.2-MW continuous wave (CW) power is practically attainable with an efficiency of 77.5% and without the presence of reflected electrons at any point in the whole circuit.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Characterization of Pseudospark Discharge-Based Multigap Plasma Cathode
           Electron Source for the Generation of Short Pulsed Energetic Electron Beam
           

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      Authors: Varun;Ram Prakash Lamba;Udit Narayan Pal;
      Pages: 4572 - 4578
      Abstract: Pseudospark (PS) discharge-based devices are known as excellent source for the generation of high current density and energetic self-focused electron beam in the hollow cathode (HC) phase. In this article, short pulsed ( $!!!< 100$ ns) and high energetic (~20 keV) electron beam has been generated and propagated (up to ~60 mm) in the drift region without using any external guiding magnetic field from the four-gap configuration of PS discharge-based plasma cathode electron (PD-PCE) source. The particle-in-cell (PIC) simulation code OOPIC Pro has been employed, whose results have shown the strong dependence of beam propagation into the drift region on the penetration and distribution of potential lines. The combined experimental and simulation investigations have also been carried for the multigap (four-gap) with wide range of external storage capacitor (40 pF–18 nF) and operating voltages (5–35 kV). The circuit parameter controls the appearance of HC phase for the energetic (50%–70% applied voltage) electron beam and conductive phase for the high current (~10 A to ~0.5 kA) electron beam. The potential distribution has clearly indicated that the electron beam with higher applied voltages can propagate more focused in the drift region. The investigations have evidently shown the generation of low energy and high current to high energy and low current electron beams suitable to cover the potential applications in the field of extreme ultraviolet (EUV)/soft X-ray radiation generation, surface modification, and microwave-terahertz radiation generation.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Novel Configuration for a C-Band Axial Vircator With High
           Output Power

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      Authors: Giacomo Migliore;Antonino Muratore;Alessandro Busacca;Pasquale Cusumano;Salvatore Stivala;
      Pages: 4579 - 4585
      Abstract: We present a novel configuration for an axial virtual cathode oscillator (Vircator) operating in the ${C}$ -band and designed for high output power applications. In order to enhance the efficiency, we have employed a geometry with up to seven reflectors along the drift space. While in previous research works this optimization process has been performed only varying the reflectors radii while using a fixed distance between reflectors, in our work we propose an optimization in terms of both reflectors radii and distances. Our optimized structure for the axial Vircator is able to provide an efficiency up to 15.6% and an output power of 1.6 GW in the ${C}$ -band, with a working voltage of 510 kV and a cathodic current of 24 kA.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Using Phase Jumping Method to Enhance the Beam–Wave Interaction
           Efficiency in Terahertz Folded-Waveguide Traveling-Wave Tube

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      Authors: Feng Lan;Mengzhen Li;Zugen Guo;Ruifeng Zhang;Jiezhong Luo;Han Lai;Zhaoyun Duan;Yubin Gong;Fei Xiao;Gil Travish;Huarong Gong;
      Pages: 4586 - 4591
      Abstract: The folded-waveguide (FWG) traveling-wave tube (TWT) is a promising high-power terahertz (THz) amplifier. However, it is challenging to develop THz FWG-TWT with high beam–wave interaction efficiency. In this work, a phase jumping technology, which originates from free-electron lasers, is proposed to boost the beam–wave interaction efficiency of THz FWG-TWT. A modified slow wave structure acts as the phase shifter to adjust the phase gap between electron beam and electromagnetic wave. By jumping the phase gap to an appropriate value, the bunching center of electron beam keeps for a long time in the deceleration region. Thus, more energy is transferred to electromagnetic wave from bunching electron beam. To verify such proposition, a THz FWG-TWT example utilizing the phase jumping is presented in this article. Compared with conventional one, its efficiency within the operation bandwidth from 212 to 224 GHz is improved by 60%–140%.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Effect of Microwave Leakage on Backward Current in an X-Band Dual-Mode
           RBWO Packaged With Permanent Magnet

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      Authors: Kun Chen;Renzhen Xiao;Yanchao Shi;Tianze Miao;Guangshuai Zhang;Shaofei Huo;Yihang Yang;
      Pages: 4592 - 4597
      Abstract: In this article, the effect of microwave leakage into the diode region on the suppression of backward current in a relativistic backward wave oscillator (RBWO) operating at low magnetic field is investigated by the theoretical analysis, particle-in-cell (PIC) simulation, and experiments. The theoretical results show that some backward electrons are absorbed by the cathode holder due to microwave leakage, and as the microwave power increases, the microwave frequency increases, and the guiding magnetic field decreases, it will promote the absorption of electrons. The PIC simulations based on the first principle reveal that the leakage microwave partially suppresses the backward current and the suppression is enhanced when the incidence TM02 is dominant. In the ${X}$ -band dual-mode RBWO packaged with permanent magnet experiments, a microwave pulse with the power of 3.9 GW, the frequency of 9.93 GHz, and the efficiency of 33% was measured when the diode voltage was 820 kV and diode current was 14.5 kA.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Attenuation and Reflection of TEM and TE Microwaves Through a Dielectric
           With Multipactor

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      Authors: Huihui Wang;Laqun Liu;Dagang Liu;Lin Meng;
      Pages: 4598 - 4603
      Abstract: A theoretical model in terms of RF and electric field is proposed for the attenuation and reflection of TEM and TE microwaves through a dielectric with multipactor. The reflected power is much lower than the attenuated power. Also, both ratios of reflected and attenuated powers increase dramatically when the RF decreases to be near the cutoff frequency for TE microwaves. The attenuation ratio can be larger than 10% and smaller than 0.1%, while previously, it is usually considered as a small constant. The phenomena of power attenuation and reflection are also observed directly by electromagnetic particle-in-cell simulations, and simulation results are consistent with theoretical results.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Simulation Design of G-Band FWG TWT Amplifier Enhanced by π-Mode Extended
           Interaction

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      Authors: Ningjie Shi;Changqing Zhang;Hanwen Tian;Shaomeng Wang;Zhanliang Wang;Ping Zhang;Tao Tang;Zhaoyun Duan;Zhigang Lu;Huarong Gong;Yubin Gong;
      Pages: 4604 - 4610
      Abstract: This article studies and summarizes the operating characteristics of a ${G}$ -band folded waveguide traveling wave tube (TWT) amplifier enhanced by the $pi $ -mode extended interaction cavities. Compared with conventional ${G}$ -band TWTs, the proposed amplifier can at once obtain a higher gain in a shorter interaction circuit length and ensure a proper operating bandwidth. The key of the design is introducing the $pi $ -mode multigap resonant cavity with alternating wide and narrow slots, which will improve the working performance of the whole device by shortening the length of the interaction circuit, enhancing its interaction effect, and improving its gain of unit length. In this design, the operation bandwidth is expanded by stagger tuning technique. In addition, the influence of cavity loss is examined so that the optimal performance is achieved. The PIC simulation results show that when the operating voltage is 21 kV and the operating current 80 mA, the maximum average output power of the designed TWT amplifier is 65.78 W at 217.4 GHz, which is corresponding to the maximum gain and efficiency of 37.38 dB and 3.9%, respectively. The gain per unit length is 12.64 dB/cm and the 3-dB bandwidth is 3.5 GHz.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A High-Power and Broadband G-Band Extended Interaction Klystron Based on
           Mode Overlap

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      Authors: Feng Zhang;Yaqi Zhao;Cunjun Ruan;
      Pages: 4611 - 4616
      Abstract: A ${G}$ -band multigap extended interaction klystron (EIK) adopting mode overlap method with ladder-type structure is proposed to achieve high power, high efficiency, and broad bandwidth. The gap number is set larger than the conventional EIK to achieve its potential. The high-frequency characteristics of the modes in output cavity are studied. The length ratio of long and short slots is optimized to obtain appropriate mode frequency interval and effective characteristic impedance. In our scheme, the gap number of output cavity is determined as 17 with the mode overlap of $pi $ mode and $15/ 16pi $ mode. The circuit structure and working conditions are carefully designed and optimized to solve the problem of instability under large gap number. With a beam current of 0.3 A, a voltage of 15.8 kV, and a magnetic field of 0.75 T, the particle-in-cell simulation shows that with the increase of frequency, the output cavity can work with two modes overlap and expand the 3-dB bandwidth to 1.32 GHz, which is more than two times of our previous work. Also, a maximum output power of 870 W, an efficiency of 18.4%, and a gain of 46.4 dB are finally obtained. The numerical simulation results definitely demonstrate the feasibility of mode overlap and its ability to the expansion of EIK bandwidth in the terahertz band.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide
           Trench MOS Structure

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      Authors: Zhiyu Guo;Zhi He;Fengxuan Wang;Jingmin Wu;Xiang Yang;Zhongchao Fan;Fuhua Yang;
      Pages: 4617 - 4623
      Abstract: In this work, characteristics of trench sidewall capacitance were investigated in a 4H-SiC stepped thick-oxide (STO) trench metal–oxide–semiconductor (MOS) structure. Multigroup SiC trench MOS capacitor test patterns with different structures and geometric parameters were designed and fabricated. From the capacitance–voltage measurements, the characteristics of the described SiC STO trench MOS were calculated and analyzed, including the thicknesses of the oxide at different locations in trench, the position of the oxide step at trench sidewall, and the flat-band voltages as well as the oxide charge densities of MOS from the upper part and lower part of oxide step at trench sidewall. Results showed that the flat-band voltages of MOS from the upper part (10.2 V) and lower part (12.5 V) of trench sidewall step had pronounced positive shifts over the ideal flat-band voltage (0.36 V), indicating a massive negative charges in the sidewall oxide film. Meanwhile, the net oxide charge density of MOS from the lower part of sidewall step ( $- 0.92times10$ 12 cm $^{-2}$ ) was smaller than that from the upper part ( $- 2.41times10$ 12 cm $^{-2}$ ), which was likely attributed to the massive shallow states in the oxide and to the poor quality of the thick-oxide film grown via chemical vapor deposition technology. The present works are providing a convenient technology to monitor the trench MOS structure by measuring the capacitance during SiC trench MOSFETs fabrication.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Complementary-Switchable Dual-Mode SHF Scandium Aluminum Nitride BAW
           Resonator

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      Authors: Dicheng Mo;Shaurya Dabas;Sushant Rassay;Roozbeh Tabrizian;
      Pages: 4624 - 4631
      Abstract: This article presents a bulk acoustic wave (BAW) resonator with complementary switchable operation in the first and second thickness extensional modes (TE1 and TE2) at 7.04 and 13.4 GHz. Two ferroelectric scandium aluminum nitride (Sc0.28Al0.72N) layers are alternatively stacked with three molybdenum electrodes, creating a laminated BAW resonator with independent switchability of polarization in constituent transducers. This enables intrinsic switchability of the resonator in TE1 and TE2 modes, when the ferroelectric Sc0.28Al0.72N layers are poled in the same or opposite directions, respectively. A generalized analytical proof of complementary switchable operation, extended to laminated BAW resonators consisting of arbitrary number of ScxAl1-xN layers, is presented. For the demonstrated prototype, electromechanical coupling coefficients ( ${k}_{t}^{2}$ ) of 10.1% and 10.7%, and quality factors ( ${Q}$ ) of 115 and 151, are measured for TE1 and TE2 modes, respectively, when the resonator is configured in the corresponding operation states. Besides showing intrinsically configurable operation in super-high-frequency regime with high ${k}_{t}^{textbf {2}}$ and ${Q}$ , a laminated Sc0.28Al0.72N BAW resonator exhibits repeatable operation under switching cycles.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Experimental Investigation of a Shape-Optimized Staggered Double-Vane
           Slow-Wave Structure for Terahertz Traveling-Wave Tubes

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      Authors: Shengkun Jiang;Guang Yang;Zhanliang Wang;Xin Wang;Xuanming Zhang;Zhifang Lyu;Tao Tang;Huarong Gong;Yubin Gong;Zhaoyun Duan;
      Pages: 4632 - 4637
      Abstract: Enormous concerns focus on the high-power and wide bandwidth traveling-wave tube (TWT) for its outstanding performance. In this article, a shape-optimized staggered double-vane slow-wave structure (SWS) for terahertz (THz) sheet beam TWT is proposed. The shape-optimized staggered double-vane SWS takes the advantages of higher interaction impedance, lower transmission loss, and lower phase velocity than conventional staggered double-vane SWSs. The shape-optimized staggered double-vane SWS with 85 periods is designed, fabricated, and cold tested. The measured transmission loss of the shape-optimized staggered double-vane SWS is less than 0.79 dB/cm in the frequency range of 0.211–0.26 THz, which is in good agreement with the simulation results. Furthermore, the beam–wave interaction analysis of a sheet beam TWT with this SWS is given. The output power is predicted to be >100 W with 3-dB bandwidth of >50 GHz. The results show that the shape-optimized staggered double-vane SWS is a very promising scheme to construct a high-power and wideband THz TWT for future applications such as communication and imaging.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Accurate Quantum Transport Modeling of High-Speed In0.53Ga0.47As/AlAs
           Double-Barrier Resonant Tunneling Diodes

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      Authors: Davide Cimbri;Begüm Yavas-Aydin;Fabian Hartmann;Fauzia Jabeen;Lukas Worschech;Sven Höfling;Edward Wasige;
      Pages: 4638 - 4645
      Abstract: In this article, we demonstrate a reliable physics-based simulation approach to accurately model high-speed In0.53Ga0.47As/AlAs double-barrier resonant tunneling diodes (RTDs). It relies on the nonequilibrium Green’s function (NEGF) formalism implemented in SILVACO Atlas TCAD quantum simulation package to closely mimic the actual device physics, together with the judicious choice of the material parameters, models, and suitable discretization of the associated epitaxial layer structure. The validity of the approach was proved by comparing simulated data with experimental measurements resulting from fabricated micrometer-sized RTD devices featuring two different epitaxially grown layer stacks. Our results show that the simulation software can correctly compute the peak current density ${J} _{p}$ , peak voltage ${V} _{p}$ , and the valley-to-peak voltage difference $Delta {V}$ = ${V} _{v} - {V} _{p}$ associated with the negative differential resistance (NDR) region of the RTD heterostructure static current density–voltage ( ${J}$ – ${V}$ ) characteristic at room temperature (RT), all of which are key parameters in the design of these devices for use in oscillator circuits. We believe that this work will now help in optimizing the RTD epitaxial structure to maximize its radio-frequency (RF) power performance, accelerating developments in the rapidly evolving RTD technology for emerging applications, including next-generation ultra-broadband short--ange wireless communication links and high-resolution imaging systems.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • BCM Learning Rules Emulated by a-IGZO-Based Photoelectronic Neuromorphic
           Transistors

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      Authors: Shuo Ke;Chuanyu Fu;Xinhuang Lin;Yixin Zhu;Huiwu Mao;Li Zhu;Xiangjing Wang;Chunsheng Chen;Changjin Wan;Qing Wan;
      Pages: 4646 - 4650
      Abstract: Hardware implementation of Bienenstock–Cooper–Munro (BCM) learning rules would be of great implications toward artificial intelligent systems. In this work, amorphous indium gallium zinc oxide (a-IGZO)-based photoelectronic neuromorphic transistors were proposed for mimicking BCM learning rules. A SiO2 electrolyte film with a large electric-double-layer capacitance ( $0.33~mu text{F}$ /cm2) was used for the gate dielectric film. Light induced short-term synaptic plasticity can be mimicked by such device, including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and high-pass temporal filtering. More importantly, BCM learning rules are realized based on this photoelectronic neuromorphic transistor. These results would provide a step forward the development of photoelectronic neuromorphic systems with sophisticated learning rules.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Verilog-A-Based Analytical Modeling of Vortex Spin-Torque Nano Oscillator

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      Authors: Sonal Shreya;Yasser Rezaeiyan;Alex Jenkins;Tim Böhnert;Hooman Farkhani;Ricardo Ferreira;Farshad Moradi;
      Pages: 4651 - 4658
      Abstract: Topological spin textures are the next-generation spintronic building blocks for storing and processing information because of their controllable formation and annihilation. Memory, logic, and neuromorphic computing applications are reported using such devices having 2-D and 3-D spin textures, namely, vortex, skyrmions, localized bullet, and so on. A robust device-to-circuit-to-system level design is required for developing a neural network (NN) or a neuromorphic computing system (NCS) using these spin devices. Hence, in this work, we present a Verilog-A-based analytical model of a vortex spin-torque nano oscillator (V-STNO) for enabling circuit-level simulation. The model presented here is functional for both linear and nonlinear dynamics of the magnetic vortex core. The nonlinear dynamics show the formation and annihilation of the magnetic vortex depending on its critical currents. Furthermore, the developed model is analyzed for the nanopillar’s diameter and free layer thickness variations. Moreover, an investigation of the temperature effect on the device performance for a range of −40°C to 140 °C is carried out.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Physics and Modeling of Multidomain FeFET With Domain Wall-Induced
           Negative Capacitance

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      Authors: Nilesh Pandey;Yogesh Singh Chauhan;
      Pages: 4659 - 4666
      Abstract: In this article, we present the dynamics and modeling of multidomains in the ferroelectric FET (FeFET). Due to the periodic texture of domains, the electrostatics of the FeFET exhibit an oscillatory conduction band profile. To capture such oscillations, we solve coupled 2-D Poisson’s equation with the net ferroelectric energy density (gradient energy + free energy + depolarization energy) equation. Multidomain dynamics are captured by minimizing the net ferroelectric energy, leading to a thermodynamically stable state. Furthermore, we show that the motion of domain walls originates from local bound charge density in the ferroelectric region, which induces the negative capacitance (NC) effect. The strength of domain wall-induced NC is determined by the gradient energy of the ferroelectric material. FeFET exhibits variability in the drain current with domain period due to the inherent NC effect. Additionally, the impact of domain wall transition (soft $rightleftharpoons $ hard) on the device’s electrostatic/transport is also analyzed. The model also accurately captures both nucleations of a new domain and the motion of the domain wall. Furthermore, the model is thoroughly validated against experimental results and phase-field simulations.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Analysis of Low Frequency Noise in Schottky Junction Trigate Silicon
           Nanowire FET on Bonded SOI Substrate

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      Authors: Yingtao Yu;Zhen Zhang;Si Chen;
      Pages: 4667 - 4673
      Abstract: In this work, low frequency noise (LFN) in Schottky junction trigate silicon nanowire (SiNW) field-effect transistors (FETs) (SJGFETs) fabricated on bonded silicon on insulator (SOI) substrate is systematically analyzed. The LFN exhibited a typical 1/ ${f}$ spectrum and can be well described by the carrier number fluctuation (CNF) with correlated mobility fluctuation (CMF) model. It was found that CNF is the dominant component of the LFN, while CMF associated with the Coulomb scattering near the buried oxide (BOX)/SiNW channel interface plays an insignificant role. Applying a substrate bias can further modulate the LFN of the SJGFETs, and the effect is ascribed to the nonuniform energy distribution of the BOX/SiNW channel interface traps. Confining current path in the channel bulk away from the interface brought limited gain in terms of LFN performance. Finally, our experimental results suggested a possible transition of CMF mechanism from Coulomb scattering to surface roughness scattering when the current path is pushed away from the BOX/SiNW channel interface to the channel bulk.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Design Considerations for 2-D Dirac-Source FETs—Part I: Basic
           Operation and Device Parameters

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      Authors: Peng Wu;Joerg Appenzeller;
      Pages: 4674 - 4680
      Abstract: Dirac-source field-effect transistors (DS-FETs) have been proposed as promising candidates for low-power switching devices by leveraging the Dirac cone of graphene as a low-pass energy filter. In particular, using 2-D materials as the channel in a DS-FET is of interest for ultimate scaling purposes. In this article, we investigate the design considerations for 2-D DS-FETs using ballistic simulations based on the Landauer formalism. We study the impact of several key device parameters on the device performance, such as graphene doping, Schottky barrier heights, and effective mass of the 2-D channel. In Part II of this article, we study the impact of nonidealities on the performance of DS-FETs and benchmark the performance of DS-FETs for different channel materials.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Design Considerations for 2-D Dirac-Source FETs—Part II:
           Nonidealities and Benchmarking

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      Authors: Peng Wu;Joerg Appenzeller;
      Pages: 4681 - 4685
      Abstract: In Part I of this article, we discussed the basic operation of 2-D Dirac-source field-effect transistors (DS-FETs) and studied the impact of key device parameters on the device performance. In this article, we continue to study the impact of nonidealities on the performance of DS-FETs, such as graphene disorder and rethermalization, as well as ways to mitigate them. In addition, we study the performance improvement by introducing a bandgap in the graphene source. Finally, we benchmark the performance of DS-FETs for different channel materials, providing a guide for the proper choice of material for 2-D DS-FETs.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Performance Enhancement and Transient Current Response of Ferroelectric
           Tunnel Junction: A Theoretical Study

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      Authors: Hsin-Hui Huang;Yueh-Hua Chu;Tzu-Yun Wu;Ming-Hung Wu;I-Ting Wang;Tuo-Hung Hou;
      Pages: 4686 - 4692
      Abstract: A comprehensive physical model is established to understand the device operation and optimization strategy of the ferroelectric tunnel junction (FTJ). This model is capable of simulating write (switching polarity), read [tunnel electroresistance (TER)], and ac transient operations with a good agreement with experiments. The strategy of optimizing the thickness of the ferroelectric layer and nonpolar interfacial layer is discussed for enlarging TER ratio. We also discussed the possible misinterpretation of the measured TER ratio according to our model.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical
           Insight

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      Authors: Shobhit Srivastava;Sourabh Panwar;Abhishek Acharya;
      Pages: 4693 - 4699
      Abstract: While considering the low power demand as a fundamental bottleneck for nanoscale devices, this work comprehensively investigates a novel concept that incorporates the area-scaled tunneling in a nanosheet field-effect transistor (NSFET) at a 5-nm technology node. Integrating the area scale tunneling phenomenon with NSFET provides improved electrical performance. We observed ${sim } 50times $ improvement in drain current and $sim 2times $ improvement in subthreshold slope (SS) by incorporating epitaxial layer over the source region underneath the gate. Furthermore, 100 mV of the shift in tunneling onset voltage ( ${V}_{T, mathrm{scriptscriptstyle ON}}$ ) is also noted when source doping increases from $1 times 10^{{18}}$ to $1 times 10^{{20}}$ cm $^{-{3}}$ . The gate–source overlap ( ${L}_{text {OV}}$ ) significantly improves the transconductance without sacrificing the output resistance. It is examined that epitaxial layer thickness ( ${T}_{text {EPI}}$ ) of 3–4 nm gives the best possible drive current for the proposed device. However, the OFF current exhibits an inversely proportional relation with ${T}_{text {EPI}}$ . It is worth highlighting that optimum ${T}_{text {EPI}}$ can be determined by only conside-ing the suitable epitaxial layer doping profile ( ${N}_{text {EPI}}$ ). A linear shift in ${V}_{T, mathrm{scriptscriptstyle ON}}$ of the proposed device with work function (WF) is also reported in our work. Finally, the concept of multiple stacking is explored to boost the device’s performance. Including the presented device design guidelines, the ${I}_{mathrm{scriptscriptstyle ON}}/{I}_{mathrm{scriptscriptstyle OFF}}$ ratio of $sim 4.5 times 10^{{8}}$ with an average SS of ~20 mV/dec is successfully demonstrated for the proposed device.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Time-Division Multiplexing Ising Computer Using Single Stochastic Magnetic
           Tunneling Junction

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      Authors: Yu Liu;Tianqi Gao;Bolin Zhang;Yijiao Wang;Deming Zhang;Lang Zeng;
      Pages: 4700 - 4707
      Abstract: A magnetic tunneling junction (MTJ) with very low energy barrier, which shows controllable stochastic property, is recently proposed to constitute the probability bit (P-Bit). With the P-Bit, Ising computation, which is a general and powerful computing platform for both conventional and non-conventional problems, is implemented. However, such hardware emulation suffers from the severe intrinsic variations of a stochastic MTJ device. The nonuniform probability switching curves of different stochastic MTJs hinder straightforward expansion of Ising computer to a large P-Bits array for solving more complicated problems. In this work, we propose a novel Ising computer using a single stochastic MTJ device. With the utilization of the time-division multiplexing (TDM) technology, a “Compute–Read–Switch” scheme is proposed, so that the single stochastic MTJ can act as multiple P-Bits during Ising computation. A design guide for the current magnitude and time duration of the “Compute–Read–Switch” scheme is investigated and provided. Furthermore, NOT and XOR logic gates are implemented with our proposal. An accuracy rate as high as 69% for the integer factorization is also achieved, which is comparable with conventional Ising computer. Meanwhile, the TDM Ising computer avoids the calibration process, which is mandatory in the conventional Ising computer.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Computationally Efficient Region-Wise Potential- Based Extremely
           Closed-Form Analytical Modeling of B/N Substitution Doped GFETs

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      Authors: L. Chandrasekar;K. P. Pradhan;
      Pages: 4708 - 4716
      Abstract: A simplified region-wise potential-based analytical model is established for boron (B) or nitrogen (N) substitution doped graphene field-effect transistor (GFET). The closed-form direct analytical relation between graphene channel potential and applied bias condition is developed by imposing the effective approximation for Fermi–Dirac integral function in various regions of operation. The boundary for distinct GFET operating regime is separated based on the position of Dirac point and Fermi energy level with respect to applied bias condition. The semiclassical drift and diffusive transport model is utilized to obtain the drain current. In addition to that, the drift component, diffusion coefficient, and its corresponding current component for B and N substitution doped GFETs have been modeled individually and their influence on total current is discussed. The proposed region-potential-based analytical model has shown good agreement with numerically solved self-consistent model. Also, the physical insights in device design, such as threshold voltage and saturation drain potential model with respect to various doping/device parameters, have been examined.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall
           Spacer in Negative Capacitance FinFET

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      Authors: Vibhuti Chauhan;Dip Prakash Samajdar;Navjeet Bagga;
      Pages: 4717 - 4724
      Abstract: Gate sidewall spacers, a pathway to the fringing fields, play a crucial role in the device design. In this article, using well-calibrated TCAD models, we have explored the impact of a sidewall ferroelectric (FE) spacer on a negative capacitance (NC) FinFET. In the proposed study, the FE layer is present beneath the gate electrode and at the spacer region that operates in the NC region. Through three novel FE–dielectric (FE–DE) spacer configurations, we found that proficient electrostatic control can be attained with the optimized stacked placement of the spacers. The fringing fields alter the FE polarization present at the spacer stack and modulates the channel charge, which is a prime objective of this work. Furthermore, we have varied the FE parameters, drain doping, and extension length to optimize the proposed FE–DE spacer configurations. We have done mixed-mode simulations to design an inverter and a three-stage ring oscillator to emphasize our results. The optimized spacer configuration shows~3.9% overshoot due to higher gate capacitance ( ${C}_{GG}$ ); however, the $I_{mathrm{ON}} / I_{mathrm{OFF}}$ ratio is approximately twic than that of the baseline counterpart. The results reveal that the optimized spacer configuration also mitigates the negative differential resistance (NDR), which allows the NC-based devices to be an efficient candidate for analog applications.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Strain Release Enabled Bandgap Scaling in Ge Nanowire and Tunnel FET
           Application

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      Authors: Zhuangzhuang Wang;Yawei Lv;Lining Zhang;Lei Liao;Changzhong Jiang;
      Pages: 4725 - 4729
      Abstract: The cross-sectional scaling-induced electronic property variations of the Ge and Si nanowires are studied numerically. After removing extra atoms from bulk materials to build the nanowires, not only the lateral quantum confinement is enhanced, but also the cross-sectional size will expand due to the breaking of the intrinsic strain balance. Compared with Si, the strain release-induced size expansion is more obvious in the Ge nanowires, shrinking the bandgaps and thus providing another bandgap modulation direction relative to the quantum confinement. At specific sizes, the strain release effect dominates the modulation and reduces the bandgaps of Ge nanowires even below the bulk value, while the reductions in Si nanowires are negligible, enlarging the band offsets of their heterostructures. As an application, the Ge/Si heterostructure tunnel FET (TFET) is designed and the TCAD simulation reveals a subthreshold swing (SS) of 13.8 mV/dec and an ON-state current of $93 ~mu text{A}/mu text{m}$ , three orders of magnitude larger than that using the bulk materials.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

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      Authors: Renan Trevisoli;Marcelo A. Pavanello;Rodrigo T. Doria;Carlos E. Capovilla;Sylvain Barraud;Michelly de Souza;
      Pages: 4730 - 4736
      Abstract: This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Bending Resistant Multibit Memristor for Flexible Precision Inference
           Engine Application

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      Authors: Parthasarathi Pal;Ke-Jing Lee;Sunanda Thunder;Sourav De;Po-Tsang Huang;Thomas Kämpfe;Yeong-Her Wang;
      Pages: 4737 - 4743
      Abstract: This work reports 2-bits/cell hafnium oxide-based stacked resistive random access memory devices fabricated on flexible polyimide substrates for neuromorphic applications considering the high thermal budget. The ratio of low-resistance state current ( ${I}_{ mathrm{scriptscriptstyle ON}}$ ) to high-resistance state current ( ${I}_{ mathrm{scriptscriptstyle OFF}}$ ) or ${I}_{ mathrm{scriptscriptstyle ON}}/{I}_{ mathrm{scriptscriptstyle OFF}}$ for the fabricated devices was above $1.4times10$ 3 with a low device-to-device variation at $100 boldsymbol {mu }text{A}$ current compliance. The mechanical stability over 104 bending cycles at a 5 mm bending radius and endurance over 106 WRITE cycles makes these devices suitable for online neural network training. The data retention capability over 104s at 125°C also infuses these devices’ long-term inference capability. Furthermore, the performance of the devices has been verified for neuromorphic applications by system-level simulations with experimentally calibrated data. The system-level simulation reveals only a 2% loss in inference accuracy over ten years from the baseline.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Electrical Investigation of Wake-Up in High Endurance Fatigue-Free La and
           Y Doped HZO Metal–Ferroelectric–Metal Capacitors

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      Authors: Amey M. Walke;Mihaela I. Popovici;Kaustuv Banerjee;Sergiu Clima;Pankaj Kumbhare;Johan Desmet;Johan Meersschaut;Geert Van den Bosch;Romain Delhougne;Gouri Sankar Kar;Jan Van Houdt;
      Pages: 4744 - 4749
      Abstract: High endurance of 1011 cycles is demonstrated in ~9–10-nm stoichiometric Hafnium Zirconate (HZO) metal–ferroelectric–metal (MFM) capacitors deposited using Cl precursors with La and Y dopants. La doping is shown to offer higher remnant polarization than Y. Investigation of doped layers with asymmetric polarization versus electric field ( ${P}$ – ${E}$ ) measurements and unipolar fatigue cycles suggests that in the pristine state, the HZO is comprised of ferroelectric domains with internal built-in electric field-induced pinned coercive field ( ${E}_{c}$ ). Doping is shown to increase the pinning effect and two distinct groups of ferroelectric domains emerge, which is antialigned at zero applied electric field ( ${E}$ ). The antiferroelectric-like (pinched ${P}$ – ${E}$ loop) behavior is therefore attributed to internal built-in ${E}$ -induced pinning of the domains during growth and/or annealing steps. The initial wake-up is attributed to gradual depinning of the domains with bipolar electric pulses. Suppression of monoclinic phase was observed in doped layers that survive 1011 cycles. The wake-up is shown to be dependent on total duration and magnitude of bipolar electric pulses. Precycling scheme is demonstrated for stable operation at a lower field.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Impact of Trap Profile on the Characteristics of 2-D MoS2 Memtransistors:
           A Simulation Study

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      Authors: Panpan Zhang;Xuewei Feng;Xuanyao Fong;
      Pages: 4750 - 4756
      Abstract: The multiterminal memtransistor based on trap-rich transition metal dichalcogenide (TMD) materials has gained significant research interest due to their ability to mimic both homosynaptic and heterosynaptic plasticity. However, the current understanding of the underlying device physics remains somewhat lacking. In this article, we use a quasi-static technology computer-aided design (TCAD) model for the memtransistor based on molybdenum disulfide (MoS2) to investigate the role of the trap profile in the electrical properties. Assuming a Gaussian trap profile within the monolayer MoS2, the simulation results using our experimentally calibrated TCAD model show that tunneling width and Schottky barrier (SB) height at the contact can be modulated by shifts in the trap profile. In contrast to previous observations, we found that the presence of traps directly beneath the source contact in the MoS2 dopes the channel and forms an accumulation region, which allows for the injection of carriers vertically from the source into the accumulation region. Moreover, the trap profile may dramatically affect the Fermi level and the surface potential of the channel, which may be attributed to the quantum capacitance and inhomogeneous trap-related capacitances. The quantum capacitance, ${C}_{text {q}}$ , is extracted to be 1.8 $mu text {F/cm}^{{2}}$ , whereas the equivalent total trap capacitance, ${C}_{text {trap}}$ , is 0.9–1.8 $mu text {F/cm}^{{2}}$ (depending on the trap profile). Our findings indicate a much more complicated relationship between the trap profile and the electrical properties of MoS2 memtransistors than previousl- understood.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Exploration on Electrical Isolation Between High-Voltage SiC Thyristor and
           Small-Signal Devices for Smart Power Devices

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      Authors: Shiwei Liang;Hangzhi Liu;Hengyu Yu;Bingru Chen;Jun Wang;Gaoqiang Deng;Z. John Shen;
      Pages: 4757 - 4760
      Abstract: The Smart Discrete concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • A Compact Model of Nanoscale Ferroelectric Capacitor

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      Authors: Chien-Ting Tung;Girish Pahwa;Sayeef Salahuddin;Chenming Hu;
      Pages: 4761 - 4764
      Abstract: In this brief, we present a compact model of nanoscale ferroelectric (FE) capacitors. We first use the phase-field simulation to study the polarization switching of very small FE capacitor that contains only a few grains. We show that at higher applied voltage, the entire grain undergoes a single-domain-like switching, but at lower applied voltage, the domain wall growth mechanism dominates due to the difference between the domain wall energies of bulk and defect nuclei. To create a compact model that includes this voltage dependence, we use a time-dependent domain switching model for each discrete grain with empirical modifications capturing the two different switching mechanisms. In addition, a voltage-dependent dielectric model is included to represent the nonlinear capacitance of the FE capacitor. We verify this compact model by fitting the results of phase-field modeling results with excellent agreement.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET

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      Authors: Ming-Yen Kao;Fredo Chavez;Sourabh Khandelwal;Chenming Hu;
      Pages: 4765 - 4768
      Abstract: A new deep learning (DL)-based parameter extraction method is presented in this brief; 50k training cases are generated by Monte Carlo simulations of these preselected parameters in Berkeley short-channel IGFET model (BSIM)-common multigate (CMG). DL models are trained using backward propagation with ${C} _{text {gg}} - {V} _{g}$ and ${I} _{d} - {V} _{g}$ as the input and selected BSIM-CMG parameters as the output. A TCAD simulated FinFET device, calibrated to Intel 10-nm node, is used to test the DL models. The DL-based parameters extraction results show an excellent fit to capacitance and drain current data, with 0.16% rms error in ${C} _{text {gg}} - {V} _{g}$ and 6.1% rms error in ${I} _{d} - {V} _{g}$ (0.69% rms error in above-threshold-voltage ${I} _{d} - {V} _{g}$ ), respectively. In addition, devices with a 10% variation in gate length and oxide thickness are successfully modeled with the trained DL model. The results show tremendous promise in using the DL-based models for parameter extraction.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • Dielectrics for 2D electronics

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      Pages: 4769 - 4770
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
  • From Mega to nano: Beyond one Century of Vacuum Electronics

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      Pages: 4771 - 4772
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Aug. 2022
      Issue No: Vol. 69, No. 8 (2022)
       
 
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