A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

  Subjects -> ELECTRONICS (Total: 207 journals)
The end of the list has been reached or no journals were found for your choice.
   Most Followed Journals

   Top Publishers

   Top Subjects
Similar Journals
Journal Cover
IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 17  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [228 journals]
  • IEEE ELECTRON DEVICES SOCIETY

    • Free pre-print version: Loading...

      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • IEEE Transactions on Electron Devices information for authors

    • Free pre-print version: Loading...

      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Blank Page

    • Free pre-print version: Loading...

      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Editorial Special Issue on Dielectrics for 2-D Electronics

    • Free pre-print version: Loading...

      Authors: Mario Lanza;Kin-Leong Pey;Tibor Grasser;
      Pages: 1451 - 1453
      Abstract: It is our great pleasure to introduce this Special Issue on Dielectrics for 2-D Electronics to the IEEE TRANSACTIONS ON ELECTRON DEVICES readership. This Special Issue features the latest research aiming to clarify which would be the most suitable dielectric materials for state-of-the-art electronic devices containing 2-D materials.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Dielectric Material Technologies for 2-D Semiconductor Transistor Scaling

    • Free pre-print version: Loading...

      Authors: Yuxuan Cosmi Lin;Cheng-Ming Lin;Hung-Yu Chen;Sam Vaziri;Xinyu Bao;Wei-Yen Woon;Han Wang;Szuya Sandy Liao;
      Pages: 1454 - 1473
      Abstract: The 2-D semiconductors have been recognized as promising channel materials for the ultimately scaled transistor technologies beyond silicon. An essential technology enabler for 2-D semiconductor electronics is the development of dielectric materials interfaced with 2-D semiconductors. In this review article, we overview different types of dielectric materials that are suitable for different application scenarios, including high- ${k}$ gate dielectrics, low- ${k}$ spacers, and thermal management materials under the paradigm of 2-D semiconductor electronics. A material selection guideline for dielectric materials and the key process technology modules are discussed in detail. A special emphasis is made on how each of the dielectric technologies may enable the further scaling and practical applications of 2-D semiconductor transistors. The state-of-the-art device technologies are summarized, and the remaining challenges toward practical applications are discussed from the industrial perspective.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Dielectrics for 2-D Electronics: From Device to Circuit Applications

    • Free pre-print version: Loading...

      Authors: Anhan Liu;Xueyang Peng;Songang Peng;He Tian;
      Pages: 1474 - 1498
      Abstract: 2-D electronics is an important pathway to develop advanced monolithic integrated circuits. Due to the nature of the van der Waals force between 2-D materials and dielectrics, it is a challenge to fabricate high-quality dielectrics for 2-D materials. Here, we first review the situation of traditional insulators for 2-D field-effect transistors (FETs). The progress made in the development of new dielectric materials and advanced preparation methods is summarized. Moreover, we also discuss the application of insulators in novel device structures, arrays, and circuits. Finally, we present a perspective on the promising pathways of insulators for 2-D FETs and obstacles to the commercial application of 2-D electronics.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Probing Gate Dielectrics for Two-Dimensional Electronics at Atomistic
           Scale Using Transmission Electron Microscope

    • Free pre-print version: Loading...

      Authors: Chen Luo;Tao Xu;Zhihao Yu;Xinran Wang;Litao Sun;Junhao Chu;Xing Wu;
      Pages: 1499 - 1508
      Abstract: Layered materials with thermodynamical stability and scalable atomic thickness provide a potential solution for insulators in 2-D electronics. The formation of high-quality van der Waals interfaces provides potential solutions to overcome the present limit of gate control. To enhance the reliability and robustness of the 2-D device, the investigation of degradation kinetics and fundamental physics of breakdown events of layered dielectrics at an atomistic scale is important. However, the sub-nanometer thickness of layered gate stacks and complex interface states affected by atomic/electronic structures of local defects, which makes the breakdown mechanism research challenging. Advanced characterization technique with simultaneous analysis of elements, energy, and structure at an atomistic scale is crucial. Transmission electron microscope (TEM) is such a powerful tool to analyze the morphology, chemical composition, crystal structure, and electronic structure. In this review, the breakdown mechanism of layered insulators is summarized and discussed in depth at the atomistic scale. The challenges, which are important for the development of layered gate insulators, are also discussed.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Lanthanum Oxyhalide Monolayers: An Exceptional Dielectric Companion to 2-D
           Semiconductors

    • Free pre-print version: Loading...

      Authors: Zhuoling Jiang;Tong Su;Cherq Chua;L. K. Ang;Chun Zhang;Liemao Cao;Yee Sin Ang;
      Pages: 1509 - 1519
      Abstract: The 2-D-layered dielectrics offer a compelling route toward the design of next-generation ultimately compact nanoelectronics. Motivated by recent high-throughput computational prediction of LaO ${X}$ ( ${X}$ = Br and Cl) as the exceptional 2-D dielectrics that significantly outperform HfO2 even in the monolyaer limit, we investigate the interface properties between LaO ${X}$ and the archetypal 2-D semiconductors of monolayer transition metal dichacolgenides (TMDCs) ${M}text{S}_{{2}}$ ( ${M}$ = Mo and W) using the first-principle density functional theory (DFT) simulations. Because of interfacial charge transfer and the presence of interface dipole potential, the conduction and valance band offsets (VBOs) cannot be simply determined using Anderson’s rule. DFT calculations at the HSE06 level reveal exceptionally large band offsets between 1.12 and 2.40 eV. Based on the Murphy–Good electron emission model, we show that LaO ${X}$ is an excellent companion dielectric to ${M}text{S}_{{2}}$ for both NMOS and PMOS applications, with leakage currents much lower than ${10}^{-{2}}$ Acm $^{-{2}}$ . The presence of an interfacial tunneling potential barrier at the van der Waals gap (vdWG) further provides an additional mechanism to suppress the leakage current. Ou- findings reveal the promising role of LaO ${X}$ toward high-performance 2-D semiconductor transistor technology.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Two-Dimensional Van Der Waals Hafnium Disulfide and Zirconium Oxide-Based
           Micro-Interdigitated Electrodes Transistors

    • Free pre-print version: Loading...

      Authors: Shivani Sharma;Subhashis Das;Robin Khosla;Hitesh Shrimali;Satinder K. Sharma;
      Pages: 1520 - 1526
      Abstract: There are indelible challenges related to transistor action and realization of emerging two-dimensional van der Waals (vdW) multilayer (2D $_{{mathrm {ml}}}$ ) field-effect transistors (FETs), to the post silicon technology era. For scalability, a cost-effective large area ultrafine thin films interface and band alignment of multilayer channel material with compatible gate dielectric are essential. Here, 2D $_{{mathrm {ml}}}$ hafnium disulfide (HfS2) and ZrO2 are employed as channel material and gate dielectric, respectively, and anticipated that vdW interaction of said structures entails the high-quality interface with trivial dangling bonds and defects caused by lattice mismatch. The investigated Al/ZrO2/HfS2/Al $_{mu {text{-IDE}}}$ FETs exhibit the subthreshold swing (SS) ~65 mV/dec, ${I}_{ mathrm{scriptscriptstyle ON}}/I_{ mathrm{scriptscriptstyle OFF}}$ ratio of ~104, transconductance of ~3.99 $mu text{S}$ , effective mobility of ~74 cm2/Vs at ${V}_{{mathrm {gs}}}$ of 2 V, and leakage current density of ~33.8 nA/cm2 at ${V}_{{mathrm {gs}}}$ of −1 V. Thus, the steep SS, sturdy current saturation, low-voltage operation (~3 V), and leakage current establish the potential candidature of HfS2 and ZrO2-based 2-D FETs for both conventional and ubiquitous electronics.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Analytical Scaling of Trap-Limited Current in 2-D Ultrathin Dielectrics

    • Free pre-print version: Loading...

      Authors: Chun Yun Kee;Yee Sin Ang;Er-Ping Li;L. K. Ang;
      Pages: 1527 - 1532
      Abstract: For charge injection from an electrode into a trap-filled dielectric slab, its current–voltage ( ${I}$ – ${V}$ ) characteristics are governed by the Mark–Helfrich (MH) law. By matching the experimentally measured ${I}$ – ${V}$ characteristics to a right ${I}$ – ${V}$ model, one can characterize the microscopic properties of the dielectric like its carrier mobility and traps distribution. The original MH law was developed for a bulk solid and may not be valid for modern ultrathin dielectrics used in 2-D electronics. Here, we revise the MH law for an ultrathin trap-filled dielectric of length ${L}$ biased with a voltage of ${V}$ . Our model suggests a new scaling of the current line density: $mathcal {J}_{text {2-D}} ,,propto ,,{[}{({V}}/{alpha {L}{)}} text {exp}{(} - {(beta {l}}/{l+{1}}{)}{)} {]}^{l+{1}}$ , where $alpha $ = (2.8, 2.03) and $beta $ = (1.02, 0.94) are numerical values for two different geometrical (edge, strip) contacts, respectively. Using this 2-D ultrathin MH law, we demonstrate that the estimated carrier mobility can be signifi-antly different from the traditional MH law. Under the same material properties, our model also highlights that strip contact geometry will always lead to a larger current flow than edge contact geometry. Thus, the developed model should be useful for the characterization of the ultrathin dielectrics used in 2-D materials-based electronics, organic semiconductors, and thin-film electronics.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Modeling the Variability of Au/Ti/h-BN/Au Memristive Devices

    • Free pre-print version: Loading...

      Authors: Juan B. Roldan;David Maldonado;C. Aguilera-Pedregosa;Francisco J. Alonso;Yiping Xiao;Yaqing Shen;Wenwen Zheng;Yue Yuan;Mario Lanza;
      Pages: 1533 - 1539
      Abstract: The variability of memristive devices using multilayer hexagonal boron nitride (h-BN) coupled with Ti and Au electrodes (i.e., Au/Ti/h-BN/Au) is analyzed in depth using different numerical techniques. We extract the reset voltage using three different methods, quantify its cycle-to-cycle variability, calculate the charge and flux that allows to minimize the effects of electric noise and the inherent stochasticity of resistive switching, describe the device variability using time series analyses to assess the “memory” effect, and employ a circuit breaker simulator to understand the formation and rupture of the percolation paths that produce the switching. We conclude that the cycle-to-cycle variability of the Au/Ti/h-BN/Au devices presented here is higher than that previously observed in Au/h-BN/Au devices, and hence, they may be useful for data encryption.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Ultraviolet Photoresponse Enhancement of Graphene/Al x O y -NPs/MoS2
           Heterostructure Photodetectors

    • Free pre-print version: Loading...

      Authors: Han-Hsiang Tai;Jer-Chyi Wang;Wen-Hao Chang;Fong-Zhi Chen;Chao-Sung Lai;
      Pages: 1540 - 1547
      Abstract: Molybdenum disulfide (MoS2) has been widely used to fabricate the photodetectors in recent years due to its excellent optical properties. However, the narrow detection bandwidth of MoS2 films limits their applications. Here, a thin Al film was deposited on the surface of MoS2 and naturally oxidized to form the AlxOy nanoparticles (AlxOy-NPs) for the enhanced performance of graphene/AlxOy-NPs/MoS2 heterostructure photodetectors. The material analyses were performed to confirm the formation of AlxOy-NPs on MoS2 and its influence on light absorption. Additionally, the photoresponse of graphene/AlxOy-NPs/MoS2 heterostructure photodetectors was investigated, and found that the localized surface plasmon resonance (LSPR) was induced in the ultraviolet-A (UV-A) band (365 nm), increasing the photocurrent owing to the p-type nature of graphene channel with the recombination of excited electrons from AlxOy-NPs/MoS2 to enhance the photoresponse. The photodetectors with an AlxOy film of 0.5 nm presented a UV-A light detection capability with the photoresponsivity, quantum efficiency, and detectivity of 6.24 A/W, 2120%, and $1.79times 10^{{10}}$ Jones, respectively, at the optical power of 10 mW/cm2. Thus, the proposed one-step growth method of AlxOy-NPs on MoS2 films to fabricate the graphene/AlxOy-NPs/MoS2 heterostructure photodetectors with excellent photoresponse can facilitate the development of novel 2-D material photodetectors in future.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Plasma Jet Printing: An Introduction

    • Free pre-print version: Loading...

      Authors: Jacob Manzi;Nirmala Kandadai;Ram P. Gandhiraman;Harish Subbaraman;
      Pages: 1548 - 1553
      Abstract: Plasma jet printing is an emerging alternative to popular 2-D printing techniques, such as inkjet and aerosol jet printing. The inherent nature of the plasma provides films with good adhesion upon printing without the need for thermal sintering. The reduced logistics and the ability to print a wide range of materials on rigid and flexible substrates make it a valuable technique for printed and flexible electronics. In this tutorial article, we discuss the principles behind plasma printing, printer hardware, and printing mechanisms and provide representative print results.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Suppression of Threshold Voltage Variation by TiN Surface Treatment for
           N-FinFETs With Very Thin Work Function Metal Layers

    • Free pre-print version: Loading...

      Authors: Tao Huang;Run-Ling Li;Han-Lun Cai;Zhao-Yang Li;Yu-Long Jiang;
      Pages: 1554 - 1559
      Abstract: In this work, from the viewpoint of process integration the threshold voltage ( ${V}_{t}$ ) variation for multi- ${V}_{t}$ FinFETs fabricated by changing work function metal (WFM) TiN thickness is investigated. Four kinds of WFM thickness are prepared by the combination of three times atomic layer deposition (ALD) and three times wet etching of TiN layers. In the whole four- ${V}_{t}$ process integration scheme, it is revealed that the ${V}_{t}$ variation is very large for N-FinFET with only one layer of TiN. It is further observed that this TiN layer is partially eroded, although it should be protected by a photoresist during wet etching. It is proposed and demonstrated that the additional high-temperature prebaking treatment before spin-coating of the bottom anti-reflection coating (BARC) on the TiN surface can reduce the unexpected erosion of the TiN layer coated by photoresist, resulting in the effective suppression of ${V}_{t}$ variation.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • High Voltage PDMOS Device Design Against Breakdown Voltage Walk-In

    • Free pre-print version: Loading...

      Authors: Edward Coyne;Edward Aiguo Wang;
      Pages: 1560 - 1565
      Abstract: This article studies the design strategy to build operating and manufacturing robustness into a metal and polysilicon field plate-assisted Reduced Surface Field Effect (RESURF) $vert 225 text{V}vert $ P-type double diffuse metal oxide silicon (PDMOS) device against Breakdown Voltage Walk-In. The article uses technology computer-aided design (TCAD) to calibrate the unique walk-in properties of charge trapping along the thermal oxide interface of the extended drift region with a trap density of $7{e}^{{11}}$ eV $^{-{1}}$ cm $^{-{2}}$ , a trap occupancy breakdown voltage temperature coefficient of 1.9 V/K, and a breakdown voltage walk-in plateau of −133 V determined by the opposing electric field from the fully occupied traps inhibiting the resurf mechanism. Using this calibration, the article goes on to solve the walk-in mechanism by using a junction resurf field plate buried in the silicon lattice to create an electric field from the depleted dopant that balances the effects of the oxide-trapped charges. The design of the buried resurf field plate is optimized with TCAD for a robust $vert 225 text{V}vert $ operating voltage. This robustness is confirmed with measured silicon data.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Gate-Controlled LVTSCR for High-Voltage ESD Protections in Advanced CMOS
           Processes

    • Free pre-print version: Loading...

      Authors: Ruibo Chen;Hongxia Liu;Cong Yan;Feibo Du;Aoran Han;Yuxin Zhang;Wei Huang;Qi Xiang;Tianzhi Gao;Hao Wei;Zhiwei Liu;
      Pages: 1566 - 1573
      Abstract: In this article, a novel high robust and latch-up immune electrostatic discharge (ESD) protection device, called gate-controlled low-voltage-triggered silicon-controlled rectifier (GC-LVTSCR), is proposed for 5-V I/O protection applications in the advance 40-nm CMOS technology. By incorporating a surface current diverting path with a controlling poly-silicon gate (CG) into the conventional LVTSCR, the GC-LVTSCR’s ESD characteristics can be improved and modulated with two bias conditions of CG. The first improved GC-LVTSCR structure named gate-to-body SCR (GBSCR) with the CG tied to the PWell’s body is expected to realize higher holding voltage ( ${V}_{text {h}}{)}$ and lower trigger voltage ( ${V}_{text {t1}})$ , while the other structure named gate-to-drain SCR (GDSCR) using the CG connected to the bridging p+ region of LVTSCR is designed to gain even higher ${V}_{text {h}}$ . Measurement results show that the GBSCR has $sim $ 11% lowered ${V}_{text {t1}}$ , $sim $ 38% enhanced ${V}_{text {h}}$ , and improved charged device model (CDM) characteristics by comparing with the traditional LVTSCR, and the GDSCR possesses a further improved ${V}_{text {h}}$ with $sim $ 45% higher than the GBSCR. Besides, the new d-vices are expected to protect 5 V or above I/O in submicrometer technologies and have been realized in a 0.18- $mu text{m}$ BCD process.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Analytical Physics-Based Modeling of Electron Channel Density in Nanosheet
           and Nanowire Transistors

    • Free pre-print version: Loading...

      Authors: G. I. Zebrev;D. S. Malich;
      Pages: 1574 - 1579
      Abstract: We propose a general physics-based approach for an accurate analytical calculation of the channel charge density in field-effect transistors as a function of the external gate biases. This approach is based on consistent consideration of basic electrostatic equation as a balance of electric and chemical potentials which allows us to obtain in a unified way the explicit analytic expressions continuously describing the subthreshold and above threshold regions in the nanosheet (symmetric and asymmetric) and nanowire FETs. Two conceptually different definitions of phenomenological threshold voltage are consistently introduced and discussed.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Physics-Based Compact Model for Silicon Cold-Source Transistors

    • Free pre-print version: Loading...

      Authors: Anirban Kar;Keshari Nandan;Yogesh Singh Chauhan;
      Pages: 1580 - 1588
      Abstract: Silicon-based cold-source transistors are promising for energy-efficient logic switches and hence for semiconductor technology node scaling due to their subthermal switching capability, good ON-state performance, and compatibility with existing process technology. Owing to the importance of compact models in advancing semiconductor technology, we propose a compact model for silicon-based dual-gate cold-source field-effect transistors (DG-CSFETs). Our core model is charge-based and provides an explicit solution for surface potential, terminal charges, and drain current. The density of the cold carrier in the channel injected from the source is included physically in the developed model. In addition, we include the impacts associated with small device geometry. Furthermore, we verify the developed model against quantum transport simulations. Our model accurately captures the drain-current behavior with different geometric parameter scaling. To the best of our knowledge, this is the first compact model developed for cold-source transistors.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Impact of Lanthanum-Induced Dipoles on the Tunneling and Dielectric
           Properties of Gate-Stack

    • Free pre-print version: Loading...

      Authors: Zhongshan Xu;Guo-Dong Zhao;Rongzheng Ding;Yage Zhao;Qing Xie;Yudong Lv;Mingyan Chen;Xiaona Zhu;Shaofeng Yu;
      Pages: 1589 - 1594
      Abstract: Threshold voltage ( ${V_{t}}$ ) engineering is critical and challenging in the advanced logic devices. Inducing interface dipoles by the incorporation of dopants into the gate dielectrics is an emerging scheme to modulate the threshold voltage. However, the impact of those dipoles on gate-stack performance is of great concern. In this work, we present the first-principles calculations of dielectric constant and tunneling current of high- ${k}$ gate-stack with lanthanum (La) dopants. It is found that incorporation of La improves the local dielectric constant as well as the equivalent oxide thickness (EOT), but degrades the gate leakage current. The calculated results are consistent with the reported experimental data. Furthermore, by analyzing the transmission coefficients and band alignment across the gate-stack, a theoretical explanation for the change of gate leakage current is provided.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Temperature Effects on Electrical Response of FinFET Transistors in the
           Static Regime

    • Free pre-print version: Loading...

      Authors: Faouzi Nasri;Najeh Rekik;Haifa Bahri;Umer Farooq;A. Wahab M. A. Hussein;Hira Affan;Abdelhamid Alabid;Bachir Ouari;
      Pages: 1595 - 1600
      Abstract: The aim of this work is to develop an electrothermal model capable of predicting the FinFET operating temperature in different drain and gate biases with different gate lengths. A new effective electron mobility that depends on mobility degradation due to phonon scattering, surface roughness, and to Colombian interaction is used to enhance the drift-diffusion (D-D) model. To better investigate the electrical characteristics, heat conduction equation is coupled with the D-D model. To achieve high evidence to the proposed model, the simulation of ID-VG and ID-VD is compared with experimental data and Monte Carlo (MC) simulation, and a good concordance is observed. The output characteristics degradation due to device temperature is analyzed. We demonstrated that a drain current of 1 mA/_m is obtained when the operating temperature is around 360 K for a 20-nm FinFET. The effect of FinFET biases on power dissipation and device temperature along the channel region and in the drain side channel region interface is investigated for 10- and 20-nm FinFET gate lengths. We found that: 1) the power dissipation is four times greater when the gate length decreases from 20 to 10 nm and 2) the critical temperature, which is responsible to vanish the drain current, is from 380 to 460 K for Lg = 20 and 10 nm, respectively. This work addresses a key reliability constraint for CMOS-based FinFET circuit designers while designing tuned gate and drain biases circuit.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Vertical GaN Schottky Barrier Diode With Record Low Contact Resistivity on
           N-Polarity Using Ultrathin ITO Interfacial Layer

    • Free pre-print version: Loading...

      Authors: Xinke Liu;Haofan Wang;Junye Wu;Ping Zou;Yudi Tu;Shaojun Chen;Xinbo Xiong;Xinzhong Wang;Jiajun Han;Wenrong Zhuang;Zhichao Yang;Feng Qiu;Hsien-Chin Chiu;Ze Zhong;
      Pages: 1601 - 1606
      Abstract: In this article, an ohmic contact structure based on indium tin oxide (ITO)/Ti/Al/Ni/Au is explored for high-performance GaN-on-GaN Schottky barrier diode (SBD) for the first time. Owing to the ultrathin ITO interfacial layer, the Fermi-level pinning (FLP) effect in metal-semiconductor interface could be mitigated, thus the specific contact resistivity ( $rho _{c}{)}$ on N-polarity was reduced from $3.32times 10^{-{3}}$ to $7.36times 10^{-{5}},,Omega $ cm2, and the specific ON-resistance ( ${R}_{text {ON}}{)}$ of the device was reduced from 3.14 to 1.17 $text{m}Omega $ cm2 under the same testing condition. With the Helium ion implantation technology, a high breakdown voltage ( ${V}_{text {BR}}{)}$ of 1100 V, low turn-on voltage ${V}_{text {ON}}$ of 0.63 V, and a high figure of merit ( ${V}_{text {BR}}^{{2}}/{R}_{text {ON}}{)}$ of 1.04 GW/cm2 were achieved in this work. The vertical GaN SBD with ITO interfacial layer fabricated in this work achieved the lowest $rho _{c}$ in the reported GaN-on-GaN SBDs with an indicated anode size.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Study of TaN-Gated p-GaN E-Mode HEMT

    • Free pre-print version: Loading...

      Authors: Rijo Baby;K. Reshma;Hareesh Chandrasekar;Rangarajan Muralidharan;Srinivasan Raghavan;Digbijoy N. Nath;
      Pages: 1607 - 1612
      Abstract: We report on the study of tantalum nitride (TaN) gate-stack on p-GaN-based e-mode high electron mobility transistor (HEMT) on silicon. Besides offering an excellent etch selectivity of >1:30 over p-GaN under Cl2/O2/Ar-based dry etch, which is promising for self-aligned gate etch process, TaN-gated HEMTs exhibited three orders of lower forward gate leakage than reference devices with Ti/Au gate-stack. At 150 °C, the forward gate leakage was still found to be about $60~mu text{A}$ /mm at ${V}_{G} =$ 8 V. The threshold voltage ( ${V}_{text {th}}$ ) defined at 1 mA/mm was found to be 2.4 V for the TaN-based HEMTs. The gate Schottky barrier height was estimated to be about 1–1.5 eV higher than that for Ti/Au gate over a temperature range of 50–300 K as extracted from the gate leakage fit to Fowler–Nordheim (FN) tunneling. The effect of drain and forward gate bias stress on the dynamic ON-resistance recovery and ${V}_{text {th}}$ instability was studied. TaN-gated devices exhibited a ${V}_{text {th}}$ shift of 2%, while for the Ti/Au counterparts, it was about 10%–15% when subjected to an identical gate–drain forward stress, indicating that TaN is an attractive gate-stack for p-GaN e-mode HEMTs.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • GaN-Based Double-Heterojunction Bipolar Transistors With a Composition
           Graded p-InGaN Base

    • Free pre-print version: Loading...

      Authors: Shumeng Yan;Yu Zhou;Jianxun Liu;Yaozong Zhong;Xiujian Sun;Xin Chen;Xiaolu Guo;Qian Li;Qian Sun;Hui Yang;
      Pages: 1613 - 1621
      Abstract: The influence of energy band structure on the electrical characteristics of GaN-based double-heterojunction bipolar transistors (DHBTs) has been studied through both simulation and fabrication. According to the simulation result, a novel DHBT structure with a composition graded base was grown and fabricated. A long minority carrier lifetime of 4.08 ns has been achieved for the composition graded p-InGaN base with a greatly improved material quality. The indium composition grading of the p-InGaN base layer combined with Si doping profile tuning for the collector layer was proposed to eliminate the energy barrier usually formed at the conventional GaN/InGaN/GaN base–collector (B–C) junction interface due to the band discontinuity and polarization effect. As a result, the as-fabricated DHBT presents a high intercept voltage of 225 V extracted from the ${I}_{C}$ – ${V}_{text {CE}}$ curves and a high current gain of 49.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Compensation Dopant-Free GaN-on-Si HEMTs With a Polarization Engineered
           Buffer for RF Applications

    • Free pre-print version: Loading...

      Authors: Aniruddhan Gowrisankar;Vanjari Sai Charan;Hareesh Chandrasekar;Anirudh Venugopalarao;R. Muralidharan;Srinivasan Raghavan;Digbijoy N. Nath;
      Pages: 1622 - 1627
      Abstract: We report on the performance of compensation doping-free aluminum gallium-nitride (AlGaN)/gallium-nitride (GaN) high-electron mobility transistors (HEMTs) realized using a polarization-graded buffer scheme on Silicon for RF applications. We use a compositionally reverse-graded AlGaN (g-AlGaN) layer to engineer a resistive buffer, which in addition to acting as a back-barrier, circumvent the need for compensation dopants such as Fe or C. As a proof of concept, we have demonstrated transistors with $0.35~mu text{m}$ gate length and source-connected field plates. Devices exhibit a maximum drain current of 1 A/mm and OFF-state breakdown voltage of 144 V. Gate- and drain-lag pulsed ${I}$ – ${V}$ measurements show very low-current collapse (CC) indicating minimal buffer- and surface-trapping. Further evidence from substrate ramp characterization shows positive charge storage in the buffer, indicating a reduced buffer back-gating effect under dynamic conditions. RF performance of HEMTs on these polarization-graded buffers is reported with a peak ${f}_{t}/{f}_{text {max}}$ of 49.2/86.4 GHz. Load-pull measurements at 10 GHz yielded an output power of 1.45 W/mm with a power-added efficiency (PAE) of 11%.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Transient Thermal Management of a β-Ga₂O₃ MOSFET Using a Double-Side
           Diamond Cooling Approach

    • Free pre-print version: Loading...

      Authors: Samuel H. Kim;Daniel Shoemaker;Andrew J. Green;Kelson D. Chabak;Kyle J. Liddy;Samuel Graham;Sukwon Choi;
      Pages: 1628 - 1635
      Abstract: $beta $ -phase gallium oxide ( $beta $ -Ga2O3) has drawn significant attention due to its large critical electric field strength and the availability of low-cost high-quality melt-grown substrates. Both aspects are advantages over gallium nitride (GaN) and silicon carbide (SiC) based power switching devices. However, because of the poor thermal conductivity of $beta $ -Ga2O3, device-level thermal management is critical to avoid performance degradation and component failure due to overheating. In addition, for high-frequency operation, the low thermal diffusivity of $beta $ -Ga2O3 results in a long thermal time constant, which hinders the use of previously developed thermal solutions for devices based on relatively high thermal conductivity materials (e.g., GaN transistors). This work investigates a double-side diamond-cooled $beta $ -Ga2O3 device architecture and provides guidelines to maximize the device’s thermal performance under both direct current (dc) and high-frequency switching operation. Under high-frequency operation, the use of a $beta $ -Ga2O3 composite substrate (bottom-side cooling) must be augmented by a diamond passivation overlayer (top-side cooling) because of the low thermal diffusivity of $beta $ -Ga2O3.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • GaN-on-Si Quasi-Vertical p-n Diode With Junction Termination Extension
           Based on Hydrogen Plasma Treatment and Diffusion

    • Free pre-print version: Loading...

      Authors: Xuan Liu;Maojun Wang;Jin Wei;Cheng P. Wen;Bing Xie;Yilong Hao;Xuelin Yang;Bo Shen;
      Pages: 1636 - 1640
      Abstract: Utilizing hydrogen plasma treatment and controlled diffusion, a junction termination extension (JTE) structure for vertical gallium nitride (GaN) p-n diode with gradient hole density (GHD) is spontaneously formed based on the selective area partial passivation of Mg acceptors with hydrogen. The reverse bias for the quasi-vertical GaN-on-Si p-n diodes to reach a leakage current of 1 A/cm2 was boosted from 631 to 1100 V. In addition, the fabricated diode possessed a superior rectifying behavior with an ON/OFF-current ratio of $10^{{12}}$ , a specific differential ON-resistance of 0.75 $text{m}sf Omega cdot $ cm2.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Inversion-Type Ferroelectric Capacitive Memory and Its 1-Kbit Crossbar
           Array

    • Free pre-print version: Loading...

      Authors: Zuopu Zhou;Leming Jiao;Jiuren Zhou;Zijie Zheng;Yue Chen;Kaizhen Han;Yuye Kang;Xiao Gong;
      Pages: 1641 - 1647
      Abstract: By modulating the capacitance to store data, ferroelectric capacitive memories (FCMs) show distinct advantages compared with the conventional resistive memories, including the near-zero static power, negligible read disturbance, and immunity to IR drop problem. However, the promise of FCMs requires the improvement of their electrical characteristics, including retention, capacitance ratio, and operation speed. In this work, by introducing a heavily doped region in the metal–ferroelectric–semiconductor (MFS) structure, we propose and experimentally demonstrate an inversion-type FCM device, which simultaneously achieves: 1) high ( $times 125$ ) ${C}_{text {HCS}}/{C}_{text {LCS}}$ ratio; 2) ten-year retention under 85 °C; 3) multistate operation; and 4) improved write speed in nanosecond range. Integrating the devices on Silicon on insulator (SOI) substrates, we also realize the 1-kbit inversion-type FCM crossbar array. By setting up a test platform with a specially designed drive circuit, the read/write operation of the capacitive array is successfully demonstrated, evidencing the stable operation of the capacitive memory device in the array level.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Electric-Controlled Resistive Switching and Different Synaptic Behaviors
           in p⁺-Si/n-ZnO Heterojunction Memristor

    • Free pre-print version: Loading...

      Authors: Wenqing Song;Hao Yu;Xinmiao Li;Ruihua Fang;Wenhui Zhu;Lei Zhang;
      Pages: 1648 - 1652
      Abstract: In this study, the resistive switching (RS) and different synaptic behaviors have been observed by controlling the different applied bias voltages in the p+-Si/n-ZnO heterojunction memristor. After a big forming voltage, the formation and rupture of the oxygen vacancy filaments model has been proposed, and different migration amount of oxygen ions realizes the multiple RS behaviors. Prior to the electroforming, different synaptic behaviors have been observed dependent on the applied bias voltage based on the oxygen ion migration processes. Under small bias (
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Disturb-Free Operations of Multilevel Cell Ferroelectric FETs for Nand
           Applications

    • Free pre-print version: Loading...

      Authors: Chengji Jin;Jiacheng Xu;Jiani Gu;Jiayi Zhao;Xiaole Jia;Jiajia Chen;Huan Liu;Miaomiao Zhang;Yue Peng;Bing Chen;Ran Cheng;Yan Liu;Xiao Yu;Genquan Han;
      Pages: 1653 - 1658
      Abstract: We have experimentally investigated disturb-free operations of multilevel cell (MLC) ferroelectric field-effect transistors (FeFETs) in a NAND array. The fabricated FeFET cells are systematically characterized, and optimized schemes to write FeFET cells into multiple states with high stability are investigated. Write and read schemes to achieve stable MLC operations of FeFET NAND arrays are proposed. For the realization of disturb-free MLC operations, both program and read disturbs are systematically characterized at the array level. In addition, margins of program inhibition voltage ( ${V}_{text {inhib}}{)}$ and pass voltage ( ${V}_{text {pass}}{)}$ are determined from the measurement results. This work provides a fundamental understanding of disturb-free MLC FeFET operations for NAND applications.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Hybrid Precision in Resistive Memory-Based Convolutional Kernel for
           Fault-Resilient Neuromorphic Systems

    • Free pre-print version: Loading...

      Authors: Seonuk Jeon;Eunryeong Hong;Heebum Kang;Hyun Wook Kim;Nayeon Kim;Jiyong Woo;
      Pages: 1659 - 1663
      Abstract: As simple convolution computation is intensively and iteratively performed to extract features from input images, cross-point arrays with resistive random access memory (RRAM) serving as a kernel weight can accelerate the relevant mathematical operations in hardware. However, considering actual RRAM characteristics, either variability or unexpected permanent failure from the filamentary switching mechanism is observed, degrading recognition performance. This study investigates the impact of fault in a conventional kernel structure, where two adjacent columns in the array represent a single weight, on feature extraction using MATLAB. First, the fault types of HfOx-based multilevel RRAM is categorized. The results reveal that the unidirectional fault of RRAM primarily worsens the accuracy of image recognition. This is because the subtraction of negative weights from positive ones is crucial for identifying the edges of images through convolution operations. Therefore, we exploit a kernel structure, in which a single column dedicated to negative weights is located next to a matrix of positive weights. In addition, we reduce the weight precision for negative weights, while quantizing positive weights to higher bits. By mitigating the subtraction errors achieved by the kernel structure with hybrid precision, we improved fault tolerance, minimizing accuracy degradation.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Process-Aware Compact Model for GIDL-Assisted Erase Optimization of 3-D
           V-NAND Flash Memory

    • Free pre-print version: Loading...

      Authors: Yohan Kim;Soyoung Kim;
      Pages: 1664 - 1670
      Abstract: This article presents the accurate compact modeling methodology to optimize the gate-induced drain leakage (GIDL)-assisted erase operation for vertical stack-up, multiple stack, and ${Z}$ -directional shrink of the 3-D vertically integrated NAND (V-NAND) flash memory. The artificial neural network (ANN) is initially applied in the V-NAND transistors to describe the various GIDL characteristics with channel profile variations. In addition, physics-based RC network models are investigated to accurately model the complex process in the state-of-the-art V-NAND products. All models are implemented in Verilog-A, and the time dynamics of the GIDL-assisted channel potential increase for erase operations are successfully reproduced in the SPICE simulations. This SPICE-compatible compact model is essential to the design technology co-optimization (DTCO) for over 200-layer V-NAND, because the RC delay-related erase failures have become an important issue in the high aspect ratio (HAR) channel holes. Based on the proposed compact model, the highly accurate GIDL-assisted erase simulations are performed, and an erase optimization procedure is demonstrated with GIDL injection level, physical etch limit, and ${Z}$ shrink rate in the next V-NAND candidate structures. Therefore, this process-aware compact model is a valuable tool for pathfinding activities in the early stage of 3-D V-NAND flash memory development.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Forming-Free HfOx-Based Resistive Memory With Improved Uniformity Achieved
           by the Thermal Annealing-Induced Self-Doping of Ge

    • Free pre-print version: Loading...

      Authors: Xiang Ding;Xinwei Yu;Zhangsheng Lan;Jianguo Li;Shiqi Zhou;Choonghyun Lee;Yi Zhao;
      Pages: 1671 - 1675
      Abstract: In this work, a forming-free HfOx-based resistive random access memory (RRAM) with improved uniformity is successfully demonstrated without an additional doping process, ionic injection, or special layer deposition. The significantly enhanced performances can be attributed to the self-doping of Ge atoms from the Ge bottom electrode (BE) into the HfO2 layer during the postdeposition annealing (PDA) process. Besides, the RRAM provides a lower reset current and a higher ON/OFF ratio than the reported forming-free RRAM. These excellent properties are beneficial to the application of power-saving RRAM and its circuit operation.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Understanding the Resistive Switching Mechanism of 2-D RRAM: Monte Carlo
           Modeling and a Proposed Application for Reliability Research

    • Free pre-print version: Loading...

      Authors: Yifu Huang;Yuqian Gu;Yao-Feng Chang;Ying-Chen Chen;Deji Akinwande;Jack C. Lee;
      Pages: 1676 - 1681
      Abstract: The 2-D materials have become promising candidates for resistive random access memory (RRAM) devices as more unique resistive switching (RS) characteristics have recently been revealed. However, endurance is a major challenge for industrialization. Unlike the well-developed and recognized conductive filament (CF) model for oxide-based RRAM, the RS mechanism for 2-D RRAM is not well understood. In this article, we first review the dissociation–diffusion–adsorption (DDA) model and the cluster model proposed in previous works on monolayer 2-D RRAM devices. The use of a Monte Carlo (MC) simulator for multilayer 2-D RRAM devices to expand the application of DDA and cluster models is then discussed. A simulator was designed to provide an intuitive physical view by visualizing the stochastic behaviors of the RS process in multilayer 2-D RRAM devices. By comparing the simulated results with experimental data, the endurance characteristic was found to be mainly determined by the formation and collapse of an effective switching layer. We also found that the thickness of the effective switching layer is independent of the total thickness of the multilayer 2-D material and the initial status of the device, which is consistent with the experimental observations. The model and results discussed in this work provide additional insights and guidance for improving the reliability of 2-D RRAM devices.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • High-Voltage a-Si TFTs Using Dual-Gate With a Common Gate Structure by
           Channel Electrons Concentration Regulation

    • Free pre-print version: Loading...

      Authors: Jiaze Liu;Rongyue Liu;Shaohu Zhan;Qin Luo;Rifei Chen;Xing Cheng;
      Pages: 1682 - 1686
      Abstract: In this work, we report high-voltage amorphous silicon (a-Si) thin-film transistors (TFTs) using dual gate with a common gate structure, in which there are two extended electrodes with the same length at the junction of the two TFTs to regulate the electrons concentration in the channel. The working principle of the high-voltage a-Si TFTs is analyzed and their electrical performances are characterized. Results show that the high-voltage a-Si TFTs exhibit a maximum operating voltage ( ${V}_{text {DS}}$ ) over 370 V and a stable output current. Meanwhile, the electrical performances of the high-voltage a-Si TFTs are not significantly degraded compared to the conventional a-Si TFTs. The fabrication process is similar to that of conventional a-Si TFTs and has low cost, which makes the high-voltage a-Si TFTs have broad application prospects in high-voltage electronics.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Improvement of Performance of Back Channel Etching InGaZnO Thin-Film
           Transistors by CF4 Plasma Treatment

    • Free pre-print version: Loading...

      Authors: Chen Wang;Cong Peng;Pan Wen;Meng Xu;Longlong Chen;Xifeng Li;Jianhua Zhang;
      Pages: 1687 - 1691
      Abstract: The performance of back channel etching (BCE) amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) was improved using a carbon tetrafluoride (CF $_{{4}}{)}$ plasma treatment of the back channel (BC) after the wet-etching process of source–drain (SD) electrodes. X-ray photoelectron spectroscopy (XPS) analysis showed that the wet-etching of $text{H}_{{2}}text{O}_{{2}}$ -based etchant may result in Mo-related residue, which deteriorate a-IGZO BC. In comparison with as-etching indium gallium zinc oxide (IGZO) TFT, the saturation field effect mobility increases from 7.8 to 16.4 cm2/Vs, subthreshold swing (SS) decreases from 0.82 to 0.34 V/decade, the ratio of on current and off current improves from $7.3times 10^{{5}}$ to $1.1times 10^{{10}}$ , and the threshold voltage shift of negative bias illumination stability (NBIS) improves from −3.4 to −0.6 V. The fact confirmed that CF4 plasma treatment of the BC can effectively reduce BC defects and improve the electrical characteristics of BCE IGZO TFT comprehensively.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Analogy of Photogating to Voltage-Gating in Zinc-Tin Oxide Thin-Film
           Transistor: Efficiency and Current Saturation Mechanism

    • Free pre-print version: Loading...

      Authors: I-Wen Wang;Li-Chung Shih;Jeng-Ting Li;Jen-Sue Chen;
      Pages: 1692 - 1696
      Abstract: In contrast to the conventional voltage-gated channels of thin-film transistors (TFTs), the photo-induced gating effect provides a promising approach to control the carrier concentration in the channels and benefits the advanced application in a remote operation mode. In this work, the zinc-tin oxide TFT (ZTO TFT) is revealed the feasibility of being photo-gated at ${V}_{text {G}} =0$ V to obtain a series of output ( ${I}_{text {D}}$ – ${V}_{text {D}}{)}$ characteristics. The current saturation in ${I}_{text {D}}$ – ${V}_{text {D}}$ curves of the photo-gated ZTO TFT confirms the photo-induced pinch-off region in the ZTO channel, suggesting the presence of positive pseudogate voltage at the channel under lighting. The photo-gated output characteristic at a given ${V}_{text {D}}$ is converted to the log ${I}_{text {D}}$ verse optical power density ( $rho {)}$ curve, showing a rapid switching of ${I}_{text {D}}$ by 405-nm light illumination with the reciprocal log ( ${I}_{text {D}}{)}$ – $rho $ slope of 0.04 (mW/cm $^{{2}}{)}$ /decade. Parallel output c-aracteristics triggered electrically with various gate voltages are also performed to obtain an equivalent drain current. The correlation of ${V}_{text {G}}$ versus $rho $ for equivalent drain current reveals that photogating efficiency is 7.93 V/(mW/cm $^{{2}}{)}$ . The photogating mechanism and efficiency are discussed based on the photoionization of the neutral oxygen vacancies to positively charged oxygen vacancies, which are responsible for photo-induced gate voltage (VG,ph).
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Monolithically Stacked Two Layers of a-IGZO-Based Transistors Upon
           a-IGZO-Based Analog/Logic Circuits

    • Free pre-print version: Loading...

      Authors: Wendong Lu;Congyan Lu;Guanhua Yang;Menggan Liu;Kaifei Chen;Fuxi Liao;Xinlv Duan;Nianduan Lu;Ling Li;
      Pages: 1697 - 1701
      Abstract: In this work, back end of line (BEOL)-compatible amorphous indium–gallium–zinc oxide (a-IGZO) transistors are monolithically stacked on top of first-layer a-IGZO-based analog/digital circuits, including a single-stage amplifier and a five-stage ring oscillator (RO). The second-layer a-IGZO transistors are fabricated with a low thermal budget ( $< 200~^{circ }text{C}$ ), demonstrating an ultralow subthreshold swing of 75.7 mV/dec, ultralow leakage current ( $< 10^{-{12}}$ A), and ultrahigh ON/OFF ratio ( $10^{{9}}$ ). After 3-D integration, the performance of a-IGZO-based amplifiers and RO circuits in the first layer shows negligible degradation and exhibits a maximum voltage gain larger than 100 at ${V}_{{text {DD}}} =10$ V and a maximum oscillation frequency of 3.3 kHz at ${V}_{{text {DD}}} =5.5$ V. This work proves that a-IGZO-based transistors and circuits can be monolithically stacked without performance degradation and shows great prospects for potential high-density and high-performance monolithic 3-D integration applications.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Zero Waste and Biodegradable Zinc Oxide Thin-Film Transistors for UV
           Sensors and Logic Circuits

    • Free pre-print version: Loading...

      Authors: Gabriel L. Nogueira;Dinesh Kumar;Shoushou Zhang;Neri Alves;Jeff Kettle;
      Pages: 1702 - 1709
      Abstract: Bioderived and biodegradable electronics have the capability to reduce significantly waste electrical and electronics equipment (WEEE) and can also be applied to other sectors, where degradation to benign by-products is essential, such as marine, farming, or health monitoring. Herein, the authors report biodegradable thin-film transistors (TFTs) arrays based on zinc oxide (ZnO) active layer using molybdenum (Mo) source, drain, and gate electrodes. The developed TFTs were fabricated at room temperature onto a planarized biodegradable substrate surface and achieved an ${I}_{text {on}}/{I}_{text {off}}$ ratio of $sim 4times 10^{{6}}$ , a threshold voltage of $sim $ 2.3 V, a field-effect mobility in the saturation region of 1.3 cm $^{{2}}cdot text{V}^{-{1}}cdot text{s}^{-{1}}$ , and a subthreshold swing of 0.3 $text{V}cdot $ dec $^{-{1}}$ and show stable device performance under stability tests. Based upon the successful fabrication of the ZnO TFT array, the demonstration of a UV sensor (phototransistors mode) and simple logic circuits (inverter and both NAND and NOR gate circuits) are presented. Furthermore, a method to “control” the transience was implemented by using a printed heater that could accelerate the decomposition of material, which opens potential avenue for material recovery and zero waste products.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Experimental and Theoretical Evidence of Charge Injection Barrier Control
           by Small-Molecular Charge Injection Layer and Its Effects on
           Organic–Inorganic Complementary Inverters

    • Free pre-print version: Loading...

      Authors: Youngmin Han;Seongjae Kim;Chang-Hyun Kim;Hocheon Yoo;
      Pages: 1710 - 1714
      Abstract: Introducing a contact charge injection layer at the interface between the contact electrode and active materials is considered crucial to obtain efficient charge injection behaviors in thin-film transistors (TFTs). Here, we investigate the effect of a small molecule contact charge injection layer through experimental results and theoretical calculations. We found limited electrical characteristics derived from contact resistance in C8-BTBT TFTs with C8-BTBT as the channel and Au as the electrode. We experimentally demonstrated that the limited electrical characteristics of C8-BTBT TFT can be improved by inserting dinaphtho[2,3-b: $2^{prime} $ , $3^{prime} $ -f]thieno [3,2-b] thiophene (DNTT), which has a low contact resistance at the junction with Au, as a charge injection layer. The results of improved contact properties through the DNTT charge injection layer were also consistent with the results of energy structural simulations. Furthermore, we verified the effect of the DNTT charge injection layer at the circuit level through improved noise margin characteristics in the complementary inverter composed of asymmetric charge injection layer TFT (ACIL-TFT) and a-indium gallium zinc oxide (IGZO) TFT.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Wide-Spectrum Polarization-Sensitive Photodetector Based on Spontaneous
           GaTe/Ga2(TexO1-x)5 Heterostructure

    • Free pre-print version: Loading...

      Authors: Jingshu Zhou;Tao Xiong;Zhengfeng Guo;Kaiyao Xin;Xiaoyu Wang;Honggang Gu;Yue-Yang Liu;Liyuan Liu;Juehan Yang;Zhongming Wei;
      Pages: 1715 - 1720
      Abstract: Low-dimensional semiconductor materials with in-plane anisotropy have attracted increasing attention due to the novel physicochemical properties induced by the special lattice structure. Among III-group metal chalcogenides, GaS, GaSe, and In2Se3 have been reported impressive performances in microelectronics, optoelectronics, and ferroelectronics. Therefore, the investigation on the III-group chalcogenides and their heterostructures is important for diverse applications with promising functionalities. Gallium telluride (GaTe), as a typical III-group chalcogenide 2-D semiconductor with in-plane anisotropy, can be oxidized in atmosphere, thus forming a spontaneous van der Waals heterostructure consisting of GaTe and its oxides. After being covered with oxides, this new system shows a reduced bandgap than GaTe and exhibits improved properties than counterparts. Moreover, the photodetector based on this special heterostructure shows a broadband response from ultraviolet to infrared radiation with a responsivity of 1.67 A/W, an external quantum efficiency (EQE) of 391.25%, and a fast response time of 0.4 ms. Benefiting from the in-plane anisotropic crystal structure, the photodetector was observed polarization-sensitive behaviors under the illumination of 532- and 638-nm light. It is suggested that GaTe along with the heterostructure can be seen as promising candidates for polarization-sensitive photodetection operated in a broadband spectrum.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Simulation-Based Study of Back-Illuminated Lateral Ge/GeSn/Ge
           Photodetectors on Si Platform for Mid-Infrared Image Sensing

    • Free pre-print version: Loading...

      Authors: Harshvardhan Kumar;Ankit Kumar Pandey;
      Pages: 1721 - 1727
      Abstract: GeSn/Ge heterojunction photodetectors (PDs) have great potential to outperform conventional mid-infrared (MIR) sensors. In this work, simulated analysis is performed to demonstrate the back-illuminated lateral double $text {Ge/}{text {Ge}}_{{0.90}}{text {Sn}}_{{0.10}}text {/Ge}$ heterojunctions p-i-n PDs for MIR imaging. This lateral PDs configuration is compatible with current complementary metal–oxide–semiconductor (CMOS) technology, yielding reduced fabrication complexity and offering high resonance in optical characteristics (between 2000- and 2700-nm wavelength range), viable for high-performance operation in MIR wavelength bands. This work also investigates the effects of high-density point dislocation at GeSn/Ge heterointerface on various performance metrics, including dark current, photocurrents, detectivity, and noise-equivalent-power (NEP) of PDs. The results indicate that the defects have less impact on detectivity and NEP and have negligible impact on the collection of photogenerated carriers and thus responsivity. The device shows a maximum 3-dB optoelectrical bandwidth of $>$ 92.4 GHz, which is among the highest of other GeSn p-i-n PDs. In addition, even in the presence of defects, the device achieves high responsivity in MIR bands and its values are 0.39, 1.45, and 0.25 A/W at the operating wavelengths of 2000, 2310, and 2700 nm, respectively. Thus, the proposed work can be a major step toward GeSn-based PDs on the Si platform for MIR imaging applications.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • On-Chip Carrier-Selective Contact Photovoltaic Cell

    • Free pre-print version: Loading...

      Authors: Takaya Sugiura;Hiroki Miura;Nobuhiko Nakano;
      Pages: 1728 - 1732
      Abstract: This article proposes an on- chip photovoltaic cell equipped with a tunnel oxide passivated contact (TOPCon) exhibiting selective carrier contact. The proposed structure utilizes the gate region as the TOPCon structure and performs best when the gate oxide is high- $kappa $ hafnium oxide (HfO2). Oxide thicknesses lower than 1.5 nm enable the utilization of the device as a solar cell; therefore, it can be fabricated using high-end oriented CMOS processes. Furthermore, TOPCon technology at the bulk contact is observed to be more important than that at the emitter contact; however, a combination of the two yields an improved ${V}_{text {OC}}$ value. On applying the full TOPCon technology, ${V}_{text {OC}}$ is improved by approximately 20 mV from 601 to 619 mV, and $eta $ is improved by approximately 0.5% from 15.20% to 15.73% compared to the conventional surface diffusion (SD)-based structure.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Luminous Properties of Red, Green, and Blue Micro-LEDs and the Impacts on
           Color Gamut

    • Free pre-print version: Loading...

      Authors: Chang-Dong Tong;Guang-Yao Li;Xi Zheng;Can-Bin Chen;Zhi-Jie Ke;Rong-Xing Wu;Ting-Zhu Wu;Yi-Jun Lu;Zhong Chen;Jian-Bang Zhuang;Wei-Jie Guo;
      Pages: 1733 - 1738
      Abstract: Electrical-chromatic characteristics of red, green, and blue micro-LEDs ( $10times 10,,mu text{m}$ ) are investigated at temperatures ranging from 300 to 340 K. The external quantum efficiency (EQE) of red micro-LEDs decreases significantly with the increasement in temperature, suggesting that heat dissipation is crucial for red micro-LEDs. The impacts of temperature and driving current on the chromaticity coordinates of the light emission from micro-LEDs are determined. When the trichromatic micro-LEDs are driven by the currents corresponding to the maximum EQE, the influence of temperature on the color gamut is limited, facilitating the achievement of high color gamut and high efficiency.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • High-Performance Photodetectors With Polarization Sensitivity Based on p-n
           and p-p+ Black Phosphorus/Germanium Heterojunctions

    • Free pre-print version: Loading...

      Authors: Maolong Yang;Tian Miao;Qing Mi;Yao Lu;Ningning Zhang;Maliang Liu;Hui Guo;Tao Liu;Huiyong Hu;Liming Wang;
      Pages: 1739 - 1744
      Abstract: The heterostructures between atomically thin 2-D and 3-D semiconductors show great potential for high-performance photodetector. In this work, the efficient light detection of the p-n and p-p+ black phosphorus (bP)/germanium (Ge) heterojunction photodiode has been demonstrated. With the change of Ge doping type, the rectification direction of the heterojunction diode formed by bP and Ge could be reversed. Due to the enhanced photocarrier separation at the reverse bias, the bP/n-Ge (bP/p-Ge) device has a responsivity of 6.08 (3.43) A/W under 1550-nm illumination, with fast response speed in the 10- $mu text{s}$ level. The bP/n-Ge device has a significant photovoltaic effect due to the small conduction band energy offset, with a large open-circuit voltage of 0.34 V. Under the illumination of light with different polarization directions, the device exhibits apparent polarization-sensitive detection, and the dichroic ratio of bP/n-Ge and bP/p-Ge devices is 4.25 and 3.85, respectively. These results suggest that the bP/Ge heterojunction photodetector would have great potential in high-performance, self-powered, and polarization-sensitive photodetection.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Correlation Between Reverse Leakage Current and Electric Field Spreading
           in GaN Vertical SBD With High-Energy Ion Implanted Guard Rings

    • Free pre-print version: Loading...

      Authors: Jiayue Xu;Xuan Liu;Bing Xie;Yilong Hao;Cheng P. Wen;Jin Wei;Maojun Wang;
      Pages: 1745 - 1750
      Abstract: This work focuses on the bias-dependent reverse leakage current and carrier depletion process of vertical gallium nitride (GaN)-on-GaN Schottky barrier diodes (SBDs) with fluorine ion-implanted guard rings (GRs). The reverse leakage characteristics in the vertical GaN SBD with GRs sequentially go through ohmic conduction, thermionic field emission (TFE), and space charge limited conduction (SCLC) model as the reverse bias increases gradually. Once the traps in the implanted termination region are fully ionized, the device will undergo large leakage current at high biases. Compared with infinite area ion implanted edge termination (ET), ion-implanted GR can effectively reduce the leakage current at low biases. In addition, there are kinks in the reverse current–voltage curves, which proved to be related to the electric field spreading effect of individual GR. Based on the analysis of reverse leakage current, the electric field modulation mechanism of ion-implanted GRs is reviewed.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • An SOI LTIGBT With Self-Biased pMOS for Improved Short-Circuit Property
           and Reduced Turn-Off Loss

    • Free pre-print version: Loading...

      Authors: Weizhong Chen;Zikai Wei;Hongsheng Zhang;Yi Huang;Zhengsheng Han;
      Pages: 1751 - 1756
      Abstract: A novel silicon on insulator (SOI)-lateral trench insulated gate bipolar transistor (LTIGBT) featuring a self-biased pMOS (SBP), named SBP-LTIGBT, is proposed and investigated. The gate and drain of SBP are shortly connected with emitter electrode, and the source is connected with the P-buried, which introduces automatically turn-off and turn-on function. At the forward conduction state, the SBP is turned off when ${V}_{text {GS,P}}> {V}_{text {TH,P}}$ , and the SBP-LTIGBT shows the same electrical characteristics as conventional LTIGBT. The SBP is automatically turn-on with reduced saturation current when ${V}_{text {GS,P}}< {V}_{text {TH,P}}$ . At the switching state, the SBP is always turned on to accelerate the extraction of the excessive carriers; consequently, the turn-off loss ${E}_{text {OFF}}$ is reduced. As a result, the tradeoff relationship between forward conduction voltage ${V}_{text {ON}}$ and ${E}_{text {OFF}}$ is largely improved. The short-circuit tolerance time ( ${T}_{text {SC}}{)}$ of the SBP-LTIGBT is $10.5~mu text{s}$ , which is extended by 3.4, 2, and 1.4 times longer than that of LTIGBT with triple-RESURF (TR-LTIGBT), LTIGBT with double-RESURF (DR-LTIGBT), and conventional LTIGBT (C-LTIGBT), respectively. Furthermore, when ${V}_{text {ON}}$ is 1.4 V, ${E}_{text {OFF}}$ of the SBP-LTIGBT is 0.36 mJ/cm2, which is reduced by 73%, 60%, and 51% than that of C-LTIGBT, DR-LTIGBT, and TR-LTIGBT, respectively.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Modeling of Stacking Faults in 4H-SiC n-Type Epilayer for TCAD Simulation

    • Free pre-print version: Loading...

      Authors: Satoshi Asada;Koichi Murata;Hidekazu Tsuchida;
      Pages: 1757 - 1762
      Abstract: Current–voltage characteristics of an n-type 4H-silicon carbide (SiC) epilayer containing a stacking fault (SF) were analyzed using a technology computer-aided design (TCAD) simulation. In the simulation, the SF was modeled by a quantum well (QW) formed in the conduction band, which traps electrons and induces a potential barrier. The simulation analysis clarified that the electron conductance in the n-type epilayer containing a SF was dominantly determined by the potential barrier height. Based on this insight and the experimental results obtained from our previous study, the energetic depth and width of the QW in the conduction band were deduced for four types of SFs. The temperature dependence of the experimental current–voltage characteristics of Schottky barrier diodes (SBDs), containing the SF, was effectively reproduced by adopting the deduced QW depth and width, proving the feasibility of the proposed simulation model quantitatively predicting the impacts of SFs on SiC unipolar device performances.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Investigation of the Gate Voltage Overshoot of IGBTs Under Short Circuit
           Type II Condition

    • Free pre-print version: Loading...

      Authors: Xing Liu;Thomas Basler;
      Pages: 1763 - 1768
      Abstract: In this article, the physical reason for the gate voltage ${V}_{text {GE}}$ overshoot of the insulated gate bipolar transistor (IGBT) under short circuit type II (SC type II) condition is investigated. The classic capacitive coupling from the Miller capacitance at the low collector-emitter voltage regime is studied. Moreover, it has been found that the Miller effect is not the only cause of the ${V}_{text {GE}}$ overshoot. The interaction between the channel voltage and the gate voltage plays an essential role in the ${V}_{text {GE}}$ overshoot as well. A novel mechanism of the channel potential modification generated displacement current through the gate oxide capacitance is proposed. Consequently, both effects lead to a ${V}_{text {GE}}$ overshoot before the fast desaturation process.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Simulation of Pulse Sharpening Mechanism of Vertical Diamond Avalanche
           Diode

    • Free pre-print version: Loading...

      Authors: Zhiqing Yang;Yan Cao;Jinfeng Zhang;Qi He;Kai Su;Zeyang Ren;Jincheng Zhang;Junpeng Li;Yuanchen Ma;Dong Wang;Yong Wu;Yue Hao;
      Pages: 1769 - 1775
      Abstract: The extremely low leakage, fast response, and excellent thermal conductivity of diamond facilitate its potential application in pulse power switching devices. In this study, we investigated the static and transient characteristics of diamond avalanche diodes (DADs) via 2-D device simulation. DAD is based on a Schottky barrier diode (SBD) structure. The static breakdown voltage is 590 V. Under an input pulse voltage with a peak voltage of 2400 V and a rise time of 2 ns, the output voltage on a 50- $Omega $ load driven by the device has a peak value of 1.83 kV and a rise time of 1.282 ns. The behavior and mechanism of the sharpened rising pulse response waveform are analyzed phase by phase. The generation and dynamic changes in carrier plasma inside the device and their effect on the altered electric field, impact generation, and carrier density, as well as the transient output of the device are investigated.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Measuring Double-Sided Thermal Resistance of Press-Pack IGBT Modules Based
           on Ratio of Double-Sided Heat Dissipation

    • Free pre-print version: Loading...

      Authors: Chunsheng Guo;Shaoxiong Cui;Wenyi Tsai;Yunong Liu;Juewen Ding;Jinyuan Li;Zhongyuan Chen;Yaosheng Li;Shijie Pan;Shiwei Feng;
      Pages: 1776 - 1781
      Abstract: Precise measurements of the double-sided thermal resistance of press-pack insulated gate bipolar transistors (PP IGBTs) are challenging because of their special packaging and operating conditions. This article presents a method for calculating the double-sided heat dissipation ratio of PP IGBT modules. An indirect measurement technique for the power consumption on both sides of the module is also proposed, in which the water temperature is measured at the inlet and outlet of the water-cooled radiators corresponding to the collector and the emitter in the working state of the module. A PP IGBT device test fixture is constructed that can apply a measurable and adjustable pressure to the device and provide electrical connections. According to the proposed test theory, a matching double-sided thermal resistance test platform is developed to test a PP IGBT module made by the State Grid Smart Grid Research Institute. The influence of pressure on the thermal conduction characteristics of the PP IGBT module is then analyzed.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Impact of Post-Trench Process Treatment on Electron Scattering Mechanisms
           in 4H-SiC Trench MOSFETs

    • Free pre-print version: Loading...

      Authors: Zewei Dong;Yun Bai;Chengyue Yang;Chengzhan Li;Yidan Tang;Jilong Hao;Xiaoli Tian;Xinyu Liu;
      Pages: 1782 - 1788
      Abstract: This work reports the influence of post-trench treatment on electron scattering mechanisms in 4H-silicon carbide (SiC) trench MOSFETs. The mobilities representing different scattering mechanisms were extracted from the simulated transfer characteristics of devices with different post-trench Ar annealing conditions at temperatures of 0 °C–200 °C. Various mobilities, such as Coulomb mobility ( $mu _{text {C}}{)}$ and surface roughness mobility ( $mu _{text {SR}}{)}$ , were compared and analyzed in different samples at room temperature (RT). The result shows that accompanied by the sacrificial oxidation, Ar annealing at different temperatures and times (1500 °C and 5 min, 1500 °C and 15 min, and 1600 °C and 5 min) slightly influences Coulomb mobility but affects surface roughness mobility obviously. Further study has revealed that the Coulomb mobility is strongly related to the density of occupied interface traps, while the sidewall surface roughness gives rise to the change in surface roughness mobility.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Controlling the Ferroelectricity of Doped-HfO2 via Reversible
           Migration of Oxygen Vacancy

    • Free pre-print version: Loading...

      Authors: Jiajia Chen;Jiacheng Xu;Zhi Gong;Jiani Gu;Xiao Yu;Chengji Jin;Yue Peng;Yan Liu;Bing Chen;Ran Cheng;Genquan Han;
      Pages: 1789 - 1794
      Abstract: We have experimentally demonstrated that the ferroelectricity can be controlled by reversibly injecting oxygen vacancies ( ${V}_{text {o}}{)}$ from the interfacial layer (IL) of TiOxNy to Hf $_{{0}.{5}}$ Zr0.5O2(HZO) or extracting them from HZO to IL in the titanium nitride (TiN) $/$ HZO $/$ TiN structure for the first time. The IL between the TiN electrode and HZO thin film plays a crucial role as the ${V}_{text {o}}$ reservoir. By adjusting the electrical pre-stress time to modulate the ${V}_{text {o}}$ concentration and distribution, HZO shows multiferroelectricity which can be switchable. In addition, the experimental multiferroelectricity can be correctly reproduced by the simulation with a phase-field polarization switching model. The simulated results herein strongly support the mechanism that modulating the ${V}_{text {o}}$ migration reversibly from IL into HZO can achieve multiferroelectricity control.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Interface State Density Modification and Dielectric Reliability
           Enhancement of ErTixOy/Al2O3/InP Laminated Stacks

    • Free pre-print version: Loading...

      Authors: Lesheng Qiao;Gang He;Jinyu Lu;Qiuju Wu;Bo Yao;Zebo Fang;
      Pages: 1795 - 1801
      Abstract: Co-sputtering-derived ErTixOy gate dielectric films were deposited on atomic layer deposition (ALD)-derived Al2O3-passivated InP substrates. The interface chemistry and electrical properties of ErTixOy/Al2O3/InP MOS capacitors were investigated as a function of Er/Ti X-ray photoelectron spectroscopy (XPS) measurements, and electrical tests have revealed that an atomic ratio of 3.7/5.2 of erbium to titanium can effectively modulate the interface chemistry and obtain optimized electrical properties, achieving a large dielectric constant of 26.4, a low density of leakage current of $1.8times 10^{-{5}}$ A/cm2, and an enhanced breakdown properties ( ${V}_{text {BD}} =6.1$ V and ${t}_{text {BD}} =4950$ s on Si). Furthermore, the density of interface states ( ${D}_{text {it}}{)}$ has been evaluated based on the conductance method, and leakage current mechanisms are investigated in the temperature range of 77–377 K. Current results have indicated that ErTixOy is a ternary oxide gate dielectric with superior performance, which is of great significance for the development and exploration of new gate dielectrics for CMOS devices.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Comparative Study on the Polarization, Reliability, and Switching
           Dynamics of HfO2-ZrO2-HfO2 and ZrO2-HfO2-ZrO2 Superlattice Ferroelectric
           Films

    • Free pre-print version: Loading...

      Authors: Kaixuan Li;Yue Peng;Wenwu Xiao;Fenning Liu;Yueyuan Zhang;Ze Feng;Hong Dong;Yan Liu;Yue Hao;Genquan Han;
      Pages: 1802 - 1807
      Abstract: In this article, the effect of starting layer on the ferroelectric properties and reliability of HfO2-ZrO2-HfO2 (HZH) and ZrO2-HfO2-ZrO2 (ZHZ) superlattice (SL) films were systematically investigated. Compared with that of the ZHZ device, a higher value of remnant polarization ( ${P}_{r}{)}$ for the HZH device was achieved. However, the ZHZ structure exhibits a better wake-up performance and frequency stability than HZH, as well as a higher inversion speed and more endurance cycles. Accordingly, a hybrid model involving ferroelectric (FE) polarization and interfacial ion migration is proposed. This study is helpfxg1ul for understanding and optimizing the HfO2-based FE films for non-volatile memory applications.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A HydroDynamic Model for Trap-Assisted Tunneling Conduction in Ovonic
           Devices

    • Free pre-print version: Loading...

      Authors: F. Buscemi;E. Piccinini;L. Vandelli;F. Nardi;A. Padovani;B. Kaczer;D. Garbin;S. Clima;R. Degraeve;G. S. Kar;F. Tavanti;A. Slassi;A. Calzolari;L. Larcher;
      Pages: 1808 - 1814
      Abstract: Electrical conduction in ovonic threshold switching (OTS) devices is described by introducing a new physical model where the multiphonon trap-assisted tunneling (TAT) is coupled to a hydrodynamic theory. Static and transient electrical responses from GexSe ${}_{{1}-{x}}$ experimental devices are reproduced, outlining the role played by the material properties like mobility gap and defects in tuning the OTS performances. A clear physical interpretation of the mechanisms ruling the different OTS conduction regimes (off, threshold, on) is presented. A nanoscopic picture of the processes featuring the carrier transport is also given. The impact of geometry, temperature, and material modifications on device performance is discussed providing physical insight into the optimization of OTS devices.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Effective Channel Mobility Extraction and Modeling of 10-nm Bulk CMOS
           FinFETs in Cryogenic Temperature Operation for Quantum Computing
           Applications

    • Free pre-print version: Loading...

      Authors: Sumreti Gupta;Sujit Kumar Singh;Reinaldo A. Vega;Abhisek Dixit;
      Pages: 1815 - 1822
      Abstract: This article presents an extensive experimental investigation of transport properties in 10-nm CMOS Bulk FinFETs at cryogenic temperatures. The split-CV technique is employed to analyze the effective electron and hole mobilities from 300 to 10 K. Temperature and length dependence of effective mobilities is explored taking into account different scattering mechanisms. Hole mobilities were found to be dominated by temperature-independent neutral defects and surface scattering events for short-channel devices at low temperatures; while for electron mobilities, degeneracy effects at the cryo-temperature result in mobility enhancement at high fields. The short-channel devices show significant mobility degradation and weaker temperature dependence which could limit their utility for high-speed cryogenic-CMOS-based circuits. Variation of electrical parameters, such as subthreshold swing (SS), equivalent oxide thickness (EOT), threshold voltage, and effective length with temperature is also discussed. For accurately capturing the effective mobility trends in the specified temperature range along with the threshold voltage and SS trends, the existing BSIM-CMG 110.0.0 compact model equations are modified. The proposed model is validated across different device geometries of the short-channel bulk FinFETs fabricated with industry-standard 10-nm layout rules.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Effect of the Electron Transport Layer Thickness on I–V Characteristics
           of the S-Shaped Kinks in Perovskite Solar Cells

    • Free pre-print version: Loading...

      Authors: Jingxian Liu;Bohao Yu;Kaoming Chen;Wanling Deng;Yuzhao Yang;Junkai Huang;
      Pages: 1823 - 1828
      Abstract: In our experimental preparation of perovskite solar cells (PSCs), when the thickness of the electron transport layer (ETL) was changed from thin to thick, the current–voltage ( ${I}$ – ${V}$ ) characteristics showed the changing laws of S-shaped kinks appearance, S-shaped kinks disappearance, and S-shaped kinks appearance. A lumped-parameter equivalent circuit model is proposed to reveal the intrinsic physical significances of the S-shaped kinks for this variation laws. The explicit solution of the model is derived using the deformed difference-microvariation (DM) principle combined with the region method, and the model parameters are extracted efficiently through the firefly optimization algorithm (FA). The proposed analytical solution enables the model to be compactly implemented in photovoltaic devices and circuit simulators, and the model is expected to point the direction for process optimization of devices.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • High Number of Transport Modes: A Requirement for Contact Resistance
           Reduction to Atomically Thin Semiconductors

    • Free pre-print version: Loading...

      Authors: Emanuel Ber;Ryan W. Grady;Eric Pop;Eilam Yalon;
      Pages: 1829 - 1834
      Abstract: Electrical contacts to atomically thin 2-D semiconductors are considered as the hindering aspect of electronic devices based on these materials. The high resistance of such contacts stems from their Schottky nature in contrast to the desired low-resistance Ohmic contacts. This issue of Schottky contacts is thus one of the major inhibitors to the integration of 2-D materials into mainstream technology. In this work, we explore contact resistance ( ${R}_{text {C}}$ ) to atomically thin 2-D semiconductors in terms of the injected current through the Schottky barrier (SB) by using the Landauer-Büttiker formalism as well as experimental measurements and technology computer aided design (TCAD) simulations. We show that the SB height and width, which are determined by the metal–semiconductor interface and the number of charge carriers in the semiconductor channel, respectively, affect ${R}_{text {C}}$ when it is relatively high ( ${R}_{text {C}}>$ 1 $text{k}Omega cdot mu text{m}$ ). However, the number of transport modes for carrier injection is the limiting factor for aggressive ${R}_{text {C}}$ lowering ( ${R}_{text {C}} < $ 1 $text{k}Omega cdot mu text{m}$ ), even for near-zero SB height. Our results show that to reduce ${R}_{text {C}}$ below $100~Omega cdot mu text{m}$ , large number of transport modes are required, which can be accomplished through raising the number of channel carriers above 5. 1013 cm-2 by means of heavy doping or gating. Our conclusions offer insight for future contact engineering and can explain recently published state-of-the-art results.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • An Improved Noise Modeling Method Using a Quasi-Physical Zone Division
           Model for AlGaN/GaN HEMTs

    • Free pre-print version: Loading...

      Authors: Shuman Mao;Ruimin Xu;Bo Yan;Yuehang Xu;
      Pages: 1835 - 1842
      Abstract: Accurate characterization of transistor noise performance is significant for low-noise amplifier (LNA) design. The conventional empirical noise model contains too many fitting parameters and thus relies on a large number of on-wafer noise measurements, especially the ambient temperature effects modeling. In this article, an improved noise modeling method using the quasi-physical zone division (QPZD) theory is proposed. The boundary potential calculation in the traditional modeling method is improved by considering the effects of the charge depletion region when the transistor is in the ON-state, which can result in at least two orders of magnitude improvement in the accuracy of the noise power spectral density (PSD). With this improvement, the noise performance can be accurately predicted without adding any fitting parameters in the noise PSD models. Furthermore, ambient temperature modeling of the noise performance is realized by considering the ambient temperature effects of drain–source current ${I}_{text {ds}}$ with a modified ${V}_{text {off}}$ model and some other significant intrinsic parameters. Verification shows that the proposed QPZD noise model with the improved boundary potential calculation method can well predict the noise performance and scattering parameters at different ambient temperatures. The method of this study can be applied to physical-based noise modeling of GaN high-electron-mobility transistors (HEMTs) and LNA design.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Unipolar Conductivity Enhancement and Its Experiments in SOI-LIGBT

    • Free pre-print version: Loading...

      Authors: Wentong Zhang;Ning Tang;Yuting Liu;Yang Yu;Nailong He;Sen Zhang;Ming Qiao;Zhaoji Li;Bo Zhang;
      Pages: 1843 - 1848
      Abstract: A novel 850-V silicon-on-insulator (SOI) lateral insulated gate bipolar transistor with unipolar conductivity enhancement (UE LIGBT) is proposed and experimentally realized in this article. A thick SOI region with charge-balanced n- and p-pillars is introduced near the cathode of the UE LIGBT to enhance the conductivity by high concentration charge-balanced majority carriers. A normalized conductivity factor $eta _{text {c}}$ is proposed to evaluate the conductivity enhancement of the new device, based on which the unipolar conductivity region is optimized to reduce the ON-state voltage drop ${V}_{ mathrm{scriptscriptstyle ON}}$ while keeping the similar turn-off loss and breakdown voltage ${V}_{text {B}}$ . The experiments demonstrated that ${V}_{ mathrm{scriptscriptstyle ON}}$ and conduction capability of the UE LIGBT are improved by 16.7% and 38.9% when compared with the conventional LIGBT (Con LIGBT) under the same breakdown voltage ${V}_{text {B}}$ of 850 V.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A QCM Humidity Sensor Based on MoS₂ Nanoflower-Modified Chitosan
           Composite With High Quality Factor

    • Free pre-print version: Loading...

      Authors: Haiquan Song;Xiaoxun Zhu;Enyuan Yang;Zhonghe Han;
      Pages: 1849 - 1853
      Abstract: This article presented a quartz crystal microbalance (QCM) humidity sensor covered with chitosan/molybdenum disulfide (CS/MoS2) composite film. The prepared sensor possesses promising humidity sensing performance with high sensitivity [46.06 Hz/% relative humidity (RH)], short response/recovery time (15/3 s), and small humidity hysteresis (2.5% RH). Most notably, the MoS2 nanoflowers that play a supporting role in the CS/MoS2 composite significantly reduce the swelling effect of CS in humid environments, enabling the CS/MoS2-based QCM humidity sensor to maintain a high ${Q}$ -factor even under high humidity conditions, thereby considerably improving the stability of the sensor.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Narrow Linewidth Terahertz Filter Based on Gold-Coated Polymer Plates With
           Corrugations

    • Free pre-print version: Loading...

      Authors: Ya-Xian Fan;Hai-Ling He;Shi-Yang Zhang;Jing Ma;Huan Liu;Zhi-Yong Tao;
      Pages: 1854 - 1859
      Abstract: Terahertz (THz) devices, especially for narrowband filters, have been widely investigated over the past decades, but mostly based on semiconductor materials or metamaterials. Here, we experimentally and numerically demonstrate a waveguide-type narrowband THz filter, which is realized by two parallel plates with corrugations. The corrugated plates are fabricated by sputtering a layer of gold after laser ablation of polymer sheets. The laser periodically etches the groove and produces a wide groove in the middle, which destroys the periodicity of the structure and forms a defect. The periodicity provides a forbidden band, in which THz waves cannot propagate, and the defect leads to an additional transmission in the forbidden band. This additional transmission occurs in the middle of the gap and has a very narrow linewidth, which is a good candidate for THz filtering. The achieved linewidth and the extinction ratio are about 1.5 GHz and 29 dB, respectively, limited by our experimental system, which are further optimized in numerical simulations. The proposed fabrication method is very efficient in THz waveguide devices, which can be easily integrated in applicable THz systems.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • MiRNA-155 Biosensors Based on AlGaN/GaN Heterojunction Field Effect
           Transistors With an Au-SH-RNA Probe Gate

    • Free pre-print version: Loading...

      Authors: Yue He;Ke-Yue Chen;Ting-Ting Wang;Mao Jia;Li-Hua Bai;Xiao Wang;Yu-Yu Bu;Jin-Ping Ao;
      Pages: 1860 - 1864
      Abstract: AlGaN/gallium nitride (GaN) heterojunction field effect transistors (HFETs) have been researched widely in the fields of gas detection and ions detection. In this article, we develop a biosensor based on AlGaN/GaN HFETs to detect the tumor biomarker miRNA-155 directly. By fixing the specific sulfhydryl modified ribonucleic acid (SH-RNA) probe on the Au-gate surface of the AlGaN/GaN HFET to fabricate an RNA-Au-AlGaN/GaN HFET biosensor, this biosensor can conveniently and rapidly detect miRNA-155. The experimental results show that this biosensor has an excellent detection limit of 1.81 fM and a high sensitivity of $77,mu text{A}$ /log concentration with a linear range (2 fM–2 nM). The limit of detection is the lowest among the reported AlGaN/GaN HFET RNA biosensors. Meanwhile, this biosensor shows a high specific recognition capacity but is weak sensitive to the mismatched miRNA.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Highly Sensitive Flexible Pressure Sensor Based on Inter-Comb Structured
           Graphene Electrodes

    • Free pre-print version: Loading...

      Authors: Shilin Lu;Tianchun Nie;Yang Li;Yuanyue Li;Zhao Yao;Nam Young Kim;Shandong Li;
      Pages: 1865 - 1870
      Abstract: Susceptible and flexible pressure sensors have broad application prospects and market demands in bionic skin, human–machine interface, and intelligent wearable electronic devices. However, optimizing the sensor’s sensitivity through a simple, low-cost process is still a considerable challenge. In this work, the sensitivity of a capacitive pressure sensor was effectively improved by optimizing the geometry of the laser-scribed graphene (LSG) electrodes. The pressure sensor, based on the inter-comb structured LSG electrodes and polyvinyl pyrrolidone nanofiber membrane (PVP NM) dielectric layer, has a high sensitivity (4.352 kPa $^{-{1}}$ at 0–2 kPa), a fast response/recovery time (40/37 ms), an ultralow detection limit ( $sim $ 12 Pa), and excellent mechanical stability (6000 cycles). The sensor developed in this research can be used in health monitoring such as carotid artery pulsation and respiratory disease. In addition, the $6times $ 6 sensor array can precisely characterize the regional pressure distribution. This study demonstrates the significant potential of the inter-comb structured LSG electrodes in highly sensitive flexible pressure sensors.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Investigating Thermionic Emission Properties of Polycrystalline Perovskite
           BaMoO3

    • Free pre-print version: Loading...

      Authors: Lin Lin;Ryan Jacobs;Dane Morgan;John Booske;
      Pages: 1871 - 1877
      Abstract: Recent experimental thermionic emission characterization measurements of the perovskite oxide SrVO3 demonstrated that low work functions can be achieved with intrinsic surface dipoles on monolithic polar perovskites, while recent density functional theory (DFT) calculations suggest that many perovskites in addition to SrVO3 may also show low work function. In this investigation, we studied the thermionic emission behavior of another perovskite suggested from DFT, BaMoO3, together with its related physical properties. The temperature limited emission current density increases and then saturates with increasing voltage, consistent with patch field theory. The overall effective work functions are 2.6–2.7 eV, comparable to other thermionic emitters like LaB6, but much higher than the 1.0 eV DFT-predicted lowest work function. We attribute this discrepancy to patch field effects caused by nanoscale features decorating individual surface facets. The resulting heterogeneity yields thermionic emission characteristic of an effective work function higher than the lowest local facet work functions. Additionally, the material shows some instability when operating at high temperatures over 1200°C. Nevertheless, BaMoO3 shows emission behavior comparable to LaB6 when operated at temperatures of $< 1200~^{circ }text{C}$ , and may find use as a vacuum electron source in vacuum electronic applications such as electron microscopes and electron beam writers.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Powerful Automodulation Oscillations in a Gyrotron With a Complicated
           Cavity

    • Free pre-print version: Loading...

      Authors: Ivan V. Osharin;Roman M. Rozental;Andrei V. Savilov;
      Pages: 1878 - 1885
      Abstract: In this article, the possibility of obtaining an automodulation output signal in a powerful (megawatt-level) gyrotron is investigated. Self-modulation of the output power can be provided in a highly efficient (tens of percent) gyrotron-type regime using complicated operating cavities with special axial irregularities (phase correctors).
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Novel Injection-Locked S-Band Oven Magnetron System
           Without Waveguide Isolators

    • Free pre-print version: Loading...

      Authors: Shaoyue Wang;Yang Shen;Chongwei Liao;Jianwei Jing;Changjun Liu;
      Pages: 1886 - 1893
      Abstract: A novel injection-locked ${S}$ -band microwave oven magnetron system is proposed, analyzed, and experimented. The magnetron is considered as a two-port oscillator, and the filament structures of it are used as a port for injection locking. To our knowledge, it is the first time that microwaves have been injected through magnetron filaments. The microwave is injected into the magnetron filter box using a self-designed injection structure, entering the resonant cavity through filament leads. The intrinsic isolation between the magnetrons’ output and filament is utilized as an isolator. No waveguide circulators or couplers between the injection source and the magnetron were used in the system, resulting in low cost and compact injection locking. Two types of injection structures were performed. The maximum locking bandwidth of 0.7 MHz was achieved at an injection ratio of 0.2. The weight and volume of the proposed injection-locked magnetron system were reduced to 28% and 16%, respectively. The magnetron’s output is successfully locked by an external signal. The experiment results reveal that the proposed low-cost injection-locked oven magnetron system works reliably. It has significant potential applications for future microwave ovens with frequency-selective heating to improve both efficiency and uniformity.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Air Channel Space-Charge-Limited Transistor

    • Free pre-print version: Loading...

      Authors: Zhihua Shen;Qiaoning Li;Xiao Wang;Bin Ge;Shengli Wu;Jinshou Tian;
      Pages: 1894 - 1897
      Abstract: A vertical structural air channel transistor with a gate block dielectric layer, which can isolate gate from air channel, was proposed. With the presence of gate block dielectric layer, electrons at the edge of the 2-D electron system (2-DES) formed at gate are prevented to be injected into air channel, which may effectively minish the gate leakage current compared to the conventional vertical structure. The transistor operates in the space-charge-limited (SCL) regime of thermionic emission, which makes it theoretically possess the advantages of high-temperature reliability and low power consumption. Simulation results indicate that this transistor can achieve transconductance of $34.2~mu text{S}$ and cutoff frequency of 88.2 GHz by optimizing the dimensional parameters.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Simulation of Parasitic Backward-Wave Excitation in High-Power Gyrotron
           Cavities

    • Free pre-print version: Loading...

      Authors: Konstantinos A. Avramidis;Alexander Marek;Ioannis Chelis;Zisis C. Ioannidis;Lukas Feuerstein;John Jelonnek;Manfred Thumm;Ioannis Tigelis;
      Pages: 1898 - 1905
      Abstract: The possibility of parasitic excitation of backward waves directly in the gyrotron cavity is demonstrated, by simulation, for two existing high-power gyrotrons. These are the 140-GHz 1-MW TE $_{{28},{8}}$ -mode gyrotron for the stellarator W7-X and the 140-GHz 1.5-MW TE $_{{28},{10}}$ -mode gyrotron, also for W7-X. The parasitic backward waves, namely, the TE $_{{23},{7}}$ mode in the 1-MW gyrotron and the TE $_{{-{24},{10}}}$ mode in the 1.5-MW gyrotron, are excited at high frequencies (RF), which are of the order of $sim $ 10% lower than the nominal operating frequency and which can lead to significant performance degradation, with respect to the output power, efficiency, and stability of the tube. This finding offers an additional possibility, besides parasitic mode excitation in the gyrotron beam tunnel or after the gyrotron cavity, for the origin of experimentally observed RF parasitic oscillations in high-power, high-frequency gyrotrons, operating in high-order modes. To strengthen the confidence in the simulation, the results of two codes, each using different modeling of the interaction between the electron beam and the RF wave, are compared and the appropriateness of the modeling with respect to the accurate simulation of backward waves is discussed in detail.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Cascaded W-Band Gyro-TWT With the Configuration of Coaxial and Circular
           Waveguides

    • Free pre-print version: Loading...

      Authors: Yingjian Cao;Guo Liu;Yu Wang;Wei Jiang;Yelei Yao;Jianxun Wang;Yong Luo;
      Pages: 1906 - 1911
      Abstract: To realize a high-gain wideband millimeter-wave amplification, we present and simulate a ${W}$ -band gyrotron traveling wave tube (gyro-TWT) with cascaded coaxial- and circular-waveguide amplifiers. The amplifiers are operated in a coaxial and circular TE01 mode, respectively, and driven by two 60-kV gyrating electron beams with a pitch factor of 1.2 but different beam currents of 1 and 10 A. They are designed to possess relatively low individual gains below all oscillation thresholds to maintain high stability and achieve a high total cascaded gain for the whole gyro-TWT. A coupling circuit is adopted to cascade these two sections, converting the coaxial TE01 mode to the circular one with a −3-dB bandwidth of 6.8 GHz (94.1–100.9 GHz). particle-in-cell (PIC) simulation shows that the designed gyro-TWT can achieve a maximum saturated output power of 239.8 kW at 100 GHz, with a gain greater than 60 dB over a −3-dB bandwidth of 8.0 GHz (94.5–102.5 GHz).
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Preliminary Experimental Research on Split-Cathode-Fed Relativistic
           Magnetron With Bidirectional Emission Structure

    • Free pre-print version: Loading...

      Authors: Renjie Cheng;Tianming Li;Jiaoyin Wang;Chaoxiong He;Haiyang Wang;Hao Li;Yihong Zhou;Mingyu Yang;Meiling Ou;Tingxu Chen;Fadhel M. Ghannouchi;Biao Hu;
      Pages: 1912 - 1916
      Abstract: Simulations and experiments of an ${S}$ -band TEM-output relativistic magnetron (RM) driven by split cathode (SC) are proposed. In the previous researches on SC, as a result of the space-charge-screening effect of squeeze-state electrons accumulated nearby the emission surface, the diode current is limited, which finally results in low output power. To improve the output performance, a bidirectional emission SC (BSC) is introduced. Experimental results on EPA-90 high-voltage electron beam accelerator demonstrate that when the voltage is around 480 kV and the axial magnetic field is 0.49 T, comparing with a conventional unidirectional emission SC, the output power can be enhanced from 124 to 400 MW by adding an extra downstream emitter. This work lays a foundation for further researches to make the SC-fed RM more practical.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Novel 0.22-THz Extended Interaction Oscillator Based on the
           Four-Sheet-Beam Orthogonal Interconnection Structure

    • Free pre-print version: Loading...

      Authors: Jielong Li;Zhenhua Wu;Diwei Liu;Wei Wang;Tao Zhao;Renbin Zhong;Zongjun Shi;Kaichun Zhang;Zhaoyun Duan;Yanyu Wei;Yubin Gong;Shenggang Liu;Min Hu;
      Pages: 1917 - 1922
      Abstract: Numerous terahertz vacuum electronic devices (TVEDs) have been proposed. Among these devices, extended interaction oscillators (EIOs) exhibit small-volume, lightweight, low-working-voltage, stable-working frequency, and high-power characteristics. The ladder-line slow wave structure exhibits strong coupling and can interact with the sheet beam to considerably improve the efficiency of beam–wave interaction. In this study, a novel high-frequency structure was proposed. Four conventional ladder-line slow wave structures were placed vertically to form a four-sheet-beam orthogonal interconnection structure (OIS) that considerably increased the coupling efficiency between the cavities, improved output power and efficiency, and interacted perfectly with the TM81 mode. In this study, the dispersion characteristics and field distribution were studied through numerical and simulation calculations, and the optimal working parameters and output structure were analyzed using particle-in-cell (PIC) software. Next, a 0.22-THz extended interaction oscillator based on four-sheet-beam OSI was designed. Simulation results have shown the achievement of the output power of 0.22-THz wave over 500 W with four sheet beams at 16.6 kV and each current of 0.8 A. Finally, preliminary processing and cold tests of the structure were performed. This novel structure provided an alternative for the development of terahertz EIOs.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Investigation on Thermal Efficiency Enhancement and Sideband Emission
           Suppression for Magnetron Injection Gun

    • Free pre-print version: Loading...

      Authors: Binyang Han;Wei Jiang;Chaoxuan Lu;Boxin Dai;Jianxun Wang;Youlei Pu;Guo Liu;Zewei Wu;Yong Luo;
      Pages: 1923 - 1928
      Abstract: At low-power operation, an approach with a capture structure is employed to absorb the trapped electrons for the $textit {Ka}$ -band gyro-traveling wave tube (Gyro-TWT). When the power is further increased, the capture structure cannot play a role and the working current fluctuates. In subsequent experiments, the capture structure was found to have severe traces of melting. According to the position characteristics of the capture structure, the main reason for its melting is the phenomenon of sideband emission from the cathode of magnetron injection gun (MIG). In heat transfer systems of the conventional cathode, the rear electrode emits trapped electrons, which are accelerated by an electric field and bombard the capture structure. We adopted the scheme of adjusting the cathode heat transfer system. The enhanced cathode is called the isolated cathode (ISO-cathode). The test experiment proved that sideband emission is suppressed and thermal efficiency is improved. In the experiment, the cathode power decreased from 85 to 42 W when the operating temperature is at 1050 °C. In the end, the absorbed power of the capture structure is less than about 1/10 of the original power by simulation. The life and reliability of MIG are increased by ISO-cathode. The foundation is laid for further improvement on the average power by ISO-cathode.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Design and Efficiency Enhancement of Klystron-Like Relativistic Backward
           Wave Oscillator With Triple Cavity Extractor

    • Free pre-print version: Loading...

      Authors: Pratibha Verma;M. Thottappan;
      Pages: 1929 - 1935
      Abstract: In this article, the design and investigation of an ${X}$ -band klystron-like relativistic backward wave oscillator (KL-RBWO) are presented. The present design includes three extractor cavities at the output Section of KL-RBWO that has been studied for their beam-wave interaction behavior using a finite difference time domain (FDTD) based 3-D electromagnetic (EM) particle-in-cell (PIC) code. The three extractor cavities used in the downstream of KL-RBWO before the collector increased the overall efficiency of the device with a sharp increase in the axial electric field and current in the region. The PIC simulation of the present KL-RBWO predicted an RF power of $sim $ 2.3 GW at $sim $ 9.55 GHz with electronic efficiency of $sim $ 60% for the developed electron beam current of $sim $ 6.72 kA. A constant microwave generation was observed up to 270 ns under the external guiding magnetic field of 2.9 T.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Frequency-Tunable Sub-Terahertz Gyrotron With External Mirror: Design and
           Simulations

    • Free pre-print version: Loading...

      Authors: Ilya V. Bandurkin;Yuriy K. Kalynov;Ivan V. Osharin;Andrei V. Savilov;Evgeniy S. Semenov;
      Pages: 1936 - 1941
      Abstract: In this article, we describe a concept of a sub-terahertz frequency-tunable gyrotron based on a combination of a low-Q irregular cavity and a frequency-tunable external reflector. Simulations predict possibilities for the creation of gyrotrons with high (10% and higher) efficiency provided in a wide (~10%) frequency band.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • An Experimental Study on Novel Gas Discharge Tubes With Graphene as
           Electron Emission Material

    • Free pre-print version: Loading...

      Authors: Mingyu An;Hao Lu;Wenjun Zhao;Chuanxiao Zheng;Yanlin Wang;Yong Hu;
      Pages: 1942 - 1949
      Abstract: Electrical equipment is subjected to gas discharge tube (GDT) direct current (dc) breakdown voltage dispersion and breakdown voltage drop after a surge. It is noteworthy that GDT damage may even cause the failure of electrical equipment. Accordingly, the chemical vapor deposition (CVD) of graphene was proposed in this study as an electron emission material of the GDT based on the existing electron powder GDT. The GDT exhibiting a voltage class of 470 V was prepared, and its structure and surge characteristics were analyzed. The effects of gas pressure, aging time, and ambient temperature on the breakdown voltage of the graphene GDT were studied. The surge process of the graphene GDT was simulated using the 8/ $20~mu text{s}$ impulse current generator, and the resistance ability of the graphene GDT against the surge was examined. Moreover, it was compared with the same type of commercial electron powder GDT. As indicated by the experimental results, a positive correlation was identified between the gas pressure and the dc breakdown voltage of the graphene GDT under a certain pressure. The effect of aging time and ambient temperature on dc breakdown voltage was limited. The breakdown voltage of the graphene GDT was first increased and then decreased with the increase in the number of surges. After 100 surges, the breakdown voltage of the graphene GDT stabilized at 350 V, whose stability was better than that of the electron powder GDT. The above-described analysis confirmed that graphene GDT exhibits better surge resistance ability.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Experimental Study on the Frequency Tunability of a Magnetically Insulated
           Transmission Line Oscillator

    • Free pre-print version: Loading...

      Authors: Xiaoyu Wang;Zeyang Liu;Baoping Yang;Wenqiang Xu;Ting Shu;Yuwei Fan;Bing Han;
      Pages: 1950 - 1955
      Abstract: In the present study, the frequency tunability of a magnetically insulated transmission line oscillator (MILO) is investigated by simulation in conjunction with an experiment. In the simulation, the tunable MILO reaches a maximum output power of approximately 5.0 GW with an applied voltage of 590 kV and an input power of 29 GW. The corresponding power efficiency is 17.2%, and the frequency is 1.575 GHz. In addition, by adjusting the outer radius of the vane from 77 to 150 mm, the 3-dB tunable frequency of the tunable MILO ranges from 0.85 to 2.12 GHz, and the tuning bandwidth is 85.5%. The experimental results show that when the voltage and current are 405 kV and 42 kA, respectively, the peak microwave power of the tunable MILO is approximately 2.3 GW with a microwave frequency of approximately 1.900 GHz. The difference in the two frequencies at the peak microwave power is significant because of the tuning mechanism. When the outer radius of the vane varies in the range of 76.6–93.0 mm, the 3-dB tunable frequency range is between 1.552 and 2.168 GHz, corresponding to a 3-dB tuning bandwidth of 33.1%. The experimental measurements verify the simulation results.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Cold-Test Characterization of Metamaterial-Assisted Side Coupled Cavity

    • Free pre-print version: Loading...

      Authors: Neetu Kumari;Manpuran Mahto;Pradip Kumar Jain;
      Pages: 1956 - 1961
      Abstract: In this article, a new S-band metamaterial-assisted side coupled cavity (MSCC) structure is proposed for high-power microwave (HPM) applications. The electromagnetic features of the proposed MSCC and conventional side coupled cavity (SCC) are investigated. The dispersion curve and average interaction impedance of the two models have been compared to ascertain the advantages of MSCC over SCC. For the $pi $ /2 mode resonant frequency, the radial dimension of MSCC is 17 mm, whereas the radial dimension of the conventional SCC is 39 mm. The average interaction impedance of the proposed MSCC is $sim 200,Omega $ , while it is $sim 110,Omega $ for the SCC. The proposed MSCC offers high average interaction impedance and compact size compared to SCC. The transmission properties of the fabricated MSCC have been measured with the help of Anritsu MS2037C VNA Master. The measured reflection coefficient confirms the operation of MSCC at 2.89 GHz. The measured and simulated values of reflection and transmission coefficients are in good agreement. The proposed structure is designed to be used as a modulation cavity in one of the prominent HPM sources, i.e., Reltron oscillator.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Effective Numerical Simulations of Multipactor by WBPAT Theory

    • Free pre-print version: Loading...

      Authors: Xi Chao Bo;Hongguang Wang;Yonggui Zhai;Xinbo Wang;Jian Feng Zhang;Tie Jun Cui;
      Pages: 1962 - 1969
      Abstract: We propose a fast electromagnetic particle-in-cell (EM-PIC) method to simulate multipactor in waveguide devices. First, complex amplitudes (amplitudes and phases) at multiple frequencies are quantitatively extracted by using the wideband power-to-amplitude transformation (WBPAT) algorithm in the finite-difference time-domain (FDTD) method. Then the charged particles are advanced one way from the time-domain (TD) electromagnetic (EM) fields transformed from the complex amplitudes without considering the space-charge effects. Therefore, the conventional FDTD iterations and interpolations to cell nodes are avoided at the iterative stage. As a result, the simulation efficiency can be greatly improved. The efficiency can be further promoted by using the time step magnification and local region simulation. The proposed method can also be utilized for analyzing the multicarrier multipactor. For the ${C}$ -band impedance transformer under the excitations by different multicarrier waveforms, the simulation speed of the proposed method can be improved by several orders of magnitude and the accuracy of the power threshold is comparable with the self-consistent simulation.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Demonstration of a Nanosheet FET With High Thermal Conductivity Material
           as Buried Oxide: Mitigation of Self-Heating Effect

    • Free pre-print version: Loading...

      Authors: Sunil Rathore;Rajeewa Kumar Jaisawal;P. N. Kondekar;Navjeet Bagga;
      Pages: 1970 - 1976
      Abstract: Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures. Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect (SHE) is a prime concern as the channels are surrounded by low-thermal conductivity material (i.e., a stack of SiO2 and HfO2 layers). In this article, through well-calibrated TCAD models, we propose a buried oxide (BOX) engineered NSFET structure, which provides an appropriate heat flow path and mitigates the SHE-induced degradation. Unlike the conventional NSFET, where SiO2 is kept as a BOX layer, in the proposed NSFET, a crystalline-diamond-like carbon (DLC) is placed ubiquitously beneath the lower sheet, resulting in a reduction in the lattice temperature from the device active region (channel/sheet) toward the DLC substrate. Furthermore, the impact of device geometry, such as channel length ( ${L}_{g}$ ), channel width ( ${T}_{w}$ ), BOX thickness ( ${T}_{{text {BOX}}}$ ), and the number of vertically stacked sheets ( ${N}_{S}$ ), on the thermal and electrical reliability of the proposed device has been investigated.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • A Multiscale Simulation Study of the Structural Integrity of Damascene
           Interconnects in Advanced Technology Nodes

    • Free pre-print version: Loading...

      Authors: Sagarika Mukesh;Nicholas A. Lanzillo;
      Pages: 1977 - 1982
      Abstract: The structural stability of tight-pitched (18 nm and below) damascene interconnects for back-end-of-line (BEOL) technologies are analyzed using force-field-based molecular dynamics simulations and finite-element modeling. At these pitches surface energy-dominated effects come into the picture, which lead to structural instability. The candidate metals analyzed are beyond copper (Cu) interconnect metals-ruthenium (Ru), cobalt (Co), and tungsten (W); and Cu is analyzed for reference. Cohesive traction and normal bonding energy are calculated using force-field- based molecular dynamics simulations and then fed as input to a finite-element analysis (FEA) tool, where their dependence on the physical dimensions of the interconnect lines is studied. The parameters studied for the BEOL structures are sidewall angle, aspect ratio, the internal stress of the metal, and modulus of elasticity of the dielectric material around the metal to understand the sensitivity of these parameters to the structural stability of the interconnects. We observe that a lower aspect ratio and higher modulus of elasticity of the dielectric results in stable structures whereas, intrinsic stress of the metal and side wall angle have a minor impact on the overall stability. The stability is analyzed at the seed-layer deposition step and based on this study, Co is the most stable alternate metal amongst Ru, Co, and W.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Wake-Up and Endurance Characteristics in Hf0.5Zr0.5O2-Based
           Metal-Ferroelectric-Metal Capacitor Depending on the Crystal Orientation
           of the TiN Bottom Electrodes

    • Free pre-print version: Loading...

      Authors: Dong Hee Han;Ae Jin Lee;Min Kyeong Nam;Seungwoo Lee;Su Jin Choi;Youngjin Kim;Taehwan Moon;Woojin Jeon;
      Pages: 1983 - 1988
      Abstract: The ferroelectric properties of Hf0.5Zr0.5O2(HZO) according to the preferred orientations of the titanium nitride (TiN) bottom electrode (BE) were investigated. The (111) and (200)-oriented TiN were used as BEs. The difference in crystallinity of HZO was observed and the following electrical properties were compared. By employing the various crystal structure analyses and electrical measurements, it was found that the HZO thin film grown on TiN(200) forms more ferroelectric non-centrosymmetric orthorhombic phase in the pristine state due to the local epitaxial relation between TiN(200) and HZO.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Memristor-Based Cryogenic Programmable DC Sources for Scalable In Situ
           Quantum-Dot Control

    • Free pre-print version: Loading...

      Authors: Pierre-Antoine Mouny;Yann Beilliard;Sébastien Graveline;Marc-Antoine Roux;Abdelouadoud El Mesoudy;Raphaël Dawant;Pierre Gliech;Serge Ecoffey;Fabien Alibart;Michel Pioro-Ladrière;Dominique Drouin;
      Pages: 1989 - 1995
      Abstract: Current quantum systems based on spin qubits are controlled by classical electronics located outside the cryostat. This approach creates a major wiring bottleneck, which is one of the main roadblocks toward scalable quantum computers. Thus, we propose a scalable memristor-based programmable dc source that can perform biasing of quantum dots (QDs) inside the cryostat. This novel cryogenic approach would enable to control the applied voltage on the electrostatic gates by programming the resistance of the memristors, thus storing in the latter the appropriate conditions to form the QDs. In this study, we first demonstrate multilevel resistance programming of TiO2 memristors at 4.2 K, an essential feature to achieve voltage tunability of the memristor-based dc source. We then report hardware-based simulations of the electrical performance of the proposed dc source. A cryogenic TiO2 memristor model fit on our experimental data at 4.2 K was used to show a 1 V voltage range and 100 $mu text{V}$ resolution in situ memristor-based dc source. Finally, we simulate the biasing of double QDs (DQDs), enabling 120 s stability diagrams. This demonstration is a first step toward advanced cryogenic applications for resistive memories, such as cryogenic control electronics for quantum computers.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Effect of Scandium Insertion Into the Gate-Stack of Ferroelectric
           Field-Effect Transistors

    • Free pre-print version: Loading...

      Authors: Bong Ho Kim;Song-Hyeon Kuk;Seong Kwang Kim;Joon Pyo Kim;Yoon-Je Suh;Jaeyong Jeong;Dae-Myeong Geum;Seung-Hyub Baek;Sang Hyeon Kim;
      Pages: 1996 - 2000
      Abstract: We demonstrated improved switching voltage and retention and endurance characteristics in HfZrOx (HZO)-based ferroelectric field-effect transistors (FeFETs) via oxygen scavenging with Sc. Insertion of Sc into the gate-stack successfully reduced the thickness of the interfacial SiOx layer (IL) between HZO and Si; thus, the FeFET with Sc could perform an immediate read-after-write at a 2-V pulse. In addition, although the IL thickness became thinner, the endurance characteristics of FeFETs with Sc were improved up to $10^{{10}}$ cycles, due to the lower ${V}_{g}$ required for the same memory window (MW) and less trapping when positive pulses are applied. We believe that this work contributes to the low-voltage operation of FeFET and proposes the potential of oxygen scavenging.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory

    • Free pre-print version: Loading...

      Authors: Ming-Shyue Yeh;Ya-Ching Wang;Yao-Hung Huang;Jiaw-Ren Shih;Yue-Der Chih;Jonathan Chang;Chrong-Jung Lin;Ya-Chin King;
      Pages: 2001 - 2008
      Abstract: In this study, a multilevel logic-compatible two-transistor-two-resistor (2T2R) latch array for computing-in-memory (CIM) is proposed, featuring high power efficiency, fast response, and high resolution. Combining the resistive switching pairs of the Hf-based gate dielectric layers and a near-threshold-operated output transistor for resistance ratio enhancement, non-volatile memory (NVM) latch arrays are implemented on Si. Taking the advantage of the stable and reliable output by complementary resistive states, the ON– OFF current ratio can be greatly improved. In addition, low power consumption by the near-threshold operation, high data density by multilevel cell, and the novel latch arrays successfully enhance the accuracy and lower power of the analog multiply–accumulate-operation (MAC) and become a promising module in the CIM applications.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Experimental Assessment of Multilevel RRAM-Based Vector-Matrix
           Multiplication Operations for In-Memory Computing

    • Free pre-print version: Loading...

      Authors: Emilio Perez-Bosch Quesada;Mamathamba Kalishettyhalli Mahadevaiah;Tommaso Rizzi;Jianan Wen;Markus Ulbricht;Milos Krstic;Christian Wenger;Eduardo Perez;
      Pages: 2009 - 2014
      Abstract: Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of $8times $ 8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Machine Learning-Assisted Statistical Variation Analysis of Ferroelectric
           Transistor: From Experimental Metrology to Adaptive Modeling

    • Free pre-print version: Loading...

      Authors: Gihun Choe;Prasanna Venkatesan Ravindran;Jae Hur;Maximilian Lederer;André Reck;Asif Khan;Shimeng Yu;
      Pages: 2015 - 2020
      Abstract: A novel machine learning (ML)-assisted approach is proposed for investigating the variability of ferroelectric field-effect transistor (FeFET) to shorten the loop of technology pathfinding. To quantify the ferroelectric (FE) domain variation, the atomic intragranular misorientation of Si-doped HfO2 thin film is measured by transmission Kikuchi diffraction (TKD) and is transformed into a polarization map. With the metrology data, polarization variation (PV) of FE domains on the gate-stack is modeled in technology computer-aided design (TCAD) to assess the impact of PV on the FeFET performance and to obtain datasets for ML-assisted analysis. A neural network model is trained using the datasets (input: polarization maps; output: high/low threshold voltage, ON-state current, and subthreshold slope) for the 28-nm bulk FeFET analysis. Our trained network, if used for inference to obtain three-sigma statistics, shows >98% of accuracy of the device features and significantly faster simulation time than TCAD. In addition, we used the transfer learning technique to reduce the number of training datasets by 83% for the fully depleted silicon-on-insulator (FDSOI) FeFET by applying the pretrained model from the bulk FeFET.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Leveraging Voltage-Controlled Magnetic Anisotropy to Solve Sneak Path
           Issues in Crossbar Arrays

    • Free pre-print version: Loading...

      Authors: Kezhou Yang;Abhronil Sengupta;
      Pages: 2021 - 2027
      Abstract: In crossbar array structures, which serves as an “in-memory” compute engine for artificial intelligence (AI) hardware, write sneak path problem causes undesired switching of devices that degrades network accuracy. While custom crossbar programming schemes have been proposed, device-level innovations leveraging nonlinear switching characteristics of the cross-point devices are still under exploration to improve the energy eff iciency of the write process. In this work, a spintronic device design based on magnetic tunnel junction (MTJ) exploiting the use of voltage-controlled magnetic anisotropy (VCMA) effect is proposed as a solution to the write sneak path problem. In addition, insights are provided regarding appropriate operating voltage conditions to preserve the robustness of the magnetization trajectory during switching, which is critical for proper switching probability manipulation.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Fabrication of GeSn Nanowire MOSFETs by Utilizing Highly Selective Etching
           Techniques

    • Free pre-print version: Loading...

      Authors: Tzu-Chieh Hong;Wen-Hsiang Lu;Yeong-Her Wang;Jiun-Yun Li;Yao-Jen Lee;Tien-Sheng Chao;
      Pages: 2028 - 2033
      Abstract: Germanium–tin (GeSn) epitaxy layer was prepared on an 8-in SOI wafer with a Ge buffer layer. The etching rates of different solutions for the GeSn layer were investigated. The ammonia peroxide mixture can remove the Ge buffer layer with high efficiency and selectivity to the GeSn layer. Heated ammonia solution is able to etch the Si layer without damaging the GeSn layer significantly. The two-step etching process developed in this study is conducive to achieving GeSn nanowires (NWs) by selectively etching the Ge buffer and Si bottom layers. GeSn NWFETs were fabricated and measured. The strain of the GeSn NW channels is preserved with the optimized fabrication process proposed in this study.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Physics-Based Modeling and Validation of 2-D Schottky Barrier Field-Effect
           Transistors

    • Free pre-print version: Loading...

      Authors: Ashwin Tunga;Zijing Zhao;Ankit Shukla;Wenjuan Zhu;Shaloo Rakheja;
      Pages: 2034 - 2041
      Abstract: In this work, we describe the charge transport in 2-D Schottky barrier field-effect transistors (SB-FETs) based on the carrier injection at the Schottky contacts. We first develop a numerical model for thermionic and field-emission processes of carrier injection that occur at a Schottky contact. The numerical model is then simplified to yield an analytic equation for current versus voltage ( ${I}$ – ${V}$ ) in the SB-FET. The lateral electric field at the junction, controlling the carrier injection, is obtained by accurately modeling the electrostatics and the tunneling barrier width. Unlike previous SB-FET models that are valid for near-equilibrium conditions, this model is applicable for a broad bias range, as it incorporates the pertinent physics of thermionic, thermionic field-emission (TFE), and field-emission processes from a 3-D metal into a 2-D semiconductor. The ${I}$ – ${V}$ model is validated against the measurement data of two-, three-, and four-layer ambipolar MoTe2 SB-FETs fabricated in our laboratory, as well as the published data of unipolar 2-D SB-FETs using MoS2. Finally, the model’s physics is tested rigorously by comparing model-generated data against TCAD simulation data.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Trench Gate Nanosheet FET to Suppress Leakage Current From Substrate
           Parasitic Channel

    • Free pre-print version: Loading...

      Authors: Khwang-Sun Lee;Byung-Do Yang;Jun-Young Park;
      Pages: 2042 - 2046
      Abstract: Recently, nanosheet FETs (NS FETs) have been introduced as promising candidates for beyond 3-nm node technology. However, difficulties remain for mass production of the NS FETs. One of the concerns is increased OFF-state current ( ${I}_{ mathrm{OFF}}$ ) due to leakage current from the substrate parasitic channel. Since the NS FET includes a 2-D parasitic FET on the bottom substrate, increased leakage current through the bottom is inevitable. The traditional methodology to suppress the leakage current from the parasitic channel is to use a punchthrough stopper (PTS). However, the PTS requires both ion implantation and an annealing process, which are detrimental to device yield. In this context, the trench gate (TG) NS FET is proposed as a new device architecture. The TG structure increases the effective gate length ( ${L}_{Gtext {,EFF}}$ ) of the parasitic FET, reducing the leakage current through the bottom. Moreover, the fabrication process for the TG NS FET is fully compatible with conventional processes.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Physically Transient Artificial Neuron Based on Mg/Magnesium Oxide
           Threshold Switching Memristor

    • Free pre-print version: Loading...

      Authors: Yaxiong Cao;Saisai Wang;Rui Wang;Jing Sun;Mei Yang;Xiaohua Ma;Hong Wang;Yue Hao;
      Pages: 2047 - 2051
      Abstract: Threshold switching (TS) devices have received significant interests for constructing high-density integrated and energy-efficient artificial neurons in neuromorphic computing. On the other hand, physically transient electronics that can vanish harmlessly after completing the assigned task have great potential for temporary biomedical devices and secure information systems. Therefore, the development of physically transient artificial neurons based on TS devices has the wide application prospects in biointegrated medical electronics and security neuromorphic computing. However, physically transient artificial neurons based on TS devices are still lacking. Here, a physically transient artificial neuron realized with a W/MgO/Mg/W memristor device is proposed. The transient device shows robust TS characteristics with fast switching speed and high switching endurance (105 circles). The key functions of a biological neuron were successfully emulated by the leaky integrate-and-fire (LIF) neuron implemented with this transient device. In addition, the device’s arrays on a poly (vinyl alcohol) (PVA) substrate can disintegrate completely when soaked in deionized (DI) water at room temperature (RT) for 40 min. These results demonstrate that physically transient artificial neurons pave the way for applications in secure neuromorphic computing, biointegrated electronics, and human–machine interfaces.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD
           In2O3 FETs Toward Monolithic 3-D Integration

    • Free pre-print version: Loading...

      Authors: Pai-Ying Liao;Dongqi Zheng;Sami Alajlouni;Zhuocheng Zhang;Mengwei Si;Jie Zhang;Jian-Yu Lin;Tatyana I. Feygelson;Marko J. Tadjer;Ali Shakouri;Peide D. Ye;
      Pages: 2052 - 2058
      Abstract: In this work, the transient thermal and electrical characteristics of top-gated (TG), ultrathin, atomic-layer-deposited (ALD), back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors on various thermally conductive substrates are co-optimized by visualization of the self-heating effect (SHE) utilizing an ultrafast high-resolution (HR) thermo-reflectance (TR) imaging system and overcome the thermal challenges through substrate thermal management and short-pulse measurement. At the steady-state, the temperature increase ( $Delta {T}$ ) of the devices on highly resistive silicon (HR Si) and diamond substrates are roughly 6 and 13 times lower than that on a SiO2/Si substrate, due to the much higher thermal conductivities ( $kappa $ ) of HR Si and diamond. Consequently, the ultrahigh drain current ( ${I}_{D}$ ) of 3.7 mA/ $mu text{m}$ at drain voltage ( ${V}_{text {DS}}$ ) of 1.4 V with direct current (dc) measurement is achieved with TG ALD In2O3 FETs on a diamond substrate. Furthermore, transient thermal study shows that it takes roughly 350 and 300 ns for the devices to heat-up and cool-down to the steady-states, being independent of the substrate. The extracted thermal time constants of heat-up ( $tau _{h}$ ) and cool-down ( $tau _{c}$ ) processes are 137 and 109 ns, respectively. By employing electrical short-pulse measurement with a pulsewidth ( ${t}_{text {pulse}}$ ) shorter than $tau _{h}$ , the SHE can be significantly reduced. Accordingly, a higher ${I}_{D}$ of 4.3 mA/ $mu text{m}$ is realized with a 1.9-nm-thick In2O3 FET on HR Si substrate after co-optimization. Besides, to integrate BEOL-compatible ALD In2O3 transistors on the front-end-of-line (FEOL) devices with the maintenance of the satisfactory heat dissipation capability, a FEOL-interlayer-BEOL structure is proposed where the interlayer not only electrically isolates the FEOL and BEOL devices but also serves as a thermally conductive layer to alleviate the SHE.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Back-End-of-Line-Compatible Fin-Gate ZnO Ferroelectric Field-Effect
           Transistors

    • Free pre-print version: Loading...

      Authors: Qiwen Kong;Long Liu;Zijie Zheng;Chen Sun;Zuopu Zhou;Leming Jiao;Annie Kumar;Rui Shao;Jishen Zhang;Haiwen Xu;Yue Chen;Bich-Yen Nguyen;Xiao Gong;
      Pages: 2059 - 2066
      Abstract: We report the back-end-of-line (BEOL)-compatible 3-D oxide semiconductor (OS) fin-gate ferroelectric field-effect transistors (Fe-FETs) featuring atomic layer deposition (ALD)-grown zinc oxide (ZnO) channel and Zr-doped HfO2 (HZO) ferroelectric dielectric. Both ZnO and HZO are able to conformally cover the fin-shaped tungsten (W) metal gate with uniform thickness on all surfaces. With the optimization of ALD for the growth of the ZnO channel film and extensive gate-stack engineering, our ZnO Fe-FETs show excellent electrical characteristics, including memory windows (MWs) of 1.9 and 1.5 V with the channel length ( ${L}_{text {ch}}$ ) of $1~mu text{m}$ and 50 nm, respectively, the high endurance of $10^{{8}}$ cycles, long-term retention of more than ten years at room temperature, robust ON/OFF ratio of more than six orders, and good linearity of the multistate conductance characteristics. Together with the capability to suppress the device-to-device threshold voltage ( ${V}_{text {th}}$ ) variation due to the unique fin-gate structure, our devices demonstrate tremendous potential for future ultrahigh-density 3-D integrated computing applications.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Dielectric Interface Engineering for High-Performance Monolayer MoS2
           Transistors via TaOxInterfacial Layer

    • Free pre-print version: Loading...

      Authors: Hao-Yu Lan;Vladimir P. Oleshko;Albert V. Davydov;Joerg Appenzeller;Zhihong Chen;
      Pages: 2067 - 2074
      Abstract: Field-effect transistors (FETs) based on 2-D materials have great potential for future ultimate-scaled electronics. However, nonideal semiconductor–dielectric interfaces due to interfacial traps and oxide traps have constrained the potential of 2-D semiconductors. Here, we report a new dielectric interface engineering approach for monolayer (1L) MoS2 transistors employing a relatively high- $kappa $ TaOx interfacial layer ( $kappa sim $ 7) whose defect bands are located outside of the operation window of the MoS2 Fermi level. Such band alignment can minimize active interface trap states in top-gate (TG) dielectric stacks. The TaOx interfacial layer can also act as an efficient doping layer, with the highest ON-current ${I}_{text {on}}$ reaching 861 $mu text{A}/mu text{m}$ at ${V}_{text {DS}} $ = 1.5 V and overdrive voltage ${V}_{text {OV}} $ = 3 V. The lowest contact resistance is down to $230 Omega cdot mu text{m}$ . Dual-gate (DG) FETs can achieve subthreshold slope (SS) values down to $sim $ 70 mV/dec in short-channel devices ( ${L}_{text {CH}} =55$ –75 nm). Our reported SS, ${I}_{text {on}}$ , and ${R}_{C}$ are among the best-r-ported values for MoS2 devices. For low-power applications, our devices exhibit a record-high ${I}_{text {on}}$ of 598 $mu text{A}/mu text{m}$ at ${V}_{text {DS}} =0.65$ V. The new dielectric engineering approach proposed in this study can pave the way for realizing high-performance logic devices based on 2-D materials.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Record RF Power Performance at 94 GHz From Millimeter-Wave N-Polar
           GaN-on-Sapphire Deep-Recess HEMTs

    • Free pre-print version: Loading...

      Authors: Weiyi Li;Brian Romanczyk;Matthew Guidry;Emre Akso;Nirupam Hatui;Christian Wurm;Wenjian Liu;Pawana Shrestha;Henry Collins;Christopher Clymore;Stacia Keller;Umesh K. Mishra;
      Pages: 2075 - 2080
      Abstract: In this article, N-polar GaN-on-sapphire deep-recess metal–insulator–semiconductor (MIS)-high-electron-mobility transistors (HEMTs) with a breakthrough performance at ${W}$ -band are presented. Compared with prior N-polar GaN MIS-HEMTs, a thin GaN cap layer and atomic layer deposition (ALD) ruthenium (Ru) gate metallization were used along with high-quality GaN-on-sapphire epitaxy from Transphorm Inc. Before SiN passivation, 94 GHz large signal load–pull shows that the transistor obtains a record-high 9.65 dB linear transducer gain and demonstrated 42% power-added efficiency (PAE) with associated 4.4 W/mm of output power density at 12 V drain bias. By biasing the drain at 8 V, the device shows an even higher PAE of 44% with an associated 2.6 W/mm of output power density. After SiN passivation, the fabricated N-polar GaN-on-sapphire HEMTs show a high PAE of 40.2% with an associated 4.85 W/mm of output power density. Furthermore, a very high output power density of 5.83 W/mm with 38.5% PAE is demonstrated at a 14 V drain bias. This power performance shows significant efficiency improvement over previous N-polar GaN-on-SiC and demonstrates a combined efficiency and power density beyond what has been reported for Ga-polar devices, in spite of the low-thermal-conductivity sapphire substrate. This shows that N-polar GaN-on-sapphire technology is an attractive candidate for millimeter-wave power amplifier applications with simultaneous high efficiency and power density.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Sub-50 nm Terahertz In0.8Ga0.2As Quantum-Well High-Electron-Mobility
           Transistors for 6G Applications

    • Free pre-print version: Loading...

      Authors: Wan-Soo Park;Hyeon-Bhin Jo;Hyo-Jin Kim;Su-Min Choi;Ji-Hoon Yoo;Hyeon-Seok Jeong;Sethu George;Ji-Min Baek;In-Geun Lee;Tae-Woo Kim;Sang-Kuk Kim;Jacob Yun;Ted Kim;Takuya Tsutsumi;Hiroki Sugiyama;Hideaki Matsuzaki;Jae-Hak Lee;Dae-Hyun Kim;
      Pages: 2081 - 2089
      Abstract: We present a systematic study on the gate length ( ${L}_{{g}}text {)}$ scaling behavior and the impact of the side-recess spacing ( ${L}_{text {side}}text {)}$ on dc and high-frequency characteristics of In0.8Ga0.2As quantum-well (QW) high-electron-mobility transistors (HEMTs) with ${L}_{{g}}$ from 10 $mu $ m to 20 nm, for the purpose of understanding the scaling limit of maximum oscillation frequency ( ${f}_{text {max}}text {)}$ and thereby demonstrating terahertz devices. The fabricated In0.8Ga0.2As QW HEMTs with ${L}_{{g}} =20$ nm and ${L}_{text {side}} =150$ nm exhibited values of drain-induced-barrier-lowering (DIBL) of 60 mV/V, current-gain cutoff frequency ( ${f}_{{T}}text {)}$ of 0.75 THz, and ${f}_{text {max}}$ of 1.1 THz, while the device with ${L}_{text {side}} =50$ nm showed DIBL of 110 mV/V and ${f}_{{T}}$ / ${f}_{text {max}}$ of 0.72/0.53 THz. It was central to strictly control short-channel effects (SCEs) from the perspective of DIBL to maximize the improvement of ${f}_{text {max}}$ , as ${L}_{{g}}$ was scaled down deeply. In an effort to understand the ${L}_{{g}}$ scaling behavior of ${f}_{text {max}}$ , we carried out the small-signal modeling for both types of devices and found that the increase of the intrinsic output conductance ( ${g}_{text {oi}}text {)}$ played a critical role in determining ${f}_{text {max}}$ in short- ${L}_{{g}}$ HEMTs. On the contrary, the fabricated devices with ${L}_{text {side}} =150$ nm exhibited a tight control of SCEs at ${L}_{{g}}$ of 20 nm. As a result, ${f}_{text {max}}$ in those devices was boosted to 1.1 THz, and more importantly this high ${f}_{text {max}}$ was maintained even as ${L}_{{g}}$ was scaled down to 20 nm. The results in this work represent the best balance of ${f}_{{T}}$ and ${f}_{text {max}}$ in any transistor technology on any material system, displaying both ${f}_{{T}}$ and ${f}_{text {max}}$ in excess of 700 GHz simultaneously.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Ab Initio Computational Screening and Performance Assessment of van der
           Waals and Semimetallic Contacts to Monolayer WSe2 P-Type Field-Effect
           Transistors

    • Free pre-print version: Loading...

      Authors: Ning Yang;Yuxuan Cosmi Lin;Chih-Piao Chuu;M. Saifur Rahman;Tong Wu;Ang-Sheng Chou;Hung-Yu Chen;Wei-Yen Woon;Szuya Sandy Liao;Shengxi Huang;Xiaofeng Qian;Jing Guo;Iuliana Radu;H.-S. Philip Wong;Han Wang;
      Pages: 2090 - 2097
      Abstract: Recent technology development of logic devices based on 2-D semiconductors such as MoS2, WS2, and WSe2 has triggered great excitement, paving the way to practical applications. Making low-resistance p-type contacts to 2-D semiconductors remains a critical challenge. The key to addressing this challenge is to find high-work function metallic materials which also introduce minimal metal-induced gap states (MIGSs) at the metal/semiconductor interface. In this work, we perform a systematic computational screening of novel metallic materials and their heterojunctions with monolayer WSe2 based on ab initio density functional theory and quantum device simulations. Two contact strategies, van der Waals (vdW) metallic contact and bulk semimetallic contact, are identified as promising solutions to achieving Schottky-barrier-free and low-contact-resistance p-type contacts for WSe2 p-type field-effect transistor (pFETs). Good candidates of p-type contact materials are found based on our screening criteria, including 1H-NbS2, 1H-TaS2, and 1T-TiS2 in the vdW metal category, as well as Co3Sn2S2 and TaP in the bulk semimetal category. Simulations of these new p-type contact materials suggest reduced MIGS, less Fermi-level pinning effect, negligible Schottky barrier height and small contact resistance (down to $20~Omega mu text{m}$ ).
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • High-Performance Top-Gated and Double-Gated Oxide–Semiconductor
           Ferroelectric Field-Effect Transistor Enabled by Channel Defect
           Self-Compensation Effect

    • Free pre-print version: Loading...

      Authors: Chun-Kuei Chen;Sonu Hooda;Zihang Fang;Manohar Lal;Zefeng Xu;Jieming Pan;Shih-Hao Tsai;Evgeny Zamburg;Aaron Voon-Yew Thean;
      Pages: 2098 - 2105
      Abstract: In this article, we demonstrate a low-thermal budget defect-engineered process to achieve top-gated (TG) oxide–semiconductor ferroelectric field-effect transistors (FeFETs). The demonstrated TG FeFETs, with the channel length scaled down to 40 nm, exhibit a highly stabilized ferroelectric memory window (MW) of 2 V and a high current ON/ OFF ratio of $10^{{6}}$ . This is achieved by an engineered InGaZnOx (IGZO) and InSnOx (ITO) heterojunction channel that produces the defect self-compensation effect to passivate the intrinsic oxygen-deficient defects, existing in the indium-gallium-zinc-oxide (IGZO) channel interface and bulk. Effective interface/bulk defects passivation with good control of defect-induced channel carrier concentration has been notoriously difficult to achieve. Hence, realizing performant TG oxide-based FeFETs with back-end-of-line (BEOL) thermal budget constraints remains a fundamental challenge. Our study shows that heterojunction channel engineering on FETs and FeFETs can be a reliable solution to overcome this challenge. With such a technique, we can now enable double-gated (DG) ITO–IGZO FeFET and FETs. Such devices can enable BEOL-compatible reconfigurable nonvolatile logic switches that provide extremely low off-state leakage, high switch conductance ratio, and memory read-write disturb-free features.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Proposal of Low-Loss Non-Volatile Mid-Infrared Optical Phase Shifter Based
           on Ge2Sb2Te3S2

    • Free pre-print version: Loading...

      Authors: Yuto Miyatake;Kotaro Makino;Junji Tominaga;Noriyuki Miyata;Takashi Nakano;Makoto Okano;Kasidit Toprasertpong;Shinichi Takagi;Mitsuru Takenaka;
      Pages: 2106 - 2112
      Abstract: An optical phase shifter based on phase-change materials (PCMs) is a promising building block of quantum photonic integrated circuits (QPICs) operating at mid-infrared (MIR) wavelengths on a Si photonics platform. In this article, we propose a record low-loss non-volatile PCM phase shifter operating at MIR wavelengths based on Ge2Sb2Te3S2 (GSTS), which is a new Se-free widegap PCM. On the basis of the refractive index and extinction coefficient spectra measured by spectroscopic ellipsometry, we show that GSTS has excellent material properties for optical phase shifters. By using GSTS in the MIR range, the optical absorption of a PCM phase shifter can be considerably reduced. We achieved an optical loss of 0.29 dB for a $pi $ phase shift, which is the lowest loss ever reported for a PCM phase shifter integrated with a Si waveguide. We also demonstrate the non-volatile resonance wavelength tuning of a microring resonator (MRR) with a GSTS phase shifter and the optically induced phase transition of a GSTS phase shifter based on laser irradiation.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Self-Organized Germanium Quantum Dots/Si3N4 Enabling Monolithic
           Integration of Top Si3N4-Waveguided Microdisk Light Emitters and p-i-n
           Photodetectors for On-Chip Sensing

    • Free pre-print version: Loading...

      Authors: Chih-Hsuan Lin;Po-Yu Hong;Bing-Ju Lee;Horng-Chih Lin;Thomas George;Pei-Wen Li;
      Pages: 2113 - 2120
      Abstract: Using a coordinated combination of lithographic patterning and self-assembled growth, Ge spherical quantum dots (QDs) were controllably generated within host layers of Si3N4 as active medium for Si photonics. A significant fabrication advantage of our approach is the high-temperature thermal stability of Ge QDs that are formed by thermal oxidation of poly-SiGe lithographically patterned structures at 800 °C–900 °C, offering flexibility in the waveguide (WG)-material choices, co- design, and integration of Ge photonic devices. Our Ge QDs enable monolithic integration of microdisk light emitters and p-i-n photodetectors (PDs) with top-Si3N4 WG-coupled structures using standard Si processing. Low dark current of 0.3 mA/cm2 at 300 K and $0.2,mu text{A}$ /cm2 at 77 K in combination with 3-dB frequency of 12 GHz for Ge-QD PDs and low threshold power of 0.6 kW/cm2 for optically pumped Ge QD/SiN microdisks light emission evidence the high degree of crystallinity of our Ge QDs being an effective building block for 3-D SiN photonic integrated circuits.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Highly Scaled GaN Complementary Technology on a Silicon Substrate

    • Free pre-print version: Loading...

      Authors: Qingyun Xie;Mengyang Yuan;John Niroula;Bejoy Sikder;James A. Greer;Nitul S. Rajput;Nadim Chowdhury;Tomás Palacios;
      Pages: 2121 - 2128
      Abstract: This article reports on the scaling of GaN complementary technology (CT) on a silicon substrate to push its performance limits for circuit-level applications. The highly scaled self-aligned (SA) p-channel FinFET (a fin width of 20 nm) achieved an ${I}_{D,text {max}}$ of −300 mA/mm and an ${R}_{ mathrm{ ON}}$ of $27 Omega cdot $ mm, a record for metal organic chemical vapor deposition (MOCVD)-grown III-nitride p-FETs. A systematic study on impact of fin width scaling and recess depth in these transistors was conducted. A new SA scaled n-channel p-GaN-gate FET (n-FET) process, compatible with the p-FinFET, demonstrated enhancement-mode (E-mode) n-FETs ( ${L}_{G} = {200}$ nm, ${I}_{D,text {max}} = {525}$ mA/mm, and ${R}_{ mathrm{ ON}}={2}.{9},,Omega cdot $ mm) on the same epitaxial platform. The p-FETs and n-FETs feature competitive performance in their respective categories and, when taken together, offer a leading solution for GaN CT on a silicon substrate.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Improved Vertical β-Ga2O3 Schottky Barrier Diodes With
           Conductivity-Modulated p-NiO Junction Termination Extension

    • Free pre-print version: Loading...

      Authors: Weibing Hao;Feihong Wu;Wenshen Li;Guangwei Xu;Xuan Xie;Kai Zhou;Wei Guo;Xuanze Zhou;Qiming He;Xiaolong Zhao;Shu Yang;Shibing Long;
      Pages: 2129 - 2134
      Abstract: In this work, we demonstrate a novel conductivity-controlled junction termination extension (JTE) technique using p-type NiO—a key element for the potential commercialization of Ga2O3 power devices. The surface electric field at the Schottky edge is effectively suppressed by the p-type NiO JTE. Simultaneously, it can control the concentration of p-type NiO to maximize the breakdown voltage ( ${V}_{text {br}}$ ) by changing the gas atmosphere during magnetron sputtering growth. The electrical characteristics of the $beta $ -Ga2O3 Schottky barrier diodes (SBDs) with p-type NiO JTE are studied systematically. All $beta $ -Ga2O3 SBDs with JTE show great advantages in terms of device performance parameters whether at room temperature or high temperature, which indicates the effectiveness of p-NiO JTE in reducing the fringe electric field. In particular, the $beta $ -Ga2O3 SBDs with an optimized hole concentration of approximately $10^{{17}}$ cm $^{-{3}}$ for NiO in the JTE region exhibit a low specific ON-resistance of 2.9 $text{m}Omega $ cm2 and a high ${V}_{text {br}}$ of 2.11 kV, yielding a high power figure-of-merit (PFOM) of 1.54 GW/cm2. Our results demonstrate the great potential of p-NiO as a controllable and reliable technique for junction engineering in $beta $ -Ga2O3 power devices.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures

    • Free pre-print version: Loading...

      Authors: Ruben Asanovski;Alexander Grill;Jacopo Franco;Pierpaolo Palestri;Arnout Beckers;Ben Kaczer;Luca Selmi;
      Pages: 2135 - 2141
      Abstract: Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( ${T}$ ), referred to as “excess 1/f noise,” observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Fatigue Mechanism of Antiferroelectric Hf0.1Zr0.9O2 Toward Endurance
           Immunity by Opposite Polarity Cycling Recovery (OPCR) for eDRAM

    • Free pre-print version: Loading...

      Authors: K.-Y. Hsiang;J.-Y. Lee;Z.-F. Lou;F.-S. Chang;Y.-C. Chen;Z.-X. Li;M. H. Liao;C. W. Liu;T.-H. Hou;P. Su;M. H. Lee;
      Pages: 2142 - 2146
      Abstract: Opposite polarity cycling recovery (OPCR) is proposed to completely restore a fatigued antiferroelectric (AFE) capacitor back to its initial state, thereby extending the endurance number of switching cycles for AFE-RAM. A comprehensive model exclusive to AFE with unipolar cycling is revealed to achieve unlimited endurance, and the unipolar cycling with OPCR is experimentally demonstrated to accumulate $10^{{12}}$ cycles, while achieving the nondegradation and complete restoration of the remnant polarization ( ${P}_{r}$ ). Furthermore, the proposed OPCR achieves a recovery time ratio of 0% ( ${t}_{text {recovery}}/{t}_{text {period}}$ ), which indicates no extra time to spend for the recovery procedure.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Reconfigurable Pb-Free Perovskite Array for X-Ray In-Sensor Computing

    • Free pre-print version: Loading...

      Authors: Guan-Hua Dun;Ken Qin;Hai-Nan Zhang;Qi-Xin Feng;Ze-Shu Wang;Xiang-Shun Geng;Yuan-Yuan Li;Peng Wan;Yi-Chu He;Jian-Guo Hu;Jia-Li Peng;Ren-Rong Liang;Dan Xie;He Tian;Yi Yang;Tian-Ling Ren;
      Pages: 2147 - 2152
      Abstract: Conventional X-ray imaging architectures feature data redundancy and hardware consumption due to the separated sensory terminal and computing units. In-sensor computing architectures are promising to overcome such drawbacks. However, its realization in the X-ray range remains elusive. We propose an ion distribution-induced reconfigurable mechanism and demonstrate the X-ray band in-sensor computing array based on Pb-free perovskite. Redistribution of Br− ion in perovskite induces the switching of positive and negative (PN) and NP modes under electrical pooling. X-ray detection sensitivity can be switched between two stable self-power sensing modes with 4373 ± 298 and $-7804,,pm ,,429,,mu text{C}$ ${mathrm {Gy}}_{{text {air}}}^{-{1}}$ cm−2, respectively, which are superior to that of commercial a-Se detectors ( $20 ~mu text{C}$ ${mathrm {Gy}}_{{text {air}}}^{-1}$ cm−2). Both modes exhibit a low detection limit of 48.4 ${mathrm {nGy}}_{{text {air}}},,text{s}^{-{1}}$ , which is two orders lower than the typical medical dose rate of $5.5 ~mu {mathrm {Gy}}_{{text {air}}},,text{s}^{-{1}}$ . The perovskite array sensors can integrate with thin-film transistors (TFTs) with low-temperature (80 °C) process, in which the photocurrent distribution under irradiation shows good uniformity. An in-sensor computing algorithm of attention mechanism is performed on array sensors for chest X-ray images disease recognition, which enables an -ccuracy improvement of up to 98.2%. Our results can pave the way for future intelligent X-ray imaging.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Nearly Ideal Breakdown Voltage Observed in Lateral p-i-n Diodes Fabricated
           on a SiC High-Purity Semi-Insulating Substrate

    • Free pre-print version: Loading...

      Authors: M. Kaneko;A. Tsibizov;T. Kimoto;U. Grossner;
      Pages: 2153 - 2156
      Abstract: Lateral p-i-n diodes with small i-region width (less than $5 ~mu text{m}$ ) were fabricated by direct ion implantation into a high-purity semi-insulating silicon carbide (SiC) substrate. The breakdown voltage of the diodes increased with increasing the i-region width and a lateral effective breakdown electric field of 1.7–1.9 MV/cm was obtained. The experimental breakdown voltage well agreed with the technology computer-aided design (TCAD) simulation, indicating that deep levels contributing the semi-insulating property do not seriously deteriorate the breakdown voltage in case of the small i-region width.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Neural Network-Based BSIM Transistor Model Framework: Currents, Charges,
           Variability, and Circuit Simulation

    • Free pre-print version: Loading...

      Authors: Chien-Ting Tung;Chenming Hu;
      Pages: 2157 - 2160
      Abstract: We present a neural network (NN)-based transistor modeling framework, which includes drain, source, and gate currents and charges and their variabilities. The training data are generated by a Berkeley short-channel IGFET model (BSIM) with ranges of channel lengths, widths, and oxide thicknesses. The NNs are trained to learn the geometry dependence. The drain, source, and gate currents are modeled with one NN and the charges by another NN. The NNs are trained to produce accurate variability prediction and derivatives of currents and charges. Quality and robustness tests, such as Gummel symmetry, harmonic balance, and ring oscillator, are performed and show excellent results.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Concept of Gyrotron Complexes With Serial Phase and Frequency Locking

    • Free pre-print version: Loading...

      Authors: R. M. Rozental;I. V. Zotova;A. S. Sergeev;N. S. Ginzburg;G. G. Denisov;
      Pages: 2161 - 2164
      Abstract: For the development of complexes of coherently operating gyrotrons, we propose a scheme with serial connection when the generation frequency and phase of each gyrotron are locked by a previous one. In contrast with a more basic parallel connection, such a scheme does not imply the use of a master-oscillator by dividing its power into many channels, that is, the number of connected gyrotrons is not limited. Besides, a significant part of the power of each generator can be used to synchronize the next element in the series; thus, the locking bandwidth is expanded. In accordance with the numerical simulations, the drop in efficiency when a strong external signal is applied can be negated by varying the value of the guiding magnetic field.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Research on a Highly Overmoded Slow Wave Circuit for 0.3-THz Extended
           Interaction Oscillator

    • Free pre-print version: Loading...

      Authors: Yifan Zu;Ying Lan;Xuesong Yuan;Xiaotao Xu;Qingyun Chen;Hailong Li;Matthew T. Cole;Yong Yin;Bin Wang;Lin Meng;Yang Yan;
      Pages: 2165 - 2169
      Abstract: Here, we present the complete design process of a highly overmoded slow wave circuit (SWC) stably operating in the quasi-TM04 mode for terahertz (THz) extended interaction oscillator (EIO). The developed interaction circuit emits THz frequency electromagnetic radiation through structural size of the engineered millimeter-wave (MMW) circuits, which provides a new technological horizon for overcoming the engineering challenges caused by the limitation of circuit size. Through careful engineering of the electron optical system, a cylindrical beam with a diameter of 0.38 mm and a current of 0.25 A is obtained at a bias of 14.8 kV. Through the particle-in-cell (PIC) simulation, these new design approaches have been shown to achieve an output power of 250 W at 0.3 THz in a cylindrical cavity with an inner diameter of 4.16 mm.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Solution-Processed InGaZnO-Based Artificial Neuron for Neuromorphic System

    • Free pre-print version: Loading...

      Authors: Yafang Zeng;Xianghong Zhang;Yanxue Hao;Yi Zou;Bangyan Zeng;Qian Yang;Tailiang Guo;Huipeng Chen;Wei Chen;
      Pages: 2170 - 2174
      Abstract: Artificial neurons have good application prospects as efficient processing units in artificial neural morphology. Indiun galliun zinc oxide (IGZO) is widely used in artificial synapses and artificial neurons due to its high reliability. In this study, we propose a neural device based on IGZO memristors fabricated by the solution method, owing to its simple process steps, no vacuum treatment process, rapid film formation, easy doping, and more suitability for low-temperature film deposition on a flexible substrate, as well as compatibility with a thin-film transistor (TFT). The influence of In, Ga, and Zn component ratios on neuron performance is investigated. Indium contributes greatly to the conductivity of the device, gallium inhibits the formation of oxygen vacancies, and zinc has a large impact on the morphology of the film, all of which impact neuron properties. Finally, we successfully simulate the integrate and fire (IF) characteristics of neurons through suitable component ratios and explore the difference in the electrical properties of the devices under different annealing atmospheres. The solution-processed IGZO-based neurons show great potential for neuromorphic systems.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Toward Understanding Thickness Dependence on Dielectric Breakdown
           Mechanism Under Forward Gate Bias in 4H-SiC MOS Technologies

    • Free pre-print version: Loading...

      Authors: Jia-Wei Hu;Po-Chien Huang;Pin-Wei Huang;Jheng-Yi Jiang;Chih-Fang Huang;Tian-Li Wu;
      Pages: 2175 - 2178
      Abstract: In this brief, the oxide characteristics and breakdown mechanism under forward gate bias in 4H-SiC MOS technologies are investigated. We found that the ${I}_{text {G}}$ – ${V}_{text {G}}$ curves consist of two regions divided by a turning point. The region in the lower oxide fields is dominated by Pool–Frenkel (P–F) or Fowler–Nordheim (F–N) tunneling and the other in the higher oxide fields by impact ionization. MOS capacitors with three different oxide thicknesses (27.8, 44.4, and 69.0 nm) are fabricated and evaluated under different temperatures. Constant voltage stress was then conducted at $200~^{circ }text{C}$ to evaluate oxide integrity under the electric field where F–N tunneling dominates. Weibull plot and 63% failure times versus oxide field are shown for three oxide thicknesses. With the measure-stress-measure method, flat band voltage shift versus accumulative stress time and ${D}_{text {it}}$ distribution are presented to understand the type of charge trapping. It was found that 27.8 nm oxide shows the highest electric field for a ten-year lifetime.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Lengthy Testing of a K-Band Multifrequency Gyro-TWT With Double-Disk
           External Reflector

    • Free pre-print version: Loading...

      Authors: R. M. Rozental;S. V. Samsonov;A. A. Bogdashov;I. G. Gachev;
      Pages: 2179 - 2182
      Abstract: We present the results of experimental investigations of multifrequency oscillations in a ${K}$ -band gyrotron traveling-wave tube (gyro-TWT) with double-disk external reflector. The system operation in multifrequency regime was tested for a prolonged period of time with temperature monitoring by an infrared camera. Based on the measurement results, the possibility of stable generation for a period of several tens of minutes at the output power level of more than 2 kW is demonstrated.
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Role of Solar Cells in Global Energy Transformation

    • Free pre-print version: Loading...

      Pages: 2183 - 2184
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Semiconductor Device Modeling for Circuit and System Design

    • Free pre-print version: Loading...

      Pages: 2185 - 2186
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
  • Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power
           Applications

    • Free pre-print version: Loading...

      Pages: 2187 - 2188
      PubDate: April 2023
      Issue No: Vol. 70, No. 4 (2023)
       
 
JournalTOCs
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Email: journaltocs@hw.ac.uk
Tel: +00 44 (0)131 4513762
 


Your IP address: 44.201.94.236
 
Home (Search)
API
About JournalTOCs
News (blog, publications)
JournalTOCs on Twitter   JournalTOCs on Facebook

JournalTOCs © 2009-