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IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 18  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [228 journals]
  • IEEE ELECTRON DEVICES SOCIETY

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • IEEE Transactions on Electron Devices information for authors

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      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
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      Abstract: This page or pages intentionally left blank.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Novel Trench Inner-Spacer Scheme to Eliminate Parasitic Bottom Transistors
           in Silicon Nanosheet FETs

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      Authors: Jinsu Jeong;Jun-Sik Yoon;Sanguk Lee;Rock-Hyun Baek;
      Pages: 396 - 401
      Abstract: A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) is proposed based on fully calibrated Technology Computer-Aided Design (TCAD) simulation. Highly doped punch-through stopper (PTS) layers are generally used to suppress trpbt. Unfortunately, trpbt is still a fatal failure factor in electrical performance degradation when the source/drain (S/D) recess is overetched. Moreover, the proposed TIS scheme prevents the diffusion of S/D dopants toward the PTS region beneath the bottom gate, thereby inhibiting the formation of trpbt. Furthermore, the TIS-NSFETs exhibit excellent immunity to overetched S/D recess depth variations. Additionally, the thermal characteristics of the TIS scheme are compared to that of the bottom oxide (BOX) scheme forming dielectrics beneath the S/D epitaxies, one of the methods used to suppress trpbt. Lattice temperature caused by self-heating and thermal resistance in the TIS-NSFETs are much lower than that in the BOX-NSFETs for both n/p-type devices. The thermal advantage of TIS-NSFETs compared to BOX-NSFETs is confirmed in both DC and AC conditions, similar to an actual operating environment. Therefore, the proposed TIS scheme is highly recommended to eliminate the undesired trpbt without critical DC/AC degradation and to resolve poor heat dissipation problems in the BOX scheme simultaneously.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Origin of Soft Breakdown in Thin-Barrier AlGaN/GaN SBD With C-Doped GaN
           Buffer

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      Authors: Hao Wu;Xuanwu Kang;Yingkui Zheng;Ke Wei;Rikang Zhao;Yafei Yuan;Xinyu Liu;Guoqi Zhang;
      Pages: 402 - 408
      Abstract: In this work, we investigate the soft breakdown (BD) behavior in thin-barrier (TB) AlGaN/GaN Schottky barrier diode (SBD) with carbon-doped GaN buffer. The soft BD behavior is the result of the coupling of multiple mechanisms. In the off-state, the ionized carbon (C) acceptors make the electric field ( ${E}$ -field) crowd at the cathode and cause the impact ionization. Then, the holes generated by impact ionization compensate with the ionized C acceptors, thus suppressing ${E}$ -field crowding and preventing the further avalanche BD. The residual holes flow to and accumulate under the anode, which leads to a continuous increase in the Schottky ${E}$ -field and Schottky leakage, eventually causing the soft BD. Due to the tunneling effect, Schottky leakage is highly sensitive to the Schottky ${E}$ -field in TB structure, so the leakage rise rate during soft BD is abnormally high.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Bias Dependence of Non-Fourier Heat Spreading in GaN HEMTs

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      Authors: Yang Shen;Xue-Song Chen;Yu-Chao Hua;Han-Ling Li;Lan Wei;Bing-Yang Cao;
      Pages: 409 - 417
      Abstract: In this article, self-heating in gallium nitride (GaN) high-electron-mobility transistors (HEMTs) is studied by combining the technology computer-aided design (TCAD) and phonon Monte Carlo (MC) simulations. The simulation results indicate that the bias-dependent heat generation in the channel can have a remarkable impact on the thermal spreading process and the phonon ballistic effects simultaneously. Based on the two-heat-source model, we propose a two-thermal-conductivity model to predict the device junction temperature with the consideration of bias-dependent phonon transport in the HEMT. The proposed model is easy to be coupled with the finite-element method (FEM)-based thermal analysis without the need for time-consuming multiscale electrothermal simulations.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Analytical Electro-Thermal Model for Multianode Schottky Diodes With
           Improved Temperature-Dependent Parameters Extraction Method

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      Authors: Yaoling Tian;Yue He;Kun Huang;Changxing Lin;Jun Jiang;
      Pages: 418 - 423
      Abstract: An analytical electro-thermal model for multianode Schottky diodes is proposed in this work. By characterizing the self-heating effects, the temperature-dependent parameters including series resistance, ideality factor, and saturation current could be accurately extracted. By means of self-consistent mapping between thermal and electrical domain, the proposed model could eliminate the errors in conventional method, which makes the assumption that each anode operates at the same temperature even at high-junction current levels. This approach is capable of determining highly accurate real-time parameters for diode under different dissipated powers, which is critical for circuit reliability analysis and high-power multiplier design. The proposed electro-thermal model has been applied to analyze a novel four-port balanced tripler, operating up to 220 GHz, with the comparison to two conventional models. With an input power of 350 mW, the circuit efficiency simulated based on this extraction method only features a difference of ~1.1% at 219-GHz measured results.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Novel In-Situ AlN/p-GaN Gate HEMTs With Threshold Voltage of 3.9 V and
           Maximum Applicable Gate Voltage of 12.1 V

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      Authors: Yinhe Wu;Shuang Liu;Jincheng Zhang;Shenglei Zhao;Xiangdong Li;Kai Zhang;Yue Ai;Weihang Zhang;Tangsheng Chen;Yue Hao;
      Pages: 424 - 428
      Abstract: In this article, we demonstrate a novel E-mode HEMT featuring in situ AlN dielectric layer on p-GaN cap layer. Compared with conventional p-GaN gate HEMT, the threshold voltage of in situ AlN/p-GaN gate HEMT shifts from 1.8 to 3.9 V, and the forward gate breakdown voltage is increased from 10.0 to 17.6 V. By considering 10 years’ lifetime at 63% failure level, the maximum applicable gate voltage for AlN/p-GaN gate HEMT reaches a remarkable high value of 12.1 V (E-model), which is much higher than that of 6.1 V for conventional HEMT. In addition, the novel E-mode HEMT exhibits a high ON/OFF ratio of $10^{{9}}$ . Experiments demonstrate that E-mode in situ AlN/p-GaN gate HEMT has great potential in power electronics applications.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Simulation of AlGaN/GaN MISFET With 3.6-GW/cm2 High FOM by SIPOS Field
           Plates Electric Field Modulation

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      Authors: Baoxing Duan;Junchao Ma;Luoyun Yang;Yulong Wang;Yintang Yang;
      Pages: 429 - 434
      Abstract: In this article, a novel vertical trench gate AlGaN/GaN metal–insulator–semiconductor field-effect transistor (MISFET) with semi-insulating polycrystalline silicon (SIPOS) field plates [SIPOS vertical trench gate AlGaN/GaN (VT-AlGaN/GaN) MISFET] is proposed for the first time. In the OFF-state, the electric field distribution in the n-GaN buffer is more uniform due to the presence of SIPOS field plates and deep trench structure, and the breakdown voltage (BV) is increased. Simulation results using Technology Computer-Aided Design (TCAD) Sentaurus show that under the same n-GaN buffer layer thickness ( $7~mu text{m}$ ), the BVs of SIPOS VT-AlGaN/GaN MISFET and conventional vertical trench gate AlGaN/GaN MOSFET (conv.VT-AlGaN/GaN MOSFET) are 1828 and 1506 V, which increased 17.6%. In the ON-state, a majority carrier accumulation layer is formed on the surface between the n-GaN buffer and the thin Al2O3 layer. This high concentration electron region is equivalent to local high concentration doping region, and the specific ON-resistance ( ${R}_{ rm{ON,sp}}$ ) of the device is greatly reduced. When the BV remains almost the same (1500 V), ${R}_{ rm{ON,sp}}$ of SIPOS VT-AlGaN/GaN MISFET and conv.VT-AlGaN/GaN MOSFET is 0.63 and 1.03 $text{m}Omega cdot text {cm}^{{2}}$ , respectively. ${R}_{ rm{ON,sp}}$ decreased by 38.8%. The maximum figures of merit (FOMs) of the SIPOS-vertical AlGaN/GaN MISFET and conv.VT-AlGaN/ GaN MOSFET are 3.6 and 2.4 GW/cm2, respectively. The proposed SIPOS VT-AlGaN/GaN MISFET achieves a better compromise betwee- BV and ${R}_{ rm{ON,sp}}$ .
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Experimentally Validated Gate-Lag Simulations of AlGaN/GaN HEMTs Using
           Fermi Kinetics Transport

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      Authors: Nicholas C. Miller;Matt Grupen;Ahmad E. Islam;John D. Albrecht;Dave Frey;Richard Young;Miles Lindquist;Andrew J. Green;Dennis E. Walker;Kelson D. Chabak;
      Pages: 435 - 442
      Abstract: This article presents for the first time a direct connection between gate lag observed in drain current transient measurements of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) and traps located in the barrier of the transistor epitaxy. Semiclassical numerical simulations are presented using the Air Force Research Laboratory’s (AFRL’s) Fermi kinetics transport (FKT) solver and are validated with drain current transient measurements. Capacitance–voltage ( ${C} - {V}$ ) and conductance–voltage ( ${G} - {V}$ ) measurements are also presented to provide further insights into the trap location used in the FKT simulations. These simulations indicate that equivalent defects located specifically at the AlGaN barrier/GaN cap interface of an AFRL GaN HEMT with a density of $7.5times 10^{{12}}$ cm−2 and positioned 1.464 eV below the GaN cap conduction band edge were the salient traps linked to the gate-lag phenomenon. The study highlights the importance of experimentally benchmarked device simulation for trapping analysis in GaN HEMTs and may provide significant insights into device engineers for mitigating trapping effects in state-of-the-art GaN technologies.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Radio Frequency Characteristics of InGaAs FE-FETs With Scaled Channel
           Length

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      Authors: P. Huang;M. Y. Chen;Q. H. Luc;J. Y. Wu;N. A. Tran;E. Y. Chang;
      Pages: 443 - 448
      Abstract: RF performance comparison between InGaAs MOSFETs and ferroelectric field-effect transistors (FE-FETs) as a function of channel length ( ${L}_{{text {ch}}}$ ) is investigated using a technology computer-aided design (TCAD) simulator. The RF characteristics and energy efficiencies of FE-FETs are shown to have performance parity or even inferiority as compared with the conventional MOSFETs at relatively long ${L}_{{text {ch}}}$ . However, as ${L}_{{text {ch}}}$ scaled down, FE-FETs with substantial performance enhancement are observed. The highest improvement in unit gain cutoff frequency ( ${f}_{T}$ ) and maximum oscillation frequency ( ${f}_{{text {MAX}}}$ ) is 15.4% ( ${L}_{{text {ch}}} = {75} ,,text {nm}$ ) and 22.5% ( ${L}_{{text {ch}}} =85$ nm), respectively. In addition, for FE-FETs, device energy efficiencies are shown to achieve much higher improvement of 53.4% and 69.3% in transconductance generation factor (TGF) and transconductance frequency product (TFP), respectively, at an optimized ${L}_{{text {ch}}}$ of 15 nm. The superior RF properties obtained in FE-FETs can be attributed to the higher effective electron velocity ( ${V}_{{text {eff}}}$ ), better gate controllability, and reduced gate resistance (
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Using Gate Leakage Conduction to Understand Positive Gate Bias Induced
           Threshold Voltage Shift in p-GaN Gate HEMTs

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      Authors: Shun-Wei Tang;Benoit Bakeroot;Zhen-Hong Huang;Szu-Chia Chen;Wei-Syuan Lin;Ting-Chun Lo;Matteo Borga;Dirk Wellekens;Niels Posthuma;Stefaan Decoutere;Tian-Li Wu;
      Pages: 449 - 453
      Abstract: In this work, the gate current characteristics are investigated to explain the threshold voltage shift in AlGaN/GaN high electron mobility transistors (HEMTs) with a p-GaN gate. First, the intrinsic gate current conduction mechanisms are identified: in the low bias range (2.5 V $ < {V}_{G} < $ 4 V), thermionic emission (TE) dominates in the AlGaN/GaN region, whereas in a higher bias range (4 V $ < {V}_{G} < $ 7 V) trap-assisted tunneling (TAT) is occurring in the Schottky/p-GaN region. Secondly, the threshold voltage shift of the stress phase is evaluated by applying a positive gate bias for various stress times. A consistent trap level with an activation energy of ${E}_{A}sim $ 0.6 eV is found. In conclusion, a physical model explaining the negative ${V}_{text {TH}}$ shift by considering TAT via hole transport is proposed.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Normally-Off β-(AlxGa1-x)2O3/Ga2O3 Modulation-Doped Field-Effect
           Transistors With p-GaN Gate: Proposal and Investigation

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      Authors: Ashvinee Deo Meshram;Anumita Sengupta;Tarun K. Bhattacharyya;Gourab Dutta;
      Pages: 454 - 460
      Abstract: A novel $beta $ -(AlxGa1-x)2O3/gallium oxide (Ga2O3) modulation-doped field-effect transistor (MODFET) with p-GaN gate is proposed and investigated for the first time. TCAD device simulator calibrated with experimental results is used to develop the physical insight of device operation and to evaluate the proposed device’s performance. Besides normally- OFF operation, the proposed MODFET also shows a higher driving capability and lower ON-resistance compared to conventional Ga2O3-MODFETs of similar device dimensions. The effect of individual device parameters on the electrical characteristics of the proposed device is also investigated in detail. Besides, an analytical model is formulated to estimate the threshold voltage of these normally- OFF devices. This model is rigorously validated with numerical results for a wide range of device parameters.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • A Novel Array Programming Scheme for Large Matrix Processing in
           Flash-Based Computing-in-Memory (CIM) With Ultrahigh Bit Density

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      Authors: Yang Feng;Dong Zhang;Guoqing Zhao;Zhaohui Sun;Maoying Bai;Yueran Qi;Xiao Gong;Jing Liu;Junyu Zhang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen;
      Pages: 461 - 467
      Abstract: Computing-in-memory (CIM) architecture is a promising approach to breaking the bottleneck in von Neumann’ architecture. To shed light on large matrix operations in flash-based CIM with ultrahigh bit density (4–5 bit/cell), this work presents a novel incremental positive–negative step pulse programming (IPNPP) array programming scheme. The proposed scheme utilizes positive pulses for rough tuning and subsequent negative pulses for fine-tuning to cells’ threshold voltages. By adopting the IPNPP scheme in 55-nm NOR flash CIM arrays, it is shown that the latency and power consumption could be lowered effectively. As for image dehazing of ultrahigh-resolution images, ~180.6-TOPS/W high energy efficiency with great accuracy and variation tolerability has been demonstrated successfully. Our results indicate that the IPNPP is effective for CIMs that require high precision and low power consumption.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Multilevel Non-Volatile Memristive Response in e-Textile

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      Authors: Suraj P. Khanna;Satish Singh;C. K. Suman;Nandan Kumar;Alok Dabi;
      Pages: 468 - 472
      Abstract: Multilevel non-volatile (NV) resistive switching response is reported in electronic textile. The electroconductive textile as a phase change material displayed a typical write-once-read-many (WORM) memory behavior and switched abruptly from OFF to ON under the voltage-sweep mode. Furthermore, current-sweep characterization revealed a large number of intermittent multilevel NV states. A mapping of the single active and multiple passive devices across the 2-D planar structure of the textile allowed to achieve conduction modulation using a remote current-bias write/input stimulus. A comparative study of the wale and course directions in the textile displayed an anisotropic current spreading that may be utilized for selective memory writing/emulating neuron-like behavior. In addition, the textile also displayed the reset WORM or ReWORM effect, enabling it to revert to its initial high resistive state.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Y2O3-Based Crossbar Array for Analog and
           Neuromorphic Computation

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      Authors: Sanjay Kumar;Dhananjay D. Kumbhar;Jun H. Park;Rajanish K. Kamat;Tukaram D. Dongale;Shaibal Mukherjee;
      Pages: 473 - 477
      Abstract: Here, we report an implementation of ( $8times8$ ) $text{Y}_{{2}}text{O}_{{3}}$ -based memristive crossbar array (MCA) out of a total dimension of ( $30times25$ ) array fabricated by utilizing a dual ion beam sputtering (DIBS) system. The selected ( $8times8$ ) MCA is further used to electrically write random alphabets and perform synaptic learning characteristics to perform analog and neuromorphic computing applications. The MCA effectively exhibits multiple current levels and mimics various artificial synaptic properties with superior bidirectional switching responses. The MCA mimics potentiation, depression, and different Hebbian learning-based spike-time-dependent plasticity rules, suggesting the importance of the $text{Y}_{{2}}text{O}_{{3}}$ -based MCA for large-scale neuromorphic and analog computations. This work provides different insights into the design of an artificial synapse by utilizing $text{Y}_{{2}}text{O}_{{3}}$ as a switching oxide in memristors.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Low-Energy Shared-Current Write Schemes for Voltage-Controlled
           Spin-Orbit-Torque Memory

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      Authors: Albert Lee;Irina Alam;Jiyue Yang;Di Wu;Sudhakar Pamarti;Puneet Gupta;Kang L. Wang;
      Pages: 478 - 484
      Abstract: Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individually yet programmed via a shared current. In this work, we propose two implementations of shared-current write: the horizontal shared current write (HSCW), which reduces the average SOT current per bit by the number of bits on the SOT bus, and the vertical shared current write (VSCW), which can further leverage data dependency for increased performance. We simulate the efficiency of the HSCW and VSCW using a Landau–Lifshitz–Gilbert (LLG)-based VC-SOT model and a 28-nm CMOS technology and show that HSCW and VSCW can achieve an energy saving of 74% and 40%–87%, respectively, in a 32-bit setting. Analysis of data patterns in common workloads finds that 40% of data share more than 85% common bits, for which VSCW can leverage for further improved performance.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • 3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of
           Integration Parameters on Inference Accuracy

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      Authors: Ankit Kaul;Yandong Luo;Xiaochen Peng;Madison Manley;Yuan-Chun Luo;Shimeng Yu;Muhannad S. Bakir;
      Pages: 485 - 492
      Abstract: Three-dimensional heterogeneous integration (3-D-HI) has been proposed as a potential method to stack a large amount of embedded memory required in state-of-the-art compute-in-memory (CIM) artificial intelligence (AI) accelerators. While embedded nonvolatile memory, such as resistive RAM (RRAM), is a promising alternative to static random access memory (SRAM)/dynamic random access memory (DRAM) as a CIM synaptic device owing to high density, low leakage, and nondestructive read, thermal-induced device conductance drift remains a challenge. High-temperature-driven lower retention can be more significant in dense memory-logic 3-D integration due to increased volumetric power, which has not been studied in prior work. The scope of this work is to quantify the thermal impact of different 3-D-HI architectures on the reliability of 3-D-integrated binary RRAM devices for CIM applications. A device-integration-application reliability evaluation methodology is proposed, using which 3-D integration architectures and logic-memory partitioning configurations are benchmarked. Due to higher junction temperatures for memory tier in both five-tier monolithic 3-D (M3D) and five-tier through silicon via (TSV)-based 3-D compared to the 2-D baseline, the drop in inference accuracy at ten years is $approx 80$ %. For our assumed device, integration, and application parameters, a three-tier configuration provides a balanced design option between thermal and application performance. The integrated benchmark framework is released on GitHub (https://github.com/i3dsystems/3D_CIM_thermal_v1.0) as an open-source tool for the research community.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Nonideality Suppression and 16-State Multilevel Cell Storage Optimization
           in Phase Change Memory With Linear-Like Circuit

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      Authors: Cheng Chen;Chenchen Xie;Houpeng Chen;Siqiu Xu;Xi Li;Zhenchao Sui;Zhitang Song;
      Pages: 493 - 498
      Abstract: Phase change memory (PCM) provides unique advantages in embedded, mass storage, and in-memory computing. Resistance drift and noise are decreasing the resistance ratio of PCM cell in amorphous and crystalline state, thereby reducing the readout window and data reliability, especially making obstacles to multilevel storage and neural network computing applications. A novel linear-like circuit is proposed to reduce drift coefficient and noise significantly and enhance the adjacent conductance ratio of the 16-level multilevel storage technology. Test results show that the drift coefficient reduced by 78%, and the noise reduced by three orders of magnitude. By constructing a PCM-based spiking recurrent neural network (SRNN) neural network in PyTorch, we achieved 97.4% accuracy, demonstrating that linear-like circuit could suppress drift and noise and improve the multilevel storage performance, which reduces the training loss despite PCM nonidealities.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Methods to Realize Low-BER and High-Reliability RRAM Chip With Fast
           Page-Forming Capability

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      Authors: Xueqi Li;Liyang Pan;Junyi Wang;Bin Gao;Jianshi Tang;He Qian;Huaqiang Wu;
      Pages: 499 - 505
      Abstract: Resistive random access memory (RRAM) exhibits advantages, such as high speed, simple structure, and good compatibility with CMOS technology. However, an additional forming step is usually inevitable, which requires cell-by-cell verification and can be very time-consuming. This article proposes a novel dual-step page-forming method that can realize low-current forming and improve a bit error rate (BER). Based on this technique and corresponding circuit, a no-verify page-forming scheme is proposed and can achieve a fast-forming speed of 7.56 Mb/s. Moreover, the impact of parameters, such as forming voltage and forming time in the forming process on the BER, is discussed. In addition, to achieve lower BER and better reliability, a two-transistor-two-resistor (2T2R) cell structure is adopted, and both digital verify (DV) and analog verify (AV) methods are proposed. The proposed page-forming and two verify methods are experimentally validated on a 1-MB RRAM chip. An ultralow BER of 10−5/10−6 (DV/AV) without any error correction is achieved. Excellent endurance (>107 cycles for both AV and DV) and retention (>10 years at 25 °C for AV) are also demonstrated on the chip level. Overall, this work demonstrates a useful strategy to design high-reliability RRAM chip with excellent memory performance.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable
           Memory

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      Authors: Siri Narla;Piyush Kumar;Ann Franchesca Laguna;Dayane Reis;X. Sharon Hu;Michael Niemier;Azad Naeemi;
      Pages: 506 - 513
      Abstract: This article presents the design of a novel and compact spin-orbit torque (SOT)-based ternary content addressable memory (TCAM). Experimentally validated/calibrated micromagnetic and macrospin simulations have been used to quantify various tradeoffs regarding the write operation, such as write energy, error rate, and retention time. SPICE simulations incorporating various sources of variability are used to evaluate search operations, optimize the proposed novel TCAM cell based on SOT magnetic random access memory (SOT-MRAM), and benchmark it against static random access memory (SRAM)- and FeFET-based TCAMs. We show low search error rates (SERs) (< 10−4) while considering various sources of variability for four transistors- and two magnetic tunnel junctions (MTJs)-based TCAM array.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Read Disturbances in Cross-Point Phase-Change Memory Arrays—Part I:
           Physical Modeling With Phase-Change Dynamics

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      Authors: Donguk Kim;Jun Tae Jang;Changwook Kim;Hyun Wook Kim;Eunryeong Hong;Sanghyun Ban;Minchul Shin;Hanwool Lee;Hyung Dong Lee;Hyun-Sun Mo;Jiyong Woo;Dae Hwan Kim;
      Pages: 514 - 520
      Abstract: Phase-change memory (PCM) connected to an additional selector has been implemented in cross-point arrays for storage class memory applications. In the one-PCM and one-selector (1S-1R) configuration, the selector should be turned on first to read the resistance state of the PCM. This requires a large read voltage ( ${V}_{read}$ ), and a high read current from the PCM is instantly produced, which causes read disturbances. To understand the underlying mechanism of the disturbance, in this study, we developed a physics-based Verilog-A model to describe the measured electrical behavior of the 1S-1R cell in HSPICE by considering thermally induced crystallization and melting dynamics. Based on ${V}_{TH}$ , which is the voltage induced when the selector is on, the crystalline and amorphous phases of the PCM can be identified indirectly. Based on the measured data, when the pristine amorphous state of the PCM is programmed by a higher SET current ( ${I}_{SET}$ ), ${V}_{TH}$ decreases owing to enhanced crystallization, leading to a low-resistance state. However, ${V}_{TH}$ subsequently begins to increase with respect to ${I}_{SET}$ , which results in a U-shaped ${V}_{TH}$ – ${I}_{SET}$ curve. It is inferred that melting is preferred at temperatures above 900 K induced by the high-read current. The ${V}_{TH}$ increase in-uced by the amorphization can be explained by transient simulations. The simulation results are in good agreement with the experimental data and reveal that the temperature generated from the 1S-1R cell plays an important role in triggering the unwanted phase transition of the GeSbTe layer during the read operation.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Read Disturbance in Cross-Point Phase-Change Memory Arrays—Part II:
           Array Simulations Considering External Currents

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      Authors: Donguk Kim;Jun Tae Jang;Changwook Kim;Hyun Wook Kim;Eunryeong Hong;Sanghyun Ban;Minchul Shin;Hanwool Lee;Hyung Dong Lee;Hyun-Sun Mo;Jiyong Woo;Dae Hwan Kim;
      Pages: 521 - 526
      Abstract: In Part I of this study, we demonstrated that when a high-read current from phase-change memory (PCM) programmed at a high-SET current ( ${I}_{text {SET}}{)}$ is achieved, melting dynamics in the chalcogenide layer are promoted, thus leading to read disturbances. Therefore, we analyzed additional external current sources that worsened the read disturbances by considering the PCM cell and additional selector and core circuits used in practical applications. By means of HSPICE simulations, the impact of two noticeable external overshoot and inrush currents generated during respective SET and read operations in one-selector and one-PCM (1S-1R) array was investigated. Our findings show that resistance-related components mainly affect the magnitude of the inflowing external current to the 1S-1R cell. The PCM can thus be easily heated up by the current, making the memory state vulnerable to the melting process. For these reasons, we showed that the disturbance primarily observed in the high ${I}_{text {SET}}$ operated PCM can also occur even at low- ${I}_{text {SET}}$ settings, given the actual cross-point array environment. Finally, we explored the maximum achievable array size that ensures disturbance-free read endurance by quantifying the read current to examine the location wherein the melting occurs.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Electrical Reliability of Flexible Low-Temperature Polycrystalline Oxide
           Thin-Film Transistors Under Mechanical Stress

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      Authors: Chanhee Han;Hyojung Kim;Dongbhin Kim;Jaewoo Shin;Yubin Park;Changwoo Byun;Byoungdeog Choi;
      Pages: 527 - 531
      Abstract: Electronic devices based on flexible displays have been developed for use in various applications. Upon bending such devices, the applied mechanical force deteriorates the reliability of the devices. Therefore, a high bending reliability that is influenced by tensile and compressive forces that vary depending on the bending radius of curvature must be secured to ensure a reliable device operation. In this study, we investigated the electrical characteristics of flexible low-temperature polycrystalline silicon (LTPS) and amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) on polyimide (PI) substrate and subsequently conducted reliability evaluation of the devices under mechanical stress by applying negative bias temperature illumination stress (NBTIS). The degradations in the electrical properties, such as threshold voltage ( ${V}_{text {th}}$ ) shift, OFF-state current ( ${I}_{text {off}}$ ), and subthreshold slope (SS), and reliability, increased, and the reliability worsened, as the tensile force increased under decreasing radius of curvature, whereas relatively low degradation occurred under compressive force. A tensile stress-induced increase in grain boundary state density in polycrystalline silicon (poly-Si) and oxygen vacancy in a-IGZO were verified by density of state (DOS) extraction; the cracks occurring due to tensile stress were optically analyzed; the external moisture penetration along the cracks further degrades the device characteristics. This study provides an analysis of device design for ensuring reliability under the application of mechanical stress, thereby contributing to the development of reliable flexible technology.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Ultrathin Indium Oxide Thin-Film Transistors With Gigahertz Operation
           Frequency

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      Authors: Adam Charnas;Jackson Anderson;Jie Zhang;Dongqi Zheng;Dana Weinstein;Peide D. Ye;
      Pages: 532 - 536
      Abstract: The remarkable dc performance of ultrathin indium oxide transistors offers a path toward high-performance back-end-of-line (BEOL) and monolithically integrated logic and memory devices for next-generation computing. Its very low thermal budget, high reliability, scalability, and 3-D conformality are additional factors that make these devices well-suited for these applications. Here, the radio frequency (RF) performance of indium oxide transistors with a high working frequency is characterized for the first time. A new record high cutoff frequency ( ${f}_{T}$ ) among amorphous metal–oxide–semiconductor transistors is reported with simultaneously high maximum oscillation frequency ( ${f}_{text {max}}$ ). Detailed statistical measurements across a wide variety of channel lengths and gate overlaps provide insight into optimization of the device parasitics and future scaling trends. Even at relatively long channel lengths of 1 $mu text{m}$ , the operation frequency is sufficient for these devices to function alongside traditional silicon CMOS devices that are generally clocked at less than 5 GHz.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • High-Performance 1-V IGZO Thin-Film Transistors Gated With Aqueous and
           Organic Electrolyte-Anodized Al x O y

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      Authors: Xiaoyu Lin;Qian Xin;Jaekyun Kim;Jidong Jin;Jiawei Zhang;Aimin Song;
      Pages: 537 - 543
      Abstract: In this work, ultrathin AlxOy films used as gate dielectrics in thin-film transistors (TFTs) are prepared in aqueous and organic electrolytes using an anodization process. A series of anodization voltages are used to investigate the effects of anodization electrolyte on the surface morphologies and electrical properties of AlxOy films. By using such anodized AlxOy films as gate dielectrics, 1-V indium–gallium–zinc–oxide (IGZO) TFTs are fabricated. The electrical characteristics of the IGZO TFTs with AlxOy films prepared in organic electrolyte are enhanced in comparison with those of the IGZO TFTs with AlxOy films prepared in aqueous electrolyte. The enhancement may be due to more carbon species introduced to the anodized dielectric films. This work offers a method to further improve the properties of ultrathin anodized dielectrics and shows the potential of using anodization in the future for large-area low-power electronics.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Effects of Static and Repetitive Uniaxial Bending Strains on the
           Electrical Properties and Trap Characteristics of Flexible Low-Temperature
           Polysilicon Thin-Film Transistors

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      Authors: Na Xie;Hui Zhu;Yiqun Zhang;Zeng Huang;Zhixuan Fang;Zheng Liu;Dong Li;Shiwei Feng;Chunsheng Guo;Yamin Zhang;Bo Liu;Lixing Zhou;Xing Liu;Yerong Sun;Zhirang Zhang;Yilin Li;Zhiwen Yao;
      Pages: 544 - 549
      Abstract: Changes in the electrical properties and trap characteristics of flexible low-temperature polysilicon thin-film transistors (TFTs) under the application of uniaxial bending strains and during repetitive bending cycles were investigated. When the bending strain increased, the transfer curve showed a negative shift, the output current decreased, and the subthreshold slope increased. After the bending strains were removed, the electrical performance showed recovery behavior, but the device performance could not return fully to its original state. The devices were also subjected to repetitive bending cycles. The transfer curves showed a positive shift after $10^{{4}}$ bending cycles and the output current increased. Using the transient current method, it was established that the detrapping time constant of the traps decreased and the peak amplitudes increased as a result of both the bending strain and the bending cycles. However, while the trap activation energy was not changed by static bending, it did decrease after the repetitive bending cycles. Both the changes in the electrical properties and the time constant spectra confirm that the trap state density increased as a result of the bending processes. However, the different trapping behaviors contributed to different degradations in the device’s electrical properties.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Optimizing Photonic Annealing Technique for High-k Dielectric of
           Full-Solution-Processed Oxide Thin Film Transistor

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      Authors: Meng Xu;Sunjie Hu;Cong Peng;Longlong Chen;Xifeng Li;Jianhua Zhang;
      Pages: 550 - 555
      Abstract: In this article, it is demonstrated that the photonic annealing process of ultraviolet (UV) irradiation or rapid thermal annealing (RTA)-assisted LA technique can effectively enhance the bias and illumination stability of full-solution-processed oxide thin film transistor (TFT). Although both post-annealing treatments have comparable effects, UV irradiation has relatively less heat loss and time consumption of only 3 min, compared to the RTA process that heats at a temperature of 400 °C and holds 10 min. Depending on the laser annealing (LA)/UV technique, the amorphous hafnium-aluminum oxide (HAO) dielectric thin film exhibits a smooth surface with an rms value of 0.293 nm, a high optical bandgap of 6.19 eV, and good dielectric performance with high dielectric constants of 12.9, low leakage current densities, and high breakdown field of about 4 MV/cm. Moreover, full-solution-processed indium-tin-oxide (ITO)–HAO–tungsten-zinc-tin-oxide (WZTO) TFT shows excellent overall properties with the mobility ( $mu $ ) of 10.65 cm $^{{2}}cdot text{V}^{-{1}}cdot text{s}^{-{1}}$ , subthreshold swing (SS) of 198 mV/dec. And the device has good bias and illumination stability, especially the threshold voltage ( ${V}_{T}$ ) shifts are all less than 3 V under positive bias illumination stress (PBIS) and negative bias illumination stress (NBIS) testing for 10000 s. These indicate the potential for the photonic annealing process of the UV-assisted LA technique on improving the stability of the full-solution-processed TFTs, which is attributed to high-throughput fabrication for large-area, transparent, and flexible electronics.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Enhanced Stability Performance of Transparent Ozone ALD ZnO Thin-Film
           Transistors With SiAlO X Dielectric

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      Authors: Wanpeng Zhao;Ning Zhang;Chong Yao;Junfeng Zhang;Tianfeng Huang;Yang Liu;Shurong Dong;Zhi Ye;Jikui Luo;
      Pages: 556 - 562
      Abstract: A new method is proposed to improve the stability performance of zinc oxide (ZnO) thin-film transistors (TFTs) by reducing density of oxygen vacancies and enlarging valance band offset (VBO) between channel/insulator simultaneously. At first, ozone (O3) is used as oxidant during the atomic layer deposition (ALD) of ZnO to reduce its oxygen vacancies from 22.64% to 14.32%, compared with the oxidant of H2O, resulting in less shift of threshold voltage ( $boldsymbol {Delta }{V}_{text {TH}}$ ) under negative bias stress with illumination (NBIS). To further improve the stability of TFTs under NBIS, Al2O3 layer is replaced by SiO2 to obtain larger VBO, but it introduces worse interface quality with larger hysteresis window (~0.57 V). Hence, a compound dielectric layer SiAlO $_{X}$ is proposed and prepared by ALD to improve the interface quality of ZnO/insulator. Combining O3 ALD ZnO and SiAlO $_{X}$ dielectric, the ZnO TFTs exhibit a high saturation mobility of 43.8 cm $^{{2}}cdot text{V}^{-1}cdot text{s}^{-{1}}$ , a negligible hysteresis window (< 0.01 V), and excellent stability under various stresses, especially under NBIS ( $boldsymbol {Delta }{V}_{text {TH}}= -1.09$ V).
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Design and Simulation of a Highly Sensitive Charge Detector With
           Nondestructive Readout Mode for Fully Depleted Thick CCDs

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      Authors: Miguel Sofo-Haro;Kevan Donlon;Barry Burke;Juan Estrada;Farah Fahim;Chris Leitz;
      Pages: 563 - 569
      Abstract: Several applications with charge-coupled devices (CCDs) and Skipper-CCDs can be significantly improved with an enhancement in pixel readout speed. In this work, we present the design and TCAD modeling of a highly sensitive double-gate MOSFET for charge amplification in CCD detectors. The design steps followed to integrate the device into high-voltage fully-depleted thick CCDs are described. Like Skipper-CCDs, the device allows for nondestructive readout of the charge packet for noise reduction. The simulations predict a sensitivity of $2.5,,text {nA}/text {e}^{-}$ and a readout noise of $2.4,,text {e}^{-}_{text {rms}}/text {pix}$ at a readout speed of $300 text {kpixels/s}$ . In a multisampling operation, a readout noise of $0.1,,text {e}^{-}_{text {rms}}/text {pix}$ can also be achieved at a readout speed in the order of $700 text {pixels/s}$ , approximately seven times faster than the Skipper-CCD at that same readout noise level.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Trap Behavior of the Optical Power Fluctuation in AlGaN-Based UV-C LEDs
           Degradation

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      Authors: Mengwei Su;Hongxia Liu;Ming Cai;Wenhong Sun;
      Pages: 570 - 575
      Abstract: The trap behavior of the optical power (OP) fluctuation in the degradation of deep ultraviolet light-emitting diodes (DUV-LEDs) is investigated in this work. The OP fluctuation under current stress is related to the combined action of acceptor activation, migration, and recombination. After stress, the changes observed in the admittance spectroscopy and deep-level transient spectroscopy measurements are due to a reduction in electron traps at ${E}_{c}$ –20 meV ( ${E}_{{1}}$ ) and increases in electron traps at ${E}_{c}$ –0.5 eV ( ${E}_{{2}}$ ), 0.68–0.79 eV ( ${E}_{{3}}$ ), and 0.95–1.2 eV ( ${E}_{{4}}$ ). The electron trap ${E}_{{1}}$ , located at the active region interface, has a prominent proportion in the apparent charge distribution profile and recombines with holes to restrict their entry into the quantum wells. The other traps contribute to an increase in the leakage current and nonradiative recombination. Reduction of the interface traps would weaken the hole transport shielding effect, but the hole injection augmentation would be wasted in the nonradiative recombination centers when defects are greatly generated in the active region during the long-term operation. Our study dissects the complex mechanisms in the electrical stress-induced degradation of DUV-LEDs and provides a constructive perspective on fabricating high-reliability AlGaN-based devices.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • High-Performance Carbon Nanodots/Graphene Heterojunction Solar-Blind
           Ultraviolet Photodetector via Vertical Structure

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      Authors: Taihao Chen;Shipeng Lin;Yong Fang;Zhiwei Zhao;
      Pages: 576 - 581
      Abstract: The vertical-structure heterojunction has been highlighted as a promising candidate for the solar-blind ultraviolet (UV) photodetector (PD) due to the control of its channel length and the strong electric field-induced high carrier mobility. Meanwhile, carbon nanodot (CND) has drawn great attention to be playing an essential role in absorbing solar-blind UV waves as the active layer of the PD. However, CND prepared for solar-blind UV PDs, independent of sophisticated manufacturing method and extreme process conditions, has yet to be well developed. Herein, for the very first time, a vertical structure CNDs/graphene heterojunction type solar-blind UV PD is introduced, where the CND and the graphene are used as the photosensitive layer and the transparent electrode, respectively. Particularly, the CND is fabricated with a low-cost and one-step electrochemical strategy. The device realizes an optimized performance tradeoff, presenting responsivity of 76.01 mA/W, normalized detectivity of $4.17times 10^{{10}}$ Jones, and rise/decay time of 0.54/0.27 s under the illumination of 1.47 mW/cm2 at 254-nm wavelength, along with the bias voltage of −5 V and the substrate voltage of 10 V applied. The results show that this work has unlocked the critical bottleneck of developing a graphene-based solar-blind UV PD with higher responsivity, greater detectivity, and shorter response time, unveiling the potential for missile warning, flame detection, and other areas of interest.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Design and Characterization of n/p-well CMOS SPAD With Low Dark Count Rate
           and High Photon Detection Efficiency

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      Authors: Jau Yang Wu;Chun-Hsien Liu;
      Pages: 582 - 587
      Abstract: We have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18- $mu text{m}$ high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Embedded Electrode Micro-LEDs With High Modulation Bandwidth for Visible
           Light Communication

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      Authors: Zihe Zhu;Lei Lei;Tingjun Lin;Linhao Li;Zhengliang Lin;Hongsheng Jiang;Guoqiang Li;Wenliang Wang;
      Pages: 588 - 593
      Abstract: GaN-based light-emitting diodes (LEDs) are the ideal light sources for visible light communication (VLC). However, both the low modulation bandwidth (MB) and unstable lighting output power (LOP) of LEDs at high current density restrict the further development of VLC. In this work, micro-LEDs ( $mu $ LEDs) with embedded ${N}$ electrodes have been proposed, possessing high MB and remarkable stability. The as-prepared $mu $ LEDs show a high MB of 240 MHz at 8.5 kA/cm2 and a small LOP aging rate of 6% under high temperature and humidity conditions due to the embedded electrode structure, which can effectively improve the uniformity of current spreading and increase the injection saturation current density, thereby effectively broadening the −3-dB MB and improving the LOP stability of $mu $ LEDs in harsh environments with high temperature and high humidity. Such high MB and reliable $mu $ LEDs shed light on a promising solution for industrial fabrication and chip arrays in underwater VLC systems.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • FD-SOI-Based Pixel With Real-Time Frame Difference for Motion Extraction
           and Image Preprocessing

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      Authors: Liqiao Liu;Xu Ren;Kai Zhao;Yandong He;Gang Du;
      Pages: 594 - 599
      Abstract: A frame differencing pixel (FDP) design based on fully depleted silicon-on-insulator (FD-SOI) technology is presented, demonstrating the capability of the FDP to perform pixel-level real-time frame difference (FD) for motion extraction and image preprocessing. The photo charges are collected by the diode under the buried oxide (BOX) and sensed by the MOSFET above. The capacitance of the BOX is used to generate the FD signal without incurring more area costs. TCAD simulations of the FD-SOI FDP were performed to help the analysis. An optimal pixel design model was developed to describe the relationship between noise performance and area allocation. According to the simulation results, the FDP could achieve light sensitivity of $25.6 ~mu text{A}$ /( $mu text{J}$ /cm2) and a differential signal-to-noise ratio of 35 dB with a $4 ~mu text{m}$ pixel pitch and 76% fill factor.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Effect of Different Ligands Coating on the Photovoltaic Performance of
           CdSe Quantum Dot-Sensitized Solar Cells

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      Authors: Yexin Chen;Shibing Zou;Wenhua Zou;Dongyang Wang;Junhong Duan;Weiqing Liu;Huaming Wu;
      Pages: 600 - 604
      Abstract: In this article, oleic acid (OA), oleylamine and tri-n-octylphosphine (OAm-TOP), and OA-TOP were used as ligands in the synthesis of CdSe quantum dots (QDs), respectively. Effect of three different ligands on the photovoltaic performance of CdSe QD-sensitized solar cells (QDSCs) is systematically investigated. Based on the results of UV-vis absorption spectra, it is confirmed that the absorption range is widen for CdSe QDs coated with OAm-TOP or OA-TOP compared with OA. Electrochemical impedance spectroscopy (EIS) study indicates that CdSe QDs synthesized using OAm-TOP or OA-TOP can better passivate the surface defects of QDs resulting in the improvement of photoelectric conversion efficiency (PCE) of devices. The optimized PCE of 3.6% was achieved for CdSe QDSCs modified with OAm-TOP.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Boosted Ambient Contrast Ratio of Light-Emitting Diode Display Devices
           With High Light Output Using a Laminated Interlaced Microgroove Janus
           Structure

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      Authors: Zongtao Li;Yunlong Zhang;Guanwei Liang;Fengyi Zhang;Jiasheng Li;
      Pages: 605 - 611
      Abstract: A high ambient contrast ratio (ACR) and brightness are critical for realizing high dynamic range (HDR) in advanced display applications. However, improving the ACR while maintaining high light output for display devices is still challenging. To solve this issue, we proposed a laminated interlaced microgroove (LIM) Janus structure, consisting of intersecting microgrooves cutting through the extinction and scattering layers, leading to highly improved ACR with less optical loss for display devices. Optical simulation was performed to optimize the LIM Janus structure, revealing the antireflection and light extraction mechanism with low reflectance and high light output. According to the high-speed dicing technique, the optimized LIM Janus film was prepared and assembled on light-emitting diode (LED) display devices. Compared with commercial display devices with graphite coating, the LIM display devices achieved a high ACR boosted from 2209 to 25 188 with an improvement of 1040% (ambient light 500 lux) while maintaining the high light output. The LIM Janus structure is facile and can be easily integrated into display devices to obtain excellent ACR and light output to satisfy the broad application of advanced displays.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Photoresponse Enhancement in Ge MSM Photodetector With Ge Micropillar
           Array

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      Authors: Ningning Zhang;Jifang Shao;Yuekai Hao;Yu Chen;Zhifang Zhang;Yichi Zhang;Liang Gao;Tian Miao;Zhenyang Zhong;Huiyong Hu;Liming Wang;
      Pages: 612 - 618
      Abstract: Improving detection efficiency of Ge photodetector near the absorptance edge is crucial for fiber-optic telecommunication. Here, we report the unique photodetection properties of germanium (Ge) metal–semiconductor–metal (MSM) photodetector with Ge micropillar array. The responsivity and detectivity of the device at 1550 and 1990 nm are studied. When compared with the Ge photodetector without micropillar, the responsivity and detectivity of micropillar Ge device are improved by 2.76 and 4.21 times at 1550 nm, respectively. This phenomenon is mainly associated with the enhanced absorption efficiency by geometrical light trapping effect and guided modes supported in the micropillar array. Particularly, the values of responsivity and detectivity in the device with Ge micropillar array are enhanced over 29.9 and 37.1 times at 1990 nm than the results in the device without micropillar, which are quite larger than the values at 1550 nm. This feature is related to that the suitable position of absorption enhancement caused by the micropillar array, which can result in the efficiently separation and suppressed recombination of photogenerated carriers under bias voltage. This work provides a feasible approach to broaden the detection wavelength of Ge-based photodetectors, enhance the absorption near the absorption edge, and improve the detection performance.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Fully-Vertical GaN-on-SiC Schottky Barrier Diode: Role of Conductive
           Buffer Structure

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      Authors: Yanjun Li;Shu Yang;Kai Liu;Kai Cheng;Kuang Sheng;Bo Shen;
      Pages: 619 - 626
      Abstract: This article reports a low ON-resistance fully-vertical GaN-on-SiC Schottky barrier diode (SBD) featuring a highly conductive buffer structure between the GaN drift layer and SiC substrate. To optimize the buffer structure, which is critical to the fully-vertical GaN-on-SiC SBD, heavily doped Al0.25Ga0.75N buffer layer on top of SiC substrate and graded Al $_{{0.25}to {0}}$ Ga $_{{0.75}to {1}}text{N}$ layer at the GaN/Al0.25Ga0.75N interface are implemented, yielding a reduced specific ON-resistance of 0.96 $text{m}Omega cdot $ cm2. The fully-vertical GaN-on-SiC SBD exhibits a high forward current density over 3000 A/cm2, a high current swing of ~ $10^{{11}}$ , a nearly ideal Schottky interface with a low ideality factor of ~1.03, and an enhanced reverse blocking voltage of ~520 V with fluorine-implanted termination (FIT). The optimization scheme of the buffer structure and its impact on the electrical performance have been analyzed and revealed. The demonstration of the fully-vertical GaN-on-SiC SBD with highly conductive buffer structure shows a practical approach to realizing fully-vertical GaN-on-SiC power devices and paves the way toward monolithic integration of GaN/SiC power devices.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Performance of a Novel Rear-Triggered 4H-SiC Photoconductive Semiconductor
           Switch

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      Authors: Zhuoyun Feng;Chongbiao Luan;Longfei Xiao;Yangfan Li;Huiru Sha;Xun Sun;Xiufang Chen;Xiangang Xu;Hongtao Li;
      Pages: 627 - 632
      Abstract: Radial lateral structure photoconductive switches are fabricated in this work via vanadium-doped 4H-SiC and high-purity 4H-SiC materials. The switches are triggered by 355- and 532-nm laser, and the performance of the switch is compared in the applied voltage range of 1–10 kV and laser energy range of 0.3–14 mJ. The experimental results show that the conduction current of the laser incident from the rear is larger. Simulations of the current density distribution of a 2-D cross section of the photoconductive switch provide theoretical support for this phenomenon. Additionally, the conduction current of the high-purity material is found to be higher than that of the vanadium-doped material under the same conditions.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Chip Size Minimization for Wide and Ultrawide Bandgap Power Devices

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      Authors: Boyan Wang;Ming Xiao;Zichen Zhang;Yifan Wang;Yuan Qin;Qihao Song;Guo-Quan Lu;Khai Ngo;Yuhao Zhang;
      Pages: 633 - 639
      Abstract: Chip size ( ${A}_{text {chip}}$ ) optimization is key to the accurate analysis of device and material costs and the design of multichip modules. It is particularly critical for wide bandgap (WBG) and ultrawide bandgap (UWBG) power devices due to high material cost. Moreover, the designs of ${A}_{text {chip}}$ and the drift region thickness ( ${W}_{text {dr}}$ ) and doping concentration ( ${N}_{text {dr}}$ ) are interdependent, requiring their co-optimization. Current design practices for ${A}_{text {chip}}$ , ${W}_{text {dr}}$ , and ${N}_{text {dr}}$ rely on optimizing electrical parameters. $^{^{^{}}}$ This work presents a new, holistic, electrothermal approach to optimize ${A}_{text {chip}}$ for a given set of target specifications, including breakdown voltage (BV), conduction current ( ${I}_{{0}}$ ), and switching frequency ( ${f}$ ). The conduction and switching losses of the device are considered as well as the heat dissipation in the chip and its package. For a given BV and ${I}_{text {o}}$ , the optimal ${A}_{text {chip}}$ , ${W}_{text {dr}}$ , and ${N}_{text {dr}}$ show a strong dependence on ${f}$ and thermal management. Such dependencies are missing in prior ${A}_{text {chip}}$ design methods. This approach is applied to compare the optimal ${A}_{text {chip}}$ of WBG and UWBG devices up to a BV over 10 kV and ${f}$ of 1 MHz. $^{^{^{}}}$ Our approach offers more accurate cost analysis and design guidelines for power modules.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Study on Transient Turn-On Characteristics of Pulse Power Thyristor-Type
           Devices Under Ultrahigh di/dt Condition

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      Authors: Chao Liu;Pengcheng Xing;Shuyi Zhang;Wanjun Chen;Ruize Sun;Xiaorui Xu;Yun Xia;Yajie Xin;Yijun Shi;Zhaoji Li;Bo Zhang;
      Pages: 640 - 646
      Abstract: Specially optimized thyristor-type devices for fast turn-on and high $text{d}{i}/text{d}{t}$ capability are promising in pulse power applications. In this work, the transient turn-on characteristics of MOS-gate triggered and current-gate triggered thyristor-type devices operating at ultrahigh $text{d}{i}/text{d}{t}$ conditions are first studied. The injected charge transport process is theoretically analyzed and modeled by considering the effect of the transient electric field, during short pulse duration, which then clearly reveals the difference between the MOS-gate triggered and current-gate triggered thyristor-type devices on the transient turn-on characteristics. TCAD simulations and experimental measurements are carried out to verify the transient turn-on process. The theoretical, simulated, and experimental results show that the MOS-gate triggered thyristor has better turn-on characteristics than the current-gate triggered thyristor, which attributes to the reduced turn-on step and consequently stronger conductivity modulation. This work helps further optimization of thyristor-type devices achieving fast turn-on and high- $text{d}{i}/text{d}{t}$ capability.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Low On-State Voltage and EMI Noise 4H-SiC IGBT With Self-Biased Split-Gate
           pMOS

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      Authors: Lijuan Wu;Mengjiao Liu;Mengyuan Zhang;Jiahui Liang;Gang Yang;Tengfei Zhang;Qing Liu;
      Pages: 647 - 652
      Abstract: A 15-kV-scale 4H-SiC insulated-gate bipolar transistor (IGBT) with a self-biased split-gate pMOS (SGPMOS) is proposed and simulated in this work. By introducing the SGPMOS, the proposed IGBT forms a hole barrier in the ON-state and a hole extraction path during the turn-on and turn-off transient, respectively. Compared to GS IGBT, the ON-state voltage ( ${V}_{text {ON}}{)}$ of the SGPMOS IGBT is decreased by 54.95% for the same turn-off loss ( ${E}_{text {off}}$ ). Meanwhile, compared with pMOS IGBT, the ${C}$ – ${V}$ and gate charge ( ${Q}_{g}{)}$ characteristics exhibit that the Miller capacitance ( ${C}_{text {gc}}{)}$ and ${Q}_{g}$ of the SGPMOS IGBT are reduced by 56.60% and 35.85%, respectively. Moreover, SGPMOS can extract the hole accumulated both under the gate oxide and in the P-shield region during the turn-on transient. This diminishes reverse displacement current ( ${I}_{G_{}{text {dis}}}{)}$ , contributing to low electromagnetic interference (EMI) noise. Simulation results demonstrate that, compared to pMOS IGBT, the SGPMOS IGBT achieves better controllability in peak turn-on current ( ${I}_{text {max}}{)}$ and turn-on $text{d}{I}_{C}/text{d}{t}$ , featuring a 52.-5% lower maximum reverse recovery $text{d}{V}_{text {KA}}/text{d}{t}$ for the same turn-on loss ( ${E}_{text {on}}{)}$ .
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • A 3-D Thermal Network Model for Monitoring of IGBT Modules

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      Authors: Ke Heng;Xin Yang;Xinlong Wu;Junjie Ye;
      Pages: 653 - 661
      Abstract: With the continuous improvement of power densities and power levels for power converters, temperature information at critical sites of the power modules has become essential in health monitoring and thermal management. However, existing thermal models often ignore the temperature distributions of the chip and rarely discuss their applicability under high-temperature operation conditions. Here, a novel 3-D physical RC network model is proposed for insulated-gate bipolar transistor (IGBT) modules, which considers the temperature effects. This model can be efficiently and conveniently obtained with the assistance of finite-element method (FEM) steady-state thermal simulations. Based on the heat flux curves inside the power module, a novel method for 3-D RC parameters extraction is presented to monitor the temperatures at critical sites of the IGBT chip, and meanwhile, the temperature effects and uneven power loss distribution on the chip are considered. Compared with the prior-art Foster-type temperature-dependent 3-D thermal models, the modeling time cost for the proposed model has been remarkably reduced under the same computing hardware facilities since the temperature responses are no longer needed. Finally, FEM simulation and experimental results verify the effectiveness and accuracy of the proposed 3-D physical RC network model.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Fast-Switching and Low-Loss SOI LIGBT With Recombination Electrode and
           Double U-Shaped P-Regions

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      Authors: Jie Wei;Kaiwei Dai;Kemeng Yang;Pengchen Zhu;Jie Li;Zhaoji Li;Bo Zhang;Xiaorong Luo;
      Pages: 662 - 666
      Abstract: A novel fast-switching low loss silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed and investigated by simulation. It features a recombination electrode (RE) at anode side and U-shaped P-regions (UP) at the anode and cathode side, respectively (UPRE LIGBT). In a low ON-state anode voltage ( ${V}_{text {A}}$ ), the anode side UP (UPa) depletes the N-region under the RE to increase the distributed resistance and thus realize snapback free. Meanwhile, the UPa increases the hole injection area to reduce the ON-state voltage drop ( ${V}_{ mathrm{scriptscriptstyle ON}}$ ). During the turning off, the depletion region between the UPa and N-region shrinks and provides an electron path to the RE, which accelerates electrons to recombine with holes through the RE and thus decreases ${E}_{ mathrm{scriptscriptstyle OFF}}$ . Therefore, the UPRE LIGBT performs a superior tradeoff relationship between ${V}_{ mathrm{scriptscriptstyle ON}}$ and ${E}_{ mathrm{scriptscriptstyle OFF}}$ . Furthermore, the cathode side UP (UPc) provides a low-resistance hole current path to enhance the latch-up immunity. Consequently, at the same ${E}_{ mathrm{scriptscriptstyle OFF}}$ , ${V}_{ mathrm{scriptscriptstyle ON}}$ of UPRE LIGBT is 27% and 10% lower than that of separated shorted-anode (SSA) and multisegment anode (MSA) LIGBT, respectively. At the same ${V}_{ mathrm{s-riptscriptstyle ON}}$ , the UPRE LIGBT reduces ${E}_{ mathrm{scriptscriptstyle OFF}}$ by 32% compared with the MSA LIGBT. The UPRE LIGBT improves the short-circuit (SC) withstanding time by 33.8% compared with the one without UPc.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • High-Current and Short-Circuit Capability SOI-LIGBT With Double-Integrated
           Self-Adapted MOS-Resistors

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      Authors: Kemeng Yang;Wei Su;Junnan Wang;Jie Wei;Yuxi Wei;Tao Sun;Zhaoji Li;Bo Zhang;Xiaorong Luo;
      Pages: 667 - 674
      Abstract: A 300-V-rated high-performance SOI-LIGBT with double-integrated MOS resistors (MR LIGBT) is proposed and its mechanism is investigated. It features double-integrated self-adapted MOS resistors ${R}_{text {M1}}$ and ${R}_{text {M2}}$ . ${R}_{text {M1}}$ and ${R}_{text {M2}}$ influence states of the parasitic diode ${D}_{{0}}$ in the conventional LIGBT region and parasitic diode ${D}_{{1}}$ in ${R}_{text {M1}}$ by modulating the potential of ${P}^{+}{(}{V}_{text {P}}{)}$ and ${N}^{+}{(}{V}_{text {N}}{)}$ near the trench gate. In the ON-state, the adaptive turn-on ${D}_{{0}}$ caused by the large ${R}_{text {M1}}$ enhances the conductivity modulation. When ${D}_{{1}}$ is triggered at a high anode voltage, ${V}_{text {N}}$ is clamped and the device turns into saturation. The turn-on ${D}_{{0}}$ increases the saturation current density of the MR LIGBT to $2.5times $ of self-adjust conduct-vity modulation trench (SCMT) LIGBT and reduces the ON-state voltage drop ( ${V}_{text {on}}$ ) by 49% and 36% compared with conventional (Con.) LIGBT and SCMT LIGBT, respectively. ${D}_{{0}}$ adaptively turns off during short-circuit and turn-off periods. Consequently, compared with the Con. and SCMT LIGBTs, the MR LIGBT not only lengthens the short-circuit time ( ${t}_{text {SC}}$ ) to $24.7~mu text{s}$ from 7.12 to $19.8~mu text{s}$ , but also decreases ${E}_{text {off}}$ by 74% and 54% at the same ${V}_{text {on}}$ . Owing to the prominent static and dynamitic characteristics, the total power loss of the MR LIGBT is reduced by 28% and 40% at ${f} =50$ kHz compared with that of SCMT and Con. LIGBTs.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • On-Resistance–Reliability Tradeoffs in Al₂O₃/LaAlO₃/SiO₂ Gate
           for SiC Power MOSFETs

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      Authors: Linhua Huang;Yong Liu;Xin Peng;Takashi Tsuji;Yuichi Onozawa;Naoto Fujishima;Johnny K. O. Sin;
      Pages: 675 - 682
      Abstract: On-resistance–reliability tradeoffs are investigated for SiC power MOSFETs using Al2O3/LaAlO3/SiO2 gate dielectrics. Due to the high gate capacitance, the Al2O3/LaAlO3/SiO2 gate device shows an improvement on the channel resistance ( ${R}_{text {ch}}$ ) versus threshold voltage shift ( ${Delta } {V}_{text {th}}$ ) tradeoff compared to the SiO2 gate counterpart. Besides, the short-circuit withstand time of the Al2O3/LaAlO3/SiO2 gate device is 1.55 times longer than that of the SiO2 gate device, while the two devices have the same on-resistance. Furthermore, the predicted lifetime of the Al2O3/LaAlO3/SiO2 gate device is ten years at an effective electric field ( ${E}_{text {eff}}$ ) of 4.8 MV/cm, which is comparable with the latest reported result of the SiO2 gate counterpart.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Transient-Liquid-Phase Bonding of Granulated Cu–Sn Bumps With a 4-μm
           Fine Pitch

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      Authors: Yunfan Shi;Zilin Wang;Huawei Zhang;Jin Kang;Kai Zheng;Weihai Bu;Zheyao Wang;
      Pages: 683 - 688
      Abstract: It is difficult for Cu–Sn transient-liquid-phase (TLP) bonding to achieve fine bump pitches because liquid Sn extrudes laterally under bonding pressure and may cause electrical short of adjacent bumps. To solve this problem, this article reports a new Cu–Sn bonding method that uses granulated Sn layers instead of conventional continuous Sn layers. To form Sn granules, a reflow method is developed by exploiting a new phenomenon that sequential oxidation and reduction of melted Sn changes it to granulated structures. During Cu–Sn bonding, the granulated Sn allows fast Cu diffusion and rapid Cu–Sn reaction, which consumes Sn quickly and avoids liquid Sn extrusion. The Cu–Sn reaction forms intermetal compounds (IMCs) with a coral-like structure and large porosity, further alleviating the Sn extrusion by accommodating the melted Sn. Using this method, fine-pitch Cu–Sn bump bonding with a $2.9~mu text{m}$ diameter and a $4~mu text{m}$ pitch has been successfully achieved with high bonding yield and low resistivity.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Multiscale Simulations of 2-D Material Ink-Based Printed Network Devices

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      Authors: Prabhat Kumar Dubey;Damiano Marian;Gianluca Fiori;
      Pages: 689 - 694
      Abstract: We present a simulation study of printed transistors composed of networks of two-dimensional materials flakes based on a multiscale approach. Printed devices are modeled by generating flake distribution using a Monte Carlo method, performing ab initio density functional theory (DFT) and nonequilibrium Green’s function (NEGF) calculations to obtain flake-to-flake mobility and finally computing transport in a three-dimensional drift-diffusion scheme coupled with the electrostatics by means of the Poisson equation. The method has been applied to MoS2-based devices while investigating the impact of trap charges on the device performances as well as the mixing of MoS2with graphene, a technological option currently experimentally investigated in the literature. We will show that the presence of traps is detrimental to the OFF current, which could be the main reason for the reduced current modulation observed in experiments. Mixing MoS2with graphene can instead be considered as an option to optimize the ON and OFF current of the device.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Modeling and Characterization of Annealing-Induced Cu Protrusion of TSVs
           With Polyimide Liner Considering Diffusion Creep Behavior

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      Authors: Baoyan Yang;Yingtao Ding;Zhiqiang Cheng;Anrun Ren;Lei Xiao;Yangyang Yan;Ziyue Zhang;Zhiming Chen;
      Pages: 695 - 701
      Abstract: Polymer liner has been used in through-silicon-vias (TSVs) for smaller parasitic capacitance and better thermo-mechanical performance. For the application in heterogeneous integrated systems, it is critical to study the thermal reliability of such TSVs in both theoretical modeling and experimental characterization. Among the numerous reliability challenges, the Cu protrusion phenomenon of TSVs is one of the most severe issues, which can lead to cracks and delamination in integrated systems. In this article, the annealing-induced Cu protrusion of polyimide (PI) liner TSVs is studied by experiments and simulations. PI-TSVs are fabricated and the Cu protrusion at various annealing conditions is characterized. Finite element analysis (FEA) is carefully carried out taking into account the diffusion creep rate model, and the deviations between FEA and experiment results of protrusion heights are less than 3%. Besides, the deformation procedure and the creep behavior of Cu pillars during annealing are analyzed. Based on the proposed FEA model, comprehensive parametric analyses are conducted to study the effects of different annealing conditions on the Cu protrusion heights, which are helpful to understand and improve the thermal reliability of PI-TSVs.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Porosity Dependence of Thermal and Electrical Properties in Nano-Silver
           Paste

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      Authors: Weishan Lv;Jiaxin Liu;Xin Lei;Fulong Zhu;
      Pages: 702 - 707
      Abstract: Nano-silver paste is considered one of the most promising die-attach materials for high-temperature applications contributing to its excellent thermal and electrical properties and low bonding temperature. However, it is difficult to measure the thermal conductivity and electrical resistivity of nano-silver in practical applications. In this work, we proposed a finite element modeling method to predict the thermal conductivity and electrical resistivity of nano-silver. Nano-silver flake and film with different porosity were prepared by adjusting the sintering temperature, and the thermal and electrical properties were measured. The simulated results are in good agreement with the experimental results under all porosity. The error values between the experimental and simulated temperatures are less than 10%. With the increase of porosity, the thermal conductivity of nano-silver decreases and the electrical resistivity increases. Pores will cause heat flow and current concentration, and increase the possibility of failure of nano-silver in practical applications. The results indicate that the porosity plays a more important role in the thermal and electrical properties of the nano-silver compared with pores location.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Quasi-Fermi-Based Charge Transport Scheme for Device Simulation in
           Cryogenic, Wide Bandgap, and High-Voltage Applications

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      Authors: Zlatan Stanojević;José María González-Medina;Franz Schanovsky;Markus Karner;
      Pages: 708 - 713
      Abstract: We present a novel approach to solving the transport problem in semiconductors. We reformulate the drift-diffusion (DD) equations in terms of the quasi-Fermi-energies as solution variables; a drastic increase in numerical stability is achieved, which permits the simulation of devices at cryogenic temperatures as well as wide bandgap devices using double precision arithmetic, instead of extended precision arithmetic which would otherwise be required to solve these applications using regular DD.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Coexistence of Space Charge Limited and Variable Range Hopping Conduction
           Mechanism in Sputter-Deposited Au/SiC Metal–Semiconductor–Metal Device
           

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      Authors: Alisha Arora;Satyendra Mourya;Neetika Singh;Sandeep Kumar;Ramesh Chandra;V. K. Malik;
      Pages: 714 - 719
      Abstract: Despite being the cornerstone of high-temperature and high-power applications, the fabrication of silicon carbide (SiC) thin films has been a major challenge among research activities related to wide bandgap semiconductors. As almost all the reported SiC thin films produced by RF sputtering are amorphous, the growth of crystalline thin film on p-type silicon substrate at high temperature (>900 °C) is presented in this work. A metal–semiconductor–metal (MSM) device is fabricated with gold (Au) electrodes by sputtering. A unique behavior of current–voltage ( ${I}$ – ${V}$ ) characteristics is found in different voltage regimes. The thermionic emission model fails to explain the observed ${I}$ – ${V}$ characteristics. To understand the current transport mechanism in detail, ${I}$ – ${V}$ characteristics are carried out in the temperature range 250–380 K and divided into two voltage regimes, below and above 1 V. Below 1 V, variable range hopping mechanism (VRH) is found to be dominant and above 1 V, and ohmic conduction followed by space charge limited conduction (SCLC) is held accountable for the current transport mechanism. The analysis of both mechanisms indicates the presence of disorder states and gives valuable information about trap centers. The ${C}$ – ${V}$ characteristics further suggest the presence of interface states and deep traps. The advantageous implementation of this information will help to design optoelectronic, magnetic, and efficient energy storage devices to extract the maximum performance.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Thermal Sensing Characteristics of Low-Voltage n-Channel Organic
           Field-Effect Transistors With Triple Layers of
           Naphthalenediimide-Containing Conjugated Polymer and Gate-Insulating
           Polymers

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      Authors: Chulyeon Lee;Woongki Lee;Myeonghun Song;Hwajeong Kim;Youngkyoo Kim;
      Pages: 720 - 725
      Abstract: Organic field-effect transistors (OFETs) were fabricated with n-type naphthalenediimide-based conjugated polymer (N2200) as a channel layer and poly(methyl methacrylate) (PMMA)/poly(vinyl alcohol) (PVA) as a gate-insulating layer. The OFETs with the N2200/PMMA/PVA triple layers were operated with an n-channel mode at low voltages (≤5 V) and their electron mobility reached ca. 0.63 cm2/ $text{V}cdot text{s}$ at a drain voltage of 5 V. The drain current of OFETs was gradually increased as the temperature of channel region increased from 25 °C to 80 °C, whereas no shift in threshold voltage was measured upon the temperature variation. The relative thermal sensitivity of devices was almost linearly increased with the temperature, while a two-stage behavior by a border of ca. 35 °C was measured for specific thermal sensitivity. The present n-channel OFETs exhibited excellent thermal sensing performances upon repeated approaching/retracting tests using a heat source.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Random Number Generation With a Hybrid Conjugated Polymer Memristor

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      Authors: Stephen H. Foulger;Yuriy Bandera;Benjamin Grant;Jiři Pfleger;
      Pages: 726 - 731
      Abstract: A two-terminal memristor was constructed from electrochemically doped poly(4-(6-(9H-carbazol-9-yl)hexyl)-4H-dithieno[3,2-b:2’,3’-d]pyrrole) (pC6DTP) and employed as a random number generator (RNG). The polymer exhibited a conductive nature that was dependent on its voltage history that was theorized to be due to two synergistic percolation mechanisms: one associated with the pendant electroactive heterocyclic rings and one associated with the polymer backbone conjugation. The generated random number (RN) stream was evaluated for “randomness” with select tests from NIST SP 800–22 Rev. 1a testing protocol, which indicated that the bitstream was classified as random as generated without any postprocessing, while the energy required to generate a bit was ca. 0.67 pJ.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Self-Powered Paper-Based Pressure Sensor Driven by Triboelectric
           Nanogenerator for Detecting Dynamic and Static Forces

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      Authors: Sheng-Yuan Xia;Liang-Yan Guo;Lu-Qi Tao;Yunfeng Long;Zhengyong Huang;Jianfa Wu;Jian Li;
      Pages: 732 - 738
      Abstract: To meet the growing demand for self-powered pressure sensors that can be used to detect both dynamic and static forces, this study presents a self-powered pressure sensor driven by the triboelectric nanogenerator (TENG). This TENG-driven piezoresistive pressure sensor (DRPS) consists of paper-based reduced graphene oxide (rGO)/carbon nanotube (CNT) piezoresistive pressure sensor and polyimide (PI)/copper TENG in series. Our piezoresistive pressure sensor has a high sensitivity (26.4 kPa−1) in the small pressure range (0–3 kPa). The open-circuit voltage of our PI/copper TENG enhanced by rGO paper is about 250 V. The DRPS has a high linear sensitivity (18.6782 kPa−1) in the pressure range of 0–5 kPa, which meets the demand for self-powered pressure sensors for detecting various forces. The response time and the recovery time of DPRS are both 500 ms. The Morse code is achieved by the DRPS, which demonstrates the potential application. This study presents a new insight into the development of self-powered pressure sensors.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • A Washable, Permeable, and Ultrasensitive Sn-Based Textile Pressure Sensor
           for Health Monitoring

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      Authors: Meiying Li;Yuting Wang;Xiaolong Wen;Anchun Tang;Chubin Wan;Tingting Sui;Dandan Zhang;Xin Ju;
      Pages: 739 - 745
      Abstract: Wearable pressure sensors have attracted significant consideration due to their wide use in healthcare, intelligent robotics, and electronic skin. In this article, a dielectric material composed of Sn-based nanofibers containing SnOx/SnCl2 ( ${x} =$ 1 and 2) was proposed for the first time to enhance the performance of pressure sensors. Compared with most of the reported nanofiber-based film pressure sensors, our tissue-like nanocomposite sensors achieve optimized sensitivity and working range and are particularly suitable for wearable applications. In contrast to most current research, electrospun nanofiber mats were oxidized without further pyrolysis at 100 °C, 200 °C, and 300 °C. Especially after annealing at 200 °C, the assembled tissue-like pressure sensor presents remarkable performance with a working range of up to 50 kPa and a sensor sensitivity of 11.6 kPa−1 (0–1 kPa). In addition, this sensor exhibits excellent cycling stability, permeability, and washability. Therefore, polyvinylpyrrolidone (PVP)/SnCl2 tissue-like nanocomposite sensors can be utilized in a wide variety of flexible and wearable electronic device applications in the future.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Identification of the Current Transport Mechanism in a Vertical
           Zr/LaB6/p-Diamond Schottky Barrier Diode for Low-Power Highly Sensitive
           Temperature Sensor

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      Authors: Guoqing Shao;Juan Wang;Yanfeng Wang;Wei Wang;Hong-Xing Wang;
      Pages: 746 - 751
      Abstract: We proposed a low-power highly sensitive temperature sensor based on a diamond Schottky barrier diode (SBD) with an inserted lanthanum hexaboride (LaB6) interlayer at the Zr/diamond interface. The Zr/LaB6/p-diamond SBD exhibits excellent thermal stability with rectification ratios higher than $10^{{10}}$ in a wide temperature range of 298–573 K. The Schottky barrier height (SBH) increases, whereas the ideality factor decreases with increasing temperature. This SBD delivers a high SBH of 2.06 eV and an ideality factor close to 1 at 573 K. In addition, a thermionic emission (TE) theory assumes the Gaussian distribution of SBH to be the dominating current transport mechanism (CTM) for Zr/LaB6/diamond SBD, due to the existence of SBH inhomogeneities at Zr/diamond interface. Meanwhile, the extracted values of the mean SBH and Richardson constant are 2.74 eV and 82.43 A/cm $^{{2}}~cdot ~text{K}^{{2}}$ , respectively, which are much closer to their theoretical values of 2.72 eV and 96 A/cm $^{{2}}~cdot ~text{K}^{{2}}$ , respectively. Furthermore, a high thermal sensitivity of 5.1 mV/K is obtained for a temperature sensor based on this SBD. Our results suggest the great potential of adopting this SBD structure for high-performance temperature sensors.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Demonstration of an Ultracompact, High-Isolation Power Coupler for W-Band
           Sheet Beam Traveling Wave Tubes

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      Authors: Yixin Wan;Jianxun Wang;Xinjie Li;Zihao Dai;Wei Jiang;Qiang Zheng;Yong Luo;
      Pages: 752 - 758
      Abstract: The emerging sheet beam devices have become a research hotspot in the field of vacuum electronics due to their excellent performance in the millimeter-wave and even terahertz bands, but there are still many technical bottlenecks in the actual manufacture and the engineering realization. In this article, an ultracompact high-isolation power coupler prototype is demonstrated for high-efficiency injection and extraction of electromagnetic energy from the sheet beam traveling wave tubes (SB-TWTs). The introduction of polarized rotators avoids the coupling of electromagnetic waves into the electron channel, thereby improving isolation performance. The improved structure with multiparameter tunability ensures low reflection and broadband characteristics. The simulation shows that its extreme bandwidth (BW) is 40% and the in-band isolation is less than −50 dB. Moreover, the parasitic resonance mode is analyzed and related suppression technology is also proposed. Then, two prototypes of a ${W}$ -band coupler have been processed and tested. The related machining errors have been analyzed and a good consistency is verified between the experiment and the simulation. Compared with the best level of the existing coupler, this ultracompact structure with less than one free-space wavelength (calculated from the central frequency point) relieves the pressure of the sheet beam transmission system, reduces the risk of electronic interception, and provides a feasible solution for engineering realization of sub-millimeter-wave or terahertz SB-TWTs.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Efficiency Enhancement of a Dual-Band Magnetically Insulated Line
           Oscillator Using a Modulation Cavity

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      Authors: Mohit Kumar Singh;Manpuran Mahto;Pradip Kumar Jain;
      Pages: 759 - 764
      Abstract: In this article, performance enhancement of a dual-band magnetically insulated line oscillator (DBMILO) using a modulation cavity has been presented. In the proposed design, a modulation cavity has been introduced in between the slow wave structure (SWS) of the output end, which lessens the energy spread of the modulated beam electrons. The impact of the modulation cavity on the transmission characteristics and the operating frequency of the modified DBMILO are investigated through electromagnetic (EM) simulation. The dimensions of the modulation cavity are optimized to ensure approximately the same operating frequency in the modified design. The RF behavior of the proposed and conventional design is examined through the particle-in-cell (PIC) solver code. For the input dc voltage and current of 500 kV and 56 kA, respectively, the output power of the conventional DBMILO provides ~3.6 GW with 12.8% efficiency, whereas the proposed DBMILO with modulation cavity generates ~4.8 GW with 17.1% efficiency. The microwave frequency in both cases is 3.4 and 10.1 GHz. Compared to the conventional DBMILO, the power efficiency of DBMILO with modulation cavity enhances by 33%.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Study on Pseudospark Switch Triggered by 532-nm Focused Laser

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      Authors: Guoxiang Sun;Xia Wang;Weidong Ding;Jiaqi Yan;Saikang Shen;Shaohao Nie;
      Pages: 765 - 770
      Abstract: The influence of laser energy, irradiation position, photoelectric material, and anode voltage on the trigger characteristics of a pseudospark switch triggered by a 532-nm nanosecond focused laser is studied. The parameters of the seed electrons induced by the interaction between the focused laser and metal are measured. It is found that the increase of laser energy and anode voltage can increase the current density of seed electrons, reduce the time of electrons diffusion to the cathode hole, and thus reduce the trigger delay. When the irradiation position is close to the cathode hole, the surface electric field is larger, which is conducive to achieving a smaller trigger delay and jitter under low laser energy. The seed electron current induced by the focused laser has two peaks. The first peak mainly corresponds to the thermal emission, with a short time delay and narrow pulsewidth, contributing to the trigger. The second peak mainly corresponds to the electrode surface ablation, with a long time delay and large pulsewidth, contributing little to the trigger. In this case, the electrode surface temperature is more important than the work function, so Cu has better electron emission characteristics than Mg. With the increase of laser energy, the number of electrons in high-energy components increases.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Electrical Characterization of Plasma-Assisted Electron Beam Source With
           Sub-mm Sheet Aperture

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      Authors: Anand Abhishek;Niraj Kumar;Vishant;Bharat Lal Meena;Sahil Jain;Shriganesh Prabhu;Ajay Mishra;Nimish Dixit;Sudhir Khare;
      Pages: 771 - 775
      Abstract: In this article, the electrical characterization of a plasma-assisted electron beam source with a sub-mm sheet aperture has been performed. The developed sheet electron beam source comprises a hollow cathode cavity, two floating anodes, and one ground potential anode with a sheet aperture of $1.5times0.3$ mm. The source has been characterized under varying applied gap potential range, i.e., 10–30 kV in self-breakdown operating mode. The breakdown parameters and resultant beam parameters, such as ${V} - {I}$ characteristics, electron beam current density, duration to reach the conductive phase, and the energy transformation efficiency of the developed source, have been analyzed. The successive breakdown phenomenon has also been presented in the profile of the developed electron beam source.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Ion Intercalation Enabled Tunable Frequency Response in Lithium Niobite
           Memristors

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      Authors: Aheli Ghosh;Alex S. Weidenbach;Bill Zivasatienraj;Timothy M. McCrone;W. Alan Doolittle;
      Pages: 776 - 781
      Abstract: Memristors have emerged as a viable component for developing neuromorphic hardware platforms, which can compete with biological systems in density, accuracy, and energy efficiency. Among contemporary memristive systems, intercalation-driven lithium niobite (LiNbO2) memristors have the advantage of inherent flux-driven large analog conductance tunability ( $Delta {R}/{R}>89$ ), a wide resistance range (~10–1E $7 Omega $ ) selected via geometry selection, and low-power (~100–150 mV) neuromorphic functionality resembling synaptic weight updates in the synaptic membrane. Emerging neural systems require nonstatic temporal responses to implement temporally diverse architectures, such as recurrent neural networks (RNNs), yet these temporally diverse memristors are rare. There is a gap in understanding of the frequency response of nonvolatile memristors, which is a fundamental characteristic in memristive systems and ultimately dictates the speed of adaptive learning in deployed neural networks and the memory windows available for designers in RNNs. Using both large and small signal characterization methods, these memristors demonstrate up to a decade of span in tunable frequency-dependent response, statically controlled via device geometry and scaling design rules, and dynamically tuned via channel lithium concentration. Thus, the tunable frequency dependence of resistance modulation in LiNbO2 memristors is evaluated, enabling future neural network design rules to be identified for scalable multifunctional memristive systems for neuromorphic computing applications.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Improved Performance of MoS2 Negative-Capacitance Field-Effect Transistors
           by Optimizing Gate-Stack of Al-Doped HfO2/Al2O3

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      Authors: Yuqin Xia;Lu Liu;Xinge Tao;Yuying Tian;Jing-Ping Xu;
      Pages: 782 - 788
      Abstract: In this work, negative-capacitance field-effect transistors (NCFETs) based on Hf $_{{1}-{x}}$ AlxOy ferroelectric films are fabricated, and the effects of the Al content in Hf $_{{1}-{x}}$ AlxOy films and the thicknesses of the ferroelectric Hf $_{{1}-{x}}$ AlxOy layer/Al2O3 match layer on the electrical properties of the NCFETs are focused. The results show that as the Al content decreases and the thickness of the ferroelectric layer/the match layer increases/decreases, the remanent polarization intensity of the gate-stack of Hf $_{{1}-{x}}$ AlxOy/Al2O3 becomes large, and the subthreshold swing (SS) and total hysteresis of the relevant NCFETs are decreased. When the ratio of Al to Hf is about 1:19 to form Hf0.95Al0.05Oy ferroelectric film and the thicknesses of Hf0.95Al0.05Oy/Al2O3 are 10 nm/2 nm, respectively, excellent device performance is obtained with a low SS of 35.4 mV/dec, high ON/ OFF current ratio of $5.0times 10^{{6}}, $ and negligible hysteresis of 36.2 mV. The involved mechanisms lie in enhanced ferroelectricity of Hf $_{{1}-{x}}$ AlxOy films and a good matching between the ferroelectric capacitance and MOS capacitance of devices under the suitable structure and process parameters.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • A Drift-Diffusion Based Modeling and Optimization Framework for Nanoscale
           Spin-Orbit Torque Devices

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      Authors: Piyush Kumar;Yu-Ching Liao;Daniel C. Ralph;Azad Naeemi;
      Pages: 789 - 795
      Abstract: We present a comprehensive set of experimentally validated/calibrated models that capture the physics of the nanoscale spin-orbit torque (SOT) devices. We consider various effects that are prominent at nanoscale including incomplete current redistribution, interface spin mixing, and nonuniform resistivity that were ignored in the prior modeling efforts. We develop a formalism based on drift-diffusion equations and the transfer matrix method to accurately estimate spin current distribution. We utilize finite element simulations to accurately calculate electric current density and field, and see considerable differences to the results from the simplified lumped model commonly used. For example, we calculate ~20% smaller spin current in a 15-nm-wide ferromagnet with a 4-nm-thick $beta $ -W SOT channel. We further account for the effect of interface scattering on resistivity. Finally, we quantify the optimal SOT-layer thickness that minimizes the write energy as a function of spin diffusion length and conductivity of SOT materials. We show that the optimal thickness increases with the spin diffusion length and decreases with the conductivity.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Improved Subthreshold Swing of MoS₂ Negative-Capacitance Transistor by
           Using HfZrAlO as Ferroelectric Layer of Gate-Stack

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      Authors: Xinge Tao;Lu Liu;Jingping Xu;
      Pages: 796 - 800
      Abstract: In this work, a hafnium–zirconium–aluminum–oxide (HZAO) is proposed and atomic layer deposition (ALD), and its ferroelectricity is shown to be stronger than hafnium–zirconium–oxide (HZO) by measuring polarization versus electric field ( ${P} - {E}$ ) loop. Also, a large sharp peak of capacitance–voltage ( ${C} - {V}$ ) curve is observed in ${C} - {V}$ measurement to confirm the strong negative-capacitance (NC) effect. The fabricated MoS2 NCFET using HZAO as a ferroelectric layer of gate-stack exhibits a significantly reduced subthreshold swing (SS) (17 mV/dec almost over four orders of drain current magnitude, with a minimal SS of 12.8 mV/dec) as compared to its counterpart with the HZO ferroelectric layer (a minimal SS of 38.5 mV/dec). The involved mechanisms lie in that incorporation of Al atoms into the HZO film can form the additional hafnium–aluminum–oxide (HAO) and zirconium–aluminum–oxide with ferroelectricity, and as a result, the formed composite HZAO film can convert more monoclinic phases to orthorhombic phase than the HZO film, leading to stronger ferroelectricity for the former than the latter and, thus, smaller SS for its relevant NCFET.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Design Insights Into Switching Performance of Germanium Source L-Shaped
           Gate Dopingless TFET Based on Cladding Layer Concept

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      Authors: Iman Chahardah Cherik;Saeed Mohammadi;
      Pages: 801 - 805
      Abstract: In this article, a germanium source dopingless tunnel field-effect transistor (TFET) is presented, in which the cladding layer concept is employed to induce a hole layer in the intrinsic germanium source, instead of employing an inductive metal. Utilizing semiconductor–semiconductor junction eliminates the possibility of silicide formation in the source region, and gives us the freedom to modulate the energy bands at the source-channel tunneling junction similar to the conventional dopingless TFETs. The materials and the fabrication steps of our proposed device are CMOS compatible. The DC performance of our proposed device in the presence of quantum confinement effects is completely investigated using a calibrated TCAD simulator. Furthermore, device reliability in the presence of non-idealities such as trap assisted tunneling and ambipolar conduction is evaluated. The considerable achievements such as ${I}_{text {on}} = {7.57} mu text{A}/mu text{m}$ , SS $_{text {avg}} = {18.65}$ mV/dec, and ${I}_{text {on}}/{I}_{text {AMB}} = {8.82} times 10^{{9}}$ , which is close to ${I}_{text {on}}/{I}_{text {off}}$ ratio, show that our device is a notable candidate for digital applications.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Physical Insights Into the Performances of Negative Capacitance Field
           Effect Transistors Using Single-Domain Versus Multidomain Models

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      Authors: Ming-Hao Li;Guan-You He;Qiang Li;Lei-Ying Ying;Bao-Ping Zhang;Zhi-Wei Zheng;
      Pages: 806 - 811
      Abstract: In this study, the performances of negative capacitance field effect transistors (NCFETs) are compared by simulation using single-domain (SD) and multidomain (MD) models. Based on the MD model with the gradient energy coefficient, the ferroelectric (FE) polarization distribution is investigated. The results reveal the correlation among the FE polarization distribution, the NC effect, and the device performances for different device parameters, including the FE thickness ( ${T}_{mathrm{FE}}$ ) and the oxide thickness ( ${T}_{mathrm{OX}}$ ). The FE polarization distribution tends to transform from the SD state into the MD state with the increase of ${T}_{mathrm{FE}}$ and the decrease of ${T}_{mathrm{OX}}$ . The increased ${T}_{mathrm{FE}}$ and decreased ${T}_{mathrm{OX}}$ could result in a more significant distinction in the FE polarization distribution and a further larger difference in the NC effect between the MD state and the conventional SD state for NCFETs. The phenomenon above is confirmed by transient characteristics in NCFETs. More analysis and design space of NCFETs are provided by the study results.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • New Insights of the Switching Process in GeAsTe Ovonic Threshold Switching
           (OTS) Selectors

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      Authors: Zeyu Hu;Weidong Zhang;Robin Degraeve;Daniele Garbin;Zheng Chai;Nishant Saxena;Pedro Freitas;Andrea Fantini;Taras Ravsher;Sergiu Clima;Jian Fu Zhang;Romain Delhougne;Ludovic Goux;Gouri Kar;
      Pages: 812 - 818
      Abstract: Experimental evidence and analysis in this work provide new insights into the fast switching process in GeAsTe ovonic threshold switching (OTS) selectors. For the first time, the full switching- OFF process, covering the defect cluster shrinking and rupture stages, can be measured and characterized. Two distinct switch- OFF mechanisms and their dependence on the total impedance of the selector and resistor (1S1Rs) circuit are identified. The impact of series resistance value on the switching process, the 1S1Rs operation, and the underlying mechanisms can be explained by the dynamic resistance of OTS that is induced by the transition of defect clusters. This research sheds new light on OTS switching mechanism and its impact on 1S1Rs operation.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Low-Power Dynamic Circuit Design With Steep-Switching Hybrid Phase
           Transition FETs (Hyper-FETs)

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      Authors: Md Mazharul Islam;Maria Hernandez Rivero;Garrett Rose;Ahmedullah Aziz;
      Pages: 819 - 825
      Abstract: Dynamic logic circuits suffer from leakage current during their evaluation period causing output voltage degradation. Although the keeper transistor is added to protect the output node from leakage, it comes with a considerable area and power penalty. In this article, we propose a novel design topology of a low-power dynamic logic circuit based on steep-switching hybrid phase transition FETs (Hyper-FETs). A Hyper-FET utilizes a phase transition material that exhibits selective insulator-to-metal transition enabling it to overcome the fundamental Boltzmann’s limit. The characteristic feature of the Hyper-FET also includes a higher ON–OFF ratio than the conventional counterpart. We utilize this unique advantage to alleviate the leakage issue in the dynamic circuits. We use a compact model of the phase transition material calibrated with experimental data of a single crystal VO2. For the baseline transistor, we use the predictive technology model of 14-nm FinFET. We comprehensively analyze the effects of different material parameters to explore the scope of further performance improvement. From our analysis, we deduce a range of insulating and metallic state resistance of the phase transition material (PTM) for optimum performance. We also examine the effect of process variation by performing the Monte Carlo variation analysis. Our analysis indicates that the leakage problem of the dynamic circuits is substantially improved as the phase transition material provides an additional high resistance with the pull-down network. We also observe that our design can outperform the conventional dynamic logic circuit even under random process variation.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Novel High Power Pulsed Mode Operation of Commercial Continuous-Wave
           Magnetron

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      Authors: Yuri Chernousov;
      Pages: 826 - 829
      Abstract: In this article, for the first time, we proposed and studied the operation of industrial 1 kW continuous-wave (CW) S-band magnetrons in a high-power pulsed mode. It turns out that these devices in standard version have a superior pulsed performance: range of stable regulation of pulse power with high efficiency up to 8 kW, pulse duration from $0.3~mu text{s}$ to continuous mode, and repetition rate of at least 1 MHz. The possibility of forming sequences of paired pulses with an adjustable time shift from $1~mu text{s}$ has been demonstrated. The parameters are provided both in the free-running and injection-locking modes. A specialized high-voltage pulse power supply (PPS) with adjustable parameters was designed for measurements. On a passive resistive load, the PPS provides output high voltage of 4.0–5.2 kV, output current up to 3 A in pulse and 0.5 A in average mode, pulse duration from $0.1~mu text{s}$ , pulse edges less than 0.1 $mu text{s}$ , and repetition rate up to 1 MHz. The effect of limiting the pulsed microwave power by emission current was detected for the first time. The investigated CW magnetrons in pulsed mode can be used in microwave technology, accelerator equipment, and for research purposes.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Research on Folded Double-Groove Waveguide With Two Sheet Beams Operating
           on High-Order TE20 Mode for High-Power Terahertz TWT

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      Authors: Yanyan Tian;Guoxiang Shu;Yubin Gong;Huabi Yin;Wenlong He;
      Pages: 830 - 834
      Abstract: In this article, a folded waveguide with two coupling grooves is proposed for high-power and high-frequency traveling wave tubes (TWTs). The structure allows a modified TE20 high-order mode interact with two sheet electron beams. The transmission characteristics of this novel structure were simulated and measured. A good ${S}_{{21}}$ of −10 dB and ${S}_{{11}}$ of less than −15 dB were achieved in the 218–230-GHz range. Moreover, simulations of the beam–wave interaction in this structure predicted an output power of 930 W at 220 GHz, with a small signal gain of 58 dB and a 3-dB bandwidth of 1.3 GHz.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Corrections to “Experimental Study of Adversarial Magnetic Field
           Exposure Attacks on Toggle MRAM Chips”

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      Authors: Supriya Chakraborty;Manan Suri;
      Pages: 835 - 835
      Abstract: In the above article [1], the magnetic field strength mentioned was “700 KGauss.” The occurrence of “K” in the units is an inadvertent, unintentional typographical error. The correct value must be “700 Gauss” in the last sentence of Section III-A and in the captions of Figs. 5–11.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Semiconductor Device Modeling for Circuit and System Design

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      Pages: 836 - 837
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power
           Applications

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      Pages: 838 - 839
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
  • TechRxiv: Share Your Preprint Research with the World!

    • Free pre-print version: Loading...

      Pages: 840 - 840
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Feb. 2023
      Issue No: Vol. 70, No. 2 (2023)
       
 
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