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IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 18  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [228 journals]
  • IEEE Electron Devices Society Information

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • IEEE Transactions on Electron Devices information for authors

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      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
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      Abstract: This page or pages intentionally left blank.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Impact of Back-Gate Biasing on the Transport Properties of 22 nm FD-SOI
           MOSFETs at Cryogenic Temperatures

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      Authors: Fahad Al Mamun;Dragica Vasileska;Ivan Sanchez Esqueda;
      Pages: 5417 - 5423
      Abstract: This article reports on the impact of back gate bias on the transport properties and performance of 22 nm fully depleted silicon-on-insulator (FD-SOI) MOSFETs. FD-SOI MOSFETs were analyzed as a function of back-gate bias from 300 down to 8 K in the context of quasi-ballistic transport. Our analysis revealed a significantly larger effect of back-gate bias on effective channel mobility at cryogenic temperatures compared to 300 K. This is attributed to the more significant contribution from surface roughness and Coulomb scattering at low temperatures. In this context, the application of a back-gate bias shifts the position of the charge carriers away from the top gate oxide/semiconductor interface thereby reducing the impact of scattering. These findings are verified with self-consistent calculations of the charge distribution in the FD-SOI structure using a 1-D Schrödinger–Poisson solver. This work provides new insight on the impact of back-gate biasing on apparent mobility, mean free path, and ballistic ratio in FD-SOI MOSFETs at cryogenic temperatures.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Determination of the Time Constant Distribution of a Defect-Centric
           Time-Dependent Variability Model for Sub-100-nm FETs

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      Authors: P. Saraza-Canflanca;R. Castro-Lopez;E. Roca;J. Martin-Martinez;R. Rodriguez;M. Nafria;F. V. Fernandez;
      Pages: 5424 - 5429
      Abstract: The origin of some time-dependent variability phenomena in FET technologies has been attributed to the charge carrier trapping/detrapping activity of individual defects present in devices. Although some models have been presented to describe these phenomena from the so-called defect-centric perspective, limited attention has been paid to the complex process that goes from the experimental data of the phenomena up to the final construction of the model and all its components, specifically the one that pertains to the time constant distribution. This article presents a detailed strategy aimed at determining the defect time constant distribution, specifically tailored for small area devices, using data obtained from conventional characterization procedures.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Investigation of Transient Two-Stage Thermal Equivalent RC Network of
           SOI-MOSFETs Using Nano Double-Pulse Measurement

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      Authors: Yifan Li;Tao Ni;Juanjuan Wang;Linchun Gao;Xiaojing Li;Jiangjiang Li;Jianhui Bu;Duoli Li;Lida Xu;Runjian Wang;Chuanbin Zeng;Zhijie Wang;Bo Li;Fazhan Zhao;Jiajun Luo;
      Pages: 5430 - 5436
      Abstract: The self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFETs brings challenges to the measurement and modeling of transient electrothermal characteristics. For the first time, this study obtains the transient two-stage thermal equivalent RC network of SOI MOSFETs by nano double-pulse measurement combined with network identification by a deconvolution (NID) method. The two-stage model provides a comprehensive reference for the accumulation of residual heat under dynamic operation. We reveal that since the oxide layer acts as a thermal reservoir, the heat dissipation process can be divided into three phases according to thermal time constants. The results of geometry dependence of thermal parameters show that the gate length and width-to-length ratio ( ${W}/{L}$ ) increase: the thermal resistance trend of both stages decreases, the one-stage thermal time constant increases, but the two-stage thermal time constant decreases. Also, as the scaling of device dimension and mutual thermal coupling, the thermal transient response boosts significantly.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Investigation of Four-Port Characteristic Dependence on Gate Length for
           MOSFETs in the Breakdown Region

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      Authors: Chie-In Lee;Wei-Cheng Lin;Yan-Ting Lin;
      Pages: 5437 - 5442
      Abstract: In this article, gate length-dependent RF four-port characteristics of MOSFETs are investigated in the avalanche regime by using the double feedback and chain rule methods for the first time. The obvious decline of the imaginary part of source input impedance at high drain voltage for short-channel MOSFETs is investigated through the double feedback instead of only the series feedback for the origin of the inductive source impedance. The dominant terms causing the reduction of inductive source impedance due to parallel feedback are determined by this chain rule method. When compared with the conventional analysis due to short-channel effects on the direct-current (DC) characteristics of threshold voltage and substrate current, short-channel MOSFETs resulting in the aspect of RF characteristics are further analyzed by using different gate length MOSFETs. Besides, as gate length reduces, drain-to-source transmission raises significantly in the avalanche regime due to the RF avalanche network according to this analysis. This mechanism results in lower isolation at the breakdown for the shorter gate length MOSFETs. Good agreement of the four-port scattering parameter (S-parameter) between simulation and measurement is obtained for the MOSFETs operating in the both breakdown and saturation regions. The methods can be utilized for other advanced technology nodes and are helpful for the design of RF CMOS amplifiers in the impact ionization region.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Demonstration of Reconfigurable FET and Logic Gates on Epitaxial Lateral
           Overgrowth Silicon Platform

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      Authors: Seong Hyun Lee;Sang Hoon Kim;Sungyeop Jung;Jeong Woo Park;Tae Moon Roh;Wangjoo Lee;Dongwoo Suh;
      Pages: 5443 - 5449
      Abstract: We developed a novel technique, selective epitaxial lateral overgrowth (ELO), to fabricate a local but sufficiently large silicon-on-insulator (SOI) platform on conventional silicon wafers. Based on high-level crystallinity of the local SOI, we implemented reconfigurable FETs with three gates. These FETs demonstrate n- and p-type behavior depending on the applied bias. Not only the reconfigurable FETs but also their logic gates (inverter and NAND) delivered sound performance. Using a compact model based on the surface potential of the channel, we derived the key parameters of the proposed reconfigurable FET and used the model to explain the peculiarities in its working behavior. Owing to the unique advantages of a local SOI, reconfigurable FETs can be seamlessly incorporated into a silicon platform as a building block for CMOS-SOI hybrid electronics.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Carrier Stored Trench-Gate Bipolar Transistor With Stepped Split
           Trench-Gate Structure

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      Authors: Hang Xu;Yafen Yang;Jingjing Tan;Hao Zhu;Qing-Qing Sun;David Wei Zhang;
      Pages: 5450 - 5455
      Abstract: In this work, a stepped split trench-gate (SSG) insulated-gate bipolar transistor (IGBT) employing enhanced carrier storage (CS) technique is proposed. The trench gate is split into two symmetrical gates in a deep trench structure (connected to the emitter). The bottom of the deep trench is embedded into the drift region to reduce the Miller capacitance and improve the breakdown voltage (BV) characteristics simultaneously. Additional arsenic ion implantation is performed during stepped trench formation enabling high doping CS layer. The simulation results show that in comparison with conventional carrier stored trench-gate bipolar transistor (CSTBT), the gate-to-collector charge ( ${Q}_{{mathrm {GC}}}$ ) and ( $E_{text {OFF }}$ ) of the proposed device are decreased by 51.5% and 35.6%, respectively, with a constant conduction voltage drop ( $V_{mathrm{ON}}$ ) of 1.36 V. In addition, an optimized tradeoff between $V_{mathrm{ON}}$ and BV has been achieved. The proposed device shown here can offer an attractive technical approach with compatible manufacturing process toward high-performance power electronics applications.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Analytical V th Modeling for Dual-Gate MOSFETs With Independent Gate
           Control

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      Authors: Soumajit Ghosh;M. Miura-Mattausch;T. Iizuka;Hafizur Rahaman;H. J. Mattausch;
      Pages: 5456 - 5461
      Abstract: We report a study on the threshold voltage ( ${V}_{text{th}}$ ) description for dual-gate MOSFETs with independent gate control, which provides the major contribution for multigate MOSFETs. Specifically, we focus on the understanding of the control mechanisms with two gates, leading to the derivation of an appropriate ${V}_{text{th}}$ description. The results demonstrate that ${g}_{m}$ -linear extrapolation (GMLE) method can extract a ${V}_{text{th}}$ value, which reflects the device physics in the best way. Both front- and back-gate charges are found to induce important contributions to the threshold condition. The newly developed ${V}_{text{th}}$ equation includes only device parameters and accurately predicts ${V}_{text{th}}$ value for any back-gate bias conditions. Based on this ${V}_{text{th}}$ model, a further analytical equation is derived for the situation, where the back-gate charge becomes comparable and starts to exceed the front-gate charge. The independent gate control induces two ${V}_{text{th}}$ values if the back-gate control becomes strong enough in comparison to that of the front gate. It is further shown that the developed model can be applied for device performance optimization to meet circuitry requirements.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Device Parameters Based Analytical Modeling of Ground-Bounce Induced
           Jitter in CMOS Inverters

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      Authors: Vinod Kumar Verma;Jai Narayan Tripathi;
      Pages: 5462 - 5469
      Abstract: This article presents an analytical approach to estimate jitter in CMOS inverters in the presence of ground-bounce noise (GBN). The relationships between output and input, considering the effect of ground noise, are derived in terms of device parameters for modeling the timing variations. The deviation of each transition edge from the ideal transition edge is modeled using analytical equations to obtain peak-to-peak ground noise induced jitter. To examine the proposed modeling, five case studies are considered for covering the time domain as well as frequency domain estimations. The results obtained using the proposed methodology have a close match with those obtained from the simulations using the electronic design automation (EDA) tool. To claim the independence of proposed modeling with respect to a particular technology, the results are verified at 40, 65, and 180 nm technology nodes of United Microelectronics Corporation (UMC).
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Active Thermal Management of GaN-on-SiC HEMT With Embedded Microfluidic
           Cooling

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      Authors: Yuxin Ye;Mei Wu;Yanmei Kong;Ruiwen Liu;Ling Yang;Xuefeng Zheng;Binbin Jiao;Xiaohua Ma;Weimin Bao;Yue Hao;
      Pages: 5470 - 5475
      Abstract: In recent decades, gallium nitride (GaN) high-electron-mobility transistor (HEMT) has become increasingly popular for microwave applications due to its wide bandgap and high saturated electron velocity. However, self-heating inhibits the improvement of its electrical characteristics and reduces device reliability. In this study, a thermoelectric analysis based on embedded microfluidic cooling is performed. By embedding the microchannel into the silicon carbide (SiC) substrate, the coolant can be introduced directly to realize active near junction cooling. According to the thermal resistance model, embedded cooling shortens the thermal path and enhances the capacity of heat convection, and the improvement in the HEMT output characteristics is also verified experimentally. The saturation current increases by 19.5%, and the heat flux of the gates reaches 6349.2 W/mm2 at 70 mL/min, which is 1172% higher than that of traditional remote cooling. The maximum temperature is only 67.4 °C. Therefore, the embedded microfluidic cooling scheme can markedly suppress the self-heating effect and further explore the electrical potential of GaN-based devices.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Electrostatic Engineering of β-Ga2O3 Trench
           Metal–Insulator–Semiconductor Schottky Barrier Diodes Using a Bilayer
           Dielectric Stack

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      Authors: Ravikiran Lengare;Chandan Joishi;Saurabh Lodha;
      Pages: 5476 - 5483
      Abstract: We predict improved electrostatic fields in a $beta $ -Ga2O3trench metal–insulator–semiconductor (MIS) Schottky barrier diode (SBD) by integrating a bilayer dielectric as the insulator layer. The bilayer leverages the benefits offered by a high- ${K}$ /low- ${K}$ dielectric arrangement to obtain lower gate leakage as well as alleviated peak fields compared with a stand-alone dielectric insulator. Through detailed 2-D simulations of geometrically optimized MIS trench SBDs, electrostatic engineering of the bilayer dielectric device is performed to predict better breakdown characteristics and the initiation of impact ionization, which is a measure of the intrinsic capability of the material, at comparatively higher doping of the drift layer, as well as a higher power figure-of-merit (FoM; ≈4 GW/cm2) compared with single-layer dielectric insulators.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • HEMT Average Temperature Determination Utilizing Low-Power Device
           Operation

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      Authors: M. Florovič;J. Kováč;A. Chvála;J. Kováč;J.-C. Jacquet;S. L. Delage;
      Pages: 5484 - 5489
      Abstract: The modified thermal device model was adapted to determine the channel temperature of the AlGaN/GaN HEMT operating under pulsed and quasi-static conditions. The differential analysis of the isothermal and thermal part of the resulting current, as well as ambient temperature variation, is utilized to determine the average channel temperature. Ambient temperature increases in the device operating range is required under low-power operation only, while under high-power operation the thermal stress of the device is significantly reduced due to small ambient temperature variation. In addition, trapping phenomena incorporation is demonstrated to obtain more accurate results utilizing the HEMT threshold voltage shift and transconductance. For experimental verification of the thermal model, Al0.25Ga0.75N/GaN HEMT electrical properties are investigated. Experimentally verified results are in a good agreement with numerical simulations.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Transport and Breakdown Mechanisms of Gate Leakage Current in
           Lattice-Matched In₀.₁₇Al₀.₈₃N/GaN HEMTs

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      Authors: Bingxian Ou;Ning JIn;Yancheng Li;Xiaohong Yan;Jian Xu;Yang Li;Jinping Ao;Dawei Yan;
      Pages: 5490 - 5495
      Abstract: Charge transport and breakdown mecha- nisms of gate leakage current in lattice-matched In0.17Al0.83N/GaN high electron mobility transistors (HEMTs) were investigated by combining the current–voltage ( ${I}-{V}$ ) measurement, the bias-step stress method, and the emission microscopy (EMMI) technique. Based on a refined dislocation model, the detailed dislocation-related charge transport processes were depicted, suggesting an excessive Fowler–Nordheim (FN) tunneling current at high reverse biases. It is further proposed that: 1) at the heterojunction interface, these tunneling electrons will lose the obtained energy by releasing a large number of photons as “hot spots” and phonons as heat and 2) due to a reduced effective bandgap, the breakdown electric field at the dislocation site is significantly decreased compared with the defect-free region, which triggers a premature current breakdown, once the surface electric field is increased to the critical value.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • The Device Instability of p-GaN Gate HEMTs Induced by Self-Heating Effect
           Investigated by on-State Drain Current Injection (DCI) Technique

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      Authors: Jiarui Chen;Yuanzhang Su;Chaowu Pan;Weizhe Kuang;Kai Yang;Haochen Wang;Maojun Wang;Bo Zhang;Qi Zhou;
      Pages: 5496 - 5502
      Abstract: In this work, the device stability of p-GaN gate HEMTs under self-heating effect is comprehensively investigated by the ON-state drain current injection (DCI) technique. By delicately modulating the DCI condition, the devices exhibit different chip temperatures ranging from 40 °C to 150 °C, while the devices show quite distinguishing instability behaviors. Particularly, substantial threshold voltage shift and saturation drain current degradation is constantly observed in the device with severe self-heating effect after DCI stress. Significant ${V}_{text{th}}$ shift of +0.83 V and saturation current reduction up to 18% are observed after the DCI stress, corresponding to a chip temperature of ~150 °C. After the device degradation, the device characteristics show a recoverable dynamic. By investigating the gate leakage current together with the electrothermal device TCAD simulation, ${V}_{text{th}}$ instability induced by the self-heating is revealed to be the electron trapping in the p-GaN gate-stack, while the saturation drain current degradation originates from a composited action of thermally enhanced electron trapping/de-trapping in p-GaN gate-stack as well as the access region at the hot spot close to the source field plate. The results reported in this work suggest that self-heating is a critical issue that may cause unstable operation of p-GaN gate HEMTs. The revealed underlying mechanisms are beneficial for further improving device stability.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Bias-Dependent Conduction-Induced Bimodal Weibull Distribution of the
           Time-Dependent Dielectric Breakdown in GaN MIS-HEMTs

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      Authors: Haozhe Sun;Wen Lei;Jianguo Chen;Yufeng Jin;Maojun Wang;
      Pages: 5503 - 5508
      Abstract: In this article, we investigated the bimodal behavior in the Weibull distribution of time to breakdown during time-dependent dielectric breakdown (TDDB) measurement in GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) with Si3N4 gate insulator. We propose that the gate leakage current is a mixture mechanism of Poole–Frenkel (PF) emission and Fower–Nordheim (FN) tunneling current. The dominant mechanism of devices could shift from PF emission to FN tunneling when the stress bias is above a certain value, which is related to the properties of traps in the gate dielectric. The evolution of the leakage mechanism with stress bias leads to the deviation of the Weibull slope from the original one at low stress bias, where PF emission is the dominant one.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Nonuniform Mechanism for Positive and Negative Bias Stress Instability in
           β-Ga2O3 MOSFET

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      Authors: Zhuolin Jiang;Jie Wei;Yuanjie Lv;Yuxi Wei;Yuangang Wang;Juan Lu;Hongyu Liu;Zhihong Feng;Hong Zhou;Jincheng Zhang;Guangwei Xu;Shibing Long;Xiaorong Luo;
      Pages: 5509 - 5515
      Abstract: In this article, we experimentally study the instability of the key electrical characteristic for the fabricated ${beta }$ -Ga2O3 MOSFET under positive bias stress (PBS) and negative bias stress (NBS), such as threshold voltage ( ${V}_{{mathrm {TH}}}$ ), ON-resistance ( ${R}_{{mathrm {on}}}$ ), subthreshold slope (SS), and hysteresis. An ionized traps model is proposed to explain the instability, which depicts the traps and interfaces states capturing/releasing electrons from the channel. We find nonuniform instability mechanisms. Under the PBS of ${V}_{GS} = 4$ V for 1000 s, the ${V}_{{mathrm {TH}}}$ and ${R}_{{mathrm {on}}}$ are increased by 0.8 V and 19%, respectively. The constant interface state density indicates that this instability is caused by border traps in the gate oxide capturing electrons from channel. For the NBS of ${V}_{GS} = -4$ V for 1000 s, the variation in the ${V}_{{mathrm {TH}}}$ and ${R}_{{mathrm {on}}}$ is −0.54 V and −8.8%, respectively. The instability is attributed to both the border traps and interface states, and the net increase in activated interface states is $2.25times10$ 11 cm−2 extracted from hysteresis. Unlike the PBS- the interface states release electrons to bulk traps, and thus the activated interface state density changes. A good agreement with experimental results shows that the proposed model could accurately describe the instability mechanism under both PBS and NBS. These results provide guidance for identifying defects, optimizing device structure, and fabrication process to improve the reliability of $boldsymbol {beta } $ -Ga2O3 MOSFET.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Difference-Microvariation Solution and Analytical Model for Generic
           HEMTs

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      Authors: Kaoming Chen;Yi Chen;Xiaolin Cen;Xiaoyu Ma;Wanling Deng;Junkai Huang;
      Pages: 5516 - 5521
      Abstract: An analytical dc model of AlGaN/GaN and AlGaAs/GaAs-based high-electron mobility transistors (HEMTs) is proposed, while the charge accumulated in the barrier layer at high gate biases voltage is taken into account. To break through the bottleneck problem of solving model accurately and efficiently, an improved difference-microvariation (DM) explicit algorithm is developed to solve the complex transcendental equations of Fermi level and surface potential in the physical model, including two important subbands in a triangular potential well. Compared with the existing analytical surface potential-based algorithms, the DM algorithm quantifies the high-order component and obtains a more precise solution. The universality and accuracy of the model and DM solutions are verified against numerical results and experimental data under a wide range of operation region, which proves that the model combined with DM method is expected to become the suitable simulation tools for generic heterojunction HEMTs.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • MIS-Based GaN Schottky Barrier Diodes: Interfacial Conditions on the
           Reverse and Forward Properties

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      Authors: Fuping Huang;Zhizhong Wang;Chunshuang Chu;Qianqian Liu;Yongjian Li;Zhen Xin;Yonghui Zhang;Qian Sun;Zi-Hui Zhang;
      Pages: 5522 - 5529
      Abstract: In this work, we have conducted systematic studies on the interfacial conditions for gallium nitride (GaN)-based trench metal/insulator/semiconductor (MIS)-type barrier Schottky rectifier (TMBS) with the help of the T-CAD tools. Our results show that the donor-type traps tend to reduce the Schottky barrier height ( ${q}varphi _{s}$ ), which weakens the charge coupling effect, increases the leakage current, and finally reduces the breakdown voltage (BV). On the contrary, the acceptor-type traps at the contact interface and mesa sidewall will increase ${q}varphi _{s}$ and the turn-on voltage ( ${V}_{mathrm{ON}}$ ) because they can capture electrons in the mesa region and show the negative polarity. This then enhances the electron depletion at the contact interface and the mesa sidewall, resulting in an increase in ${q}varphi _{s}$ and ${V}_{mathrm{ON}}$ . Therefore, this process can increase the reverse blocking characteristics. However, for solving the complicated interfacial conditions in the Schottky contact region, we propose using an MIS structure with a 1-nm Al2O3 insulation layer for the GaN-based TMBS rectifiers. Based on the results, the tunneling process and thermionic-emission (TE) process take into account for the current transport mechanism for the MIS-TMBS rectifiers. Meanwhile, the 1-nm thick Al2O3 interlayer increases the effective Schottky barrier height ( ${q}varphi _{s} + {q}varphi _{T}$ ), which significantly reduces the reverse leakage. In addition, this design offers more freedom in selecting the Schottky contact el-ctrode for the MIS-TMBS rectifier.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Breakdown Mechanism of AlGaN/GaN HEMT on 200-mm Silicon Substrate With
           Silicon Implant-Assisted Contacts

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      Authors: Antoine Chanuel;Yveline Gobil;Chuan Lun Hsu;Matthew Charles;Marianne Coig;Jérôme Biscarrat;François Aussenac;Nicolas Defrance;Christophe Gaquière;Fred Gaillard;Erwan Morvan;
      Pages: 5530 - 5535
      Abstract: We present an access technology suitable for scaled gallium nitride (GaN) high electron mobility transistor (HEMT) in Ka-band. The comparison between OFF-state characteristics of a silicon implant-assisted contact and a conventional recessed Ti/Al-based Ohmic contact is presented. The transistor with source/drain extension by Si implantation has a low contact resistance with ${R}_{C}$ down to $0.4 ~Omega cdot {mathrm {mm}}$ and a sheet resistance of the implanted layer of $67~ Omega $ /sq. In addition to promising contact performance, transistors with source and drain extension sustain high breakdown voltage (BV) with short dimensions for high-frequency applications. The systematic study of gate–source, gate–drain, and gate length variations shows a new breakdown mechanism for implanted access technology with current flowing beneath the channel leading to an unusual correlation between source–drain spacing and BV. With a conventional titanium-alloyed contact, a punchthrough effect is responsible for the BV. Cross-sectional transmission electron microscopy and secondary ion mass spectroscopy (SIMS) characterizations on both wafers highlight a degradation of the AlGaN-based back-barrier and a high silicon concentration deep into the epitaxial stack on the implanted wafers indicating a way to improve BV with an adapted process flow.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Read Optimization Enables Ultralow Resistance Drift for Phase Change
           Memory

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      Authors: Cheng Chen;Xi Li;Chenchen Xie;Houpeng Chen;Siqiu Xu;Zhitang Song;
      Pages: 5536 - 5541
      Abstract: Phase change memory (PCM) has been proven to have unique advantages in embedded applications, mass storage, and in-memory computing areas. To further improve the reliability of data reading for PCM, numerous studies have shown that the spontaneous structural relaxation of the amorphous phase material causes resistance drift and finally affects the reliability. By studying the effect of different read voltages on the resistance stability of PCM cells with various electrode sizes, a read optimization method on low drift property has been presented in this article. The average drift coefficient decreased by one order of magnitude to 0.0034 and, thus, promising higher data reliability of data reading.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Improvement in Short-Channel Effects of the Thin-Film Transistors Using
           Atomic-Layer Deposited In–Ga–Sn–O Channels With Various Channel
           Compositions

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      Authors: Shin-Ho Noh;Hyo-Eun Kim;Jong-Heon Yang;Yong-Hae Kim;Young-Ha Kwon;Nak-Jin Seong;Chi-Sun Hwang;Kyu-Jeong Choi;Sung-Min Yoon;
      Pages: 5542 - 5548
      Abstract: In–Ga–Sn–O (IGTO) thin-film transistors (TFTs) were fabricated with channel lengths from $3 mu text{m}$ to 500 nm to investigate the short-channel effects (SCEs), in which IGTO channel compositions were modulated during the atomic-layer deposition. The SCEs appearing in the IGTO TFTs were found to be manifested by increasing the In/Ga ratio of IGTO channel, showing typical channel composition dependence. Alternatively, small values of the channel-length reduction and contact resistance could be obtained to be 50 nm and 0.52 $text{k}Omega $ , respectively, for the device using the IGTO channel with an In/Ga ratio of 1.7. Threshold voltage shifts of the IGTO TFT were estimated to be only +0.03 and +1.22 V under negative and positive gate-bias stress for 104 s, respectively, even with a channel length as short as $1 mu text{m}$ .
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Improved Stability With Atomic-Layer-Deposited Encapsulation on
           Atomic-Layer In2O3 Transistors by Reliability Characterization

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      Authors: Adam Charnas;Mengwei Si;Zehao Lin;Peide D. Ye;
      Pages: 5549 - 5555
      Abstract: Ultrathin In2O3 and other recently explored low-thermal-budget ultrathin oxide semiconductors have shown great promise for back-end-of-line (BEOL)-compatible logic layers and monolithic 3-D (M3-D) integration. However, the long-term stability and reliability of these defect-rich atomically thin channels have not been intensively explored yet. Here, we present a study of the long-term reliability of transistors with 1.2-nm-thick atomic-layer-deposited (ALD)-grown In2O3 channels by room-temperature positive bias instability (PBI) and negative bias instability (NBI) experiments. The observed behavior can be largely explained by a trap neutrality level (TNL) model. A route to reduce the parameter drift has been developed using encapsulation in sequence with ${V}_{T}$ engineering by an O2 plasma treatment. After treatment, the magnitude of long-term ${V}_{T}$ shift is reduced for both positive and negative gate bias stresses, and for negative bias stress, other transistor parameters are stabilized as well. In all cases, the subthreshold swing (SS) does not change over time, suggesting that stress-induced interface defects form far below the conduction band, if at all.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Bilateral 60-V Amorphous InGaZnO Thin-Film Transistors With Symmetric
           Stair Gate Dielectric

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      Authors: Guangan Yang;Zuoxu Yu;Hao Tian;Tingrui Huang;Yong Xu;Huabin Sun;Weifeng Sun;Wangran Wu;
      Pages: 5556 - 5561
      Abstract: This work implemented bilateral 60-V amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with symmetric stair gate dielectric at the contact sides. The stair gate dielectric lowers the electrical field between the gate and the contacts, enhancing the breakdown voltage ( ${V}_{text {BD}}$ ). The ${V}_{text {BD}}$ was improved from sub-20 to 60 V and a bilateral ${V}_{text {BD}}$ of 60 V was achieved at the total stair length ( ${L}_{text {stair}}$ ) of over $2.9~mu text{m}$ for the proposed device. The transconductance ( ${G}_{m}$ ) degrades with the increasing ${L}_{text {stair}}$ , attributed to the rising equivalent thickness of the stair gate dielectric. The gate-four-probe (GFP) method measurements reveal that the ON-resistance ( ${R}_{ mathrm{scriptscriptstyle ON}}$ ) of the stair gate region has a linear dependence on the ${L}_{text {stair}}$ . The increasing electron concentration in the channel outside the stair region optimizes the output current, as confirmed by the TCAD simulation. The breakdown properties of the devices with a small $L_{text {stair}}$ ( $ < 0.1~mu text{m}$ ) were also simulated. The proposed symmetric stair gate dielectric a-I-ZO TFTs possessed low ${R}_{ mathrm{scriptscriptstyle ON}}$ and high ${V}_{text {BD}}$ at the same time.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Impact of Gate-Dielectric Annealing Temperature on Screening of Remote
           Phonon Scattering in InGaZnO Thin-Film Transistors

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      Authors: Hao Sun;Hui Su;Peter T. Lai;
      Pages: 5562 - 5567
      Abstract: InGaZnO (IGZO) thin-film transistors (TFTs) with NdHfO gate dielectric have been fabricated with different gate-dielectric annealing temperatures (room temperature, 50 °C, 100 °C, 150 °C, 200 °C, 400 °C, and 800 °C) in order to investigate the influence of remote phonon scattering (RPS) generated by the atomic vibration of the gate dielectric on the carrier mobility in the neighboring IGZO channel. Surprisingly, despite having the best gate-dielectric quality, the sample with the highest annealing temperature of 800 °C has the lowest carrier mobility. The reason should lie in its thickest interlayer grown between the gate dielectric and the gate electrode, which results in the largest separation between the gate-electrode holes and the gate-dielectric dipoles and, thus, the weakest screening effect of the former on the RPS on the charge carriers in the IGZO channel.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A New Pixel Circuit With Selectively Synchronized Dual-Gated IGZTO TFTs
           for AMOLED Displays

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      Authors: Jin Her;Won Kyung Min;Chul Sang Shin;Hoon Jeong;Jeong Ki Park;Hyun Jae Kim;
      Pages: 5568 - 5573
      Abstract: We developed an integrated dual-gate-driving thin-film transistor (TFT)-based compensation pixel circuit for active matrix organic light-emitting diode (AMOLED) displays to overcome the limitations of conventional pixel circuits that synchronize in only one direction. Our pixel circuit based on amorphous indium–gallium–zinc–tin oxide TFTs (a-IGZTO TFTs) utilizes selectively synchronized (SLT-Sync) dual-gate-driving TFTs to compensate for threshold voltage ( ${V}_{{mathrm {th}}}$ ) variations and extend the input data range for precise control of emission current. We performed simulations to verify circuit performance and fabricated new and comparable pixel circuits to evaluate the simulation result. The new pixel circuit operates as a gate-synchronized (G-Sync) dual-gate TFT compensating for ${V}_{{mathrm {th}}}$ variation, enabling more accurate and rapid sensing than a source-synchronized (S-Sync) dual-gate TFT. The field-effect mobility ( $mu _{{mathrm {FET}}}$ ) of the new pixel was 1.4-fold than that of the latter dual-gate TFTs operating mode, and the emission current error rate on ${V}_{{mathrm {th}}}$ variation (±0.5 V) was < 5.0%. The new pixel circuit behaved as an S-Sync dual-gate TFT during emission. The input data range is about 0.6 V greater than that of a G-Sync dual-gate TFT, due to the twofold increase in subthreshold swing (SS). Therefore, the new pixel circuit optimally balances fast ${V}_{{mathrm {th}}}$ compensation and input data range expansion, and will find application- in high-resolution AMOLED displays by applying the SLT-Sync dual-gate TFTs, which operate in G-Sync and S-Sync modes as needed.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • An Artificial Neural Network Implemented Using Parallel Dual-Gate
           Thin-Film Transistors

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      Authors: Yushen Hu;Tengteng Lei;Yuqi Wang;Fei Wang;Man Wong;
      Pages: 5574 - 5579
      Abstract: Implementing in-memory computation, an artificial neural network (ANN) consisting of thin-film transistors (TFTs) monolithically integrated in each unit of an array of capacitors is constructed. Both single-gate and parallel, dual-gate (DG) TFTs are deployed. The capacitors and the DG TFTs serve as the respective memory and computational elements. The DG TFT offers the capability of amplifying a weak but relevant input signal and suppressing a strong but irrelevant input signal across a synaptic gap, and the storage of charge on the capacitor is pseudostatic because of the exceptionally low OFF-state leakage current of the accompanying address TFT built on a metal–oxide semiconductor. The feasibility of such an ANN is demonstrated using a $4times6$ array for classifying a specific set of Tetris patterns.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Enhancing Optical Performance for White Light-Emitting Diodes Using
           Quantum- Dots/Boron Nitride Hybrid Reflective Structure

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      Authors: Zhaoshu Cai;Guanwei Liang;Yunlong Zhang;Caiman Yan;Yaoxing Song;Jiasheng Li;Zongtao Li;
      Pages: 5580 - 5589
      Abstract: Quantum dots (QDs) are usually used with phosphor to obtain white light-emitting diodes (WLEDs) due to their excellent lighting characteristics. For lighting effect improvement, the QDs layer and the phosphor layer are supposed to be separated to reduce reabsorption loss and enhance QDs stability. Based on the separated structure, a QDs/boron nitride hybrid reflective (QBHR) structure is proposed to enhance the optical performance of WLEDs in this study. QDs were electrostatically bonded on the boron nitride (BN) pellets and their composite particles were subsequently mixed with silicone for LED encapsulation by a spinning-coated process. It could be easily managed the performance of QBHR structure by controlling the composite particles’ concentration or centrifugal speed. The diffuse reflectance and photoluminescence (PL) intensity of QBHR structure with various thicknesses were analyzed. While applying with remote phosphor layer for WLEDs, the luminous efficacy of devices with QBHR structure increases with phosphor concentration, which are larger than that of QD/polydimethylsiloxane (QP) structures. It may be caused by the light extraction ability of the scattering BN particles and high color conversion efficiency (CCE) of QBHR structure. Finally, under the same correlated color temperature (CCT) of 3640 K, the luminous efficacy and CCE enhance by 14.2% and 19.5% using the QBHR structure, respectively. In addition, the QBHR structure shows better stability than the QP structure after aging for 387.75 h. In brief, the QBHR structure shows an effective and practical packaging method to produce high-performance WLEDs.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Sensitive UV Photodetector Based on Non-Wide Bandgap MAPbBr3
           Nanosheet

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      Authors: Ming-Ming Liu;Liang-Liang Zhou;Shi-Fu Li;Feng-Xia Liang;Yue Xing;Jing-Yue Li;Can Fu;Yao-Zu Zhao;Di Wu;Lin-Bao Luo;
      Pages: 5590 - 5594
      Abstract: A sensitive ultraviolet photodetector (UVPD) based on an ultrathin MAPbBr3 nanosheet was developed in this study. A simulation based on technology computer-aided design showed that the optical absorption of MAPbBr3 can be tailored by changing the material thickness, which is reasonable considering the wavelength dependence of the absorption coefficient of MAPbBr3. In addition, an apparent blueshift of the position of the maximum photocurrent is observed upon decreasing the nanosheet thickness. These tunable optoelectronic properties resulted in a device fabricated from medium-bandgap 43-nm-thick MAPbBr3 nanosheets being sensitive to UV light illumination. The device has a maximum photoresponse at 300 nm, a responsivity of 27.2 mA $cdot text{W}$ −1, and a response speed of 0.103/0.087 s, respectively, which are comparable to conventional UVPDs based on low-dimensional wide bandgap materials (e.g., ZnO and TiO2). This novel UVPD has application potential to optoelectronic systems.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Synergetic Effect of Photoconductive Gain and Persistent Photocurrent in a
           High-Photoresponse Ga2O3 Deep-Ultraviolet Photodetector

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      Authors: Zeng Liu;Ling Du;Shao-Hui Zhang;Lei Li;Zhao-Ying Xi;Jin-Cheng Tang;Jun-Peng Fang;Mao-Lin Zhang;Li-Li Yang;Shan Li;Pei-Gang Li;Yu-Feng Guo;Wei-Hua Tang;
      Pages: 5595 - 5602
      Abstract: In this work, a metal–semiconductor–metal (MSM) $beta $ -gallium oxide (Ga2O3) photodetector (PD) was constructed by microprocessing techniques, including UV photolithography, liftoff, and ion beam sputtering. The $beta $ -Ga2O3 thin film was deposited on a sapphire substrate by a metalorganic chemical vapor deposition method. In addition to the high-quality thin film, the PD showed a photo-to-dark current ratio of $3.5,,{times },,10$ 7, a photoresponsivity of 509.78 A/W, a specific detectivity of $8.79,,{times },,10$ 14 Jones, an external quantum efficiency (EQE) of $2.5,,{times },,10$ 5%, and a linear dynamic range of 94.41 dB at 10 V with 254-nm UV light illumination. The PD photoconductive gain decreases with the incident light intensity and reaches up to 2490 under $2000 ~mu text{W}$ cm−2. Such high photoconductive gain due to recycling transport in the active layer may lead to persistent photocurrent. Together with high photoresponsivity and EQE, the substantial internal gain may well exist in the $beta $ -Ga2O3 PD, suggesting a high deep-ultraviolet photoresponse for the $beta $ -Ga2O3 MSM photodetector in this article.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Analytical Model of the Vertical Pinned Photodiode

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      Authors: Jiwon Lee;Edward van Sieleghem;Hyunwoo Kim;Jan Genoe;
      Pages: 5603 - 5606
      Abstract: This article presents a simple analytical model of the vertical pinned photodiode (PPD). In the existing pixels with relatively large sizes, the photodiode is formed byp+-n-p doping in a planar manner, and thus the vertical electric field determines the potential of the photodiode. However, as the pixel size becomes smaller, the size of the photodiode also decreases. Accordingly, the influence of the doping concentration in the periphery becomes larger and the pinning voltage is eventually predominantly determined by the horizontal electric field in the submicrometer region. In this case, the analytical model describing the conventional photodiode structure is no longer applicable. Therefore, in this article, a simple analytical model applicable to a small pixel size is provided and verified through TCAD simulation. It is thought that the proposed simple model helps understand the potential of small pixel size and provides a major starting point for design.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Opto-Thermal Performances Investigation of High-Power WLEDs With Different
           Reflective Dams

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      Authors: Zhenyu Lei;Jinglong Liu;Yun Mou;Jiaxin Liu;Yang Peng;Mingxiang Chen;
      Pages: 5607 - 5611
      Abstract: Reflective dam is a common structure in white light-emitting diodes (WLEDs) packaging due to its advantages of light regulation, heat conduction, and enhanced packaging efficiency. In this work, the opto-thermal performances of high-power WLEDs with different reflective dams were investigated. The dichromatic light is closest to the natural white light when the phosphor concentration was set at 7 wt% from 5 to 12 wt%. As the WLED modules with different dam materials (Cu, Al, and Al2O3 ceramic) were fabricated and compared, the results showed that the WLED with Al2O3 reflective dam presents higher luminous efficiency (LE) of 132.37 lm/W and lower correlated color temperature (CCT) of 5633 K at a driving current of 350 mA. Besides, the Al2O3 reflective dam has a high reflectance of 95.2% from 400 to 800 nm. In addition, in the test of thermal performance, the stable temperature of the WLED module packaged with the Cu reflective dam is 162 °C at the current of 2000 mA, which shows lower surface temperature and displays better heat dissipation performance than the Al dam and the Al2O3 ceramic dam.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A SiGe/Si Phototransistor With High FOM of Gain*VA Using 0.35-μm BiCMOS
           Technology

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      Authors: Hongyun Xie;Yang Xiang;Yin Sha;Ruilang Ji;Fu Zhu;Xiaoting Shen;Dong Han;Xiaoxiong Yang;Wanrong Zhang;
      Pages: 5612 - 5617
      Abstract: A novel SiGe/Si phototransistor with high figure of merit (FOM) of gain*early voltage for optical communication was designed and fabricated in a standard 0.35- $mu text{m}$ BiCMOS process. A compound base consisting of a P-Si layer and a P+-SiGe layer was designed to achieve a good optical response through relieving the negative influence induced by doped ion’s mutual diffusion in device fabrication. The fabricated surface-illuminated SiGe/Si heterojunction phototransistor (HPT) was measured under 850-nm incident light with a variety of optical powers at 1-V collector bias. When the incident optical power was $2.29~mu text{W}$ , the collector current reached $4.45~mu text{A}$ . The maximum gain exceeded 6.925 with the dark current of about 100 pA. The FOM of gain*early voltage of the proposed SiGe/Si HPT can achieve 100.97. Its optical DC and RF responses under high light power were analyzed with a physically based simulation model, which considered the process effects of device fabrication detailed. The optical gain may promote to 13.3 but with the deteriorated output performance and a smaller early voltage. The maximum optical characteristic frequency may reach 17.6 GHz.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Detailed Study on the Role of Nature and Distribution of Pinholes and
           Oxide Layer on the Performance of Tunnel Oxide Passivated Contact (TOPCon)
           Solar Cell

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      Authors: Sourav Sadhukhan;Shiladitya Acharya;Tamalika Panda;Nabin Chandra Mandal;Sukanta Bose;Anupam Nandi;Gourab Das;Susanta Chakraborty;Santanu Maity;Partha Chaudhuri;Hiranmay Saha;
      Pages: 5618 - 5623
      Abstract: Industrial silicon solar cells are now mostly based on aluminum back surface field (Al-BSF) or passivated emitter rear cell (PERC) technologies on p-type crystalline silicon wafers. Recently tunnel oxide passivated contact (TOPCon) solar cell on p-type Si wafers has attracted attention due to its demonstrated higher efficiency than either Al-BSF or PERC type solar cell. Numerical analysis using 3-D Sentaurus Technology Computer Aided Design (3-D-TCAD) software leads to the enhancement of the efficiency of the p- and n-type TOPCon solar cells by optimizing the size, nature, and number density of pinholes in the oxide layer; thickness of the oxide layer with and without pinholes and B doping concentration in the hole selective p+ poly-Si layer at the rear. Effects of both types of pinholes, either completely through (physical contact) or partially through (localized thinner oxide), are studied on cell performance. Simulation results show that pinholes in tunnel oxide have an advantage in lowering of series resistance and improvement of fill factor. To achieve optimum performance, the size, nature, and number density of pinholes and thickness of the oxide layer should be optimized. Considering both types of pinholes, the efficiency achieved is 25.3% for p-TOPCon and 26% for n-TOPCon. Also, the outputs of simulated p-TOPCon are compared with simulated p-PERC solar cell. The analysis shows that TOPCon solar cell on p-type wafer has significant ability to be adopted for industrial production.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Validation of Mazhari’s Equivalent Circuit Model for Perovskites Solar
           Cells With S-Shaped J–V Curves

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      Authors: José Carlos Pérez-Martínez;Diego Martín-Martín;Gonzalo del Pozo;Belén Arredondo;Enrique Hernández-Balaguera;Beatriz Romero;
      Pages: 5624 - 5629
      Abstract: The appearance of kinks in the fourth quadrant of current–voltage curves decreases dramatically the efficiency of photovoltaic solar cells (SCs). These S-shaped ${J}$ – ${V}$ curves have been successfully reproduced using different lumped-parameter equivalent circuits, composed of two or more diodes. In this work, Mazhari’s three-diode equivalent circuit is used to model the S-shaped ${J}$ – ${V}$ curves of perovskite SCs numerically simulated with Silvaco ATLAS TCAD. The simulated cell structure is fluorine-doped tin oxide (FTO)/TiO2/MAPbI3/ 2, $2^{prime}$ ,7, $7^{prime}$ -tetrakis [N,N-di (4-methoxyphenyl) amino]-9, $9^{prime}$ -spirobifluorene (Spiro-OMeTAD)/Au and, in order to reproduce ${J}$ – ${V}$ curves with a kink, perovskite carrier mobility has been decreased below 0.25 cm2/(V $cdot $ s) and defect density in the active layer has been increased above $1times 10^{{14}}$ cm $^{-{3}}$ . For each parameter, ${J}$ – ${V}$ curves have been simulated for different AM1.5 irradiation levels, from dark conditions up to 2 suns. For each device, a set of circuital parameters has been obtained independent of irradiation level. The dependence of Mazhari’s circuit parameters on both carrier mobility and defect density will be discussed.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Transfer Printed, Vertical GaN-on-Silicon Micro-LED Arrays With
           Individually Addressable Cathodes

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      Authors: Changhao Li;Zhangxu Pan;Chan Guo;Yuzhi Li;Yue Zhou;Jiantai Wang;Shenghan Zou;Zheng Gong;
      Pages: 5630 - 5636
      Abstract: Microscale light-emitting diodes (Micro-LEDs) have attracted intensive research attention due to their potential applications in high-resolution displays, wearables, and VR/AR headsets. However, their device performance can be compromised by the common Micro-LED lateral structure, usually with both two electrodes facing toward the p-side. Here, we developed printable, silicon-based vertical Micro-LEDs with two electrodes facing oppositely, which showed better heat dissipation, and were 60% brighter over conventional lateral Micro-LEDs. We further developed a novel double-tape-assisted transfer process, which allowed these vertical Micro-LEDs to be transferred completely to a polyimide tape in a simple yet reliable manner. Combined with a bonding scheme based on low-melting-point-patterned indium alloys, these printed Micro-LEDs on the tape can be further integrated onto silicon backplanes with a shared p-contact. Followed by forming an individual n-electrode connected to each pixel, a novel-inverted, vertical microdisplay prototype device with individually addressing cathodes was demonstrated for the first time.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Analytical Modeling of Potential Barrier for Charge Transfer in Pinned
           Photodiode CMOS Image Sensors

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      Authors: Lu Liu;Yang Guo;Binkang Li;Shaohua Yang;Ming Yan;Errui Zhou;Mingan Guo;Gang Li;
      Pages: 5637 - 5643
      Abstract: A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • The Mechanism of Performance Variations in MoS2 Vertical Schottky
           Metal–Semiconductor Photodiode Based on Thermionic Emission Theory

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      Authors: Xisai Zhang;Xinpei Duan;Wencheng Niu;Xingqiang Liu;Xuming Zou;Hao Huang;Dinusha Herath Mudiyanselage;Houqiang Fu;Bei Jiang;Guoxia Liu;Zhenyu Yang;
      Pages: 5644 - 5648
      Abstract: Atomically thin 2-D semiconductors are widely used to build various novel photodiodes due to their appropriate band structure and dangling-bond-free surface. These emerging 2-D photodiodes have shown excellent performance, especially in responsivity. Here, we report a Schottky metal–semiconductor photodiode with an ultrashort molybdenum disulfide (MoS2) channel constructed by a vertical structure. The device showed excellent rectification and optical response characteristics due to the large Schottky barrier height ( $text{q}varphi _{text{SB}}$ ) through the physical transfer method to get rid of the Fermi-level pinning effect. In addition, the vertical structure dramatically reduces the channel length to the atomic scale and efficiently collects excited carriers with little recombination loss. Furthermore, the responsivity in those photodiodes is often associated with the light intensity and voltage bias. The thermionic emission theory was employed to explain the impacts of light intensity and voltage bias on the photodiode responsivity. This work can not only improve our fundamental understanding of the photovoltaic and photoconductive effects of 2-D semiconductors but also serve as an important reference for comparing and analyzing photodetectors based on 2-D semiconductors.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Effect of Dynamic Threshold-Voltage Instability on Dynamic ON-State
           Resistance in SiC MOSFETs

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      Authors: Aivars J. Lelis;Damian P. Urciuoli;Erik S. Schroen;Daniel B. Habersat;Ronald Green;
      Pages: 5649 - 5655
      Abstract: This work presents an investigation of several important phenomena related to threshold-voltage instability in SiC MOSFETs. Such instability can occur in previously unstressed as-processed devices, including trench-geometry devices, when exposed to a negative gate-bias overstress. This work also reports, for the first time for SiC MOSFETs, on the dynamic nature of ON resistance in the presence of large threshold-voltage instabilities, whether occurring in as-processed devices or due to an ac stress-induced degradation.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Defect Engineering at the Al2O3/(010) β-Ga2O3 Interface via Surface
           Treatments and Forming Gas Post-Deposition Anneals

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      Authors: Ahmad Ehteshamul Islam;Chenyu Zhang;Kursti DeLello;David A. Muller;Kevin D. Leedy;Sabyasachi Ganguli;Neil A. Moser;Rachel Kahler;Jeremiah C. Williams;Daniel M. Dryden;Stephen Tetlak;Kyle J. Liddy;Andrew J. Green;Kelson D. Chabak;
      Pages: 5656 - 5663
      Abstract: High-quality dielectrics with a low defect density at the dielectric/semiconductor interface are essential for the application of $beta $ -Ga2O3 in the next-generation power electronic devices. In this article, we demonstrate a method for reducing defect density at the Al2O3/(010) $beta $ -Ga2O3 interface, where metal–oxide–semiconductor capacitors (MOSCAPs) were fabricated by depositing Al2O3 on the surface of (010) $beta $ -Ga2O3 treated sequentially with piranha and buffered hydrofluoric (HF) acid. The devices also went through a post- dielectric deposition anneal (PDA) in a forming gas ambient (FG-PDA). The fabricated devices were then characterized using current–voltage and capacitance–voltage ( ${C}$ – ${V}$ ) measurements. The quality of Al2O3 films and surfaces was also characterized using cross-sectional transmission electron microscopy (TEM), ellipsometry, and atomic force microscopy (AFM). Electrical measurements suggested low hysteresis, consistent flat-band voltage, and excellent accumulation for MOSCAPs with an interface defect density ${D} _{{mathrm {IT}}} < 10$ 12 cm−2 $cdot $ eV−1 characterized using conductance and photo-assisted ${C}$ – ${V}$ (PC-) methods. In some devices, PCV method created additional ${D} _{{mathrm {IT}}}$ during characterization. Measured leakage current through Al2O3 until its breakdown was explained using a modified space-charge-limited conduction model. Control samples prepared without (or with limited) surface treatments and without forming gas PDA revealed the importance of different process components for reducing ${D} _{{mathrm {IT}}}$ . TEM images revealed interfacial crystallization as the origin of higher defect densities in the control samples.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Flip-Chip AlGaN/GaN Schottky Barrier Diode Using Buried-Ohmic Anode
           Structure With Robust Surge Current Ruggedness and Transient Energy
           Sustaining Capability

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      Authors: Feng Zhou;Weizong Xu;Yulei Jin;Tianyang Zhou;Fangfang Ren;Dong Zhou;Dunjun Chen;Rong Zhang;Youdou Zheng;Hai Lu;
      Pages: 5664 - 5670
      Abstract: Robust reliability is essential for electronic devices against inductive transient shocks in power switching applications. In this work, rugged surge current tolerance and transient energy sustaining capability are simultaneously demonstrated in AlGaN/GaN Schottky barrier diodes (SBDs) for the first time, which greatly fills the research gap toward the device reliability requirements for inductive switching applications. Such robustness is attributed to the combined advantages of the uniquely designed buried-ohmic anode structure and efficient thermal management enabled by substrate thinning and flip-chip packaging techniques. The resultant device exhibits a high surge current density of 3.4 kA/cm2 (42 A) and a critical transient dissipating energy density of 1.5 J/cm2 (18.6 mJ). All these values are the highest reported in AlGaN/GaN SBDs. In particular, the superior switching performance with nanosecond reverse recovery time is achieved under a 400-V operating condition with a fast di/dt of 200 A/ $mu text{s}$ , implying the desired functionality of the proposed device architecture. This work, thus, makes a significant step in reaching the promise of AlGaN/GaN SBDs for high-reliability and high-power applications.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Unclamped Inductive Switching Robustness of SiC Devices With
           Parallel-Connected Varistor

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      Authors: Wataru Saito;Zaiqi Lou;Shin-Ichi NIshizawa;
      Pages: 5671 - 5677
      Abstract: Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3–6 times higher for planar MOSFETs and 5–10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Performance Evaluation of W-C Alloy Schottky Contact for 4H-SiC Diodes

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      Authors: Ying Wang;Ke-Han Chen;Meng-Tian Bao;Xin-Xing Fei;Fei Cao;
      Pages: 5678 - 5682
      Abstract: In this article, we investigate Schottky diodes with pure W and W-C alloy metal electrodes. The electrical characteristics of samples were analyzed by comparing the current density–voltage ( ${J} - {V}$ ) and capacitance–voltage ( ${C} - {V}$ ) curves at different annealing temperatures from 400 °C to 900 °C. The ideality factor of W-C alloy diodes annealed at 400 °C was 1.162. When W-C alloy diodes were annealed at 500 °C–900 °C, the range of $emptyset _{B}^{I-{V}}$ was merely 0.08 eV, the ideality factors were below 1.15, and the difference between $emptyset _{B}^{I-{V}}$ and $emptyset _{B}^{C-{V}}$ was smaller compared to the pure W diodes. For W-C alloy diodes annealed at 500 °C, the barrier height fluctuated only slightly, and the leakage current was suppressed effectively as the operating temperature increased. These results show that the new structure has better electrical characteristics and thermal stability. Meanwhile, transmission electron microscope (TEM) and energy-dispersive X-ray (EDX) images also verify that W-C alloy diodes reduce the interface reaction between the metal and silicon carbide (SiC), which improves the barrier inhomogeneity of W-based Schottky diodes effectively.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Demonstration of a 10-kV Class Waffle-Substrate n-Channel IGBT in 4H-SiC

    • Free pre-print version: Loading...

      Authors: Monzurul Alam;Noah Opondo;Dallas T. Morisette;James A. Cooper;
      Pages: 5683 - 5688
      Abstract: The silicon carbide (SiC) waffle-substrate ${n}$ -channel insulated gate bipolar transistor (IGBT) is a vertical IGBT designed to operate at blocking voltages below about 15 kV. At these voltages, the drift and anode layers are too thin to allow complete removal of the ${n}^{+}$ substrate. Instead, a waffle pattern is etched through the substrate to expose the buried anode layer while preserving the structural integrity of the wafer. The feasibility of this approach is demonstrated by fabricating a 10-kV class ${n}$ -channel IGBT with a differential specific ON-resistance of 160 $text{m}Omega cdot text{cm}^{2}$ .
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Reliable Device Parameter Extraction Scheme for Physics-Based IGBT
           Models

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      Authors: Yifei Ding;Xin Yang;Guoyou Liu;
      Pages: 5689 - 5697
      Abstract: The physics-based IGBT models have been proved to be very effective in accurately simulating the voltage, current, and carrier dynamics. However, the biggest challenge for those promising models is lack of detailed IGBT device parameters, which chip manufacturers generally seldom reveal. To extract precise and robust device parameters, a novel parameter extraction scheme based on the particle swarm optimization (PSO) algorithm is proposed in this article. The state-of-the-art Fourier-series-based (FSB) IGBT model is used to ensure the accuracy of the parameter extraction scheme. In the proposed scheme, IGBT parameters are simultaneously extracted by IGBT static and dynamic characteristic curves to account for global interaction between all those IGBT parameters during parameter optimization. The experiment is carried out to verify the proposed parameter extraction scheme. It should be noteworthy that only an experimental switching waveform under an arbitrary operating condition is required to implement global searching for the optimal parameters by our proposed scheme. The output characteristic curves and the switching waveforms of the FSB model under different operating conditions using the proposed parameter extraction scheme are in good agreement with the experimental waveforms. Results confirm the effectiveness and usefulness of the obtained device parameters by the randomly selected operating condition. Finally, the global sensitivity analysis is introduced to further demonstrate the reliability of the proposed parameter extraction scheme.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Two-Dimensional Model for the Field-Plate Design of High-Voltage
           Transistor

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      Authors: Jian-Hsing Lee;Chih-Cherng Liao;Ching-Kuei Shih;Karuna Nidhi;Ching-Ho Li;Chun-Chih Chen;Kai-Chuan Kan;Ke-Horng Chen;
      Pages: 5698 - 5704
      Abstract: The field plate (FP) is a widely adopted concept and has been commonly used for high-voltage (HV) transistors to increase the breakdown voltage without enlarging the device dimension. In this article, a 2-D mathematical equation is derived for the FP design of HV transistors which reveals the potential and the electric field distributions in the reduced-surface field (RESURF) region. From the derived mathematical model, the mechanism of the FP-induced electric field suppression for the HV transistors is completely explained as the FP can reduce the potential gradient ( ${E} = -nabla varphi $ ) caused by the dielectric thickness differences above the RESURF region. The potential and the electric field distributions of the RESURF region will change as the FP is inserted due to the dielectric thickness variations. The derived equations also explained the capacitive behaviors and quantitatively described the potential and electric field distributions in different configurations of the FP-assisted RESURF devices. The results obtained by the derived equation are found to be very much accurate compared with technology computer-aided design (TCAD) simulation results.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Parasitic Oscillation Analysis of Trench IGBT During Short-Circuit Type II
           Using TCAD-Based Signal Flow Graph Model

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      Authors: Hiroshi Kono;Ichiro Omura;
      Pages: 5705 - 5712
      Abstract: The oscillation phenomenon of trench-type insulated gate bipolar transistors during short-circuit (SC) type II was investigated experimentally and theoretically. The gate resistance required to suppress oscillations decreased with an increasing collector voltage. The oscillation conditions were calculated from the signal flow graph model using the ${S}$ -parameter based on a technology computer-aided design simulation. The calculation results reproduced the locus of the collector voltage dependence of the experimentally measured gate resistance. The oscillation mechanism was investigated using the device simulation. The response of carrier density modulation at the base-drift layer boundary was found to transmit to the collector side through the electron–hole plasma region during the oscillation, indicating that the transfer characteristics of the carrier density modulation in the drift region at the specific collector voltage influence the collector voltage dependence of the SC oscillation. The influence of circuit parameters on the oscillation was also investigated. An increase in the emitter inductance suppressed the oscillations, whereas an increase in gate inductance increases oscillations.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage
           FlexRay Applications

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      Authors: Chen-Wei Hsu;Yu-Hsin Li;Ming-Dou Ker;
      Pages: 5713 - 5721
      Abstract: The I/O of CMOS integrated circuits of for FlexRay communication has to be tolerant with the input signals of ±60 V in its normal applications. Thus, the on-chip electrostatic discharge (ESD) protection devices for such I/O pin must be kept off unless the bus voltage is higher than 60 V or lower than −60 V. In this work, the bi-directional p-n-p (Bi-PNP) device was proposed and optimized for bi-directional ESD protection in the FlexRay communication systems. The proposed Bi-PNP devices were verified in a 0.15- $mu text{m}$ BCD technology. The relationships between the layout spacing of doping layers and other device characteristics, including trigger voltage (Vt1) and breakdown voltage (BV), were investigated, respectively. The size dependence on the ESD robustness was also studied. The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were estimated. Finally, the recommended size and parameters of the proposed Bi-PNP device for ±60 V FlexRay application are provided.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Optimization of NiO/β-Ga2O3 Heterojunction Diodes for High-Power
           Application

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      Authors: Chao Liao;Xing Lu;Tongling Xu;Paiwen Fang;Yuxin Deng;Haoxun Luo;Zhisheng Wu;Zimin Chen;Jun Liang;Yanli Pei;Gang Wang;
      Pages: 5722 - 5727
      Abstract: This work presents the optimization of a NiO/ $beta $ -Ga2O3 heterojunction diode (HJD) by adjusting the structural parameters of the NiO layer. A rapid thermal annealing (RTA) process was utilized to modulate the hole concentration of the sputtered NiO. The influence of the NiO layer geometry and its hole concentration on the HJDs’ electrical properties has been thoroughly investigated and discussed based on both the experimental study and the technology computer-aided design (TCAD) simulation. It was found that the forward current of the HJDs was mainly determined by the size of the anode electrode regardless of the NiO layer dimension, indicating the poor current spreading within the NiO film. Enlarging the NiO layer dimension with a fixed anode or adjusting the hole concentration to an optimal value could benefit the device breakdown voltage ( ${V}_{B}$ ) by reducing the electric field crowding effect. An optimum value of ${sim }2,, {}times {} 10^{17}$ cm−3 was determined for the HJDs with a drift layer doping concentration of $1.8,, {}times {}10^{16}$ cm−3. To achieve a good balance between ${V}_{B}$ and the specific ON-resistance ( ${R}_{{mathrm {ON,sp}}}$ ), a double-layer structure ( $text{p}^{+}$ NiO/ $text{p}^{-}$ NiO) was adopted and optimized, yielding a greatly enhanced performance in the NiO/ $beta $ -Ga2O3 HJDs. The results provided a useful insight into the $text{p}^{-}$ NiO-related $beta $ -Ga2O3 power device design.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Accumulation-Mode Device: Experimental of LDMOS With Folded Drift Region
           Achieving Ultralow Specific ON Resistance

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      Authors: Baoxing Duan;Ziyu Zhou;Yandong Wang;Yintang Yang;
      Pages: 5728 - 5732
      Abstract: In order to reduce the specific ON resistance ( $text{R}_{mathbf {{ mathrm{scriptscriptstyle ON}},sp}}$ ) of power device in the drift region, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is manufactured and analyzed in this article. The drift region of the FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The oxide inside the trench optimizes the electric field in the drift region, so the doping concentration can be increased while maintaining the breakdown voltage (BV). In addition, the trench increases the area of the drift region covered by the extended gate electrode, which can introduce more accumulated electrons when the device is turned on. The increased doping concentration and accumulated electrons work together to substantially increase the conductivity of the drift region, thereby obtaining ultralow $text{R}_{ mathrm{scriptscriptstyle ON},sp}$ . Furthermore, the folded accumulation LDMOS with split gate (FSLDMOS) is proposed to solve the phenomenon that the BV of the FALDMOS cannot be improved by increasing the drift length with the fixed oxide thickness. The polysilicon above the drift region is etched apart to form an extended gate and a split electrode. The electric field concentration near the drain can be alleviated by adjusting the bias on the split electrode. The FALDMOS and FSLDMOS are manufactured by the 0.35- $mu text{m}$ BCD technology and the key processes, such as trench etching and polysilicon filling, are shown. The experimental results show that $text{R}_{ mathrm{scriptscriptstyle ON},sp}$ of the FALDMOS is only 9.3 $text{m}Omega cdot $ mm2, while that the conventional LDMOS is 36.2 $text{m}Omega cdot $ mm2, which is reduced by 74.3% with the same BV of 36 V. Moreover, the current density of FALDMOS is five times higher than that of the conventional LDMOS in the same areas. The BV of the FSLDMOS is improved by 66% compared with FALDMOS.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Degradation Behavior and Mechanism of GaN HEMTs With P-Type Gate in the
           Third Quadrant Under Repetitive Surge Current Stress

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      Authors: Xiaoming Wang;Wanjun Chen;Ruize Sun;Chao Liu;Yun Xia;Yajie Xin;Xiaorui Xu;Fangzhou Wang;Xinghuan Chen;Yiqiang Chen;Bo Zhang;
      Pages: 5733 - 5741
      Abstract: In this article, the degradation behavior and mechanism of GaN high-electron-mobility transistors (HEMTs) with p-type gate in the third quadrant under repetitive surge current stress are studied. The electrical properties of devices under various surge current conditions are investigated. It can be found that the turning point exists in the degradation trend of threshold voltage ( ${V}_{text{TH}}$ ), gate leakage current ( ${I}_{text{gss}}$ ), and OFF-state drain leakage current ( ${I}_{text{dss}}$ ). The turning phenomenon is related to the peak value of the surge current ( ${I}_{text{peak}}$ ) and the stress cycle. We propose that two competing mechanisms that take place on carrier transport paths cause the degradation behavior. When ${I}_{text{peak}}$ is low, the electron trapping effect is the main degradation mechanism. As ${I}_{text{peak}}$ exceeds a certain value, as the stress cycle increases, the hole trapping effect will be greatly enhanced and even cause the reversal of the degradation rate of ${V}_{text{TH}}$ , ${I}_{text{gss}}$ , and ${I}_{text{dss}}$ . Furthermore, at higher ${I}_{text{peak}}$ , new donor traps can be generated in the gate, causing the permanent and negative shift of ${V}_{tex-{TH}}$ . Based on the simulation, further experiments, and ${V}_{text{TH}}$ recovery characteristics, the competing mechanism is confirmed. These results provide deep insights and references for the reliable applications of GaN HEMTs.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs
           With Local Oxidation of SiC Isolation

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      Authors: Chia-Lung Hung;Bing-Yue Tsui;Chun-Pin Shih;Te-Kai Tsai;
      Pages: 5742 - 5748
      Abstract: In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( ${V} _{th}$ ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Clamping Capability of Parasitic p-n Diode in SBD-Embedded SiC MOSFETs

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      Authors: Teruyuki Ohashi;Hiroshi Kono;Souzou Kanie;Takahiro Ogata;Kenya Sano;Hideki Hayakawa;Shunsuke Asaba;Shigeto Fukatsu;Ryosuke Iijima;
      Pages: 5749 - 5754
      Abstract: Schottky barrier diode (SBD)-embedded SiC MOSFETs can clamp the parasitic p-n diode that causes a lack of long-term stability and thus realize high reliability. However, the maximum current density at which the parasitic p-n diode does not operate ( ${J}_{text{umax}}$ ) decreases with increasing temperature. Therefore, further improvement of ${J}_{text{umax}}$ and understanding the mechanism of the temperature dependence of ${J}_{text{umax}}$ are urgent issues. We have developed an equivalent circuit model of SBD-embedded SiC MOSFETs and derived an analytical formula of ${J}_{text{umax}}$ . Based on the derived analytical formula of ${J}_{text{umax}}$ , we have proposed guidelines for improving ${J}_{text{umax}}$ . Then, utilizing the guidelines, we have tried to improve ${J}_{text{umax}}$ experimentally. As a result, ${J}_{text{umax}}$ of 3.3 kV SBD-embedded SiC MOSFETs has been improved by 3.8 times. In addition, the mechanisms by which ${J}_{text{umax}}$ decreases in high blocking voltage devices and at high temperature have been investigated. We have found that the blocking voltage dependence of ${J}_{text{umax}}$ is caused by the change in the current distribution due to the difference in the drift resistance. On the other hand, it has als- been confirmed that the decrease in ${J}_{text{umax}}$ is not necessarily a problem because the rated current density also decreases in high blocking voltage devices. From the partial differentiation of ${J}_{text{umax}}$ ’s analytical formula with respect to temperature, it has been clarified that the decrease in ${J}_{text{umax}}$ is mainly due to the increase in the spread resistance and the JBS resistance.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Charge Injection Into Electrodeposited Cu2O From Metallic
           Stacks and Graphene

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      Authors: Amit Kumar;Himanshu Singh;Shubham Sahay;Krishna B. Balasubramanian;
      Pages: 5755 - 5759
      Abstract: Cuprous oxide (Cu2O) is a promising semiconductor for photovoltaic applications owing to its direct bandgap, facile fabrication possibilities, and cost effectiveness. However, the efficiency of single photovoltaic cells employing Cu2O is limited to 3%–4% necessitating investigations into material quality and reliable interface conductivity with contact metals. In this article, we systematically investigate the charge transport efficiency between electrodeposited (ED) Cu2O thin films and commonly used metallic stack contact materials, such as Ti/Au, Cr/Au, and Pt. We further explore a large-area CVD-grown graphene monolayer as a transparent contact for Cu2O thin films. Using transfer length measurements (TLMs), we observe thermal emission characteristics with no noticeable Fermi-pinning effects using the metal combinations employed on ED Cu2O. We achieve the lowest reported contact resistivity on Cu2O thin films ( $boldsymbol {rho }_{C}=2.15 times 10^{-5} Omega cm^{2}$ ) using a Ti–Au metal combination with the resistivity scaling exponentially with the barrier height on other metal stacks. In contrast, the true contact resistivity between a single monolayer of undoped graphene and a Cu2O thin film was measured to be an order of magnitude higher ( $5.526times 10^{-4} Omega cm^{2}$ ). Despite the higher resistance, this result indicates that further investigations into stacking multiple layers with careful doping control can make large area graphene attractive for photovoltaic applications using functional oxides.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • High-Throughput Manufacturing of Flexible Thermoelectric Generators for
           Low- to Medium-Temperature Applications Based on Nano-Silver Bonding

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      Authors: Seyedmohammad Mortazavinatanzi;Alireza Rezania;Lasse Rosendahl;
      Pages: 5760 - 5765
      Abstract: The melting point of the commercial soldering materials is a limiting factor for the functionality of the thermoelectric generators (TEGs) in medium-temperature ranges higher than 200 °C. Hence, using a proper bonding method which could be formed at lower temperatures and withstand higher temperatures is inevitable to unlock the full potential of the commercial thermoelectric materials. Nano-silver bonding is known as the “low-temperature joining technique” due to its lower processing temperature compared with the other conventional bonding approaches. This study is focused on presenting a fabrication process of flexible TEGs using nano-silver (Ag) paste bonding. The pellets of thermoelectric materials were prepared by wire cutting of bismuth telluride ingots in desired sizes. The electrical interconnects between the thermoelectric legs are nano-silver paste traces printed by a digitally control dispenser printer. Reliability of the thermoelectric module was evaluated from room temperature up to 300 °C as well as conducting the cyclic bending test. The proposed fabrication technique is similar to the flexible hybrid electronics (FHE) concept, which is scalable for high-throughput manufacturing, such as roll-to-roll or sheet-to-sheet printing.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Thermal–Mechanical and Signal Reliability of a New Differentiated
           TSV

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      Authors: Ziyu Liu;Han Jiang;Zhiyuan Zhu;Lin Chen;Qingqing Sun;Yabin Sun;David Wei Zhang;
      Pages: 5766 - 5772
      Abstract: The thermal–mechanical and signal reliability of through-silicon via (TSV) occupies an important position in three-dimensional integrated circuits (3D-ICs). However, few studies combined the thermal–mechanical and signal reliability are found. In the work, a new differentiated structure of TSV is proposed to decrease the peak thermal stress without affecting signal integrity. The effect of TSV diameter on the peak thermal stress and its location is deeply investigated to decrease the stress. Compared with regular TSV, the differentiated TSV can reduce 22% peak thermal stress and 68% occupied silicon area. More differentiated TSVs can be placed in the same Si substrate by considering the influence of thermal stress between TSVs. Meanwhile, the differentiated TSV can better shield crosstalk noise with ensuring signal integrity.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Low Specific Contact Resistivity of 10−3Ω·cm2 for Ti/Al/Ni/Au
           Multilayer Metals on SI-GaN:Fe Substrate

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      Authors: Xianghong Yang;Long Hu;Xin Dang;Xin Li;Weihua Liu;Chuanyu Han;Song Li;
      Pages: 5773 - 5779
      Abstract: For the application of third-generation compound semiconductors based on high-voltage, high-power, and high-frequency devices, particularly in photoconductive semiconductor switches (PCSSs), the ohmic contact preparation technology on semi-insulating substrates is crucial. However, iron-doped semi-insulating gallium nitride (SI-GaN:Fe) with low carrier concentration and high bulk resistivity has a very difficult time achieving good ohmic contact characteristics. Here, we have demonstrated preliminary results on an interesting class of good ohmic contact of Ti/Al/Ni/Au on Ga-face of SI-GaN:Fe. The results indicated that the Ti and Al thickness ratio is a critical parameter when determining the optimum annealing temperature and time for ohmic contact. With alloyed Ti/Al/Ni/Au stacks of 20 nm/120 nm/55 nm/45 nm on SI-GaN:Fe after annealing at 850 °C for 35 s in N2 atmosphere, a low specific contact resistivity of $10^{-3},,Omega cdot $ cm2 is achieved. At a future date, such excellent ohmic contact characteristics can be applied to the SI-GaN:Fe-based high-power PCSS.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • AC RTN: Testing, Modeling, and Prediction

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      Authors: Kean H. Tok;Jian F. Zhang;James Brown;Zengliang Ye;Zhigang Ji;Weidong Zhang;John S. Marsland;
      Pages: 5780 - 5786
      Abstract: Random telegraph noise (RTN) adversely induces time dependent device-to-device variations and requires modeling to optimize circuit design. Many early works were focused under dc test conditions, although digital circuits typically operate under ac conditions and it has been reported that ac RTN is substantially different from dc RTN. Tests on ac RTN were carried out mainly on individual traps, and a reliable statistical distribution of trap time constants for ac RTN is still missing. This prevents verifying the statistical accuracy of Monte Carlo ac RTN simulation based on compact models, especially in terms of their ability to predict ac RTN as time window increases. Recently, an integral methodology has been proposed for dc RTN, which can not only model it at short time but also predict it at long time. By introducing the concept of effective charged traps, the need for statistical distribution of trap time constants is removed, making RTN prediction similar to aging prediction. The objectives of this work are to report statistical experimental ac RTN data and to test the applicability of integral methodology to them. For the first time, it will be shown that a model extracted from a time window of 7.8 s can be used to predict the statistical distribution of long-term ( $3times 10^{{4}}$ s) ac RTN. The dependence of ac RTN on frequency and time window is analyzed, and the contributions of carrier tunneling from gate and substrate are assessed.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Analytical Solution of the Space Charge Limited Current Using
           Lambert–Tsallis Wq Function

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      Authors: V. F. Guedes;K. Z. Nobrega;R. V. Ramos;
      Pages: 5787 - 5791
      Abstract: The space charge limited current (SCLC) has been studied since more than a century ago, and up to now, it remains a hot topic playing a key role in charge transport in microelectronic and nanoelectronic devices. Therefore, it would be useful for device engineers the existence of mathematical tools able to work with the different models of SCLC proposed in the literature. In this direction, the present work shows the applications of the Lambert–Tsallis ${W}_{q}$ function for solving some problems analytically related to different models of SCLC, like some generalizations of the 1-D Child–Langmuir (CL) law and SCLC of solids with carrier-density-dependent mobility.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Extended RC Impedance and Relaxation Models for Dissipative
           Electrochemical Capacitors

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      Authors: Anis Allagui;Hachemi Benaoum;Ahmed S. Elwakil;Mohammad Alshabi;
      Pages: 5792 - 5799
      Abstract: Electrochemical capacitors are a class of energy devices in which complex mechanisms of accumulation and dissipation of electric energy take place when connected to a charging or discharging power system. Reliably modeling their frequency-domain and time-domain behaviors is crucial for their proper design and integration in engineering applications, knowing that electrochemical capacitors in general exhibit anomalous tendency that cannot be adequately captured with the traditional ${RC}$ -based models. In this study, we first review some of the widely used fractional-order models for the description of impedance and relaxation functions of dissipative resistive–capacitive system, namely, the Cole–Cole, Davidson–Cole, and Havriliak–Negami models. We then propose and derive new ${q}$ -deformed models based on modified evolution equations for the charge or voltage when the device is discharged into a parallel resistive load. We verify our results on anomalous spectral impedance response and time-domain relaxation data for voltage and charge obtained from a commercial supercapacitor.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • UV-Enhanced Electrical Performances of ZnO:Ga Nanostructure Nanogenerators
           by Using Ultrasonic Waves

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      Authors: Yen-Lin Chu;Ren-Jie Ding;Tung-Te Chu;Sheng-Joue Young;
      Pages: 5800 - 5807
      Abstract: In this work, nanogenerator (NG) devices based on gallium-doped zinc oxide (ZnO) nanorods (NRs) (Ga-doped ZnO NRs) were triumphantly developed and explored by a simple fabrication process. All one-dimensional (1-D) nanostructures were hydrothermally grown on an indium-tin-oxide (ITO) substrate at a low temperature of 90 °C for 6 h. After field-emission scanning electron microscope (FE-SEM), X-ray diffractometer (XRD), and high-resolution transmission electron microscope (HR-TEM) measurement, a hexagonal wurtzite structure with good single crystallinity was exhibited, and a preferential growth with ${c}$ -axis direction was revealed. The optical properties of all samples were annealed at high temperature and explored through photoluminescence (PL) spectroscopy, displaying two different emission peaks, including ultraviolet (UV) and green emissions. The compositions of the NRs were also examined by an X-ray photoelectron spectroscopy (XPS) and an energy-dispersive X-ray (EDX) spectroscopy. As a result, the performance of ZnO NGs with Ga elements exhibits an outstanding improvement in electrical measurements compared with ZnO NGs. Furthermore, the output voltage and current of Ga-doped ZnO NG under UV irradiation were approximately 0.053 V and $4.86times10$ −6 A, respectively. It is attributed to produce numerous electrons by UV light and Ga dopant. The designed NG in this article may collect electrical energy in the people’s surroundings and has potential Internet of Thing applications (e.g., portable electronics, wireless devices, and implantable biomedical sensors).
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Self-Sustained Mass Sensor With Physical Closed Loop Based on
           Thermal-Piezoresistive Coupled Resonators

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      Authors: Aojie Quan;Hemin Zhang;Chen Wang;Chenxi Wang;Linlin Wang;Rui Amendoeira Esteves;Yangyang Guan;Chengxin Li;Michael Kraft;
      Pages: 5808 - 5813
      Abstract: This article reports a mode-localized mass sensor based on thermal-actuation piezoresistive-detection self-oscillated weakly coupled resonators. Detailed theoretical models and simulations of the self-oscillation of the coupled resonators were established and were also verified using optical and electrical measurements. The sensor was fabricated and characterized in terms of stability, linearity, sensitivity, and resolution. Supplied with only a constant direct current (DC), the resonant mass sensor could oscillate at its resonant frequency with an ultrahigh quality factor of 95 k in air. By implementing the principle of the mode localization phenomenon, ~200 times parametric sensitivity improvement with amplitude ratio output was implemented compared to the traditional frequency output metric. A real-time mass detector with 84-fg resolution and larger than ~700-pg linear measurement range was obtained.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Design, Simulation, and Cold Test of a W-Band Double Nonparallel Staggered
           Grating Backward Wave Oscillator

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      Authors: Jin Zhang;Yasir Alfadhl;Xiaodong Chen;Liang Zhang;Adrian W. Cross;
      Pages: 5814 - 5818
      Abstract: A novel double nonparallel staggered grating (DNPSG) slow wave structure (SWS) is proposed to enhance the coupling impedance in a ${W}$ -band backward wave oscillator (BWO) driven by a pseudospark-sourced sheet electron beam. The DNPSG SWS has been shown a broadband of 72–125 GHz and a higher coupling impedance compared with the traditional double staggered grating (DSG) SWS in simulation. The DNPSG BWO structure consisting of ten SWS units and a broadband output structure is designed and fabricated. In the cold test of the DNPSG BWO, the measured ${S}_{11}$ (double of the losses in the DNPSG BWO) is above −10 dB in most of the band, which is satisfactory in the pseudospark-driven high-power device. The hot-test performance of the DNPSG BWO is analyzed by particle-in-cell (PIC) simulation in a beam voltage range of 14–90 kV and a current density range of 1.5– $5times10$ 7 A/m2, obtaining a high output power (max. 190 kW) over an ultrawide tuning band of 38 GHz (75–113 GHz) due to enhanced coupling impedance.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Increasingly Accurate Stability Study of the Experimental W-Band TWT Using
           Code TESLA-Z Stability Analysis Framework

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      Authors: Igor A. Chernyavskiy;Alan M. Cook;John C. Rodgers;
      Pages: 5819 - 5825
      Abstract: We present the results of our comprehensive numerical stability study of the experimental, high-power, two-stage Serpentine ${W}$ -band traveling-wave tube (TWT) with ~10% working bandwidth. This device demonstrated an output power level of ~215 W at 92 GHz at the nominal beam voltage of 20 kV and ~285 W at an increased beam voltage of 20.8 kV. The experimental device was observed to be stable in all cases when operated within the designed beam voltage range. The onset of instability near the lower band edge was observed at higher beam voltages approaching a threshold value of ~21.0 kV. We use the recently developed stability analysis framework, based on the Naval Research Laboratory (NRL) 2-D large-signal code TESLA-Z, to find the predicted threshold of zero-drive instabilities, which could develop near the lower band edge of the experimental ${W}$ -band TWT. An initial study was done by using a simplified model for geometry of the experimental electrodynamic structure of the TWT, which ignored all interface elements. TESLA-Z predictions for onset of instability, in this case, were found much higher in beam voltage than its measured value. Next, an advanced TESLA-Z-based stability study was performed using a more accurate, detailed model for geometry of the experimental electrodynamic structure of the TWT, including important elements such as couplers (transformers), lossy load (sever), and windows. This more detailed analysis gave more accurate results for the onset of instability, in good agreement with the measurements.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A High Interaction Impedance Microstrip Meander-Line With Conformal
           Dielectric Substrate Layer for a W-Band Traveling-Wave Tube

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      Authors: Lingna Yue;Wenbo Shan;Chiyi Liu;Jia Lu;Wenxiang Wang;Jin Xu;Dongchun Chen;Guoqing Zhao;Hairong Yin;Guo Guo;Wenxin Liu;Yanyu Wei;
      Pages: 5826 - 5831
      Abstract: A U-shaped microstrip meander-line (MML) with an additional conformal dielectric substrate layer (CMML) is investigated for application in ${W}$ -band traveling-wave tubes (TWTs). The interaction impedance of such slow wave structure (SWS) is at least 29% higher than that of typical N-shaped and U-shaped MML circuits with the same dimensions. Furthermore, the conformal substrate layer probably results in less energy concentration in the dielectric substrate to reduce attenuation and also reduces the chance of electron striking and accumulation on the substrate. In addition, a customized waveguide housing with input–output coupler is optimized for the relatively wider substrate width to house the SWSs and facilitate measurements. The particle-in-cell (PIC) simulation results predict that it potentially could provide maximum saturated output power 31.4 W and 21.9 dB gain at 96 GHz, with a 3-dB bandwidth of 92–98 GHz when the operating voltage is 6550 V and beam current is 100 mA, respectively. If the thickness of conformal quartz layer increases to $30 ~mu text{m}$ , the maximum output power can reach over 80 W. The measured S-parameters of the proposed entire 20-period structure match the simulated one well. The measured ${S}_{21}$ is better than −5.3 dB in the frequency range of 88–102 GHz. Attenuation is about 5.9–7.7 dB/cm in the ${W}$ -band, which is better than the measured results reported before.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Electromagnetic and Electrostatic Particle-in-Cell Simulations for
           Multipactor in Parallel-Plate Waveguide

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      Authors: Yonggui Zhai;Hongguang Wang;Meng Cao;Shu Lin;Min Peng;Yun Li;Wanzhao Cui;Yongdong Li;
      Pages: 5832 - 5838
      Abstract: This article introduced a multipactor threshold criterion based on collision and emission currents, and the simulation results were compared using a traditional method. The impact of macroparticle weight on multipactor saturation was studied using electromagnetic particle-in-cell (EM-PIC) simulations of CST Particle Studio. It was found that the simulation results converged when the macroparticle weight was less than 106. A model calculating accumulated charge on the dielectric surface was proposed and validated against theoretical calculations. The dynamic evolution of multipactor in dielectric-loaded parallel-plate waveguide was analyzed, and predictions were validated against results from the existing model. Finally, the effect of surface charge fields and space charge effect on the multipactor mechanism was studied. The results showed that the multipactor could be suppressed when the ratio of the number of accumulated electrons on the dielectric surface to the saturation electron population was greater than 3.96.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Research on Typical Displacement Current Peak in Relativistic Magnetron
           Priming

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      Authors: Tingxu Chen;Tianming Li;Renjie Cheng;Hao Zhou;Haiyang Wang;Tao Yang;Biao Hu;
      Pages: 5839 - 5844
      Abstract: During the operation of the relativistic magnetron (RM), the sudden change of voltage waveform will produce displacement currents that play a prominent role in assessing the operation state of magnetron, while they have been neglected in the previous research. Therefore, in this article, we introduce a novel method to analyze the working state of the magnetron in the starting stage by using the typical displacement current peak (TDP). The theoretical analysis shows that the TDP in a well-matched RM is attributed to the asynchrony between the mutation of self-magnetic field and electron beam, and the appearance of the TDP means the slow oscillation establishment or sluggish electron beam growth in the RM. According to such theory, we present a method to improve the operation state of RM and eliminate the TDP, and it is verified in our experiment. This work is beneficial for diagnosis and adjustment of RM working state in priming.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Design of Magnetron Injection Gun and Solenoid for G-Band Gyro-TWT Based
           on Collaborative Optimization Method

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      Authors: Yelei Yao;Haibing Huang;Bo Guan;Wenqi Gao;Yibin Sun;Wei Jiang;Yong Luo;
      Pages: 5845 - 5851
      Abstract: In this article, a collaborative design method for gyrotron magnetron injection gun (MIG) and solenoid is proposed for the first time. On this basis, the shape of the electrodes and solenoid sizes is optimized by the means of global optimization techniques. Simplified theory and numerical methods of MIG have been developed, and the results agree well with the PIC simulation. By using the new method, the calculation time is reduced and the numerical stability has been greatly improved compared with that directly solving the Lorentz equation. As an example, a helical electron beam with a velocity pitch ratio of 1.20 and a transverse velocity spread of 1.65% is obtained for G-band gyro-TWT.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Study of the Input Cavity Characteristics With Two-Beam Loading for
           Developing a Compact and High-Power Ka-Band Klystron

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      Authors: Xinyu Jiang;Liangjie Bi;Yu Qin;Bin Wang;Hailong Li;Lin Meng;Yong Yin;
      Pages: 5852 - 5857
      Abstract: Input cavity characteristics with a two-beam loading are one of the most important scientific problems for using a two-beam scheme to develop compact, high-power millimeter-wave klystrons. This article focuses on this problem with a 400 kW two-beam loading in an overmoded input cavity which is proposed to develop a Ka-band klystron with peak power toward 150–200 kW. The input cavity exploits TM13 mode to support two equivalent sections of field gaps for modulating two beams. The beam loading parameters, such as ${P}_{t}$ , and ${Q}_{b}$ , and cavity parameters, such as electric field distribution, frequency ( ${f}$ ), and cavity ${Q}_{l}$ without beams can be optimized and selected to achieve matching absorption by two beams with a certain RF power injection in the Ka-band. The CST Studio Suite (CST) simulation results show that over 99% power of the input signal around 35 GHz can be absorbed by the input cavity loaded by two beams with ${P}_{t}$ of 0.473– $0.716~mu text{P}$ . Constant ${P}_{t}$ exercises about the same degree of two-beam loading on the input cavity.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Design and Simulation Investigations of Dual-Band RBWO Using Sectional
           Slow Wave Structures for Long Pulse Generation

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      Authors: V. Venkata Reddy;M. Thottappan;
      Pages: 5858 - 5864
      Abstract: In this article, a relativistic backward wave oscillator (RBWO) with sectional slow wave structures (SWSs) has been designed to generate a long high-power microwave (HPM) pulse at two different frequencies. Two individual SWSs were cascaded using a drift section (drift section-II) that separated them at a sufficient distance to generate dual microwave frequencies. The first section of the SWS (SWS-I) has been designed to generate S-band frequency and the second section of the SWS (SWS-II) to generate C-band frequency. A rectangular resonant reflector (RR) has been used to reflect the backward traveling wave into a forward wave toward the collector. The drift section-II also acted as an RR for the C-band frequency in addition to make the phase adjustment between the backward and forward microwaves and end reflections of SWS-I. The performance of the dual-band RBWO with sectional SWSs has been studied through the particle-in-cell (PIC) simulation by a finite difference time domain (FDTD)-based numerical code. The present simulation predicted a total RF output power of ~600 MW in TM01 mode at ~3.6 and ~4.5 GHz with a power conversion efficiency of ~20% for an annular electron beam with voltage ~550 kV, developed current ~5.4 kA, and the guiding magnetic field of ~1.3 T. A clear and more stable RF output power up to 100 ns of simulation time at both operating frequencies was observed with a frequency difference (between S- and C-band) of ~0.9 GHz.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Theoretical Analysis of Sheet Beam Electron Gun for Terahertz Vacuum
           Electron Devices

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      Authors: Yiyang Su;Pengpeng Wang;Wenbo Wang;Cunjun Ruan;Wenlong He;
      Pages: 5865 - 5870
      Abstract: In the terahertz band, the vacuum electron devices with planar and miniaturized structures require the ultrahigh-precision description of high-density electron beams for formation and transportation with the theoretical analysis and simulation. Thus, the absence of the available theory for the sheet beam electron is put forward to investigate the 3-D spatial potential using a differential geometry and tensor analysis. The equation of electron beam potential can be derived by establishing a moving coordinate frame, carrying out the numerical calculations, and doing series expansion. To solve the complex sheet beam description of the existence of four corner singularities, the Riemann method and conformal mapping are adopted to overcome this difficulty. Then, a 0.22-THz vacuum electron tube using a sheet beam electron gun and corresponding optical system are designed. The beam voltage and current are 16.5 kV and 0.5 A, respectively, with a beam channel size of 1.4 mm $times0.14$ mm and a uniform magnetic field of 5980G. With the 3-D simulation, the high-density sheet electron beam can transport 18 mm successfully. The spatial potential of numerical calculation with the obtained sheet beam theoretical function and the simulation model are compared to verify the theoretical description. Both the results are with good consistency, which preliminarily proves the effectiveness of the theoretical function. This work will give the deep physical mechanics vision for the development of high-power and high-efficiency sheet beam terahertz tube in the future.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Effect of Electron Beam Properties on a Second Harmonic Gyrotron

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      Authors: Xianfei Chen;Yu Huang;Pengbo Wang;Houxiu Xiao;Zhaolun Deng;Zhenglei Wang;Donghui Xia;Tao Peng;Xiaotao Han;
      Pages: 5871 - 5878
      Abstract: In harmonic gyrotrons, the narrow operating region of the harmonic mode is significantly restricted by the severe mode competition from the fundamental parasitic modes, which makes it important to study the nonlinear effects of beam-wave interaction in the case of a nonideal electron beam. In this article, the effect of the electron velocity spread and the beam radius spread on the mode excitation, interaction efficiency as well as mode competition are analyzed for the desired harmonic mode and the parasitic fundamental mode operating far from the cut-off frequency. The effect of velocity spread is interpreted via the electron cyclotron resonance condition as well as the electron beam susceptibility with respect to the resonator field. The results show that the velocity spread can greatly broaden the effective operating region of the harmonic mode and the efficiency degradation can be contained at a reasonable level by proper design consideration of the interaction circuit. Whereas, the beam radius spread is the main factor that accounts for the efficiency degradation and can aggregate the mode competition. The results are referential to the design and analysis of harmonic gyrotrons as well as continuously frequency tunable gyrotrons.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Performance of a Multigap Multiaperture Pseudospark Switch in Series With
           the Saturable Inductor

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      Authors: Akhilesh Mishra;Shikha Misra;Ram Prakash Lamba;Abhijit Ravindra Tillu;Udit Narayan Pal;
      Pages: 5879 - 5885
      Abstract: In this study, experimental investigation has been performed for discharge characteristics of a multigap multiaperture (MGMA) configuration of pseudospark switch (PSS) with a saturable inductor (SI) in series at the anode. The impact of the number of inductor cores on the commutation process is studied experimentally. Initially, in the commutation process, when the anode voltage is 40 kV with five toroid cores, the inductor is unsaturated, and it offers high impedance, resulting in a slow current rise rate of $approx 2.5$ kA/ $mu text{s}$ with fast voltage drop rate. During the second phase, when the inductor gets saturated and offers low impedance, it leads to a fast-current rise rate of $approx 4.35$ kA/ $mu text{s}$ . Due to the SI, the discharge current rise lags behind the breakdown voltage drop of MGMA-PSS. It results in a significant reduction in power dissipation across the switch during the commutation process. Furthermore, equivalent electrical circuit modeling has also been proposed for the estimation of power losses during the commutation process. During the application of 40-kV anode voltage with five inductor cores at 30-Pa background H2 gas pressure, the commutation losses have been reduced up to ≈95%, which also enhanced the performance of PSS. The proposed analysis and optimization of the inductor core would be very much useful for the reduction in the anode erosion and improved the switching performance of the MGMA-PSS.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Analysis and Improvement of Performance Instability in Extended
           Interaction Klystrons With Random Geometrical Perturbations

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      Authors: Naining Guo;Zhaowei Qu;Xinwen Shang;Haibing Ding;Kegang Liu;Wenke Song;Han Wang;Jing Wang;Ding Zhao;Qianzhong Xue;
      Pages: 5886 - 5894
      Abstract: This article describes and evaluates the effect of random geometrical perturbations on resonance characteristics and output performance of extended interaction klystrons (EIKs). The perturbations, assuming a normal distribution, will result in random variation in resonance characteristics, including resonant frequency shift, quality factor shift, and field distortion. The results are demonstrated in a 220-GHz extended interaction cavity by combining theory, simulations, and experimental measurements. In addition, 3-D particle-in-cell (PIC) simulation and small-signal theory are employed to gain insights into the output performance instabilities caused by variation in the resonance characteristics. The comprehension of the factors that contribute to performance instability is fundamental to avoid excess costs in the fabrication process. Aided by the small-signal theory code with a calculation speed that is several orders faster than PIC simulation, we address the instability by applying cathode voltage adjustment technology, frequency tuning technology, and multiparameter optimization based on a genetic algorithm. Such analysis and improvement patterns are general for the EIKs operating in the terahertz regime.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Improving the Response Speed of an Active-Current Controlled Field Emitter
           Arrays by Modifying the Controlled Current

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      Authors: Deyi Huang;Yicong Chen;Chengyun Wang;Juncong She;Shaozhi Deng;Jun Chen;
      Pages: 5895 - 5899
      Abstract: Using an active-current control (ACC) component such as MOSFET in field emitter arrays (FEAs) is an important way to achieve stable emission current. However, the controlled current of ACC may reduce the response speed of FEAs due to the longer charging process, which limits its application. In this work, a general model for the field emission of MOSFET-controlled FEAs has been established to study the influence of controlled saturation current on its response speed. It is found that the response speed which decreases nearly linearly as the saturation current decreases can be reduced down by above 1 order of magnitude comparing to the intrinsic value. The field emission characteristics of a MOSFET-controlled ZnO nanowire FEAs under different saturation current and duty ratio have been investigated, in which the result is in consistency with the model. A solution using a controlled current which is larger than the induced current during the charging process and can rapidly reduce down to the field emission current has been proposed for balancing the stability and response speed in MOSFET-controlled FEAs. All the results provide a method for obtaining fast response ACC-FEAs, which should be useful in the application that requires pulsed driving FEAs.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Fully Analytical Current Model for Gate–Source Overlap Tunneling FETs
           as the Ternary Devices

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      Authors: Zhijun Lyu;Hongliang Lu;Chen Liu;Yuming Zhang;Yimen Zhang;Yi Zhu;Jiale Sun;Bin Lu;Ziji Jia;Mengqing Zhao;
      Pages: 5900 - 5905
      Abstract: Gate–source overlap tunneling FETs (GSO-TFETs) as a novel ternary device are very promising in low-power neuromorphic circuits. In this article, an accurate potential model of the ternary GSO-TFETs is presented for the face-tunnel region considering the quasi-mobile charges (QMCs) based on the analysis of the face-tunnel mechanism. Then a potential-based analytical current model is developed for the first time to predict the face-tunnel process and line-tunnel current simultaneously with both the gate and the drain modulations. The modeling results are validated with TCAD simulations and good agreement within a wide biasing range is achieved, which indicates the great potential of this SPICE-friendly model for the tunneling-based ternary device in the commercial IC design fields.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Enhancing the On/Off Current Ratio in Single-Molecule FET via Destructive
           Quantum Interference

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      Authors: Chiara Elfi Spano;Yuri Ardesi;Gianluca Piccinini;Mariagrazia Graziano;
      Pages: 5906 - 5912
      Abstract: We investigate through atomistic calculation the electronic structure and transport properties of 3-phenylethynylene (OPE3), 7-phenylvynylene (OPV7), and [3, 3]paraCyclophane (pCp)-based molecules. We reveal and analyze the Destructive Quantum Interference (DQI) phenomenon for the pCp single-molecule junction. The provided explanation of DQI via the dominant concurrence of inter-orbital and intra-orbital interference may support DQI engineering through the chemical synthesis of ad hoc molecular channel. Furthermore, we propose a Back gate Biasing-based method for the ON/OFF CUrrent Ratio Enhancement of the single-molecule Field-Effect transistor via the control of DQI (BBB-CURE-DQI). As an important outcome of the proposed method, an ON/OFF current ratio of 103 is achieved for pCp single-molecule FET. This value is orders of magnitude larger than typical values presented in the literature. The benefit of the DQI and the effectiveness of the BBB-CURE-DQI method are finally demonstrated at the circuital level by SPICE simulations of digital inverters implemented with the investigated molecules. Our analysis and results motivate the importance of future research investment for DQI manipulation via chemical synthesis and successive control to enable single-molecule FET-based nanocomputing applications.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Systematic Interpretation of Time Effect on Negative Capacitance of
           Ferroelectrics Based on Electrostatics and Charge Dynamics

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      Authors: Yulong Dong;Danyang Chen;Ni Zhong;Jingquan Liu;Chungang Duan;Xiuyan Li;
      Pages: 5913 - 5920
      Abstract: Negative capacitance (NC) effects in ferroelectric (FE) films have attracted intensive attention recently in terms of both polarization kinetics modeling and low-power CMOS applications. Its physical origin, however, is controversial because the experimentally observed NC effects are different from the initial concept, particularly on the frequency/voltage dependence and hysteresis. Recently, we have proposed an electrostatic model, with which the NC effect with hysteresis and voltage dependence in FE/paraelectric (PE) stacks in dc mode is explained from a viewpoint of polarization switching. Based on this, in this work, the NC effect in the dimension of time in both FE/PE and FE capacitor–resistor (FE-R) circuit is analytically formulated and experimentally studied by comprehensively considering the dynamics of polarization switching, charge communication with power supply, and charge leaking through the capacitor. Our results suggest that such NC effects only occur in a time window in both systems and a competition between FE switching and charge compensation is the key to determine the time window. Thus, a systematic understanding is accomplished to explain most of the phenomenon associated with NC effects in FEs.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Demonstration of a 2-D SnS/MXene Nanohybrid Asymmetric Memristor

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      Authors: Soumi Saha;Vivek Adepu;Khush Gohel;Parikshit Sahatiya;Surya Shankar Dan;
      Pages: 5921 - 5927
      Abstract: This article demonstrates the fabrication and characterization of a low-cost, energy-efficient, easy-to-fabricate SnS/MXene memristor in which an SnS/Ti3C2Tx active layer is sandwiched in between two copper electrodes. The device has been showing substantial merits with an experimental ${R}_{text{off}}$ : ${R}_{text{on}}$ ratio of ~22 with good cyclic stability, exceptional reproducibility, and data retention capability up to 1000 cycles. This article explains the detailed physics governing the various regions of the proposed memristor characteristics in terms of the dual ionic conduction mechanism. Furthermore, the article explains the memristor’s asymmetric behavior using the concept of the trapping and de-trapping of charge carriers. Real-time band structures extracted using sophisticated ultraviolet photoelectron spectroscopy (UPS) strongly support the claims reported in this article. Finally, this article concludes with a practical application of the fabricated device as a low-cost, tunable asymmetric clock generator circuit.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • A Computational Framework for Gradually Switching Ferroelectric-Based
           Negative Capacitance Field-Effect Transistors

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      Authors: Hyunjae Lee;Mayuri Sritharan;Youngki Yoon;
      Pages: 5928 - 5933
      Abstract: While the Landau approach is widely used to model polarization switching of ferroelectric (FE) materials, it cannot accurately describe gradual transition of polarization switching for a stand-alone FE in steady states. To overcome such limitations, the Miller model (MM) was used previously to replicate the switching behavior of FE within an FE–dielectric (FE-DE) capacitor. In this study, we demonstrate a new computational framework for gradually switching FE-based negative capacitance (NC) field-effect transistors (FETs) in steady states. In particular, we solve three modules iteratively: 1) non-equilibrium Green’s function (NEGF) for carrier transport; 2) Poisson’s equation for electrostatics; and 3) the MM for spontaneous polarization ( ${P}$ ) versus applied electric field ( ${E}_{text{FE}}$ ). Unlike the FE-DE capacitor, polarization varies along the device position due to the applied field across the device, and hence, polarization interactions are considered. Our simulation result exhibits hysteresis-free, steep-switching characteristics of the NCFET even with the “positive slope” in the ${P}-{E}_{text{FE}}$ curve originating from the MM. We have also explicated the physical origin of the experimentally demonstrated critical FE thickness, at which minimum subthreshold swing can be achieved, using two competing mechanisms. Finally, we vary FE parameters (i.e., saturation polarization, remnant polarization, and coercive field) within the MM to investigate their effects on the characteristics of the NCFET. This work not only suggests a novel computational framework for the simulation of the NCFET based particularly on gradually swi-ching FE but also provides irreplaceable physical insight into the optimization of the NCFET by tuning material and device parameters.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Tunneling FET Based on Monolayer Antimonene: The Role of Vacancy

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      Authors: Hossein N. Niknezhad;Shoeib Babaee Touski;
      Pages: 5934 - 5939
      Abstract: In this work, the electrical performance of the antimonene TFET is investigated using nonequilibrium Green’s function (NEGF) through a tight-binding approach. In the following, the effect of atom vacancy on the electrical behavior of the TFET is explored. The creation of the mid-gap state due to the vacancy is shown using the local density of states (LDOS) for the TFET and the density of states (DOS) for a ribbon. Furthermore, the effects of these mid-gap states on the ON-current, OFF-current, ON– OFF ratio, and subthreshold swing (SS) are discussed. Finally, the effect of the scaling in presence of vacancy is explored. The results show that a small vacancy percentage declines the SS while the variation of the ON– OFF ratio is negligible.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Grain Size Engineering Using Amorphous-Ge/Si Stack to Enhance Channel
           Mobility for NAND Flash Memory

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      Authors: Tae In Lee;Min Ju Kim;Eui Joong Shin;Gyusoup Lee;Jaejoong Jeong;Yun Hee Lee;Jung Hoon Lee;Jaeduk Lee;Byung Jin Cho;
      Pages: 5940 - 5943
      Abstract: We demonstrated that polycrystalline-Si (poly-Si) channel mobility could be significantly enhanced through a combined effect of grain size engineering and Ge diffusion into the poly-Si channel. By crystallizing an amorphous-Ge/Si stack via thermal annealing, grain size enlargement and Ge diffusion occur together, resulting in an increase of the channel mobility of up to lpzrptsim100%. The enhanced poly-Si channel mobility improved the program and erase speeds by 55.8% and 30.5%, respectively, with no adverse effect on retention and endurance characteristics.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Influence of Termination Isolation Deep-Oxide Trenches on Short-Circuit
           Capability in Silicon-On-Insulator Lateral IGBT

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      Authors: Jie Ma;Yong Gu;Long Zhang;Min Luo;Chengwu Pan;Siyang Liu;Weifeng Sun;Jing Zhu;Nailong He;Sen Zhang;
      Pages: 5944 - 5947
      Abstract: Termination isolation deep-oxide trenches (TITs) are inserted in the emitter side of silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) for electrical isolation. TITs have unstudied effect on electrical characteristics of SOI-LIGBT. In this article, the influence of location and electrical potential of TITs on short-circuit characteristics is investigated. SOI-LIGBTs with different TITs are fabricated and measured, and then, detailed calibrated TCAD simulations are carried out to elucidate the influence of TITs. By adjusting the location of TITs, the electrical potential distribution in the emitter side is reshaped, and the electrical potential at the end of inversion channel ( ${V}_{text{ch}}$ ) is lowered. A lower saturation current is achieved due to the reduced ${V}_{text{ch}}$ . TITs with negative electrical potential can attract more holes in the short-circuit condition, which can suppress the activation of parasitic n-p-n transistor. Both reduced ${I}_{text{sat}}$ and suppressed latch up can significantly improve short-circuit withstanding time ( ${t}_{text{SC}}$ ). By optimizing location and electrical potential of TIT, SOI-LIGBT can achieve 69.1% increase in ${t}_{text{SC}}$ at ${V}_{text{CE}} = 400$ V and ${V}_{text{GE}} = 15$ V without influencing other electrical characteristics.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Characterizing HfO2-Based Ferroelectric Tunnel Junction in
           Cryogenic Temperature

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      Authors: Jae Hur;Chinsung Park;Gihun Choe;Prasanna Venkatesan Ravindran;Asif Islam Khan;Shimeng Yu;
      Pages: 5948 - 5951
      Abstract: Since the discovery of ferroelectric properties in doped HfO2, various types of memory devices have emerged based on this novel material. Especially, the ferroelectric tunnel junction (FTJ) has gained considerable attention for selector-less crossbar array. Although various studies have been carried out for the HfO2-based FTJs, there are no investigations of them at a cryogenic temperature. While cryogenic memories are getting increasing attentions for diverse applications from high-performance computing to aerospace electronics, exploring the FTJ at cryogenic temperature is particularly interesting because it has been known for relatively poor retention characteristics and endurance at room temperature (RT). For the first time, we characterize the HfO2-based FTJ at cryogenic temperature down to 77 K. It was found that both the retention and endurance characteristics become greatly improved at 77 K. Furthermore, the read voltage was found to be critical for optimized performance in terms of ON-current, OFF-current, and their ratio at 77 K.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Corrections to “1-D Drift-Diffusion Simulation of Two-Valley
           Semiconductors and Devices”

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      Authors: Markus Müller;Philippe Dollfus;Michael Schröter;
      Pages: 5952 - 5952
      Abstract: In the above article [1], the numerator and denominator on the right-hand side of (12) should be interchanged to the following:
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Materials, processing and integration for neuromorphic devices and
           in-memory computing

    • Free pre-print version: Loading...

      Pages: 5953 - 5954
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power
           Applications

    • Free pre-print version: Loading...

      Pages: 5955 - 5956
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • Semiconductor Device Modeling for Circuit and System Design

    • Free pre-print version: Loading...

      Pages: 5957 - 5958
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • TechRxiv: Share Your Preprint Research with the World!

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      Pages: 5959 - 5959
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
  • IEEE Open Access Publishing

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      Pages: 5960 - 5960
      Abstract: Advertisement.
      PubDate: Oct. 2022
      Issue No: Vol. 69, No. 10 (2022)
       
 
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