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  Subjects -> ELECTRONICS (Total: 207 journals)
Showing 1 - 200 of 277 Journals sorted by number of followers
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 314)
Control Systems     Hybrid Journal   (Followers: 252)
IEEE Transactions on Geoscience and Remote Sensing     Hybrid Journal   (Followers: 202)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 194)
Electronics     Open Access   (Followers: 138)
Advances in Electronics     Open Access   (Followers: 132)
Electronic Design     Partially Free   (Followers: 129)
Electronics For You     Partially Free   (Followers: 128)
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 120)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 91)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 89)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 88)
IEEE Transactions on Software Engineering     Hybrid Journal   (Followers: 84)
IEEE Transactions on Industrial Electronics     Hybrid Journal   (Followers: 84)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 81)
IET Power Electronics     Open Access   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 67)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 63)
IEEE Embedded Systems Letters     Hybrid Journal   (Followers: 62)
IEEE Transactions on Industry Applications     Hybrid Journal   (Followers: 58)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 53)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 53)
Advances in Power Electronics     Open Access   (Followers: 49)
IEEE Nanotechnology Magazine     Hybrid Journal   (Followers: 45)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 45)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 41)
IEEE Transactions on Biomedical Engineering     Hybrid Journal   (Followers: 35)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 34)
IET Microwaves, Antennas & Propagation     Open Access   (Followers: 34)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 32)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 30)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 28)
Electronics Letters     Open Access   (Followers: 28)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 27)
Microelectronics and Solid State Electronics     Open Access   (Followers: 27)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Aerospace Innovations     Full-text available via subscription   (Followers: 24)
Journal of Sensors     Open Access   (Followers: 23)
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 22)
IEEE Reviews in Biomedical Engineering     Hybrid Journal   (Followers: 20)
IEEE/OSA Journal of Optical Communications and Networking     Hybrid Journal   (Followers: 19)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 18)
Journal of Artificial Intelligence     Open Access   (Followers: 18)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 17)
IET Wireless Sensor Systems     Open Access   (Followers: 17)
Circuits and Systems     Open Access   (Followers: 16)
Machine Learning with Applications     Full-text available via subscription   (Followers: 15)
Archives of Electrical Engineering     Open Access   (Followers: 15)
International Journal of Control     Hybrid Journal   (Followers: 14)
IEEE Transactions on Signal and Information Processing over Networks     Hybrid Journal   (Followers: 14)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 14)
IEEE Women in Engineering Magazine     Hybrid Journal   (Followers: 13)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
IEEE Solid-State Circuits Magazine     Hybrid Journal   (Followers: 13)
IEEE Transactions on Learning Technologies     Full-text available via subscription   (Followers: 12)
IEEE Transactions on Broadcasting     Hybrid Journal   (Followers: 12)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 12)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 11)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 11)
International Journal of Advanced Electronics and Communication Systems     Open Access   (Followers: 11)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 11)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 11)
Open Journal of Antennas and Propagation     Open Access   (Followers: 10)
IETE Journal of Research     Open Access   (Followers: 10)
Solid-State Electronics     Hybrid Journal   (Followers: 10)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
IETE Technical Review     Open Access   (Followers: 9)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 9)
Nature Electronics     Hybrid Journal   (Followers: 9)
Superconductivity     Full-text available via subscription   (Followers: 9)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 9)
Batteries     Open Access   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 8)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 8)
International Journal of Antennas and Propagation     Open Access   (Followers: 8)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 8)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 8)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 8)
IEEE Transactions on Autonomous Mental Development     Hybrid Journal   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
China Communications     Full-text available via subscription   (Followers: 8)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 7)
Power Electronic Devices and Components     Open Access   (Followers: 7)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 7)
Nanotechnology, Science and Applications     Open Access   (Followers: 7)
IEEE Magnetics Letters     Hybrid Journal   (Followers: 7)
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 6)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 6)
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access   (Followers: 6)
International Journal of Electronics     Hybrid Journal   (Followers: 6)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 6)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 6)
Journal of Power Electronics     Hybrid Journal   (Followers: 6)
Annals of Telecommunications     Hybrid Journal   (Followers: 6)
Electronic Markets     Hybrid Journal   (Followers: 6)
Energy Storage Materials     Full-text available via subscription   (Followers: 6)
IEEE Transactions on Services Computing     Hybrid Journal   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
Journal of Optoelectronics Engineering     Open Access   (Followers: 5)
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 5)
Journal of Field Robotics     Hybrid Journal   (Followers: 5)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Batteries & Supercaps     Hybrid Journal   (Followers: 5)
IEEE Pulse     Hybrid Journal   (Followers: 5)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal   (Followers: 4)
Networks: an International Journal     Hybrid Journal   (Followers: 4)
EPE Journal : European Power Electronics and Drives     Hybrid Journal   (Followers: 4)
Advanced Materials Technologies     Hybrid Journal   (Followers: 4)
Frontiers in Electronics     Open Access   (Followers: 4)
Wireless and Mobile Technologies     Open Access   (Followers: 4)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
IEEE Transactions on Haptics     Hybrid Journal   (Followers: 4)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 4)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 4)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Informatik-Spektrum     Hybrid Journal   (Followers: 3)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 3)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 3)
Advancing Microelectronics     Hybrid Journal   (Followers: 3)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 3)
IETE Journal of Education     Open Access   (Followers: 3)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Sensors International     Open Access   (Followers: 3)
e-Prime : Advances in Electrical Engineering, Electronics and Energy     Open Access   (Followers: 3)
EPJ Quantum Technology     Open Access   (Followers: 3)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 3)
Transactions on Electrical and Electronic Materials     Hybrid Journal   (Followers: 2)
ACS Applied Electronic Materials     Open Access   (Followers: 2)
IET Smart Grid     Open Access   (Followers: 2)
Energy Storage     Hybrid Journal   (Followers: 2)
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 2)
Australian Journal of Electrical and Electronics Engineering     Hybrid Journal   (Followers: 2)
Journal of Information and Telecommunication     Open Access   (Followers: 2)
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 2)
Journal of Semiconductors     Full-text available via subscription   (Followers: 2)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 2)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Journal of Nuclear Cardiology     Hybrid Journal   (Followers: 2)
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access   (Followers: 1)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 1)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 1)
IEEE Letters on Electromagnetic Compatibility Practice and Applications     Hybrid Journal   (Followers: 1)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Електротехніка і Електромеханіка     Open Access   (Followers: 1)
Open Electrical & Electronic Engineering Journal     Open Access   (Followers: 1)
IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology     Hybrid Journal   (Followers: 1)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Transactions on Cryptographic Hardware and Embedded Systems     Open Access   (Followers: 1)
International Journal of Hybrid Intelligence     Hybrid Journal   (Followers: 1)
Ural Radio Engineering Journal     Open Access   (Followers: 1)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
Edu Elektrika Journal     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Automatika : Journal for Control, Measurement, Electronics, Computing and Communications     Open Access  
npj Flexible Electronics     Open Access  
Elektronika ir Elektortechnika     Open Access  
Emitor : Jurnal Teknik Elektro     Open Access  
IEEE Solid-State Circuits Letters     Hybrid Journal  
IEEE Open Journal of Industry Applications     Open Access  
IEEE Open Journal of the Industrial Electronics Society     Open Access  
IEEE Open Journal of Circuits and Systems     Open Access  
Journal of Electronic Science and Technology     Open Access  
Solid State Electronics Letters     Open Access  
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Journal of Engineered Fibers and Fabrics     Open Access  
Jurnal Teknologi Elektro     Open Access  
IET Nanodielectrics     Open Access  
Elkha : Jurnal Teknik Elektro     Open Access  
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Jurnal Teknik Elektro     Open Access  
IACR Transactions on Symmetric Cryptology     Open Access  
Acta Electronica Malaysia     Open Access  
Bioelectronics in Medicine     Hybrid Journal  
Chinese Journal of Electronics     Open Access  
Problemy Peredachi Informatsii     Full-text available via subscription  
Technical Report Electronics and Computer Engineering     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Visión Electrónica : algo más que un estado sólido     Open Access  
Telematique     Open Access  
International Journal of Nanoscience     Hybrid Journal  
International Journal of High Speed Electronics and Systems     Hybrid Journal  
Semiconductors and Semimetals     Full-text available via subscription  

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IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 18  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [228 journals]
  • IEEE Electron Devices Society Information

    • Free pre-print version: Loading...

      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • IEEE Transactions on Electron Devices Information for Authors

    • Free pre-print version: Loading...

      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Blank Page

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      Abstract: This page or pages intentionally left blank.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Analysis of Abnormal GIDL Current Degradation Under Hot Carrier Stress in
           DSOI-MOSFETs

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      Authors: Yijun Qian;Yuan Gao;Amit Kumar Shukla;Lu Sun;Xinbo Zou;Tao Wu;Zhiqiang Mu;Kai Lu;Yemin Dong;Xing Wei;Yumeng Yang;
      Pages: 5965 - 5970
      Abstract: It is generally believed that the gate-induced drain leakage (GIDL) current would increase with the hot carrier stress (HCS) time. As more interface electron traps are generated near the drain side, it results in a steeper energy barrier that makes the band-to-band tunneling (BTBT) process much easier. In this work, however, an abnormal decrease of such leakage current was observed in double silicon on insulator MOSFET under floating body (FB) condition. Through systematic characterization on different devices and operation conditions, we find that this behavior can be explained by the activation of lateral parasitic bipolar transistor (PBT), and the subsequent reduction of its current gain after the stress cycle. This is further supported by the simulation results that the induced additional traps would lower the amplified current by increasing the electron recombination rate. Our findings would shed more light on the roles of interface traps played in the MOSFET reliability analysis.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and
           Balanced Driving Currents Using Single Work Function Metal Process

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      Authors: Lei Cao;Qingzhu Zhang;Yanna Luo;Jie Gu;Weizhuo Gan;Peng Lu;Jiaxin Yao;Haoqing Xu;Peng Zhao;Kun Luo;Yongqin Wu;Weihai Bu;Zhenhua Wu;Huaxiang Yin;
      Pages: 5971 - 5977
      Abstract: In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed and investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on the fabrication process of general gate-all-around (GAA) nanosheet FETs (NSFETs), the special fishbone-like channel composed of vertically stacked Si NSs and sandwiched SiGe nano-fins is experimentally demonstrated by the channel-first process. The simulated electrical characteristics show that the width of the nano-fins should be within 5 nm for a better gate control. Unlike traditional NSFETs, symmetrical threshold voltages ( ${V}_{text {th}}text{s}$ ) for n-type and p-type fishbone FETs can be achieved by using a sWFM, and $Delta {V}_{text {th}}$ is optimized by 99.26% compared with that of NSFETs. Meanwhile, it is also found that the SiGe nano-fins contribute more driving current for p-type devices. Therefore, the proposed fishbone FETs with sWFM not only exhibit significantly enhanced driving current but also provide good balance between the performances of n-type and p-type fishbone FETs with a little extra process cost.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • 3-D Modeling of Fringe Gate Capacitance in Complementary FET (CFET)

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      Authors: Xiaoqiao Yang;Yabin Sun;Ziyu Liu;Yun Liu;Xiaojin Li;Yanling Shi;
      Pages: 5978 - 5984
      Abstract: In this work, an analytical model for fringe gate capacitance in complementary FET (CFET) is proposed. Three kinds of CFET based on the fin, gate-all-around (GAA) nanowire, and nanosheet are investigated. The fringe capacitance of CFET is separated into n- and p- FETs like dc performance. For each n- or p-FET, the fringe capacitances are divided into seven components according to the geometric topology. Conformal mapping and integral methods are used to calculate the dual- ${k}$ dielectric perpendicular capacitance and coplanar plate capacitance. The model accuracy is verified with the 3-D field solver. The impact of device parameters on the overall fringe gate capacitance is also evaluated. The proposed fringe gate capacitance model is implanted in the BSIM model and is verified for 3-D TCAD simulations. The proposed model is helpful for reducing the parasitic capacitance in CFET device design and CFET-based circuit design.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Reliable High-Voltage Drain-Extended FinFET With Thermoelectric
           Improvement

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      Authors: Ki Yeong Kim;Young Suh Song;Garam Kim;Sangwan Kim;Jang Hyun Kim;
      Pages: 5985 - 5990
      Abstract: In this article, a reliable drain-extended (De) fin-shaped field-effect transistor (DeFinFET) with improved thermal performance and electrical performance is proposed for high-voltage (HV) system-on-chip (SoC) applications at 10-nm technology nodes. The proposed device structure uses the dual split field plate (DS) technique and high thermal conductivity of silicon dioxide (SiO2), which enables significant thermal improvement in DeFinFET. The proposed structure shows an improvement in maximum lattice temperature ( ${T}_{text {MAX}}$ ) from 473 to 424 K, and an improvement in thermal resistance ( ${R}_{text {TH}}$ ) from 18.7 to 11.9 K/ $mu text{W}$ . As a result, effective electron mobility ( $mu _{text {eff}}$ ) is consequently enhanced, which enables the highest ON-current ( ${I}_{text {on}}$ ) of the proposed device structure compared to the conventional DeFinFET (plate with SiO2) and previous DeFinFET (plate with HfO2). This thermal and electrical co-improvement indicates that the proposed device structure with DS technique could enable the thermal-aware design for next-generation HV SoC application.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Impact of ZnO Cap Layer on the Performance of MgZnO/CdZnO Heterostructure
           With YO Spacer Layer

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      Authors: Pawan Kumar;Sumit Chaudhary;Md Arif Khan;Ruchi Singh;Myo Than Htay;Rahul Prajesh;Ajay Agarwal;Shaibal Mukherjee;
      Pages: 5991 - 5995
      Abstract: In this work, we report the impact of the ZnO cap layer on mobility ( $mu $ ), sheet carrier density ( ${n} _{s}$ ), and conductance ( ${n} _{s} times mu $ ) of dual ion beam sputtering (DIBS) grown MgZnO/CdZnO (MCO) heterostructure with and without $text{Y}_{{2}}text{O}_{{3}}$ spacer layer. Hall measurements demonstrate that the addition of a 30-nm ZnO cap layer results in an enhancement of $mu $ by about $2.3times $ compared to that for the uncapped MCO heterostructure with a spacer layer. The results presented are significant for the realization of cost-effective and large area MCO-based heterostructure field-effect transistor (HFET) for sensor, microwave, and power devices.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Electrical Characteristics and Defect Dynamics Induced by Swift Heavy Ion
           Irradiation in Pt/PtO/-Ga₂O₃ Vertical Schottky Barrier Diodes

    • Free pre-print version: Loading...

      Authors: N. Manikanthababu;Hardhyan Sheoran;K. Prajna;S. A. Khan;K. Asokan;J. V. Vas;R. Medwal;B. K. Panigrahi;R. Singh;
      Pages: 5996 - 6001
      Abstract: In situ ${I}$ – ${V}$ and ${C}$ – ${V}$ measurements were performed on Pt/PtOx/ $beta $ -Ga2O3 vertical Schottky barrier diodes (SBD) during 120 MeV Au9+ swift heavy ion (SHI) irradiation in a fluence range of $1times 10^{{10}}$ – $2times 10^{{12}}$ ions/cm2. The reverse leakage current density increased from $1.21times 10^{-{10}}$ to $1.69times 10^{-{4}}$ A/cm2 at −1 V. The Schottky barrier height (SBH) remains close to ~1.8 eV up to the fluence of $5times 10^{{11}}$ ions/cm2, and however, at the fluences of $1times 10^{{12}}$ and $2times 10^{{12}}$ ions/cm2, the SBH increased to 1.93 and 2.03 eV, respectively. Also, the ideality factor (IF) increased from 1.07 to 1.38. The in situ ${C}$ – ${V}$ measurements showed a similar trend, as the SBH decreased from 2.04 to ~1.88 eV until $5times 10^{{11}}$ ions/cm2, but it increased to 2.14 and 2.56 eV at $1times 10^{{12}}$ and $2times 10^{{12}}$ ions/cm2, respectively. In addition, the doping concentration decreased from $1.01times 10^{{16}}$ to $0.27times 10^{{16}}$ cm $^{-{3}}$ as the defects increased significantly at the fluence of $2times 10^{{12}}$ ions/cm2. The cathodoluminescence measurements revealed various Ga and O defects produced during SHI irradiation. Cross-sectional transmission electron microscopy measurements confirmed the formation of tracks within $beta $ -Ga2O3 along the SHI path, and these results are explained with the inelastic thermal spike model.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Quasi-2-D Physical Modeling of GaN Microwave HEMTs for RF Applications

    • Free pre-print version: Loading...

      Authors: Morgan G. Carpenter;Peter H. Aaen;Christopher M. Snowden;
      Pages: 6002 - 6009
      Abstract: The dc and small-signal characterization of microwave gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs) is described, using a new quasi-2-D (Q2D) physical model which allows fast, physics-based electronic and microwave simulation with predictive process variation for these devices at dc and RF frequencies for the first time, which is suitable for device design and development. The predicted results are compared to measured data of transistors intended for communications applications. The simulation uses a self-consistent Schrödinger–Poisson solver, coupled with current- and energy-continuity solutions for carrier transport. The simulator incorporates hot electrons, polarization, temperature dependence, and short-gate effects.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Trapping Effect in AlInN/GaN HEMTs: A Study Based on Photoionization and
           Pulsed Electrical Measurements

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      Authors: R. Strenaer;Y. Guhel;C. Gaquière;B. Boudart;
      Pages: 6010 - 6015
      Abstract: The aim of this article is to detect electron traps in AlInN/GaN transistors operating at room temperature by combining pulsed electrical measurement with photoionization techniques to rapidly assess their activation energies and time constants. In addition, this technique can also reveal the presence of electron traps that cannot be observed by using pulsed measurements alone. Thus, two electron traps were identified including a deep level whose origin could be related to dislocations in the GaN buffer existing in the devices. At the same time, this study has shown that the time constants of these electron traps are inferior to 400 ns and that the electrical behavior of the components is also degraded by the presence of surface states with a time constant of 4 $mu text{s}$ . Moreover, these two traps are at the origin of the gate lag effects observed during the pulsed electrical characterization of the AlInN/GaN high electron mobility transistors (HEMTs). Likewise, a negative output conductance induced by a trapping effect has been put forward.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Electrical Characterization and Modeling of GaN HEMTs at Cryogenic
           Temperatures

    • Free pre-print version: Loading...

      Authors: Mohammad Sajid Nazir;Pragya Kushwaha;Ahtisham Pampori;Sheikh Aamir Ahsan;Yogesh Singh Chauhan;
      Pages: 6016 - 6022
      Abstract: In this work, we present a phenomenological cryogenic model for gallium nitride (GaN) high electron mobility transistors (HEMTs) with validity all the way down to a temperature of 10 K, benchmarked with experimental characterization results. The device under test (DUT) for cryogenic characterization is a GaN HEMT with a channel length of 250 nm and a gate width of $40~mu text{m}$ . The characterization results exhibit the negative threshold voltage shifts of −3.437, −3.087, and −2.998 V at the temperatures of 300, 60, and 10 K, respectively. Additionally, kink effects at cryogenic temperatures in output characteristics are observed that behave non-monotonically with gate-to-source bias. The impact of detrapping is modeled to investigate the negative shift in ${V}_{text {TH}}$ with increasing temperature. To model the kink, the effects of temperature, impact ionization, and field-dependent trapping/detrapping on ${V}_{text {TH}}$ have been explored and implemented as a submodel in the industry standard Advanced SPICE Model (ASM)-HEMT framework. Here, we aim to overcome the limitations of the prior GaN device models in the quest for enabling GaN-based circuits for cryogenic applications, such as deep space reception, radio astronomy, and quantum computing.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Low-Resistance Ta/Al/Ni/Au Ohmic Contact and Formation Mechanism on
           AlN/GaN HEMT

    • Free pre-print version: Loading...

      Authors: Hao Lu;Bin Hou;Ling Yang;Fang Song;Meng Zhang;Mei Wu;Xiaohua Ma;Yue Hao;
      Pages: 6023 - 6027
      Abstract: In this article, we systematically investigated the Ta/Al/Ni/Au and Ti/Al/Ni/Au ohmic contacts, and contact formation mechanism on ultrawide bandgap (UWBG) AlN barrier heterostructure without using the source–drain regrowth technique. The excellent ohmic contact performance of the Ta-based scheme was observed. The transmission line model (TLM) results depicted an ultralow contact resistance of $0.08 Omega cdot $ mm and a specific contact resistance of $1.06times 10^{-{7}} ,, Omega cdot $ cm2. Atomic force microscope (AFM) shows that the Ta/Al/Ni/Au sample presents a surface morphology improvement compared with the Ti/Al/Ni/Au sample. Transmission electron microscope (TEM) illustrated that the dominant contact mechanism for ultralow resistance is direct contact through TaxAlyAuz alloy penetration. Meanwhile, the difficulty of contact formation for the Ti-based sample was also discussed through the microstructural analysis. These results demonstrate that the proposed Ta/Al/Ni/Au metal scheme is a high-performance and cost-effective ohmic contact technique well suited for AlN/GaN HEMT fabrication process.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Analysis of Impact Ionization Effects on Current Collapse of AlGaN/GaN
           HEMTs

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      Authors: Hiraku Onodera;Toshiaki Kabemura;Kazushige Horio;
      Pages: 6028 - 6034
      Abstract: Computer-aided analysis of impact ionization effects on turn-on characteristics or current collapse of AlGaN/GaN HEMTs is performed. Here, an intrinsic semi-insulating buffer is adopted in which deep donors are assumed to compensate deep acceptors, then the ionized deep donor usually plays a role as an electron trap. Calculated turn-on characteristics show that when impact ionization is not included, the drain current begins to increase relatively slowly because electrons are emitted from the deep donors, showing a large current collapse. On the other hand, when impact ionization is included and an ON-state drain voltage ${V}_{text {D} {{ text {ON}}}}$ is high, generated holes between the gate and drain flow toward the buffer and are captured by neutral deep donors, particularly at the source side. The hole capturing time becomes relatively short when ${V}_{text {D} {{ text {ON}}}}$ is high and the hole density is high. Because of these increases in positive space charges in the buffer, the drain current increases relatively fast before the electron emission under the gate starts. Therefore, the current collapse becomes weaker when the impact ionization is considered and ${V}_{text {D} {{ text {ON}}}}$ is higher. The situation may be similar with a different type of buffer such as an Fe-doped semi-insulating buffer in which the Fe-originated level (deep acceptor) is above the midgap and it usually plays a role as an electron trap.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Interplay of Device Design and Carbon-Doped GaN Buffer Parameters in
           Determining Dynamic in AlGaN/GaN HEMTs

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      Authors: Vipin Joshi;Sayak Dutta Gupta;Rajarshi Roy Chaudhuri;Mayank Shrivastava;
      Pages: 6035 - 6042
      Abstract: Using a well-calibrated computational framework, we reveal a complex interplay between the device design and the epi-stack parameters, which determines the electron trapping in the carbon-doped GaN buffer, leading to dynamic ON resistance ( ${R}_{ mathrm{scriptscriptstyle ON}}$ ) in AlGaN $/$ GaN HEMTs. The parameters being considered here are surface trap concentration, passivation thickness, field plate length, unintentionally doped (UID) GaN channel thickness, strain-induced piezoelectric polarization in the AlGaN layer, buffer traps, and carbon–Si co-doping of the GaN buffer. The role of surface traps in determining the extent of electron injection and trapping in the GaN buffer is revealed. Furthermore, its dependence on piezoelectric polarization in the AlGaN layer and implications on dynamic ${R}_{ mathrm{scriptscriptstyle ON}}$ is discussed. Correlation among the passivation thickness, the field plate length, and the UID channel thickness affecting the channel electric field profile is explored, which, in turn, determines the extent of electron injection into the GaN buffer and eventually the extent of the dynamic ${R}_{ mathrm{scriptscriptstyle ON}}$ degradation. This work also develops detailed physical insights explaining the mechanisms responsible for the disclosed complex interplay. This allowed us to discuss buffer-doping optimization to minimize electron trapping in the GaN buffer and resulting dynamic ${R}_{ mathrm{scriptscriptstyle ON}}$ while maximizing the breakdown voltage of the device. These new findings are expected to provide guidelines to design dynamic ${R}_{ mathrm{scriptscriptstyle ON}}$ resilient HEMTs and also to explain experimental trends associated with dynamic ${R}_{ mathrm{scriptscriptstyle ON}}$ behavior as a function of the device and epi-stack parameters.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Memristive Fast-Canny Operation for Edge Detection

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      Authors: Jing Tian;Hou-Ji Zhou;Han Bao;Jia Chen;Xiao-Di Huang;Jian-Cong Li;Ling Yang;Yi Li;Xiang-Shui Miao;
      Pages: 6043 - 6048
      Abstract: Memristor-based in- memory computing paradigm is a promising path for edge detection in image preprocessing on end devices that reduces the computational pressure on data centers. However, the implementation of the well-performing Canny operator for edge detection faces challenges in terms of computational time and area overhead when mapped to memristor arrays. In this work, we proposed an efficient memristive one-step implementation of a fast-Canny operator. Exploiting the associative property of multiplication, the conventional Canny operator consisting of Gaussian and Sobel operators is converted into a fast-Canny operator and mapped to an array of nine parallel memristors. Then, the output currents are the final pixels of the edge image. To verify the feasibility of the method, successful edge detection with high accuracy (OIS = 0.73) is achieved in device-aware simulation under device variation (
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Leaky Integrate-and-Fire Neuron Based on Hexagonal Boron Nitride (h-BN)
           Monocrystalline Memristor

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      Authors: Fangsheng Qian;Ruo-Si Chen;Ruopeng Wang;Junjie Wang;Peng Xie;Jing-Yu Mao;Ziyu Lv;Shenghao Ye;Jia-Qin Yang;Zhanpeng Wang;Ye Zhou;Su-Ting Han;
      Pages: 6049 - 6056
      Abstract: As a competitive candidate for artificial neurons, memristors have become the focus of intense research owing to their intrinsic ion migration tunability, enabling an authentic implementation of biomimicry. However, they still suffer from variability issues due to 3-D uncontrollable filament dynamics in an amorphous medium and modeling of switching dynamics underlying filament growth and rupture is still under investigation. In this work, we present volatile memristors that exhibit desired characteristics for neuromorphic computing with low performance variations utilizing a hexagonal boron nitride (h-BN) monocrystalline as a switching medium. Theoretical investigations assisted by the Monte Carlo simulation combined with experimentally detected ${I}$ – ${V}$ characteristics described that the electric field dominates the set process, whereas the Gibbs–Thomson interfacial energy minimization and heat dissipation influence the relaxation process mostly. Additionally, h-BN memristors with high switching uniformity provide an ideal hardware platform for credible neuron emulation and software identification of digital images.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Theoretical Study of Carrier Transport in
           Metal–Ferroelectric–Insulator–Semiconductor Ferroelectric Tunnel
           Junction Memristor

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      Authors: Huali Duan;Erping Li;Yanbin Yang;Wenchao Chen;
      Pages: 6057 - 6064
      Abstract: Ferroelectric tunnel junction (FTJ) based on the metal–ferroelectric–insulator–semiconductor (MFIS) stacks shows great potential in neuromorphic and in-memory computing. Tunneling current in the MFIS-FTJ can be calculated by the Wentzel–Kramers–Brillouin (WKB) method with the band profile solved from Poisson’s equation or by self-consistently solving Poisson’s equation and the drift-diffusion transport equations with a tunneling-induced carrier generation rate. The carrier redistribution in the semiconductor is neglected in the former method, which reduces the complexity and saves the computational cost but may or may not lead to significant errors. In this article, a comprehensive study of the two simulation methods mentioned above is performed to investigate their applicable conditions and balance the accuracy and computational cost. The current densities of the MFIS-FTJs with different material parameters, including the barrier width, barrier height, carrier mobility, and polarization charge density simulated by the two methods, are compared and analyzed. As the voltage drop across the semiconductor cannot be neglected, method II is required to take the carrier transport in the semiconductor into account and method I is not accurate; otherwise, method I is more suitable due to its low computational cost without loss of accuracy.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Highly Linear Analog Spike Processing Block Integrated With an AND-Type
           Flash Array and CMOS Neuron Circuits

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      Authors: Kyu-Ho Lee;Dongseok Kwon;Sung Yun Woo;Jong Hyun Ko;Woo Young Choi;Byung-Gook Park;Jong-Ho Lee;
      Pages: 6065 - 6071
      Abstract: In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array ( $25times4$ synapses) and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). We investigate the synaptic behavior of the CTF cells and the operating principle of the neuron circuits. Under the given operating conditions, the fabricated SPB consistently exhibits a highly linear relationship ( ${R}^{{2}}$ > 0.999) between the current sum and the output spike frequency, enabling the SNNs to precisely mimic the layer of artificial neural networks (ANNs) with rectified linear unit (ReLU) activation function. Based on the fabricated SPB, a single-layer SNN is experimentally demonstrated for classifying the $5times5$ digit patterns.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • First Demonstration of Ferroelectric Tunnel Thin-Film Transistor
           Nonvolatile Memory With Polycrystalline-Silicon Channel and HfZrO Gate
           Dielectric

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      Authors: William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Yao-Jen Lee;Ju-Heng Lin;Pin-Hua Wu;Jui-Che Chang;Cheng-Lun Yen;Hsin-Chun Tseng;Hsu-Tang Liao;Yu-Wen Chou;Min-Yu Chiu;Yan-Qing Chen;
      Pages: 6072 - 6077
      Abstract: In this work, the nonvolatile memory constructed on the tunnel thin-film transistors (tunnel-TFTs) using polycrystalline-silicon channel featuring ferroelectric HfZrOx layer is demonstrated for the first time. When the pulse voltages of program (PG) and erase (ER) are, respectively, 3.5 and −2 V with the pulsewidth of $1 ~mu text{s}$ , the threshold voltage modulation amount of the ferroelectric tunnel-TFT can reach −0.524 and 0.496 V, respectively. In addition, the endurance behaviors of the ferroelectric tunnel-TFT exhibit a strong PG/ER pulsewidth dependence. The wake-up effect of the ferroelectric layer becomes more pronounced as increasing the PG/ER pulsewidth. Moreover, the increase of the PG/ER pulsewidth also causes the ferroelectric tunnel-TFT to be subjected to the electrical dynamic stress effect, leading to the degradation of the subthreshold swing (SS) and the electron trapping effect. When the pulsewidth is 100 ns, the endurance is mainly dominated by the fatigue effect of the ferroelectric layer and the degradation of the SS. When the pulsewidth increases to $1 ~mu text{s}$ , the endurance is mainly dominated by the electron trapping effect of the ferroelectric layer in addition to the fatigue effect. The retention of the ferroelectric tunnel-TFT exhibits stable behavior at 50 °C. Consequently, the ferroelectric tunnel-TFT exhibits sufficient electrical performance and can be integrated with display panels and various sensor systems on smart wearable devices for edge computing applications.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling
           Compact SRAM Design—Part I: Device Concept

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      Authors: Peng Wu;Mengyuan Li;Bo Zhou;Xiaobo Sharon Hu;Joerg Appenzeller;
      Pages: 6078 - 6084
      Abstract: Tunnel diodes (TDs) and resonant tunneling diodes (RTDs) with negative differential resistance (NDR) have attracted interest in implementing high-density, low-power circuits, such as static random access memory (SRAM). However, the low peak-to-valley current ratios (PVCRs) in these devices cause high static leakage currents, leading to poor performance in the circuits and limiting their application. This article presents a novel device, i.e., a cross-coupled gated tunneling diode (XTD), that exhibits NDR with PVCRs exceeding $10^{{5}}$ . The device design is validated by TCAD simulation as well as an experimental demonstration. In contrast to conventional TDs, which operate in the forward bias direction, the XTD operates in the reverse bias direction, thus suppressing thermionic emission and trap-assisted tunneling (TAT) currents, which together allow for the large PVCR. In Part II of this article, we continue to discuss compact, low-power SRAM cells based on the XTD.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling
           Compact SRAM Design—Part II: SRAM Circuit

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      Authors: Mengyuan Li;Peng Wu;Bo Zhou;Joerg Appenzeller;Xiaobo Sharon Hu;
      Pages: 6085 - 6088
      Abstract: In Part I of this article, we present a novel device, i.e., a cross-coupled gated tunneling diode (XTD), which exhibits negative differential resistance (NDR) with peak-to-valley current ratios (PVCRs) exceeding 105. In this part of this article, based on the XTD, we introduce a compact static random access memory (SRAM) cell using a one-transistor and two-XTD (1T-2X) design. The layout of the SRAM cell as well as a detailed analysis of the cell behavior and SRAM array performance are presented. In particular, our simulation results show that the 1T-2X SRAM cell can achieve $70times $ improvement in standby power with ~ $8times $ area reduction compared to standard CMOS SRAM.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Single-Event Upset in 3-D Charge-Trap NAND Flash Memories

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      Authors: Jounghun Park;Jin-Woo Han;Gilsang Yoon;Donghyun Go;Donghwi Kim;Jungsik Kim;Jeong-Soo Lee;
      Pages: 6089 - 6094
      Abstract: The effects of single-event upset (SEU) on the threshold voltage ( ${V}_{T}$ ) of a programmed cell in 3-D charge-trap (CT) NAND flash memory have been investigated using 3-D technology-computer-aided design (TCAD) simulations. After ion strikes, the surrounding electric field ( ${E}$ -field) accelerates the generated holes into the CT layer (CTL), which lowers ${V}_{T}$ of the programmed cell. The tunneling oxide (TOX) strike causes a more severe ${V}_{T}$ shift than the blocking oxide (BOX) strike due to the higher ${E}$ -field in the TOX layer. As the strike angle increases from 0° (lateral) to 90° (vertical), the effective irradiation volume is reduced, resulting in the mitigation of the SEU influence. Scaling of cell dimensions becomes more vulnerable to SEU except for the thinner TOX.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal
           Methodology Using Sensitivity With Respect to Parasitic - and -Values

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      Authors: Yanna Luo;Lei Cao;Qingzhu Zhang;Yu Cao;Zhaohao Zhang;Jiaxin Yao;Gangping Yan;Xuexiang Zhang;Weizhuo Gan;Jiali Huo;Haoqing Xu;Guoliang Tian;Weihai Bu;Yongqin Wu;Zhenhua Wu;Huaxiang Yin;
      Pages: 6095 - 6101
      Abstract: Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit introduced by new transistor architectures. In this article, we propose a universal methodology to determine the layout optimization direction of 6T static random-access memory (6T-SRAM) cells by studying the sensitivity of 6T-SRAM cell performance to various parasitic parameters. And adopt this method to optimize the CFET SRAM cell layout structure under the advanced nodes beyond 3 nm. The performances of CFET 6T-SRAM cells with different layout schemes are comparatively evaluated. It is found that the influence of the parasitic resistance on 6T-SRAM performances is double-sided, and parasitic resistances from transistor to power rail ( ${R}_{mathrm {pds}}$ , ${R}_{mathrm {pud}}$ ) and from access (AX) devices to bit-lines (BLs) ( ${R}_{mathrm{bax}}$ ) have the most important effect on improving read noise margin (RNM) together with write margin (WM). The BL-first scheme with reduced ${R}_{mathrm{bax}}$ and increased ${R}_{mathrm {pud}}$ is proven to have 76.3% improvement in WM and 122.5% decrease in write time (WT) compared to the BL-last scheme, and a 63.8% improvement in RNM compared to conventional nanosheet architecture. Further optimized ${R}_{mathrm{bax}}$ in the buried-BL scheme is proven to have higher WM, as well as lower WT.-The BL-first scheme and buried-BL scheme is proven to be the most efficient approach to boost CFET SRAM performance.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Effect of Temperature on Analog Memristor in Neuromorphic Computing

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      Authors: Yifu Huang;Reed Hopkins;David Janosky;Ying-Chen Chen;Yao-Feng Chang;Jack C. Lee;
      Pages: 6102 - 6105
      Abstract: In this article, the influence of the temperature instability of resistive memory switching on potential neuromorphic computing applications is extensively studied using an Intel TaOx-based analog-type memristor as a synaptic weight modulator in a neural network. Evaluation results show that the effect of ambient temperature during training and interference can degrade the neural network’s accuracy due to inefficient weight updates and inevitable resistance or conductance drifting. Our results provide additional insights into device-level physical models and simple circuit-level design guidance for potential hardware-based neuromorphic computing applications.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Exploration of Scandium Doping in SbTe for Phase Change Memory
           Application

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      Authors: Marinela Barci;Daniele Leonelli;Xue Zhou;Xiaojie Wang;Daniele Garbin;Ganesh Jayakumar;Thomas Witters;Nathali Franchina Vergel;Shreya Kundu;Senthil Vadakupudhu Palayam;Huifang Jiao;Hao Wu;Gouri Sankar Kar;
      Pages: 6106 - 6112
      Abstract: In this work, we fabricate and electrically demonstrate a 65-nm technology-compatible Phase change memory (PCM) pillar device using Sc-doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on a 300-mm wafer in the 1T1R configuration. ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to $1~mu text{s}$ for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. The fabricated devices show the potential to extend the PCM technology toward high-speed storage class memory (SCM) applications.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A New Design Paradigm for Auto-Nonvolatile Ternary SRAMs Using
           Ferroelectric CNTFETs: From Device to Array Architecture

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      Authors: Mohammad Khaleqi Qaleh Jooq;Mohammad Hossein Moaiyeri;Khalil Tamersit;
      Pages: 6113 - 6120
      Abstract: Preserving the data stored in a static random access memory (SRAM) during power gating or a sudden power outage is a necessary but costly need. This work proposes an ultraefficient auto-nonvolatile ternary SRAM (ATSRAM) cell using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs). By harnessing the unique features in Fe-CNTFETs, the proposed ATSRAM utilizes only 12 transistors. The proposed design can automatically perform backup and restore operations without additional resources and nonvolatile elements during a power outage. This unique specification eliminates the redundancies usually required to provide nonvolatility. The utilized hysteretic cross-coupled two-transistor standard ternary inverters (STIs) provide a superior static noise margin (SNM) beyond the binary SRAMs and the ideal noise margin limitation ( ${V}_{text {DD}}$ /4). The proposed ATSRAM array structure benefits from a row-shared supply disconnector to mitigate the static current drawn from the power supply during data retention. Our results demonstrate that the proposed ATSRAM indicates, on average, 40% improvement in transistor count, 2.8 times higher SNMs, 27% reduction in total power consumption, and 41% (66%) improvement in the read (write) energy compared with the state-of-the-art volatile ternary SRAMs. In a ${32} times {32}$ ternary array configuration, 94% (98%) improvement in the read (write) energy is obtained compared with the other counterparts. Our design methodology provides a new paradigm for designing ultraefficient and ultracompact nonvolatile multivalued logic (MVL) memories using ferroelectric-based FETs.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Impact of Interface Traps in Floating-Gate Memory Based on Monolayer
           MoS

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      Authors: G. Giusi;G. M. Marega;A. Kis;G. Iannaccone;
      Pages: 6121 - 6126
      Abstract: Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatile memories (NVMs) based on 2DMs. In this work, using technology CAD simulations and model calibration with experiments, we show that the experimental program/erase characteristics of floating-gate (FG) memory devices based on monolayer molybdenum disulphide can be explained by considering bandgap trap states at the dielectric–semiconductor interface. The simulation model includes a classical approach based on drift-diffusion longitudinal channel transport and on nonlocal Wentzel–Kramers–Brillouin (WKB) tunneling for transversal transport (responsible of FG charging/discharging) and for tunneling at contacts. From hysteresis and pulse programming simulations on scaled devices, we find that the long-channel programming window is still maintained at $sim 100$ nm and that process improvements aimed at reducing the concentration of interface traps in the semiconducting bandgap could significantly optimize memory operation.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for
           SRAM-Based Cache Memory Applications

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      Authors: Shubham Tayal;Billel Smaani;Shiromani Balmukund Rahi;Abhishek Kumar Upadhyay;Sandip Bhattacharya;J. Ajayan;Biswajit Jena;Ilho Myeong;Byung-Gook Park;Young Suh Song;
      Pages: 6127 - 6132
      Abstract: In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO2). Specifically, TiO2-based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature ( ${T}_{text {MAX}}$ ) from 564 to 431 K, which enables the improvement of electron mobility ( $mu _{text {electron}}$ ) by 53.1%. In addition, the proposed device structure shows the improvement of ON-current ( ${I}_{text {on}}$ )/gate current ( ${I}_{text {gate}}$ ), by 18%/1000%, compared to hafnium oxide (HfO2)-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of hold-signal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Reliability Improvement of Gate-All-Around Junctionless SONOS Memory by
           Joule Heat From Inherent Nanowire Current

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      Authors: Jung-Woo Lee;Joon-Kyu Han;Myung-Su Kim;Ji-Man Yu;Jin-Woo Jung;Seong-Yun Yun;Yang-Kyu Choi;
      Pages: 6133 - 6138
      Abstract: Endurance to cyclic program/erase (P/E) was experimentally improved by Joule heat from inherent nanowire current ( ${I}_{nanowire}$ ) in a gate-all-around (GAA)-based junctionless (JL) silicon channel (S), tunneling oxide (O), charge trap nitride (N), blocking oxide (O), and poly-silicon gate (S) (SONOS) flash memory. Bulk conduction in the JL structure is favorable to flow ${I}_{nanowire}$ across a source and a drain to generate Joule heat for electro-thermal annealing (ETA). Increased temperature ( ${T}$ ) arising from Joule heat was utilized to cure the damage caused by iterative P/E operations. To quantitatively evaluate the level of induced damage by P/E cycling and cured damage by Joule heat, border trap density ( ${N}_{bt}$ ) in a tunneling oxide was analyzed through low-frequency noise (LFN) measurements. Stress-induced leakage current (SILC), which is related to bulk trap density ( ${N}_{bulk}$ ), was measured and compared before and after ETA. The operation-induced damage was mostly recovered by ETA, which does not require any structural change to drive Joule heat or to make an extra nanoheater.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • An Analytical Drain Current Model of ZnO-Based Amorphous Oxide
           Semiconductor Thin-Film Transistors

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      Authors: Fei Yu;Zhaoxu Song;Kun Fang;Ying Liang;Gongyi Huang;Chuanzhong Xu;Jiahui Liu;
      Pages: 6139 - 6145
      Abstract: An analytical one-piece drain current model of ZnO-based amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) is presented in this article. This model is able to solve the main obstacle in a lack of analytical and physics-based nonregional device modeling for AOSTFTs and is suitable to be implemented into circuit simulators. Based on the effective-charge-density approach, free carrier density and localized carrier density, including tail and deep states, are unified into total carrier density. Then, one-piece surface potential is derived analytically from equivalent 1-D Poisson’s equation described in an effective-charge-density approach. It is also possible that channel carrier mobility is calculated from the ratio between free carrier and effective total carrier densities. Furthermore, drain current expression is derived analytically and validated by experimental data. Good agreements of ${I}$ – ${V}$ characteristics prove that the proposed model could serve as a useful simulation tool implemented into circuit simulators.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Enhanced Electrical and Mechanical Performance of InSnZnO TFTs With
           Multifunctional Laminated Organic Passivation Layer

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      Authors: Delang Lin;Xiang Li;Wei Zhong;Changjian Zhou;Linfeng Lan;Rongsheng Chen;
      Pages: 6146 - 6153
      Abstract: To realize high-performance and stable electrical characteristics for ZnO-based thin-film transistors (TFTs) under various environments, we propose InSnZnO (ITZO) TFTs with multifunctional laminated organic (MLO) passivation layers (PVLs). The MLO PVLs were constructed from self-assembled monolayers (SAMs) and an ultraviolet (UV) light absorber-modified polydimethylsiloxane (PDMS) layer. The SAMs can passivate the ITZO surface and suppress the chemical reaction during the spin-coating process, and the modified PDMS layer can block UV light. The MLO-treated ITZO TFTs exhibited a high-performance and robust stability with high mobility (~21.18 cm2 $cdot $ V−1 $cdot $ s−1), a considerable ON– OFF current ratio (~ $6.65times10$ 9), and a steep subthreshold slope (~100 mV/dec). The shift of the threshold voltage ( ${textit V}_{{mathrm {th}}}$ ) under gate bias stress and UV light illumination stress was investigated for the devices with different PVLs. The ITZO TFTs with MLO PVLs showed improved stability under positive gate bias stress (PBS), positive gate bias illumination stress (PBIS), and negative gate bias illumination stress (NBIS) compared to untreated and SAM-treated ITZO TFTs. Furthermore, the MLO-treated ITZO TFTs achieved a weak response to 365-nm UV light and showed superb stability with the negligible change of electrical performance, even after a 1-h water soaking test and a 100-day storing test. In addition, the MLO PVL exhibited high flexibility without signs of cracking even after 10 000 bending cycles and was proven suitable for fabricating flexible ox-de TFTs.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Low-Frequency Noise Modeling of Amorphous Indium–Zinc-Oxide
           Thin-Film Transistors

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      Authors: Weijie Ye;Yuan Liu;Bingqi Wang;Junkai Huang;Xiaoming Xiong;Wanling Deng;
      Pages: 6154 - 6159
      Abstract: An improved model for the low-frequency noise (LFN) of amorphous indium–zinc-oxide thin-film transistors (a-IZO TFTs) is developed in this article. For a-IZO TFTs, the LFN is not only attributed to the oxide traps in the gate insulator but also affected by the discrete trap centers in the active-layer film. This makes the device has excess noise in the subthreshold region, which is obviously different from monocrystalline silicon (c-Si) MOSFETs. Therefore, we put forward an accurate and physically meaningful model to characterize this excess noise. For the subthreshold region, the charge of tail states in the channel is considered to describe the excess subthreshold noise, and the channel density of states (DOS) is extracted, confirming the effectiveness of the model. For the above-threshold region, the classic carrier number with correlated mobility fluctuation ( $Delta N$ – $Delta mu $ ) mechanism has been investigated to explain the noise behavior. Furthermore, the proposed unified model is validated, and it has been successfully applied to a-IZO TFTs with different tail-state densities.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • An Advanced Full Adder Based Arithmetic Logic Unit (ALU) Using
           Low-Temperature Poly-Si Oxide TFTs

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      Authors: Hansai Ji;Di Geng;Xichen Chuai;Xinlv Duan;Qian Chen;Wanming Wu;Chuanke Chen;Wenfeng Jiang;Jin Jiang;Ling Li;
      Pages: 6160 - 6165
      Abstract: This work presents a full adder-based CMOS arithmetic logic unit (ALU) made of p-type low-temperature poly-Si (LTPS) and n-type amorphous indium–gallium–zine oxide (a-IGZO) thin-film transistors (TFTs). The p-type TFT performs the maximum field-effect mobility ( $mu $ ) of 70 cm2/V $cdot $ s and subthreshold swing (SS) of 0.6 V/decade. The n-type TFT exhibits the mobility of 10.8 cm2/V $cdot $ s and SS of 0.4 V/decade. The six-clock signals and three-supply voltage are employed to obtain a full output swing from high output voltage to low output voltage, where three clocks are used for selection operation mode and three clocks are input signals. For input swing of −15 to 15 V, constant high voltage of 15 V, and low voltage of 0 V, the proposed ALU shows a full output swing of 0–15 V with a fast fall time of $32~mu text{s}$ and a rise time of $64~mu text{s}$ in the worst situation. The proposed ALU is fully cascadable with five functionalities. The first LTPO CMOS-based ALU circuit demonstrates the potentiality of this emerging technology in logic operation.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Hybrid GaO/AlGaN/GaN Ultraviolet Detector With Gate Metal in the Grooved
           AlGaN Layer for Obtaining Low Dark Current and Large Detectivity

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      Authors: Zupin Liu;Chunshuang Chu;Bingxiang Wang;Guansen Huang;Ke Jiang;Yonghui Zhang;Xiaojuan Sun;Zi-Hui Zhang;Dabing Li;
      Pages: 6166 - 6170
      Abstract: In this work, a metal/Ga2O3/AlGaN/GaN hybrid-structured metal–semiconductor–metal ultraviolet photodetector (MSM UV PD) with low dark current has been proposed and fabricated. In the dark condition, the depletion region formed by the metal gate and the AlGaN layer pinches off the two-dimensional electron gas (2DEG) channel, and we can obtain a dark current even lower than 10−10 A/cm2. In the illumination condition, due to the electric field formed by the metal and the Ga2O3 layer, the photogenerated electrons will move to the AlGaN/GaN channel to form the 2DEG. We then get a photo-to-dark current ratio of $8.77times10$ 8. Furthermore, the detectivity of the device is higher than $3.30times10$ 12 Jones when a 254-nm UV illumination signal is applied.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Photoconductive and Photovoltaic Properties of Dual-Junction
           Thin-Film-Based Er-Doped ZnO/MoS/P-Si Heterostructure

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      Authors: Richa Singh;Anshika Srivastava;Ajay Kumar Dwivedi;Shweta Tripathi;
      Pages: 6171 - 6177
      Abstract: This work features the photoconductive and photovoltaic phenomenon of fabricated heterostructure erbium (Er)-doped zinc oxide (ZnO)/molybdenum disulfide (MoS2)/P-silicon (P-Si). The proposed structure shows good performance in terms of detection range, covering ultraviolet (UV) to near-infrared (NIR) region with a peak responsivity of 9.08 A/W, a detectivity of $4.8times 10^{{13}}$ Jones at −1 V, and a self-detection of 0.08 A/W at 0 V. This outstanding photodetection in reverse bias is due to the efficient carrier separation facilitated by MoS2/P-Si and Er-ZnO/MoS2 interface. The device also exhibits solar cell-like properties with open-circuit voltage ( ${V}~_{text {OC}}$ ), short-circuit current density ( ${J} _{text {SC}}$ ), and power conversion efficiency (PCE) of 0.170 V, $3.41times 10^{-{2}}$ mA/cm2, and 1.2%, respectively. This solar cell-like performance is due to the built-in voltage created at the MoS2/P-Si junction.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A CMOS-Compatible Photonic Demodulator With Low-Power Consumption for
           Time-of-Flight Image Sensor

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      Authors: Shun-Qi Dai;Cristine Jin Estrada;An-Nan Xiong;Chen Xu;Jie George Yuan;Mansun Chan;
      Pages: 6178 - 6183
      Abstract: This article presents a CMOS-compatible low-power photonic demodulator for time-of-flight (ToF) CMOS image sensor. The proposed device called the junction-assisted photonic demodulator (JAPD) uses electric field applied through two guide electrodes to facilitate the collection of optically generated minority carriers but using a p-n junction to prevent direct majority carrier current. A prototype of the JAPD has been fabricated in a 0.18- $mu text{m}$ standard CMOS foundry process. Experimental results show that it can achieve a low-power consumption of 29 fW per pixel and a high modulation contrast (MC) of 98%. Through process optimization, it is shown that the optical window can be fully depleted during the demodulation process. In TCAD simulation, the frequency response can be significantly improved by ensuring full depletion of the optical window.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Origin of the Low-Frequency 1/f Noise of a Photoelectrochemical
           Photodetector

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      Authors: Jiaxun Song;Kaixiang Shu;Jialin Wang;Xingfu Wang;Nengjie Huo;Richard Nötzel;
      Pages: 6184 - 6187
      Abstract: The low-frequency photocurrent noise power density ${S}_{I}$ of a self-powered photoelectrochemical photodetector (PEC PD) based on InGaN/Cu2O core–shell nanowire p-n junctions follows a 1/ ${f}^{beta }$ frequency dependence. The exponent $beta $ increases from 1.5 to about 2 with increase of the photocurrent density ${I}_{p}$ . ${S}_{I}$ strongly deviates from the standard quadratic ${I}_{p}$ dependence with an exponent of 1.6. The noise behavior of the dark current density driven by an external voltage is very similar. $beta $ distinctly depends on the NaI electrolyte concentration. Hence, the physical origin of the low-frequency 1/ ${f}^{beta }$ noise is the redox noise generated by the Faradaic charge transfer at the electrode-electrolyte interface. The redox noise dominates the total noise of the PEC PD.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • TCAD Calibration at Cryogenic Temperatures for CMOS Image Sensor
           Simulations

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      Authors: O. Marcelot;A. Panglosse;P. Martin-Gonthier;V. Goiffon;
      Pages: 6188 - 6194
      Abstract: A simple calibration method is presented for the technology computer-aided design (TCAD) simulation at cryogenic temperature, with a special focus on image sensor application. Based on the principle that TCAD tools are not completely mature for cryogenic environment, a calibration is needed to perform reliable simulations. In this work, measurements and simulations of sheet resistances are used for the TCAD calibration, and an experimental verification is performed by means of the extraction of pinning voltages on JFETs and on a pixel including a pinned photodiode (PPD).
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Degradation in Efficiency of InGaN/GaN Multiquantum Well Solar Cells With
           Rising Temperature

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      Authors: Hengsheng Shan;Yun-Jian Mei;Ning Wang;
      Pages: 6195 - 6200
      Abstract: In this article, the authors theoretically and experimentally investigate the mechanism of degradation of InGaN/GaN multi-quantum well (MQW) solar cells. InGaN/GaN MQW solar cells with chips of size $1times1$ mm2 were fabricated and characterized within a range of temperature of 50 °C–250 °C to determine the effects of dislocations on their efficiency. The internal intensity of X-ray diffractions was used to construct a 2-D physical model of the density of edge dislocations in the InGaN/GaN MQW that was then simulated in Silvaco. The results show that the relative error in $eta $ between the simulation and the experiment was less than 5% over the examined range of temperature. This shows that an intensified number of nonradiative recombinations owing to high temperature contribute to edge dislocations that eventually degrade the performance of photoelectric devices. The work here provides a theoretical and experimental basis for the growth of high-quality InGaN materials to fabricate highly efficient solar cells.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Self-Powered Short-Wavelength Infrared Photodetectors Composed of
           MXene/InGaAs Heterostructures

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      Authors: Chao Xie;Jiyu Xu;Yi Wang;Wenhua Yang;Yuyi Zhao;Siliang Wang;Hao Liu;Qi Wang;Xueguang Yuan;Wei Zeng;Zhixiang Huang;
      Pages: 6201 - 6205
      Abstract: High-performance short-wavelength infrared (SWIR) photodetectors are vital components of many optoelectronic devices with extensive uses in military and civilian domains. In this work, we report on a highly sensitive SWIR photodetector composed geometrically of a two-dimensional Ti3C2 ${text {T}}_{x}$ MXene/three-dimensional In0.53Ga0.47As heterostructure, which can be assembled via an easy solution processable drop-casting approach. Owing to the notable photovoltaic activity, the heterostructure can operate in self-powered mode at zero bias with ${I}_{text {light}}/I_{text {dark}}$ ratio of up to ${5}.{8} times {10}^{{3}}$ . Significantly, the device exhibits decent responsivity of about 86.4, 56.2, and 45.5 mAW−1 at infrared wavelengths of 970, 1300, and 1550 nm, respectively. Additionally, other critical performance parameters including specific detectivity and response speed are exceeding 1010 Jones and 39/ $35~mu text{s}$ , respectively. It is expected that this work will pave a facile way for developing SWIR photodetectors with good performance and low cost.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • High-Pixel-Density 960 × 540 Flip-Chip AlGaInP Red MicroLED Display

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      Authors: Meng-Chyi Wu;Zi-Liang Hsu;Cheng-Yeu Wu;
      Pages: 6206 - 6211
      Abstract: This article reports the active matrix (AM) 630-nm red flip-chip $960times540$ micro-light-emitting diode (MicroLED) displays with high pixels per inch (PPI) of 1600. A novel p-side-up AlGaInP thin-film structure by a wafer-transfer technique onto the sapphire substrate is proposed to fabricate the $960times540$ MicroLED array. In addition, the single pixel with a diameter of $10~mu text{m}$ on the MicroLED array exhibits excellent characteristics, including a forward voltage of 1.96 V at $17.4~mu text{A}$ , an extremely low leakage current of 90 fA at −10 V, and a high light output power of $94~mu text{W}$ at 1 mA. The highest external quantum efficiency (EQE) is 5.3% at 330 A/cm2 for the single pixel of MicroLED. The operability and lightening pixels of flip-chip bonding to AM driver IC analyzed by software image J are 80.21% and 415 808, respectively. Through flip-chip bonding technology, the $960times540$ MicroLED display can demonstrate the high-resolution graphic and video images. It is a prospective technology for the application of augmented and virtual realities (AR and VR) and optogenetic neural stimulation.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Graphene/PtSe/Pyramid Si van Der Waals Schottky Junction for
           Room-Temperature Broadband Infrared Light Detection

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      Authors: Longhui Zeng;Wei Han;Shuo-En Wu;Di Wu;Shu Ping Lau;Yuen Hong Tsang;
      Pages: 6212 - 6216
      Abstract: Uncooled infrared (IR) photodetection has attracted increasing research interest due to its important applications in civil and military fields. Recently, platinum diselenide (PtSe2), a newly discovered group-10 two-dimensional (2D) noble metal dichalcogenide (NMD) member, has emerged as an attractive candidate for highly sensitive IR photodetection due to its layer-dependent bandgap transition from semiconductor to semimetal, wide optical absorption, and high carrier mobility. Here, we demonstrate the successful assembly of PtSe2/pyramid Si mixed-dimensional van der Waals (vdW) Schottky junction with a graphene transparent electrode. Due to the novel vertical device structure with a graphene top contact, the photodetector achieves an appealing device performance, including an ultrabroadband response up to $10.6~mu text{m}$ , a high responsivity of 0.528 A/W, a large specific detectivity of ~1012 Jones, and a fast response time of $8.2~mu text{s}$ at zero bias voltage. More importantly, these findings have enabled the realization of an excellent room-temperature long-wave IR (LWIR) imaging capability and its utilization as an optical receiver in optical IR communication. Our work demonstrates a reliable approach to the construction of a high-performance Schottky junction device for room-temperature broadband IR photodetection.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • An 11–40-GHz High-Power Switch With Miniaturized High-Order Topology
           Using 100-nm GaN-on-Si HEMTs

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      Authors: Guangxu Shen;Haoshen Zhu;Quan Xue;Wenquan Che;
      Pages: 6217 - 6224
      Abstract: This article proposes an ultrawideband switch with miniaturized high-order topology. A 100-nm gate-length GaN-on-Si process is used for high-power capability, and the modeling of the GaN high-electron-mobility transistors (HEMTs) is given to analyze its parasitic values. For wideband or high isolation, the high-order switch is one solution, whose die area is naturally large. To address this issue, a miniaturized coupled-resonator switch topology was proposed using inverter transformation, where two parallel LC tanks and four inverters are replaced by two series LC tanks. Furthermore, a miniaturized coupling structure is introduced using a common inductor to replace three individual ones, contributing to an 86% size reduction. For demonstration, one 11–40.5-GHz single-pole single-throw (SPST) switch with four transmission poles (TPs) has been designed and fabricated. A small chip size of 0.32 mm2, low ON-state minimum insertion loss (IL) of 0.55 dB, and a high-power capability of 1.3 W are achieved.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Comparison of Commercial Planar and Trench SiC MOSFETs by Electrical
           Characterization of Performance-Degrading Near-Interface Traps

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      Authors: Mayank Chaturvedi;Sima Dimitrijev;Daniel Haasmann;Hamid Amini Moghadam;Peyush Pande;Utkarsh Jadli;
      Pages: 6225 - 6230
      Abstract: The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO2 interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Vertical Diamond Trench MOS Barrier Schottky Diodes With High Breakdown
           Voltage

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      Authors: Juan Wang;Guoqing Shao;Qi Li;Genqiang Chen;Xiuliang Yan;Zhiqiang Song;Yanfeng Wang;Ruozheng Wang;Wei Wang;Shuwei Fan;Hong-Xing Wang;
      Pages: 6231 - 6235
      Abstract: We carried out the first experimental demonstration of vertical diamond trench MOS barrier Schottky (TMBS) diodes. The electrical properties of fabricated diamond TMBS diodes with varied mesa width ( ${W}_{text{mesa}}$ ) were investigated by current–voltage and capacitance–voltage (CV) measurements at room temperature. Diamond TMBS diodes exhibit enhanced reverse blocking capability while maintaining good forward conduction characteristics. The breakdown voltage (BV) of TMBS diode with ${W}_{text{mesa}}$ of $2 ~mu text{m}$ reaches up to 265 V, which is 54% higher than that of the regular Schottky diode without trench MOS structure. This indicates that diamond TMBS diodes have significant potential for high-power application in the future.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Reverse Blocking Diode Thyristor With High Di/Dt Capability for Explosive
           Foil Initiator Applications

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      Authors: Zhengheng Qing;Lin Liang;Xinyuan Huang;
      Pages: 6236 - 6240
      Abstract: High-voltage switch with high current and high current rise rate capability is important in explosive foil initiator (EFI) applications because the current with high amplitude and short rise time is necessary in order to gasify the explosive foil. In this work, reverse blocking diode thyristor (RBDT) for this application is optimally designed and fabricated. The 2-D numerical model of RBDT is first established. Based on this model, the cathode layout and the doping concentration of P base layer of the device are carefully analyzed. The cell size and the length ratio of the emitter to the short-circuit point at cathode are analyzed. Samples of RBDT are developed in our laboratory, with the blocking voltage of 1600 V. The peak current of 2400 A is acquired in the pulse discharge experiment, with a maximum current rise rate as high as 18 kA/ $mu text{s}$ , which is the highest $text{d}{i}/text{d}{t}$ value reported for RBDT until now. This result makes the proposed RBDT a promising candidate for EFI applications.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Modeling and Analysis of SiC GTO Thyristor’s Dynamic Turn-On
           Transient

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      Authors: Hangzhi Liu;Jun Wang;Shiwei Liang;Hengyu Yu;Gaoqiang Deng;Yuwei Wang;Z. John Shen;
      Pages: 6241 - 6248
      Abstract: The fast turn-on speed of silicon carbide (SiC) gate-turn-off (GTO) thyristor is preferred for pulse power applications. However, the turn-on delay phenomenon hinders its improvement. In this article, the dynamic turn-on transient process of SiC GTO thyristor is investigated and analyzed extensively by means of both numerical simulation and physical modeling. The physical mechanism behind its turn-on transient process is discussed in detail. A physical model based on the charge-control theory is proposed to identify the dominant factors influencing the dynamic turn-on transient. Then the theoretical analysis is quantitatively made on the parameter design of GTO’s unit cell, and methods to increase the turn-on switch speed are extensively discussed. This study provides not only in-depth physical insights into the device’s turn-on characteristics, but also designs guidelines for the advancement of SiC GTO thyristor.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Low-Loss Diode Integrated SiC Trench MOSFET for Improving Switching
           Performance

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      Authors: Jiawei Ding;Xiaochuan Deng;Songjun Li;Hao Wu;Xu Li;Xuan Li;Wanjun Chen;Bo Zhang;
      Pages: 6249 - 6254
      Abstract: A novel silicon carbide (SiC) asymmetric trench MOSFET with integrated low-loss diode (LLD-ATMOS) is proposed and investigated by numerical simulations to reduce switching loss and eliminate bipolar degradation of body diode. The N-channel region beneath the dummy gate provides a low barrier path to transport electrons form the N-drift layer to N+ source region, with the result that the forward conduction voltage drop is reduced from 3.5 V at 10 A of the pn body diode to 1.9 V at 10 A of the LLD-ATMOS. Furthermore, the reverse recovery charge (QRR) of LLD and the gate-to-drain capacitance ( ${C}_{text {gd}}$ ) of LLD-ATMOS are 76% and 95% lower than those of the conventional asymmetric trench MOSFET (C-ATMOS). As a result, the turn-off and turn-on losses of LLD-ATMOS are reduced by 49% and 58%, respectively. The calculated high-frequency figure of merit ( $text {HF-FOM} = {R}_{ {{text{ON}}},text {sp}} times {C}_{text {gd}}$ ) of LLD-ATMOS is tremendously decreased to one-fourteenth of the value of C-ATMOS. In addition, a conduction band energy analysis model for the LLD is developed. The improved performances suggest that LLD-ATMOS is a competitive option in power electronic systems.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • High Breakdown Voltage and High Current Injection Vertical GaN-on-GaN p-n
           Diodes With Extremely Low On-Resistance Fabricated on Ammonothermally
           Grown Bulk GaN Substrates

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      Authors: Andrzej Taube;Maciej Kamiński;Jarosław Tarenko;Oskar Sadowski;Marek Ekielski;Anna Szerling;Paweł Prystawko;Michał Boćkowski;Izabella Grzegory;
      Pages: 6255 - 6259
      Abstract: In this work, we report fabrication and characterization of high breakdown voltage and high current injection vertical gallium nitride (GaN)-on-GaN p-n diodes with an etched mesa structure with guard rings termination on ammonothermally grown bulk GaN substrates. Bright electroluminescence from active region under forward bias was observed with high intensity near band edge emission and low intensity defect and unintentional impurities-related bands. Fabricated devices were characterized by a high breakdown voltage up to 1940 V, a high on/off current ratio over $10^{{13}}$ , a high current density above 10 kA/cm2, and an extremely low ON-resistance below 0.1 $text{m}Omega $ cm2 under high current injection.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Improved-Performance Diamond Schottky Barrier Diode With Tin Oxide
           Interlayer

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      Authors: Shumiao Zhang;Juan Wang;Qi Li;Guoqing Shao;Genqiang Chen;Shi He;Ruozheng Wang;Wei Wang;Renan Bu;Feng Wen;Hong-Xing Wang;
      Pages: 6260 - 6264
      Abstract: A SnO2 thin layer was deposited between the diamond and Schottky electrode to fabricate the metal–insulator–semiconductor Schottky barrier diode (MIS-SBD). The current–voltage and current–voltage–temperature characteristics in the range from 25 °C to 150 °C of diamond SBD were investigated. The Schottky barrier height of MIS-SBD is 1.84 eV. Compared with metal–semiconductor (MS) SBD, the diamond MIS-SBD shows more stable values of barrier height and ideality factor as temperature increased. The difference in interface states density between MIS-SBD and MS-SBD is almost 2 orders of magnitude, and the breakdown voltage was increased from 102 to 123 V after introducing SnO2 layer. These results indicate that the MIS-SBD with SnO2 insulating layer shows a better performance.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Warpage Reduction and Thermal Stress Study of Dicing Process in
           Wafer-to-Wafer Bonding Fabrication

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      Authors: Wei Feng;Haruo Shimamoto;Tsuyoshi Kawagoe;Ichirou Honma;Masato Yamasaki;Fumitake Okutsu;Takatoshi Masuda;Katsuya Kikuchi;
      Pages: 6265 - 6269
      Abstract: We successfully study the warpage after wafer-to-wafer (W2W) bonding by the experiments and the full wafer model simulation. Furthermore, the effect of the dicing process on the warpage reduction and the thermal stress of bonded wafer are investigated by varying the dicing pitch from a one pitch as chip size to a quarter pitch. When the dicing pitch decreases to a quarter pitch, the bonded wafer warpage is observed to decrease by 27.8%. A full wafer model is established with the representative volume element (RVE) method in simulation and validated by good agreement with the measured wafer warpage data. The radial stress distribution of bonded wafer indicates tensile stress for the dynamic random access memory (DRAM) layers and compressive stress for the DRAM/Si substrate interface of top and bottom wafers due to the shrinkage of the DRAM layers under the temperature decrease from its high fabrication temperature to the room temperature. The radial stress distribution after the dicing process with different pitches indicates a similar stress level after one-pitch dicing and half-pitch dicing. When the dicing pitch decreases to a quarter value, the compressive stress decreases, correspondingly resulting in a warpage reduction. The stress released by interrupting the continuity of the wafer with a small dicing pitch is revealed to be the origin of wafer warpage reduction. This study provides a guideline of dicing street pitch for warpage reduction and is useful for optimizing the device layout design.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Understanding Early Failure Behavior in 3D-Interconnects: Empirical
           Modeling of Broadband Signal Losses in TSV-Enabled Interconnects

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      Authors: Kevin J. Coakley;Pavel Kabos;Stéphane Moreau;Yaw S. Obeng;
      Pages: 6270 - 6276
      Abstract: We develop an empirical model for measured frequency-dependent insertion loss ( $vert {S}_{{21}}vert $ ). The model parameters are determined with a stochastic optimization implementation of the Levenberg–Marquard method. We compare measured $vert {S}_{{21}}vert $ on through silicon via (TSV)-interconnects, from two different providers, as a function of the extent of thermal annealing. The frequency-dependent changes in the electrical characteristics of the interconnect are attributed to silanol (Si-OH) and other dangling bond polarizations at the Si–SiO interface between the silicon substrate and the lateral silicon oxide that isolates the coaxial metal core from the silicon substrate. The changes in the polarizations are traceable to changes in the chemistry of the isolation dielectric during thermal annealing. The data also suggest that the evolution of the chemical defects inherent in the “as-manufactured” products may be responsible for some of the signal integrity degradation issues and other early reliability failures observed in TSV-enabled 3-D devices.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Ge Content Optimization in Ge(SbSe)N OTS Materials for Selector
           Applications

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      Authors: Camille Laguna;Mathieu Bernard;Frédéric Fillot;Denis Rouchon;Névine Rochat;Julien Garrione;Lucie Prazakova;Emmanuel Nolot;Valentina Meli;Niccolò Castellani;Simon Martin;Chiara Sabbione;Guillaume Bourgeois;Marie-Claire Cyrille;Liviu Militaru;Abdelkader Souifi;François Andrieu;Gabriele Navarro;
      Pages: 6277 - 6283
      Abstract: In this article, we investigate the influence of germanium content in GeSbSeN-based ovonic threshold switching (OTS) selector devices. We performed physico-chemical analyses on five different Gex(SbSe)1–xN alloys to understand how the germanium content influences the material structure and its integrity once submitted to temperatures up to 400 °C. Thanks to the electrical characterization of Gex(SbSe)1–xN OTS devices, we analyze the evolution of the electrical parameters along cycling up to 108 cycles and before and after annealing at 400 °C. Cycle -to -cycle variability and drift phenomenon are also investigated. Finally, we demonstrate how Ge content should be properly tuned to improve the thermal stability of the alloy without affecting the leakage current and the electrical parameters’ variability.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Improved Sensitivity and Stability for SnO Ion-Sensitive Field-Effect
           Transistor-Based pH Sensor by Electrical Double Layer Gate and AlO
           Sensitive Film

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      Authors: Xianghong Yang;Jiapei Ao;Xin Li;Long Hu;Weihua Liu;Chuanyu Han;Xiaoli Wang;
      Pages: 6284 - 6289
      Abstract: Hydrogen ion sensor (pH sensor) with high sensitivity and good stability has great potential in modern life, medicine, industry, and other fields. As a core of the pH sensor, an ion-sensitive field-effect transistor (ISFET) based on SnO2 is paired with a high selectivity Al2O3 inorganic insulating film, which enhances its pH sensitivity. In the presence of a voltage applied to the extended gate, the gate and channel act as capacitance plates, and the sensor is equivalent to an electrical double layer (EDL). The hydrogen ions in solution alter the solution capacitance, which changes the capacitance of the solid dielectric layer, regulating the source–drain current. As a result of this work, the sensitivity of the ISFET-based pH sensor with extended gate increased $15.8times $ to 25.33 nA/pH $cdot text{V}$ when $V_{{mathrm {GS}}}$ is 300 mV, compared to a SnO2-based sensor without the extended gate. Also, the stability of the sensor has been greatly improved, as well as the response time of 0.2 s. Our research provides an effective strategy for high-performance ISFET-based pH sensor, and the concept of using the pH-ISFET with an extended gate for direct quantification of pH values in solutions provides a dependable method for industrial applications.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • CMOS Compatible MEMS Multienvironmental Sensor Chip for Human Thermal
           Comfort Measurement in Smart Buildings

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      Authors: Izhar;Wei Xu;Hadi Tavakkoli;Xu Zhao;Yi-Kuen Lee;
      Pages: 6290 - 6297
      Abstract: In this article, CMOS compatible microelectromechanical systems (MEMS) multienvironmental sensor chip (MESC) is reported. The chip is comprised of temperature, humidity, and air velocity sensors. The MESC has several advantages. First, it incorporates low-cost three-mask CMOS compatible MEMS fabrication process to realize temperature, humidity, and air velocity sensing in the environment. Second, the air velocity sensor on MESC utilizes dual pairs of detectors and is completely released from the substrate, which achieved low-power consumption. Finally, a minimum level of crosstalk effect is observed among the sensors fabricated on MESC. The characterization results indicated that the developed temperature sensor achieved a sensitivity of 20.09 mV/°C, the humidity sensor obtained an average sensitivity of 7.83 fF/%RH, and the air velocity sensor achieved a sensitivity of 312 mV/m/s in dual detectors mode. Furthermore, the crosstalk among sensors on the chip was studied, which suggested that the air velocity sensor can affect the chip (temperature and humidity sensors) temperature by 2 °C–7 °C. This crosstalk is relatively less than the reported multisensor chips (10 °C). The experimental results achieved by the developed MESC make it promising for human thermal comfort (HTC) measurement in smart buildings in the era of the Internet of Things (IoT).
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Flexible Liquid Crystal Thermistor and Its Application in Temperature
           Sensor

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      Authors: Fanxi Meng;Meng Fan;Keming Wu;Jingjing Sun;Minglei Cai;Tongzhou Zhao;Changyong Yang;Yibo Xin;Jun Xing;Hongyu Xing;Wenjiang Ye;
      Pages: 6298 - 6303
      Abstract: Liquid crystals (LCs) are an excellent material for temperature sensors because of their thermistor properties of negative temperature coefficient (NTC). In this study, a flexible thermistor, made by the indium tin oxide (ITO)-polyethylene terephthalate (PET) flexible substrate and the nematic LC (NLC) NHG715600-100 with negative dielectric anisotropic was presented and its application in temperature sensor was explored. It offers low power consumption, high transparency, high sensitivity, and high accuracy achieved through temperature-resistance characteristics. Using ln ${R}$ as the intrinsic variable for characterizing temperature, the sensor achieves a better non-linear fit to the temperature at low voltages and reaches a maximum sensitivity of −6.615%/K at 0.05 V and 500 Hz. The transmittance reaches 61.29%–92.15% in the visible range, and the rising and fall times respectively reduces by 75.19% and 73.38% compared to the rigid LC thermistor. In addition, it also continues to show remarkable stability, recovery, and durability in various tests. Compared with common thermistors, this device is smaller and lighter in weight, resulting in a wider range of applications in temperature sensing.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Experimental Validation on the Industrial Panel-Level Process for
           Producing Solid-State EGFET Sensor Chips

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      Authors: Wei-Sin Kao;Yu-Wen Hung;Wen-Hsiang Liao;Yi-Chen Chou;Che-Hsin Lin;
      Pages: 6304 - 6309
      Abstract: This article presents the experimental validations on an industrial panel-level produced solid-state multisensor for simultaneously pH, electrical conductivity (EC), and temperature detection of solution. Indium tin oxide (ITO) is adopted as the sensing material of the sensor chip due to its good ion selectivity, EC, and linear temperature coefficient of resistance (TCR) characteristics. Meanwhile, thin film deposited Ag/AgCl reference electrode is produced surrounding the sensing electrode to enhance the sensing performance. The sensing chip is produced in the glass substrate and is directly connected to the integrated circuit via a commercial USB-C flexible wire. The experimental results prove that the developed integrated sensor exhibits a high acidity response of 0.1 V/pH ranging from pH 2 to 13. The measured sensitivity is 0.9/°C for temperature detection with a high linearity of 0.9999 and 0.07 V/mS for solution conductivity with the ${R}$ -squared value of 0.9993. The sensing performance of the developed chips is also evaluated by measuring the urine samples of the five volunteers after drinking water, coffee, and beer, respectively. The measured results are also compared with commercial sensors. The developed integrated sensor has shown its potential for rapid and high performance for detecting the pH, ionic strength, and temperature in solution samples.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Advanced Theoretical Models for Broadband Klystron Development

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      Authors: J. C. Cai;J. Xu;S. Chen;Z. X. Su;L. N. Yue;H. R. Yin;G. Q. Zhao;R. Guo;D. G. Shen;W. X. Wang;Y. Y. Wei;
      Pages: 6310 - 6317
      Abstract: Broadband klystrons (BBKs) offer the potential of both high power and broad-bandwidth performance as microwave amplifiers. Staggered tuned bunching circuit and filter-loaded output cavity are the mainstream techniques adopted for developing such devices. However, in the design and optimization stage, the accurate and fast theoretical models are still missing before final particle-in-cell (PIC) simulations are conducted. In this article, the small-signal theory of klystron has been derived from accurate large-signal models used in KlyC, where complex mode field distribution, relativistic effects, mode coupling, and precise space charge model are fully considered in the final analytic formulas compared with existing simplified models. Furthermore, mode coupling theory with partially beam-loading conditions has been developed in KlyC to analyze the filter-loaded output cavity and overall klystron performance in the large-signal domain. An example of the retrofit design of 100-kW five-cavity ${X}$ -band klystron is then presented to demonstrate the advanced design methodology based on the above fast theoretical models. The 3-D PIC simulation finally verifies this BBK design, showing −1-dB bandwidth of 200 MHz is attainable with output power over 100 kW, where the maximum discrepancy between theoretical models and PIC is within 2% in the whole bandwidth.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Optimization of a Cusp Gun With a Grid for a Terahertz Gyrotron
           Traveling-Wave Amplifier

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      Authors: Bo Li;Chong Peng;Huabi Yin;Wenlong He;
      Pages: 6318 - 6321
      Abstract: A magnetic cusp gun with a control grid was optimized through parametric simulations for a gyrotron traveling-wave amplifier with an output power of 10 kW and a central operating frequency of 220 GHz. The ON and OFF of the electron beam are controlled by applying appropriate biases to the grid. An axis-encircling electron beam of current 1.5 A, a pitch factor of 1.23, and a relative pitch-factor spread of ~3.5% were predicted when the gun was operated at 70 kV.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Investigation of a Bifrequency Magnetically Insulated Line Oscillator With
           Ridged-Disk-Loaded Vanes

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      Authors: Mohit Kumar Singh;Manpuran Mahto;Pradip Kumar Jain;
      Pages: 6322 - 6328
      Abstract: In this article, a bifrequency magnetically insulated line oscillator (BFMILO) with ridge-disk-loaded vanes has been investigated in order to increase the device efficiency. The influence of ridged slow wave structure (RSWS) on electromagnetic (EM) characteristics of the BFMILO has been studied in the absence of an electron beam with CST Eigenmode solver. Cold (without electron beam) EM simulation demonstrates the impact of the ridge at the disk tip on the resonance frequency, phase velocity, and coupling impedance of the ridged BFMILO (RBFMILO). It shows that the RSWS can significantly enhance the coupling impedance of the RBFMILO, improving overall power efficiency. The CST particle-in-cell (PIC) simulation has been carried out to assess the RF performance of the RBFMILO. For the input dc voltage of 500 kV and the current of 45 kA, the PIC simulation detects a high-power microwave (HPM) with two frequencies of 3.35 and 3.60 GHz, generating a collective peak RF power of 4.2 GW. The peak power conversion efficiency of the device is 18.7%.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Design and Simulation for 100-Watt-Class 340-GHz Extended Interaction
           Klystron

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      Authors: Fengyuan Zhang;Wenxin Liu;Zhihao Jin;Zhiqiang Zhang;Zhaochuan Zhang;Kedong Zhao;Jin Xu;Yanyu Wei;Feng Lan;Ziqiang Yang;
      Pages: 6329 - 6335
      Abstract: An extended interaction klystron (EIK) working at the frequency of 340 GHz is designed in this present article. The characteristic impedance, coupling coefficient, and normalized electron conductance of the cold cavities are analyzed and optimized. To improve the output power, the EIK adopts a prebunching (PB)-cavity high-frequency structure (HFS). Compared with the conventional terahertz (THz) EIK, the coherence of PB-cavity EIK is enhanced, and the output power is improved. The 3-D particle-in-cell (PIC) simulation predicts the EIK, driven by a 0.20-A, 22.4-kV electron beam confined in a 0.2-mm-diameter beam tunnel, and generates an output power of 138.3 W at the frequency of 339.7 GHz. The gain, electronic efficiency, and 3-dB bandwidth are 39.6 dB, 3.1%, and 500 MHz, respectively. The proposed EIK can be applied to the THz high-resolution radar.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Metamaterial-Inspired Interaction Structure for MW-Level Klystron at 714
           MHz

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      Authors: Xuanming Zhang;Shaozhe Wang;Jianjun Zou;Xin Wang;Yurong Liu;Yongming Li;Zhanliang Wang;Huarong Gong;Yubin Gong;Zhaoyun Duan;
      Pages: 6336 - 6341
      Abstract: A metamaterial (MTM)-inspired interaction structure for MW-level klystron at 714 MHz is proposed. The electromagnetic characteristics of MTM-inspired resonant cavities with single-bridge complementary electric split ring resonators (CeSRRs) are studied, and the cold-tested results confirm the feasibility of miniaturizing the resonant cavity. Furthermore, the beam–wave interaction simulation for the interaction structure constructed by MTM-inspired resonant cavities with single-bridge CeSRRs is carried out, demonstrating 2.28 MW of output power at 714 MHz for a 100 kV, 40 A electron beam. The radius and length of the MTM-inspired interaction structure are 1/2 and 2/3 of the conventional counterparts, respectively. The promising performance makes it attractive for future applications such as linacs.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Efficient, 0.35-THz Overmoded Oscillator Based on a Two-Dimensional
           Periodic Surface Lattice

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      Authors: A. J. MacLachlan;C. W. Robertson;A. W. Cross;A. D. R. Phelps;
      Pages: 6342 - 6347
      Abstract: We present the theory, design, and numerical modeling of a cylindrical, two-dimensional periodic surface lattice (2D-PSL) intended for use as the interaction region of an electron beam-driven, pulsed source. The production of 1.95-MW peak, pulsed 0.35-THz radiation with an electronic efficiency of 24% is reported. Mode selection in the oversized cavity, where the diameter D is almost $3.5times $ larger than the operating wavelength $lambda $ , is achieved by coupling volume and surface fields to form a coupled cavity eigenmode. We demonstrate the advantages (including enhanced output power and improved spectral purity) of using a 2D-PSL over a simpler 1-D structure. The cylindrical ${D}/lambda sim {3.5} 2text{D}$ -PSL demonstrates the “proof-of-principle” high-order mode coupling with the potential to increase ${D}/lambda $ to values of 20 or more for the realization of CW 2D-PSL sources or very powerful pulsed sources. The theory is applicable over a broad frequency range.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Study of the Frequency Self-Modulation in Gyro-TWT Based on Two -Band
           Amplifiers

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      Authors: Yelei Yao;Guo Liu;Wei Jiang;Weijie Wang;Yingjian Cao;Jianxun Wang;Yong Luo;
      Pages: 6348 - 6351
      Abstract: Periodical radiation spectrum with a frequency difference of ~160 MHz is observed in hot-test experiments of Ku-band gyrotron traveling-wave tubes (gyro-TWTs). By the means of eigenmode analyses and particle-in-cell (PIC) simulation considering the whole output transition section from the interaction circuit end to the output window, we found that the circuit oscillation is pronounced because of frequency self-modulation (FSM). As a comparison, the cutoff taper contributing to the FSM is removed and a new amplifier has been developed; hot-test results indicate that the periodical property has been greatly alleviated as expected and the stability of the amplifier is well improved.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Research on Sub-Microsecond Compact L-Band Relativistic Cherenkov
           Oscillator

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      Authors: Peng Zhang;Xingjun Ge;Fangchao Dang;Hang Chi;Hanwu Yang;Juntao He;
      Pages: 6352 - 6357
      Abstract: Prolonging the microwave pulsewidth is an important research direction to improve high-power microwaves’ energy and average power level. In this article, a sub-microsecond compact ${L}$ -band relativistic Cherenkov oscillator (RCO) is studied. The device adopts a coaxial slow wave structure to reduce the radial size and a coaxial collector structure to improve the resonance characteristics of the slow wave structure to reduce the axial size. In particular, a coaxial outer corrugated slow wave structure is used instead of the coaxial double-corrugated slow wave structure to increase the power handling capacity (PHC) of the slow wave structure and reduce its surface electric field. Moreover, the collector structure has been improved to suppress the effects of plasma expansion. In the experiment, the device obtained a high-power microwave output with a microwave frequency of 1.496 GHz, a power of 2.0 GW, a pulsewidth of 317 ns (single pulse energy of 634 J), and a power conversion efficiency of 32%. The pulsewidth and the single pulse energy are the highest levels reported for the RCO.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A 3-D Printed Helix for Traveling-Wave Tubes

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      Authors: G. Ulisse;P. Schürch;E. Hepp;W. W. Koelmans;R. Doerner;V. Krozer;
      Pages: 6358 - 6361
      Abstract: In this work, a 3-D printed copper helix for a traveling-wave tube (TWT) is reported. The fabricated helix was designed to be used in a TWT operating at millimeter-wave frequencies (60–80 GHz). The helix was realized with an additive micromanufacturing technique ( $mu $ AM). Measurements were also performed to estimate the losses of the printed material and evaluate the RF performance of deposited copper. Simulations showed that a TWT based on the 3-D printed helix can have a gain of about 30 dB at 66 GHz and a 1-dB bandwidth of about 5 GHz. The estimated losses from RF measurements reveal an RF copper conductivity of about $2times 10^{{7}}$ S/m, measured in air without any surface cleaning steps, which is a very good value and comparable to bulk copper conductivity in the millimeter-wave range.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Electron Transportation Experiment and Analysis for a G-Band Magnetron
           Injection Gun

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      Authors: Wei Jiang;Boxin Dai;Chaoxuan Lu;Jianxun Wang;Guo Liu;Youlei Pu;Zewei Wu;Yong Luo;
      Pages: 6362 - 6368
      Abstract: The electron beam transportation profile is important for the gyro-traveling-wave tube (Gyro-TWT), and a transportation prototype of Gyro-TWT has been developed. The symmetric-rotating calibration (SRC) method for the superconducting magnet (SCM) alignment is proposed, and the tilt angle and transverse displacement of the magnetic field are reduced from 0.05° to 0.01° and 0.15 to 0.05 mm after alignment, respectively. Then, the beam transportation experiment is done, with a transportation rate of ~85%. The beam trajectory is analyzed and indicates that the stray electron is the main reason for transportation degeneration. Then, a new magnetron injection gun (MIG) with an optimized rear electrode, isolated thermal gap, and antiemission coating is designed and fabricated to enhance the transmission rate. The stability of the new gun is also analyzed, and the stray electron is reduced. Finally, the transportation rate improves to 97.1%, and the transported beam is with a pitch factor of 1.25 and a velocity ratio of 2.5%. The beam quality is good for the interaction circuit.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Understanding the Origin of Unreliable Low-Resistance State During
           Initialization Process

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      Authors: Yiwei Duan;Haixia Gao;Yuxin Sun;Shuliang Wu;Mengyi Qian;Jingshu Guo;Mei Yang;Xiaohua Ma;Yintang Yang;
      Pages: 6369 - 6375
      Abstract: The main factor hindering the massive employment for resistive random access memory (RRAM) can be ascribed to reliability issues. It has been reported that resistive switching (RS) characteristics were unstable during initial ${I}-{V}$ cycles; however, the reason has not been studied yet. In this article, the mechanism for a significant increase in a low-resistance state (LRS) value during the initial cycles has been investigated. In this article, we suggest that the initialization process is actually the formation process of a stable TaOx interface layer between the RS layer and the top electrode (TE). Furthermore, a co-regulation model of the filament-type and the interface-type switching mechanisms on RS behavior is proposed, which explains the complete working process of devices. By reducing the size of the device and increasing the positive stop voltage, the initialization process of the device has been greatly shortened. This article may promote the development of advanced and reliable RRAM devices.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Fast Algorithms for Exact IR Drop De-Embedding in Analog
           Multiply–Accumulate Computing

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      Authors: Shifan Gao;Fan Yang;Cimang Lu;Yi Zhao;
      Pages: 6376 - 6383
      Abstract: IR drop that comes from the line resistance is a well-known issue of the crossbar structure. When the latter is used in the in-memory computing, this issue sets the limit for the analog computing parallelism. In this work, the previously unappreciated linear network modeling is proven to be sufficient for its calibration. Fast algorithms exploiting this simplification are proposed for an exact and efficient de-embedding of the IR drop. Physical pictures are offered for a more intuitive understanding. Scaling in the input and output peripherals is proposed to overcome the dynamic range overflow issue while maintaining the memristor cell precision. An all-in-one-chip MNIST demonstration is presented. Neural network scheduling and gear-like convolution are proposed for real-time processing. Full MNIST test set with the calibration shows a 98.70% accuracy, with 0.45% loss from the software baseline and a 3.58% improvement upon the without-calibration case. Besides inference deployment, these methods may also be generalized to edge learning where the computation resources are limited.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Monte Carlo Analysis of -Type SiGe-Channel Nanosheet
           Performance

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      Authors: F. M. Bufler;H. Arimura;P. Favia;G. Eneman;P. Matagne;N. Horiguchi;G. Hellings;
      Pages: 6384 - 6387
      Abstract: The performance of Si0.75Ge0.25-channel ${p}$ -type nanosheet (NS) devices with a gate length of 14 nm and a sheet width of 12 nm is investigated by Monte Carlo (MC) device simulation. It is found that the stress in the Si–Ge channel can eliminate the performance imbalance with ${n}$ -type NSs arising from the (001) surface in the absence of stress. The performance is the same as the theoretical performance of Si-channel (cSi) ${p}$ -type NSs with Si0.5Ge0.5 source/drain (S/D) pockets under the ideal assumption that no stress relaxation, e.g., due to grain boundaries from merging epitaxial growth occurs for the cSi devices. It is shown that the performance levels can be related to stress-induced quasi-ballistic velocity overshoot and the impact of alloy scattering. This is not captured by standard drift–diffusion (DD) simulation where a smaller saturation velocity predicts a performance degradation for Si–Ge channel devices.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Thermal Conductivity Model to Analyze the Thermal Implications in Nanowire
           FETs

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      Authors: Nitish Kumar;Pragyey Kumar Kaushik;Sushil Kumar;Ankur Gupta;Pushpapraj Singh;
      Pages: 6388 - 6393
      Abstract: In this article, a thermal conductivity ( $kappa $ ) model is proposed (i.e., dependent on the temperature, thickness, and doping concentration) for investigating the thermal behavior of silicon-on-insulator (SOI)-based devices. The proposed model is less complex in calculating the thermal conductivity ( $kappa $ ) compared to the existing model because the analysis of the existing model is complicated due to multiple equations. The proposed model is also easier to implement in the TCAD simulator than the existing model, which is currently being used in the Sentaurus TCAD electrothermal module to study the thermal behavior of the devices. The thermal conductivity ( $kappa $ ) predictions are analyzed using the proposed model, which agrees with the reported experimental data and existing complex analytical models. The thermal behavior of junctionless nanowire (JL-NW) FET is investigated using the sub-5-nm technology node-based physical parameters. It is observed that the thermal behavior depends on the temperature, thickness, and doping concentrations of the SOI devices. The proposed model provides an insightful and accurate analysis of the behavior of the SOI-based nanodimension transistors.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Impact of the Figures of Merit (FoMs) Definitions on the Variability in
           Nanowire TFET: NEGF Simulation Study

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      Authors: Yunhe Guan;Vihar P. Georgiev;Asen Asenov;Feng Liang;Haifeng Chen;
      Pages: 6394 - 6399
      Abstract: In this article, we investigate the effect of variability in p-type nanowire tunnel FET (TFET) using quantum mechanical transport simulations. The simulations have been carried out using the Nano Electronics Simulation Software (NESS) from the University of Glasgow. Random discrete dopants (RDDs) and work-function variations (WFV) have been investigated in the simulations. Our statistical simulations reveal that key figures of merit (FoMs) such as the current variability generally decrease as the gate voltage decreases, the threshold voltage variability increases as the threshold current increases, and the dependences of these FoM variabilities on criteria become stronger with the switch characteristic ameliorated. Furthermore, it is interesting to find that the band offset in heterostructure can more or less alleviate the current variability, especially around the OFF-state.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Flexibility of Key Electronic and Optical Properties of Reduced Graphene
           Oxide Through Its Controlled Synthesis

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      Authors: Rewrewa Narzary;Palash Phukan;Satyajit Das;Partha Pratim Sahu;
      Pages: 6400 - 6407
      Abstract: Recently, graphene oxides (GOs), reduced GO (rGO), and their derivatives have been focused on as a superior flexible material due to having easy processability and high carrier mobility. Here, we report an inexpensive green synthesis of GO/rGO at a relatively low temperature of 150 °C. The scanning electron microscopy (SEM)/energy-dispersive X-ray (EDX), X-ray diffraction (XRD), Raman, Fourier transformed IR (FTIR), and UV–visible spectroscopy confirm the successful fabrication of rGO with an enhanced carbon–0carbon (sp2/sp3) component with an enhanced carbon-to-oxygen ratio (C/O) from 0.93 to 2.76. Here, a work function tuning of 5.6–4.5 eV, a bandgap modulation of 3.93–2.63 eV, a charge carrier density tuningfrom $1.12times10$ 16 to $1.14times10$ 21 cm−3, and a mobility tuning from $1.51times10$ −2 to 59.663 cm2/ $text{V}cdot text{s}$ are made through its controlled reduction of GOs, which are much better than the results obtained at high temperature >1000 °C. The flexible nature of both electronic and optical properties of rGO nanostructures assures it as an excellent material for electronics and optoelectronics devices.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Development of an Imaging and Impedance Flow Cytometer Based on a
           Constriction Microchannel and Deep Neural Pattern Recognition

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      Authors: Xiao Chen;Hongyan Liang;Yimin Li;Deyong Chen;Junbo Wang;Jian Chen;
      Pages: 6408 - 6416
      Abstract: This article presents an imaging and impedance flow cytometer based on a constriction microchannel with corresponding cell-type classification based on deep neural pattern recognition. When an incoming cell reached the entrance of the constriction microchannel, the image of the nucleus labeled with fluorescence was captured by a high-speed camera without the concern of losing focus, whereas when the cell deformed through the constriction microchannel by effectively blocking electrical lines, large impedance variations were sampled by an impedance analyzer. Six key biostructural and bioelectrical parameters (e.g., cell diameter, nuclear roundness, and cytoplasmic conductivity) from thousands of single cells were extracted, producing a successful rate of 88.3% in classifying A549 versus Jurkat versus K562 cells based on the feedforward neural network. In addition, multilayer neural networks of deep learning (e.g., VGG16 of CNN and LSTM of RNN) were also used to process fluorescent images and impedance profiles, producing an almost 100% successful rate in cell-type classification. In summary, the microfluidic flow cytometer reported in this article could characterize single-cell biostructural and bioelectrical properties in a high throughput manner, realizing high successful rates of cell-type classification.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Electrospinning-Driven InHfOx Nanofiber Channel Field-Effect Transistors
           and Humidity Stability Exploration

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      Authors: Jin Yan;Gang He;Bo He;Qingqing Hu;Qian Gao;Shanshan Jiang;Yanmei Liu;
      Pages: 6417 - 6422
      Abstract: High-performance field-effect transistors (FETs) based on electrospun Hf-doped In2O3 nanofibers as channel layers have been constructed in this article. InHfOx nanofibers were studied using scanning electron microscopy (SEM), X-ray diffraction (XRD), and electrical measurements to investigate their crystallinity, surface morphology, and electrical properties. Enhanced electrical performance has been achieved for FETs with an optimized Hf doping concentration of 3%, including high field-effect mobility ( $mu _{{mathrm {FE}}}$ ) of 1.93 cm2V−1s−1, a large ${I}_{{mathrm {on}}}/{I}_{{mathrm {off}}}$ of $1.39times 10$ 7, a low ${V}_{{mathrm {TH}}}$ of 0.59 V, and a small interfacial trap state ( ${D}_{{mathrm {it}}}$ ) of $7.29times10$ 11 cm−3. Humidity stability explorations have indicated that InHf $_{3%}text{O}$ -based FET device performance is the most stable of all devices, confirmed by low-frequency noise (LFN) measurements and positive bias stress tests (PBSTs). The main reason can be attributed to the Hf-doping-induced hydrophobicity of InHfOx nanofibers. To demonstrate the capability of the device in more complex logic circuits, a resistor-loaded inverter based on InHf $_{3%}text{O}$ /SiO2 FET exhibits excellent full swing characteristics with a voltage gain of 3. Our work has indicated the great potential prosp-cts of electrospinning-derived nanofiber-based FETs in future oxide-based electronics.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Fabrication and Modeling of Flexible High-Performance Resistive Switching
           Devices With Biomaterial Gelatin/Ultrathin HfOx Hybrid Bilayer

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      Authors: Anurag Dwivedi;Anil Lodhi;Shalu Saini;Harshit Agarwal;Shree Prakash Tiwari;
      Pages: 6423 - 6429
      Abstract: Flexible resistive random access memory (RRAM) devices with biomaterial gelatin and ultrathin HfOx hybrid bilayer dielectric exhibiting excellent resistive switching (RS) behavior are demonstrated. The fabricated devices show a very high memory window of greater than $10^{{5}}$ and data retention of $10^{{4}}$ s without any degradation in a pristine state. Moreover, to investigate the mechanical stability of the hybrid bilayer film and variation in switching performance upon bending was studied by bending the devices at a 12-mm radius followed by 7 mm. Even after this extreme bending, the device maintained the memory window of $10^{{5}}$ without any degradation in data retention, indicating excellent electromechanical stability of the device. Furthermore, a simple mathematical model of the RRAM device was used to simulate these devices with the help of our experimental data and the ${I}$ – ${V}$ equations. The developed model shows excellent accuracy with a relative root mean square (RMS) error of less than 5%, which can prove to be an excellent tool for the simulation of circuits and systems based on these RRAMs.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at
           Sub-7-nm Technology Node: A Simulation-Based Optimization Study

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      Authors: Suman Das;Avik Chattopadhyay;Suchismita Tewari;
      Pages: 6430 - 6437
      Abstract: In this article, for the first time, an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and investigated for its suitability to be a universal device. After validating the simulation scheme with the experimental results of fabricated TFET devices, the impact of thickness of the said epilayer ( ${T}_{text {epi}}$ ), on device performance, has been thoroughly investigated in terms of a variety of performance metrics, both in analog and digital (Ana–Digi) domains. To increase the vitality of the work, the device-level analysis is stretched to the circuit level. The impact on the inverter performance, both in Ana–Digi domains, in terms of fundamental circuit performance parameters, viz., dc gain, short-circuit power dissipation during switching, noise margin (NM), and so on, has been studied, and ultimately, the most optimized TFET structure, in each domain, has been identified. Finally, in this whole device/circuit co-analysis, after summing up all the performance metrics in both the domains while looking for meeting the low-power (LP) requirements (following the goals, as applicable, of international roadmaps), altogether, we have found that AU-TFET with ${T}_{text {epi}} $ = 6 nm could be considered as the ultimate optimized universal LP Ana–Digi TFET structure.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Ferroelectric Field-Effect Transistors for Binary Neural Network With 3-D
           NAND Architecture

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      Authors: Geun Ho Lee;Min Suk Song;Sangwoo Kim;Jiyong Yim;Sungmin Hwang;Junsu Yu;Daewoong Kwon;Hyungjin Kim;
      Pages: 6438 - 6445
      Abstract: Ferroelectric field-effect transistor (FeFET) can be operated as a nonvolatile memory device with low programming voltage based on polarization. In particular, it can be used as a synaptic device in a neuromorphic system based on the NAND flash array structure. We demonstrate a Hf0.5Zr0.5O2 (HZO)-based FeFET device fabricated on a silicon-on-insulator (SOI) substrate with high ON/OFF ratio and reliability characteristics. The HZO-based FeFET is utilized as a synaptic device based on the 3-D NAND architecture. It is verified with the binarization of input–output signals and weight value for efficient vector–matrix multiplication (VMM) operation using the 3-D NAND architecture. In addition, a neural network layer-mapping method increasing synaptic cell efficiency is proposed. A system-level simulation is performed based on the FeFET single-device experimental data. The VMM operation is verified through the SPICE Berkeley short-channel IGFET model (BSIM), and off-chip (ex-situ) learning with binary neural network (BNN) is performed for the Modified National Institute of Standards and Technology Database MNIST and fashion-MNIST data. The results confirm that the proposed FeFET-based BNN can perform accurate VMM operations and is robust to variations due to the binary weight state.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Efficient Implementation of Max-Pooling Algorithm Exploiting
           History-Effect in Ferroelectric-FinFETs

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      Authors: Musaib Rafiq;Shivendra Singh Parihar;Yogesh Singh Chauhan;Shubham Sahay;
      Pages: 6446 - 6452
      Abstract: Convolutional neural networks (CNNs) have become the state-of-the-art tool for image classification, object detection, and segmentation. The max-pooling layer in the CNN architecture leads to a significant enhancement in the classification accuracy by extracting the most prominent features from the feature maps produced by the convolutional layers, reducing the number of computations, and preventing overfitting. However, the conventional digital/analog implementations of the max-pooling layer are energy-hungry. Moreover, compact and energy-efficient hardware implementation of the max-pooling layer is essential for realizing CNNs which may handle complex artificial intelligence (AI)/machine learning (ML) workloads on Internet of Things (IoT) edge devices. To this end, in this work, for the first time, we have proposed a highly scalable, compact, and energy-efficient implementation of the max-pooling algorithm utilizing a single Ferroelectric (Fe)-FinFET. We have designed a novel feature-to-pulse mapping scheme and exploit the history-effect in the polarization state of Fe-FinFETs (which is otherwise undesirable for memory application). Our comprehensive analysis using an experimentally calibrated compact model for the doped-HfO2 ferroelectric capacitor integrated with 14-nm-FinFET technology indicates that the final polarization state of the Fe-FinFET corresponds to the maximum input feature irrespective of the order of application of inputs with a mean relative error of 4.95% while consuming 22.8 fJ of energy. Furthermore, extensive network simulations show that such a small deviation of the max-pooling layer output from the ideal value does not lead to a significant degradation in the classification accuracy ( $< 2$ % drop in network fidelity).
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Universal Compact Model for Spin-Transfer Torque-Driven Magnetization
           Switching in Magnetic Tunnel Junction

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      Authors: Xiaoyi Yang;Yue Zhang;Yue Zhang;Peng Wang;
      Pages: 6453 - 6458
      Abstract: Current-induced magnetization switching through spin-transfer torque (STT) has shown great potential for low-power information storage. However, predicting its mesoscopic behavior induced by both electrical current and thermal fluctuation is a fundamental challenge in spintronics. Moreover, the physical models in different switching regimes have not been properly unified. Here, we propose a novel analytical model to describe the mean magnetization switching time in general terms. By incorporating a nondimensional parameter ${k}$ in (0,1) to elucidate the relative impact of thermal activation and current, the unified model shows good agreement with the experimental data in all the regimes, including high current regime, thermal activation regime, and the intermediate regime between them. Finally, we develop an electrical model of magnetic tunnel junction (MTJ) device with Verilog-A language and perform transient simulation to demonstrate its functionality with Spectre. The Monte Carlo simulations have also been implemented to confirm their stochastic switching behavior. This model will be greatly beneficial for accurate and efficient designs for spintronic-based integrated circuits.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Dynamical Effects of Excess Carriers on SOI FeFET Memory Device Operations

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      Authors: Jung-Han Hsia;Yu-Hung Liao;Neelesh Ramachandran;Sayeef Salahuddin;
      Pages: 6459 - 6464
      Abstract: We study the carrier dynamics of memory program (PGM) and readout operations for an n-type silicon-on-insulator (SOI) ferroelectric field-effect transistor (FeFET) through TCAD simulations. We found that gate-induced drain leakages (GIDL) during the PGM operation with large negative gate biases can result in excess hole concentrations as high as 7.3 $times 10^{{20}}$ cm $^{-{3}}$ in the potential well formed in the SOI channel. The hole accumulation causes a large electric field across the ferroelectric (FE) layer and results in a polarization boost at a low PGM voltage. For a nano-scale SOI channel, the retention time of the excess holes can exceed microseconds according to our simulations. The outflow of the excess holes leads to a transient effect in the drain current during the readout operation, and we observed additional retention effects for the FeFET memory window due to the hole dynamic effects on the electrostatics and the FE polarizations. While the excess holes result in a ~100 ps delay in the readout phase before a large read margin can be detected, they have boosted the PGM speed and polarization window. The boosted polarization can be retained for milliseconds, and potentially beyond, resulting in an appreciable ON/OFF ratio during readout. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Resistive Switching and Synaptic Behavior of Perovskite Lanthanum
           Orthoferrite Thin Film for Neuromorphic Computing

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      Authors: Amit Kumar Shringi;Atanu Betal;Satyajit Sahu;Michael Saliba;Mahesh Kumar;
      Pages: 6465 - 6470
      Abstract: A resistance random access memory (RRAM), based on a metal oxide thin film with resistive switching behavior, has been explored as an emerging candidate for their application as nonvolatile memories, due to their various advantages, such as simple device configuration, long data retention, high switching speed, and low operating voltage. Various metal oxides have been explored for resistive switching applications including, e.g., binary and ternary compounds. Among all metal oxides, the perovskites have attracted considerable interest due to their potential to be used for information storage and neuromorphic application. In this work, we demonstrate stable bipolar resistive switching devices based on the sputtered LaFeO3 thin film on fluorine doped tin oxide (FTO)-coated glass with circular-shaped silver contacts. The memory performance of fabricated devices was characterized as a function of the thickness of the LFO thin layer. The resistive switching properties are investigated using macroscopic ${I}$ – ${V}$ measurements, showing low-voltage switching with a high ON–OFF ratio ( $approx 300$ ) and long retention (≥9000 s). The fabricated devices demonstrate the stable, low voltage and high-speed switching. Furthermore, in this work, we demonstrate the synaptic behavior of the LFO thin-film memory devices, as it exhibits analog memory characteristics, potentiation, and depression.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Single Crystalline Diamond p-Channel Cascode and Inverter

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      Authors: Senchuan Ding;Zeyang Ren;Yufei Xing;Jinfeng Zhang;Yuanchen Ma;Kai Su;Junpeng Li;Hanxue Wang;Jincheng Zhang;Yue Hao;
      Pages: 6471 - 6475
      Abstract: The cascode structure was fabricated by combining the H-diamond normally-ON p-FET with the Si normally-OFF p-FET. The cascode shows normally- OFF characteristics with the threshold voltage of −0.8 V and the maximum transconductance of 344.6 mS/mm. The maximum saturation drain current and minimum ON-resistance are 34.2 mA/mm and $18.74 ~Omega cdot $ mm, respectively. In addition, the cascode structure can work as an inverter. The voltage transfer characteristics (VTCs) and dynamic switching characteristics at the frequency of 200 Hz of the diamond cascode inverter were demonstrated first. These results indicate that the diamond cascode is suitable to be used to achieve diamond normally- OFF device and can also be used to work as the inverter.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Neural Network-Based and Modeling With High Accuracy and Potential Model
           Speed

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      Authors: Chien-Ting Tung;Ming-Yen Kao;Chenming Hu;
      Pages: 6476 - 6479
      Abstract: In this brief, we demonstrate a neural network (NN)-based device modeling framework. This NN model is built to model advanced field-effect transistors (FETs). Specific transfer functions and loss functions are chosen to achieve high accuracy and smoothness in the output of this NN model. Both ${I}$ – ${V}$ (current–voltage) and ${C}$ – ${V}$ (capacitance–voltage) characteristics are studied in this work. Speed comparison between the NN-based model and Berkeley short-channel IGFET model (BSIM) has been done to show that NN has a great potential to accelerate circuit simulation speed. We also present that this NN modeling framework is not only useful for more Moore technologies [e.g., gate-all-around FET (GAAFET)] but also beyond Moore transistors [e.g., negative capacitance FET (NCFET)].
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Solution-Processed p-Type CuI Thin-Film Transistors With NAND Logic
           Function

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      Authors: Xing Yuan;Wei Dou;Yifan Wang;Jing Zeng;Liushun Wang;Liuhui Lei;Dongsheng Tang;
      Pages: 6480 - 6484
      Abstract: In this article, copper iodide (CuI) is used as the channel layer in thin-film transistors (TFTs) for the first time to realize the NAND logic function. $vphantom {_{int }}$ TFTs are optimized by 80 °C annealing and have an ON/ OFF current ratio of $2.7times10$ 2 and a field-effect mobility of 0.18 cm2 $cdot text{V}$ −1 $cdot text{s}$ −1, demonstrating good stability and reproducibility. Furthermore, by using chitosan with electric-double-layer (EDL) effect as the gate dielectric instead of standard silica, the operating voltage can be decreased to 2.0 V. The p-type CuI TFTs have the potential to be used in complementary electronic circuits with low energy consumption as well as portable sensors.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • An Ultralow Turn-On GaN Lateral Field-Effect Rectifier With Schottky-MIS
           Cascode Anode

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      Authors: Fangzhou Wang;Zeheng Wang;Wanjun Chen;Ruize Sun;Wenjun Xu;Yang Wang;Haiqiang Jia;Bo Zhang;
      Pages: 6485 - 6491
      Abstract: In this article, we experimentally propose an ultralow turn-on GaN lateral field-effect rectifier (LFER) incorporating a Schottky-MIS cascode anode (CA-LFER). In the CA-LFER, the lateral Ti/GaN Schottky contact as well as the Ti/HfO2/AlGaN MIS-controlled channel is cascoded at the anode. Ti, which has a very low work function, contributes to lowering the Schottky barrier height (SBH) at the lateral Ti/GaN Schottky contact. At the same time, both Ti and the high dielectric constant HfO2 material can significantly lower the threshold voltage ( ${V}_{text {TH}}$ ) of the Ti/HfO2/AlGaN MIS-controlled channel. The two features result in an ultralow turn-on voltage ( ${V}_{text {ON}}$ ). Furthermore, when applying a reverse bias, the potential difference between the Ti anode metal and the two-dimensional electron gas (2DEG) in the GaN channel immediately depletes the Ti/HfO2/AlGaN MIS-controlled channel. As a result, the low SBH lateral Ti/GaN Schottky contact can be protected from the high reverse leakage current ( ${I}_{text {LEAK}}$ ), leading to a high breakdown voltage (BV). The fabricated CA-LFER shows a competitive ${V}_{text {ON}}$ – ${I}_{text {LEAK}}$ relationship including an ultralow ${V}_{text {ON}}$ of 0.19 V and a relatively low ${I}_{text {LEAK}}$ of $3.6times 10^{-{6}}$ A/mm, together with a BV of 710 V. This high performance suggests that the CA-LFER can be a pro-ising candidate for the GaN power rectifier applications requiring ultralow ${V}_{text {ON}}$ and a better ${V}_{text {ON}}$ – ${I}_{text {LEAK}}$ tradeoff.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Erratum to “Characterization and Modeling of Reduced-Graphene Oxide
           Ambipolar Thin-Film Transistors”

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      Authors: Nicolò Lago;Marco Buonomo;Rafael Cintra Hensel;Francesco Sedona;Mauro Sambi;Stefano Casalini;Andrea Cester;
      Pages: 6492 - 6492
      Abstract: In the above article [1], an error is present in (1). The correct equation should read as in (1), shown at the bottom of the page.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Call for Papers: Materials, processing and integration for neuromorphic
           devices and in-memory computing

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      Pages: 6493 - 6494
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Call for Papers: Wide and Ultrawide Band Gap Semiconductor Devices for RF
           and Power Applications

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      Pages: 6495 - 6496
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Call for Papers: Semiconductor Device Modeling for Circuit and System
           Design

    • Free pre-print version: Loading...

      Pages: 6497 - 6498
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • TechRxiv: Share Your Preprint Research with the World!

    • Free pre-print version: Loading...

      Pages: 6499 - 6499
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • IEEE Open Access Publishing

    • Free pre-print version: Loading...

      Pages: 6500 - 6500
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
 
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