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Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Abstract: This page or pages intentionally left blank. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Munhyeon Kim;Kitae Lee;Sihyun Kim;Jong-Ho Lee;Byung-Gook Park;Daewoong Kwon;
Pages: 2232 - 2235 Abstract: In this article, for the first time, we proposed the side-shielded forksheet (S-FS) device to sustain extreme device scaling and to expand device design margins. Through the process simulations calibrated based on transmission electron microscopy (TEM) dimensions of the process integration modules, it is verified that n/p-type nanosheet (NS)-shaped stacked channel devices are physically isolated in the S-FS by the dielectric wall formed by the proposed dual liner process scheme (DLS). In addition, distributed correlation is rigorously analyzed by 3-D technology computer aided design (TCAD) device simulations with precisely calibrated models. As a result, it is revealed that the S-FS shows the superior electrical characteristics and design margin compared to the conventional forksheet (C-FS) device when structural variation and work function (WF) fluctuation are considered in extremely scaled devices. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yu Fu;Yuhao Chang;Shozo Kono;Atsushi Hiraiwa;Kyotaro Kanehisa;Xiaohua Zhu;Ruimin Xu;Yuehang Xu;Hiroshi Kawarada;
Pages: 2236 - 2242 Abstract: In this article, the normally- OFF oxidized Si-terminated (C–Si) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) with as-deposited 0.5-nm silicon on diamond annealed at high temperature as the subsurface p-channel were presented for the first time. A novel method utilizing both a metal mask to realize the regrown heavily boron-doped (001) diamond layer first (p+-diamond-first) and a molecular beam deposition (MBD) method to procure atomic-scale silicon deposition was achieved. Scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDS) element mapping results suggest that the C–Si diamond/Al2O3 interface is quite continuous and atomically flat. A remarkably high threshold voltage ( ${V}_{text{TH}}$ ) of −10 V and a maximum drain current density ( ${I}_{D_{}{text{MAX}}}$ ) of −156 mA/mm are simultaneously achieved in the fabricated devices. The devices with different source and drain (S/D) distances ( $L_{text{SD}}$ ) deliver robust ${V}_{text{TH}}$ results and feature low OFF-state S/D leakage current $vert {I}_{text{leakage}}vert $ of ~ $6times10$ −6 mA/mm at ${V}_{text{GS}}$ = 0 V. The extracted field-effect mobility is as high as 127 cm2 $cdot text{V}$ −1 $cdot text{s}$ −1 and the interface state density is as low as $4.35times10$ 12 eV−1 $cdot $ cm−2. These competitive results reveal that this first attempt of employing the combination of p+-diamond-first and MBD approaches promotes the integration of the advanced silicon manufacturing process with wide bandgap diamond material for power applications. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Joachim Knoch;Bin Sun;
Pages: 2243 - 2247 Abstract: This article studies the sub-linearity of the output characteristics measured in Schottky-barrier metal-oxide-semiconductor field-effect transistors with simulations and experiments. It is shown that the sub-linearity is not due to the forward-biased Schottky diode at the drain contact interface but due to the drain bias impact on the source-side Schottky-barrier, resulting in an increased carrier injection with increasing drain–source voltage. The simulation results are confirmed with the measurements of fabricated dual-gate Schottky-barrier transistors. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Mourina Ghosh;Ankur Singh;Shekhar S. Borah;John Vista;Ashish Ranjan;Santosh Kumar;
Pages: 2248 - 2255 Abstract: This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is $2.6~mu text{W}$ . In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Biyao Zhao;Jinshun Bi;Yue Ma;Jian Zhang;Yan Wang;Linjie Fan;Tingting Han;Viktor Stempitsky;
Pages: 2256 - 2261 Abstract: In this work, the localized backside etching (LBE) structure is introduced as a strategy for total ionizing dose (TID) irradiation hardening. Immunity to TID-irradiation-induced radio frequency (RF) property degradation is observed for the first time in SOI substrates with the LBE structure. Identical co-planar waveguide transmission lines (CPW TLines), crosstalk characterization structures, and planar spiral inductors are designed and fabricated on different 8-in SOI wafers to characterize the RF properties of substrates. Electrical characterization in the frequency ranges from 100 MHz to 40 GHz reveals that the LBE structure is beneficial to suppressing the parasitic surface conduction (PSC) effect, which will lead to better RF properties of SOI substrate. It is shown that under 60Co $gamma $ -ray irradiation, RF losses are significantly increased in the case of conventional substrates. In contrast, LBE substrates are almost insensitive to TID irradiation due to suppression of PSC. A developed physical model is proposed to characterize the behavior of inductors under PSC and TID effects, and the improvement by LBE structure on RF TID tolerance is separated through model parameter extraction. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Qianshu Wu;Jia Chen;Liang He;Jinwei Zhang;Qiuling Qiu;Chenliang Feng;Liuan Li;Taotao Que;Zhenxing Liu;Zhisheng Wu;Zhiyuan He;Yang Liu;
Pages: 2262 - 2269 Abstract: The Schotty-type p-GaN gate high-electron-mobility transistors (HEMT) feature a unique gate structure. A comprehensive understanding of the charge control mechanism in the p-GaN gate region is a fundamental step for the optimization of this technology. In this work, a physics-based analytical model is presented which takes into consideration all the capacitive effects from gate metal deep into the GaN buffer. According to our analysis, the p-GaN layer can be either partially depleted by the metal/p-GaN Schottky junction or fully depleted, depending on the doping concentration and thickness of the p-GaN layer. Our model accurately captures the charge control properties under both conditions and is validated against TCAD numerical simulations. For a certain p-GaN thickness, a lightly doped p-GaN leads to a full-depletion condition, such that the acceptor concentration directly affects the band diagram at AlGaN/GaN interface. The ${V}_{text {th}}$ of the HEMT increases quickly with acceptor concentration in p-GaN. With sufficiently high acceptor concentration in p-GaN, the device reaches the partial-depletion condition, the acceptor concentration loses its influence over the band diagram at the location of the AlGaN/GaN interface, since the Fermi-level at the AlGaN surface is pinned near the valence band of p-GaN. The ${V}_{text {th}}$ starts to decrease with acceptor concentration, but at a relatively slow rate. The maximum ${V}_{text {th}}$ is obtained near the boundary between partial-and full-depletion conditions. In consideration of the process margin, the device designed with a partially depleted p-GaN is preferable, since it ameliorated the ${V}_{text {th}}$ sensibility -gainst acceptor concentration. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Weiguang Wang;Qian Li;Ning An;Jianping Zeng;
Pages: 2270 - 2274 Abstract: A novel metal-2DEG-metal (M-2DEG-M) varactor based on GaN high electron mobility transistor (HEMT) structures was designed and investigated. The novel varactor employed metal-2DEG direct contacts to form two back-to-back Schottky junctions, eliminating the threshold voltage and showing a strong nonlinear CV behavior at zero bias, which was more beneficial to terahertz (THz) multiplier circuits design compared with the conventional metal–semiconductor–metal (MSM) 2DEG varactors. The metal-2DEG direct contacts reduced the junction capacitance and the series resistance simultaneously. For the M-2DEG-M varactor with an electrode length of $1 mu text{m}$ , the device capacitance at zero bias was determined to be 3.0 fF (without de-embedding the parasitic component), with the series resistance of $25.4 Omega $ , resulting in a record high cutoff frequency of 2.09 THz for GaN-based varactors. After de-embedding the parasitic pad-to-pad capacitance, the cutoff frequency and figure of merit (FOM) would be 3.13 and 7.14 THz, respectively. Additionally, the whole fabrication process of the novel varactor only needed two steps of ordinary UV lithography without elaborate nanoscale T-gates, totally compatible with GaN-based HEMT process. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ahtisham Ul Haq Pampori;Sheikh Aamir Ahsan;Yogesh Singh Chauhan;
Pages: 2275 - 2281 Abstract: In this article, we introduce an engineering approach to model the current and charge characteristics of an AlGaN/GaN Fin–HEMT. The model handles the effective width of the 2DEG channel by considering its depletion due to the presence of gates on the sidewalls of the fin. This width modulation of the 2DEG, and the bias-dependence associated with it, significantly affects the transconductance and the capacitance behavior of the device. In this work, we modify and couple two industry-standard compact models: 1) the advanced SPICE model for GaN HEMTs (ASM-GaN-HEMT) model and 2) the Berkeley short-channel insulated-gate FET model for common multiple gate (BSIM-CMG) model. While the former provides the physics-based calculations for electrostatics and transport in the 2DEG, the latter is incorporated to account for the width-modulation due to the sidewalls. The developed methodology is validated for dc, ${C}$ – ${V}$ , and RF behavior against experimental data of GaN Fin–HEMTs. To the authors’ knowledge, this is the first compact model that provides an end-to-end dc–radio frequencies (RF) modeling solution for the state-of-the-art GaN Fin–HEMTs and therefore could play a role in the evolution of the GaN Fin–HEMT technology. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Guangnan Zhou;Fanming Zeng;Rongyu Gao;Qing Wang;Kai Cheng;Lingqi Li;Peng Xiang;Fangzhou Du;Guangrui Xia;Hongyu Yu;
Pages: 2282 - 2286 Abstract: We present a novel p-gallium nitride (GaN) gate HEMT structure with reduced hole concentration near the Schottky interface by doping engineering in metal-organic chemical vapor deposition (MOCVD), which aims at lowering the electric field across the gate. By employing the additional unintentionally doped GaN (u-GaN) layer, the gate leakage current is suppressed and the gate breakdown voltage is boosted from 10.6 to 14.6 V with negligible influence on the threshold voltage and ON-resistance. A reduced Mg concentration in the u-GaN layer was confirmed by secondary-ion mass spectrometry. Time-dependent gate breakdown measurements reveal that the maximum gate drive voltage increases from 6.2 to 10.6 V for a ten-year lifetime with a 1% gate failure rate, which effectively expands the operating voltage margin of the p-GaN gate HEMTs without any other additional process step. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Huan Wang;Yan Lin;Junsong Jiang;Dan Dong;Fengwei Ji;Meng Zhang;Ming Jiang;Wei Gan;Hui Li;Maojun Wang;Jin Wei;Baikui Li;Xi Tang;Cungang Hu;Wenping Cao;
Pages: 2287 - 2292 Abstract: In this article, the thermally induced threshold voltage ( ${V}_{text{TH}}$ ) shift was investigated on two types of normally- OFF p-GaN gate high-electron-mobility transistors (HEMTs), featuring either an Ohmic-type or a Schottky-type gate. A positive ${V}_{text{TH}}$ shift in a Schottky-type device and a negative ${V}_{text{TH}}$ shift in an Ohmic-type device were observed at elevated temperatures. Temperature-dependent gate current–voltage ( ${I}-{V}$ ) and the transfer-length-method (TLM) analysis revealed that the bias condition across the p-GaN/AlGaN/GaN heterostructures was changed in both Schottky- and Ohmic-type devices as temperature increased. We propose that: 1) temperature-enhanced hole injection through thermionic emission which lowers the knee voltage of the Ohmic-metal/ p-GaN contact in Ohmic-type devices and 2) thermally enhanced gate current which enlarges the bias voltage across the Schottky-metal/p-GaN junction in Schottky-type devices, resulted in the observed ${V}_{text{TH}}$ instability characteristics. The photoluminescence measurements were conducted to verify the thermally-enhanced ionization of magnesium dopants in the p-GaN and the corresponding instability issues. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ming Yang;Zhiliang Gao;Xinguang Su;Yuanyuan Wang;Yanhui Han;Xu Tang;Ben Li;Jihao He;Jun Liu;Ruojue Wang;Xiao Liu;Fei Mei;Lei Wang;Li Zhou;Wei Song;Yingqian Liu;Fayu Wan;Zhengang Cui;Bin Liu;
Pages: 2293 - 2298 Abstract: A method is proposed to determine drain access resistance in saturation region of AlGaN/GaN heterostructure field-effect transistors (HFETs). The variation of drain access resistance is analyzed qualitatively and quantificationally. Comparing with source access resistance, the difference is attributed to the asymmetry of additional polarization charge distribution at AlGaN/GaN interface. Interaction strength between additional polarization charge and gate–drain channel electron is stronger than that of gate–source channel electron. The drain access resistance components corresponding to polarization Coulomb field (PCF) scattering, polar-optical-phonon (POP) scattering, piezoelectric (PE) scattering, and interface roughness (IFR) scattering are obtained quantificationally. POP scattering dominates drain access resistance with the increase of drain–source current, because of hot-electron and hot-POP effect. Moreover, PCF scattering also plays an important role, especially under low drain–source current, because of stronger PCF scattering potential and lower hot-POP temperature. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ajay Kumar Visvkarma;Khushwant Sehra;Chanchal;Robert Laishram;Amit Malik;Sunil Sharma;Sudhir Kumar;D. S. Rawal;Seema Vinayak;Manoj Saxena;
Pages: 2299 - 2306 Abstract: In this article, the impact of gamma ( $gamma $ ) irradiation on passivated and unpassivated AlGaN/GaN HEMT is presented in detail. Passivated and unpassivated GaN-HEMT devices have been exposed to $gamma $ -radiations to a total dose of 10 kGy. Post- $gamma $ -irradiation, a refinement in ohmic contact, which makes device source/drain, is recorded. Alteration in Schottky gate electrical characteristics ( ${C} - {V}$ and ${I}!!-!!{V}$ ) along with advances in device drain current and transconductance has been observed in unpassivated HEMT, while it remained almost unaltered in passivated GaN-HEMT after $gamma $ -irradiation. The OFF-state gate leakage has deterioration in both types of HEMTs, suggesting a modification in trap concentration beneath the gate and near gate region during $gamma $ -exposure. This is confirmed via pulsed ${I}!-!{V}$ measurements. A strong upswing in drain current recovery after stress bias is recorded post- $gamma $ -irradiation in both types of HEMTs. This confirms that the trapping sites have been altered during $gamma $ -exposure. Possible reasons causing this modification are improvement in gate metal barrier inhomogeneities and reduction/rearrangement of crystal defects during $gamma $ -exposure. The effect of $gamma $ -radiation on intrinsic/extrinsic device parameters has also been determined using S-parameters measurements. Intrinsic/extrinsic device parameters of passivated HEMT are observed to be less affected by $gamma $ -irradiation in comparison to unpassivated GaN-HEMT devices, and post-radiation, both the devices have similar device parameters values as it was prior radiation making it suitable for harsh environment applications. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Benito González;Antonio Lázaro;Raúl Rodríguez;
Pages: 2307 - 2312 Abstract: In this article, an ac conductance method has been successfully employed to extract the thermal resistance of GaN-based high-electron-mobility transistors (HEMTs) on silicon. The resulting thermal resistances, when varying the channel length and gate width, are comparable to those obtained with pulsed measurements, by making use of positive drain-to-source pulsed voltages from a zero power dissipation quiescent bias point and 3-D thermal simulations. Furthermore, the gate geometry dependence of the thermal resistance of GaN-based HEMTs has been successfully modeled for circuit-design purposes. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Jie Li;Min Tang;Junfa Mao;
Pages: 2313 - 2318 Abstract: An analytical thermal model for AlGaN/GaN high-electron-mobility transistors (HEMTs) is proposed in this article. By means of the conformal mapping technique, the device structure is transformed into a simplified geometry, and the solution to the heat conduction equation is easily obtained. The model is capable of accurately predicting the maximum temperature rise of the device channel. Moreover, based on the superposition principle, this model provides an accurate estimation of thermal coupling between the gate fingers of multifinger devices, as well as the temperature rise of each gate finger. In addition, the temperature-dependent and orthotropic properties of thermal conductivity can also be taken into consideration. The proposed model provides an efficient prediction of hot spots in AlGaN/GaN devices. The accuracy of this model is verified by the simulation results and experimental data. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Hasan Kocer;Yilmaz Durna;Burak Gunes;Gizem Tendurus;Bayram Butun;Ekmel Ozbay;
Pages: 2319 - 2324 Abstract: Gallium nitride (GaN) high-electron-mobility transistor (HEMT) devices, which have wide application potential from power amplifiers to satellite, need to be thoroughly examined in terms of reliability in order to benefit the superior intrinsic properties of the device. The most critical parameter in the device reliability is the hotspot, or ${T}_{text {max}}$ , which occurs somewhere on the subsurface and along the channel of the GaN HEMT, which is optically inaccessible due to optical path disability. Therefore, the ${T}_{text {max}}$ value is underestimated in optical measurements, such as the thermographic IR and Raman methods. With 3-D electrothermal simulations, ${T}_{text {max}}$ is obtained close to reality, but it requires a huge computation load and the complex modeling of semiconductor device physics. In 2-D or 3-D thermal simulations that do not use electrothermal simulations, since the self-heating is mostly modeled with a single heat source, neither the correct ${T}_{text {max}}$ value is obtained nor the effect of bias conditions is considered. To address the aforementioned shortcomings, a hybrid method is demonstrated, which exploits the electrical measurements of GaN HEMT, which RF and reliability engineers often and easily do. It is demonstrated that ${T}_{text {max}}$ can be determined quickly and close to the electrothermal simulations in a GaN HEMT device with a two-heat source method and finite element analysis (FEA) hybrid interaction with respect to various bias conditions. Moreover, the impact of the knee voltage is investigated with different knee-detection techniques. The propo-ed method provides GaN HEMT reliability engineers with an easy-to-implement alternative to reveal the hotspot location and the value. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Xuemin Tian;Tingting Zhao;Jun Li;Tongkuai Li;Li Yuan;Xianyang Xue;Zhigan Wang;Jianhua Zhang;
Pages: 2325 - 2330 Abstract: The artificial neural networks based on biomimetic synaptic devices attempts to process and memorize information by simulating a human brain. Electrolyte-gated transistors (EGTs) are promising candidates for artificial synaptic devices, due to their large specific capacitance, low operating voltage, and sensitive interfacial properties. Although large-scale EGTs array based on inorganic electrolytes and small-scale EGTs arrays based on organic electrolytes are reported, large-scale EGTs arrays based on organic electrolytes have not yet been focused. In this work, a large-scale EGTs array ( $10times10$ ) based on coplanar-gate structure using lignin as electrolyte is fabricated. The organic dielectric layer fabricated in the last step can be protected from the damage caused by wet etching, thus providing an opportunity for the application of other organic electrolytes in the large-scale EGTs array. Lignin exhibits good electric performance and is environment-friendly due to its renewable property. The synaptic properties of single transistor in the EGTs array, such as excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and high-pass filtering are realized. The real-time learning and forgetting procedures stimulated by different spike numbers of EGTs array are also demonstrated. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yu-Ching Liao;Chia-Sheng Hsu;Dmitri Nikonov;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi;
Pages: 2331 - 2337 Abstract: Voltage-controlled spintronic devices are considered promising candidates for low-power applications due to the nonvolatility and the elimination of the Joule heating energy. Recently, experiments have demonstrated the voltage-controlled magnetization switching in the bismuth ferrite (BFO)/CoFe heterojunction that can achieve 180° switching at room temperature. In addition, it has been demonstrated that the ferroelectric coercive voltage of the La-doped BFO can be as low as 0.2 V by tuning the doping concentration of La and choosing a thinner BFO layer. To evaluate the potential performance of the magnetoelectric magnetic random access memory (ME-MRAM) using the BFO/CoFe heterojunction, we first build a physics-based compact model of the antiferromagnet/ferromagnet (AFM/FM) bilayer. The results from our circuit-compatible model match well with the micromagnetic simulations on the dynamics of the order parameters in both the AFM and FM layers. Next, we simulate the read and write performances of ME-MRAM using the compact model we have developed. Our results show that the write energy of the ME-MRAM can be as low as a few fJ per bit and the layout area is ~20 F2, which is more energy and area efficient compared to SRAM and other spintronic memory candidates. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Nosheen Shahzadi;Myungsang Park;Donghyuk Yun;Sanghyeon Baeg;
Pages: 2338 - 2345 Abstract: This article reveals the leakage mechanisms corresponding to the dominant leakage path of individual tail cells in $2times $ nm technology double data rate (DDR)4 DRAM at operating temperature. For leakage path determination, activation energy ( ${E}_{a}$ ) was used as a tool through its extraction by retention time measurement. To get a wide distribution of ${E}_{a}$ , retention testing was performed at the target retention time (10, 15, 20, or 25 s); during this, the number of retentions failed cells were recorded with each temperature. In this experiment, 1.65 e−2% of the selected bank cells found retention failures. From the total retention failed cells, the selected commonly retention failed cells at the target retention times comprise 1.5 e−3% of the selected bank cells. From commonly retention failed cells, the distribution of ${E}_{a}$ is analyzed with the retention time at room temperature. This analysis reveals that subthreshold, junction, and gate-induced drain leakage (GIDL) leakage paths dominate in 3.48%, 93.89%, and 2.61% of the total retention failed cells, respectively, at room temperature. Using another experimental approach, retention testing performed at operating temperature on selected 0.07-ppm retention tail cells concludes that GIDL is the dominant leakage path in this device. Correlation between ${E}_{a}$ and retention time measured at operating temperature (40 °C, 60 °C, or 80 �-0;C) explored the leakage mechanisms corresponding to ${E}_{a}$ of the extracted dominant leakage path (GIDL). These failure leakage mechanisms, dominating on certain values of operating temperature, are divulged as the root cause of failure at that temperature. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Sheng Li Fang;Chuan Yu Han;Zheng Rong Han;Bo Ma;Yi Lin Cui;Weihua Liu;Shi Quan Fan;Xin Li;Xiao Li Wang;Guo He Zhang;Xiao Dong Huang;Li Geng;
Pages: 2346 - 2352 Abstract: Neuromorphic computing based on spiking neural networks (SNNs) has attracted significant research interest due to its low energy consumption and high similarity to biological neural systems. The artificial spiking afferent neuron (ASAN) system is the essential component of neuromorphic computing system to interact with the environment. This work presents an ASAN system with simple structure by employing a new architecture of one VO2 Mott memristor and one resistive sensor (1M1S). The Mott memristors show the bidirectional Mott transition, good endurance (> $1.3times10$ 9), and high uniformity. By incorporating a flexible pressure sensor into the 1M1S architecture, a tactile ASAN system is realized with the pressure stimuli converted into rate-coded spikes. Using a $3times3$ array of the tactile ASAN systems, different pressure stimulus patterns can be well recognized. The strong adaptability of the proposed system will enable it to convert lots of environmental stimuli through the widely used resistive sensors into rate-coded spikes as the inputs of neuromorphic computing based on SNNs. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Wesley H. Brigner;Naimul Hassan;Xuan Hu;Christopher H. Bennett;Felipe Garcia-Sanchez;Can Cui;Alvaro Velasquez;Matthew J. Marinella;Jean Anne C. Incorvia;Joseph S. Friedman;
Pages: 2353 - 2359 Abstract: CMOS devices display volatile characteristics and are not well suited for analog applications such as neuromorphic computing. Spintronic devices, on the other hand, exhibit both non-volatile and analog features, which are well suited to neuromorphic computing. Consequently, these novel devices are at the forefront of beyond-CMOS artificial intelligence applications. However, a large quantity of these artificial neuromorphic devices still require the use of CMOS to implement various neuromorphic functionalities, which decreases the efficiency of the system. To resolve this, we have previously proposed a number of artificial neurons and synapses that do not require CMOS for operation. Although these devices are a significant improvement over previous renditions, their ability to enable neural network learning and recognition is limited by their intrinsic activation functions. This work proposes modifications to these spintronic neurons that enable configuration of the activation functions through control of the shape of a magnetic domain wall track. Linear and sigmoidal activation functions are demonstrated in this work, which can be extended through a similar approach to enable a wide variety of activation functions. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
P. Bousoulas;C. Tsioustas;J. Hadfield;V. Aslanidis;S. Limberopoulos;D. Tsoukalas;
Pages: 2360 - 2367 Abstract: The development of low-power neurons with an intrinsic degree of stochasticity is considered quite important for the emulation of the respective probabilistic procedures that take place within the biological neural networks. While the majority of the reported artificial neuronal configurations relies on the demonstration of well-defined spiking patterns or the realization of complicated neuromorphic properties, there is an urgent need to devise biological-like neurons with arbitrary firing capabilities. Along these lines, we present a novel threshold switching memristor from SiO2-based bilayer conductive-bridge resistive switching memory (CBRAM) and Pt nanoparticles (NPs) used as a bottom electrode (BE) in order to implement robust stochastic neuron activity accompanied with steep transition slope [~0.75 mV/dec(A)], large OFF-state (~ $10^{11} Omega $ ), low switching voltage (~200 mV), and ultrafast turn-on speed (~50 ns). Moreover, probabilistic leaky-integrate-and-fire (LIF) neuron properties were attained by employing a simple RC circuit as well as tunable integrate-and-fire (IF) properties from stand-alone threshold switching elements, which are of great significance for the development of artificial spiking neuromorphic networks. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
P. Bousoulas;C. Tsioustas;J. Hadfield;V. Aslanidis;S. Limberopoulos;D. Tsoukalas;
Pages: 2368 - 2376 Abstract: A deep understanding of the underlying resistive switching mechanism for the implementation of volatile memristive properties is regarded as of great importance for enhancing their performance. Along these lines, a 2-D dynamical model is introduced to interpret the whole memristive pattern within the bilayer configuration, as well as the crucial of the dense layer of the Pt nanoparticles (NPs) on the local thermal distribution. Moreover, the probabilistic leaky-integrate-and-fire (LIF) neuron properties were simulated by considering a simple $textit {RC}$ circuit in order to perform Bayesian extrapolation within a spiking neural network. A classification application is consequently demonstrated by using the liver tumor dataset. The advantageous capabilities of the stochastic-based spike neural networks (SNNs) are highlighted in striking contrast with the conventional artificial neural networks (ANNs), as well as the deterministic-based SNNs, in terms of prediction accuracy and power consumption. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Senne Fransen;Kherim Willems;Harold Philipsen;Devin Verreck;Willem Van Roy;Olivier Y. F. Henry;Antonio Arreghini;Geert Van den bosch;Arnaud Furnémont;Maarten Rosmeulen;
Pages: 2377 - 2383 Abstract: We propose a storage memory device that enables bit densities of >1 Tbit/mm2 based on the electro- deposition and electrodissolution of multilayered metal stacks in deep nanometer-sized wells. This device addresses the challenge of bit density scaling slowdown expected for 3-D NAND flash beyond 2030. We describe in detail the operating principles and discuss the response time, bandwidth, retention, and cycling endurance requirements for the device to be viable. As a proof-of-principle, we provide a first demonstration of the write/read (W/R) mechanism on millimeter- and micrometer-sized electrodes and show the device’s potential for reaching very high bit densities. To evaluate how the response time scales for the envisioned nanometer-sized electrodes, we derive simple analytical expressions based on finite element simulations that relate the well depth, radius, and electrolyte composition to the deposition/dissolution rate. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Puyang Cai;Hao Li;Zhiwei Liu;Tianxiang Zhu;Min Zeng;Zhigang Ji;Yanqing Wu;Andrea Padovani;Luca Larcher;Milan Pešić;Runsheng Wang;Ru Huang;
Pages: 2384 - 2390 Abstract: To fully understand the mechanisms for shifting of coercive field ( ${E}_{text {c}}$ ) during the bipolar stress cycling in doped HfO2 ferroelectric (FE) material, we present a systematic study with both characterization and simulation on HfZrOx (HZO) capacitor. First, with the help of time-dependent dielectric breakdown (TDDB) results, defect redistribution is found to be localized during the bipolar stress cycling. Then, with the advanced simulation framework Ginestra®, influences of work function (WF) mismatch of the electrodes and defect distribution on the ${E}_{text {c}}$ symmetry and breakdown property are discussed. It indicates that the shift of ${E}_{text {c}}$ is mostly due to the redistribution of defects from FE phase to non-FE phase and grain boundaries. Furthermore, nucleation limited switching (NLS) model is adopted to investigate the switching dynamics during coercive field shift in more detail. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Pei Chen;Xumeng Zhang;Zuheng Wu;Yongzhou Wang;Jiaxue Zhu;Yunxia Hao;Guan Feng;Yize Sun;Tuo Shi;Ming Wang;Qi Liu;
Pages: 2391 - 2397 Abstract: Threshold switching (TS) devices based on NbOx materials show intriguing potential for constructing artificial neurons in a neuromorphic machine. However, the high electroforming voltage, the low TS yield, and the poor device uniformity hinder the practical application of NbOx-based TS devices. In this work, we systematically investigate the effect of film composition on device performance by adjusting the oxygen contents in the NbOx films. The electroforming voltage decreases with lowering the oxygen content, and the forming yield for activating TS behavior increases without an additional reset process. Moreover, we propose a stacked method by inserting a NbOy layer with high oxygen content between the low oxygen NbOx layer and the bottom electrode. The intercalated NbOy layer serves as a virtual bottom electrode after breakdown, enhancing the local electrical field and improving cycle-to-cycle stability and device-to-device uniformity. These results demonstrate that the device performances are greatly improved by optimizing the oxygen content and structure, guiding for practical applications of NbOx-based TS devices in neuromorphic computing. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Wei Zhong;Jianfeng Zhang;Yuan Liu;Lijun Tan;Linfeng Lan;Sunbin Deng;Fion Sze Yan Yeung;Hoi Sing Kwok;Rongsheng Chen;
Pages: 2398 - 2403 Abstract: Self-assembled monolayer (SAM) treatment of gate dielectrics is a standard process for manufacturing organic thin-film transistors (TFTs) to reduce interface trap density and surface energy. However, it is rarely used for oxide semiconductor-based TFTs because the SAMs may be damaged during the manufacturing process. To explore the feasibility of using a SAM-treated gate dielectric to improve the performance of oxide TFTs, we study the effects of different SAM treatments of the gate dielectric layer on the performance of InSnZnO (ITZO) TFTs, which can help guide the selection of SAMs. After treatment with methyltriethoxysilane (C1-SAM), the performance of the TFTs is significantly improved, showing a drastic improvement in the ON/ OFF ratio and carrier mobility, and a reduction of the interface trap density and ${V}_{text {th}}$ shift of the device under positive/negative bias stress (PBS/NBS). However, after treatment with n-octyltriethoxysilane (C8-SAM) and octadecyltriethoxysilane (C18-SAM), the performance of the TFTs deteriorate or even fail. Nevertheless, this work demonstrates an effective strategy for the construction of high-performance metal oxide TFTs, though it may require careful selection of the SAMs. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Xue Chen;Jiaxian Wan;Juan Gao;Hao Wu;Chang Liu;
Pages: 2404 - 2408 Abstract: In this study, we illustrate a novel way to improve the stability under negative bias illumination stress (NBIS) of ZnO thin-film transistors (TFTs) by adding O3 treatment after each cycle of growth at 100°C by atomic layer deposition. Compared with the TFTs without O3 treatment, the shift of threshold voltage ( $Delta {V}_{th}$ ) is reduced from −4.39 to −0.98 V under NBIS, while the mobility decreased from 31.2 to 18.4 cm2 V−1s−1. (H2O and O3 as oxidants)/ZnO (H2O as oxidant) bilayer structure, a high filed-effectmobility of 32.1 cm2V−1s−1 and an excellent stability ( $Delta V_{mathrm {th}} = -2.34$ V) have been obtained simultaneously. These improved performance and stabilities are attributed to the bilayer channel structures and the reduction of $V_o$ in the ZnO channel layer treated by O3. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Min Jae Kim;Hyeong Jin Park;Sungwon Yoo;Min Hee Cho;Jae Kyeong Jeong;
Pages: 2409 - 2416 Abstract: Amorphous indium–gallium–zinc oxide (a-IGZO) is a promising channel material for an upper transistor in monolithic three-dimensional devices. Although the field-effect transistors (FETs) with a rather thick channel thickness >10 nm have been intensively examined, less information is available for the IGZO FETs with an ultra-thin body (< 10 nm). In this study, the FETs with the IGZO channel layer ranging from 2 to 20 nm were investigated in detail. As the channel thickness decreased from 20 to 7 nm, the mobility and subthreshold swing (SS) values were improved. In contrast, the deterioration in mobility and SS occurred when the IGZO thickness was less than 7 nm. The physical rationale for the strong IGZO thickness dependence on performance of the resultant FETs was discussed based on subgap density-of-state distribution and mobility models such as percolation and surface-roughness scattering mechanisms using a technological computer-aided design simulation with a quantum mechanical model. IGZO FET with an IGZO thickness of 7 nm exhibited the best performance, which was attributed to the synergic balance by percolation efficiency and reduction in effective subgap defect density of IGZO. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Gangping Yan;Hong Yang;Weibing Liu;Na Zhou;Yanpeng Hu;Yunfei Shi;Jianfeng Gao;Guoliang Tian;Yadong Zhang;Linjie Fan;Guilei Wang;Gaobo Xu;Jinshun Bi;Huaxiang Yin;Chao Zhao;Jun Luo;
Pages: 2417 - 2422 Abstract: In this article, mechanisms of extremely low OFF-state current and abnormal negative bias stress (NBS) are systematically investigated by the varying process that contains various gas ratios and gas flows during In–Ga–Zn–O (IGZO) sputtering, and different annealing conditions. One model is proposed to indicate the level of ultralow leakage in IGZO thin-film transistor (TFT) dominated by the trap-limited conduction (TLC) along with different internal chemical states of the film, which is highly consistent with the results acquired by X-ray photoelectron spectroscopy (XPS) data. Some special leakage behaviors of devices with low oxygen-deficient defects or with high oxygen-related states are well matched the present model. Moreover, all devices show an abnormal positive threshold voltage shift ( $Delta {V}_{text {TH}}$ ) under NBS, which are also discussed using the similar mechanism. Following the proposed optimization strategy based on mechanism analysis, the IGZO TFT exhibits $> 100times $ reduction in leakage, $0.55times $ decrease in subthreshold (SS), and $1.24times $ increase in mobility compared with the pristine device, achieving an ultralow leakage of PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yu-Zhe Zheng;Po-Hsun Chen;Ting-Chang Chang;Tsung-Ming Tsai;Kuan-Ju Zhou;Yu-Fa Tu;Yu-Xuan Wang;Chia-Chuan Wu;Yu-An Chen;Pei-Jun Sun;Juan-Jie Chen;Hong-Yi Tu;Yang-Hao Hung;Yu-Shan Lin;Fong-Min Ciou;Yu-Shan Shih;Hui-Chun Huang;
Pages: 2423 - 2429 Abstract: In this study, the electrical performance and bending stress endurance of flexible low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) are enhanced by increasing the helium concentration (1500 sccm) during gate insulator (GI) manufacture to create a high-quality GI device. Experimental results confirm that the subthreshold swing (S.S.) and mobility of these new “high-flow” devices are better than those with a lower helium concentration, which we term “low-flow” devices. The flow of helium gas is increased to achieve a better-quality oxide layer. The energy-dispersive X-ray spectroscopy (EDS) line data show a clear enhancement in oxygen content in the devices under this helium gas process. After mechanical compression and tensile bending stresses of 100000 iterations in the channel width-axis direction, perpendicular to the channel, with bending at ${R} = {2}$ mm, the modified GI devices with their more Si-O bond content exhibit less stress damage in the GI layer than do low-flow devices. As a result, this new manufacturing condition can effectively reduce the electrical degradation after negative-bias temperature stress (NBTS), and improve the overall electrical performance. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Guowei Chen;Min Guo;Xiaojie Li;Weiliang Wang;Fengjuan Liu;Ce Ning;Guangcai Yuan;Jun Chen;Shaozhi Deng;Chuan Liu;
Pages: 2430 - 2435 Abstract: The reliability of amorphous oxide semiconductor thin-film transistors (AOS-TFTs) is vital for high-definition displays and functional electronic devices. However, drain current drop (DCD) degradation has been commonly observed in the output characteristics of thin-film transistors (TFTs) with channel lengths of ${L} < 10 mu text{m}$ . Here, we show that DCD is a reversible process that is closely related to reduced metal-oxygen bonds. Based on device theory and simulations, we propose that the DCD effect is mainly caused by hot carriers, whose velocities are inversely proportional to the drain depletion width. Therefore, DCD failure could be alleviated simply by using the drain-offset structure. Experiments show that drain-offset TFTs improve DCD critical voltages (by ~130%) without sacrificing the ON-/ OFF-ratio. These studies provide theoretical and experimental approaches to effectively suppress DCD. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Kishwar Mashooq;Jaesung Jo;Rebecca L. Peterson;
Pages: 2436 - 2442 Abstract: Recently, p-type tin monoxide (SnO) thin-film transistors (TFTs) have gained interest for all-oxide complementary metal–oxide semiconductor (CMOS) circuits for flexible electronics and back-end-of-line integration with Si. However, most SnO TFTs demonstrated so far exhibit a low on– off-current ratio and limited field effect mobility. To understand and improve SnO TFT performance, it is necessary to quantitatively characterize the subbandgap defects in SnO and at its dielectric interface. In this work, we establish numerical models which provide this understanding. By concurrent fitting of simulated ${I}_{text{D}}$ – ${V}_{text{GS}}$ and effective mobility versus ${V}_{text{GS}}$ to experimentally measured data, we can accurately extract SnO defect state profiles. Using the extracted simulation models, we then identify ways to improve SnO TFT performance. Specifically, a reduction in the density of shallow, bulk Gaussian acceptor states, is necessary to reduce the off-current, while reducing the contact resistance and interface donor-like tail state density can improve the SnO field effect mobility. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Shan Li;Zu-Yong Yan;Jin-Cheng Tang;Jian-Ying Yue;Zeng Liu;Pei-Gang Li;Yu-Feng Guo;Wei-Hua Tang;
Pages: 2443 - 2448 Abstract: Heterojunction photodetectors (PDs) with photovoltaic effect could play a crucial role in future energy-conservation photoelectronic devices for their self-powered work manner. Herein, a self-powered PD was successfully constructed on the all-oxide Ga2O3/V2O5 thin-film heterojunction. With a type-I straddling band alignment, the Ga2O3/V2O5 heterostructure demonstrated an obvious photovoltaic effect with an open-circuit voltage of 0.4 V. The large bandgap (5.01 eV) of $beta $ -Ga2O3 and the effective electron–hole pair separation within heterointerface produced a superhigh solar-blind spectral discriminability for the Ga2O3/V2O5 heterojunction PD, with deep-ultraviolet (DUV)/visible rejection ratio ( ${R}_{{240}}/{R}_{{400}}$ ) of 6.0 $times 10^{{4}}$ , photo-to-dark current ratio (PDCR) of $2.6 times 10^{{7}}$ , on/off switching ratio of $1.87times 10^{{5}}$ , and specific detectivity of 7.8 $times 10^{{13}}$ Jones. The largest responsivities in self-powered mode (0 V) and power-supply mode (−5 V) were 19.8 and 79.2 mA/W, respectively. The excellent self-powered photodetection performance of Ga2O3/V2O5 oxide heterojunction provides a new strategy for next-generation energy-conservation solar-blind PDs. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Hussein M. Ayedh;Christopher W. Förbom;Juha Heinonen;Ismo T. S. Rauha;Marko Yli-Koski;Ville Vähänissi;Hele Savin;
Pages: 2449 - 2456 Abstract: Photoluminescence imaging (PLI) technique is conventionally used in silicon (Si) photovoltaics (PV) for device characterization and inline quality control, providing substantial assistance for a wafer-level process monitoring from as-cut wafers to fully fabricated devices. Surprisingly, employing this method has not spread outside PV, and thus, its potential remains largely unknown in other fields. In this case study, a fully processed Si photodetector wafer, consisting of photodiodes with various sizes, has been chosen as an example to explore the potential of PLI beyond PV. First, we show that the standard PLI measurement is able to provide a high-resolution full-wafer luminescence image of the complete devices only within a couple of seconds. The image reveals various types of inhomogeneities present in the devices, such as furnace contamination and other processing-induced defects. The measured data are then converted to an effective lifetime image followed by benchmarking with a conventionally measured recombination lifetime map obtained by microwave-detected photoconductance decay ( $mu $ -PCD), demonstrating further superiority of PLI in terms of the spatial resolution and the measurement time. Finally, correlation with diode leakage current and photoresponse measurements show that PLI is able to provide useful information on the final device performance without a need for traditional electrical contact measurements. While this study has focused on Si photodetectors, the results imply that PLI also has potential in other semiconductor devices for fast wafer-level process monitoring purposes as well as for a single device characterization either before or after wafer dicing. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Can Fu;Chuan Lu;Hai-Yang Cheng;Xiang Zhang;Zhi-Xiang Zhang;Yu-Tian Xiao;Di-Hua Lin;Jiang Wang;Ji-Gang Hu;Zhi-Li Wang;Di Wu;Lin-Bao Luo;
Pages: 2457 - 2461 Abstract: In this work, a wavelength sensor that is capable of quantitatively distinguishing the wavelength in the range of ultraviolet (UV) to near-infrared (NIR) light (265–1050 nm) is presented. The wavelength sensor is fabricated by depositing two parallel Au electrodes on the two sides of a $200 ~mu text{m}$ Si wafer. It is found that the as-formed two photodetectors display completely different optical properties. And then, the relationship between the photocurrent ratio of two photodetectors and incident wavelength can be described as a numerical function, through which the wavelength from 265 to 1050 nm can be precisely calculated. The unique operation mechanism of the Si wavelength sensor is unveiled by technology computer-aided design (TCAD) simulation. Remarkably, the wavelength sensor easily distinguishes the light with a wavelength difference of 1 nm, which is much better than previously reported devices based on the vertically stacked structures and charge collection narrowing mechanism. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Min Sun;Xiaoping Liao;
Pages: 2462 - 2468 Abstract: This article presents the theoretical and experimental investigations of a novel integrated power generator. A solar cell and a thermoelectric generator (TEG) are integrated in a single chip. The fabrication process of the integrated power generator is compatible with the CMOS process and microelectromechanical system (MEMS) technology. Hence, the TEG and the solar cell can collect luminous energy and thermal energy at the same time. The TEG consists of n-type and p-type thermal legs, which are connected in squares and can supply a dc voltage. By experimental measurements, when the TEG is covered by an aluminum layer, its voltage factor and power factor are 0.149 V/cm2K and 3.03 nW/cm2K2, respectively. The performance is better than the chip filled by thermal grease. In addition, the solar cell consists of several p-n junctions, which are formed by doping on the silicon substrate. Both the top and back of the solar cell can receive light. When light is incident on the top and bottom surfaces of the chip, the conversion efficiencies of the photoelectric generator are 4.45% and 0.682%, respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Chunyan Wu;Bin Zeng;Kunnan Zhou;Longqiang Shan;Junjie Wang;Li Wang;Yizhong Yang;Yuxue Zhou;Linbao Luo;
Pages: 2469 - 2473 Abstract: In this work, we demonstrate the fabrication of GaAs photodetector with grating perovskite (G-PVK) for a broadband enhanced ultraviolet (UV)-near-infrared (NIR) photodetection. The device shows a peak photoresponse under 530-nm illumination, presenting a responsivity of 0.3 A/W, a specific detectivity of $2.24,,times10$ 10 Jones, and 0.6/0.56 ms for rise/fall time, respectively. Compared to the device without PVK, the dark current was suppressed by two orders of magnitude and the photoresponse was enhanced up to 215%. This should be ascribed to the effective spatial separation of the vertical build-in electric field between GaAs and G-PVK and the enhanced light trapping arising from the diffraction grating. The well-aligned grating also shows a high sensitivity to the polarized light, giving rise to a peak-to-valley ratio ${I}_{{mathrm {max}}} / {I}_{{mathrm {min}}}$ of about 2.14. This suggests the potential application of the device in the polarization-sensitive imaging system. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Prashant Kumar Gupta;Utkarsh Pandey;Bhola N. Pal;Amritanshu Pandey;
Pages: 2474 - 2480 Abstract: Deep UV radiation is commonly used as a disinfectant with an appropriate dose for better efficacy. However, continuous monitoring of UV radiation is required to have appropriate dose exposure for proper disinfection. This article reports a low-cost solution-processed fabrication method of the UV photodetector (PD) with a device geometry of Al/MoS2 quantum dots (QDs)/Al on Si/SiO2 substrate, which is sensitive to deep UV radiations ~275 nm, commonly used for water and surfaces disinfection technologies. Colloidal MoS2 QDs with an average size of 1.99 nm have been synthesized by an inexpensive hydrothermal method. The surface ligand of MoS2 QDs has been replaced by a shorter ligand 1, 2-ethanedithiol (EDT) to reduce dot-to-dot distance. The fabricated device shows high responsivity (21.62 mA/W), external quantum efficiency (EQE) (9.74%), and detectivity ( $3.57times 10$ 10 Jones) under the deep UV irradiation of ~275 nm. The PD has a good photoresponse speed of rise and decay times of 173 and 92 ms, respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Takaya Sugiura;Satoru Matsumoto;Nobuhiko Nakano;
Pages: 2481 - 2487 Abstract: In this study, we propose an advanced tunnel oxide passivated contact (TOPCon) solar cell structure for bifacial usage. The proposed structure, named advanced industrial TOPCon (Ai-TOPCon), adopts rear-side local carrier-selective contacts to avoid rear-side light-absorption loss. Ai-TOPCon features larger rear-side light currents and improves the power density by approximately 0.28 mW/cm2 for bifacial usage in a 20% albedo scenario. Several types of Ai-TOPCon and industrial TOPCon (i-TOPCon) are evaluated, and the optimization of the structure resulted in a power density of 28.73 mW/cm2. Loss analysis revealed that the reduced Auger recombination volume was the main factor contributing to the improvement of cell performance, and the light-absorption problem was solved by reducing the rear-side heavy-doped region. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Mayank Dubey;Gaurav Siddharth;Ruchi Singh;Chandrabhan Patel;Sanjay Kumar;Myo Than Htay;Victor V. Atuchin;Shaibal Mukherjee;
Pages: 2488 - 2493 Abstract: This work presents the influence of substrate temperature ( ${T}_{text{sub}}$ ) and post-sulfurization on compositional, structural, electrical, and optical properties of dual-ion beam sputtering (DIBS)-grown Cu2(Sn,Ge)(S,Se)3 (CTGSSe) thin films grown on a soda-lime glass (SLG) substrate using a single target. Post-sulfurization of CTGSSe thin films is carried out in a quartz tube chemical vapor deposition (CVD) system. X-ray diffraction (XRD) analysis reveals that the crystal structure of CTGSSe thin films is preferentially tetragonal with (112) and (204) lattice planes at $2theta $ values of 27.3° and 47.3°, respectively. Field-emission scanning electron microscopy (SEM) has emphasized that the high ${T}_{text{sub}}$ growth resulted in a larger grain size of 87 nm and better thin-film morphology. Spectroscopic ellipsometry (SE) analysis shows the bandgap values of 1.46–1.62 eV by varying ${T}_{text{sub}}$ from room temperature (RT) to 300 °C. Furthermore, the bandgap widens from 1.56 to 1.64 eV in the CTGSSe thin films due to post-sulfurization. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Deepak Kumar Jarwal;Ashwini Kumar Mishra;Kamalaksha Baral;Amit Kumar;Chandan Kumar;Gopal Rawat;Bratindranath Mukherjee;Satyabrata Jit;
Pages: 2494 - 2499 Abstract: This article discusses the direct effect of the seed layers on the growth of the ZnO nanorods (ZNRs) and related photovoltaic parameters of the hybrid perovskite solar cell (PSC). Four different types of ZnO seed layer samples are prepared to analyze the growth of ZNRs over the respective seed layers. Various device parameters for the respective PSCs made of different seed layers are investigated. The ZnO quantum dot-based seed layer shows the well-aligned, vertical, and uniform distribution of ZNRs and improves SC parameters over the other three samples. The ZnO seed layer deposited via drop cast methods results in less density, random, and nonuniform distribution of the ZNRs. The surface morphology, optical absorption, transmission, and crystalline structure were analyzed with high resolution scanning electron microscopy (HRSEM), TEM, UV-visible absorption, and X-ray diffraction (XRD) techniques. 10.69% of power conversion efficiency with improved open-circuit voltage ( ${V}_{OC}$ ) of 1.01 V is achieved for device structure, fluorine doped tin oxide (FTO)/ZnO QDs seed layer/ZNRs/perovskite/poly[bis(4-phenyl)(2,5,6-trimethylphenyl)amine (PTAA)/gold (Au). PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Tingmei Fan;Min Cui;Yu Wang;
Pages: 2500 - 2507 Abstract: We have theoretically reported the cell temperature ( ${T}_{C}$ )-dependent structure and performances for experimentally available n-on-p Gax ${text{In}}_{1 -{x}}$ Asy ${text{Sb}}_{1 -{y}}$ thermophotovoltaic (TPV) cells with a bandgap at room temperature ( ${E}_{g,text{RT}}$ ) in the range of 0.50–0.60 eV. It is shown here that ${V}_{text{OC}}$ and all structure parameters, e.g., active layer thickness and grid separation, of formed cells present a linearly ${T}_{C}$ -relying reduction, while a nonlinear evolution is traced for ${J}_{text{SC}}$ and efficiency. Importantly, it is further observed that all coefficients desired for the modeling of ${T}_{C}$ -dependent evolution are ${E}_{g,text{RT}}$ -dependent and can be reasonably yet uniformly modeled by an ${E}_{g,text{RT}}$ -based cubic function. This provides an effective method to phenomenologically correlate the optimum structure and performances of Gax ${text{In}}_{1 -{x}}$ Asy ${text{Sb}}_{1 -{y}}$ TPV cell at room temperat-re with its counterpart beyond room temperature. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Guanzhong Pan;Meng Xun;Xue Chen;Zhuangzhuang Zhao;Yun Sun;Jingtao Zhou;Dexin Wu;
Pages: 2508 - 2513 Abstract: The existing Bessel beam generators generally require bulk optics counterparts and additional spatial laser sources, which adds complexity and bulkiness to the system. In this work, we propose Bessel beam devices with high compactness based on vertical-cavity surface-emitting lasers (VCSELs) and microdielectric axicons made by Si3N4. The transparent microaxicons are fabricated by one-step direct writing of focused ion beam (FIB) on the surface of meticulously designed top-emitting VCSELs. Zero- and first-order Bessel beams are obtained by engineering the lasing modes of the VCSELs through simply adjusting the oxide aperture diameter. Even if the VCSEL device works at multimode, Bessel beams can still be realized. This method provides great compatibility with different VCSEL configurations and emitting wavelengths. Such high-compactness devices may enable advanced research and applications relevant to Bessel beams. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yin Sha;Hongyun Xie;Yang Xiang;Ruilang Ji;Fu Zhu;Xiaoting Shen;Weicong Na;Dongyue Jin;Wanrong Zhang;
Pages: 2514 - 2520 Abstract: High-efficiency, high-speed phototransistors applicable in visible wavelength and the near-infrared regime are highly desirable for optical communication links utilized for data centers, high-performance computing, and laser radar application. To overcome the intrinsic weak absorption of silicon material and alleviate the compromise between efficiency and speed of the device, a SiGe/Si heterojunction phototransistor (HPT) with photon-trapping nanoholes is demonstrated in this article. With photon-trapping nanohole structures, the absorption efficiency of the HPT is greatly improved near the whole band ranging from 600- to 1000-nm wavelength compared to one without nanoholes. The responsivity of nanohole-assisted HPT is 25.69, 27.02, and 15.65 A/W at 650-, 850-, and 940-nm wavelength, exhibiting 85.22%, 192.42%, and 848.48% improvement compared with its counterpart without nanoholes. The thin base region also allows a high speed of the HPT with a transient response of 0.45 ns at 850-nm wavelength. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yuan Li;Xintian Zhou;Yuanfu Zhao;Yunpeng Jia;Dongqing Hu;Yu Wu;Liqi Zhang;Zibo Chen;Alex Q. Huang;
Pages: 2521 - 2527 Abstract: The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional ${V}_{text {TH}}$ shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Wentong Zhang;Le Zhu;Fengrun Tian;Jie Luo;Nailong He;Zhili Zhang;Sen Zhang;Jinping Zhang;Ming Qiao;Zhaoji Li;Bo Zhang;
Pages: 2528 - 2533 Abstract: A homogenization field lateral double diffused metal oxide semiconductor based on the trench-stopped depletion (TS-HOF LDMOS) is proposed and experimentally realized in this article. By solving the 3-D Poisson equation, the curvature factor ${k}$ is introduced to give the quantitative relationship between the maximum field ${E}_{text {max}}$ and parameters of the 3-D bulk curvature effect. Based on the theory, the trench-stop concept and the TS-HOF structure were proposed to reduce ${E}_{text {max}}$ . In the new structure, the depletion of the last discrete metal insulator semiconductor (MIS) array is stopped by process compatible drain trenches for suppressing the serious 3-D bulk curvature effect especially at high voltage, which is a special technology for improving breakdown voltage ${V}_{text {B}}$ of the complementary homogenization field (C-HOF) LDMOS. It was demonstrated by experiments that ${V}_{text {B}}$ of the TS-HOF LDMOS is more than 15% higher than that of the C-HOF device while maintaining the same specific ON-resistance ${R} _{text {on,sp}}$ . The TS-HOF LDMOS achieved a measured ${V}_{text {B}}$ of 675 V and a ${R} _{text {on,sp}}$ of 49.1 $text{m}Omega ,cdot $ cm2, which represents a reduction of 43.2% when compared with the theoretical value o- the triple reduced surface field (RESURF) technology. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Jizhi Liu;Yilin Liu;Aoran Han;Yanlin Nie;Qiupei Huang;Zhiwei Liu;
Pages: 2534 - 2542 Abstract: In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ce Wang;Hengyu Wang;Baozhu Wang;Haoyuan Cheng;Kuang Sheng;
Pages: 2543 - 2551 Abstract: Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of $1.8 mu text{m}$ and active area of 0.104 mm2 achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98 $text{m}Omega ,cdot $ cm2. The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the ${x}$ -direction and trapezoidal mesas in the ${y}$ -direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ( $vert {V}_{text{on}}vert $ ) and the maximum current before gate junction turn-on ( ${J}_{text{umax}}$ ). The third-quadrant performance can be improved by using forward-on gate voltage, a $vert {V}_{text{on}}vert $ lower than 0.2 V (at 100 A/cm2) and a ${J}_{text{umax}}$ larger than 500 A/cm2 are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
N. K. Kranthi;James Di Sarro;Krishna Rajagopal;Hans Kunz;Rajkumar Sankaralingam;Gianluca Boselli;Mayank Shrivastava;
Pages: 2552 - 2559 Abstract: This article discloses a unique failure mode in high-voltage bidirectional (Bi-Di) silicon-controlled rectifier (BDSCR) cells during International Electrotechnical Commission (IEC) air discharge electrostatic discharge (ESD) events. Failure was found to be sensitive to IEC measurement conditions or variabilities such as the speed of IEC gun and angle of approach, which causes different stress rise times. Hence, observed failure was a peculiar function of the rise times of the discharge current waveform. Remarkably, failure in high-voltage BDSCR was observed only for a window of current rise times. A new approach is presented using 3-D TCAD simulations of multifinger BDSCR to study and probe the failure mechanism dependent on these system-level stress parameters and variabilities. By emulating the experimental conditions in a 3-D TCAD environment, physical insights are developed to probe the root cause of the observed air discharge failures. Furthermore, a device engineering approach has been proposed, with the help of 3-D TCAD simulations of multifinger BDSCR, which computationally demonstrated improved robustness of BDSCR multifinger cells against IEC air discharge failures. The proposed design mitigates the nonuniform turn-on and failure due to IEC stress or rise time variability at the cost of a negligibly small area overhead. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Lijuan Wu;Xing Chen;Jinsheng Zeng;Shaolian Su;Haifeng Wu;
Pages: 2560 - 2565 Abstract: In this article, accumulation mode (AC) is used for superjunction (SJ) vertical double-diffused metal–oxide–semiconductor (VDMOS) and a new SJ VDMOS with extended SJ (ESJ) gate is proposed. The AC ESJ VDMOS is proposed by introducing p pillar and n pillar between the electrodes of gate and drain. In the $mathrm{scriptscriptstyle ON}$ -state, the electron accumulation layer and the inversion layer are formed in the drift region, which widens the current path and reduces the specific $mathrm{scriptscriptstyle ON}$ -resistance ( ${R}_{mathrm{scriptscriptstyle ON},text {sp}}$ ). In the $mathrm{scriptscriptstyle OFF}$ -state, the ESJ modulates the surface electric field of the drift region, which enhances the breakdown voltage (BV). Simulation results indicate that with the drift region of $19~{mu } text{m}$ , ${R}_{mathrm{scriptscriptstyle ON},text {sp}}$ of AC ESJ VDMOS can be reduced by 71.1% (0.63 $text{m}{Omega } cdot $ cm2) compared with the conventional SJ VDMOS (2.18 $text{m}{Omega } cdot $ cm2), and the BV is increased by 12.3% from 349.2 to 392.2 V. Compared with the p-type ESJ SJ VDMOS, the BV of AC ESJ VDMOS is increased by 16.23% from 617.2 to 717.4 V under the drift region of $39~mu text{m}$ . PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Habib Ahmad;Zachary Engel;Aheli Ghosh;Christopher M. Matthews;W. Alan Doolittle;
Pages: 2566 - 2572 Abstract: The use of beryllium as both an i-layer and current spreading layer (CSL) dopant in GaN quasi-vertical p-i-n diodes on sapphire was investigated. With the inclusion of the Be CSL, the current uniformity dramatically improves from $sim 40$ % of the p-contact radii to 100% resulting in higher breakdown performance and reduced leakage currents. Metal modulated epitaxy (MME) GaN p-i-n diodes on sapphire templates with beryllium-doped GaN (GaN:Be) i-layer thicknesses in the range of 1– $10~mu text{m}$ are reported. Additionally, a GaN:Be CSL sandwiched between two conductive Si-doped GaN layers is used to achieve a high quasi-vertical p-i-n diode breakdown voltage of 375 V and a breakdown field of 1.875 MV/cm for the $2~mu text{m}$ i-layer p-i-n diodes. At room temperature, the diode with a mesa diameter of $100~mu text{m}$ showed a differential ON-resistance ( ${R}_{ mathrm{scriptscriptstyle ON}} ,,=,,text{d}{V}/text{d}{I}$ ) as low as 0.3 $text{m}Omega $ -cm2 for a $10~mu text{m}$ GaN:Be i-layer diode. A Baliga’s figure of merit (BFOM) ( $text {V}_{text {Br}}^{{2}}/{R}_{ mathrm{scriptscriptstyle ON}}$ ) of 363 MW/cm2 was achieved for the $10~mu text{m}$ i-layer p-i-n diode. This is the highest reported BFOM fo- GaN p-i-n diodes on foreign substrates. Additionally, the leakage current density is very low: $1times 10^{{-{9},,{ }}}$ kA/cm2 at 300 V reverse bias for the 5 and $10~mu text{m}$ GaN:Be i-layer devices. These devices exhibit a current ON/ OFF ratio ten orders of magnitude. Given the low particle environment, rapid growth rates, ease of compatibility with the toxic dopant Be, and high device performance, the use of Be as a dopant is very useful for high-power devices. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Linlin Cai;Mingyue Zheng;Yaoyang Lyu;Wangyong Chen;
Pages: 2573 - 2578 Abstract: Electromigration (EM) of metal interconnects is the continuous reliability concern for high-density integration beyond 5-nm technology, especially for the buried power rails in vertically stacked device structure. In this work, EM reliability of alternative metal interconnects based on complementary FET (CFET) is investigated by kinetic Monte Carlo (KMC) method. The microscopic evolutions of void formation in power rails can be well reproduced by considering the coupled effects of thermal and stress distribution during the EM simulation. The influences of grain boundary in different metal materials on EM lifetime are analyzed to provide the optimal strategy of process integration. Thermal-aware EM reliability is further predicted, indicating the importance of self-heating on EM evaluation of power rails in CFET. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Oscar D. Restrepo;Dhruv Singh;Mohamed Rabie;Peter Paliwoda;Eduardo C. Silva;
Pages: 2579 - 2584 Abstract: The understanding of self-heating effects and heat dissipation in semiconductor devices is a necessary element for the accurate modeling and prediction of reliability indicators. Unfortunately, the small dimensions, the complex device structures, and the presence of thin-oxidized interfacial layers make it impractical to determine these quantities experimentally. In this work, we calculate electrical conductances ( ${sigma }$ ), electronic thermal conductances ( ${k}$ ), and their respective Lorenz numbers [ $text {L}={k}/{(}sigma {T},{)}$ ], for materials and relevant interfaces at the BEOL and MOL levels in advanced CMOS technologies. We progress from bulk to pure metal interfaces to realistically oxidized interfaces, and find the model works well, enabling a physical understanding of the impacts of oxidation, unavoidable in high-volume manufacturing. We find that Wiedemann–Franz (W–F) law applies very well for these metallic interfaces with Lorenz numbers being close to the bulk counterpart. We also find that interface oxidation exponentially increases the interface resistances. This can readily enable thermal characterization of these interfaces through electrical measurements, allowing accurate self-heating modeling for FinFET and beyond technologies. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Shuai Zhao;Guodong Yuan;Qiuhao Zhu;Luhang Song;Di Zhang;Yumeng Liu;Jun Lu;Weihua Han;Junwei Luo;
Pages: 2585 - 2589 Abstract: Cryogenic mobility enhancement, corres- ponding to the reduction of interfacial disorder, is always a research focus in Si-based MOS device manufacturing toward practical quantum computing chips. In this work, we report the dependency of MOSFET cryogenic mobility on reactive ion etching (RIE)-induced damages at 5–75 K. We discover that RIE will introduce a lot of atomic steps and charged traps at SiO2/Si interfaces or conducting channel boundaries during the mesa formation stage, severely degrading device mobility, especially at a low temperature. With a post-RIE high-temperature SiO2 regrowth process, the device cryogenic (1.8 K) peak mobility is enhanced to ~20314 cm2/( $Vs$ ) at a small electron density of $1.05times10$ 12/cm2, meaning the successful removal of RIE-induced extra effective scattering centers within the optimized device. Notably, our work presents the adverse impacts of RIE on MOS device cryogenic mobilities and provides a feasible integration flow to recover device performances, which may promote the evolution of Si-based MOS quantum dot computation. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Juhyun Kim;Hyungcheol Shin;
Pages: 2590 - 2596 Abstract: In this article, a physically based explicit analytical model for grain boundary (GB) barrier height ( $psi _{text {B}}$ ) near the polycrystalline Si (poly-Si) channel/gate oxide interface is proposed for macaroni MOSFETs, the unit cell of 3-D NAND Flash memory. The model is derived by considering a cylindrical coordinate system and is expressed as the Lambert W function and the cosine integral. To verify our model, a computer-aided design (TCAD) simulation tool, including a carrier transport model for poly Si channel, is used and calibrated against experimental data of 3-D NAND string current. The validity of $psi _{text {B}}$ -model at ${V}_{text {GS}}> {V}_{text {FB}}$ is demonstrated by comparing the model with simulation data extracted from calibrated exponential density of states (DOS) distribution for grain boundary traps (GBTs). In the verification stage, simulations are also implemented under various exponential DOS distributions and channel hole radius, and a good agreement between the model and the simulation data is achieved. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Wenhan Jia;Wen Chen;Yuhao Xiao;Zhongye Wu;Guoqiang Wu;
Pages: 2597 - 2603 Abstract: In this article, the design, implementation, and characterization of a micro-oven-controlled dual-mode piezoelectric microelectromechanical system (MEMS) resonator are presented. The designed MEMS resonator simultaneously operates in the width extensional (WE) mode and length shear (LS) mode. Both modes show high quality factor ( ${Q}$ ). The measured ${Q}$ is 15672 for the WE mode and 17781 for the LS mode. Taking advantage of the significant difference in frequency–temperature characteristics between the two modes, accurate temperature sensing and precisely closed-loop micro-oven control are implemented by phase locking the MEMS resonator at an oven-set temperature. In-plane micro-oven is composed of four folded beams and an isolation frame, which maintains an extremely uniform temperature distribution on the resonating element. The micro-oven structure requires less than 7.8 mW to maintain the resonator’s temperature at the preset temperature over variations in the external temperature range of −40 °C to 80 °C. Measured real-time frequency stability of the reported micro-oven-controlled MEMS resonator is less than ±400 ppb over a wide temperature range from −40 °C to 80 °C. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Wonjun Shin;Seongbin Hong;Yujeong Jeong;Gyuweon Jung;Byung-Gook Park;Jong-Ho Lee;
Pages: 2604 - 2610 Abstract: We investigate the effects of postdeposition annealing (PDA) ambience on the nitrogen dioxide (NO2) gas sensing performance in the Si-based field-effect transistor (FET)-type gas sensor having an indium–gallium–zinc oxide (IGZO) as a sensing material. After the IGZO thin films are deposited, the sensors are postannealed in vacuum and atmospheric ambiences. The content of oxygen vacancy in IGZO films varies depending on the PDA ambience, which changes the electrical properties and NO2 gas sensing performance of the sensors. The sensor postannealed in a vacuum ambience has more oxygen vacancy, which acts as an electrical donor, than that in an atmospheric ambience. Thus, the former has a larger coupling ratio and transconductance of the FET transducer. Also, the oxygen vacancy produces negatively charged oxygen species, increasing the response to NO2. Due to a larger response to NO2 gas and low noise, the sensor postannealed in a vacuum shows excellent signal-to-noise ratio (SNR) and limit-of-detection performances. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Vadim Jabotinski;Igor A. Chernyavskiy;Alexander N. Vlasov;Thomas M. Antonsen;Baruch Levush;
Pages: 2611 - 2617 Abstract: A theory and general method for calculating self-excitation thresholds for a large class of standing and traveling-wave structures used in amplifiers, klystrons, traveling-wave tubes, and other vacuum electronic devices (VED) is presented. One determines the circuit parameters of RF structures that are changed due to the presence of electron beam and analyze the stability of the obtained matrices. New determinant equations defined by such stability matrices are derived in a general form applicable to any RF structure and as an important special case for RF structures with electron beams. The theory and computational methods described here are essential for stability analysis of RF structures and VED. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yucheng Liu;Weihao Liu;Qika Jia;Baogen Sun;Jun Chen;
Pages: 2618 - 2624 Abstract: Compact, high-power, and broad-spectral coverage terahertz sources have application prospects in diverse scientific and technological fields, which attract great interest from researchers. The recently developed microelectronic device, a so- called terahertz laser diode (TLD), affords a promising candidate to develop desirable terahertz sources. However, the performances and the accessibility of TLD have unavoidable restrictions in the practices. In this article, we propose an enhanced TLD, which uses multiple field-emitter cathodes with an array of coupled cavities. The power and efficiency can be several times higher than that in previous TLDs. The required electric field intensity and the emission current density from the field-emitter cathode can be significantly reduced, which enables established field-emitting materials to be applicable and decreases the manufacturing difficulty as well. In addition, the fields in different cavities can be coupled, forming a series of unified oscillation modes, which can work as operation modes with various output frequencies. This improved TLD is attractive for developing compact, high-power, and broad-spectrum coverage terahertz sources for practices. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Quangui Chao;Rui Zhang;Yong Wang;Xu Zhang;
Pages: 2625 - 2630 Abstract: The efficiency of the RF power sources is one of the major concerns in the large-scale high-energy accelerator projects such as the future circular collider (FCC) and the compact linear collider (CLIC). The new bunching method, the core stabilization method (CSM), can achieve high efficiency in the case of shorter interactive length. The multibeam klystron (MBK) could accommodate high RF power with a low operating voltage, compared with a single-beam klystron. This article presents the design and simulation of a 650-MHz, 0.9-MW continuous wave (CW) CSM MBK. The detailed design of a six-beam optics system is also elaborated in this article. The performance of such a device was validated by the 3-D particle-in-cell (PIC)-code computer simulation. With an operating voltage of 50 kV, PIC simulation predicts an efficiency of 81.8%. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ruifeng Zhang;Mengzhen Li;Zugen Guo;Feng Lan;Yubin Gong;Zhaoyun Duan;Fei Xiao;Huarong Gong;
Pages: 2631 - 2636 Abstract: With demanding applications in high-data-rate communication, a folded-waveguide (FWG) traveling-wave tube (TWT) faces the challenge of gain fluctuation and bandwidth limitation. To flatten gain and extend bandwidth, a novel 3-stage gain equalization technique (GET) is proposed and applied in FWG-TWT in this article. This technique shifts the operating point to a high-frequency range in the middle section. Gain equalization can be implemented by improving gain at high frequency and decreasing gain at low frequency. Furthermore, the GET also has a significant advantage in extending bandwidth. Accordingly, a 3-stage FWG-TWT is realized. Compared with a ${Q}$ -band FWG-TWT with a uniform slow-wave structure (SWS), the 3-stage FWG-TWT extends the 3-dB bandwidth by more than ~45% and the gain variation less than 0.3 dB in the operating bandwidth, which demonstrates great improvement. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Xin Zhang;Yi Xiong;Yee Sin Ang;Lay Kee Ang;Juncheng Guo;
Pages: 2637 - 2643 Abstract: The unusual electronic properties of 3-D topological Dirac semimetals have led to intensive research efforts focusing on their potential applications in high-performance electronic, photonic, and optoelectronic devices. In this work, we propose a conceptual design of thermionic energy converters (TECs) based on a Cd3As2 anode with significantly improved performance. Using the electronic properties of Cd3As2—an air-stable topological Dirac semimetal—from first-principle density functional theory (DFT) calculation, such a device can achieve a maximum output power density and conversion efficiency of 10.96 W/cm2 and 57.29% at 1800 K, respectively. The advantages of topological Dirac anode over conventional metal- and graphene-based TECs are revealed. This work opens an exciting route toward high-performance energy converters via the union of topological material and thermionic devices. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Bingchuan Xie;Rui Zhang;Yong Wang;Huanhuan Wang;Xu Zhang;Quangui Chao;Kegang Liu;Zhihui Geng;Yunfeng Liao;Xiudong Yang;
Pages: 2644 - 2649 Abstract: In this article, the design study of a V-band klystron with an internal coupling cavity is presented. The effective characteristic impedance of the internal coupling cavity is approximately 25% higher than that of the external coupling cavity when both operate at $pi $ mode. A V-band RF circuit of 35% efficiency has been designed based on the proposed internal coupling cavity. An RF circuit based on single-gap resonators was designed first with the help of genetic algorithms (GAs). Then, a five-gap internal coupling cavity replaced the last several resonators to improve circuit bandwidth and efficiency. Simulation results have shown that the proposed internal coupling cavity can significantly improve the efficiency and bandwidth of an RF circuit based on single-gap resonators. Driven by a 60-kV and 9-A pencil beam, the designed RF circuit can achieve a peak power of 188.5 kW, a gain of 47.8 dB, and a 1-dB bandwidth of 180 MHz. The matching high compression ratio beam optics is also elaborated in this article. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yanyan Tian;Hexin Wang;Zhiwei Chang;Guoxiang Shu;Yubin Gong;Wenlong He;
Pages: 2650 - 2655 Abstract: In this article, we design an input–output energy-coupling method for the parallel operation of two terahertz folded groove waveguides (FGWs)—a conversion from TE10 mode to two modes of TE11. The mode is first converted in the H-plane of standard waveguide WR4 from TE10 to TE11, and which is then subsequently converted into two TE11 modes through a Y-branch step impedance transformation. The novel energy-coupling structure was manufactured and measured so that the S parameter $text{S}_{{11}}$ is less than −10 dB in the frequency range of 170–260 GHz. And in the frequency range of 190–250 GHz, the simulated and measured transmission coefficient $text{S}_{{21}}$ tends to be consistent. Moreover, using the coupling structure, the dispersion characteristics of the parallel operation of two FGWs was measured. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
R. Yang;J. Xu;L. Yue;P. Yin;J. Luo;H. Yin;G. Zhao;G. Guo;S. Yu;X. Niu;M. Hu;D. Liu;W. Wang;W. Liu;D. Li;Y. Wei;
Pages: 2656 - 2661 Abstract: This article reports a slow-wave structure (SWS) working at 1 THz which can be fabricated through nano-computer numerical control (nano-CNC) technology for the first time. First, a 1 THz deformed quasi sine waveguide (D-QSWG) SWS has been designed and simulated in this article. To reduce the metal loss of input and output waveguide, a coupler which transit the waveguide to over mode rectangular waveguide has been designed. The simulation result shows that input and output waveguides with this coupler have lower metal loss than that of WR1 rectangular waveguide. To fabricate the designed D-QSWG SWS, tungsten steel endmills have been used. The fabricated SWS has the surface roughness around 58–74 nm, the corresponding effective conductivity is around $2times 10^{{7}}$ –1.85 $times 10^{{7}}$ S/m. And the cold test results show that the insertion loss of the fabricated model is less than 30 dB while the reflection loss is less than −15 dB in the frequency range of 0.998–1.016 THz, which has a good consistency with the simulated results. The beam-wave interaction simulation results based on the cold test results show that the designed D-QSWG traveling wave tube (TWT) has the output power of 300 mW, and the 3 dB bandwidth is around 3 GHz. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Àndrey V. Àrzhannikov;Naum S. Ginzburg;Peter V. Kalinin;Àndrey M. Malkin;Ivan V. Martyanov;Nikolai Yu. Peskov;Denis A. Samtsov;Evgeny S. Sandalov;Alexander S. Sergeev;Stanislav L. Sinitsky;Vasily D. Stepanov;Àlexander À. Vikharev;Vladislav Yu. Zaslavsky;
Pages: 2662 - 2667 Abstract: A powerful spatially extended planar Cherenkov maser project operating in ${W}$ -band is under development in collaboration between Budker Institute of Nuclear Physics of the Russian Academy of Sciences (BINP RAS) (Novosibirsk) and Institute of Applied Physics of the Russian Academy of Sciences (IAP RAS) (Nizhny Novgorod). The ELMI accelerator (1 MeV/5–7 kA/ $3~mu text{s}$ ) forms a sheet electron beam with the transverse size (width) of up to 18 cm, which serves to drive the oscillator. The electrodynamic system of this Cherenkov maser is based on doubly periodical structure, which combines the properties of a slow wave system that realizes conditions for an effective Cherenkov interaction with a high-current rectilinear sheet electron beam and a high- ${Q}$ resonator that implements the mechanism of two-dimensional distributed feedback and provides selective excitation of the operating mode in the strongly oversized interaction space. In this article, the crucial elements and design parameters of the oscillator are discussed, and the results of simulations are presented to demonstrate the possibility of achieving a stable narrow-band generation regime for a transverse system size reaching about 50 wavelengths and a gigawatt output power level. To provide a single-directed output of radiation, a planar Bragg reflector is elaborated for installation at the cathode side of the interaction space. A mode converter formed by a slowly tapered waveguide section for transformation of the radiated wavebeam into a Gaussian-type wavebeam was designed to be installed at the oscillator output. In the electron-optical experiments, the formation of a large-width sheet electron beam with parameters acceptable to drive designed ${W}$ -band Cherenkov maser is demonstrated. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Guo Liu;Yingjian Cao;Yu Wang;Wei Jiang;Weijie Wang;Jianxun Wang;Yong Luo;
Pages: 2668 - 2674 Abstract: Overall design and cold test of a G-band gyrotron traveling-wave tube (gyro-TWT) amplifier are presented. This gyro-TWT aims at achieving a goal of 10-kW pulse output power in the range of 210–220 GHz. It is operated in a circular TE01 mode at the fundamental cyclotron harmonics, which is driven by a 50-kV, 3-A gyrating electron beam. Low velocity spread diode-type magnetron injection gun (MIG), multichannel TE01 mode input coupler, broadband metasurface output window, and lossy material loaded beam–wave interaction circuit are simulated and partially measured. Particle-in-cell (PIC) simulation shows that the designed gyro-TWT can achieve a saturated output power over 10 kW in the range of 210–228 GHz with a beam velocity spread of 2.29%. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
E. Taradaev;G. Sominskii;
Pages: 2675 - 2679 Abstract: Characteristics of annular electron flow formed in electron gun with a multitip field emitter were determined experimentally and by numerical simulations, and the possibility to achieve electron beam current up to 75 mA was demonstrated. The gun performance was stable in technical vacuum conditions—at the pressure of ~10−7 torr. Electron velocity distributions in a flow on transverse and longitudinal components were determined. It was shown that the relative root-mean-square transverse velocity spread varied with radial coordinate within the annular beam wall from ca. 6% to 30%, while the total spread in the electron flow was about 60%. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Carlotta Gastaldi;Matteo Cavalieri;Ali Saeidi;Eamon O’Connor;Francesco Bellando;Igor Stolichnov;Adrian M. Ionescu;
Pages: 2680 - 2685 Abstract: In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond-range pulses enables us to observe hysteresis-free NC and reconstruct the ${S}$ -shaped polarization-voltage curves. The devices with the inner metal plate show a higher equivalent NC value, which offers the potential for a higher differential amplification in a NC-FET. However, such a NC region is observed over a smaller range of electric field and polarization, which leads to hysteresis. Moreover, the presence of a metal layer in between the ferroelectric and the insulator favors domain formation resulting in destabilization of the NC effect. For the gate structure where the ferroelectric and the insulator are in contact, the ${S}$ -shaped polarization-voltage curve shows a better agreement with Landau–Ginzburg–Devonshire formalism for the monodomain state. The uniform polarization closely mimicking the monodomain state is possible due to the polarization imprint occurring due to the structural asymmetry. By nanometer resolution polarization mapping via off-resonance piezoelectric force microscopy (PFM), we corroborate the presence of imprint, which can intrinsically stabilize one ferroelectric state. Overall, the article provides an experimental demonstration that the absence of the inner metal plane in the gate structures stabilizes the NC regime favorable for hysteresis-free NC-FET. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Chandra Prakash Singh;Saurabh Kumar Pandey;
Pages: 2686 - 2691 Abstract: In this article, we have investigated the forming free bipolar resistive switching (RS) phenomena of ${e}$ -beam evaporated amorphous tin-oxide-based RS device with copper as a bottom electrode. To describe the impact of copper electrode over electrical response of tin-oxide-based RS device, we have used tungsten probe tip contact as a top electrode and copper as a bottom electrode. The crystal structure, energy bandgap, surface morphology, and device cross-sectional nanostructure view of deposited thin RS layer (tin-oxide) have been characterized by using X-ray diffraction (XRD), UV–visible spectroscopy, and field-emission scanning electron microscopy (FESEM), respectively. The electrical behavior of fabricated switching device has been recorded by Keithley-4200 parametric analyzer with customized probe station. Reported switching device has capability to perform reversible RS phenomena for 500 cycles with low set/reset (−0.52/0.39 V) voltage and good resistive window (~15) without any considerable degradation. We have also discussed the primary reason for RS dynamics in the proposed device along with its conduction mechanism. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Suruchi Sharma;Rikmantra Basu;Baljit Kaur;
Pages: 2692 - 2697 Abstract: The dopingless tunnel field-effect transistors (DLTFETs) are captivating researchers over conventional TFETs as the former eliminates fabrication-related challenges such as random dopant fluctuations, requisite high thermal budget, and expensive annealing techniques, along with providing benefits of conventional TFET such as extremely low off-state current ( $I_{{off}} $ ), less than 60-mV/dec average subthreshold swing, and immunity toward short-channel effects. However, DLTFET also faces challenges of low on-state current ( $I_{{on}} $ ) and variation in electrical characteristics with temperature as bandgap of semiconductor material varies with temperature. So, in this article, we investigate the temperature-associated variations of Si/Ge heterojunction asymmetric-double-gate DLTFET (HJ-ADG-DLTFET) under the influence of interface trap charges (ITCs) for reliability assessment. This is done by investigating the effect of ITC along with temperature variations from 200 to 500 K, on analog/RF and linear performance metrics via simulations using Silvaco ATLAS. It is found that the Shockley-Read-Hall (SRH) phenomenon dominates at lower gate bias, resulting in $I_{{off}} $ degradation at elevated temperatures. However, band-to-band tunneling (BTBT) phenomenon is prevalent at large gate voltage, which is weakly dependent on variations in temperature. Accordingly, at high temperatures, $ I_{{off}} $ is deteriorated by an order of 10⁵ , that is, increases from 10⁻¹⁷ A (200 K) to 10⁻¹² A (500 K). Also, at high temperatures, the reduction in threshold voltage ( $ V_{th} $ ) and delay (τ) and, increment in cut-off frequency ( $ f_{T} $ - is observed, causing up-gradation in device performance. Furthermore, the impact of source-gate length ( $ L_{GAP,S} $ ), drain-gate length ( $ L_{GAP,D} $ ), and semiconductor body thickness ( $ T_{Si} $ ) variations are also investigated. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Cheng Wang;Fuquan Wang;Yitong Xie;Ruiqing Xing;Yuan Jia;Wenwei Zhang;Bo Zhang;Tingting Han;Weixiang Ye;
Pages: 2698 - 2704 Abstract: In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Zijuan Peng;Weijie Ye;Zhi Luo;Junkai Huang;Wanling Deng;
Pages: 2705 - 2710 Abstract: In this article, a physics-based analytical current model for armchair graphene nanoribbon field-effect transistors (A-GNRFETs) is developed, which is valid from ballistic to quasi-ballistic transport regimes. The roles of line-edge roughness (LER) for different roughness parameters and Fermi level of GNRs are numerically investigated. Furthermore, the effect of LER-related tunneling current has a strong impact on the drain–source current for the OFF state, and it is considered in this model. The good agreement between our proposed current model and the nonequilibrium Green function (NEGF) simulations proves its validity. The results indicate that depending on the geometrical and roughness parameters, the transport properties can be ballistic or quasi-ballistic. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Xinpei Jia;Jinjuan Xiang;Hao Xu;Wenjun Liu;Xiaolei Wang;Wenwu Wang;
Pages: 2711 - 2717 Abstract: The ferroelectric field-effect transistor (FeFET) is a promising candidate for emerging memory. However, data retention loss is a key issue. One reason for the data retention loss is the depolarization field ( ${E}_{dep}$ ). In this work, we theoretically investigate ${E}_{dep}$ of ferroelectric transistors with the metal/Hf0.5Zr0.5O2/SiO2/Si substrate (MFIS) gate structure considering the minor loop and charge trapping effect at the ferroelectric/interlayer interface. We find that ${E}_{dep}$ increases first and then decreases with the increased interlayer thickness ( ${t}_{IL}$ ). The charge trapping phenomenon will decrease ${E}_{dep}$ and make ${t}_{IL}$ at which ${E}_{dep}$ reaches the peak value larger. To design a ferroelectric transistor considering both the depolarization field and the memory window, different schemes about how to choose suitable interlayer and ferroelectric layer thicknesses in three different regions need to be adopted. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ana Mitrovic;Eby G. Friedman;
Pages: 2718 - 2724 Abstract: The operation of rapid single flux quantum (RSFQ) circuits depends upon the superconductive properties of the Josephson junctions (JJs) and metal layers, which are highly dependent on the temperature. Increasing densities and frequencies of JJs in RSFQ circuits have created a need to accurately model the local ambient thermal environment. In this article, an analytic thermal model of RSFQ circuit structures targeting the MIT Lincoln Laboratory SFQ5ee 10 kA/cm2 technology is presented. The model is based on a network of thermal resistances, representing the heat generation and thermal paths within an RSFQ circuit. An error of less than 0.22% between the model and a numerical solver is achieved. To reduce the computational complexity, the sparsity of the matrix of thermal resistances among the nodes is increased by exploiting the effective radius of the heat spreading behavior. Ignoring the thermal effects of the heating elements outside of a target radius reduces the number of thermal resistances by 50%, increasing the maximum error of the model to only 0.26%. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Sumit Choudhary;Daniel Schwarz;Hannes S. Funk;D. Weißhaupt;Robin Khosla;Satinder K. Sharma;Jörg Schulze;
Pages: 2725 - 2731 Abstract: There are vital challenges to harness the unique assets of germanium (Ge) because of Ge-on-insulator (GeOI) processing issues. The advances in molecular beam epitaxy (MBE) technology have enabled the defect-free growth of atomic-level Ge stacks over the standard monolithic silicon platform to leverage the properties of the Ge as a channel layer. Here, we present the first ever report on the authoritative integration of ferroelectric (FE) hafnium zirconium oxide (HZO) over the p-Ge/n-Ge $_{-on-}text{n}$ -Si system. A rudimentary approach for the carrier modulation in the channel was employed using depletion approximation and negative capacitance (NC) to fabricate HZO and thin p-Ge channel-based FET. The TaN/HZO/TaN stacks were optimized and characterized for enhanced ferroelectricity and non-centrosymmetric orthorhombic phase, which is further confirmed with piezoresponse force microscopic (PFM) analysis. The trivial loop hysteresis conditions to validate the NCFET operation was discussed. The devices demonstrated a lower subthreshold swing (SS) of ~23.44 mV/dec and ${I}_{ mathrm{scriptscriptstyle ON}}/{I}_{ mathrm{OFF}}$ ratio of 105. The threshold voltage shift ${V}_{t} = -0.6$ and −1.1 V with the body bias voltage of 0.25 and 0.5 V, respectively. Minimum DIBL measured ~26 mV/V, and rule-out gate induces drain lowering (GIDL) effect due to no gate–drain region overlap. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Chih-Chieh Hsu;Yu-Sheng Chien;Wun-Ciang Jhang;
Pages: 2732 - 2737 Abstract: An aluminum oxynitride (AlOx:N) resistive memory with a large ON/OFF ratio of 106 at a low read voltage of 0.5 V is proposed. The AlOx:N resistive switching (RS) layer is fabricated using a two-stage thermal oxynitridation process of an evaporated Al film. The Al/AlOx: N/n+-Si device shows write-once–read-many-times (WORM) characteristics and the writing operation is voltage-polarity-independent. The resistance states can be repeatably read $10^{4}times $ and the data retention time is over 104 s. A high read-disturb immunity is also observed for over 104 s. Data retention and read-disturb characteristics measured at 85 °C predict a ten-year lifetime of the device. The carrier transport and the RS mechanisms are studied and illustrated. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
You-Sheng Liu;Pin Su;
Pages: 2738 - 2740 Abstract: This brief investigates scaled 2-D MoS2 ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS2 channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS2 FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS2 and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS2 FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Zheng Wen;Jirun Luo;Ying Li;Zhiqiang Zhang;Fang Zhu;Wei Guo;Min Zhu;
Pages: 2741 - 2741 Abstract: In the above article [1], comparing (14) and (15) with (1), for all units of the NP ML-SWS to satisfy the BWS condition, the simplest way is to define the relationship between $L_{n}$ and $d_{n}$ as (16). Such that (16) should read as PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Pages: 2742 - 2743 Abstract: Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Pages: 2744 - 2745 Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Pages: 2746 - 2746 Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Pages: 2747 - 2747 Abstract: Advertisement: This publication offers open access options for authors. IEEE open access publishing. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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