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  Subjects -> ELECTRONICS (Total: 207 journals)
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IEEE Solid-State Circuits Letters
Number of Followers: 0  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Online) 2573-9603
Published by IEEE Homepage  [228 journals]
  • High-Efficiency 28-/39-GHz Hybrid Transceiver Utilizing Si CMOS and GaAs
           HEMT for 5G NR Millimeter-Wave Mobile Applications

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      Authors: Youngmin Kim;Hongjong Park;Sangmin Yoo;
      Pages: 1 - 4
      Abstract: This letter presents the first demonstration of 5G millimeter-wave hybrid front-ends (FEs) for a phased-array transceiver in order to show efficient transmitter performance with low cost and compact area. The configuration of the proposed hybrid FEs is CMOS-based FEs combined with compact GaAs HEMT-based power-cell array to obtain all the benefits of silicon and III-V technology. The architecture and design method of a millimeter-wave transmitter (TX)/receiver (RX) combiner for antenna-port sharing suitable for the proposed hybrid structure is newly introduced. A developed 29-GHz transceiver FE achieves a linear output power of 14.9 dBm with PAE of 28.5% at SC-FDMA 64QAM 100-MHz EVM of −25 dB in TX mode and noise figure (NF) of 5.5 dB in RX mode. Moreover, a developed 38-GHz transceiver FE achieves a linear output power of 12.8 dBm with PAE of 25.2% at SC-FDMA 64QAM 100-MHz EVM of −25 dB in TX mode and NF of 5.5 dB in RX mode.
      PubDate: 2023
      Issue No: Vol. 6 (2023)
       
  • A 0.11-mW 2.4-GHz Receiver Employing a Q-Boosted Impedance Transformer and
           Regenerative Amplifier Achieving −101-dBm Sensitivity and −28-dB SIR

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      Authors: Bao H. Lam;Hongyu Lu;Ahmed G. Gadelkarim;Nader Fathy;Prasad Gudem;Patrick P. Mercier;
      Pages: 5 - 8
      Abstract: This letter presents a 2.4-GHz OOK receiver that employs a $Q$ -boosted impedance transformer and a regenerative amplifiers (RA) to provide high gain and sharp filtering prior to demodulation. A differential envelope detector (ED) is also used to increase the conversion gain further to help nullify the noise contribution of the subsequent baseband stages. Fabricated in 65 nm, the receiver achieves a sensitivity of −101 dBm at a data rate of 5 Kb/s, all while consuming $112~mu text{W}$ . The sharp RF filtering helps enable a signal-to-interference ratio (SIR) of −28 dB.
      PubDate: 2023
      Issue No: Vol. 6 (2023)
       
  • A High-Output Power 1-V Charge Pump and Power Switch for Configurable,
           In-Field-Programmable Metal eFuse on Intel 4 Logic Technology

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      Authors: Stafford Hutchins;Atresh Sanne;Zhanping Chen;Mohammad M. Hasan;Uddalak Bhattacharya;Eric Karl;Jaydeep P. Kulkarni;
      Pages: 9 - 12
      Abstract: A flexible, low-cost design solution for in-field-programmable (IFP) metal eFuse is reported. The design maximizes fuse yield through a tunable program voltage provided by a two-stage charge pump (CP), placed in closed loop (CL) with a low dropout regulator (LDO). The integration of CP and LDO solves electrical over-stress (EOS) concerns and achieves stability and low voltage operation through several design innovations. The CP integrates with the fuse macro by distributed, extra-high voltage (EHV) power-gate power-switch (PGPS), which switches between CP and nominal supply for fuse read, increases array efficiency, and reduces leakage. The solution does not require a specific power sequence or metal–insulator–metal cap, enabling maximum design adaptability and integration flexibility. This design is implemented and characterized on Intel 4 technology, where >99.9% successful fuse bit program was measured across [−40 °C, 125 °C] temperature, and down to 0.95 V.
      PubDate: 2023
      Issue No: Vol. 6 (2023)
       
  • A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3×
           Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

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      Authors: Andac Yigit;Emmanuel Nieto Casarrubias;Robert Giterman;Andreas Burg;
      Pages: 13 - 16
      Abstract: Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process nodes, leading to frequent power-hungry refresh operations. In order to reduce the refresh overhead, GC-eDRAM macros utilize external assist voltages which improve the bitcell write-ability, leading to an enhanced DRT. However, the requirement for external analog supply voltages creates additional overhead and is often impractical in the design of compact systems-on-chip (SoC). This work presents an on-chip write-assist technique implemented with a negative boosted bootstrap driver which generates the required wordline boosting on-chip without external components. The proposed circuitry is integrated compactly inside the GC-eDRAM macro to provide an area-efficient low-power solution which improves the bitcell’s write-ability and reduces its refresh requirement. A 128-kbit GC-eDRAM macro utilizing the proposed boosting circuitry has been fabricated in a 28-nm FD-SOI technology, demonstrating an $11.3times $ DRT improvement at only 2.5% area overhead.
      PubDate: 2023
      Issue No: Vol. 6 (2023)
       
 
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