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IEEE Solid-State Circuits Letters
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  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Online) 2573-9603
Published by IEEE Homepage  [228 journals]
  • Three-Winding Transformer-Based 60-GHz DCO With −185.1-dB FoM in
           40-nm CMOS

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      Authors: Yun Fang;Robert Bogdan Staszewski;Hao Gao;
      Pages: 1 - 4
      Abstract: This letter presents a 60-GHz fundamental DCO featuring an FoM of −185.1dB at a 10-MHz offset. The DCO is intended for a 60/120-GHz fundamental-and-harmonic dual-frequency Doppler radar thanks to its cost-efficiency advantages. Based on a three-winding transformer, the proposed class-F DCO achieves good phase noise (PN), which is essential for narrowing the detected range uncertainty. In this work, a $pi $ -model of the three-winding transformer is adopted and analyzed. A methodology of optimizing the resonator’s quality factor and the zero-crossing slope is proposed. The DCO is fabricated in 40-nm CMOS and achieves a 14% tuning range with a minimum frequency step of 2.3MHz. At 66.4GHz, the measured PN is −98.2dBc/Hz at 1-MHz offset, and −120.1dBc/Hz at 10-MHz offset.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • An N-Way Single-Inductor High-Pass Power Divider for 5G
           Applications

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      Authors: Aniello Franzese;Renato Negra;Andrea Malignaggi;
      Pages: 5 - 8
      Abstract: This letter reports on the analysis and the design of a novel N-way single-inductor power divider (PD), which allows for a compact size regardless of the number of ports. Moreover, the reported topology simplifies the interconnection of the isolation resistors, making the design of PDs with more than four ports straightforward and systematic. Finally, a 4-way silicon prototype has been fabricated employing the IHP SG13S BiCMOS technology to validate the concept. The chip is meant for mmWave frequencies and is devoted to 5G applications. It occupies an area of 0.005 mm2 and provides a minimum loss of 1 dB, as well as phase and amplitude errors lower than 0.4 dB and 2°, respectively, in the band of interest. To the best of our knowledge, this design results in the smallest silicon area occupation, halving the size with respect to the state-of-the-art PDs. Comparable physical dimensions to the presented 4-way PD can only be achieved with 2-way designs.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Fully Digital On-Chip Wideband Background Calibration for Channel
           Mismatches in Time-Interleaved Time-Based ADCs

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      Authors: Okko Järvinen;Ilia Kempi;Vishnu Unnikrishnan;Kari Stadius;Marko Kosunen;Jussi Ryynänen;
      Pages: 9 - 12
      Abstract: This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an $8times $ TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 17-mW 0.5–1.5-GHz Bandwidth TIA Based on an Inductor-Stabilized OTA
           With 35–42-dBm In-Band IIP3

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      Authors: Nimesh Nadishka Miral;Danilo Manstretta;Rinaldo Castello;
      Pages: 13 - 16
      Abstract: A transimpedance amplifier (TIA) is presented for 5G and future mobile standards. The bandwidth of the TIA can be programmed from 500 MHz to 1.5 GHz. The operational transconductance amplifier (OTA) is designed combining feedforward compensation and inductive peaking, to ensure loop stability and obtain high loop gain with low-power dissipation. TSMC 28-nm HPC technology was used to implement a test chip. With a power dissipation of 17 mW, the TIA achieves an in-band IIP3 ranging from 35 to 42 dBm and output integrated noise of 300 $mu $ Vrms.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Frontend for Magnetoresistive Sensors With a 2.2-pA/√Hz Low-Noise
           Current Source

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      Authors: Ayman Mohamed;Marco Wagner;Hadi Heidari;Jens Anders;
      Pages: 17 - 20
      Abstract: In this letter, we present an integrated readout chip for magnetoresistive (MR) sensors consisting of a readout chain that comprises a dc-coupled fully differential difference amplifier (FDDA) followed by a programmable gain amplifier (PGA), as well as a low-noise current biasing scheme for the MR sensor. The current bias scheme features a 10-bit digital-to-analog converter (DAC) to compensate for process variations of the MR sensing element as well as to calibrate for variations in the dc bias field of the sensor. The bias current source achieves a very low current noise floor of 2.2 pA/ $sqrt {mathrm {Hz}}$ for bias currents up to 1 mA. The readout chip is manufactured in 180-nm SOI CMOS and consumes a total power of 38 mW. The letter is an extended version of (Mohamed et al., 2021) incorporating additional modeling details and measurement results.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • 112G+7-Bit DAC-Based Transmitter in 7-nm FinFET With PAM4/6/8
           Modulation

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      Authors: Euhan Chong;Sina N. Shahi;Faisal A. Musa;Ahmed N. Mustafa;Peter Krotnev;Paul Madeira;Davide Tonietto;
      Pages: 21 - 24
      Abstract: This letter describes a 56 Gbaud 7-bit DAC-based transmitter (TX) demonstrating data rates of 112, 140, and 168 Gb/s in PAM4, PAM6, and PAM8, respectively. The TX with 1.2-Vppd high-swing driver is implemented in a 7-nm FinFET process. Time domain analysis is performed to compare PAM modulation formats. The power efficiency is 1.5 pJ/b (PAM4) and 1.0 pJ/b (PAM8).
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Swing-Enhanced Class-D VCO Using a Periodically Time-Varying (PTV)
           Inductor

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      Authors: Xiaoqi Lin;Jun Yin;Pui-In Mak;Rui P. Martins;
      Pages: 25 - 28
      Abstract: This letter reports the design and analysis of a swing-enhanced class-D voltage-controlled oscillator (VCO) utilizing a periodically time-varying (PTV) inductor to boost the output swing that effectively improves the phase noise (PN) in both $1/f^{2}$ and $1/f^{3}$ regions at a low supply voltage ( $V_{mathrm{ DD}}$ ). Without extra switches, the PTV inductor reuses the original cross-coupled transistors in the class-D oscillator that semiperiodically cancels the magnetic flux between two coupled inductors. Fabricated in 65-nm LP CMOS, the 3.67-to-4.43-GHz VCO prototype measures figure of merits of 192.4 ± 1.5 dBc/Hz at 1-MHz offset frequency and 194.4 ± 0.8 dBc/Hz at 10-MHz offset frequency when the $V_{mathrm{ DD}}$ varies from 0.3 to 0.4 V.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • SRAM With Stability Monitoring and Body Bias Tuning for Biomedical
           Applications

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      Authors: B. Vanhoof;W. Dehaene;
      Pages: 29 - 32
      Abstract: This work presents a novel low-leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep submicron technology nodes, it includes static noise margin monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of the first failure. As proof of concept, a macro of 1 Mb is fabricated in 22-nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 12-V Single-Input Multiple-Independently Configurable-Output Dynamic
           Voltage Scaling Supply in Standard 0.18-μm CMOS for Electrical
           Stimulation Applications

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      Authors: Xuetao Zeng;Xuan Zhang;Zeyu Wang;Zhengtuo Zhao;Xue Li;Lei Yao;Ning Xue;
      Pages: 33 - 36
      Abstract: This letter presents the design and implementation of a single-input multiple-independently configurable-output (SIMICO) dynamic voltage scaling supply (DVSS) for multiple-channel electrical stimulation applications. The proposed SIMICO DVSS mainly consists of a 3-stages charge pump (CP) and 16 low-voltage (LV) compatible 5:1 power multiplexers (MUXs). The 3-stages CP is supplied by a single supply VDD and capable of outputting four voltage levels VDD, 2 $times $ VDD, 3 $times $ VDD, and 4 $times $ VDD. Each of the 16 LV compatible 5:1 power MUX can be independently configured to connect its output to GND or one of the four generated voltage levels from the CP, which enables individual channel supply control (ICSC) for multiple-channel stimulation applications. The proposed circuit achieves maximum 12-V output voltage and 1-mA output current with maximum 32% energy reduction compared to the conventional DVSS architecture. This design is implemented in SMIC standard 1.8/3.3 V 0.18- $mu text{m}$ CMOS process occupying a core area of $1500,,mu text{m},,times 1200,,mu text{m}$ .
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Positive-Feedback-Based Design Technique for Inherently Stable Active Load
           Toward High-Gain Amplifiers With Unipolar a-IGZO TFT Devices

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      Authors: Mohit Dandekar;Kris Myny;Wim Dehaene;
      Pages: 37 - 40
      Abstract: This letter presents analysis of an inherently stable positive-feedback-based active load, first reported in our prior work, to realize high gain analog amplifiers using unipolar a-IGZO TFT technology. Additionally reported are theoretical performance bounds and design guidelines to maximally utilize a general positive-feedback scheme for the active load while maintaining stability. To demonstrate a design implementation, a single stage fully differential operational transconductance amplifier with common mode feedback has been manufactured and measured to have 40-dB open-loop gain at dc and a unity gain frequency of 61 kHz while driving a 30-pF load capacitance.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 0.5-mm2 Solar Cell-Powered Biofuel Cell-Input Biosensing System With LED
           Driving for Stand-Alone RF-Less Continuous Glucose Monitoring Contact Lens
           

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      Authors: Guowei Chen;Yue Wang;Tran Minh Quan;Naofumi Matsuyama;Takuya Tsujimura;Kiichi Niitsu;
      Pages: 41 - 44
      Abstract: This letter presents the first solar cell (SC)-powered biofuel cell (BFC)-input biosensing system with pulse interval modulation (PIM) and pulse density modulation (PDM) LED driving capability for continuous glucose monitoring (CGM) contact lenses featuring stand-alone RF-less operation. Power supply from on-lens SCs can eliminate the necessity of wireless power delivery, and LED implementation can eliminate the necessity of wireless communication. By employing the BFC-input approach instead of using a power-hungry potentiostat, powering and sensing components are separated, which reduces the power budget from SCs. The measured power of 28/144 nW at the PIM/PDM mode with a 0.31/0.39-V supply voltage can be managed by the on-lens SCs, enabling a fully stand-alone on-lens operation under office-room ambient light whose typical illumination intensity is 800–1600 lx.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Mixer-First Receiver With Class-F Adiabatic Switching

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      Authors: Tim Schumacher;Markus Stadelmayer;Harald Pretl;
      Pages: 45 - 48
      Abstract: This letter introduces the use of class- F adiabatic switching in a mixer-first 2.45-GHz ISM-band receiver. By using the principle of adiabatic switching with a class-F VCO, a resonant multiharmonic drive for an N-path-based mixer-first receiver is generated, resulting in a reduced power consumption while maintaining a good mixer noise figure (NF). To optimize the area, coupled inductors in the VCO are used. By employing a switched capacitor (SC) feedback network in the baseband (BB) amplifier, a proper input matching and flexible common-mode (CM) bias is achieved. A packaged chip implemented in 28-nm CMOS achieves a low-power consumption of 3.5 mW with a gain of 22 dB and an NF of 7.4 dB.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Editorial

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      Authors: Tony Chan Carusone;
      Pages: 49 - 49
      Abstract: The IEEE Solid-State Circuits Letters is now over four years old. Our Editorial Board has led the Letters through its initial growth into a thriving, stable publication of the Solid-State Circuits Society. The Editorial Board’s continual renewal is essential to the Letters’ long-term success. Thus, at this time, Chih-Cheng Hsieh, Hun-Seok Kim, Nima Maghari, and Hoi-Jun Yoo are retiring after having provided excellent service as Editorial Board Members since the beginning. On behalf of the entire community, I sincerely thank them.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • 5-nm Low-Power SRAM Featuring Dual-Rail Architecture With Voltage-Tracking
           Assist Circuit for 5G Mobile Application

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      Authors: Sangyeop Baeck;Inhak Lee;Hoyoung Tang;Dongwook Seo;Jaeseung Choi;Taejoong Song;
      Pages: 50 - 53
      Abstract: Voltage auto tracking cell power lowering (VACPL) write assist circuit and voltage auto tracking assist (VATA) are proposed for low-power SRAM with dual-rail architecture to mitigate the SRAM design margin issues. VACPL controls the cell voltage adaptively with respect to the dual-rail offset voltage to maximize bitcell write-ability. The access disturb is recovered by lowering the WL voltage level with VATA at the large dual-rail offset voltage condition. A 5-nm EUV FinFET test chip demonstrates 210-mV $text{V}_{mathrm{ MIN}}$ improvement and $4.7times $ larger range of operating voltage with VACPL. The proposed VACPL and VATA achieve 95.2% leakage power reduction by lowering VDDC by 400 mV in 5-nm 5G mobile device.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Track and Hold Amplifier Investigation for 100-GHz Bandwidth, 200-GS/s ADC
           Front Ends

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      Authors: Gregory Cooke;Naftali Weiss;Peter Schvan;Pascal Chevalier;Andreia Cathelin;Sorin P. Voinigescu;
      Pages: 54 - 57
      Abstract: We report on the track and hold amplifier (THA) topology choice and design details of a $4times $ time-interleaved 200-GS/s SiGe BiCMOS ADC front end with a measured SNDR > 25 dB up to 63 GHz, and with a large signal bandwidth of 58 GHz when subsampling at 5 GS/s. We show that by replacing the current-mode-logic (CML) MOS switch with a quasi-CML switch and increasing the tail current, a THA with a measured small-signal bandwidth of 101 GHz is obtained in the same 55-nm SiGe BiCMOS technology. The ADC front end bandwidth could thus be further improved at the same sampling rate.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 3T eDRAM In-Memory Physically Unclonable Function With Spatial Majority
           Voting Stabilization

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      Authors: Jiahao Song;Haoyang Luo;Xiyuan Tang;Kuan Xu;Zhigang Ji;Yuan Wang;Runsheng Wang;Ru Huang;
      Pages: 58 - 61
      Abstract: This letter presents a 3T eDRAM in-memory physically unclonable function (PUF) for low-cost Internet of Things (IoT) applications. The proposed design integrates PUF to eDRAM with a small peripheral overhead. With the subthreshold leakage of the bit-cell read path exploited as the entropy source, two adjacent 3T eDRAMs (with 2 $times $ 197 F2=394 F2 area) race to generate the key bit. To overcome voltage and temperature variations, the spatial majority voting (SMV) is adopted. Implemented in 65-nm CMOS, the proposed eDRAM PUF achieves < 0.35% bit error rate (BER) across a voltage range of 1.0–1.2 V and temperature range of 0 °C–60 °C, presenting a low-cost and robust solution for IoT security.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 196.5 dBc/Hz FOM T 16.8–21.6-GHz Class-F23 CMOS VCO With
           Transformer-Based Optimal Q-Factor Tank

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      Authors: Feifan Hong;Tianao Ding;Dixian Zhao;
      Pages: 62 - 65
      Abstract: This letter presents an optimal tank- $Q$ Class-F23 voltage-controlled oscillator (VCO) in 65-nm CMOS. The $Q$ -factor of the transformer-based multi-LC resonator is maximized in the Class-F operation mode by the proposed graphical $Q$ -optimization method. The frequency tuning range (TR) is expanded by 26% as well. The phase noise (PN) is improved by reshaping the impulse sensitivity function (ISF) with the 2nd and 3rd harmonic tuning. Occupying 0.112 mm2, the VCO at 16.8 GHz exhibits −112.2 dBc/Hz PN at 1 MHz offset and 196.5 dBc/Hz $text{FOM}_{T}$ at 10 MHz offset. The measured TR is 25% (16.8–21.6 GHz). The oscillator core consumes 7 mW at 1 V supply.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A GMSK/PAM4 Multichannel Magnetic Human Body Communication Transceiver

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      Authors: Miao Meng;Hossein Rahmanian Kooshkaki;Xiaoyang Wang;Shih-Kai Kuo;Erda Wen;Patrick P. Mercier;
      Pages: 66 - 69
      Abstract: This letter presents a dual-mode multichannel transceiver implemented with low path loss offered by magnetic human body communication (mHBC) toward ultraefficient body-area networking. Two spectral-efficient modulation schemes: 1) Gaussian minimum-shift keying (GMSK) and 2) 4-level pulse-amplitude modulation (PAM4), are used to reduce interference on adjacent channels. A power oscillator is used to efficiently generate both GMSK- and PAM4-modulated magnetic fields while multichannel selection is implemented by on-chip capacitor tuning and an analog PLL, enabling 5 and 10 Mb/s data for GMSK and PAM4, respectively. The transmitter achieves an efficiency of 15.5 and 19.4 pJ/bit, while the receiver consumes 4.6 and 2.7 pJ/bit for GMSK and PAM4, respectively.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Energy-Efficient In-Memory Binary Neural Network Accelerator Design Based
           on 8T2C SRAM Cell

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      Authors: Hyunmyung Oh;Hyungjun Kim;Daehyun Ahn;Jihoon Park;Yulhwa Kim;Inhwan Lee;Jae-Joon Kim;
      Pages: 70 - 73
      Abstract: We present an in-memory binary neural network (BNN) accelerator based on 8-transistor and 2-capacitor (8T2C) SRAM cell. The proposed SRAM computing-in-memory (CIM) cells rely on DRAM-like charge sharing operations to avoid undesirable static currents and potential read-disturb problems in conventional resistive SRAM-CIM designs. In addition, unlike the previous capacitive SRAM-based CIM designs, the proposed SRAM CIM does not consume energy when the input value is 0, thereby achieving the higher energy efficiency in benchmark testing. Measurement results of the 256 $times $ 64 array prototype chip in the 28-nm CMOS technology showed 3182 TOPS/W at 0.7 V which is $4.7times $ higher energy efficiency than that of a state-of-the-art design.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A CMOS Peak Stretcher/Peak Detector for Wide Dynamic Range Spectroscopy
           Applications With 32-μW Power Consumption

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      Authors: Filippo Mele;Irisa Dedolli;Giuseppe Bertuccio;
      Pages: 74 - 77
      Abstract: A CMOS peak stretcher for pulse-height analysis in spectroscopy applications with an optimized peak-height accuracy and low power consumption, is presented. The proposed circuit has a minimized switch-on transient overshoot, which guarantees a high accuracy also for low-amplitude input pulses. The experimental characterization of the circuit, fabricated in low-noise 0.35- $mu text{m}$ CMOS technology, are presented, showing a peak-height error below 1% across the 10 mV–1 V input range, and a constant switch-on overshoot of around 800 $mu text{V}$ . The complete circuit, including the integrated peak detector, is characterized by a ultralow static power consumption of $sim 32~mu text{W}$ and has a total area occupation of 0.01 mm2.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • An Energy-Efficient Reconfigurable AI-Based Object Detection and Tracking
           Processor Supporting Online Object Learning

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      Authors: Yuchuan Gong;Teng Zhang;Hongtao Guo;Qingsong Liu;Luying Que;Conghan Jia;Jiahui Huang;Ye Liu;Jiayan Gan;Yuxiang Xie;Yong Zhou;Lili Liu;Xiaoqiang Xiang;Liang Chang;Rui Yan;Jun Zhou;
      Pages: 78 - 81
      Abstract: This letter presents an energy-efficient reconfigurable AI-based object detection and tracking processor for smart drone/robot applications. Several techniques have been proposed to achieve high energy efficiency while supporting flexible object detection and tracking tasks with online object learning, including a reconfigurable object detection and tracking architecture with reconfigurable neural network (NN) engine, an online object learning architecture with shared NN inference and learning engine and automatic label generation engine, and a layer- and stride-aware NN computing technique. Compared with several state-of-the-art designs, the proposed design achieves better energy efficiency (2.13 mJ/frame), while supporting flexible object detection and tracking tasks with online object learning.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Ultralow Power Feature Extractor Using Switched-Capacitor-Based Bandpass
           Filter, Max Operator, and Neural Network Processor for Keyword Spotting

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      Authors: Hiroshi Fuketa;
      Pages: 82 - 85
      Abstract: This letter presents an ultralow power keyword spotting (KWS) system using a feature extractor comprising a bandpass filter, a max operator, and a time-delay neural network (TDNN) processor based on a switched capacitor technique. In the proposed KWS system, TDNN is used as a classifier. The first layer of the classifier requires an accurate calculation, whereas the rest of the layers can be binarized. Thus, in this study, feature extraction and the first layer of TDNN are performed in the analog domain, while the remainder is processed in the digital domain. The proposed architecture can remove high-precision ADC, which achieves ultralow power KWS. The proposed feature extractor is fabricated in the 65-nm CMOS process. The measurement results show that the proposed KWS system consumes 270 nW to detect two keywords.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Adaptive Clocking Using Supply Tracking Clock Modulator With
           Background-Calibrated Supply Sensitivity

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      Authors: Dongin Kim;SeongHwan Cho;
      Pages: 86 - 89
      Abstract: Adaptive clocking (AC) has shown promising results for digital systems when there is a supply droop. However, coping with clock buffer delay and coarsely quantized clock frequency still remains a challenge. To solve these issues, we propose a supply tracking clock modulator placed after the clock buffer, which continuously changes the clock frequency to the supply. A prototype fabricated in 28-nm CMOS allows 36% higher system clock frequency and 25% higher power efficiency in a 15% supply droop, than a normal system without AC.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Design of a Compact Dual-Band Absorptive Single-Pole Double-Throw Switch

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      Authors: Yo-Shen Lin;Li-Wen Deng;
      Pages: 90 - 93
      Abstract: In this letter, a compact dual-band absorptive single-pole double-throw (SPDT) switch design is proposed. It utilizes the bridged-T coil as a miniaturized dual-band $lambda /4$ transformer such that the concurrent dual-band operation in the on-state and the desired absorptive property in the off-state can be both achieved. The proposed design concept is validated through a 2.45/5.8-GHz dual-band absorptive SPDT switch design implemented in a commercial GaAs pHEMT process. The measured on-state insertion loss is 1.54/1.97 dB and the off-state isolation is 35/29 dB at 2.45/5.8 GHz, while the measured return losses at all ports are better than 20 dB at 2.45/5.8 GHz. In addition, a compact chip size of 2.0 mm $times $ 1.5 mm is achieved.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked
           Loop for ±10%-SSC Clock-Embedded Display Interface

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      Authors: Ching-Yuan Yang;Yen-Kuei Lu;Miao-Shan Li;Tai-Yuan Chen;Chin-Lung Lin;
      Pages: 94 - 97
      Abstract: A clock and data recovery (CDR) circuit based on a multiphase multiplexed recirculating delay-locked loop (MRDLL) is presented for spread-spectrum-modulation clock-embedded display interface. In the training stage, the MRDLL CDR is acting as a phase-locked loop (PLL) to generate sampling clocks. After the PLL is locked, the MRDLL CDR operates as a recirculating DLL to recover the incoming data. Implemented in the 90-nm CMOS process, the chip active area of the proposed MRDLL CDR is 0.118 mm2. As a 2.7-Gb/s spread-spectrum signal of 200-kHz modulation frequency and ±10% modulation depth with a triangular-shape frequency modulation is applied, the measured root-mean-square jitter of recovered data and clock is 9.27 and 4.03 ps, respectively. The power consumption is 5.23 mW.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 58.6/91.3 pJ/b Dual-Mode Belief-Propagation Decoder for LDPC and Polar
           Codes in the 5G Communications Standard

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      Authors: Bei-Sheng Su;Chia-Heng Lee;Tzi-Dar Chiueh;
      Pages: 98 - 101
      Abstract: This letter presents the first belief propagation (BP) decoder IC implementation for the two forward error correction (FEC) codes in the 5G communication standard. The LDPC mode supports 5G BG2 with 128 lifting size, while the polar mode supports code length $N = 1024$ . The 40-nm CMOS chip features BP module sharing, memory reuse, check node unit design, forwarding and layer pipelining, and dataflow rearrangement. Compared to two single-mode decoders, this dual-mode decoder saved 37% in the overall die area, 32% in the computation circuit area, and 41% in the memory area. The chip delivers throughputs of 2.38 and 1.85 Gb/s from 0.9-V Vdd with energy efficiencies of 58.6 and 91.3 pJ/b in the LDPC mode and the polar mode, respectively.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • IEEE SIM 2022

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      Pages: 100 - 100
      Abstract: Presents information on the IEEE SIM 2022 Conference.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 1.55-mW 2-GHz ERBW 7-b 800-MS/s Pipelined SAR ADC in 28-nm CMOS Using a
           7T Dynamic Residue Amplifier

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      Authors: Hyeonsik Kim;Seonkyung Kim;Jintae Kim;
      Pages: 102 - 105
      Abstract: This letter presents a 3-stage pipelined successive-approximation-resister (SAR) analog-to-digital converter (ADC) using a seven transistor-dynamic residue amplifier (7T-DA) for kickback noise cancelation. Thanks to the pipeline structure, the input capacitance is only 16 fF, achieving an effective resolution bandwidth (ERBW) of 2 GHz. The gain sensitivity to the temperature of the dynamic amplifier is reduced by an on-chip low-dropout voltage regulator (LDO) and a pulse generator. Fabricated in the 28-nm CMOS process, the prototype ADC running at 800 MS/s achieves a peak SNDR of 42.7 dB and SFDR of 52.0 dB at Nyquist input. It also achieves SNDR of 38.9 dB and SFDR of 49.9 dB at a 2-GHz input. The total power consumption of ADC is 1.55 mW, which corresponds to the Waldon figure of merit of 17.4 fJ/conv step and Schreier FoM of 156.8 dB, respectively.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Ultrahigh PSR Output-Capacitor-Free Adaptively Biased 2-Power-Transistor
           LDO With 200-mV Dropout

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      Authors: Xu Han;Wing-Hung Ki;Lianbo Wu;Yuan Gao;
      Pages: 106 - 109
      Abstract: This letter presents an output-capacitor-free cascaded 2-power-transistor low-dropout (2-PT LDO) regulator with ultrahigh power supply rejection (PSR) and fast transient response for low-power biomedical system on chips. The proposed 2-PT LDO consists of two stages in series, and the total dropout voltage is 200 mV. In order to boost the total PSR in a wide frequency range, different PSR enhancement strategies are adopted in each stage and a reversed-phase supply-ripple-cancelation technique is provided by a proposed reference buffer to further improve the PSR performance. Furthermore, adaptive biasing with robust frequency compensation is utilized to maintain system stability with fast transient response. Designed and fabricated in a 0.18- $mu text{m}$ CMOS process, the active area is only 0.0237 mm2. With the input voltage of 1.1–1.2 V, the 2-PT LDO supplies 0.9–1 V with a total quiescent current of $24.2~mu text{A}$ at no-load current. Experimental results show that PSR is better than −95dB up to 100 kHz.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 1596-GB/s 48-Gb Stacked Embedded DRAM 384-Core SoC With Hybrid Bonding
           Integration

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      Authors: Xiping Jiang;Fengguo Zuo;Song Wang;Xiaofeng Zhou;Yubing Wang;Qi Liu;Qiwei Ren;Ming Liu;
      Pages: 110 - 113
      Abstract: A 384-Keccak cryptographic cores system on chip (SoC) (die size > 800 mm2 and reticle size > 25.5 mm $times $ 32.0 mm) with 48-Gb stacked embedded DRAM (SeDRAM) is presented using 110-K/mm2 integration density and 0.1-fF capacitive load hybrid bonding integration. The SeDRAM’s advantages of low power and low latency are fully utilized by 49152 wide-IO and network-on-chip design in logic. Thermal stress and reliability are resolved to get a high package yield. The proposed SoC consumes 1596-GB/s bandwidth with 55-W power consumption only and achieves a great system performance improvement.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave
           Systems in Low-Cost Highly Integrated CMOS Technologies

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      Authors: Mohamad El-Chaar;Florence Podevin;Sylvain Bourdel;Antonio A. L. de Souza;Jean-Daniel Arnould;
      Pages: 114 - 117
      Abstract: This letter presents a stacked parallel plate (SPP) shunt capacitor (SC) that benefits from metal stack increment with process nodes advancement. It demonstrated high quality ( $Q$ ) factor and high self-resonance frequency (SRF), promoting the design of analog integrated circuits (ICs) in low-cost highly integrated CMOS technologies at the millimeter-wave (mm-wave) frequency range. As a proof-of-concept, an analytical-equation-based design method is also proposed and three ac-grounded capacitors: 300; 600; and 900-fF, are implemented in STMicroelectronics (STM) 55-nm process. Characterization is performed up to 100 GHz. An effective capacitance density of 0.8 ${mathbf {fF}}/mu mathbf {m}^{mathbf {2}}$ is obtained. Measurements show $Q$ -values reaching up to 14.7 at 100 GHz and equivalent input series resistances with flat wideband behavior reaching at most an average of 0.55 $Omega $ . SRFs of 140 GHz for the 900-fF SPP-SC up to 368 GHz for the 300-fF SPP-SC are also determined from measurements: the highest SRFs for such large capacitances to the authors’ knowledge.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A High-Voltage Fast-Speed Pulse Generator With Current-Mode Dead-Time
           Control Comparator for Shoot-Through Current Suppression

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      Authors: Yong-Joon Jeon;Ravinder Pal Singh;M. Kumarasamy Raja;
      Pages: 118 - 121
      Abstract: This letter presents a high-voltage fast-speed pulse generator with the suggested current-mode dead-time control (DTC) comparator. Measurements show that the propagation delay is in the range from 8.09 to 14.63 ns between the input pulse VIN and the output pulse VOUT and the rising and falling times of output pulses are 5.64 and 2.86 ns, respectively, for 20-V output pulses with the capacitive load of 22 pF. The integrated wide-band I–V converter for easy monitoring of shoot-through currents reveals that shoot-through currents during high-to-low output transition can be effectively suppressed with the DTC comparator. The total power consumption of the suggested pulse generator is reduced to 154.0 mW with the DTC comparator enabled in comparison with the power consumption of 264.5 mW when the DTC comparator is disabled at the operation frequency of 7 MHz with the output load of 22 pF and the supply voltage of 20 V.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Hybrid Continuous-Time Incremental and SAR Two-Step ADC With 90.5-dB DR
           Over 1-MHz BW

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      Authors: Yanchao Wang;Siladitya Dey;Tao He;Lukang Shi;Jiawei Zheng;Manjunath Kareppagoudr;Yi Zhang;Kazuki Sobue;Koichi Hamashita;Koji Tomioka;Gabor Temes;
      Pages: 122 - 125
      Abstract: This letter presents a hybrid continuous-time (CT) incremental and SAR two step ADC to provide high resolution with low oversampling ratio (OSR) and Nyquist conversion rate. The first CT incremental ADC (IADC) stage achieves large bandwidth, low thermal noise, and power consumption. The residual error of the CT IADC is extracted at the last integrator output and transferred to the 2nd SAR for further conversion. In this architecture, only the mismatch between the cascade of analog integrators (CoIs) and digital decimation filter transfer functions causes 1st stage quantization noise leakage, which is much smaller than that in the multistage noise-shaping (MASH) architecture. The ADC is fabricated in the AKM 180-nm CMOS process with 1.8-V supply voltage. It achieves a DR of 90.5 dB, SNR/SFDR/SNDR of 82.5/85/80.5 dB, and Schreier figure of merit (FoMs) of 165.5 dB over 1-MHz bandwidth (BW).
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Digital PLL With Multitap LMS-Based Bandwidth Control

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      Authors: Mario Mercandelli;Luca Bertulessi;Carlo Samori;Salvatore Levantino;
      Pages: 126 - 129
      Abstract: Automatic bandwidth control based on least mean-square adaptive filters has been demonstrated to desensitize the loop gain of a phase-locked loop (PLL) from process spreads, environmental variations, and channel frequency. This work extends this concept to low-jitter designs that adopt aggressive out-of-band filtering, by introducing multitap adaptive filtering. The method requires no injection of a training sequence, potentially degrading phase noise, and it is particularly suitable for bang-bang PLLs whose loop bandwidth depends on input noise. A 3.7-to-4.1-GHz PLL prototype embedding a 16-tap adaptive filter for loop-gain estimation demonstrates 150-kHz loop bandwidth over input noise and voltage supply variations, at 183-fs RMS-integrated jitter and 5.3-mW power consumption.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 1-Bit-DSM-Based Digital Polar Power Amplifier Supporting 1024-QAM

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      Authors: Yuncheng Zhang;Bangan Liu;Junjun Qiu;Atsushi Shirane;Kenichi Okada;
      Pages: 130 - 133
      Abstract: This letter proposes a Sub-GHz digital polar power amplifier circuit, which is intrinsically linear and power efficient. The architecture is based on a 1-bit delta–sigma modulator (DSM) to achieve amplitude modulation without a lossy capacitor array, which improves efficiency. A deskewing circuit eliminates skew-induced nonlinearity and improves the EVM without predistortion. The proposed 1-bit-DSM-based PA, integrated in a 65-nm CMOS process, achieves −36.5-dB RMS EVM and 24.1% PAE for a 10 MSymbol/s 1024-QAM modulated signal at 960-MHz carrier, without predistortion.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 10-Bit 1280 × 720 Micro-LED Display Driver With 2-Transistor Pixel
           Circuits and Current-Mode Pulse Width Modulation

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      Authors: Pei-Yi Lai Lee;Sheng Hui Li;Tzu Yi Hung;Ya-Wen Yang;Sih-Han Li;Jian-Jhih Sun;Chih-Wei David Lin;Chih-Wen Lu;Yen-Hsiang Fang;Wei-Hung Kuo;Li-Chun Huang;Guo-Dung John Su;Poki Chen;
      Pages: 134 - 137
      Abstract: This study proposes a 1280 $times $ 720 micro-LED display driver with 10-bit current-mode pulse width modulation. A two-transistor pixel circuit and a precharge scheme are proposed. A 1280 $times $ 720 micro-LED display driver with 3969 pixels per inch was fabricated using standard 0.18- $mu text{m}$ CMOS technology. The measured maximal DNL and INL values were 0.33 and 1 LSB, respectively. A 1280 $times $ 720 common-cathode micro-LED array was bonded on the display driver chip; hence, the feasibility of the display driver was verified. The display was successfully lit up at a 90-Hz frame rate and a power consumption of 76.3 mW.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Cross-Correlation-Based Time-of-Flight Design for Pulsed Chaos Lidar
           Systems

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      Authors: Yi-Cheng Lin;Ping-Hsuan Hsieh;Jian-Lun Hong;Yu-Hsiang Lai;Jun-Da Chen;Fan-Yi Lin;Yuan-Hao Huang;Po-Chiun Huang;
      Pages: 138 - 141
      Abstract: This work presents an integrated circuit design of a time-of-flight module for pulsed chaos lidar systems. With a mixed-signal architecture and 1-bit digitization, the proposed design evaluates the delay in time and the corresponding distance by calculating the cross-correlation function between the two signals using a 16-unit multiplier-and-integrator array. Tunable filtering further allows resolution and dynamic range scaling. The prototype IC with 90-nm CMOS was evaluated using an in-house pulsed chaos lidar system. At 5 GS/s, experimental results demonstrate a maximum ranging error of 3.38 cm with 1- $sigma $ of 1.97 cm over a distance of 7.4 m. With the signal pulse width of 100 ns and a repetition period of 50 $mu text{s}$ , this work consumes 113 mW under a 1-V supply.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Systolic-RAM: Scalable Direct Convolution Using In-Memory Data Movement

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      Authors: Jacob N. Rohan;Jaydeep P. Kulkarni;
      Pages: 142 - 145
      Abstract: A 12.8-kbit static random access memory (SRAM) is demonstrated in 40-nm CMOS for signed 8-bit convolution in-memory. While conventional compute-in-memory (CIM) approaches rely on the indirect convolution algorithm, the proposed “Systolic-RAM” performs a form of direct convolution which eliminates the need for data duplication and near-memory registers. To achieve this, an in-memory data pipeline is employed to move data within the array and mimic the physical movement of the convolution kernel. In between data movement cycles, back-end-of-line (BEOL) structures perform charge-domain vector-matrix multiplication (VMM). The indirect convolution algorithm is illustrated, and the supporting circuits are presented in detail. Quantized neural network training methods are also employed to achieve test accuracy close to that of a floating-point network. The demonstrated array is configured for a $5 times 5 $ kernel, achieves 175(113) peak (continuous) multiply accumulate (MAC) operations per clock cycle and consumes 3.0 mW at 100 MHz.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A CMOS 24–30-GHz Low-Phase-Variation Variable Gain Amplifier Design
           for 5G New Radio

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      Authors: Junjun Qiu;Jian Pang;Bangan Liu;Xueting Luo;Yun Wang;Yuncheng Zhang;Atsushi Shirane;Kenichi Okada;
      Pages: 146 - 149
      Abstract: This letter presents a 24–30-GHz variable gain amplifier (VGA) achieving low-phase variation in a standard RF 65-nm CMOS process. The proposed VGA employs two stages. Phase compensation during the gain variation is realized with the dynamic complementary phase variation at the first stage. The second stage is utilized to increase the gain and keep linearity. Measurement results prove that the proposed VGA achieves a continuous gain tuning range of 8.3 dB. Under this condition, low-phase variation is realized with the root-mean-square (RMS) phase error less than 3° from 24 to 30 GHz. Moreover, the RMS phase error is less than 2° at the desired 5G frequency band from 27.5 to 29.5 GHz. The peak gain is measured with 18.7 dB at 29 GHz. With the max gain setting, the measured OP1dB and OIP3 are 5.1 and 9.3 dBm, respectively, and the measured noise figure is from 4.6 to 6.8 dB at the frequency range from 24 to 30 GHz.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 23.8–30.4-GHz Vector-Modulated Phase Shifter With Two-Stage
           Current-Reused Variable-Gain Amplifiers Achieving 0.23° Minimum RMS Phase
           Error

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      Authors: Linghan Zhang;Yiyu Shen;Leo de Vreede;Masoud Babaie;
      Pages: 150 - 153
      Abstract: This letter presents a millimeter-wave (mm-wave) vector-modulated phase shifter (VMPS) for phased-array applications. To improve the phase-shift accuracy without drastically increasing design complexity, the proposed VMPS structure employs variable-gain amplifiers (VGAs) that offer $2times $ better resolution at their low-gain states compared to their high-gain states. A two-stage current-reused structure is also proposed to implement the desired VGAs with minimal layout complexity, negligible gain penalty, and no extra power. Moreover, the proposed VMPS can maintain its phase-shift accuracy even at lower voltage gains. Fabricated in 40-nm CMOS, the prototype core consumes 11 mW from a 1.1-V supply and occupies a core area of 0.19 mm2. At 28 GHz, with a phase resolution of 0.61°, the measured RMS phase error is 0.23° at the maximum gain and remains $ < 0.5^circ $ at 9-dB gain back-off. With a fixed set of VGA’s codewords, the RMS phase error and gain variation error are, respectively, lower than 1° and 0.24-dB over a bandwidth of 23.8–30.4 GHz.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Bimodal Low-Power Transceiver Featuring a Ring Oscillator-Based
           Transmitter and Magnetic Field-Based Receiver for Insertable Smart Pills

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      Authors: Angsagan Abdigazy;Manuel Monge;
      Pages: 154 - 157
      Abstract: This letter presents a novel bimodal, low-power, mm-scale transceiver for insertable smart pills. The proposed power amplifier (PA)-less, 915-MHz uplink transmitter (TX) incorporates an $1.2times 1.2$ mm2 on-chip, nonresonated antenna as part of a current-starved ring oscillator (RO) and directly transmits data by turning the RO on/off. This RO-based uplink TX is implemented in 180-nm CMOS along with a power management unit, which generates all internal reference voltages and supplies from a single battery. The uplink TX achieves a data rate of 33 Mb/s and consumes $210~mu text{W}$ , resulting in an energy efficiency of 6.4 pJ/bit. The orientation-insensitive magnetic field-based downlink receiver (RX) is implemented with an external 3-D magnetic sensor, achieves 0.02 kb/s of data rate limited by our measurement setup, and consumes 270 $mu text{W}$ . Wireless measurements in saline over 150 cm and prototype of the $3.2times 13.6times 2.3$ mm3 insertable pill are presented.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • An Indirect Time-of-Flight SPAD Pixel With Dynamic Comparator Reuse for a
           Single-Slope ADC

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      Authors: Kasper Buckbee;Neale A. W. Dutton;Robert K. Henderson;
      Pages: 158 - 161
      Abstract: This letter presents a 2-bin single-photon avalanche diode (SPAD)-based indirect time-of-flight (ITOF) pixel circuit with low-power low-voltage differential clock distribution and a partially in-pixel single-slope analog-to-digital converter (ADC). An in-pixel dynamic comparator performs dual functions as a SPAD event-driven low-swing clock sampler and a comparator for self-referenced ADC conversion with digital delta reset sampling (DRS). The pixel achieves a full well capacity of 128–512 photons (6.83–8.82 effective bit depth), a low dynamic power consumption of 13.9–24.5-nW/MHz SPAD rate at a pitch of 7.2 $mu text{m}$ in STMicroelectronics’ 40-nm CMOS and is 3-D stacking ready.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Reconfigurable Neural Stimulation IC With a High-Resolution Strength
           Control and In-Situ Neural Recording Function for Cochlear Implant Systems
           

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      Authors: Woojin Ahn;Doohee Kim;Jonghyeok Park;Joeng Hoan Park;Taeju Lee;Kyeongwon Jeong;Kyou Sik Min;Hoseung Lee;Minkyu Je;
      Pages: 162 - 165
      Abstract: This letter presents a neural stimulation IC for the 32-channel cochlear implant system. A zoom current DAC (I-DAC), whose full range is reconfigured to fit the interval between the comfort (C) and threshold (T) levels, is introduced for high-resolution stimulation strength control to provide high-fidelity sound perception with minimal hardware overhead. The IC also includes an in-situ neural recording function. The effectiveness of auditory nerve stimulation is validated by monitoring electrically evoked compound action potential (ECAP) in-vivo using a rat model. It is found that the action potential amplitude increases as the stimulation current level becomes larger.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Compact Integrated High-Voltage Pulser Insensitive to Supply Transients
           for 3-D Miniature Ultrasound Probes

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      Authors: Yannick M. Hopf;Boudewine Ossenkoppele;Mehdi Soozande;Emile Noothout;Zu-Yao Chang;Hendrik J. Vos;Johan G. Bosch;Martin D. Verweij;Nico de Jong;Michiel A. P. Pertijs;
      Pages: 166 - 169
      Abstract: In this letter, a compact high-voltage (HV) transmit circuit for dense 2-D transducer arrays used in 3-D ultrasonic imaging systems is presented. Stringent area requirements are addressed by a unipolar pulser with embedded transmit/receive switch. Combined with a capacitive HV level shifter, it forms the ultrasonic HV transmit circuit with the lowest reported HV transistor count and area without any static power consumption. The balanced latched-based level shifter implementation makes the design insensitive to transients on the HV supply caused by pulsing, facilitating application in probes with limited local supply decoupling, such as imaging catheters. Favorable scaling through resource sharing benefits massively arrayed architectures while preserving full individual functionality. A prototype of 8 $times $ 9 elements was fabricated in the TSMC $0.18~boldsymbol {mu }text{m}$ HV BCD technology and a $160,,boldsymbol {mu }text{m},,times ,,160,,boldsymbol {mu }text{m}$ PZT transducer matrix is manufactured on the chip. The system is designed to drive 65-V peak-to-peak pulses on 2-pF transducer capacitance and hardware sharing of six elements allows for an area of only 0.008 mm2 per element. Electrical characterization as well as acoustic results obtained with the 6-MHz central frequency transducer are demonstrated.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • 64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh
           Technique

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      Authors: Odem Harel;Emmanuel Nieto Casarrubias;Manuel Eggimann;Frank Gürkaynak;Luca Benini;Adam Teman;Robert Giterman;Andreas Burg;
      Pages: 170 - 173
      Abstract: Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64-kB GC-eDRAM macro was fabricated in a 65-nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 $mathrm { mu text {s} }$ retention time.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • An Open-Source and Autonomous Temperature Sensor Generator Verified With
           64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration
           

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      Authors: Qirui Zhang;Wenbo Duan;Tim Edwards;Tim Ansell;David Blaauw;Dennis Sylvester;Mehdi Saligane;
      Pages: 174 - 177
      Abstract: This letter presents an open-source framework for autonomous generation of tapeout-ready temperature sensors. This framework uses a leakage-based digital temperature sensor design as the template. A cell-based design methodology is employed to allow full synthesizability and compatibility with computer-aided designs (CADs) flow and advanced technology nodes. Furthermore, the generator automates the design flow end-to-end in Python and supports designing completely with open-source CAD tools. Verified with 64 instances in SkyWater 130 nm, the generator also enables low-effort silicon-proven design space exploration that unveils the characteristics of leakage-based digital temperature sensors, with the most efficient one achieving 9.7 pJ $cdot text{K}^{2}$ FoM, −0.67/0.74 °C 3 ${sigma }$ inaccuracy, 130-nW power, and 24-mK resolution. To the best of our knowledge, this work is the world’s first open-source silicon-proven generator for temperature sensors.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 120-Gb/s 100–145-GHz 16-QAM Dual-Band Dielectric Waveguide
           Interconnect With Package Integrated Diplexers in Intel 16

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      Authors: Georgios C. Dogiamis;Thomas W. Brown;Neelam Prabhu Gaunkar;Ye Seul Nam;Triveni S. Rane;Surej Ravikumar;Vijaya B. Neeli;Jessica C. Chou;Said Rami;Johanna Swan;
      Pages: 178 - 181
      Abstract: This letter presents a dual-band superheterodyne transceiver system in Intel 16 operating at 109 and 135 GHz center frequencies with a measured rejection >60 dB within the 11 GHz guard band. The transceiver is flip-chip assembled on a multilayer organic package, which integrates hairpin resonator diplexers and electromagnetic waveguide launchers. A connector assembled on the organic package feeds a 3–4-m long PTFE dielectric waveguide ensuring a stable mechanical connection. This letter demonstrates up to 120 Gb/s data rates with measured error vector magnitudes (EVMs) between −19.2 dB and −16.2 dB at 3–4-m distances with combined power consumption of 1116 mW. This is the first work in the literature reporting beyond 60 Gb/s over dielectric waveguide channels at link distances greater than 1 m. Combining frequency division multiplexing with a low tap count FFE equalizer and sharp on-die analog and RF filtering with a low loss on package diplexer enabled the >100 Gb/s at multimeter distances.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • 16-Core BiCMOS VCOs With Phase Noise Down to –130 dBc/Hz at 1-MHz
           Offset From 20 GHz

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      Authors: Domenico Riccardi;Alessandro Franceschin;Andrea Mazzanti;
      Pages: 182 - 185
      Abstract: This letter presents two 16-core 20-GHz VCOs in 55-nm BiCMOS technology proving an ultralow phase noise. Through a design approach careful to the issues of large oscillators arrays, the first voltage-controlled oscillator (VCO) achieves a phase noise as low as −130 dBc/Hz at 1-MHz offset, with 17.4% tuning range. The second VCO, exploiting diode-based coupling switches can be reconfigured 2-by-2 from 2- to 16-core, trading power and phase noise efficiently. An overall 12.5% tuning range is achieved, while the phase noise at 1 MHz scales from −120 to −128.8 dBc/Hz.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 1.68–23.2-Gb/s Reference-Less Half-Rate Receiver With an ISI-Tolerant
           Unlimited Range Frequency Detector

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      Authors: Yu-Ping Huang;Yi-Wei Chang;Wei-Zen Chen;
      Pages: 186 - 189
      Abstract: This letter presents a reference-less half-rate receiver with an unlimited range frequency detector (URFD) for $13.8times $ continuous rate operation. To tolerate channel loss induced intersymbol interference (ISI), the receiver is integrated with a continuous-time linear equalizer (CTLE) and a 2-tap decision feedback equalizer (DFE) on the same chip. Incorporating with the novel pulse width-based URFD, the date rate of the receiver is limited by the frequency tuning range of the voltage-controlled oscillator (VCO). The energy efficiencies of the whole receiver and clock and data recovery (CDR) are about 2.39 and 0.97 pJ/bit, respectively. Implemented in a TSMC 28-nm CMOS process, the active area is 0.056 mm2.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Highly Selective Bandpass Switch Block With Applications of MMIC SPDT
           Switch and Switched Filter Bank

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      Authors: Di Lu;Junbo Liu;Ming Yu;
      Pages: 190 - 193
      Abstract: A new bandpass single-pole–single-throw (SPST) switch (BPSW) is proposed in this letter. The proposed BPSW configuration can be directly employed as a building block to construct the single-pole–N-throw (SPNT) switch or the highly selective switched filter bank with no need for the extra control circuit, thus effectively reducing the circuit size and lowering the loss. The operation mechanism of the BPSW is analyzed, and the filter-synthesis-based design method is given. For demonstration, 3–6 and 4–8 GHz BPSW blocks are built using the commercial GaAs pHEMT process to construct the single-pole–double-throw (SPDT) switch as well as the two-way integrated switched filter bank. The filter bank is implemented in 0.25- ${mu }text{m}$ GaAs pHEMT process. Two passbands are measured at 2.7–5.79 and 3.72–7.35 GHz with a minimum insertion loss of 2.7 dB, while the all-OFF state can be set with over 35-dB suppression. The measurement results are in good agreement with the simulation that verifies the concept.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 12-b 1-GS/s 61-dB SNDR Pipelined-SAR ADC With Inverter-Based Residual
           Amplifier and Tunable Harmonic-Injecting Cross-Coupled-Pair for Distortion
           Cancelation Achieving 6.3 fJ/conv-step

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      Authors: Liang Fang;Tao Fu;Xianshan Wen;Ping Gui;
      Pages: 194 - 197
      Abstract: A 1-GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog-to-digital converter (ADC) is presented. It consists of three stages (4b-4b-6b) with two one-bit interstage redundancies implemented. A novel harmonic-injecting cross-coupled pair (HXCP) is proposed in an inverter-based residual amplifier (RA) as a critical part of the presented ADC. By implementing the HXCP, the linearity of the RA is effectively improved and meanwhile the gain of the RA is boosted to about 8. The HXCP is designed to be tunable to enhance its robustness against PVT variation. The prototype single-channel ADC was fabricated in 28-nm CMOS process and achieves $mathbf {mathrm {> }}60$ -dB SNDR and $mathbf {mathrm {> }}70$ -dB SFDR up to 320 MHz, corresponding to a 6.3 fJ/conv-step FoMw and 170.5-dB FoMs.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 28-nm 198.9-TOPS/W Fault-Tolerant Stochastic Computing Neural Network
           Processor

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      Authors: Yixuan Hu;Yawen Zhang;Runsheng Wang;Zuodong Zhang;Jiahao Song;Xiyuan Tang;Weikang Qian;Yanzhi Wang;Yuan Wang;Ru Huang;
      Pages: 198 - 201
      Abstract: Previous energy-efficient neural network (NN) processors suffer from bit errors when operating at lower voltages for further power reduction. Stochastic computing (SC) shows great potential due to its low hardware cost and high fault tolerance. Conventionally, limited by the long latency of bitstreams, SC-based NN accelerators adopt a hybrid stochastic-binary architecture, sacrificing fault tolerance and hardware efficiency. This letter proposes a fully SC architecture that maximizes fault tolerance while offering excellent energy and area efficiency. The fabricated 28-nm prototype is the first silicon-proven SC-based NN processor, realizing an energy efficiency of 198.9 TOPS/W and an area efficiency of 2630 GOPS/mm2 with an accuracy loss reduction of 70%.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • An Improved Linearity Ring Oscillator-Based Current-to-Digital Converter

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      Authors: Anthony Wall;Paul Walsh;Khosrov Sadeghipour;Ivan O’Connell;Daniel O’Hare;
      Pages: 202 - 205
      Abstract: Many biosensors produce single-ended current outputs. Lab-on-chip applications demand parallel readout channels requiring low area current-to-digital converters. High HD2 has limited the current controlled ring oscillator’s (CCROs) adoption as a low area, single-ended converter. This work improves CCRO open loop linearity by 10 dB. A wide-bandwidth current buffer is also designed. A low area (0.0025 mm 2), low power ( $357 ~mu mathrm {W}$ ), single-ended, and 1 MHz bandwidth converter suitable for array readout is presented with the measured performance.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 4.4–75-TOPS/W 14-nm Programmable, Performance- and Precision-Tunable
           All-Digital Stochastic Computing Neural Network Inference Accelerator

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      Authors: Wojciech Romaszkan;Tianmu Li;Rahul Garg;Jiyue Yang;Sudhakar Pamarti;Puneet Gupta;
      Pages: 206 - 209
      Abstract: We present the first programmable and precision-tunable stochastic computing (SC) neural network (NN) inference accelerator. The use of SC makes it possible to achieve multiply–accumulate (MAC) density of 38.4k MAC/mm2, enabling a level of spatial data reuse unachievable to conventional, fixed-point architectures. This extensive reuse amortizes the cost of SC conversion and reduces the number of memory accesses, which can otherwise consume significant energy and latency. Our accelerator is a stand-alone architecture, with a custom instruction set architecture (ISA), and support for end-to-end model inference with convolutional and fully connected layers of variable input and filter sizes. Further, it demonstrates extensive accuracy–latency tradeoffs by varying the stream length. The 14-nm demonstration chip achieves 2.4-TOPS and 75-TOPS/W peak throughput and energy efficiency, outperforming comparable fixed-point accelerators.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Single-Transistor Amplifier With Back-Gate Feedback in 22-nm FD-SOI

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      Authors: Stephen Weinreich;Boris Murmann;
      Pages: 210 - 213
      Abstract: Fully-depleted silicon-on-insulator (FD-SOI) technology provides an additional degree of circuit design freedom due to its fourth terminal, the back-gate (BG). In this letter, we present a single-transistor common-source amplifier exploiting the FD-SOI BG as a feedback injection point. This negative BG feedback improves linearity and reduces device-to-device gain variation without increasing noise or power and with no added components. A prototype amplifier, implemented in 22-nm FD-SOI, operates from weak to moderate inversion and achieves 5–10 $times $ lower gain variation and 6–20-dB higher VIP3 compared to a reference two-transistor amplifier with a diode-connected load.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A Compact 140-GHz CMOS Power Amplifier With 10.5-dBm Output Power and
           27.6-dB Power Gain Supporting up to 128-QAM Modulation

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      Authors: Liang Chen;Lei Zhang;Weiping Wu;Yan Wang;
      Pages: 214 - 217
      Abstract: A compact 140-GHz power amplifier (PA) with an employed multilayer stacked transformer (MLST) matching network is implemented in a 65-nm CMOS process. The employed MLST matching network adopts two metal layers as the primary coil and one single layer as the secondary coil to increase the coupling factor and decrease the insertion loss (IL) of the matching network at the D-band frequency range. Besides, a gain-boosting unit (GBU) is further introduced in the first stage of the PA to enhance the power gain. The proposed 140-GHz PA achieves a measured power added efficiency of 6.9%, a ${P_{textrm {sat}}}$ of 10.5 dBm, and an ${OP_{textrm {1dB}}}$ of 7.03 dBm with a maximum power gain of 27.6 dB when the GBU turns off. By turning on the GBU, the power gain managed to increase from 27.6 to 31 dB with stability. Furthermore, modulation measurement shows that the proposed D-band PA supports 24-Gb/s 64-QAM and 11.2-Gb/s 128-QAM modulated signals with error vector magnitudes (EVMs) of −23.1/−22.87 dB at the output power of 7 dBm, respectively. The core chip area and dc power consumption of the PA are only 0.0275 mm2 and 170 mW.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • A 100-Gb/s PAM-4 Voltage-Mode Transmitter With High-Resolution Unsegmented
           Three-Tap FFE in 40-nm CMOS

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      Authors: Yan-Ting Chen;Pen-Jui Peng;Hung-Wen Lin;
      Pages: 218 - 221
      Abstract: This letter presents a 100-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-mode transmitter (TX) with a three-tap feed-forward equalizer (FFE). A new configuration, including FFE and output impedance ( $Z_{mathrm{ out}}$ ) control loops, for implementing voltage-mode FFE is proposed to avoid the driver being segmented. The method can significantly decrease the layout complexity of a high-resolution voltage-mode FFE, improving the output bandwidth. The TX front end merges the 2:1 multiplexer into the driver and adopts a quarter-rate clocking scheme to save significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX achieves a maximum data rate of 100 Gb/s with 2.39-pJ/b energy efficiency under a chip-on-board assembly with 5-dB Nyquist loss.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • MIPSIMO: A Multi-Input Piezo-Adaptive Single-Inductor Multi-Output Energy
           Harvester Achieving Using a Shared Inductor With an Integrated Analog
           Computer Achieving 95% MPPT Efficiency

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      Authors: Salar Chamanian;Patrick P. Mercier;
      Pages: 222 - 225
      Abstract: This letter presents a multi-input piezo-adaptive single-inductor multioutput (MIPSIMO) architecture that harvests energy from up to three inputs while regulating up to three loads plus a battery all in a single power stage. The proposed power management unit performs load domain inductor switching to reduce switching losses by $3times $ and allows recycling of excess energy back to the battery for decoupled single-stage regulation, all while utilizing an adaptive ON-time PFM control method during battery utilization to free up inductor cycles as much as possible for harvesting. The proposed architecture implements a technique that performs multiphase piezoelectric harvesting (PEH) charge flipping (CF) using the single shared inductor from the power stage together with four flying capacitors that reduce the required inductor size by $8times $ while achieving 90% flipping efficiency. In addition, a fully integrated power-extraction analog computer is employed to enable real-time hill-climbing MPPT compatible with PEH sources. Fabricated in 180 nm, the analog computer achieves an MPPT efficiency of 95% and the converter supports the power range of 6 $mu text{W}$ –60 mW and achieves a peak efficiency of 87%.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • Picowatt-Power Analog Gain Stages in Super-Cutoff Region With
           Purely-Harvested Demonstration

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      Authors: Joydeep Basu;Karim Ali;Longyang Lin;Massimo Alioto;
      Pages: 226 - 229
      Abstract: In this work, gain stages with power down to the sub-pW/stage range are introduced to enable always-on mm-scale systems based on either pure harvesting across all practical environmental conditions, or micro-battery with near-shelf life lifetime (e.g., 20 years). The proposed circuit techniques suppress the need for supply voltage regulation, allowing direct harvesting (i.e., no intermediate dc–dc conversion). A CMOS 180-nm fully differential operational transconductance amplifier (OTA) is shown to consume 0.43–1.26 pW at 0.4–0.6 V as voltage harvested across all practical conditions from 2.16-mm2 solar cell down to 1 lux. The OTA shows 0.8-mV input offset and 18- $mu text{V}$ input-referred noise. As an example of its application, a pW-power human grip/touch detection system for always-on event monitoring is demonstrated at light-harvesting down to moonlight.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • An Unconditionally Stable Three-Stage OTA

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      Authors: H. Aminzadeh;A. Ballo;M. Valinezhad;A. D. Grasso;
      Pages: 230 - 233
      Abstract: A three-stage operational transconductance amplifier (OTA) stable for any load capacitor is introduced for the first time in literature. It contains a novel local ac feedback network in the intermediate stage in addition to the cascode-Miller compensation strategy. The final topology is Miller-compensated for the light and $C_{L}$ -compensated for the heavy capacitive loads, and its operation is improved by, including a feed-forward stage and a slew-rate enhancer. A prototype of the proposed amplifier was fabricated in a 65-nm standard CMOS process with 1.2-V supply voltage, occupying an active area of 0.0028 mm2 with 13.07- $mu text{A}$ quiescent current. A DC gain of about 100 dB was measured with a unity-gain frequency of 4000, 705, and 22 kHz for 0.03, 0.5, and 100-nF capacitive loads, respectively.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
  • SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit
           Computation

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      Authors: Edward Jongyoon Choi;Injun Choi;Chanhee Jeon;Gichan Yun;Donghyeon Yi;Sohmyung Ha;Ik-Joon Chang;Minkyu Je;
      Pages: 234 - 237
      Abstract: In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient “one-step” method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.
      PubDate: 2022
      Issue No: Vol. 5 (2022)
       
 
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