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  Subjects -> ELECTRONICS (Total: 207 journals)
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IEEE Open Journal of Circuits and Systems
Number of Followers: 0  

  This is an Open Access Journal Open Access journal
ISSN (Online) 2644-1225
Published by IEEE Homepage  [228 journals]
  • IEEE Circuits and Systems Society

    • Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Editorial: Where Are We Now and Where Do We Go From Here

    • Authors: Gabriele Manganaro;
      Pages: 1 - 3
      Abstract: Happy 2022 and welcome to the third volume of the IEEE Open Journal of Circuits and Systems (OJ-CAS).
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using
           Convolutional Non-Linear Neural Network

    • Authors: Atsutake Kosuge;Yao-Chung Hsu;Mototsugu Hamada;Tadahiro Kuroda;
      Pages: 4 - 14
      Abstract: A pipelined wired-logic deep neural network (DNN) processor implemented in a 16-nm field-programmable gate array (FPGA) is presented. The latency and power required for memory access are minimized by utilizing the wired-logic architecture, thus enabling low power and high throughput operation. One technical issue with the wired-logic architecture is that it requires a lot of hardware resources. To reduce them, two core technologies are developed: (1) a convolutional non-linear neural network (CNNN) and (2) a pipeline-type neuron cell. The CNNN optimizes both the network structure and the non-linear activation function of each neuron by using a newly developed back-propagation-based training method. While conventional reinforcement learning can train only a small size network thus limiting its application to handwritten number recognition, the proposed CNNN enables a larger network size making it applicable to object recognition. The pipeline-type neuron cell has a small look-up table (LUT) to process non-linear functions using only a small amount of hardware resources. These two technologies enable the implementation of the entire network on a single FPGA chip with the wired-logic architecture. Three types of CNNN trained on the CIFAR-10 dataset are implemented in 16-nm FPGAs. An energy efficiency of 0.09, 0.12, and $0.61~mu text{J}$ /frame is achieved with 70%, 75%, and 82% accuracy, respectively. Compared with a state-of-the-art accelerator using a binary neural network (BNN), the energy efficiency is improved by more than two orders of magnitude.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Stability Boundaries of Wide-Input-Range COT Buck Converters With Ripple

    • Authors: Federico Bizzarri;Paolo Nora;Angelo Brambilla;
      Pages: 15 - 24
      Abstract: In this paper, we focus on instability issues of a wide-input-range Constant ON-Time buck converter. A transconductance stage in the control path that implements ripple compensation characterizes the architecture of this switching circuit. On the whole, decision rules, that heavily influence stability, govern the dynamical evolution of the converter. We show the onset of sub-harmonic oscillations and pulse-bursting caused by the presence of hysteresis in the regulation comparator. Operational boundaries are provided both in analytical and numerical form. They easily support the designer in choosing the converter parameter values. Theoretical results are verified against SIMetrix/SIMPLIS and MPLAB® Mindi™ simulations for a case study involving a commercial adjustable-frequency, synchronous buck regulator featuring an adaptive ON-time control architecture. A good agreement is obtained, as shown.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method
           for FPGA Hardware

    • Authors: Josh Goldsmith;Louise H. Crockett;Robert W. Stewart;
      Pages: 25 - 37
      Abstract: We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 $mu text{s}$ , enabling radio applications in which latency is a principal constraint.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Optimization of Quantized Analog Signal Processing Using Genetic
           Algorithms and μ-Law

    • Authors: Qingnan Yu;Tony Chan Carusone;Antonio Liscidini;
      Pages: 38 - 49
      Abstract: Digital mismatch calibration for quantized analog (QA) signal processing is proposed for the first time. Since the proposed calibration mechanism does not require uniform QA slicer levels, non-uniform quantization can be applied to improve the system performance. We propose two methods utilizing the genetic algorithm and $mu $ -law to find non-uniform slicer levels offering superior performance compared to uniform levels. Simulations show that for a QA amplifier consisting of 32 slices, the signal-to-noise-and-distortion ratio (SNDR) under a multitone input can be doubled by adjusting only the quantization levels while maintaining the same structure and same power, compared to uniform quantization levels that provide 54 dB of SNDR.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using
           Fault-Localization and Partial Reconfiguration

    • Authors: Muhammad Ali Akbar;Bo Wang;Amine Bermak;
      Pages: 50 - 58
      Abstract: In this paper, a self-checking and -repairing carry-lookahead adder (CLA) is proposed with distributed fault detection ability. The presented design with self-checking and fault localization ability requires an area overhead of 69.6% as compared to the conventional CLA. It can handle multiple faults simultaneously without affecting the delay of conventional CLA, with the condition that each module has a single fault at a time. The repairing operation utilizes the hot-standby approach with partial reconfiguration in which the faulty module would be replaced by an accurately functioning module at run-time. The proposed self-repairing adder with high fault coverage requires 161.5% area overhead as compared to conventional CLA design which is 35.3% less as compared to the state-of-the-art partial self-repairing CLA. Moreover, the delay of the proposed 64-bit self-repairing CLA is 40.7% more efficient as compared to conventional ripple carry adder.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Applicability of Hyperdimensional Computing to Seizure Detection

    • Authors: Lulu Ge;Keshab K. Parhi;
      Pages: 59 - 71
      Abstract: Hyperdimensional (HD) computing is a form of brain-inspired computing which can be applied to numerous classification problems. In past research, it has been shown that seizures can be detected from electroencephalograms (EEG) with high accuracy using local binary pattern (LBP) encoding. This paper explores applicability of binary HD computing to seizure detection from intra-cranial EEG (iEEG) data from the Kaggle seizure detection contest based on using both LBP and power spectral density (PSD) features. In the PSD method, three novel approaches to HD classification are presented for both selected features and all features. These are referred as single classifier long hypervector, multiple classifiers, and single classifier short hypervector. To visualize the quality of classification of test data, a hypervector distance plot is introduced that plots the Hamming distance of the query hpervectors from one class hypervector vs. that from the other. Simulation results show that: 1). LBP method offers an average 80.9% test accuracy, 71.9% sensitivity, 81.4% specificity and 76.6% test AUC whereas the PSD method can achieve an average of 91.0% test accuracy, 81.8% sensitivity, 92.0% specificity and 86.9% test AUC. 2). The average seizure detection latency is 2.5s for LBP method and is 4.5s for the PSD methods. This average latency, less than 5s, is a relevant parameter for fast drug delivery, indicating that both LBP and PSD methods are able to detect the seizures in a timely manner. The performance using selected PSD features is better than that using all features. 3). It is shown that the dimensionality of the hypervector can be reduced to 1, 000 bits for LBP and PSD methods from 10, 0-0. Futhermore, for some approaches of selected features, the dimensionality of the hypervector can be reduced to 100 bits.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based
           Transimpedance Amplifier

    • Authors: Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami;
      Pages: 72 - 81
      Abstract: In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB $Omega $ , a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm2.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Analysis and Design Methodology of RF Energy Harvesting Rectifier Circuit
           for Ultra-Low Power Applications

    • Authors: Ziyue Xu;Adam Khalifa;Ankit Mittal;Mehdi Nasrollahpourmotlaghzanjani;Ralph Etienne-Cummings;Nian Xiang Sun;Sydney S. Cash;Aatmesh Shrivastava;
      Pages: 82 - 96
      Abstract: This paper reviews and analyses the design of popular radio frequency energy harvesting systems and proposes a method to qualitatively and quantitatively analyze their circuit architectures using new square-wave approximation method. This approach helps in simplifying design analysis. Using this analysis, we can establish no load output voltage characteristics, upper limit on rectifier efficiency, and maximum power characteristics of a rectifier. This paper will help guide the design of RF energy harvesting rectifier circuits for radio frequency identification (RFIDs), the Internet of Things (IoTs), wearable, and implantable medical device applications. Different application scenarios are explained in the context of design challenges, and corresponding design considerations are discussed in order to evaluate their performance. The pros and cons of different rectifier topologies are also investigated. In addition to presenting the popular rectifier topologies, new measurement results of these energy harvester topologies, fabricated in 65nm, 130nm and 180nm CMOS technologies are also presented.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Design and Implementation of an On-Demand Maximum-Likelihood Sequence
           Estimation (MLSE)

    • Authors: Mohammad Emami Meybodi;Hector Gomez;Yu-Chun Lu;Hossein Shakiba;Ali Sheikholeslami;
      Pages: 97 - 108
      Abstract: This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Stable Digital Impedance Circuit Design Method for Resistive Source

    • Authors: Christopher G. Daniel;Thomas P. Weldon;
      Pages: 109 - 114
      Abstract: The recent discovery that the input impedance of digital impedance circuits is dependent on the external source impedance requires the development of new design procedures to address the significant complexity of this discovery. These circuits are of particular utility for the implementation of difficult non-Foster impedances such as negative capacitance. Therefore, a new digital impedance circuit design procedure is presented where stable digital filter coefficients are computed to provide desired digital impedance values at two chosen frequencies, given that a stable solution exists. The new design procedure explicitly addresses the aforementioned dependence on the external source impedance for digital impedance circuits with resistive sources. Lastly, simulation results from a negative capacitance design example are compared to the new theory to confirm the efficacy of the new design procedure.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Low-Rank CNN Architecture for Real-Time Semantic Segmentation in Visual
           SLAM Applications

    • Authors: Laura Falaschetti;Lorenzo Manoni;Claudio Turchetti;
      Pages: 115 - 133
      Abstract: Real-time semantic segmentation on embedded devices has recently enjoyed significant gain in popularity, due to the increasing interest in smart vehicles and smart robots. In particular, with the emergence of autonomous driving, low latency and computation-intensive operations lead to new challenges for vehicles and robots, such as excessive computing power and energy consumption. The aim of this paper is to address semantic segmentation, one of the most critical tasks for the perception of the environment, and its implementation in a low power core, by preserving the required performance of accuracy and low complexity. To reach this goal a low-rank convolutional neural network (CNN) architecture for real-time semantic segmentation is proposed. The main contributions of this paper are: i) a tensor decomposition technique has been applied to the kernel of a generic convolutional layer, ii) three versions of an optimized architecture, that combines UNet and ResNet models, have been derived to explore the trade-off between model complexity and accuracy, iii) the low-rank CNN architectures have been implemented in a Raspberry Pi 4 and NVIDIA Jetson Nano 2 GB embedded platforms, as severe benchmarks to meet the low-power, low-cost requirements, and in the high-cost GPU NVIDIA Tesla P100 PCIe 16 GB to meet the best performance.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Design Space Exploration of Single-Lane OFDM-Based Serial Links for
           High-Speed Wireline Communications

    • Authors: Gain Kim;
      Pages: 134 - 146
      Abstract: The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline

    • Authors: Jeremy Cosson-Martin;Hossein Shakiba;Ali Sheikholeslami;
      Pages: 147 - 159
      Abstract: This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a $35dB$ channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
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