 Subjects -> ELECTRONICS (Total: 207 journals)
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- New Year Editorial 2023
Authors:
Gabriele Manganaro;Nicole Mcfarlane;
Pages: 2 - 2
Abstract: DEAR readers, happy 2023! I have recently been elected as the Vice President for Publications for the CAS Society for the 2023–2024 term. Because of that I am unable to complete my term as EiC, which would have otherwise elapsed on 31 December 2023. We are lucky to have two outstanding leaders, Alison Burdett and Nicole Mcfarlane, presently serving as Associate Editors-in-Chief (AEiC). The IEEE Circuits and Systems Society (CASS) has formally appointed Nicole Mcfarlane to serve as the IEEE Open Journal of Circuits and Systems (OJCAS) Editor-in-Chief for the 2023 calendar year and I am glad that she accepted to work in this capacity. I have no doubts that Nicole will carry her new appointment flawlessly and I wish her all the best.
PubDate:
2023
Issue No: Vol. 4 (2023)
- High Efficiency Power Management Unit for Implantable Optical-Electrical
Stimulators
Authors:
Noora Almarri;Dai Jiang;Peter J. Langlois;Mohamad Rahal;Andreas Demosthenous;
Pages: 3 - 14
Abstract: Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation therapy using optical stimulation of genetically modified peripheral neurons requires high current loads. Standard rectification topologies are inefficient and have associated voltage drops unsuited for miniaturized implants. This paper presents an integrated power management unit (PMU) for an optical-electrical stimulator to be used in the treatment of motor neurone disease. It includes a power-efficient regulating rectifier with a novel body biased high-speed comparator providing 3.3 V for the operation of the stimulator, a 3-stage latch-up charge pump with 12 V output for the input stage of the optical-electrical stimulator, and 1.8 V for digital control logic. The chip was fabricated in a $0.18 ~mu text{m}$ CMOS process. Measured results show that for a regulated output of 3.3 V delivering 30.3 mW power, the peak power conversion efficiency is 84.2% at 6.78 MHz inductive link tunable frequency reducing to 70.3% at 13.56 MHz. The charge pump with on chip capacitors has 90.9% measured voltage conversion efficiency.
PubDate:
2023
Issue No: Vol. 4 (2023)
- Imitation System of Humanoid Robots and Its Applications
Authors:
Ze-Feng Zhan;Han-Pang Huang;
Pages: 15 - 24
Abstract: In this paper, we propose an imitation system that imitates human motions in videos to plan robot actions that are similar to human motions, with the aim of the complicated whole-body action planning of humanoid robots. Additionally, we created an interaction system that will enable basic human-robot interaction for our humanoid robot. To obtain the 3D coordinates of the key points on the human body, we used the 3D pose estimation model. The key points were then transformed into various trajectory files needed by the robot to complete the motion, using the mapping method proposed in this research, which refers to the control strategy and stability of the robot. In addition, we proposed some post-processing methods to post-process the trajectories. In the interaction system, we created a speech and vision system so that the robot could detect human gestures or postures and converse with people. It also has a music rhythm recognition system developed by seniors that enables the robot to dance to the beats of the song. Finally, through this system, we completed several human-robot interaction scenarios, which proved the convenience, and effectiveness of motion planning with an imitation system, and the completeness of the interaction system.
PubDate:
2023
Issue No: Vol. 4 (2023)
- A 672-nW, 670-nVrms ECG Acquisition AFE With
Noise-Tolerant Heartbeat Detector
Authors:
Yanhan Zeng;Zhixian Li;Weijian Chen;Wei Zhou;Yuchen Bao;Yongsen Chen;Yongfu Li;
Pages: 25 - 35
Abstract: This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in $0.18 ~mu text{m}$ CMOS process, the circuit only occupies an area of $0.122 mm^{2}$ and consumes $0.62 ~mu text{W}$ at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30–45 dB and 65–105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.
PubDate:
2023
Issue No: Vol. 4 (2023)
- An Inductorless Optical Receiver Front-End Employing a High Gain-BW
Product Differential Transimpedance Amplifier in 16-nm FinFET Process
Authors:
Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami;
Pages: 36 - 49
Abstract: In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dB $Omega $ , a BW of 14.8 GHz, an input-referred noise of 33.6 pA/ $surd $ Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consumes 49 mW and occupies an active area of 0.0076 mm 2.
PubDate:
2023
Issue No: Vol. 4 (2023)
- Comprehensive Mapping of Continuous/Switching Circuits in CCM and DCM to
Machine Learning Domain Using Homogeneous Graph Neural Networks
Authors:
Ahmed K. Khamis;Mohammed Agamy;
Pages: 50 - 69
Abstract: This paper proposes a method of transferring physical continuous and switching/converter circuits working in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) to graph representation, independent of the connection or the number of circuit components, so that machine learning (ML) algorithms and applications can be easily applied. Such methodology is generalized and is applicable to circuits with any number of switches, components, sources and loads, and can be useful in applications such as artificial intelligence (AI) based circuit design automation, layout optimization, circuit synthesis and performance monitoring and control. The proposed circuit representation and feature extraction methodology is applied to seven types of continuous circuits, ranging from second to fourth order and it is also applied to three of the most common converters (Buck, Boost, and Buck-boost) operating in CCM or DCM. A classifier ML task can easily differentiate between circuit types as well as their mode of operation, showing classification accuracy of 97.37% in continuous circuits and 100% in switching circuits.
PubDate:
2023
Issue No: Vol. 4 (2023)
- Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault
Detection in RFCMOS Amplifiers
Authors:
Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander;
Pages: 70 - 84
Abstract: Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in $0.35 mu mathrm{m}$ CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape $Pleft(T_Eright)$ and yield loss $Pleft(Y_Lright)$ of $5 cdot 10^{-2}$ and $1.89 cdot 10^{-2}$ respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.
PubDate:
2023
Issue No: Vol. 4 (2023)
- An On-Chip Fully Connected Neural Network Training Hardware Accelerator
Based on Brain Float Point and Sparsity Awareness
Authors:
Tsung-Han Tsai;Ding-Bang Lin;
Pages: 85 - 98
Abstract: In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other applications, gradually replacing traditional algorithms. It shows that the rise of neural networks has led to the reform of artificial intelligence. Since neural network algorithms are computationally intensive, they require GPUs or accelerated hardware for real-time computation. However, the high cost and high power consumption of GPUs result in low energy efficiency. It recently led to much research on accelerated digital circuit hardware design for deep neural networks. In this paper, we propose an efficient and flexible neural network training processor for fully connected layers. Our proposed training processor features low power consumption, high throughput, and high energy efficiency. It uses the sparsity of neuron activations to reduce the number of memory accesses and memory space to achieve an efficient training accelerator. The proposed processor uses a novel reconfigurable computing architecture to maintain high performance when operating Forward Propagation and Backward Propagation. The processor is implemented in Xilinx Zynq UltraSacle+MPSoC ZCU104 FPGA, with an operating frequency of 200MHz and power consumption of 6.444W, and can achieve 102.43 GOPS.
PubDate:
2023
Issue No: Vol. 4 (2023)
- A Brief Tutorial on Mixed Signal Approaches to Combat Electronic
Counterfeiting
Authors:
Troy Bryant;Yingjie Chen;David Selasi Koblah;Domenic Forte;Nima Maghari;
Pages: 99 - 114
Abstract: As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks.
PubDate:
2023
Issue No: Vol. 4 (2023)
- Adaptive Control Technique for Portable Solar Powered EV Charging Adapter
to Operate in Remote Location
Authors:
Nishant Kumar;Harshit Kumar Singh;Roland Niwareeba;
Pages: 115 - 125
Abstract: Every EV (Electric Vehicle) comes with limited energy storing capability. After travelling a certain distance, a charging facility is required to recharge the EV batteries, which is easy to be made available in cities. But, in remote locations, charging service is challenging. Therefore, big countries like USA, Canada, China, Russia, India, Australia, and few Arabian countries are planning to provide pillar top solar panels on remote locations for EV charging in emergency situations. To operate in this situation, a special charging adapter is required to extract maximum power from the panel using the MPPT (Maximum Power Point Tracking) technique, monitor the charging current, and safely complete the charging process. In this paper, a single sensor-based economical charging adapter is presented for EVs to fulfil this objective. Moreover, the Single Input Fuzzy Logic tuned Deterministic Optimization (SIFL-DO) algorithm is proposed to accomplish MPPT operation and battery charging management. Because of its low cost and fast response, the single current sensor-based charging adapter is highly economical. Additionally, the SIFL-DO algorithm has very good condition estimation and decision-making capability, which accurately performs MPPT and charging management. In this work, the capability of the developed adapter with the SIFL-DO algorithm is evaluated on Hardware prototype. Also, comparative studies are performed w.r.t. state-of-the-art techniques. Further to determine the industry’s suitability, the developed technique is tested on European Standard EN50530.
PubDate:
2023
Issue No: Vol. 4 (2023)
- An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering
16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in
28-nm CMOS
Authors:
Liwen Lin;Ka-Meng Lei;Pui-In Mak;Rui P. Martins;
Pages: 126 - 138
Abstract: This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager $(mu $ PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such $mu $ PM shows a high power efficiency by introducing a 3-stage cascaded structure and a single voltage-regulation loop; they together uphold the performance of the XO-Timer amid supply-voltage and temperature variations. The core amplifier of the XO-Timer is ULV-enabled, and is reconfigurable (i.e., 1-stage and 3-stage gm) to balance between the power budget and performance under the high-performance mode (HPM) and low-power mode (LPM). Fabricated in 28-nm CMOS, the XO-Timer in HPM generates a 16-MHz clock with a power of $24.3 ~mu text{W}$ , and a phase noise of −133.8 dBc/Hz at 1-kHz offset, resulting in a Figure-of-Merit (FoM1) of −236 dBc/Hz. In the LPM, the XO-Timer delivers a 32.258-kHz clock while consuming $11.4 ~mu text{W}$ . The sleep-timer FoM2 is $14.8 ~mu text{W}$ and the Allan deviation is 35.1 ppb, achieving the lowest supply voltage (0.25 V) not only for a dual-mode XO-Timer but also for a MHz-range XO.
PubDate:
2023
Issue No: Vol. 4 (2023)
- Circuit-Level Modeling and Simulation of Wireless Sensing and Energy
Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural
Devices
Authors:
Diptashree Das;Ziyue Xu;Mehdi Nasrollahpour;Isabel Martos-Repath;Mohsen Zaeimbashi;Adam Khalifa;Ankit Mittal;Sydney S. Cash;Nian X. Sun;Aatmesh Shrivastava;Marvin Onabajo;
Pages: 139 - 155
Abstract: A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.
PubDate:
2023
Issue No: Vol. 4 (2023)
- Polychronous Oscillatory Cellular Neural Networks for Solving Graph
Coloring Problems
Authors:
Richelle L. Smith;Thomas H. Lee;
Pages: 156 - 164
Abstract: This paper presents polychronous oscillatory cellular neural networks, designed for solving graph coloring problems. We propose to apply the Potts model to the four-coloring problem, using a network of locally connected oscillators under superharmonic injection locking. Based on our mapping of the Potts model to injection-locked oscillators, we utilize oscillators under divide-by-4 injection locking. Four possible states per oscillator are encoded in a polychronous fashion, where the steady state oscillator phases are analogous to the time-locked neuronal firing patterns of polychronous neurons. We apply impulse sensitivity function (ISF) theory to model and optimize the high-order injection locking of the oscillators. CMOS circuit design of a polychronous oscillatory neural network is presented, and coloring of a geographic map is demonstrated, with simulation results and design guidelines. There is good agreement between theory and Spectre simulation.
PubDate:
2023
Issue No: Vol. 4 (2023)
- A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios
Authors:
Mathieu Xhonneux;Jérôme Louveaux;David Bol;
Pages: 165 - 175
Abstract: We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – $332~mu text{W}$ ) for the digital signal processing of the software-defined radios.
PubDate:
2023
Issue No: Vol. 4 (2023)
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