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IEEE Open Journal of Circuits and Systems
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  This is an Open Access Journal Open Access journal
ISSN (Online) 2644-1225
Published by IEEE Homepage  [228 journals]
  • IEEE Circuits and Systems Society

    • Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Editorial: Where Are We Now and Where Do We Go From Here

    • Authors: Gabriele Manganaro;
      Pages: 1 - 3
      Abstract: Happy 2022 and welcome to the third volume of the IEEE Open Journal of Circuits and Systems (OJ-CAS).
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using
           Convolutional Non-Linear Neural Network

    • Authors: Atsutake Kosuge;Yao-Chung Hsu;Mototsugu Hamada;Tadahiro Kuroda;
      Pages: 4 - 14
      Abstract: A pipelined wired-logic deep neural network (DNN) processor implemented in a 16-nm field-programmable gate array (FPGA) is presented. The latency and power required for memory access are minimized by utilizing the wired-logic architecture, thus enabling low power and high throughput operation. One technical issue with the wired-logic architecture is that it requires a lot of hardware resources. To reduce them, two core technologies are developed: (1) a convolutional non-linear neural network (CNNN) and (2) a pipeline-type neuron cell. The CNNN optimizes both the network structure and the non-linear activation function of each neuron by using a newly developed back-propagation-based training method. While conventional reinforcement learning can train only a small size network thus limiting its application to handwritten number recognition, the proposed CNNN enables a larger network size making it applicable to object recognition. The pipeline-type neuron cell has a small look-up table (LUT) to process non-linear functions using only a small amount of hardware resources. These two technologies enable the implementation of the entire network on a single FPGA chip with the wired-logic architecture. Three types of CNNN trained on the CIFAR-10 dataset are implemented in 16-nm FPGAs. An energy efficiency of 0.09, 0.12, and $0.61~mu text{J}$ /frame is achieved with 70%, 75%, and 82% accuracy, respectively. Compared with a state-of-the-art accelerator using a binary neural network (BNN), the energy efficiency is improved by more than two orders of magnitude.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Stability Boundaries of Wide-Input-Range COT Buck Converters With Ripple

    • Authors: Federico Bizzarri;Paolo Nora;Angelo Brambilla;
      Pages: 15 - 24
      Abstract: In this paper, we focus on instability issues of a wide-input-range Constant ON-Time buck converter. A transconductance stage in the control path that implements ripple compensation characterizes the architecture of this switching circuit. On the whole, decision rules, that heavily influence stability, govern the dynamical evolution of the converter. We show the onset of sub-harmonic oscillations and pulse-bursting caused by the presence of hysteresis in the regulation comparator. Operational boundaries are provided both in analytical and numerical form. They easily support the designer in choosing the converter parameter values. Theoretical results are verified against SIMetrix/SIMPLIS and MPLAB® Mindi™ simulations for a case study involving a commercial adjustable-frequency, synchronous buck regulator featuring an adaptive ON-time control architecture. A good agreement is obtained, as shown.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method
           for FPGA Hardware

    • Authors: Josh Goldsmith;Louise H. Crockett;Robert W. Stewart;
      Pages: 25 - 37
      Abstract: We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 $mu text{s}$ , enabling radio applications in which latency is a principal constraint.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Optimization of Quantized Analog Signal Processing Using Genetic
           Algorithms and μ-Law

    • Authors: Qingnan Yu;Tony Chan Carusone;Antonio Liscidini;
      Pages: 38 - 49
      Abstract: Digital mismatch calibration for quantized analog (QA) signal processing is proposed for the first time. Since the proposed calibration mechanism does not require uniform QA slicer levels, non-uniform quantization can be applied to improve the system performance. We propose two methods utilizing the genetic algorithm and $mu $ -law to find non-uniform slicer levels offering superior performance compared to uniform levels. Simulations show that for a QA amplifier consisting of 32 slices, the signal-to-noise-and-distortion ratio (SNDR) under a multitone input can be doubled by adjusting only the quantization levels while maintaining the same structure and same power, compared to uniform quantization levels that provide 54 dB of SNDR.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using
           Fault-Localization and Partial Reconfiguration

    • Authors: Muhammad Ali Akbar;Bo Wang;Amine Bermak;
      Pages: 50 - 58
      Abstract: In this paper, a self-checking and -repairing carry-lookahead adder (CLA) is proposed with distributed fault detection ability. The presented design with self-checking and fault localization ability requires an area overhead of 69.6% as compared to the conventional CLA. It can handle multiple faults simultaneously without affecting the delay of conventional CLA, with the condition that each module has a single fault at a time. The repairing operation utilizes the hot-standby approach with partial reconfiguration in which the faulty module would be replaced by an accurately functioning module at run-time. The proposed self-repairing adder with high fault coverage requires 161.5% area overhead as compared to conventional CLA design which is 35.3% less as compared to the state-of-the-art partial self-repairing CLA. Moreover, the delay of the proposed 64-bit self-repairing CLA is 40.7% more efficient as compared to conventional ripple carry adder.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Applicability of Hyperdimensional Computing to Seizure Detection

    • Authors: Lulu Ge;Keshab K. Parhi;
      Pages: 59 - 71
      Abstract: Hyperdimensional (HD) computing is a form of brain-inspired computing which can be applied to numerous classification problems. In past research, it has been shown that seizures can be detected from electroencephalograms (EEG) with high accuracy using local binary pattern (LBP) encoding. This paper explores applicability of binary HD computing to seizure detection from intra-cranial EEG (iEEG) data from the Kaggle seizure detection contest based on using both LBP and power spectral density (PSD) features. In the PSD method, three novel approaches to HD classification are presented for both selected features and all features. These are referred as single classifier long hypervector, multiple classifiers, and single classifier short hypervector. To visualize the quality of classification of test data, a hypervector distance plot is introduced that plots the Hamming distance of the query hpervectors from one class hypervector vs. that from the other. Simulation results show that: 1). LBP method offers an average 80.9% test accuracy, 71.9% sensitivity, 81.4% specificity and 76.6% test AUC whereas the PSD method can achieve an average of 91.0% test accuracy, 81.8% sensitivity, 92.0% specificity and 86.9% test AUC. 2). The average seizure detection latency is 2.5s for LBP method and is 4.5s for the PSD methods. This average latency, less than 5s, is a relevant parameter for fast drug delivery, indicating that both LBP and PSD methods are able to detect the seizures in a timely manner. The performance using selected PSD features is better than that using all features. 3). It is shown that the dimensionality of the hypervector can be reduced to 1, 000 bits for LBP and PSD methods from 10, 0-0. Futhermore, for some approaches of selected features, the dimensionality of the hypervector can be reduced to 100 bits.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based
           Transimpedance Amplifier

    • Authors: Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami;
      Pages: 72 - 81
      Abstract: In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB $Omega $ , a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm2.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Analysis and Design Methodology of RF Energy Harvesting Rectifier Circuit
           for Ultra-Low Power Applications

    • Authors: Ziyue Xu;Adam Khalifa;Ankit Mittal;Mehdi Nasrollahpourmotlaghzanjani;Ralph Etienne-Cummings;Nian Xiang Sun;Sydney S. Cash;Aatmesh Shrivastava;
      Pages: 82 - 96
      Abstract: This paper reviews and analyses the design of popular radio frequency energy harvesting systems and proposes a method to qualitatively and quantitatively analyze their circuit architectures using new square-wave approximation method. This approach helps in simplifying design analysis. Using this analysis, we can establish no load output voltage characteristics, upper limit on rectifier efficiency, and maximum power characteristics of a rectifier. This paper will help guide the design of RF energy harvesting rectifier circuits for radio frequency identification (RFIDs), the Internet of Things (IoTs), wearable, and implantable medical device applications. Different application scenarios are explained in the context of design challenges, and corresponding design considerations are discussed in order to evaluate their performance. The pros and cons of different rectifier topologies are also investigated. In addition to presenting the popular rectifier topologies, new measurement results of these energy harvester topologies, fabricated in 65nm, 130nm and 180nm CMOS technologies are also presented.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Design and Implementation of an On-Demand Maximum-Likelihood Sequence
           Estimation (MLSE)

    • Authors: Mohammad Emami Meybodi;Hector Gomez;Yu-Chun Lu;Hossein Shakiba;Ali Sheikholeslami;
      Pages: 97 - 108
      Abstract: This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Stable Digital Impedance Circuit Design Method for Resistive Source

    • Authors: Christopher G. Daniel;Thomas P. Weldon;
      Pages: 109 - 114
      Abstract: The recent discovery that the input impedance of digital impedance circuits is dependent on the external source impedance requires the development of new design procedures to address the significant complexity of this discovery. These circuits are of particular utility for the implementation of difficult non-Foster impedances such as negative capacitance. Therefore, a new digital impedance circuit design procedure is presented where stable digital filter coefficients are computed to provide desired digital impedance values at two chosen frequencies, given that a stable solution exists. The new design procedure explicitly addresses the aforementioned dependence on the external source impedance for digital impedance circuits with resistive sources. Lastly, simulation results from a negative capacitance design example are compared to the new theory to confirm the efficacy of the new design procedure.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Low-Rank CNN Architecture for Real-Time Semantic Segmentation in Visual
           SLAM Applications

    • Authors: Laura Falaschetti;Lorenzo Manoni;Claudio Turchetti;
      Pages: 115 - 133
      Abstract: Real-time semantic segmentation on embedded devices has recently enjoyed significant gain in popularity, due to the increasing interest in smart vehicles and smart robots. In particular, with the emergence of autonomous driving, low latency and computation-intensive operations lead to new challenges for vehicles and robots, such as excessive computing power and energy consumption. The aim of this paper is to address semantic segmentation, one of the most critical tasks for the perception of the environment, and its implementation in a low power core, by preserving the required performance of accuracy and low complexity. To reach this goal a low-rank convolutional neural network (CNN) architecture for real-time semantic segmentation is proposed. The main contributions of this paper are: i) a tensor decomposition technique has been applied to the kernel of a generic convolutional layer, ii) three versions of an optimized architecture, that combines UNet and ResNet models, have been derived to explore the trade-off between model complexity and accuracy, iii) the low-rank CNN architectures have been implemented in a Raspberry Pi 4 and NVIDIA Jetson Nano 2 GB embedded platforms, as severe benchmarks to meet the low-power, low-cost requirements, and in the high-cost GPU NVIDIA Tesla P100 PCIe 16 GB to meet the best performance.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Design Space Exploration of Single-Lane OFDM-Based Serial Links for
           High-Speed Wireline Communications

    • Authors: Gain Kim;
      Pages: 134 - 146
      Abstract: The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline

    • Authors: Jeremy Cosson-Martin;Hossein Shakiba;Ali Sheikholeslami;
      Pages: 147 - 159
      Abstract: This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a $35dB$ channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022

    • Authors: Alison Burdett;
      Pages: 160 - 161
      Abstract: The International Symposium on Integrated Circuits and Systems (ISICAS) is a forum for dissemination of original work with experimental results from integrated circuits and systems in the areas of analog, digital, power, energy, biomedical, sensor interfaces and communications. Papers accepted to be presented at the symposium are automatically published in special issues of leading IEEE Circuits and Systems Society (CASS) journals, namely Transactions on Circuits and Systems (TCAS) Parts I and II, Transactions on Biomedical Circuits and Systems (TBioCAS), and Open Journal of Circuits and Systems (OJCAS).
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • SEKV-E: Parameter Extractor of Simplified EKV I-V Model for Low-Power
           Analog Circuits

    • Authors: Hung-Chi Han;Antonio D’Amico;Christian Enz;
      Pages: 162 - 167
      Abstract: This paper presents the open-source Python-based parameter extractor (SEKV-E) for the simplified EKV (sEKV) model, which enables the modern low-power circuit designs with the inversion coefficient design methodology. The tool extracts the essential sEKV parameters automatically from the given $I$ - $V$ curves using the direct extraction and the multi-stage optimization process. It also handles the overfitting issue because of non-linear least squares. Moreover, this work demonstrates the SEKV-E as a universal tool by widely applying it to different silicon technologies, temperatures, dimensions, and back-gate voltages.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional
           Neural Networks

    • Authors: Jinho Yi;Jiachen Xu;Ethan Chen;Maysamreza Chamanzar;Vanessa Chen;
      Pages: 168 - 179
      Abstract: Real-time in-sensor spike sorting is a forefront requirement in the development of brainmachine interfaces (BMIs). This work presents the characterization, design, and efficient implementation on a field-programmable gate array (FPGA) of a novel approach to neural spike sorting intended for implantable devices based on convolutional neural networks (CNNs). While the temporal features, the shape of the spike signals, could be highly mitigated from the ambient noise, the proposed classifier effectively extracts spatial features from the multi-channel neural signal to maintain high accuracy on the noisy data. The proposed classifier mechanism was tested on real data that is recorded from multi-channel electrodes, containing 27 neural units, and the classifier achieves 93.1% accuracy despite high temporal noise in the signal. For hardware synthesis, the CNN weights are quantized to reduce the model storage requirement by 93% compared to its floating point-precision version, and the model achieves an accuracy of 86.1%.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash

    • Authors: Li-Wei Liu;Mu-Hua Yuan;Yen-Chin Liao;Hsie-Chia Chang;
      Pages: 180 - 191
      Abstract: The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Resistor-Less nW-Level Bandgap Reference With Fine-Grained Voltage and
           Temperature Coefficient Trims

    • Authors: Ori Bass;Asaf Feldman;Joseph Shor;
      Pages: 192 - 198
      Abstract: A nW-level BJT-based bandgap reference with fine grained voltage and temperature coefficient trimming is presented. The bandgap reference utilizes switched capacitors (SC) as impedance elements instead of resistors in a current mode configuration. This configuration enabled low power (38nW) with a minimal area (0.0174 mm2). The voltage could be trimmed independently without affecting the temperature coefficient. The SC’s are stacked in order to achieve accurate trimming without using unrealistically small capacitors. The temperature coefficient can be trimmed between 50-200 ppm/°C in either direction, while the voltage can be trimmed between 580-800mV.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant
           Mixed-Criticality Systems

    • Authors: Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar;
      Pages: 199 - 215
      Abstract: Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named ${mathbf {L}}ife-time ,,{mathbf {P}}eak ,,{mathbf {P}}{ower~management~in},,{mathbf {M}}{ixed}-{mathbf {C}}{riticality,, systems}$ (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data
           Recovery System

    • Authors: Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone;
      Pages: 216 - 227
      Abstract: This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller–Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE) are evaluated from a phase detector performance perspective to enable high CDR loop bandwidth. The impact of loop latency on the timing recovery of ADC-based PAM-4 receivers is also analyzed and demonstrated using accurate behavioral simulations. The analysis and behavioral results show that, to achieve high CDR loop bandwidth with a good jitter tolerance, the phase detector gain to noise ratio should be maximized, and CDR loop latency should be minimized.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash

    • Authors: Li-Wei Liu;Yen-Chin Liao;Hsie-Chia Chang;
      Pages: 228 - 236
      Abstract: An error floor phenomenon, decoding performance, and throughput are three major concerns for LDPC decoders in NAND Flash applications. With a penalty method and an active iteration mechanism, we present a Unified Penalty Gradient Descent Bit Flipping (UP-GDBF) decoding algorithm, which not only possesses error-floor free property but also improves convergence speed in decoding performance. To fulfill the high-throughput requirement while maintaining reliable error correction capability, we propose an energy-based backtracking scheme to reduce 40% latency with a negligible 0.8% area overhead. Implemented in TSMC 16nm process, the proposed 4KB LDPC decoder can achieve a throughput of 19.3 Gbps with 0.120 mm2 area to satisfy ONFI 5.0 throughput requirement. Compared to existing approaches, our decoder architecture provides superior data rate and decoding performance in both 1KB and 4KB LDPC codes.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • RF Analog Hardware Trojan Detection Through Electromagnetic Side-Channel

    • Authors: John Kan;Yuyi Shen;Jiachen Xu;Ethan Chen;Jimmy Zhu;Vanessa Chen;
      Pages: 237 - 251
      Abstract: With the advent of globalization, hardware trojans provide an ever-present threat to the security of devices. Much of the research to date has centered around documenting and providing detection methods for digital trojans. Few, however, have explored the space of trojans in the RF/analog front end. Two hardware trojans, an analytical analysis of the trojan impacts on two different types of amplifiers, and an unsupervised ML detection method for edge IOT applications using magnetic tunnel junction sensors for side-channel monitoring are explored. A classification autoencoder for anomaly detection is presented with an accuracy of greater than 90% with both single tone and BLE data is presented.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Demonstrating Analog Inference on the BrainScaleS-2 Mobile System

    • Authors: Yannik Stradmann;Sebastian Billaudelle;Oliver Breitwieser;Falk Leonard Ebert;Arne Emmel;Dan Husmann;Joscha Ilmberger;Eric Müller;Philipp Spilger;Johannes Weis;Johannes Schemmel;
      Pages: 252 - 262
      Abstract: We present the BrainScaleS-2 mobile system as a compact analog inference engine based on the BrainScaleS-2 ASIC and demonstrate its capabilities at classifying a medical electrocardiogram dataset. The analog network core of the ASIC is utilized to perform the multiply-accumulate operations of a convolutional deep neural network. At a system power consumption of 5.6W, we measure a total energy consumption of $mathrm {192 ~mu text {J} }$ for the ASIC and achieve a classification time of 276 $mu$ s per electrocardiographic patient sample. Patients with atrial fibrillation are correctly identified with a detection rate of (93.7 ± 0.7)% at (14.0 ± 1.0)% false positives. The system is directly applicable to edge inference applications due to its small size, power envelope, and flexible I/O capabilities. It has enabled the BrainScaleS-2 ASIC to be operated reliably outside a specialized lab setting. In future applications, the system allows for a combination of conventional machine learning layers with online learning in spiking neural networks on a single neuromorphic platform.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A 2D Chaotic Oscillator for Analog IC

    • Authors: Partha Sarathi Paul;Parker Hardy;Maisha Sadia;MD Sakib Hasan;
      Pages: 263 - 273
      Abstract: In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic map, Tent map, and so on, or off-the-shelf component-based analog circuits. Due to complex hardware requirements, neither of them is feasible for hardware-efficient integrated circuit (IC) implementations. To the best of our knowledge, this proposed work is the first-ever report of an analog 2D discrete-time chaotic oscillator design that is suitable for hardware-constrained IC implementations. The chaotic performance of the proposed design is analyzed with bifurcation plots, the transient response, 2D Lyapunov exponent, and correlation coefficient measurements. It is demonstrated that the proposed design exhibits promising chaotic behavior with low hardware cost. The real-world application of the proposed 2D chaotic oscillator is presented in a random number generator (RNG) design. The applicability of the RNG in cryptography is verified by passing the generated random sequence through four standard statistical tests namely, NIST, FIPS, TestU01, and Diehard.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Wang Algebra: From Theory to Practice

    • Authors: Bob Ross;Cong Ling;
      Pages: 274 - 285
      Abstract: Wang algebra was initiated by Ki-Tung Wang as a short-cut method for the analysis of electrical networks. It was later popularized by Duffin and has since found numerous applications in electrical engineering and graph theory. This is a semi-tutorial paper on Wang algebra, its history, and modern applications. We expand Duffin’s historic notes on Wang algebra to give a full account of Ki-Tung Wang’s life. A short proof of Wang algebra using group theory is presented. We exemplify the usefulness of Wang algebra in the design of T-coils. Bridged T-coils give a significant advantage in bandwidth, and were widely adopted in Tektronix oscilloscopes, but design details were guarded as a trade secret. The derivation presented in this paper, based on Wang algebra, is more general and simpler than those reported in literature. This novel derivation has not been shared with the public before.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Editorial IEEE Open Journal of Circuits and Systems: Special Section on
           Advanced Power Electronics Techniques for Smart Grid Applications

    • Authors: Mengqi Wang;Xiu Yao;
      Pages: 286 - 287
      Abstract: The Advent of modern power electronics has brought tremendous impact on emerging power systems. In an emerging smart grid, as the number of inverter- and converter-based devices increases to more than hundreds of thousands, it is rather intuitive that the state-of-the-art technical solutions and industry practices will no longer be sustainable. The combination of power electronics and advanced control technologies serve as the key enabler of a wide range of smart grid applications. While tremendous progress has been made in advancing the standalone power electronics technologies, much less attention has been paid to bridging the gap between traditionally disjoint research areas – power electronics, power systems, and intelligent control – ultimately facilitating the vision of 100% carbonneutral energy systems come to fruition. There is a growing interest in the concepts of power electronics-enabled power systems around the world. This special section includes two high-quality papers, which cover the trending topic on the control strategy for inverters that are essential for Smart Grid applications.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Control Strategy of Three-Level NPC Inverter Based on Variable Coefficient
           Virtual Vector Model Predictive Control

    • Authors: Weiquan Gu;Huangzheng Liao;Jiaqi Lin;Zewen Li;Tao Jin;
      Pages: 288 - 297
      Abstract: The Conventional model predictive control (C-MPC) uses only a single voltage vector in each control period, resulting in poor control performance. In addition, the computational burden in discrete space state generated by three-level inverter cannot be ignored. To improve the control performance, this paper proposes a variable coefficient virtual vector MPC (VC-VV-MPC) method, a five-level virtual space voltage vector is constructed to improve the control performance, and a scaling coefficient is used to further improve the control performance. In addition, a voltage vector pre-selection method is used to reduce the computational burden. The simulation and experiment results shown that, compare with C-MPC and adjacent vector MPC (AV-MPC), the proposed VC-VV-MPC can achieve the improvement of control performance under lower computational burden.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • IEEE Open Journal of Circuits and Systems Information for Authors

    • Pages: 294 - 294
      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Droop-Controlled Bidirectional Inverter-Based Microgrid Using
           Cascade-Forward Neural Networks

    • Authors: Mohamad Alzayed;Michel Lemaire;Sina Zarrabian;Hicham Chaoui;Daniel Massicotte;
      Pages: 298 - 308
      Abstract: The voltage source inverters in microgrids often rely on the droop control method integrated with voltage and inner current control loops in order to provide a reliable electric power supply. This research aims to present a Cascade-Forward Neural Network (CFNN) droop control method that manages inverter-based microgrids under grid-connected/islanded operating modes. The proposed method operates the inverter in a bi-directional technique for a wide range of battery energy storage systems or any other distributed generation systems. The proposed strategy uses the CFNN to learn the inverter’s nonlinear model to achieve accurate demand and reference power tracking under different operating conditions for smart grid applications. Additionally, it reformulates the grid control concept to drive the inverter based on the optimal conditions by considering the power demand, reference power, equipment size, and disturbances. Also, it does not require any tuning procedure. The power tracking and operating performance of the proposed CFNN controller are evaluated through several experimental tests using the power hardware-in-the-loop (PHIL) methodology in different scenarios. All results are matched with the proven conventional strategy to confirm its effectiveness.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • Introduction to the Special Section on Smart Imaging

    • Authors: Ping-Hsuan Hsieh;Vanessa Chen;
      Pages: 309 - 310
      Abstract: This Special Section of the IEEE Open Journal of Circuits and Systems is dedicated to a collection of articles on Smart Imaging, to promote techniques in both system and circuit levels to tackle various challenges as the requirements for image quality, efficiency, and levels of integration keep increasing and to provide insightful guidelines for intelligent vision in the years to come. This Special Section covers articles for applications including vision system, time-of-flight system, and terahertz imaging system.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Vision System With 1-inch 17-Mpixel 1000-fps Block-Controlled
           Coded-Exposure Stacked-CMOS Image Sensor for Computational Imaging and
           Adaptive Dynamic Range Control

    • Authors: Tomoki Hirata;Hironobu Murata;Taku Arii;Hideaki Matsuda;Hajime Yonemochi;Yojiro Tezuka;Shiro Tsunai;
      Pages: 311 - 323
      Abstract: This study introduces a vision system that can acquire images at high speeds and high resolutions. Image sensors are used not only in digital still cameras but also in various applications that require capturing wide luminance differences beyond human perception. For example, fast, high-resolution object recognition, and motion tracking in automatic driving systems are essential, particularly in dark tunnels or the mid-summer sunshine. However, the resolution, frame rate, pixel size, and dynamic range should be traded off to achieve a high performance in capturing moving objects with a high contrast. We have developed a high-speed vision system with a readout operation of 1000 fps, resolution of 4K ${times },4text{K}$ , dynamic range of 110 dB, and fine pixels of $2.7~{mu }text{m}$ . These characteristics were achieved using several technologies such as 1) coded exposure (CE), which divides the image plane into smaller blocks and controls the exposure time of each block individually, 2) arrangement of analog-to-digital converters in parallel for each block, and 3) three-dimensional wafer stacking, which enables high-density integration of circuits and pixels. The proposed system can be applied in CE-based computational imaging in addition to high-dynamic-range applications for handling both the dark and bright areas in a scene.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • A Nearly Interference-Free and Depth-Resolution-Configurable
           Time-of-Flight System Based on a Mega-Pixel Vertical Avalanche Photodiodes
           CMOS Image Sensor

    • Authors: Shota Yamada;Motonori Ishii;Shigetaka Kasuga;Masato Takemoto;Hiromu Kitajima;Toru Okino;Yusuke Sakata;Manabu Usuda;Yugo Nose;Hiroshi Koshida;Masaki Tamaru;Akito Inoue;Yuki Sugiura;Shigeru Saito;Taiki Kunikyo;Yusuke Yuasa;Kentaro Nakanishi;Naoki Torazawa;Takashi Shirono;Tatsuya Kabe;Shinzo Koyama;Mitsuyoshi Mori;Yutaka Hirose;Masayuki Sawada;Akihiro Odagawa;Tsuyoshi Tanaka;
      Pages: 324 - 335
      Abstract: We present a long range (~250 m) time-of flight (TOF) system with suppressed (nearly-free) mutual-interference. The system is based on a $1296times960$ pixels vertical avalanche photodiodes (VAPD) CMOS image sensor (CIS). Real-time long-range 3D-imaging with 30 fps speed (450 fps for 2D imaging) is demonstrated. Designs and operation principles of the core circuits, i.e., a photon counting circuit and a global shutter driver, are fully described. The ranging method is based on a sub-range synthesis (SRS) where a range is set by the phase of exposure pulses with respect to that of the light source of the system. The depth resolution is configurable in that the minimum sub-range width limited by the light source pulse width of 10 ns or 1.5 m can be reduced to a 10 cm by introducing an indirect-TOF operation. Furthermore, by employing a random flight timing (RFT), mutual-interference in raw signal level is suppressed by 35 dB when 2 cameras are simultaneously operated. By simulation, the present system is estimated to be tolerant up to a case of 27 cameras operation.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • FPGA-Based Tensor Compressive Sensing Reconstruction Processor for
           Terahertz Single-Pixel Imaging Systems

    • Authors: Wei-Chieh Wang;Yi-Chun Hung;Yu-Heng Du;Shang-Hua Yang;Yuan-Hao Huang;
      Pages: 336 - 350
      Abstract: Terahertz (THz) imaging system has great potentials for material identification, security screening, circuit inspection, bioinformatics and bio-imaging because it can penetrate various non-metallic materials and inhibits unique spectral fingerprints of a great variety of optically opaque materials in our daily lives. However, THz emitters and detectors are still extremely expensive. Therefore, the single-pixel compressive sensing imaging technique becomes a potential solution for the implementation of a THz imaging system. This paper presents a tensor-based single-pixel compressive sensing model and a reconstruction algorithm for THz single-pixel imaging systems based on the generalized tensor compressive sensing framework. To accelerate the THz image reconstruction, a low-complexity 2-D compressive sensing processor based on power singular value decomposition method (2DCS-PSVD) was designed and implemented in this paper. In the $32times32$ single-pixel THz imaging system, the 2DCS-PSVD algorithm requires 78.9% complexity of the modified generalized tensor compressive sensing parallel algorithm (GTCS-P) with little image quality degradation. The 2DCS-PSVD processor was further designed and implemented in the Xilinx ZCU102 SOC FPGA plate-form. The proposed FPGA-based tensor-based compressive sensing processor achieved a throughput of 1127 frames/sec and had the highest normalized hardware efficiency compared to other state-of-the-art works in the literature.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
  • 2022 Index IEEE Open Journal of Circuits and Systems Vol. 3

    • Pages: 351 - 358
      Abstract: Presents the 2022 author/subject index for this issue of the publication.
      PubDate: 2022
      Issue No: Vol. 3 (2022)
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