 Subjects -> ELECTRONICS (Total: 207 journals)
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- A Full-Stack View of Probabilistic Computing With p-Bits: Devices,
Architectures, and Algorithms-
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Authors:
Shuvro Chowdhury;Andrea Grimaldi;Navid Anjum Aadit;Shaila Niazi;Masoud Mohseni;Shun Kanai;Hideo Ohno;Shunsuke Fukami;Luke Theogarajan;Giovanni Finocchio;Supriyo Datta;Kerem Y. Camsari;
Pages: 1 - 11
Abstract: The transistor celebrated its 75th birthday in 2022. The continued scaling of the transistor defined by Moore’s law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning (ML) and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.
PubDate:
June 2023
Issue No: Vol. 9, No. 1 (2023)
- Oscillator-Inspired Dynamical Systems to Solve Boolean Satisfiability
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Authors:
Mohammad Khairul Bashar;Zongli Lin;Nikhil Shukla;
Pages: 12 - 20
Abstract: Dynamical systems can offer a novel non-Boolean approach to computing. Specifically, the natural minimization of energy in the system is a valuable property for minimizing the objective functions of combinatorial optimization problems, many of which are still challenging to solve using conventional digital solvers. In this work, we design two oscillator-inspired dynamical systems to solve quintessential computationally intractable problems in Boolean satisfiability (SAT). The system dynamics are engineered such that they facilitate solutions to two different flavors of the SAT problem. We formulate the first dynamical system to compute the solution to the 3-SAT problem, while for the second system, we show that its dynamics map to the solution of the Max-not-all-equal (NAE)-3-SAT problem. Our work advances our understanding of how this physics-inspired approach can be used to address challenging problems in computing.
PubDate:
June 2023
Issue No: Vol. 9, No. 1 (2023)
- Dynamical System-Based Computational Models for Solving Combinatorial
Optimization on Hypergraphs-
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Authors:
Mohammad Khairul Bashar;Antik Mallick;Avik W. Ghosh;Nikhil Shukla;
Pages: 21 - 28
Abstract: The intrinsic energy minimization in dynamical systems offers a valuable tool for minimizing the objective functions of computationally challenging problems in combinatorial optimization. However, most prior works have focused on mapping such dynamics to combinatorial optimization problems whose objective functions have quadratic degree [e.g., maximum cut (MaxCut)]; such problems can be represented and analyzed using graphs. However, the work on developing such models for problems that need objective functions with degree greater than two, and subsequently, entail the use of hypergraph data structures, is relatively sparse. In this work, we develop dynamical system-inspired computational models for several such problems. Specifically, we define the “energy function” for hypergraph-based combinatorial problems ranging from Boolean Satisfiability (SAT) and its variants to integer factorization, and subsequently, define the resulting system dynamics. We also show that the design approach is applicable to optimization problems with quadratic degree, and use it to develop a new dynamical system formulation for minimizing the Ising Hamiltonian. Our work not only expands on the scope of problems that can be directly mapped to, and solved using physics-inspired models, but also creates new opportunities to design high-performance accelerators for solving combinatorial optimization.
PubDate:
June 2023
Issue No: Vol. 9, No. 1 (2023)
- A Stochastic Computing Scheme of Embedding Random Bit Generation and
Processing in Computational Random Access Memory (SC-CRAM)-
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Authors:
Brandon R. Zink;Yang Lv;Masoud Zabihi;Husrev Cilasun;Sachin S. Sapatnekar;Ulya R. Karpuzcu;Marc D. Riedel;Jian-Ping Wang;
Pages: 29 - 37
Abstract: Stochastic computing (SC) has emerged as a promising solution for performing complex functions on large amounts of data to meet future computing demands. However, the hardware needed to generate random bit-streams using conventional CMOS-based technologies drastically increases the area and delay cost. Area costs can be reduced using spintronics-based random number generators (RNGs), and however, this will not alleviate the delay costs since stochastic bit generation is still performed separately from the computation. In this article, we present an SC method of embedding stochastic bit generation and processing in a computational random access memory (CRAM) array, which we refer to as SC-CRAM. We demonstrate that SC-CRAM is a resilient and low-cost method for image processing, Bayesian inference systems, and Bayesian belief networks.
PubDate:
June 2023
Issue No: Vol. 9, No. 1 (2023)
- A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic
Impedance Boosting and In-ADC Computing-
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Authors:
Tian Xie;Shimeng Yu;Shaolan Li;
Pages: 38 - 46
Abstract: Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. Instead of using access transistors as switches, this work explores their analog characteristics as common-gate current buffers. So the cell current can be minimized and the output impedance is boosted. The idea of In-ADC Computing (IAC) is also proposed to further decrease the complexity of the peripheral circuits. Benefiting from the proposed ideas, a pretrained VGG-8 network based on the CIFAR-10 dataset can be implemented, and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit multiply-and-accumulate (MAC) operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still being able to operate in a power-efficient way.
PubDate:
June 2023
Issue No: Vol. 9, No. 1 (2023)
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