Authors:
Shimeng Yu;
Abstract: Deep learning and nonconvex optimization problems are well known data-intensive applications. Although graphic processing units (GPUs) have become the mainstream platform to accelerate the algorithms in the cloud, there is a growing interest to develop application-specific integrated-circuit (ASIC) chips for further improving the energy-efficiency for these data-intensive workloads. Digital multiply-and-accumulate (MAC) arrays are generally employed as ASIC solutions, and data flow is often optimized to increase the data reuse on-chip. Nevertheless, most of the inputs and outputs are moved across MAC arrays and from global buffers. Therefore, it is more attractive to embed the MAC computations into the memory array itself, namely compute-in-memory (CIM), to minimize the data transfer. In CIM, the vector–matrix multiplication is executed in parallel (with analog computation) where the input vectors activate multiple rows. The dot-product is obtained as the multiplication of input voltage and cell conductance, and the partial sum is added up by the column current. An analog-to-digital converter (ADC) at the edge of the array generally converts the partial sum to binary bits for further digital processing. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Shubham Sahay;Mohammad Bavandpour;Mohammad Reza Mahmoodi;Dmitri Strukov;
Pages: 18 - 26 Abstract: The emerging mobile devices in the era of Internet-of-Things (IoT) require a dedicated processor to enable computationally intensive applications such as neuromorphic computing and signal processing. Vector-by-matrix multiplication is the most prominent operation in these applications. Therefore, there is a critical need for compact and ultralow-power vector-by-matrix multiplier (VMM) blocks to perform resource-intensive low-to-moderate precision computations. To this end, in this article, we propose a time-domain mixed-signal VMM exploiting a modified configuration of 1MOSFET-1RRAM (1T-1R) array. The proposed VMM overcomes the energy inefficiency of the current-mode VMM approaches based on RRAMs. A rigorous analysis of different nonideal factors affecting the computational precision indicates that the nonnegligible minimum cell currents, channel length modulation (CLM), and drain-induced barrier lowering (DIBL) are the dominant mechanisms degrading the precision of the proposed VMM. We also show that there exists a tradeoff between the computational precision, dynamic range, and the area- and energy-efficiency of the proposed VMM approach. Therefore, we provide the necessary design guidelines for optimizing the performance. Our preliminary results indicate that an effective computational precision of 6 bits is achievable owing to the inherent compensation effect in the modified 1T-1R blocks. Furthermore, a 4-bit $200times200$ VMM utilizing the proposed approach exhibits a significantly high energy efficiency of ~1.5 Pops/J and a throughput of 2.5 Tops/s including the contribution from the input/output (I/O) circuitry. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Gouranga Charan;Abinash Mohanty;Xiaocong Du;Gokul Krishnan;Rajiv V. Joshi;Yu Cao;
Pages: 27 - 35 Abstract: Resistive random access memory (RRAM) is a promising technology for energy-efficient neuromorphic accelerators. However, when a pretrained deep neural network (DNN) model is programmed to an RRAM array for inference, the model suffers from accuracy degradation due to RRAM nonidealities, such as device variations, quantization error, and stuck-at-faults. Previous solutions involving multiple read–verify–write (R-V-W) to the RRAM cells require cell-by-cell compensation and, thus, an excessive amount of processing time. In this article, we propose a joint algorithm-design solution to mitigate the accuracy degradation. We first leverage knowledge distillation (KD), where the model is trained with the RRAM nonidealities to increase the robustness of the model under device variations. Furthermore, we propose random sparse adaptation (RSA), which integrates a small on-chip memory with the main RRAM array for postmapping adaptation. Only the on-chip memory is updated to recover the inference accuracy. The joint algorithm-design solution achieves the state-of-the-art accuracy of 99.41% for MNIST (LeNet-5) and 91.86% for CIFAR-10 (VGG-16) with up to 5% parameters as overhead while providing a 15– $150times $ speedup compared with R-V-W. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Justin M. Correll;Vishishtha Bothra;Fuxi Cai;Yong Lim;Seung Hwan Lee;Seungjong Lee;Wei D. Lu;Zhengya Zhang;Michael P. Flynn;
Pages: 36 - 44 Abstract: Analog compute-in-memory with resistive random access memory (RRAM) devices promises to overcome the data movement bottleneck in data-intensive artificial intelligence (AI) and machine learning. RRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMMs), which is a vital operation in these applications. The prototype IC is the first complete, fully integrated analog-RRAM CMOS coprocessor. This article focuses on the digital and analog circuitry that supports efficient and flexible RRAM-based computation. A passive $54times108$ RRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the RRAM crossbar. The single-chip CMOS prototype includes a reduced instruction set computer (RISC) processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface with the passive RRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18- $mu text{m}$ CMOS prototype with a postprocessed RRAM array demonstrates several key functions of machine learning, including online learning. The mixed-signal core consumes 64 mW at an operating frequency of 148 MHz. The total system power consumption considering the mixed-signal circuitry, the digital processor, and the passive RRAM array is 307 mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Wei-Chen Wei;Chuan-Jia Jhang;Yi-Ren Chen;Cheng-Xin Xue;Syuan-Hao Sie;Jye-Luen Lee;Hao-Wen Kuo;Chih-Cheng Lu;Meng-Fan Chang;Kea-Tiong Tang;
Pages: 45 - 52 Abstract: Nonvolatile computing-in-memory (nvCIM) exhibits high potential for neuromorphic computing involving massive parallel computations and for achieving high energy efficiency. nvCIM is especially suitable for deep neural networks, which are required to perform large amounts of matrix–vector multiplications. However, a comprehensive quantization algorithm has yet to be developed, which overcomes the hardware limitations of resistive random access memory (ReRAM)-based nvCIM, such as the number of I/O, word lines (WLs), and ADC outputs. In this article, we propose a quantization training method for compressing deep models. The method comprises three steps: input and weight quantization, ReRAM convolution (ReConv), and ADC quantization. ADC quantization optimizes the error sampling problem by using the Gumbel-softmax trick. Under a 4-bit ADC of nvCIM, the accuracy only decreases by 0.05% and 1.31% for the MNIST and CIFAR-10, respectively, compared with the corresponding accuracies obtained under an ideal ADC. The experimental results indicate that the proposed method is effective for compensating the hardware limitations of nvCIM macros. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Liuting Shang;Muhammad Adil;Ramtin Madani;Chenyun Pan;
Pages: 53 - 61 Abstract: Linear programming optimization is central to engineering designs, logistics management, and decision-making in every sector of the economy. Traditional hardware using CPU and GPU platforms for this purpose is severely limited by the scaling of the transistor technology. In this article, we design an analog in-memory computation circuit for accelerating linear programming optimization problems. The scheme includes a memristive crossbar array and analog peripheral circuits that do not require DAC/ADC between each algorithm iteration. In addition, several key parameters related to nonideal device characteristics and interconnect parasitics are discussed for providing practical guidelines. Furthermore, three design schemes are proposed to alleviate the computation error caused by the interconnect resistance for a large-scale crossbar array implementation. Optimal design parameters are quantified under a given number of array size and memristive resistance. Finally, the proposed hardware accelerator and error mitigation techniques are applied to six real-world power system optimization problems. The results show that the average error of generator power and the overall cost is less than 3%. It is demonstrated that the proposed accelerator achieves area, delay, and energy consumption reductions of $sim 151times $ , $sim 33times $ , and $sim 21times $ , respectively, compared with the CMOS digital circuits at the 16-nm technology node for a $1000times1000$ array with 6-bit precision. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Shadi Sheikhfaal;Ronald F. Demara;
Pages: 62 - 70 Abstract: Biological memory structures impart enormous retention capacity while automatically providing vital functions for chronological information management and update the resolution of the domain and episodic knowledge. A crucial requirement for hardware realization of such cortical operations found in biology is to first design both short-term memory (STM) and long-term memory (LTM). Herein, these memory features are realized via a beyond-CMOS-based learning approach derived from the repeated input information and retrieval of the encoded data. We first propose a new binary STM-LTM architecture with composite synapse of the spin Hall effect-driven magnetic tunnel junction (SHE-MTJ) and capacitive memory bit cell to mimic the behavior of biological synapses. This STM-LTM platform realizes the memory potentiation through a continual update process using STM-to-LTM transfer, which is applied to neural networks based on the established capacitive crossbar. We then propose a hardware-enabled and customized STM-LTM transition algorithm for the platform considering the real hardware parameters. We validate the functionality of the design using SPICE simulations that show the proposed synapse has the potential of reaching ~30.2-pJ energy consumption for STM-to-LTM transfer and 65 pJ during STM programming. We further analyze the correlation between energy, array size, and STM-to-LTM threshold utilizing the MNIST data set. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Masoud Zabihi;Arvind K. Sharma;Meghna G. Mankalale;Zamshed Iqbal Chowdhury;Zhengyang Zhao;Salonik Resch;Ulya R. Karpuzcu;Jian-Ping Wang;Sachin S. Sapatnekar;
Pages: 71 - 79 Abstract: This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Zamshed I. Chowdhury;Masoud Zabihi;S. Karen Khatamifard;Zhengyang Zhao;Salonik Resch;Meisam Razaviyayn;Jian-Ping Wang;Sachin S. Sapatnekar;Ulya R. Karpuzcu;
Pages: 80 - 88 Abstract: Recent years have witnessed an increasing interest in the processing-in-memory (PIM) paradigm in computing due to its promise to improve the performance through the reduction of energy-hungry and long-latency memory accesses. Joined with the explosion of data to be processed, produced in genomics—particularly genome sequencing—PIM has become a potential promising candidate for accelerating genomics applications since they do not scale up well in conventional von Neumann systems. In this article, we present an in-memory accelerator architecture for DNA read alignment. This architecture outperforms corresponding software implementation by >49X and >18 000X, in terms of throughput and energy efficiency, respectively, even under conservative assumptions. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Giacomo Pedretti;Piergiulio Mannocci;Shahin Hashemkhani;Valerio Milo;Octavian Melnic;Elisabetta Chicca;Daniele Ielmini;
Pages: 89 - 97 Abstract: Data-intensive computing applications, such as object recognition, time series prediction, and optimization tasks, are becoming increasingly important in several fields, including smart mobility, health, and industry. Because of the large amount of data involved in the computation, the conventional von Neumann architecture suffers from excessive latency and energy consumption due to the memory bottleneck. A more efficient approach consists of in-memory computing (IMC), where computational operations are directly carried out within the data. IMC can take advantage of the rich physics of memory devices, such as their ability to store analog values to be used in matrix–vector multiplication (MVM) and their stochasticity that is highly valuable in the frame of optimization and constraint satisfaction problems (CSPs). This article presents a stochastic spiking neuron based on a phase-change memory (PCM) device for the solution of CSPs within a Hopfield recurrent neural network (RNN). In the RNN, the PCM cell is used as the integrating element of a stochastic neuron, supporting the solution of a typical CSP, namely a Sudoku puzzle in hardware. Finally, the ability to solve Sudoku puzzles using RNNs with PCM-based neurons is studied for increasing size of Sudoku puzzles by a compact simulation model, thus supporting our PCM-based RNN for data-intensive computing. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Authors:
Mohammad Bavandpour;Mohammad R. Mahmoodi;Dmitri B. Strukov;
Pages: 98 - 106 Abstract: We introduce “aCortex,” an extremely energy-efficient, fast, compact, and versatile neuromorphic processor architecture suitable for the acceleration of a wide range of neural network inference models. The most important feature of our processor is a configurable mixed-signal computing array of vector-by-matrix multiplier (VMM) blocks utilizing embedded nonvolatile memory arrays for storing weight matrices. Analog peripheral circuitry for data conversion and high-voltage programming are shared among a large array of VMM blocks to facilitate compact and energy-efficient analog-domain VMM operation of different types of neural network layers. Other unique features of aCortex include configurable chain of buffers and data buses, simple and efficient instruction set architecture and its corresponding multiagent controller, programmable quantization range, and a customized refresh-free embedded dynamic random access memory. The energy-optimal aCortex with 4-bit analog computing precision was designed in a 55-nm process with embedded NOR flash memory. Its physical performance was evaluated using experimental data from testing individual circuit elements and physical layout of key components for several common benchmarks, namely, Inception-v1 and ResNet-152, two state-of-the-art deep feedforward networks for image classification, and GNTM, Google’s deep recurrent network for language translation. The system-level simulation results for these benchmarks show the energy efficiency of 97, 106, and 336 TOp/J, respectively, combined with up to 15 TOp/s computing throughput and 0.27-MB/mm2 storage efficiency. Such estimated performance results compare favorably with those of previously reported mixed-signal accelerators based on much less mature aggressively scaled resistive switching memories. PubDate:
June 2020
Issue No:Vol. 6, No. 1 (2020)
Hybrid journal (It can contain Open Access articles)
