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  Subjects -> ELECTRONICS (Total: 207 journals)
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Journal of Electronic Design Technology
Journal Prestige (SJR): 0.1
Number of Followers: 8  
 
  Full-text available via subscription Subscription journal
ISSN (Print) 2321-4228
Published by STM Journals Homepage  [66 journals]
  • A Review of Android Application Development

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      Authors: Deependra Pandey, Rohan Raj Gupta
      Pages: 1 - 10
      Abstract: Android applications are now ubiquitous and an essential element of the present and future landscape. With over 2.8 billion active users in over 190 countries and a market share of 75%, the Android Operating System is one of the most popular operating systems in the world. It is a Google-sponsored open-source operating system created by the Open Handset Alliance. It was also founded in 2003 by Andy Rubin, Rich Miner, Nick Sears, and Chris White. Samsung, Huawei, and Xiaomi are the top three Android smartphone manufacturers. It's easy to use, has a wide user base, allows for more customization, and many companies produce Android-compatible smartphones. As a result, the market for Android mobile application development is experiencing a boom in demand, necessitating the hiring of skilled developers with the requisite skill set. Android was created with the intention of being a mobile operating system. Because of the expansion of code libraries and its popularity among developers in the divergence sector, Android has become an absolute set of software for all devices such as tablets, wearables, set-top boxes, smart TVs, notebooks, and so on. Google prefers to write Android apps in Kotlin, which was created and is maintained by JetBrains and has been declared as an official language for Android development. Previously, Java was regarded to be the official language for Android development, however Kotlin was declared the official language during Google I/O 2017. Also, when compared to other platforms, it is simpler to publish an Android app on Google Play. 
      PubDate: 2022-06-09
      Issue No: Vol. 13, No. 2 (2022)
       
  • Analysis and Characterization of Circuits for Leakage Power Reduction at
           Sub-50 nm in CMOS Circuits

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      Authors: Nitu Gupta
      Pages: 11 - 22
      Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As the technology is increasing, transistor length is reducing in the CMOS VLSI circuit. The leakage power has been taken as a major problem as the scaling has been extended into ultra-deep sub-micron technology (UDSM). The reduction in the length of the transistor decreases the threshold voltage, and this causes the sub-threshold current increases. Designing of nanoscale CMOS VLSI circuit and the leakage power reduction are very challenging task. this leakage current should be shrunk for the trouble free operation of the desired circuits. Beforehand for leakage power reduction many methods have been used like leakage feedback technique, sleepy keeper technique, sleep transistor technique, MTCMOS (multi-threshold CMOS), dual sleep approach. As we approach UDSM design then the total chip power consumption depends on the leakage power of the circuit. This paper analysis differentiates the past work for leakage power reduction with proposed work and this paper gives better result which is quite different from the past technology because of the parameters like threshold voltage (Vth), channel width and length. The proposed work has been completed on the sub-50 nm technology file with the tool used is LTspice XVII
      PubDate: 2022-06-09
      Issue No: Vol. 13, No. 2 (2022)
       
  • Designing and Testing of various types of SRAM topologies with 90nm
           Technology

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      Authors: A. Vijayaprabhu, G. Manimegalai, Vijayaraghavan. N, Muthamizhan M.
      Pages: 12 - 16
      Abstract: VLSI technology provides a way for designing compact devices which are useful to human for leading their day to day, the advancement in the technology provides high speed and power consuming appliances. In this category, intend to design an application with high data rate and low power, memory efficient device and Static Random-Access Memory (SRAM) is structured. Improvement in the technology comprises of scaling down the design process and impact in the noise margin and make it minimum in the proposed SRAM cells. Due to the shrinking of SRAM cell it leads to a power leakage in the circuit which makes losses in the data transition. To overcome this issue, this article intended to concentrate on the power dissipation in the SRAM during transition of data from one state to another state. The objective is solved for the 6T, 7T, 8T and 9T by designing the structure with dual- threshold-voltage at the SRAM designing process. By the proper implementation the power dissipation and overall delay in transition in the cells are analyzed and evaluated. This is implemented in 90nm Generic Process Design Kit (GPDK) using tanner tool Schematic Composer and the Specter as the simulator.
      PubDate: 2022-05-26
      DOI: 10.37591/joedt.v13i1.6381
      Issue No: Vol. 13, No. 2 (2022)
       
  • Design of Voltage Controlled Oscillator using GDPK 90nm CMOS Technology

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      Authors: Pujan Vasoya, Dipesh Panchal
      Pages: 17 - 24
      Abstract: In the recent decade, there has been a major revolution in communication systems and devices. Many communication devices required a specific frequency which may range from a few Hz to several GHz by source of voltage. Voltage Control Oscillator (VCO) plays a major role in today’s modern communication system. Voltage Control Oscillator use as basic building block in communication circuits and major use in phase locked loops circuits. Due to the decrease of the channel length of MOSFET, there is a continuous evolution in voltage control oscillator design to achieved high frequency (GHz) operation at lower technology nodes. An oscillator is an essential part of numerous electronic devices and has large numerous applications for wireless devices. This paper is focused on the design of a voltage control oscillator (VCO) using GDPK 90nm CMOS technology in cadence. Mixed Ring Oscillator required less area compared to Ring Oscillator and LC based Oscillator because it is straight forward design and there is no requirement of any passive component like an inductor. Design of 3 Stage Current Starved Voltage Control Oscillator (VCO) has an odd number of cascaded inverters which placed back-to-back and the last inverter stage output is directly fed to the first inverter stage as input.. Voltage Control Oscillator is designed using 90nm CMOS technology with 1.2V power supply voltage. Voltage Control Oscillator output oscillates at a high-frequency range starting from 8.86Ghz to 15.11Ghz by varying a control voltage from 0.3V to 1.2V. The power consumption of the voltage control oscillator is 0.214-milliwatt at 15.61 GHz frequency.
      PubDate: 2022-05-26
      Issue No: Vol. 13, No. 2 (2022)
       
  • Visualizing And Forecasting Stocks Using Single Page Application

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      Authors: M. John Manohar, K. Bharath Reddy, Md. Fayazuddin, Venkata Rao Tavanam
      Pages: 23 - 28
      Abstract: In the fields of finance and economics, stock price forecasting is a vital and crucial subject. The stock market is not governed by any significant rules that may be used to anticipate or estimate the price of a stock. In an effort to forecast the price in the stock market, several techniques are employed, including technical analysis, fundamental analysis, time series analysis, statistical analysis, etc. However, none of these techniques has been consistently demonstrated to be an effective prediction tool. We attempt to implement, forecast and analyze stock market prices in this paper. With breakthroughs in the fields of computer and artificial intelligence, neural networks based on machine learning techniques are becoming more effective for stock price prediction and modelling. The relationship between the selected elements and share price is formed using the dash library in Python, which can aid in anticipating accurate outcomes. Despite the fact that the stock market can never be precisely forecasted owing to its unpredictability, the purpose of this project is to use the notion of prediction and analyze data in order to forecast stocks.
      PubDate: 2022-07-30
      Issue No: Vol. 13, No. 2 (2022)
       
  • Design of Low Noise Transimpedance Amplifier using Multiple Feedback
           filter Topology

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      Authors: E. N. Ganesh
      Pages: 25 - 30
      Abstract: This study presents the highly linear and low noise transimpedance amplifier (TIA) based on CMOS inverter as an amplifier within multiple feedback (MPFB) filter topology. Absence of complex analog circuitry and compatibility with widespread digital CMOS processes highlight this TIA topology as
      the best choice in signal conditioning chains approaching analog-to-digital converters (ADCs). Special attention has been given to the TIA stability and compensation networks. Using dedicated low-dropout (LDO) regulator, the variations in TIA performance induced by supply noise have been made more robust. Transimpedance and bandwidth programmability is ensured by design of the feedback network. Nominal transimpedance and bandwidth at 65°C are 72 dBΩ and 5 MHz, respectively. Achieved third-order intermodulation distortion is –84 dBc, while input third-order intercept point is 34 dBm. This performance is comparable with state-of-the-art TIA solutions used in optical receivers and communication baseband circuits. Basic CMOS inverters were utilized as intensifiers which saves region, yet challenges soundness of the enhancer. Crossing shaft parting pay network between TIA stages is executed while transfer speed, bending level and clamor execution were kept inside wanted edges. This multiple feedback topology gives highly linear CMOS inverter that can be utilized for excellent signal conditioning circuits and applicable for high linear operations.
      PubDate: 2022-06-21
      Issue No: Vol. 13, No. 2 (2022)
       
 
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