 Subjects -> ELECTRONICS (Total: 207 journals)
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- IEEE ELECTRON DEVICES SOCIETY
Pages: C2 - C2
PubDate:
2023
Issue No: Vol. 11 (2023)
- Editorial
Authors:
Enrico Sangiorgi;
Pages: 1 - 2
Abstract: The Journal of Electron Devices Society (J-EDS) is the Gold Open Access publication of the Electron Device Society and since inception in 2013, it has gained and consolidated its scientific reputation.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Golden List of Reviewers for 2023
Pages: 3 - 14
PubDate:
2023
Issue No: Vol. 11 (2023)
- Doping-Free Complementary Metal-Oxide-Semiconductor Inverter Based on
N-Type and P-Type Tungsten Diselenide Field-Effect Transistors With
Aluminum-Scandium Alloy and Tungsten Oxide for Source/Drain Contact
Authors:
Takamasa Kawanago;Ryosuke Kajikawa;Kazuto Mizutani;Sung-Lin Tsai;Iriya Muneta;Takuya Hoshii;Kuniyuki Kakushima;Kazuo Tsutsui;Hitoshi Wakabayashi;
Pages: 15 - 21
Abstract: In this study, we experimentally demonstrated concepts for realizing doping-free Tungsten Diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter by developing alloys and compound metals used as source/drain (S/D) contacts. Aluminum – scandium alloy (AlSc) and tungsten oxide (WOx)-based S/D contacts enable efficient electron and hole injection into WSe2 for n-type and p-type FET operation because the work function (WF) of AlSc and WOx are aligned to neighboring the conduction and valence band edge of WSe2, respectively. A dual-gate bias architecture is used to improve electrical characteristics of FETs and enhance CMOS inverter performance after device fabrication. By utilizing AlSc and WOx-based S/D contacts in conjunction with the dual-gate bias architecture, our fabricated WSe2 CMOS inverter realized a higher gain at $text{V}_{mathrm{ dd}}$ of 1 V or higher than those in the literatures. Furthermore, the fabricated WSe2 CMOS inverter is operated at a power supply voltage ( $text{V}_{mathrm{ dd}}$ ) of as low as 0.5 V. This study paves the way towards research and development of transition metal dichalcogenides-based devices and circuits.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic
Temperatures
Authors:
Anuj Bhardwaj;Sujit. K. Singh;Abhisek Dixit;
Pages: 22 - 29
Abstract: In this paper, we present on the cryogenic characterization of short channel 28-nm FD-SOI nMOS and pMOS transistors having widths of the $1 ~mu text{m}$ and $0.08 ~mu text{m}$ at temperatures ranging from T = 300 K down to T = 10 K. We report, for the first time, the alarming concerns that the narrow-width effect imposes on the overall performance of highly scaled FD-SOI technologies, at temperatures below T = 77 K. The performance comparison between nMOS and pMOS devices is based on their drain current, threshold voltage, transconductance, subthreshold slope, low field mobility and total resistance. Our results show that the sensitivity of narrow width effects towards drain current, threshold voltage and total resistance is smaller in pMOS as compared to nMOS. The effective improvement in transconductance is also significantly larger in narrow width pMOS in comparison to their nMOS counterparts. A substantial degradation of subthreshold swing, total resistance and low field mobility is also observed in narrow nMOS devices, which questions the width scaling benefits of these technologies at cryogenic temperatures.
PubDate:
2023
Issue No: Vol. 11 (2023)
- New Insights Into Noise Characteristics of Hot Carrier Induced Defects in
Polysilicon Emitter Bipolar Junction Transistors and SiGe HBTs
Authors:
Kunfeng Zhu;Peijian Zhang;Zicheng Xu;Tao Wang;Xiaohui Yi;Min Hong;Yonghui Yang;Guangsheng Zhang;Jian Liu;Jianan Wei;Yang Pu;Dong Huang;Ting Luo;Xian Chen;Xinyue Tang;Kaizhou Tan;Wensuo Chen;
Pages: 30 - 35
Abstract: Low frequency (LF) noise is a powerful and non-destructive technique for evaluating the oxide-semiconductor interface and an effective evaluating tool in characterizing electronic device’s structure and reliability. In this study, we present a systematic analysis of the striking abnormal 1/f noise behavior of the hot carrier induced defects in highspeed polysilicon emitter bipolar transistors (PE-BJTs) and SiGe HBTs. Here, the comparative results before and after hot carrier degradation reveal that low frequency noise spectra are not correlated with the density and distribution of the interfacial defects, which related to Si dangling bonds reside at the SiO2/Si interface in PE-BJTs and SiGe HBTs.
PubDate:
2023
Issue No: Vol. 11 (2023)
- A Tall Gate Stem GaN HEMT With Improved Power Density and Efficiency at
Ka-Band
Authors:
Ping-Hsun Lee;Yueh-Chin Lin;Heng-Tung Hsu;Yi-Fan Tsao;Chang-Fu Dee;Pin Su;Edward Yi Chang;
Pages: 36 - 42
Abstract: In this letter, AlGaN/GaN HEMTs with tall-gate-stem structures were realized to improve the power performance of Ka-band devices, and a film thinning process is adopted in the fabrication process to reduce the parasitic capacitance caused by the thick silicon nitride film. According to the S-parameter measurement results, devices owning a tall-gate-stem structure and undergoing the film thinning process have higher cut-off frequency (fT) and maximum oscillation frequency (fmax) values with lower extracted parasitic capacitance. For the load-pull measurement result, the AlGaN/GaN HEMT with a tall gate stem has improved output power density (Pout) and power added efficiency (PAE) at Ka-band. The device with the elevated stem shows a steady-state current density of 883 mA/mm and a maximum transconductance of 323 mS/mm at 20 V bias, and it achieves ${mathrm{ f}}_{mathrm{ T}}$ of 39.5 GHz, ${mathrm{ f}}_{max }$ of 112.9 GHz with the maximum PAE of 24.6% and the maximum ${mathrm{ P}}_{mathrm{ out}}$ of 6.6 W/mm at 38 GHz.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Investigation of Recovery Phenomena in Hf0.5Zr0.5O2-Based 1T1C FeRAM
Authors:
Jun Okuno;Tsubasa Yonai;Takafumi Kunihiro;Yusuke Shuto;Ruben Alcala;Maximilian Lederer;Konrad Seidel;Thomas Mikolajick;Uwe Schroeder;Masanori Tsukamoto;Taku Umebayashi;
Pages: 43 - 46
Abstract: We have previously studied fatigue and its recovery phenomenon on 64 kbits hafnium-based one-transistor and one-capacitor (1T1C) ferroelectric random-access memory (FeRAM) with PVD-TiN (30 nm)/ALD- Hf0.5Zr0.5O2 (8 nm)/CVD-TiN (50 nm) capacitors. In this study, we characterized a single large capacitor fabricated using the same process as the 1T1C FeRAM to clearly understand the recovery mechanism and comprehensively qualify the recovery effect. The results reveal that the recovery effect is caused by domain depinning and new domains switching owing to a redistribution of oxygen vacancy. Furthermore, it is evident from recovery voltage and recovery pulse width dependence of the recovery effect that the recovery voltage can be reduced by applying a longer recovery pulse width. This enables a more flexible circuit design of 1T1C FeRAM when the recovery method is applied to enhance the cycling endurance.
PubDate:
2023
Issue No: Vol. 11 (2023)
- RF Overdrive Burnout Behavior and Mechanism Analysis of GaN HEMTs Based on
High Speed Camera
Authors:
Chang Liu;Hong Xia Liu;Yi Qiang Chen;Yi Jun Shi;Yu Han Xie;Si Chen;Ping Lai;Zhi Yuan He;Yun Huang;
Pages: 47 - 53
Abstract: In this work, a new method for failure analysis of electronic components, high speed camera, is used to investigate burnout failure location of GaN HEMTs under RF overdrive stress. Based on the high speed camera system and the RF test system, we can filter out most of the burn flashes, and clearly locate the weak parts of devices. To further explain the burnout mechanism, a long-term (100 h) RF overdrive stress experiment was carried out and the significant degradation was observed. The drain-source current decreases and the threshold voltage drifts forward. These phenomena show that the degradation of RF overdrive stress is based on hot electron effect (HEE), which is related to the electric field. Besides, Electroluminescence (EL) tests are used and the non-uniform but strong luminescence characteristics of the gate were found, which indicates the strong electric field is the main cause of burnout. We also explore the correlation between burnout and ambient temperature. It was found that the influence of ambient temperature on the burnout was limited. At last, a TCAD simulation is carried out to confirm the temperature and electric field distribution in the device when burnout. It can be found that the electric field inside the device exceeded the breakdown electric field of GaN, which further proves that the burnout caused by RF overdrive is mainly due to electric field rather than temperature.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Germanium Spherical Quantum-Dot Single-Hole Transistors With
Self-Organized Tunnel Barriers and Self-Aligned Electrodes
Authors:
Chi-Cheng Lai;R. C. Pan;I-Hsiang Wang;T. George;Horng-Chih Lin;Pei-Wen Li;
Pages: 54 - 59
Abstract: We report the fabrication and electrical characterization of single-hole transistors (SHTs), in which a Ge spherical quantum dot (QD) weakly couples to self-aligned electrodes via self-organized tunnel barriers of Si3N4. A combination of lithographic patterning, sidewall spacers, and self-assembled growth was used for fabrication. The core experimental approach is based on the selective oxidation of poly-SiGe spacer islands located at the specially designed included-angle locations of Si3N4/Si-trenches. By adjusting processing times for conformal deposition, etch back and thermal oxidation, good tunability in the Ge QD size and its tunnel-barrier widths were controllably achieved. Each Ge QD is electrically addressable via self-aligned Si gate and reservoirs, thus offering an effective building block for implementing single-charge devices.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Interface Scattering as a Nonlocal Transport Phenomenon in Semiconductors
Authors:
M. G. Ancona;S. J. Cooke;
Pages: 60 - 71
Abstract: Macroscopically non-local effects are common in electron transport in semiconductor devices, occurring whenever the mean free path and/or the deBroglie wavelength are not small compared to geometry/flow length scales. When such effects are important, standard diffusion-drift (DD) theory becomes inaccurate and in need of revision, with the best known example being density-gradient (DG) theory wherein a gradient term is added to the electron gas equation of state to approximate the effect of quantum non-locality. Here we consider a similarly motivated gradient correction to the electron-lattice interaction that accounts for non-locality in the transport physics. Versions of DD and DG theory with this correction are discussed, and then are applied to the analysis of long-channel field-effect transistors where they are found to provide a physics-based approach for modeling and understanding interface scattering.
PubDate:
2023
Issue No: Vol. 11 (2023)
- InAlN/GaN HEMT With n+GaN Contact Ledge Structure for Millimeter-Wave Low
Voltage Applications
Authors:
Can Gong;Minhan Mi;Yuwei Zhou;Pengfei Wang;Yilin Chen;Jielong Liu;Yutong Han;Sirui An;Siyin Guo;Meng Zhang;Qing Zhu;Mei Yang;Xiaohua Ma;Yue Hao;
Pages: 72 - 77
Abstract: In this work, high performance InAlN/GaN HEMT based on the n+GaN regrown ohmic contact with n+GaN contact ledge structure is proposed. The regrown ohmic contact of InAlN/GaN HEMT is formed by MBE n+GaN regrowth and self-stopping etching, which makes the total ohmic contact resistance between the 2DEG channel and the ohmic metal decrease to $0.12 Omega cdot $ mm and forms n+GaN contact ledge structure. Owing to the n+GaN contact ledge on the InAlN barrier, with the increasing of drain-source voltage (VDS), an additional current path comes into being between the n+GaN contact ledge on the InAlN barrier and the 2DEG channel, which can “shorten” the device effective drain-source distance, thus further reducing the parasitic resistance. Compared with regrown InAlN/GaN HEMT without n+GaN contact ledge structure, the peak transconductance (Gm.max) of regrown InAlN/GaN HEMT with n+GaN contact ledge structure increases from 747 mS/mm to 874 mS/mm, and the saturation current density (ID.max) increases from 2.6 A/mm to 2.9 A/mm. Besides, the self-stopping etching on the access region does not induce extra defects, and negligible current collapse is obtained. As the results of low parasitic resistance, high output current density, low knee voltage and negligible current collapse, power-added-efficiency (PAE) of 44% together with output power density (Pout) of 2.5 W/mm is achieved at 30 GHz and $V_{mathrm{ DS}}$ of 10 V, which indicates regrown InAlN/GaN HEMT with n+GaN contact ledge structure has great potential for millimeter-wave low voltage applications. Additionally, the transfer and schottky gate charac-eristics show negligible degradation after OFF/ON-state electrical stress tests.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Suppression of Kink in the Output Characteristics of AlInN/GaN High
Electron Mobility Transistors by Post-Gate Metallization Annealing
Authors:
Sujan Sarkar;Ramdas P. Khade;Ajay Shanbhag;Nandita DasGupta;Amitava DasGupta;
Pages: 78 - 83
Abstract: In this paper, we report the effect of post-gate metallization annealing on the performance of GaN-based High Electron Mobility Transistors (HEMTs). The performances of HEMTs annealed at 200 °C (HEMT1) and at 400 °C (HEMT2) for 5 minutes in N2 ambient are compared. While there is a kink in the output characteristics of HEMT1, there is no such kink in the output characteristics of HEMT2. The kink is attributed to impact ionization in the GaN channel. Surface and interface traps of HEMT1 increase the peak electric field at the drain side gate edge and cause impact ionization. The post-gate metallization annealing at a higher temperature reduces the surface and interface traps, which reduces the peak electric field in HEMT2 and suppresses impact ionization. This is substantiated by TCAD simulations. Threshold voltage instability on the application of negative gate bias stress was also examined for these devices. A positive shift in threshold voltage was observed in HEMT1 on the application of negative gate bias stress, whereas the corresponding shift was negative in HEMT2, indicating the presence of two different types of traps in HEMT1 and HEMT2.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp
Circuits in CMOS ICs With Decoupling Capacitors
Authors:
Yi-Chun Huang;Ming-Dou Ker;
Pages: 84 - 94
Abstract: The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- $mu text{m}$ CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic
Application
Authors:
Munhyeon Kim;Sihyun Kim;Kitae Lee;Jong-Ho Lee;Byung-Gook Park;Daewoong Kwon;
Pages: 95 - 100
Abstract: In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay $({tau }_{mathrm{ delay}})$ and dynamic power $(P_{mathrm{ dyn}})$ are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the ${tau }_{mathrm{ delay}}$ and $P_{mathrm{ dyn}}$ are improved at the same $P_{mathrm{ dyn}}$ (50 $mu text{W}$ ) and ${tau }_{mathrm{ delay}}$ (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.
PubDate:
2023
Issue No: Vol. 11 (2023)
- 24.4 W/mm X-Band GaN HEMTs on AlN Substrates With the LPCVD-Grown
High-Breakdown-Field SiN
x Layer
Authors:
Junji Kotani;Junya Yaita;Kenji Homma;Shirou Ozaki;Atsushi Yamada;Masaru Sato;Toshihiro Ohki;Norikazu Nakamura;
Pages: 101 - 106
Abstract: This paper reports on an AlGaN/GaN high-electron-mobility transistor (HEMT) on free-standing AlN substrates with a record-high output power density of 24.4 W/mm at the X-band. A high-drain current operation of 1.4 A/mm was realized by employing high-density 2-dimensional electron gas channel and regrown Ohmic contacts. Furthermore, a high-voltage operation of 110 V was achieved owing to the high-density and high-breakdown SiNx layer grown by low-pressure/high-temperature chemical vapor deposition. Three-stage AlGaN buffer layers improved the electron mobility of 2-dimensional electron gas and allowed us to grow a GaN channel with a low carbon concentration. Furthermore, a regrown n-GaN contact layer was employed to minimize source/drain contact resistances. A high drain current of 1470 mA/mm and high breakdown voltage of 258 V were achieved. Our results demonstrate the potential of GaN HEMTs on the AlN substrate as next-generation high-power radio frequency devices.
PubDate:
2023
Issue No: Vol. 11 (2023)
- 3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation
Compute-In-Memory SRAM
Authors:
Md. Aftab Baig;Cheng-Jui Yeh;Shu-Wei Chang;Bo-Han Qiu;Xiao-Shan Huang;Cheng-Hsien Tsai;Yu-Ming Chang;Po-Jung Sung;Chun-Jung Su;Ta-Chun Cho;Sourav De;Darsen Lu;Yao-Jen Lee;Wen-Hsi Lee;Wen-Fa Wu;Wen-Kuan Yeh;
Pages: 107 - 113
Abstract: Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration density multi-fold while supporting the inherent SRAM advantages of low write power and near-infinite endurance. We propose stacking multiple 8-transistor CFET-SRAM layers on regular CMOS periphery to achieve an ultra-high-density array for computing-in-memory (CIM). CFET and regular CMOS (FinFET) devices are measured and calibrated with BSIM-CMG compact model. SPICE simulations are performed to evaluate the delay of CIM operation, power consumption, and analog computational error due to device non-linearity. The impact of device non-linearity on neural network inference accuracy is evaluated using the CIMulator simulation platform. Lower CFET current drive due to amorphous (deposited) silicon channel is shown to have negligible impact on CIM operational delay in many cases, as the maximum allowable current is limited by wiring resistance, not transistor drive strength while maintaining accurate weighted sum. Compared to regular 2D CMOS FinFET array. CFET SRAM cells show an improvement up to 57.19% in TOPS/W. Furthermore, the performance in TOPS/W mm 2 is improved up to $19times $ . A factor proportional to the number of stacked layers for monolithically stacked CFET SRAM cells, makes it highly promising for future edge intelligence.
PubDate:
2023
Issue No: Vol. 11 (2023)
- A Flexible Printed Circuit Board-Based ZnO Enzymatic Uric Acid
Potentiometric Biosensor Measurement and Characterization
Authors:
Po-Hui Yang;Che-Tsung Chan;Ying-Sheng Chang;
Pages: 114 - 121
Abstract: This study prepared an enzymatic potentiometric uric acid sensor based on zinc oxide (ZnO) and uricase. Also, we develop a potentiometric differential measurement system. We applied Nafion, APTES, and glutaraldehyde to immobilize the enzyme and increase sensitivity to prevent enzyme leakage. Thus, the uric acid sensor was integrated into FPCB which could provide flexibility to the sensor. In the uric acid concentration range of 2 mg/dL-10 mg/dL, we analyzed the characteristics of sensors with the voltage-time measurement system, measuring the average sensitivity, linearity, response time, limit of detection (LOD), and interference effects. The modification of Nafion and uricase improved the performance of the uric acid sensor.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Study on Flake Graphite Cathode Surface Microstructure in Relativistic
Magnetrons
Authors:
Tingxu Chen;Lihui Jiang;Tao Yang;Tianming Li;Fu Hao;Liu Yang;Renjie Cheng;Haiyang Wang;
Pages: 122 - 129
Abstract: Flake graphite has excellent explosive electron emission performance for its plenty surface micro-bulges and high graphitization degree, but its advantages have rarely been studied in relativistic magnetrons. In this paper, flake graphite cathodes with different fineness were used in coaxial diodes and relativistic magnetrons, and the influence of the surface microstructure of the flake graphite cathode on the relativistic magnetron performance is demonstrated for the first time. The result showed that the graphite microstructure mainly affected the initiation stage of explosive emission. Moreover, the delay time is determined by the degree of graphitization and the surface microstructure of graphite, and the surface microstructure plays a major role. Under the applied voltage of ~330kV-~490kV, The finer flake graphite possessed a shorter emission delay and facilitated the microwave excitation. The excitation time of finer flake graphite is $sim 3ns$ , and $sim 5ns$ for lager flake graphite. After several operations of the relativistic magnetron, the edges of flake graphite were blunted, and the surface of the flake graphite appeared droplet-like areas formed by anode atom sputtering. This work reveals the advantages of the finer flake graphite cathode in the fast priming of the relativistic magnetron, thus shedding new light on cathode design of the relativistic magnetron.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Novel Stacked Passivation Structure for AlGaN/GaN HEMTs on Silicon With
High Johnson’s Figures of Merit
Authors:
Xiaoyi Liu;Jian Qin;Jingxiong Chen;Jianyu Chen;Hong Wang;
Pages: 130 - 134
Abstract: We present a high-performance AlGaN/GaN high electron mobility transistors (HEMTs) on silicon substrate with novel stacked passivation layer (HfO2/SiO2). The stacked passivation structure can effectively modulate the electric field and reduce the electric field peak on the gate side, thus improving the breakdown voltage of the device. The prepared device with a gate length of 450 nm has a unit current gain cutoff frequency (fT) of 31.5 GHz, a maximum oscillation frequency (fMAX) of 46.3 GHz, and a three-terminal OFF-state breakdown voltage (BVgd) of 140 V at the gate-drain distance of $2.3~mu text{m}$ . The estimated Johnson’s figure of merit (J-FOM = BVgd $times text{f}$ T) is 4.4 THz•V, which is three and five times higher than that of the device with single HfO2 passivation layer and single SiO2 passivation layer, respectively. Furthermore, a significant suppression of the current collapse (~5.7%) is observed due to the electric field redistribution near the drain region. The results show that the AlGaN/GaN HEMTs with stacked passivation layer proved to be a promising candidate for high-performance radio frequency (RF) power device applications.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Effect of Amorphous Layer at the Heterogeneous Interface on the Device
Performance of β-Ga2O3/Si Schottky Barrier Diodes
Authors:
Zhenyu Qu;Wenhui Xu;Tiangui You;Zhenghao Shen;Tiancheng Zhao;Kai Huang;Ailun Yi;David Wei Zhang;Genquan Han;Xin Ou;Yue Hao;
Pages: 135 - 140
Abstract: Heterogeneous integration of $beta $ -Ga2O3 with Si substrate is considered as an effective and low-cost technology for the thermal management of $beta $ -Ga2O3 electrical devices. In this work, an isotype heterojunction of n-Ga2O3/n+-Si (Ga2O3/Si) was fabricated by surface activated bonding in which an amorphous layer was induced by ion beam bombardment. The current density of Ga2O3/Si Schottky barrier diodes (SBDs) are about two orders of magnitude lower than that of Ga2O3 bulk SBDs at 2.8 V due to the influence of amorphous layer. The results are consistent with the simulation results when $beta $ -Ga2O3 Mole Fraction (MF $=,,text{n}(beta $ -Ga2O3)/[ $text{n}(beta $ -Ga2O3) + n(SiO2)]) and thickness of amorphous layers (Tox) are set at 0.83 and 3 nm, respectively. Furthermore, devices with different MF and ${mathrm{ T}}_{mathrm{ ox}}$ were simulated based on the nonlocal tunneling model by Sentaurus TCAD. The decrease of $beta $ -Ga2O3 Mole Fraction and increase of amorphous layers thickness in the hetero-interface of Ga2O3/Si SBDs lead to a dramatic degeneration of current density and specific on-resistance in Ga2O3/Si SBDs. These results may provide some guidance for improvement of vertical heterogeneous integration $beta $ -Ga2O3 devices performance.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit
Solutions
Authors:
Ming-Dou Ker;Zi-Hong Jiang;
Pages: 141 - 152
Abstract: In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Fast and Expandable ANN-Based Compact Model and Parameter Extraction for
Emerging Transistors
Authors:
Hyunjoon Jeong;Sangmin Woo;Jinyoung Choi;Hyungmin Cho;Yohan Kim;Jeong-Taek Kong;Soyoung Kim;
Pages: 153 - 160
Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Bit Depth of Drivers for Micro-LED Displays Adopting Low-Temperature
Polysilicon Oxide Thin-Film Transistors
Authors:
Young Jo Ko;Dong-Hwan Jeon;Won-Been Jeong;Myung Gi Lim;Seung-Woo Lee;
Pages: 161 - 166
Abstract: In this paper, the minimum bit depth of drivers for active-matrix light emitting diode (AMLED) displays has been specified to overcome luminance nonuniformity of LEDs for the first time. The pixel circuit comprises seven transistors and one capacitor (7T1C) based on low-temperature polysilicon oxide (LTPO) process. For the experiments, thirty green and blue LEDs were used. When the same data voltage was applied, there was luminance nonuniformity of up to 19% and 41% for green and blue LEDs compared to the reference LEDs. Data voltages were measured to get the same luminance as the target one. It was found that the maximum voltage intervals of 0.9 mV and 1.1 mV were necessary to overcome the luminance nonuniformity for green and blue LEDs, respectively. 1.62 V and 2.80 V were the data voltage ranges of green and blue LEDs, respectively. The bit dept of 11-bit (2,048) is the minimum one because 1.62 V / 0.9 mV for green LEDs is smaller than 2,047. In this way, at least 12-bit is necessary for the bit depth of drivers for blue LEDs.
PubDate:
2023
Issue No: Vol. 11 (2023)
- High Temperature Operation of E-Mode and D-Mode AlGaN/GaN MIS-HEMTs With
Recessed Gates
Authors:
Hanwool Lee;Hojoon Ryu;Junzhe Kang;Wenjuan Zhu;
Pages: 167 - 173
Abstract: High temperature operation of enhancement-mode (E-mode) and depletion-mode (D-mode) AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) was demonstrated. By using the circular device structure, off-state current was effectively suppressed, and record high Ion/Ioff ratio around 108 was obtained at 400 °C. Atomic layer etching was used for formation of the gate recess structure in the E-mode device, and good interface was made which enabled stable normally-off operation up to 400 °C. D-mode device experienced positive threshold voltage shift during the high temperature operation and after cooling down to room temperature, due to strain relaxation. On the other hand, due to the very thin AlGaN layer retained under the gate of the E-mode device, the threshold voltage of the E-mode device is nearly unchanged when the sample is heated up and cooled down. A direct coupled field-effect transistor logic (DCFL) inverter was fabricated based on the E-mode and D-mode devices and showed stable operation up to 400 °C.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Ga-Sn-O Thin-Film Memristor and Analog Plasticity Characteristic
Authors:
Daisuke Makioka;Shu Shiomi;Mutsumi Kimura;
Pages: 174 - 178
Abstract: A Ga-Sn-O (GTO) thin-film memristor has been developed, and an analog plasticity characteristic has been observed. First, GTO thin-film memristors are fabricated by depositing three GTO layers in a stacked structure using sputtering. Next, the current-voltage characteristics are measured by varying the maximum applied voltage after a certain negative voltage, the hysteresis is observed, and the switching characteristics are evaluated, which is regarded as that an analog plasticity characteristic is observed. The parametric study is done for the stacked structure and deposition process, and the proposed operating mechanism is that oxygen vacancies reciprocate by applying negative and positive voltages. Finally, the pulse application characteristic shows the long-term potentiation and depression, which presents a practical possibility to utilize the GTO thin-film memristor for neuromorphic systems.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Development and Challenges of Reliability Modeling From Transistors to
Circuits
Authors:
Xinhuan Yang;Qianqian Sang;Chuanzheng Wang;Mingyan Yu;Yuanfu Zhao;
Pages: 179 - 189
Abstract: The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Ultrafast ID – VG Technique for Reliable Cryogenic Device
Characterization
Authors:
Pragya R. Shrestha;Akin Akturk;Brian Hoskins;Advait Madhavan;Jason P. Campbell;
Pages: 190 - 197
Abstract: An in-depth understanding of the transient operation of devices at cryogenic temperatures remains experimentally elusive. However, the impact of these transients has recently become important in efforts to develop both electronics to support quantum information science as well as cryogenic high-performance computing. In this paper, we discuss a fast time-dependent device characterization technique, capable of examining the charge trapping dynamics of devices operating at cryogenic temperatures. Careful calibrations allow for the acquisition of accurate fast I-V and transconductance transients down to 20 ns for devices operating down to 8 K. The trap charging dynamics was monitored via shifts in both threshold voltage and transconductance. The combination of fast measurements and cold temperatures were used to shift the observable measurement window to reveal charge trapping/de-trapping time dynamics of both fast and slow traps in high-k devices to demonstrate the utility of the fast I-V for cryogenic device characterization.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Cell Design Consideration in SiC Planar IGBT and Proposal of New SiC IGBT
With Improved Performance Trade-Off
Authors:
Meng Zhang;Yamin Zhang;Baikui Li;Shiwei Feng;Mengyuan Hua;Xi Tang;Jin Wei;Kevin J. Chen;
Pages: 198 - 203
Abstract: In silicon carbide (SiC) planar insulated-gate bipolar transistor (IGBT), a large distance between neighboring p-bodies is beneficial to enhance the on-state conductivity modulation, but will expose the gate oxide to high electric field in off-state. With p-bodies placed closer, the gate oxide field is reduced, but the conductivity modulation is suppressed. In this work, a new SiC planar IGBT with oxide shield is proposed and studied by TCAD simulations. The proposed SiC IGBT achieves improved trade-off between on-state voltage drop $(V_{mathrm{ ON}})$ and maximum gate oxide electric field $(E_{text {ox-m}})$ . When a quite larger distance between neighboring p-bodies is adopted in the proposed SiC IGBT, a low $V_{mathrm{ ON}}$ is obtained, while the $E_{text {ox-m}}$ can be kept at a small value with the oxide shielding structures protecting the gate oxide. Switching characteristics are also studied, and the proposed SiC-IGBT delivers much better trade-off between turn-off energy loss $(E_{mathrm{ OFF}})$ and $V_{mathrm{ ON}}$ than the conventional SiC planar IGBT.
PubDate:
2023
Issue No: Vol. 11 (2023)
- A Compact Amorphous In-Ga-Zn-Oxide Thin Film Transistor Pixel Circuit With
Two Capacitors for Active Matrix Micro Light-Emitting Diode Displays
Authors:
Kyeong-Soo Kang;Ji-Hwan Park;Jimin Kang;Chanjin Park;Changwon Jeong;Soo-Yeon Lee;
Pages: 204 - 209
Abstract: In this paper, we propose a novel amorphous In-Ga-Zn-oxide (a-IGZO) thin film transistor (TFT) pixel circuit for pulse width modulation (PWM) driving active matrix micro light-emitting diode $(mu $ LED) displays. The proposed pixel circuit compensates for wavelength shifts according to gray level and threshold voltage (VTH) variation of TFTs with only two capacitors. This compact operation can be achieved by simultaneous compensation for VTH along with data input in the constant current generation (CCG) circuit and the PWM circuit, which consist the pixel. Since the VTH variation in TFTs is compensated, the proposed pixel circuit can supply a uniform and stable current to the $mu $ LED throughout all gray levels. The compensation accuracy was verified by HSPICE with an oxide TFT model based on the measurement data. In addition, we analyzed the optimization method to improve the PWM driving by controlling the electrical properties of TFT, and verified this approach by simulation.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Impact of Channel Thickness on the NBTI Behaviors in the Ge-OI pMOSFETs
With Al2O3/GeOx Gate Stacks
Authors:
Yu Sun;Walter Schwarzenbach;Sicong Yuan;Zhuo Chen;Yanbin Yang;Bich-Yen Nguyen;Dawei Gao;Rui Zhang;
Pages: 210 - 215
Abstract: The impact of channel thickness on the negative-bias temperature instability (NBTI) behaviors has been studied for the Germanium-on-Insulator (Ge-OI) pMOSFETs. It is found that the permanent and recoverable defects are generated simultaneously during the NBTI stress of Ge-OI pMOSFETs. The lower NBTI is confirmed for the Ge-OI pMOSFETs with a thinner channel, due to the reduction of the band bending of ${mathrm{ E}}_{mathrm{ v}}$ under a fixed electrical field of NBTI stress. Thus, the channel thickness scaling could be an effective method to improve the NBTI reliability for Ge-OI pMOSFETs.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Formulation of Ground States for 2DEG at Rough Surfaces and Application to
Nonlinear Model of Surface Roughness Scattering in nMOSFETs
Authors:
Kei Sumita;Min-Soo Kang;Kasidit Toprasertpong;Mitsuru Takenaka;Shinichi Takagi;
Pages: 216 - 229
Abstract: Electron mobility in extremely-thin-body (ETB) nanosheet channels and at cryogenic temperature is known to be dominated by surface roughness scattering. However, the conventional model of surface roughness scattering lacks accuracy because it requires the use of excessive roughness parameters to represent the experimental results. One of the main difficulties for the surface roughness scattering model is that the higher-order perturbations should be accurately included in the model because the surface roughness scattering is a strongly nonlinear phenomenon. Therefore, in this study, the formulation of ground states of two-dimensional electron gas (2DEG) at rough surfaces is derived by introducing a concept of the space-averaged perturbation Hamiltonian. This revised formulation of 2DEG at rough surfaces is different from the conventional solution for 2DEG at the flat surface. The space-averaged perturbation Hamiltonian is invisible in the linearized perturbation system, while its effect is significant in the system with the nonlinear perturbation energy. We combine the revised 2DEG formulation with a nonlinear model of surface roughness scattering and calculate the 2DEG mobility of the bulk Si and ETB Si-on-insulator (SOI) nMOSFETs. As a result, the experimental mobility of bulk and ETB SOI nMOSFETs is well explained in a wide temperature range of 4.2 to 300 K by using the roughness parameters experimentally obtained by transmission electron microscopy (TEM), which also supports the understanding of mobility at cryogenic temperature. The revised nonlinear model reveals that surface roughness scattering under the present model is 13 times stronger than that predicted by the conventional linear model.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Monolithic Dual-Gate E-Mode Device-Based NAND Logic Block for GaN
MIS-HEMTs IC Platform
Authors:
Yuhao Zhu;Fan Li;Miao Cui;Zhicheng Fang;Ang Li;Dongyi Yang;Yinchao Zhao;Huiqing Wen;Wen Liu;
Pages: 230 - 234
Abstract: In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Current Prospects and Challenges in Negative-Capacitance Field-Effect
Transistors
Authors:
Md. Sherajul Islam;Abdullah Al Mamun Mazumder;Changjian Zhou;Catherine Stampfl;Jeongwon Park;Cary Y. Yang;
Pages: 235 - 247
Abstract: For decades, the fundamental driving force behind energy-efficient and cost-effective electronic components has been the downward scaling of electronic devices. However, due to approaching the fundamental limits of silicon-based complementary metal-oxide-semiconductor (CMOS) devices, various emerging materials and device structures are considered alternative aspirants, such as negative-capacitance field-effect transistors (NCFETs), for their promising advantages in terms of scaling, speed, and power consumption. In this article, we present a brief overview of the progress made on NCFETs, including theoretical and experimental approaches, a current understanding of NCFET device physics, possible physical mechanisms for NC, and future functionalization prospects. In addition, in the context of recent findings, critical technological difficulties that must be addressed in the NCFET development are also discussed.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Depletion- and Enhancement-Mode p-Channel MISHFET Based on GaN/AlGaN
Single Heterostructures on Sapphire Substrates
Authors:
Carsten Beckmann;Zineng Yang;Jens Wieben;Thorsten Zweipfennig;Jasmin Ehrler;Arno Kirchbrücher;Holger Kalisch;Andrei Vescan;
Pages: 248 - 255
Abstract: We report on p-channel metal-insulator-semiconductor heterostructure field-effect transistors (MISHFET) based on p-GaN/uid-GaN/Al textsubscript 0.29Ga textsubscript 0.71N single heterostructures on sapphire substrates, grown by metalorganic vapor phase epitaxy (MOVPE). The impact of p-GaN layer removal and channel layer thickness adjustment by dry-etching on the characteristics of the MISHFET are investigated. Depending on the remaining GaN thickness $(t_{mathrm{ GaN}})$ , the fabricated MISHFET show either depletion-mode (d-mode) operation with a threshold voltage $V_{mathrm{ th}}$ of 3.8 V and an on-current $unicode{0x007C}I_{mathrm{ D,on}} unicode{0x007C}$ of 9.5 mA/mm ( $t_{mathrm{ GaN}} = 21$ nm) or enhancement-mode (e-mode) operation with $V_{mathrm{ th}}$ of −2.3 V and $unicode{0x007C}I_{mathrm{ D,on}} unicode{0x007C}$ of 1.5 mA/mm ( $t_{mathrm{ GaN}}= 12$ nm). Independent of the etching depth, all devices exhibit a very low off-state drain current $left I_{mathrm{D}, mathrm{off}}right sim 10^{-8}$ mA/mm and a steep subthreshold swing (SS) between 80 and 89 mV/dec. Similar to n-channel devices, a $V_{th}$ instability caused by charge trapping at the dielectric/semiconductor interface is found, emphasizing that careful interface engineering is required for good device performance.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Investigations on Wide-Gap Al0.21Ga0.79N Channel MOS-HFETs With
In0.12Al0.76Ga0.12N Barrier/Buffer and Drain Field-Plate
Authors:
Ching-Sung Lee;Chih-Tsung Cheng;Jian-Hong Ke;Wei-Chou Hsu;
Pages: 256 - 261
Abstract: This work investigates, for the first time, wide-gap Al0.21Ga0.79N channel metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with In0.12Al0.76Ga0.12N barrier/buffer and drain field-plate (DFP) designs. High-k and wide-gap Al2O3 was grown as the gate oxide and surface passivation by using non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. A control device having the same epitaxial layers, except with In0.12Al0.88N barrier/buffer was studied in comparison. Enhanced spontaneous polarization effect, improved interfacial quality, and enhanced carrier confinement have been achieved by using the In0.12Al0.76Ga0.12N barrier/buffer design, which has successfully resulted in improved carrier transport, increased electron concentration, and high current densities. The present In0.12Al0.76Ga0.12N/AlN/Al0.21Ga0.79N MOS-HFET design with (without) DFP design has demonstrated superior maximum drain-source current density $(I_{DS, max})$ of >1 (>1) A/mm at $V_{DS},,=$ 20 V, high saturated drain-source current density at $V_{GS},,=$ 0 V $(I_{DSS0})$ of 791.1 (755) mA/mm, and low specific on-resistance $(R_{on, sp})$ of 2.83 (2.81) $text{m}Omega $ /cm 2. High device figure-of-merit (FOM) on $BV_{DS}^{2}/R_{on, sp}$ of 93.7 (75.4) MW/cm 2 was also obtained with the three-terminal on-state drain-source breakdown voltage $(BV_{DS})$ of 515 (460) V. The present design is promisingly advantageous to high-current and high-voltage power-switching circuit applications.
PubDate:
2023
Issue No: Vol. 11 (2023)
- High-Performance P-Type Germanium Tri-Gate FETs via Green Nanosecond Laser
Crystallization and Counter Doping for Monolithic 3-D ICs
Authors:
Hao-Tung Chung;Yu-Ming Pan;Nein-Chih Lin;Bo-Jheng Shih;Chih-Chao Yang;Chang-Hong Shen;Huang-Chung Cheng;Kuan-Neng Chen;
Pages: 262 - 268
Abstract: This paper proposed a fabrication of p-type Germanium (Ge) tri-gate field-effect transistors (Tri-gate FETs) via green nanosecond laser crystallization (GNSLC) and counter doping (CD). By using the GNSLC, the nano-crystalline-Ge (nc-Ge) with a grain size of 80 nm could be turned into polycrystalline Ge (poly-Ge) with that of above $1 ~mu text{m}$ . With the increase of laser power, the improved crystallinity and lower hole concentration of poly-Ge were also verified by Raman spectra and Hall measurement. To fabricate the high-performance Ge Tri-gate FETs, the chemical-mechanical planarization (CMP) and counter doping (CD) process would further be utilized. The CMP process eliminated the surface roughness of poly-Ge while the CD process decreased the hole concentration of poly-Ge or even converted that into an N-type one. The effect of the CD on the performance of p-type Ge Tri-gate FETs was further investigated. Consequently, the GNSLC Ge Tri-gate FETs showed threshold voltage (Vth) of −0.41 V, ION of $7.10times 10; ^{-6}$ , and IOFF of $1.28times 10; ^{-9}$ respectively, indicating better crystallinity of the Ge channel.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Highly Efficient Reconfigurable Stateful Logic Operations Based on CuI
Memristor-Only Arrays Prepared With a Solution-Based Process
Authors:
Bochang Li;Li Luo;Wei Wei;Ming Gao;Chunxiang Zhu;
Pages: 269 - 273
Abstract: The in-memory logic computing has been intensively studied as being considered as an important scenario to address the power-consumption issue posed by modern computers based on the von Neumann architecture. However, the realization of in-memory logic computing is generally based on memristors prepared by vacuum techniques and the implementation of logic operation requires multiple cycles of voltage pulses, which limits the computing efficiency. In addition, the logic architectures that cannot be mapped into large crossbar arrays restrict the level of parallelism. A CuI memristor is prepared by a solution-based process in this work. Based on the CuI memristor arrays, with delicately designed implement strategy, a set of logic operations can be implemented with one single cycle of voltage pulses, demonstrating the high efficiency. Moreover, all proposed logic architectures are able to be mapped to large memristor crossbar arrays directly, demonstrating the great potentials in computations with high degree of parallelism. Owing to the reconfigurable property, a one-bit full adder is realized by cascading the memristor-based logic gates.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Demonstration of HfO2-Based Gate Dielectric With ~0.8-nm Equivalent Oxide
Thickness on Si0.8Ge0.2 by Trimethylaluminum Pre-Treatment and Al
Scavenger
Authors:
Meng-Chien Lee;Wei-Lun Chen;Yi-Yang Zhao;Shin-Yuan Wang;Guang-Li Luo;Chao-Hsin Chien;
Pages: 274 - 281
Abstract: We disclosed HfO2-based dielectric of superb electrical properties on p-type Si0.8Ge0.2 substrate using an interfacial layer (IL) formed by trimethylaluminum (TMA) pre-treatment and Al scavenger. Our results revealed that the interface trap density (Dit) value and the gate leakage current (JG) could be improved about 60 times and 100 times by tuning the gate electrode composition without sacrificing equivalent oxide thickness (EOT) performance. The mechanism underlying the ${mathrm{ D}}_{mathrm{ it}}$ improvement of the SiGe metal-oxide-semiconductor capacitors (MOSCAPs) might be owing to the Al metal scavenger and the minimization of the oxygen atoms diffusing to the high- $kappa $ /SiGe IL, verified by x-ray photoelectron spectroscopy (XPS) analyses. In addition, the hysteresis levels of SiGe capacitors with various gate electrodes were measured to find out the optimized configuration of metal electrodes. This work demonstrated the Al scavenger effect from the aspects of both material and electrical properties and achieved an impressive EOT value of $sim 0.8$ nm for the capacitors fabricated on the SiGe substrate.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Quantitative Measurement of Interface State Density in Donor-Acceptor
Polymer Transistors
Authors:
Biaobiao Ding;Yichen Zhu;Run Li;Guangan Yang;Jie Wu;Li Zhu;Xiang Wan;Zhihao Yu;Chee Leong Tan;Yong Xu;Huabin Sun;
Pages: 282 - 287
Abstract: Donor-Acceptor (D-A) polymer field-effect transistors (pFETs) are at the cutting edge of organic electronics. However, some fundamental cognition of interface states remains unquantified, particularly at different dynamic scales. In this study, the interface states of D-A polymer transistors are quantified using the dynamic pumping method. The experimental results indicate that the interface state density of the transistor is insensitive to the measurement pulse condition and stays within the range of $ {10}^{ {12}},,sim ,, {10}^{ {13}},,rm {cm}^{ {-2}}$ . The experiments described in this paper provide a quantitative analysis of interface states. This analysis can serve as effective guidance for optimizing future devices.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With
Improved Carrier Controllability
Authors:
Jie Ma;Yong Gu;Chengwu Pan;Long Zhang;Guiqiang Zheng;Siyang Liu;Weifeng Sun;Changyuan Chang;Sen Zhang;
Pages: 288 - 293
Abstract: Easy inter-connection is a crucial advantage of the single-chip power ICs, which makes power devices with multiple ports easy to improve carrier controllability without increasing process difficulty. Electrical characteristics of the power devices get further improved thanks to the advanced carrier controllability. In this paper, a silicon-on-isolator lateral IGBT (SOI-LIGBT) featured four hybrid gates is proposed to obtain outstanding carrier controllability in turn-on, turn-off and short-circuit conditions for the first time. Four hybrid gates include three planar gates (G1, G2 and G3) and a trench gate (G4), of which G3 and G4 are grounded gate to lower saturation current and suppress latch up. Low turn-off time $(t_{OFF})$ , di/dt and improved short-circuit withstanding capability are obtained through providing different input signals to these gates. In the turn-on, G2 is pre-charged to a stable voltage equal to gate voltage $(V_{G1})$ to suppress the high di/dt before $V_{G1}$ starts to rise. In the turn-off, a P-type inversion is induced by the negative voltage of ${mathrm{ G}}_{2}~(V_{G2})$ , which provides a low-resistance hole current path to extract the stored holes. In the short-circuit condition, G3 and G4 are both shorted to the ground to lower the saturation current and suppress the activation of parasitic NPN transistor, resulting in an improved short-circuit withstanding time $(t_{SC})$ . Compared with the conventional SOI-LIGBT, $t_{OFF}$ and di/dt are reduced by 43.6% and 53.08%, an- $t_{SC}$ is prolonged from $3.04mu text{s}$ to $8.89mu text{s}$ at DC bus voltage of 400V.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Substrate Bias Stress Induced Kink Effect in GaN-on-Silicon
High-Electron-Mobility Transistor
Authors:
Ramdas P. Khade;Sujan Sarkar;Ajay Shanbhag;Amitava DasGupta;Nandita DasGupta;
Pages: 294 - 302
Abstract: In this paper, kink effect observed in the output characteristics of the AlInN/GaN-on-Si high electron mobility transistor (HEMT) after subjecting the Si-substrate to positive/negative bias stress has been studied. The charge distribution in the different buffer layers of the wafer in the presence of different substrate-bias stress has been discussed in detail. It is concluded that the induced kink is due to the trapping/de-trapping of charge carriers through acceptor-like deep levels present in the GaN buffer layer. TCAD simulations have been performed to understand the electric-field distribution within the device layers, which is strongly related to the observed kink phenomenon. Two types of traps, acceptor-like (Ea1 = 0.52 eV) and donor-like (Ea2 = 0.44 eV), were extracted from temperature-dependent drain current transient analysis using back-gating experiment. It is concluded that a carbon-induced deep acceptor-like trap is responsible for the observed kink effect.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Machine Learning-Assisted Device Modeling With Process Variations for
Advanced Technology
Authors:
Yaoyang Lyu;Wangyong Chen;Mingyue Zheng;Binyu Yin;Jinning Li;Linlin Cai;
Pages: 303 - 310
Abstract: Process variations (PV), including global variation (GV) and local variation (LV), have become one of the major issues in advanced technologies, which is crucial for circuit performance and yield. However, developing a mature and physics-based model is challenging and time-consuming. Thus, in this work, we propose a machine learning (ML) based method for device modeling with PV and implement the corresponding circuit simulation, which is demonstrated on advanced Nanosheet FETs (NSFET). Verified by TCAD simulations, the artificial neural network (ANN)-based ML algorithm enables to capture PV, e.g., dimension and work function variations (WFV), with high accuracy and improved efficiency. For GV, the ANN surrogated NSFET-based ring oscillator (RO) simulation results show that the larger width (Wsh) or height (Hsh) of the Nanosheet leads to the higher RO frequency and lower circuit delay. For LV, the respective impacts of grain size and WF on circuit performance can be distinguished. The proposed workflow, from ANN model training to circuit simulation based on the generated Verilog-A model, is fully automatic, promising to shorten the procedure of device modeling and accelerate the development of advanced technologies.
PubDate:
2023
Issue No: Vol. 11 (2023)
- Semiconductor Device Modeling for Circuit and System Design
Pages: 1304 - 1304
PubDate:
2023
Issue No: Vol. 11 (2023)
- Role of Solar Cells in Global Energy Transformation
Pages: 1305 - 1306
PubDate:
2023
Issue No: Vol. 11 (2023)
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