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IEEE Journal of the Electron Devices Society
Journal Prestige (SJR): 1.016
Citation Impact (citeScore): 3
Number of Followers: 8  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2168-6734
Published by IEEE Homepage  [228 journals]

    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: 2022
      Issue No: Vol. 10 (2022)

    • Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Editorial

    • Authors: Enrico Sangiorgi;
      Pages: 1 - 2
      Abstract: I Would like to express my sincere gratitude – and the gratitude of the Electron Device Society (EDS) community at large – to Colin McAndrew, A. G. Unil Perera, and Krishna Shenai, for their commitment, dedication, and hard work during their nine plus years of service on the Journal of the Electron Devices editorial board. They were part of the initial team that launched J-EDS and made it the internationally renowned, open access, vibrant publication of these days. I will miss their knowledge, wisdom, and responsiveness! Our very best wishes to them in their future endeavors.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Hybrid Model of Turn-Off Loss and Turn-Off Time for Junction Temperature

    • Authors: Lingfeng Shao;Guoqing Xu;Pengbo Li;
      Pages: 3 - 12
      Abstract: Temperature-sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature (Tj) extraction and prediction of power semiconductor devices. In this paper, the turn-off loss (Eoff) and turn-off time (toff) are presented as temperature-sensitive electrical parameters. The abrupt change in the junction temperature of Insulated Gate Bipolar Transistor (IGBT) occurs during switching is proved. Common deficiencies in a single temperature-sensitive electrical parameter were considered, including the necessity of the collector currents exaction, the poor junction detection accuracy. Therefore, after the linear relationship between junction temperature and turn-off time, and turn-off loss is proved, a hybrid model based on turn-off loss (Eoff) and turn-off time (toff) is proposed to extract junction temperature accurately. The experimental results show that the proposed method is with the advantages of high accuracy and strong anti-interference ability. Although some high-precision probes are required for parameter extraction, it indicates the internal mechanism of junction temperature mutation of the power device, and it is of great value for the reliability of the power devices that operate continuously.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for
           1T-DRAM Application

    • Authors: Kitae Lee;Sihyun Kim;Jong-Ho Lee;Byung-Gook Park;Daewoong Kwon;
      Pages: 13 - 18
      Abstract: The ferroelectric-metal field-effect transistor with recessed channel (RC-FeMFET) is proposed for one transistor dynamic random-access memory (1T-DRAM). Through technology computer-aided design (TCAD) simulations, the effects of inter-metal insertion on the FeFET with recessed channel (RC-FeFET) is identified. By evaluating electric field (e-field) across interlayer (IL) and memory window (MW), the improvements of program/erase cycling endurance and read current sensing margin (RSM) are verified in the RC-FeMFET. Moreover, considering program voltage (VW) and polarization switching time ( $tau _{mathrm{ p}}$ ), the guide line of the RC-FeMFET design is provided in terms of e-field across IL and MW for 1T-DRAM applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Investigation of Proton Irradiation-Enhanced Device Performances in
           AlGaN/GaN HEMTs

    • Authors: Jeong-Gil Kim;Eunjin Kim;Dong-Seok Kim;Chuyoung Cho;Jung-Hee Lee;
      Pages: 19 - 22
      Abstract: We have studied the effects of proton irradiation on the AlGaN/GaN HEMTs with AlN buffer layer as well as conventional GaN buffer layer. It was found that a short time proton irradiation (~ 50 sec) can promote beneficial effects on device performances, which results in great reduction in the off-state leakage current and the gate leakage current without degrading the output current and transconductance. The pulsed I-V measurement demonstrated that both devices exhibit greatly improved current dispersion characteristics and, particularly, the device with AlN buffer layer shows stronger radiation hardness than that of the device with GaN buffer layer. These interesting results are believed to be due to the hydrogen passivation with thermal annealing effect during the proton irradiation. It is expected that the proper irradiation condition such as fluence, energy, and time is crucial to improve the device performances, rather than to deteriorate the performances.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Scaling Design Effects on Surface Buffer IGBT Characteristics

    • Authors: Wataru Saito;Shin-Ichi Nishizawa;
      Pages: 23 - 28
      Abstract: Scaling design effects on surface buffer (SB) insulated gate bipolar transistor (IGBT) is analyzed not only for power loss reduction but also for switching controllability and robustness using TCAD simulation. Although the scaling design improves turn-off loss and on-state voltage drop $text{V}_{ce(sat)}$ trade-off due to injection enhancement (IE) effect, turn-on surge current is increased by the enhancement of negative gate capacitance due to thin gate oxide. Dual gate control improves turn-on switching controllability by hole current path control. Short circuit robustness is improved by the scaling design, because the saturation current is decreased with the scaling design due to pinch-off of the n-MOS channel. From these results, the scaling design is effective in improving the SB-IGBT characteristics including high robustness.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • 1T1C FeRAM Memory Array Based on Ferroelectric HZO With Capacitor Under

    • Authors: Jun Okuno;Takafumi Kunihiro;Kenta Konishi;Monica Materano;Tarek Ali;Kati Kuehnel;Konrad Seidel;Thomas Mikolajick;Uwe Schroeder;Masanori Tsukamoto;Taku Umebayashi;
      Pages: 29 - 34
      Abstract: A novel system-on-a-chip compatible one-transistor one-capacitor ferroelectric random-access memory array (1T1C FeRAM) based on ferroelectric Hf0.5Zr0.5O2 with a capacitor under bitline (CUB) structure was experimentally demonstrated. The CUB structure facilitates the application of post-metallization annealing on metal/ferroelectric/metal capacitors above 500 °C because they are fabricated before the back-end-of-line process. A large remanent polarization of 2Pr $ {>}40~mu text{C}$ /cm2, projected endurance ${>}10^{11}$ cycles, and ten years of data retention at 85 °C were obtained at 500 °C, after metallization using a single large capacitor. Furthermore, a large memory window of the 64 kbit 1T1C FeRAM array with 500 °C post-metallization was comprehensively demonstrated without degradation of the underlying CMOS logic transistors. The operation voltage and speed dependence were extensively investigated using a dedicated sense amplifier for the 1T1C FeRAM. Furthermore, the perfect bit functionality at an operation voltage of 2.5 V and a read/write speed < 10 ns were obtained. Therefore, superior properties of CUB-structured 1T1C FeRAM can be achieved by flexible process engineering of crystallization annealing for metal/ferroelectric/metal fabrication.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in
           Stacked Nanosheet Transistors

    • Authors: Jie Gu;Qingzhu Zhang;Zhenhua Wu;Yanna Luo;Lei Cao;Yuwei Cai;Jiaxin Yao;Zhaohao Zhang;Gaobo Xu;Huaxiang Yin;Jun Luo;Wenwu Wang;
      Pages: 35 - 39
      Abstract: A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( $text{I}_{mathrm{ on}}/text{I}_{mathrm{ off}}$ ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Mechanism of Non-Ideal Transfer Characteristic at Low Drain Voltage in
           Metal-Capped Amorphous Oxide Thin Film Transistor

    • Authors: Ji Ye Lee;Sang Yeol Lee;
      Pages: 40 - 44
      Abstract: Issues of amorphous oxide semiconductors (AOSs) thin-film transistors (TFTs) mainly focus on improving electrical performance and stability. Currently, the hump, the abnormal transfer characteristic, is also an essential factor of AOSs TFT. The hump phenomenon was observed for AOS-TFTs with a metal capping (MC) layer under various measurement conditions. The mobility in the MC TFT was improved from 14.8 cm2/Vs to 19.2 cm2/Vs compared to that of the conventional TFTs. The improved electrical characteristics in the MC structure are representative of the carrier injection effect and the change of the current path. This reason reveals that the MC structure has a hump phenomenon under the low drain to source voltage ( $V_{DS}$ ). The hump characteristic does not significantly affect the overall MC TFT characteristics (transfer characteristic, improved electrical characteristics through MC structure, etc.). In addition, it was confirmed that it exhibits very stable hump characteristics through repeated measurements and uniformity. It was found that two current paths are formed mainly due to carrier injection from the metal capping layer in the hump phenomenon observed at low $V_{DS}$ . These divided current paths can lead to two on-currents ( $I_{on}$ ) in the transfer curve. Many studies have recently been conducted to fabricate semiconductor devices with multi-values such as 0, 1, and 2. This divided current path could propose a simple method to achieve multi-values with an easy process.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Performance Improvement by Double-Layer a-IGZO TFTs With a Top Barrier

    • Authors: Jih-Chao Chiu;Song-Ling Li;Ming-Xuan Lee;Chia-Chun Yen;Tsang-Long Chen;Cheng-Hsu Chou;C. W. Liu;
      Pages: 45 - 50
      Abstract: The double-layer a-IGZO thin film transistors (DL-TFTs) using a quantum well channel and a top barrier can reduce the subthreshold swing and hysteresis by 0.73 $times$ and 0.13 $times$ , respectively, in the transfer characteristics using the bottom gate sweep as compared to the single-layer TFTs (SL-TFTs). The wide bandgap barrier on top of the narrow bandgap IGZO channel serves as a protection layer between the IGZO channel and the SiO2 top gate insulator to prevent plasma-induced damage on the IGZO channel caused by the S/D metal etching and the top gate insulator deposition. As for the mobility using the bottom gate operation with the top gate grounded, the DL-TFTs show higher mobility (1.06 $times$ ) at the room temperature due to less Coulomb scattering caused by the plasma-induced damage for percolation conduction, while the SL-TFTs have higher mobility at low temperatures due to the improved hopping efficiency for thermally activated hopping. The hysteresis is temperature independent down to 160 K, indicating the electrons tunneling between the channel and the top gate insulator is dominant. As for the reliability, DL-TFT has a smaller Vth shift than SL-TFT under both positive bias temperature stress (PBTS) due to less subgap defect in the channel.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Low Power and IR Drop Compensable AMOLED Pixel Circuit Based on
           Low-Temperature Poly-Si and Oxide (LTPO) TFTs Hybrid Technology

    • Authors: Hezi Qiu;Junjun An;Kun Wang;Congwei Liao;Chao Dai;Xin Zhang;Shengdong Zhang;
      Pages: 51 - 58
      Abstract: In this paper, an AMOLED pixel circuit based on low-temperature poly-crystalline silicon and oxide (LTPO) thin-film transistors (TFTs) hybrid technology is proposed, which features only two transistors in a serial connection with OLED. The power supply can thus be reduced by $25{sim }30$ % in the “Always-on-Display” (AOD) mode compared with the earlier LTPO pixel circuits which usually have three transistors in the current path and need a higher supply voltage. Furthermore, in addition to a strong suppressing ability to $text{V}_{mathrm{ th}}$ variations/shift, the proposed pixel circuit has an excellent compensation ability for current-resistance voltage drops (i.e., IR drop), which is also superior to the earlier LTPO ones where the IR drop has to be compensated externally. Therefore, the proposed LTPO pixel circuit is able to provide AMOLED displays with lower power consumption and higher display performance than the earlier ones.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Study of Current Collapse Behaviors of Dual-Gate AlGaN/GaN HEMTs on Si

    • Authors: Dai-Jie Lin;Jhih-Yuan Yang;Chih-Kang Chang;Jian-Jang Huang;
      Pages: 59 - 64
      Abstract: Surface traps on GaN-based HEMTs (high-electron-mobility transistors) usually result in the increase of channel on-resistance. It becomes worsen when short pulses are applied during high-frequency and high voltage switching. Here we present a dual-gate transistor structure to suppress the dynamic on-resistance increase. The auxiliary gate under a proper fixed voltage is able to induce additional electrons to compensate the channel carrier loss during main gate switching, leading to a lower dynamic on-resistance. In this work, we benchmarked the fundamental electrical properties of both single-gate and dual-gate HEMTs. We further extracted the dynamic electrical properties by stressing the devices with short pulses. The results suggest a significant mitigation of current collapse of a dual-gate HEMT under a proper bias applied on the auxiliary gate electrode. The physical mechanism based on the charge distribution in the channel is employed to explain the observations.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Mitigating DIBL and Short-Channel Effects for III-V FinFETs With
           Negative-Capacitance Effects

    • Authors: Shih-En Huang;Wei-Xiang You;Pin Su;
      Pages: 65 - 71
      Abstract: This paper, based on the IRDS 2022 technology node, investigates the DIBL and short-channel effects for InGaAs negative-capacitance FinFETs (NC-FinFETs) through a theoretical subthreshold drain current model considering key effects including negative capacitance, quantum confinement and source-to-drain tunneling. Due to the impact of negative capacitance on the source-to-drain potential profile, tunneling distance and its drain-bias dependence, the short-channel effects can be substantially improved for InGaAs NC-FinFETs. Our study indicates that, with the larger NC effect of the III-V channel, the gap in DIBL and subthreshold swing between InGaAs and Si FinFETs in the sub-20 nm gate-length regime can become much closer. Our study may provide insights for future supply-voltage/power scaling of logic devices with high-mobility channel.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Ultrathin MoS₂-Channel FeFET Memory With Enhanced Ferroelectricity in
           HfZrO₂ and Body-Potential Control

    • Authors: Jiawen Xiang;Wen Hsin Chang;Takuya Saraya;Toshiro Hiramoto;Toshifumi Irisawa;Masaharu Kobayashi;
      Pages: 72 - 77
      Abstract: We have experimentally demonstrated memory operation of a HfO2-based ferroelectric FET (FeFET) with an ultrathin MoS2 channel and bottom-gate structure. ZrO2 seed layer enhances ferroelectricity in HfZrO2 by post deposition anneal process. Surface passivation of a MoS2 layer reduces the instability of the transistor characteristics. An additional top gate effectively controls the body potential instead of floating body. Thereby, FeFET memory operation was realized with enhanced ferroelectricity and body-potential control. By using pulse write operation, the ultrathin MoS2 channel FeFET showed the memory window of 0.22V, the retention time >5000 seconds, and the endurance cycles were $> 10^{6}$ times. This work highlights the applicability of the device for high-density memory such as 3D FeFET.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS
           With Nanosheet FET

    • Authors: Seung-Geun Jung;Dongwon Jang;Seong-Ji Min;Euyjin Park;Hyun-Yong Yu;
      Pages: 78 - 82
      Abstract: For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by ~2.3% in iso-power and decrease power by ~7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by ~55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (Ceff) of the CFET compared to the standard CMOS. This low Ceff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With
           Double Trench Gate and VLD Technique

    • Authors: Moufu Kong;Zewei Hu;Jiacheng Gao;Zongqi Chen;Bingke Zhang;Hongqiang Yang;
      Pages: 83 - 88
      Abstract: An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance ( ${R} _{mathrm{ on,sp}}$ ). Numerical Simulation results show that the ${R} _{mathrm{ on,sp}}$ of the proposed SiC LDMOS is 3.5 $text{m}boldsymbol{Omega }cdot {mathrm{ cm}}^{2}$ with a breakdown voltage of ~1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a ${R} _{mathrm{ on,sp}}$ of 6.6 $text{m}boldsymbol{Omega }cdot {mathrm{ cm}}^{2}$ and a breakdown voltage of ~1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the ${R} _{mathrm{ on,sp}}$ and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Wide Bandgap Vertical kV-Class β-Ga₂O₃/GaN Heterojunction p-n Power
           Diodes With Mesa Edge Termination

    • Authors: Dinusha Herath Mudiyanselage;Dawei Wang;Houqiang Fu;
      Pages: 89 - 97
      Abstract: Breakdown capability of ${beta }$ -Ga2O3/GaN heterojunction-based vertical p-n power diodes with mesa edge termination (ET) was comprehensively investigated using TCAD simulation. With $5~{mu }text{m}~{beta }$ -Ga2O3 drift layer, the ideal breakdown voltage (BV) of the heterojunction was 1.37 kV, while the BV of the reference device without effective mesa edge termination decreased dramatically to 300 V due to the electric field crowding at the device edge. Four mesa ET structures were investigated to mitigate the electric field crowding at the junction edge, including beveled mesa, step mesa, deeply etched mesa, and p-doped guard ring. Without effective ET, the peak electric field at the junction edge was ~4.2 MV/cm at −300 V. By incorporating these ET techniques, the peak electric fields were reduced significantly to 0.73 MV/cm. Ideal BV of 1.37 kV was achievable using deeply etched mesa and guard ring ETs. The beveled mesa realized >80% of the ideal BV, while step mesa ET was less effective in alleviating the electric field crowding and only offered ~ 40% of the ideal BV. The device BV can be further scaled by varying $beta $ -Ga2O3 drift layer thickness. This work can serve as an important reference and guideline for developing high power high voltage $beta $ -Ga2O3 based bipolar power devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND
           Flash Memory

    • Authors: Zhichao Du;Zhipeng Dong;Kaikai You;Xinlei Jia;Ye Tian;Yu Wang;Zhaochun Yang;Xiang Fu;Fei Liu;Qi Wang;Lei Jin;Zongliang Huo;
      Pages: 98 - 103
      Abstract: Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the program suspend command is issued during the program stage, and particularly, they become more obvious as the delay time between program suspend operation and other following operations exceeds tens of milliseconds. By analyzing the waveform of conventional program suspend scheme, it is suggested that the unexpected extra read fail bits are caused by the different occupancy of grain boundary traps (GBTs) in the polycrystalline silicon (poly-Si) channel during the idle time after the program suspend operation. Accordingly, a novel program suspend scheme is proposed by adding a “stabilizing” pulse immediately after the program stage. Silicon experimental data show that the proposed scheme can effectively limit the read fail bit count (FBC) to a normal range, thus improving the reliability of 3D NAND flash memory significantly.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Analysis of Residual Stresses Induced in the Confined 3D NAND Flash Memory
           Structure for Process Optimization

    • Authors: Eun-Kyeong Jang;Ik-Jyae Kim;Cheon An Lee;Chiweon Yoon;Jang-Sik Lee;
      Pages: 104 - 108
      Abstract: In flash memory technology, mechanical stress is considered as one of the major factors that can influence the device performance. Furthermore, mechanical stress can have a greater impact on the electrical performance in 3D NAND than in 2D NAND because 3D NAND has a confined structure. Thus, the mechanical stress and its influence on the 3D NAND need to be investigated. In this study, we simulated the 3D NAND flash to quantify how deposition temperatures of components influenced residual stress and electrical characteristics. The stress distribution and electrical characteristics of the channel were shown to depend on the deposition temperatures of the poly-Si channel, charge trap nitride, tunneling oxide, and tungsten word line in technology computer-aided design simulations. Also, the relationship between residual stress and electrical characteristics was investigated and described using the energy band shift due to residual stress. These results have a potential to improve the cell performances and optimize process parameters in 3D NAND flash process technology.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Impacts of Pulsing Schemes on the Endurance of Ferroelectric
           Metal–Ferroelectric–Insulator–Semiconductor Capacitors

    • Authors: Cheng-Hung Wu;Nicolo’ Ronchi;Kuan-Chi Wang;Yu-Yun Wang;Sean Mcmitchell;Kaustuv Banerjee;Geert van Den Bosch;Jan van Houdt;Tian-Li Wu;
      Pages: 109 - 114
      Abstract: In this work, the impacts of various pulsing schemes on endurance are comprehensively investigated. Trapezoidal and triangular waveforms are considered in endurance cycling tests. For endurance cycling with the trapezoidal waveforms, different rising time (Tr)/falling time (Tf), e.g., 0.05– $5 mu text{s}$ , with a fixed pulse width (Twidth) and different pulse width (Twidth), i.e., 0- $10 mu text{s}$ , with fixed rising time (Tr)/falling time (Tf) are used. As for the endurance cycling with the triangular waveforms, the frequencies are ranged from 1 kHz to 1 MHz. The results indicate that a shorter rising time (Tr)/falling time (Tf) results in a completely different endurance characteristic, and a longer Twidth leads to an earlier breakdown. Furthermore, the higher frequency of the triangular waveform results in a larger remnant polarization (2Pr) after endurance cycling. Overall, the endurance is highly dependent on the pulsing schemes, suggesting that a standardized methodology for the endurance evaluation is necessary for fair benchmarks and qualification of the ferroelectric-based technologies.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With
           Gate Stack Engineering and Compact Long-Term Retention Model

    • Authors: Fei Mo;Jiawen Xiang;Xiaoran Mei;Yoshiki Sawabe;Takuya Saraya;Toshiro Hiramoto;Chun-Jung Su;Vita Pi-Ho Hu;Masaharu Kobayashi;
      Pages: 115 - 122
      Abstract: We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL) current in erase operation of FeFETs with a floating body. We also introduced a novel gate stack process for low voltage operation by inserting a Ti layer in the metal gate. The Ti layer insertion can suppress the growth of an interfacial layer (IL) by controlling oxygen intrusion into the IL during the rapid thermal anneal (RTA) process. We demonstrated an efficient erase operation at shorter and lower pulse voltage with GIDL current in the overlap structure than in the underlap structure. A compact FeFET retention model is developed based on the surface-potential based FET model, the nucleation-limited-switching (NLS) model, and the retention model of ferroelectric (FE) capacitor. Faster degradation of the program state observed in the experiment can be explained by electron detrapping according to the modeling and simulation.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Statistical Study of Degradation of Flexible Poly-Si TFTs Under Dynamic
           Bending Stress

    • Authors: Bin Li;Wenjuan Zhou;Yang Hu;Mengjun Du;Mingxiang Wang;Dongli Zhang;Huaisheng Wang;
      Pages: 123 - 128
      Abstract: Degradation of flexible low-temperature poly-Si thin film transistors (TFTs) under dynamic bending cycles is investigated with statistical method. $I_{mathrm{ ON}}$ degradation data of different bending cycles and bending conditions are compared to five different statistical distribution models, and it is determined that the Gamma distribution best fits degradation data. Based on the model, the reliability of TFTs under a given stress condition can be evaluated under two typical application scenarios: (1) reliability prediction for large bending cycles; (2) reliability evaluation based on stress test with limited sample size.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

    • Authors: Tianshi Liu;Hua Zhang;Sundar Babu Isukapati;Emran Ashik;Adam J. Morgan;Bongmook Lee;Woongje Sung;Ayman Fayed;Marvin H. White;Anant K. Agarwal;
      Pages: 129 - 138
      Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • DFT Investigation on Targeted Gas Molecules Based on Zigzag GaN
           Nanoribbons for Nano Sensors

    • Authors: Mandar Jatkar;Kamal K. Jha;Sarat K. Patra;
      Pages: 139 - 145
      Abstract: In the present investigation, we studied the structural stability and electronic properties of bare and various adsorbed gas molecules ZGaNNR-2, ZGaNNR-4 and ZGaNNR-6 configurations. The electronic properties of all considered ZGaNNR configurations exhibit the metallic behaviour and it is verified through their band structures and densities of states. Based on binding energy/adsorption calculations, Bare-ZGaNNR-6 and O2-ZGaNNR-6 configurations found the most thermostatic stable and energetically favoured configurations among all other considered ZGaNNRs. In transmission spectra, many distinct conductive states are observed in case of CO2-ZGaNNR-6. The selectivity of CO2/O2 ZGaNNR has emerged as the most preferred (24.6) one among all considered configurations. CO2-ZGaNNR-6 is emerged as the fast sensing device due to the lower recovery time (0.14 sec). The proposed device proves the high sensing capability towards the nano-scale devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Comparison of Short-Circuit Safe Operating Areas Between the Conventional
           Field-Stop IGBT and the Superjunction Field-Stop IGBT

    • Authors: Zhihao Wang;Zhi Lin;Wei Zeng;Shengdong Hu;Jianlin Zhou;
      Pages: 146 - 151
      Abstract: This paper studies the short-circuit safe operating area (SCSOA) of the conventional field-stop (FS) IGBT and the superjunction (SJ) FS IGBT, based on 1200 V-rated samples, with the help of numerical electrothermal simulations. The results show that the peak electric field influences the distribution of the temperature inside devices and plays a crucial role in determining their SCSOAs. When the doping concentration of the collector, $text{N}_{mathrm{ C}}$ , is low, the peak electric field exits near the collector. Both types of IGBTs have a long short-circuit time, $text{T}_{mathrm{ SC}}$ , which can exceed $15~{mathrm {mu }}text{s}$ . $text{T}_{mathrm{ SC}}$ decreases with the increase of $text{N}_{mathrm{ C}}$ because the peak electric field transfers to near the channel. The introduction of the SJ structure weakens the peak electric field and increases $text{T}_{mathrm{ SC}}$ . The difference is at least 4 $mu text{s}$ and up to 6.87 $mu text{s}$ , when $text{N}_{mathrm{ C}}$ ranges from 2.0 $times ,,10^{17}$ cm $^{-3}$ to 1.1 $times ,,10^{18}$ cm $^{-3}$ . Besides, $text{T}_{mathrm{ SC}}$ of the SJ IGBT can be increased by using highly-doped pillars.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Compact Millimeter-Wave On-Chip Dual-Band Bandpass Filter in 0.15-μm GaAs

    • Authors: Kai-Da Xu;Shengpei Xia;Yannan Jiang;Ying-Jiang Guo;Yiqun Liu;Rui Wu;Jianlei Cui;Qiang Chen;
      Pages: 152 - 156
      Abstract: A compact on-chip dual-band bandpass filter (BPF) at millimeter-wave frequencies is proposed in 0.15- ${mu }text{m}$ GaAs technology. To understand the working mechanism of the BPF, an LC equivalent circuit model is presented and analyzed for position estimation of the transmission zeros and poles. For demonstration, an on-chip BPF example is fabricated and tested, whose simulation and measurement are in good agreement. There are two frequency bands at 60.2 and 79.7 GHz with bandwidths of 9% and 6.8%, respectively. The chip, excluding the feedings, is only 0.304 mm $times0.464$ mm.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Fabrication and Characterization of 2-Bit per Capacitor as Functional
           Structures for Physical Unclonable Function Circuits

    • Authors: J. Biba;S. Boche;U. Goßner;W. Hansch;
      Pages: 157 - 168
      Abstract: Currently, security issues for semiconductor chips are counterfeiting and night shift problems. These factors might lead to insecure supply chains in the automotive industry. This can be avoided by using coating Physical Unclonable Functions (PUFs). The coating can be applied to every semiconductor chip in order to create a unique fingerprint. In this work, a 2-bit key per capacitor for Physical Unclonable Functions is presented for the first time. For this reason, 49 chips on a wafer with 195 metal oxide semiconductor (MOS) capacitors were fabricated. A large and random fluctuation of the capacitances was achieved by using a self-developed layer, which consisted of aluminum particles and spin-on glass. Due to the random variation in size and change in distribution of the particles, the fluctuation of capacitance varied from chip to chip and from wafer to wafer. The achieved large range in capacitance was used to create a 390-bit string out of 195 capacitors. Although the length of the bit string was doubled, the area of the structure remained constant. This led to a more secure PUF with a low error rate of 0.21% and an inter-chip Hamming distance (HDinter) of 49%.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power
           Integrated Circuits

    • Authors: Adrian Bojita;Marius Purcar;Dan Simon;Ciprian Florea;Cristian Boianceanu;Vasile Topa;
      Pages: 169 - 179
      Abstract: During development of power Integrated Circuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. $10^{4}$ -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions - the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time - and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout

    • Authors: Jang-Su Hyeon;Sang-Hyeon Kim;Hyeon-June Kim;
      Pages: 180 - 187
      Abstract: This paper presents a low-power multiple-column-parallel (MCP) readout CMOS image sensor (CIS) in terms of its structural features. Because each column in an MCP unit performs analog-to-digital (A/D) conversion sequentially, the columns have their own operating periods before and after A/D conversion. Upon completion of A/D conversion in each column, a local bias control (LBC) scheme is applied using a bias circuit of a pixel source follower (SF) to minimize power consumption. In this study, the effectiveness of the proposed LBC scheme is verified for the MCP readout structure. Through simple modification of a column-biasing circuit, the prototype MCP readout CIS achieved significant power savings, which shows its applicability to low-power CIS applications. The prototype CIS was implemented using a 1P6M 0.18- $mu text{m}$ CMOS process. A maximum frame rate of 430 fps was achieved while consuming 2.38 mW of power. Compared to a conventional column driver, the proposed LBC scheme reduces the total power consumption by 29.4%, which is an overall power savings of 15%. The prototype CIS also demonstrated figures of merit of $119.1 ~mu text{V}cdot $ nJ and $8 ~mu text{V}_{mathrm{ rms}}$ /kHz.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Sub-10 nm Top Width Nanowire InGaAs Gate-All-Around MOSFETs With Improved
           Subthreshold Characteristics and Device Reliability

    • Authors: Hua-Lun Ko;Quang Ho Luc;Ping Huang;Jing-Yuan Wu;Si-Meng Chen;Nhan-Ai Tran;Heng-Tung Hsu;Edward Yi Chang;
      Pages: 188 - 191
      Abstract: In this article, sub-10 nm top width nanowire In0.53Ga0.47As gate-all-around (GAA) MOSFETs with improved subthreshold characteristics and reliability are demonstrated. These devices exhibit a significant improvement in the subthreshold performances with subthreshold swing (SS) of 70 mV/dec, drain induced barrier lowering (DIBL) of 46 mV/V, and off-current ( $text{I}_{mathrm{ off}}$ ) of $1.6 times 10^{-4} mu text{A}/mu text{m}$ for InGaAs GAA MOSFETs. Effective control of short channel effects (SCEs) is confirmed by the error bar of statistical variation analysis. Under gate bias stress, a low degradation of SS and threshold voltage ( $text{V}_{mathrm{ th}}$ ) shift has been achieved due to N2 RP treatment of the InGaAs GAA MOSFETs. The superior performance can be attributed to the strong electrostatic control and high quality of high- $kappa $ /InGaAs interface, originating from shrinking nanowire width and RP passivation effects. These results show the developed GAA MOSFET devices have good potential for future low-power high-switching speed CMOS logic applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improved Crossbar Array Architecture for Compensating Interconnection
           Resistance: Ferroelectric HZO-Based Synapse Case

    • Authors: Mingfeng Tang;Xuepeng Zhan;Jiezhi Chen;
      Pages: 192 - 196
      Abstract: In-memory computing is a promising solution to break through the conventional von Neumann bottleneck. Owing to the low-power consumption, Si fabrication compatibility and fast switching speed, the HfZrOx (HZO)-based ferroelectric devices attract attention as artificial synapses. By using crossbar architectures, artificial synapse array can greatly speed up the efficiency for neuromorphic applications. However, interconnect resistance effect will cause a serious decrease in calculation accuracy. This paper proposes a crossbar array architecture with the HZO-based ferroelectric synapses, which can restore the current distortion caused by the interconnect resistance. At the device level, the synaptic potentiation and depression behaviors are achieved by adjusting the pulse duration. For the circuit level, the interconnect resistance can be significantly compensated. In neuromorphic computing, a high accuracy rate of 96% is realized, which can be further improved with the expansion of the array size. Our results provide a step towards the development of large-scale ferroelectric HZO-based neuromorphic devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Enhancement of Breakdown Voltage in p-GaN Gate AlGaN/GaN HEMTs With a
           Stepped Hybrid GaN/AlN Buffer Layer

    • Authors: Yuan Wang;Shengdong Hu;Jingwei Guo;Hao Wu;Tao Liu;Jie Jiang;
      Pages: 197 - 202
      Abstract: A novel p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) structure with a stepped hybrid GaN/AlN buffer layer (S-HEMT) is proposed and simulated by the Sentaurus TCAD in this paper. A stepped hybrid GaN/AlN buffer layer is adopted and the step is near the interface of the gate and drain. First, the breakdown voltage (BV) of the proposed S-HEMT is significantly improved with the introduction of a stepped hybrid GaN/AlN buffer layer, which can effectively modulate the electric field distributions along the channel. Second, the AlN buffer layer below the stepped GaN buffer has a large band offset and a strong polarization, which results in a much lower leakage current and a better carrier confinement. Consequently, the BV of the proposed S-HEMT will be improved at no expense of the specific on-resistance ( ${R} _{mathrm{ on,sp}}$ ). Compared with those of the conventional p-GaN gate AlGaN/GaN HEMT on the same gate-to-drain distance of $12 ~mu text{m}$ , a higher BV of 1781 V and FOM of 0.72 GW/cm2 are obtained for the proposed S-HEMT, which are both about five times. The proposed S-HEMT exhibits the potential and advantage in high power electronic applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • High-Temperature Piezoresistance of Silicon Carbide and Gallium Nitride

    • Authors: Takaya Sugiura;Naoki Takahashi;Ryohei Sakota;Kazunori Matsuda;Nobuhiko Nakano;
      Pages: 203 - 211
      Abstract: We examine the temperature dependence of the piezoresistive coefficients of silicon carbide (SiC) and gallium nitride (GaN) crystals, which are prospective materials for high-temperature applications owing to their wide-bandgap properties. The temperature-dependent piezoresistive coefficients of these materials were obtained by modeling experimental resistance changes using thermomechanical numerical simulations. This work reports the piezoresistive coefficients of 4H-SiC and GaN at the high-temperature environments, which are still not well researched. The results revealed that the temperature dependences of piezoresistive coefficients were strongly related to the ionization energy, and a high ionization energy stabilized the values of the piezoresistive coefficients at high temperatures. Our proposed temperature modeling method helps in predicting the temperature dependence of the piezoresistive coefficient using the value at the room temperature and the ionization energy of the material, which is useful for evaluating the piezoresistive effect at different temperatures during device simulations.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Modular Integration of a Compact Ku-Band Relativistic Triaxial Klystron
           Amplifier Packaged With Permanent Magnets for High-Power Microwave

    • Authors: Yunxiao Zhou;Jinchuan Ju;Jun Zhang;Wei Zhang;Fangchao Dang;Ting Shu;Yinhao Chen;Xiaobo Deng;Faning Zhang;
      Pages: 212 - 223
      Abstract: To achieve modular integration of relativistic triaxial klystron amplifier (TKA) devices and reduce the energy consumption of the whole high-power microwave (HPM) system, a compact Ku-band TKA packaged with permanent magnets is proposed and investigated in this paper. By optimizing the electromagnetic structure and utilizing TEM mode energy coupling, the length of the uniform magnetic field area required for the Ku-band TKA is reduced from 32 cm to 19.6 cm, with a reduction rate of 39%. By utilizing the NdFeB-N50M mainly magnetized in the ${R}$ direction, a permanent magnet guiding system weighing 90 kg is proposed. Besides, the length of the uniform zone is 20 cm with a longitudinal magnetic field of 0.5 T. Verified by the PIC simulation software CHPIC, an HPM with power of 430 MW and frequency of 14.25 GHz is generated when the diode voltage, current, and the injected microwave power are 340 kV, 4.2 kA, and 15 kW, respectively. The phase jitter of the output microwave is controlled within ${pm } 5{^circ }$ , which is beneficial to the coherent power combination of modular integrated TKA devices
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • GaN-Based GAA Vertical CMOS Inverter

    • Authors: Xinke Liu;Jiaying Yang;Jian Li;Feng Lin;Bo Li;Ziyue Zhang;Wei He;Mark Huang;
      Pages: 224 - 228
      Abstract: In this work, we simulate the static and dynamic characteristics of gallium nitride (GaN)-based gate-all-around (GAA) vertical nanowire complementary metal–oxide–semiconductor (CMOS) inverter. Based on the 3-D simulator of Silvaco-TCAD, the simulated physical models and associated model parameters have been well calibrated with the reported experimental results of GaN n-channel NWFET and the simulated typical electrical parameters match the measured data. According to the simulation results, the GaN GAA vertical nanowire CMOS inverter exhibits rail-to-rail operation, low static power dissipation, large noise margins, high thermal stability and good scalability.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Low-Resistive Source/Drain Formation Using Nitrogen Plasma Treatment in
           Self-Aligned In-Ga-Zn-Sn-O Thin-Film Transistors

    • Authors: Hiroshi Tsuji;Tatsuya Takei;Mototaka Ochi;Masashi Miyakawa;Kohei Nishiyama;Yoshiki Nakajima;Mitsuru Nakata;
      Pages: 229 - 234
      Abstract: In this work, we demonstrate the effectiveness of nitrogen plasma treatment on the formation of low-resistive source/drain (S/D) in self-aligned (SA) oxide thin-film transistors (TFTs) using a high-mobility oxide semiconductor (OS), In-Ga-Zn-Sn-O (IGZTO). The nitrogen plasma treatment was more effective at reducing the sheet resistance ( ${R} _{mathrm{ sheet}}$ ) of IGZTO films than the commonly used argon plasma treatment. Furthermore, ${R} _{mathrm{ sheet}}$ for nitrogen-plasma-treated IGZTO films remained low, even when the RF power and radiation time during the plasma treatment were increased when the minimum ${R} _{mathrm{ sheet}}$ was achieved. The same trends were also observed in OS films with different compositions, such as In-Ga-Zn-O and In-Sn-Zn-O. These results indicate that nitrogen plasma treatment is effective for achieving a reduction of ${R} _{mathrm{ sheet}}$ for various OS films with a wide process window regarding plasma processing parameters. The advantages could be attributed to the smaller sputtering effect on the OS films due to the lower mass of nitrogen ions than argon ions, which was verified by X-ray reflectivity and X-ray photoelectron spectroscopy analyses. For further validation, SA IGZTO TFTs with a channel length ( ${L}$ ) of 3 to 100 $mu text{m}$ were fabricated with nitrogen or argon plasma treatment. The width-normalized parasitic SD resistance ( $R_{mathrm{ SD}} {W}$ ) with the nitrogen plasma treatment was determined to be 11-3 $Omega cdot $ cm, which was ca. 40% lower than that with the argon plasma treatment. This improvement in $R_{mathrm{ SD}} {W}$ resulted in higher mobility ( $mu $ ) in the nitrogen-plasma-treated SA IGZTO TFTs. A nitrogen-plasma-treated SA IGZTO TFT with $L=10,,mu text{m}$ exhibited a high $mu $ of 27.2 cm2/Vs.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Piston-Mode pMUT With Mass Load

    • Authors: Lei Wang;Jie Zhou;Wei Zhu;Zhipeng Wu;Wenjuan Liu;Chengliang Sun;
      Pages: 235 - 244
      Abstract: This paper proposes a novel piezoelectric micromachined ultrasonic transducer (pMUT) with a proof mass under the central circular diaphragm to enhance transmission efficiency and fractional bandwidth (FBW) in liquid-coupled operation. Compared with the traditional pMUT, the proposed pMUT has advantages: (1) the resonance frequency of pMUT can be adjusted by proof mass; (2) a large ratio of third-order resonance frequency to first-order resonance frequency can be obtained by an additional proof mass under the circular diaphragm; (3) the mode shape of proposed pMUT changes from Gaussian-like to piston-like, which enables higher transmission sensitivity; (4) the FBW can be improved through a trade-off design. The characteristics of resonance frequency, output power, and FBW of pMUT with different proof mass are analyzed with a piezoelectric layer of $1~mu text{m}$ and a structural layer of 5 $mu text{m}$ . In this work, the far-field sound pressure is 240.5 Pa/V in water, 49.5 Pa/V higher than the traditional pMUT, benefiting from the piston diaphragm movement. Furthermore, a 23% −6 dB FBW in water is demonstrated by theoretical analysis and parameter optimization. This work provides constructive advice for pMUT for better performance of transmission and resolution.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic

    • Authors: Aditi Agarwal;B. J. Baliga;
      Pages: 245 - 255
      Abstract: Significant impact of the ion-implant straggle of the P+ shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modeling. The P+ region ion-implant straggle not only reduces the JFET width but increases the channel length. This combination is shown to displace a SiC power MOSFET structure optimized without ion-implant straggle away from the optimum JFET width required to achieve the lowest specific on-resistance, resulting in an increase in the specific on-resistance by a factor of 2-3x for the typically used JFET width of $0.7 mu text{m}$ . The theoretical analysis is supported by data measured on 1.2 kV SiC power MOSFETs fabricated with channel lengths of 0.3 and $0.5 mu text{m}$ using both accumulation and inversion mode channels. The presence of the P+ shielding region ion-implant straggle is shown to: (a) increase specific on-resistance by 15-30%; (b) suppress short-channel effects; (c) reduce electric field in the gate oxide; (d) reduce the transconductance; (e) reduce saturated drain current; and (f) significantly reduce the gate-drain capacitance and gate charge. Impact of P+ shielding region lateral straggle on device cell optimization is an important contribution of this paper.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • AM Mini-LED Backlight Driving Circuit Using PWM Method With Power-Saving

    • Authors: Chih-Lung Lin;Yi-Chien Chen;Jui-Hung Chang;Yu-Sheng Lin;Sung-Chun Chen;Ming-Hsien Lee;Chun-Yen Chang;
      Pages: 256 - 262
      Abstract: This paper proposes a mini-light-emitting diode (mini-LED) driving circuit that is driven by pulse width modulation (PWM) for the backlights of active-matrix (AM) liquid crystal displays (LCDs). The proposed circuit compensates for threshold voltage (VTH) variations of low-temperature poly-crystalline silicon thin-film transistors (LTPS TFTs) and the current-resistance (I-R) rise in VSS lines to supply a stable driving current. Operating the mini-LED at the high luminous efficacy by the PWM driving method and setting only the driving TFT on the path of the driving current reduce the power consumption of the backlight. Based on a 2.89-inch LCD panel with an AMLED $48times48$ backlit module, the TFTs are fabricated, measured, and fitted. Simulation results show that the relative current error rates are all below 4.67% when the VTH of the driving TFT varies by ±0.3 V and the VSS rises by 0.5 V. The voltage across VDD and VSS of the proposed circuit is 4.5 V lower than that of the 6T1C compensating driving circuit, so the power consumption of the circuit is at least 27.05% lower. Therefore, the proposed driving circuit is well suitable to use in mini-LED backlit LCDs.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Self-Aligned Transparent-Gate ITO/Germanium

    • Authors: Po-Yu Hong;Bing-Ju Lee;Rong-Zong Yang;Horng-Chih Lin;Pei-Wen Li;
      Pages: 263 - 268
      Abstract: We report experimental fabrication and characterization of photoMOSFETs with self-aligned gate-stacking heterostructures of indium-tin-oxide (ITO)/Ge nanospheres/SiO2-shell/Si1-xGex-nanosheets. Array of Ge-nanosphere/SiO2-shell/SiGe-nanosheet heterostructures was created in a self-organized, CMOS approach using the thermal oxidation of lithographically-patterned poly-Si0.85Ge0.15 nanopillars over buffer layers of Si3N4 on top of SOI substrates. With a polysilicon dummy-gate, source and drain self-align with the transparent ITO gate using a replacement-metal-gate process. Very high photocurrent gain, large photoresponsivity, as well as improved input capacitance and 3dB frequency were experimentally achievable in our photoMOSFETs. The pivotal roles of Ge-optical gate and SiGe-channel for large photoresponsivity and current gains were analyzed via numerical simulation.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Analog Read Noise and Quantizer Threshold Estimation From Quanta Image
           Sensor Bit Density

    • Authors: Eric R. Fossum;
      Pages: 269 - 274
      Abstract: Estimation of the analog read noise level and quantizer threshold level to within a few hundredths of an electron can be obtained by measuring the output bit density, D, of a single-bit quanta image sensor (1bQIS) as a function of quanta exposure, H. Analysis of the D-H characteristics as a function of read noise and quantizer threshold levels is performed and a procedure for extraction of estimated read noise and quantizer threshold is suggested and demonstrated.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Transparent Floating Gate Memory Based on ZnO Thin Film Transistor With
           Controllable Memory Window

    • Authors: Ning Zhang;Wanpeng Zhao;Xinyu Zhang;Yang Liu;Shurong Dong;Jikui Luo;Zhi Ye;
      Pages: 275 - 280
      Abstract: The transparent floating gate memory based on zinc oxide (ZnO) thin film transistors (TFTs) was fabricated by using one-step atom layer deposition of aluminia tunneling and ZnO charge-trap layers. Free electrons trapping mechanism of this memory device is proposed after systematical investigation of gate voltage scanning and thickness of the trapping layer. Furthermore, the relationship between the geometrical size of the charge-trapping layer and the memory window is explored. The devices with different memory windows can be controlled simply by designing the area of their trapping layer without any external process, which is much beneficial to the low cost process fabrication of the memory array and driving circuits, since the memory and switch/digital transistors can be fabricated at the same time. Finally, the presented TFT memory exhibits a maximum memory window of 15 V, excellent fatigue and retention properties more than 30,000 s without any charge loss. The transparent floating gate memory with the ZnO charge-trap layer has great potential for application of 3D, transparent or multi-value memory.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Significance of Overdrive Voltage in the Analysis of Short-Channel
           Behaviors of n-FinFET Devices

    • Authors: Yi-Chuen Eng;Luke Hu;Tzu-Feng Chang;Chih-Yi Wang;Steven Hsu;Osbert Cheng;Chien-Ting Lin;Yu-Shiang Lin;Zen-Jay Tsai;Chih-Wei Yang;Jim Lu;Steve Yi-Wen Chen;
      Pages: 281 - 288
      Abstract: The short–channel behaviors of n–channel (electron–conducting) fin field–effect transistors (n–FinFETs) set at different threshold voltages were analyzed at different power supply voltages. Interesting observations were made by considering the on and off voltage states of the overdrive voltage instead of the gate–source voltage. Intrinsic transistor characteristics were revealed, enabling the comparison of short–channel characteristics between devices designed for different threshold voltages. Drain–induced barrier lowering (DIBL), subthreshold swing (SS), on/off current ratio, $text{I}_{mathrm{ on}}/text{I}_{mathrm{ off}}$ , and other parameters of the devices were considered. In addition, the novel figure of merit introduced in our previous work for the evaluation of short–channel effects, which accounts for the DIBL, SS, and $text{I}_{mathrm{ on}}/text{I}_{mathrm{ off}}$ of the devices, was also analyzed under this context. It was shown that the off–state current does not increase significantly with the increase in the supply voltage, indicating good gate control.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Temperature-Dependent Narrow Width Effects of 28-nm CMOS Transistors for
           Cold Electronics

    • Authors: Ting Tsai;Horng-Chih Lin;Pei-Wen Li;
      Pages: 289 - 296
      Abstract: We reported temperature-dependent narrow width effects on electrical characteristics of 28-nm CMOS transistors measured at temperature of 77 K-300 K. At cryogenic temperatures, P-MOSFETs appear to have stronger temperature-induced threshold voltage ( $V_{mathrm{ th}}$ ) increase and subthreshold swing (SS) reduction than N-MOSFETs, whereas the improvement in drain-induced barrier lowering (DIBL) is more evident in N-MOSFETs. N-MOSFETs show typical reverse narrow effect (RNWEs) in terms of $V_{mathrm{ th}}$ roll-off along with SS rise-up with narrowing channel-widths ( $W_{mathrm{ G}}$ ). In contrast, P-MOSFETs exhibit anomalous RNWE, that is, $V_{mathrm{ th}}$ (SS) decreases (increases) with decreasing $W_{mathrm{ G}}$ from 3 $mu text{m}$ to 0.6 $mu text{m}$ and reversely increases (decreases) with further narrowing to 0.3 $mu text{m}$ . RNWEs on N-MOSFETs are clearly suppressed at cryogenic temperatures, whereas P-MOSFETs appear to have enhanced anomalous RNWEs in terms of $V_{mathrm{ th}}$ and DIBL variations at 77 K.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Bias-Dependence of Electroluminescence in AlGaN/GaN High-Electron-Mobility
           Transistors on SiC Substrate

    • Authors: Qiang Ma;Shiyo Urano;Atsushi Tanaka;Yuji Ando;Akio Wakejima;
      Pages: 297 - 300
      Abstract: This paper investigates bias-dependence of electroluminescence (EL) in an AlGaN/GaN HEMT fabricated on a SiC substrate. The HEMT exhibited a low-intensity reddish EL at the gate electrode at a drain voltage (Vds) of 30 V, which was confirmed with combination of a top-side view using a CMOS sensor camera and a back-side view using a silicon-intensified CCD. As Vds was increased to 48 V, color change from low-intensity red to high-intensity white was accompanied with shift of the location from the gate to the drain edge. The changes in the EL are attributed to a shift of the high electric field from the gate to the drain electrode and a concentration of electric field near the drain edge.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Mobility Enhancement and Abnormal Humps in Top-Gate Self-Aligned
           Double-Layer Amorphous InGaZnO TFTs

    • Authors: Ming-Xuan Lee;Jih-Chao Chiu;Song-Ling Li;Eknath Sarkar;Yu-Ciao Chen;Chia-Chun Yen;Tsang-Long Chen;Cheng-Hsu Chou;C. W. Liu;
      Pages: 301 - 308
      Abstract: The mobility enhancement and the positive bias stress of top-gate self-aligned TFTs using the a-IGZO channel with a front barrier are investigated. The a-IGZO front barrier can keep electrons in the a-IGZO channel away from the top-gate oxide to significantly enhance the electron mobility at the top gate operation. The parasitic channel induces a hump in the transfer characteristics. The positive bias stress shifts the hump to the negative voltage abnormally. The H2O in the polymer film on array layer is responsible for the abnormal shift. The H2O diffuses into the top-gate insulator and is electrolyzed to create H+, which forms a parasitic channel with a negative shift of threshold voltage, leading to the abnormal hump. The abnormal humps are increasingly significant with the increasing channel width and the decreasing channel length. The channel width dependence on positive bias stress is due to the inverse narrow width effect caused by the fringe electric field. The channel length dependence on positive bias stress is due to the H+ diffusion toward the center of the parasitic channel from both the source and drain sides.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • The Noise Behavior of Gap-Type Amorphous Silicon TFT Under Illumination

    • Authors: Ya-Hsiang Tai;Yi-Cheng Yuan;Cheng-Che Tu;Pin-Chun Wang;
      Pages: 309 - 312
      Abstract: Gap-type amorphous silicon (a-Si) thin-film transistor (TFT) used as photo sensor has been reported in previous literature. However, the noise behavior of gap-type a-Si TFT is not inspected yet. Therefore, we investigate the noise response of the gap-type a-Si TFT under illumination in this paper. We compare the difference between the results of the gap-type and the conventional-type TFTs. In addition, we analyze it including the perspectives of power spectrum, integral power spectrum, Hooge parameter, fluctuate slope. Finally, we explain the reason for its fluctuate slope transition and review the correlation between noise behavior and photo effect mechanism.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Hybrid Junction Termination Consisting of a Variation Lateral Doping
           Structure and a Spiral Polysilicon Resistive Field Plate

    • Authors: Zhi Lin;Wei Zeng;Zhihao Wang;
      Pages: 313 - 317
      Abstract: A hybrid junction termination structure consisting of a variation lateral doping (VLD) region and a spiral polysilicon resistive field plate (PRFP) is proposed in this brief. Surface electric fields of the VLD region are modulated by the PRFP and distribute more uniformly. Compared with the conventional VLD structure with the same size, its measured breakdown voltage increases by 11%. The breakdown voltage still has a positive temperature coefficient. And, the leakage current changes very little from −40 to 150 °C. Besides, it is more immune to the deviation of the VLD dosage. The deviation range of the VLD dosage increase from −20% - +20% to −50% - +60% when the breakdown voltage keeps above 90% of the maximum value. No extra masks or process steps are needed in power devices with a MOS gate structure, because the gate layer can be used to implement the spiral PRFP. At last, the hybrid termination is not detrimental to the switching characteristic of the device.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • AlGaN/GaN Schottky Barrier Diodes on Free-Standing GaN Substrates With a
           Si Doped Barrier Layer

    • Authors: Taofei Pu;Hsiang-Chun Wang;Kuang-Po Hsueh;Hsien-Chin Chiu;Xinke Liu;
      Pages: 318 - 323
      Abstract: This paper presented a AlGaN/GaN Schottky barrier diodes (SBDs) on free-standing GaN substrates with a Si doped barrier layer were fabricated for high power application. Compared with the conventional SBDs, the SBDs with doped barrier layer have the lower turn-on voltage ( $V_{ON}$ ) and specific on resistance (RON_SP) because more free carriers are induced in two-dimensional electron gas (2DEG) channel. With Si doping concentration of $1 times 10^{20}$ cm−3 for AlGaN barrier layer, the SBDs demonstrate RON_SP of 0.12 m $Omega cdot mathrm{cm^{2}}$ , $V_{ON}$ of 0.41 V, breakdown voltage of 339 V, and power figure-of-merit (PFOM) of 957.6 MV/cm2, which have a great potential for high-speed power device applications. Meanwhile, the SBDs with doped barrier have a faster reverse recovery time, and a better low-frequency noise (LFN) characteristics at low current density due to high carrier mobility and less generation-recombination (G-R) noise.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Limitations to Electrical Probing of Spontaneous Polarization in
           Ferroelectric-Dielectric Heterostructures

    • Authors: Mattia Segatto;Riccardo Fontanini;Francesco Driussi;Daniel Lizzit;David Esseni;
      Pages: 324 - 333
      Abstract: An accurate estimate of the ferroelectric polarization in ferroelectric-dielectric stacks is important from a materials science perspective, and it is also crucial for the development of ferroelectric based electron devices. This paper revisits the theory and application of the PUND technique in Metal-Ferroelectric-Dielectric-Metal (MFDM) structures by using analytical derivations and numerical simulations. In an MFDM structure the results of the PUND technique may largely differ from the polarization actually switched in the stack, which in turn is different from the remnant polarization of the underlying ferroelectric. The main hindrances that prevent PUND measurements from providing a good estimate of the polarization switching in MFDM stacks are thus discussed. The inspection of the involved physical quantities, not always accessible in experiments, provides a useful insight about the main sources of the errors in the PUND technique, and clarifies the delicate interplay between the depolarization field and the charge injection and trapping in MFDM stacks with a thin dielectric layer.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS
           Inverter With 3-nm Critical Feature Size Using Charge Sheet

    • Authors: Mohammad Bavir;Abdollah Abbasi;Ali Asghar Orouji;
      Pages: 334 - 340
      Abstract: In this paper, after calibrating the models and parameters used in the simulations based on experimental data, by using the opposite doping in the channel and between the gates in an asymmetric double-gate junctionless (JL) transistor with the 3nm gate length, a charge sheet (CS) was created. The results showed that, due to creating CS in the middle of the channel, the horizontal electric field was increased, thus more major carriers were depleted from the middle of the channel. With the analysis of the $text{I}_{mathrm{ DS}} - text{V}_{mathrm{ GS}}$ diagrams at different temperatures, it was concluded that in the CS JL MOSFET, while the ON-state current is very close to compared that in the JL MOSFET (same structure without CS), the drain leakage current has decreased by around 103. Furthermore, the $text{I}_{mathrm{ DS}} - text{V}_{mathrm{ DS}}$ diagram showed that the drain current in the CS JL MOSFET was much less affected by the drain voltage compared to that in the JL MOSFET. Also in AC analysis and at 1MHz frequency, by using CS the parasitic capacitances were reduced. Due to the improvement obtained in the presence of the charge sheet, the proposed structure was used in designing an inverter. The results showed that in the presence of the charge sheet, logical high input range, and logical low input range were increased, and also, noise margin low (NML) and noise margin high (NMH) were improved.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Abnormal Bias Instabilities Induced by Lateral H2O Diffusion Into Top-Gate
           Insulator of a-InGaZnO Thin-Film Transistors

    • Authors: Jiye Li;Hao Peng;Huan Yang;Xiaoliang Zhou;Lei Lu;Shengdong Zhang;
      Pages: 341 - 345
      Abstract: The environmental stability of self-aligned top-gate (SATG) a-InGaZnO thin-film transistor (TFT) was studied by performing the high-temperature high-humidity (HTHH) test. Despite the maintenance of initial electrical characteristics, the stability under positive bias stress (PBS) was considerably deteriorated, including an abnormal negative ${V} _{mathrm{ th}}$ shift ( $boldsymbol{Delta } {V} _{mathrm{ th}}$ ), increased off current, and degraded SS. Moreover, the negative ${Delta } {V} _{mathrm{ th}}$ was consistently enhanced with the channel length ( ${L}$ ) decreasing. Such ${L}$ dependence was clarified to originate from the lateral diffusion of H2O in TG insulator during HTHH tests, and the PBS instabilities were caused by the ionization and migration of H2O molecules into the a-IGZO channel, as verified by the X-ray photoelectron spectroscopy, C-V characteristics, and recovery behaviors of PBS degradation.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improving the Scalability of Ferroelectric FET Nonvolatile Memories With
           High-k Spacers

    • Authors: You-Sheng Liu;Pin Su;
      Pages: 346 - 350
      Abstract: This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer ( $text{E}_{mathrm{ IL}}$ ) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest $text{E}_{mathrm{ IL}}$ during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel $text{E}_{mathrm{ IL}}$ , and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Amorphous IGZO Thin-Film Transistor Gate Driver in Array for Ultra-Narrow
           Border Displays

    • Authors: Liufei Zhou;Xiaojun Guo;Bang Ouyang;Li’Ang Deng;Mingxin Wang;Qungang Ma;Baoping Wang;
      Pages: 351 - 355
      Abstract: A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays. In the design, each TFT in the gate driver circuits is divided into a certain number of smaller size devices, which can be placed in different subpixels. Therefore, the pixel aperture ratio loss is minimized, and uniform placement of the gate driver circuits over the pixel array area is able to be achieved. The proposed step-like repeating block structure further reduces the occupied area of the signal interconnects. A 12.4-inch fringe field switching (FFS) liquid crystal display (LCD) panel of ultra-narrow border (0.5 mm) is demonstrated with reliable operation based on this GIA design, proving its potential for practical applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Effective Suppression of Current Collapse in AlGaN/GaN HEMT With N2O
           Plasma Treatment Followed by High Temperature Annealing in N2 Ambience

    • Authors: Jingxiong Chen;Jian Qin;Wenxuan Xiao;Hong Wang;
      Pages: 356 - 360
      Abstract: We propose a high temperature annealing process in N2 ambience after N2O plasma treatment for AlGaN/GaN HEMT. The annealing process effectively improves the plasma treated surface condition and decreases the current collapse from 41.7% to 10.6%. The N2O plasma treatment is performed in a PECVD chamber and the followed high temperature annealing process is carried out at 800°C for 20min in rapid temperature annealing (RTA) system. Compared to the devices with only N2O plasma treatment, the devices with an extra high temperature annealing process perform lower surface state density (2.51E+12 cm−2eV−1, $boldsymbol{Delta }text{E}$ from 0.353 eV to 0.413 eV; 5.38E+11 cm−2, $boldsymbol{Delta }text{E}$ > 0.519 eV) and better dynamic characteristics.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and

    • Authors: Ali Saadat;Maarten L. Van de Put;Hal Edwards;William G. Vandenberghe;
      Pages: 361 - 366
      Abstract: We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on mid-voltage (30 V – 100 V) power applications. We derive an analytical relation between breakdown voltage and on-resistance to realize the ideal behavior of the drift region for an LDMOS with S-FOX. Then, we find the optimized drift doping concentration minimizing the on-resistance at a given breakdown voltage. We introduce a new figure-of-merit for the drift region of a lateral device with S-FOX. We finally verify our ideal analytical findings with numerical results modeled and simulated in a commercial Technology Computer-Aided Design (TCAD).
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Bidirectional Selector Realized Through Multilayer Tunnel Barrier

    • Authors: Dequan Dong;Huikai He;Jian Xia;Rui Yang;Xiangshui Miao;
      Pages: 367 - 372
      Abstract: The selector plays an important role in solving the leakage current issue in a large-scale memory crossbar array. Especially, the bidirectional selector has a broader application scope than the unidirectional one, since it can be connected with both unipolar and bipolar memory devices. In this letter, two engineering approaches to realize bidirectional tunneling barrier selectors were investigated: the crested barrier and variable oxide thickness (VARIOT). It is found that the selectors based on the crested barrier exhibit much higher nonlinearity and lower off-current than those fitting the VARIOT approach. The associated tunneling mechanisms have been proposed to explain the electrical properties of the crested barrier devices. The excellent multilayer barrier bidirectional selector has been realized in the ZnO/Ta2O5/ZnO stack with pA-level off current and high nonlinearity (>104). It is worth noting that the present ZnO/Ta2O5/ZnO selector shows the best performances compared with previously reported tunnel barrier selectors.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Comparative Study of Single-Event-Burnout for 4H-SiC UMOSFET

    • Authors: Ying Wang;Jian-cheng Zhou;Mao Lin;Xing-ji Li;Jian-Qun Yang;Fei Cao;
      Pages: 373 - 378
      Abstract: SiC UMOSFET is a kind of significant power device in the supply of aerospace. But it is sensitive to space radiation. In this paper, the discrepancy of SEB behavior and research of 4H-SiC UMOSFET with the different values of particle linear energy transfer (LET) are proposed and investigated by the 2D numerical simulations. And the improved MOSFET with multi-Buff was compared with the conventional UMOSFET. At last, simulation results demonstrated that under high-intensity radiation environment (high LET value heavy ion incidence), the proposed UMOSFET could increase the single-event burnout (SEB) hardness, and using the lattice temperature of device as the SEB behavior characterization of the SiC UMOSFET after heavy ion incidence is more reasonable and accurate than only using high steady-state drain current.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improved Electrical Performance of In₂O₃ Thin-Film
           Transistor by UV/Ozone Treatment

    • Authors: Han-Lin Zhao;Fei Shan;Xiao-Lin Wang;Jae-Yun Lee;Sung-Jin Kim;
      Pages: 379 - 386
      Abstract: In this work, the effect of a UV/ozone source composed of two monochromatic wavelengths of 184 nm and 254 nm irradiated upon the indium oxide film (In2O3) at the different irradiation times together with annealing at high temperature is explored. The results showed that the developed In2O3 thin-film transistors (TFTs) exposed to UV/ozone for the 40 s and annealed at 250 °C for 2 h exhibited a significantly high performance, i.e., saturation mobility of 6.1 ± 0.2 cm $^{2}/$ Vs, $text{I}_{mathrm{ on}}/text{I}_{mathrm{ off}}$ ratio of $1.4times10$ 7, low threshold voltage (1.5 ± 0.9 V), and a small subthreshold swing (0.25 V/dec). The in-depth analysis of the developed devices through electrical characteristics, surface morphology, and practical aspect of inverter function confirm that UV/ozone irradiation improves the surface trap density, thereby increasing the mobility, and eventually improves the gate-bias stress stability and time-dependent environmental stability. The current work supports the fact that UV/ozone can improve the electrical properties of In2O3 TFTs and can be used for the fabrication of cost-effective, low-temperature, and reliable electronic devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Physics-Based Analytical Channel Charge Model of
           In x Ga1-x As/In0.52Al0.48As Quantum-Well Field-Effect Transistors From
           Subthreshold to Strong Inversion Regimes

    • Authors: Hyeon-Seok Jeong;Wan-Soo Park;Hyeon-Bhin Jo;In-Geun Lee;Tae-Woo Kim;Takuya Tsutsumi;Hiroki Sugiyama;Hideaki Matsuzaki;Sung-Ho Hahm;Jae-Hak Lee;Dae-Hyun Kim;
      Pages: 387 - 396
      Abstract: This paper presents a physics-based analytical channel charge model for indium-rich InxGa1-xAs/In0.52Al0.48As quantum-well (QW) field-effect transistors (FETs) that is applicable from the subthreshold to strong inversion regimes. The model requires only seven physical/geometrical parameters, along with three transition coefficients. In the subthreshold regime, the conduction bands ( $E_{C}$ ) of all regions are flat with finite and symmetrical QW configurations. Since the Fermi–level ( $E_{F}$ ) is located far below $E_{C}$ , the two-dimensional electron-gas density ( $n_{2{-}DEG}$ ) should be minimal and can thus be approximated from Maxwell–Boltzmann statistics. In contrast, the applied gate bias lowers the $E_{C}$ of all structures in the inversion regime, yielding band-bending of an In0.52Al0.48As insulator and InxGa1-xAs QW channel. The dependency of the energy separation between $E_{F}$ and $E_{C}$ on the surface of the InxGa1-xAs QW channel upon $V_{GS}$ enables construction of the charge–voltage behaviors of InxGa1-xAs/In0.52Al0.48As QW FETs. To devel-p a unified, continuous and differentiable areal channel charge density ( $Q_{ch}$ ) model that is valid from the subthreshold to strong inversion regimes, the previously proposed inversion-layer transition function is further revised with three transition coefficients of $eta $ , $alpha $ and $beta $ in this work. To verify the proposed approach, the results of the proposed model are compared with those of not only the numerically calculated Qch from a one-dimensional (1D) Poisson–Schrödinger solver, but also the measured gate capacitance of a fabricated In0.7Ga0.3As QW metal-insulator-semiconductor FET with large gate length, yielding excellent agreement between the simulated and measured results.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Area and Thickness Scaling of NbOₓ-Based Threshold Switches for
           Oscillation Neurons

    • Authors: Hyun Wook Kim;Heebum Kang;Eunryeong Hong;Jiyong Woo;
      Pages: 397 - 401
      Abstract: The reversible transition between the on and off states of threshold switches under a constant pulse generates voltage oscillation, which can be exploited for compact neuron element in neuromorphic systems. Because the transition voltages play an important role in the oscillation behavior, area and thickness scaling analysis of NbOx-based devices is performed to identify the underlying mechanism. The threshold voltage ( $V_{th}$ ) is sensitive to the device area, indicating that the on state of the device is achieved by the local formation of a conductive phase. On the other hand, the area-independent hold voltage ( $V_{mathrm{ hold}}$ ) becomes smaller due to the higher compliance current and increased temperature ambient, which implies that spontaneous dissolution of the phase is retarded. Through HSPICE simulation, we reveal that the greater difference between $text{V}_{mathrm{ hold}}$ and $text{V}_{mathrm{ th}}$ enables a high degree of freedom of oscillation frequency modulation.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • High-Performance Field Electron Emitters Fabricated Using a Free-Standing
           Carbon Nanotube Film

    • Authors: Jun Soo Han;Sang Heon Lee;Cheol Jin Lee;
      Pages: 402 - 407
      Abstract: The carbon nanotube (CNT) field emitter was fabricated using a thin free-standing CNT film, indicating a line-shape CNT field emitter. Field emission properties of the CNT field emitter were investigated in both diode and triode configurations. The CNT field emitter showed a low turn-on electric field of 1.8 V/ $mu$ m and a high emission current of 40.3 mA, corresponding to the emission current density of 96 A/cm2 in the diode configuration. It also exhibited a high anode current of 40 mA, corresponding to the anode current density of 95.2 A/cm2 in the triode configuration. In addition, the CNT field emitter showed a good electron beam transmittance of 86.4% and excellent emission stability without degradation for 15 h. The main reason for the high performance of our CNT field emitter is caused by the high density of emission sites at the edge of the CNT film.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-All-Around
           Field-Effect-Transistor With Self-Induced Ferroelectric Ge Doped HfO₂

    • Authors: Chong-Jhe Sun;Yi-Ju Yao;Siao-Cheng Yan;Yi-Wen Lin;Shan-Wen Lin;Fu-Ju Hou;Guang-Li Luo;Yung-Chun Wu;
      Pages: 408 - 412
      Abstract: We investigated the ferroelectric properties of self-induced HfGeOx in a HfO2 film deposited on a SiGe substrate and analyzed a novel ferroelectric inverted T channel gate-all-around (IT-GAA) with a Si/SiGe bilayer channel and self-induced ferroelectric Hf germanate. The proposed ferroelectric IT-GAAFET with short-channel (gate length = 60 nm) exhibited a steep average subthreshold slope of 53 mV/dec, a drain-induced barrier lowering of only 1.7 mV/V, and a high on-off current ratio of $1.7 times 10^{7}$ . The proposed ferroelectric IT-GAA field-effect transistor can be a candidate for the sub-N3 technology node and ultralow-power, high-performance applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Foreword Special Issue on the 3rd Latin American Electron Device

    • Authors: Lluís F. Marsal;Arturo Escobosa;Benjamin Iñiguez;Fernando Guarín;
      Pages: 413 - 415
      Abstract: This Special Issue is devoted to research and development in the field of electron devices science and technology. We have selected a number of high-quality papers presented at the 3rd Latin American Electron Device Conference (LAEDC 2021). The third LAEDC edition took place virtually, from April 19th to 21st, 2021 and was sponsored by the IEEE Electron Devices Society.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Physics-Based DC Compact Modeling of Schottky Barrier and Reconfigurable
           Field-Effect Transistors

    • Authors: Christian Roemer;Ghader Darbandy;Mike Schwarz;Jens Trommer;André Heinzig;Thomas Mikolajick;Walter M. Weber;Benjamín Iñíguez;Alexander Kloes;
      Pages: 416 - 423
      Abstract: A closed-form and physics-based compact model is presented for calculating the DC characteristics of Schottky barrier field-effect transistors and dual gated reconfigurable field-effect transistors. The given model calculates the charge-carrier injection over the Schottky barriers. This current is separated into a field emission current, given by charge carriers tunneling through the Schottky barriers and a thermionic emission current, given by charge carriers overcoming the Schottky barriers. The model verification is done by comparing the model results to measurements and TCAD simulations.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

    • Authors: Jean-Pierre Raskin;
      Pages: 424 - 434
      Abstract: Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range. The high frequency performances of FD SOI transistors are presented at room but also at cryogenic and high temperature. Recently published results for FD SOI switches and low noise amplifiers are summarized. And finally, the potential interest and challenges to move from standard to high resistivity FD SOI substrates are discussed.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Solution-Processed Small Molecule Inverted Solar Cells: Impact of Electron
           Transport Layers

    • Authors: Magaly Ramírez-Como;Victor S. Balderrama;José G. Sánchez;Angel Sacramento;Magali Estrada;Josep Pallarès;Lluis F. Marsal;
      Pages: 435 - 442
      Abstract: In this work, the use of poly [(9,9-bis (30- (N,N-dimethylamino) propyl) -2,7-fluorene) -alt-2,7- (9,9-dioctylfluorene) (PFN) as electron transport layer (ETL) in inverted small molecule solar cells (SM-iOSCs) is analyzed. The optical and electrical characteristics obtained are compared with those obtained for similar SM-iOSCs where the ETL was zinc oxide. The p-DTS(FBTTh2)2 and PC70BM materials are used as donor and acceptor in the bulk heterojunction active layer, respectively for all devices. The photovoltaic devices exhibited a power conversion efficiency of 6.75% under 1 sun illumination. Impedance measurements were used to understand the causes that dominate the performance of the devices. We found that the loss resistance is governed by the PFN layer, which results in a lower fill factor value. Studies of atomic force microscopy, external quantum efficiency, and absorption UV-vis on the active layer have been performed to understand the effects of the charge transport dynamics on the performance of the devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Six Decades of Research on 2D Materials: Progress, Dead Ends, and New

    • Authors: Frank Schwierz;Martin Ziegler;
      Pages: 443 - 451
      Abstract: The present paper guides the reader through six decades of research on 2D materials, thereby putting special focus on the use of these materials for electronic devices. It is shown that after a slow start and only little activity over many years, since 2004 the exploration of 2D materials advanced at an enormous pace. While some of the high expectations raised in the so-called golden era of graphene did not fulfil, other electronic applications for 2D materials that originally were not on the agenda gain increasing attention now. One of the main research topics in the field of 2D materials during the early 2000s was high-performance graphene transistors. This effort, however, led to a dead end due the consequences of the missing bandgap in graphene. On the other hand, the semiconducting 2D materials show potential for different device concepts including stacked-channel 2D nanosheet MOSFETs and 2D memristors. The former may become the transistor architecture of choice at the end of the CMOS roadmap and 2D memristors represent a promising device concept for future neuromorphic computing, a type of information processing that shows great potential for artificial intelligence applications where energy efficiency is a key requirement.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • TCAD Evaluation of the Active Substrate Bias Effect on the Charge
           Transport of Ω-Gate Nanowire MOS Transistors With Ultra-Thin BOX

    • Authors: F. E. Bergamaschi;M. A. Pavanello;
      Pages: 452 - 458
      Abstract: This work presents an analysis of the application of active substrate bias (or back bias) on the charge transport properties of n-type $boldsymbol{Omega }$ -gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width. Additionally, the influence of back bias on the electrical parameters of these devices is also investigated through DC parameters such as on-to-off-state current ratio and DIBL. The evaluation is conducted by 3D TCAD simulations calibrated with experimental data. The application of negative back bias on nMOS transistors not only shifts the threshold voltage, but also causes mobility degradation due to the negative potential on the channel pushing the charges against the gate oxide interface. On the other hand, when positive back bias is applied, despite the mobility improvement allowed by the back channel’s superior mobility and the front channel’s less compacted inversion layer, at higher substrate bias levels, a strong mobility degradation is observed in the back channel due to the substrate’s high electric field, resulting in reduction of the channel’s overall effective mobility. The application of positive substrate bias degrades the subthreshold slope, leading to smaller on-to-off-state current ratio, as well as the reduced control of channel charges by the gate electrode worsens the DIBL.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring

    • Authors: Mauricio Banaszeski da Silva;Thiago H. Both;Gilson I. Wirth;
      Pages: 459 - 465
      Abstract: In highly scaled MOSFETs, random telegraph noise (RTN) can decrease the reliability and yield of circuits. RTN is produced by charge trapping, which in large devices results in $1/f$ noise. We derived analytical formulations for modeling the impact of RTN in the delay of inverters and in the jitter of ring oscillators. We show that the parameters of interest when characterizing RTN for circuit analysis are the distribution of current deviations and the density of traps in the space of area, energy and in log-space of time-constants. The model gives a direct relation between jitter variance in oscillators (or delay variance in inverters) and the power spectral density of RTN, which includes $1/f$ noise. The formulations can be written using time- or frequency-domain parameters.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Using Self-Heating Resistors as a Case Study for Memristor Compact

    • Authors: Rodrigo Picos;Mohamad Moner Al Chawa;Carola De Benito;Stavros G. Stavrinides;Leon O. Chua;
      Pages: 466 - 473
      Abstract: Memristors were first proposed in 1971 by Leon Chua. These devices are usually regarded as being one of the newest fundamental breakthrough for electronics. Their role in designing new electronic systems is expected to be an important, key-factor. As an example, they already come in many forms: PCA, ReRAM, etc., to mention a few. In any case, since actual memristors have only appeared quite recently, this technology has yet to be mature enough to provide with readily available, off-the-shelf components. This implies that developing and testing new concepts or design architectures based on memristors are performed mainly by the use of numerical simulation. In this paper, we discuss a powerful modeling framework that eases creating and implementing new memristor models, illustrating with some examples of use.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Investigation on the Influence of Ohmic Structure on Channel-to-Channel
           Coupling Effect in InAlN/GaN Double Channel HEMTs

    • Authors: Ling Yang;Hao Lu;Meng Zhang;Xuerui Niu;Chuzhou Shi;Bin Hou;Minhan Mi;Mei Wu;Qing Zhu;Yang Lu;Ling Lv;Kai Cheng;Xiaohua Ma;Yue Hao;
      Pages: 474 - 480
      Abstract: In this paper, the impact of ohmic structure on channel-to-channel (C2C) coupling effect in InAlN/GaN double channel (DC) HEMTs is systematically analyzed and studied. For the un-recessed ohmic structure, the electrons in the upper channel can easily inject into the bottom channel due to the ultra-thin InAlN back barrier layer. Therefore, the maximum drain current and transconductance peak of the bottom channel significantly increase. For recessed ohmic structure, the reduced vertical electric field strength of the upper channel can effectively weaken the coupling effect between the two GaN channels. Benefiting from the suppressed vertical transport of electrons in the upper channel, higher drain current and transconductance of the upper channel are obtained in the recessed ohmic structure. In addition, the transmission electron microscope (TEM) microstructural analysis of the DC HEMTs with recessed ohmic structure was also performed. This work shows that the recessed ohmic structure can modulate the electron transport mode in the InAlN/GaN DC HEMTs. The coupling effect of the two channels will play a major role in influencing the characteristics of current gain cutoff frequency ( $,f_{mathrm{ T}}$ ) / maximum power gain cutoff frequency ( $,f_{mathrm{ max}}$ ) versus $V_{mathrm{ GS}}$ and have a significant effect on large-signal characteristics, which is quite attractive for the fabrication of power microwave GaN-based HEMTs with wide gate swing.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Accounting for Optical Generation in the Quasi-Neutral Regions of
           Perovskite Solar Cells

    • Authors: Parnian Ferdowsi;Farzan Jazaeri;Efrain Ochoa-Martinez;Jovana V. Milić;Michael Saliba;Ullrich Steiner;Jean-Michel Sallese;
      Pages: 481 - 489
      Abstract: Predicting the performance of solar cells though analytical models is important for the theory-guided optimization of these devices. Earlier models neglect the impact of the optical generation in the quasi-neutral regions of a perovskite solar cell. Here, a new model is developed that takes optical generation in these regions into account. The model includes the full depletion approximation and the drift-diffusion transport mechanisms. A comparison with earlier models demonstrates the improved predictive power of the developed model. In addition, the accuracy of the model was assessed by comparing it prediction to experimental data obtained from working devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Real-Time Switching Dynamics in STT-MRAM

    • Authors: N. Yazigy;J. Postel-Pellerin;V. Della Marca;K. Terziyan;R. C. Sousa;P. Canet;G. Di Pendina;
      Pages: 490 - 494
      Abstract: In this paper a new experimental technique for measuring the switching dynamics and extracting the energy consumption of Spin Transfer Torque MRAM (STT-MRAM) device is presented. This technique is performed by a real-time current reading while a pulsed bias is applied. The switching from a high resistive state, anti-parallel (AP) alignment, to a low resistive state, parallel (P) alignment, is investigated as well as the impact of the cell diameter on the switching parameters. We demonstrate that preswitching and switching times and energies have a log-linear relationship with the applied voltage. Increasing the applied voltage leads to a higher spin torque on the free layer in a shorter time. This decreases the time needed to change the magnetization orientation of this layer, thus the time required before the switching occurs. We have also shown that for a given applied voltage, the smaller the cell the longer the time before switching. For low applied voltages, the preswitching time increases exponentially dominating the whole reversal time. The longer switching times can be explained by a lower Joule heating not sufficient to induce the thermally activated reversal process. This phenomenon is accentuated for smaller cells, where the heating is more significant and the time before switching is shorter than for larger cells.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Channel Design Optimization for 1.2-kV 4H-SiC MOSFET Achieving Inherent
           Unipolar Diode 3rd Quadrant Operation

    • Authors: Dongyoung Kim;Nick Yun;Seung Yup Jang;Adam J. Morgan;Woongje Sung;
      Pages: 495 - 503
      Abstract: SiC Schottky Barrier Diodes (SBDs) have been used in parallel with SiC MOSFETs as a freewheeling diode in power converter applications because the inherent PN body diode of the MOSFET has relatively high forward voltage drop, considerable reverse recovery current, and suffers from the expansion of stacking faults over the lifetime of the device [1]. However, an additional external diode requires extra space within a multi-chip package or power module, and adds undesirable parasitic inductance to the power loop during commutation events of the power converter. Alternatively, when the unipolar diode structure is integrated within the MOSFET, a significant reduction in wafer area is achieved by sharing active and edge termination areas. Monolithic integration of Schottky or JBS diode in a SiC MOSFET structure (JBSFET) and SiC MOSFET integrating the unipolar internal inverse channel diode were reported earlier [2]–[5], respectively. However, JBSFET from [2] has higher specific on-resistance due to the larger cell pitch from the portion of JBS diode when compared with standalone MOSFET. For [5], the fabrication of the proposed MOSFET requires a very thin and heavily doped epitaxial regrowth process, which may result in a complicated process.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Comprehensive Design and Numerical Study of GaN Vertical MPS Diodes
           Towards Alleviated Electric Field Crowding and Efficient Carrier Injection

    • Authors: Heng Wang;Sihao Chen;Hang Chen;Chao Liu;
      Pages: 504 - 511
      Abstract: In recent years, gallium nitride (GaN) has exhibited tremendous potential for power electronic devices owing to its wider energy band gap, higher breakdown electric field, and higher carrier mobility [1]–[4]. Thanks to the availability of low-dislocation-density bulk GaN substrates and the intrinsic advantages of the vertical device topology, GaN-based vertical SBDs have been developed extensively towards high voltage and high current applications [5]–[7]. However, similar to the lateral GaN SBDs based on the AlGaN/GaN heterostructures, GaN vertical SBDs also suffer from reverse leakage issues due to the energy barrier lowering effect at high reverse bias condition. To achieve a decent device performance, several device architectures have been developed, such as junction barrier Schottky (JBS) diode [8], MPS diode [9]–[12], and trench metal-insulator-semiconductor barrier Schottky (TMBS) diode [13], [14], which are designed to move the peak electric field from the interface of the Schottky junction to the inside of the device at high reverse bias, leading to a higher breakdown voltage and a lower reverse leakage current.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Zoomed Response Surface Method for Automatic Design in Parameters
           Optimization of Low-Voltage Power MOSFET

    • Authors: Wataru Saito;Shin-Ichi Nishizawa;
      Pages: 512 - 515
      Abstract: A new parameter optimization method using zoomed response surface (RS) is proposed for automatic design of low-voltage power MOSFET. Low-voltage MOSFET characteristics have been improved continuously considering with not only low power loss but also low cost to answer request to high-performance system. Complicated requirements lead long development schedule and low yield. Model-based design and machine learning are prospective method to answer the problem. However, reported methods require many simulation numbers (>1000) for training to obtain high accuracy, and it is difficult to optimize parameters considering the process margin at the same time. This article shows a simple design method using zoomed RS. Five parameters were automatically designed, taking account to process margin with simulation number of 130 only.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Schottky-Embedded Isolation Ring to Improve Latch-Up Immunity Between HV
           and LV Circuits in a 0.18 μm BCD Technology

    • Authors: Zi-Hong Jiang;Ming-Dou Ker;
      Pages: 516 - 524
      Abstract: As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common silicon substrate, the parasitic latch-up path between neighboring HV and LV circuits with limited spacing in layout would be triggered into latch-up state to cause unrecoverable failure in the chip. In this work, the isolation ring of HV n-well (HVNW) / N-buried layer (NBL) with Schottky-embedded junction to overcome the lateral HV-to-LV latch-up path was proposed and verified in a $0.18{mu }text{m}$ HV bipolar-CMOS-DMOS (BCD) technology. From the experiment results of the proposed Schottky-embedded isolation ring, the holding voltage (Vh) in the lateral HV-to-LV parasitic latch-up path can be increased to be greater than the voltage difference between the different power supplies of the neighboring HV and LV circuits. Furthermore, the layout spacing between the neighboring HV and LV circuits can be significantly reduced to save chip area. The proposed Schottky-embedded isolation ring is a cost-effective solution to provide good latch-up immunity among the HV-to-LV circuit blocks with a short layout distance.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Hf-Based and Zr-Based Charge Trapping Layer Engineering for E-Mode GaN
           MIS-HEMT Using Ferroelectric Charge Trap Gate Stack

    • Authors: Jui-Sheng Wu;Chih-Chieh Lee;Chia-Hsun Wu;Cheng-Jun Huang;Yan-Kui Liang;You-Chen Weng;Edward Yi Chang;
      Pages: 525 - 531
      Abstract: E-mode hybrid ferroelectric charge storage gate (FEG) GaN HEMTs have shown promising performances for future power GaN device applications. The FEG-HEMT demonstrates a combination of ferroelectric polarization and charge trapping process in the ferro-charge-storage gate stack, leading to a positive threshold voltage shift for E-mode operations. In this work, FEG-HEMTs with various Hf-based and Zr-based charge trapping layers are systematically studied. FEG-HEMT which employed nitrogen incorporated HfO2 (HfON) as the charge trapping layer shows an E-mode operation with the highest $V_{mathrm{ th}}$ (+2.3 V) after initialization. Moreover, the gate leakage of the HfON sample was further reduced due to the nitrogen incorporation, leading to a more complete charging process during initialization. The $V_{mathrm{ th}}$ instability is also addressed and investigated. The FEG-HEMT with HfON as the charge trapping layer showed a negligible $V_{mathrm{ th}}$ hysteresis (−43mV) and the highest $V_{mathrm{ th}}$ stability in both the PBTI (positive bias threshold voltage instability) and NBTI (negative bias threshold voltage instability) test measurements.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Cryogenic CMOS RF Device Modeling for Scalable Quantum Computer Design

    • Authors: Zhidong Tang;Zewei Wang;Ao Guo;Linlin Liu;Chengwei Cao;Xin Luo;Weican Wu;Yingjia Guo;Zhenghang Zhi;Yongqi Hu;Yongfeng Cao;Ganbing Shang;Liujiang Yu;Shaojian Hu;Shoumian Chen;Yuhang Zhao;Xufeng Kou;
      Pages: 532 - 539
      Abstract: This paper presents experimental RF characterizations and modeling on the nano-scale multi-finger gate MOSFETs of the HLMC 40 nm low-power CMOS technology. Both the resistive and capacitive components in the equivalent circuit model for the RF MOSFET devices are calibrated based on temperature-dependent S-parameter measurements (0.25 – 40 GHz) from 298 K to 6 K. By integrating the intrinsic device model and the extrinsic parasitic parameters, a generic cryogenic device RF model is developed to capture the cutoff frequency and high-frequency performance of NMOS and PMOS transistors with varied device configurations. The establishment of validated database as functions of device size, temperature, and frequency responses lays a solid foundation for practical large-scale cryo-CMOS RF circuit design and optimization.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Dynamic Characteristics of GaN MISHEMT With 5-nm In-Situ SiNx Dielectric

    • Authors: Yu Zhang;Lihua Xu;Yitian Gu;Haowen Guo;Huaxing Jiang;Kei May Lau;Xinbo Zou;
      Pages: 540 - 546
      Abstract: A comprehensive study on dynamic characteristics of GaN MISHEMT with a 5nm-thick in-situ SiNx dielectric is presented. Effects of both negative and positive gate bias on threshold voltage instability were investigated and miniature threshold voltage shift was acquired. The slight shift was considered to be associated with the traps at the insulator/AlGaN interface and in the dielectric layer itself. Pulsed I-V measurements with various gate quiescent biases presented small current collapse (11%) and low enhancement of dynamic Ron for zero quiescent drain bias. When drain quiescent bias was strengthened to 20V, an increased dynamic Ron/static Ron ratio was identified but still limited to a low value of 1.24. The conduction reduction was in a good agreement with measurement results from drain current transient spectroscopy and possibly originates from trap states existed in the access region. Additional current collapse was observed in hard switching-on operation, resulted from energetic hot electrons accelerated by drain-source electrical field during the off-to-on step. The measurement results showed stabilized threshold voltage, a low dynamic Ron/static Ron ratio, and suppressed current collapse via employing a 5-nm thin in-situ SiNx layer in GaN MISHEMT, enabling it a promising solution for high-efficiency power switching applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Piezoresistive Thermal Characteristics of Aluminum-Doped P-Type 3C-Silicon

    • Authors: Takaya Sugiura;Naoki Takahashi;Ryohei Sakota;Kazunori Matsuda;Nobuhiko Nakano;
      Pages: 547 - 553
      Abstract: This study examined the temperature-related piezoresistance issues of p-type doped 3C-silicon carbide (3C-SiC) materials. Previously, we proposed piezoresistance temperature models that describe phenomena based on the ionization energies of materials oriented for high-temperature operations. This study aimed to determine the ionization energy as a function of the aluminum doping concentration of 3C-SiC. However, at the low-temperature region a drastic decrease in the piezoresistive coefficient was observed, and it was predicted to occur when materials possessing large impurity ionization energy are used under negative thermal strained conditions. This phenomenon is in contrast to the conventional piezoresistance factor $P(N,T)$ that is based on narrow band-gap materials such as silicon or germanium; thus, it provides new insights into low-temperature piezoresistance phenomena.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Low Switching Loss Split-Gate 4H-SiC MOSFET With Integrated Heterojunction

    • Authors: Hai-Yong Xu;Ying Wang;Meng-Tian Bao;Fei Cao;
      Pages: 554 - 561
      Abstract: A 4H-SiC MOSFET with p-type region injection and integrated split gate and heterojunction diode is proposed in this paper. Compared with the conventional MOSFET, the proposed structure has a lower on-resistance and switching loss. And the gate oxide layer has been well protected by the p-type region, which reduces the electric field in gate oxide layer at the off-state. The on-resistance of device can be greatly reduced by increasing the doping concentration of current spreading layer and will not cause a huge electric field in gate oxide layer. The specific on-resistance is decreased by about 27.8% and the static characteristic (BV2/ $text{R}_{mathrm{ on,sp}}$ ) of the device is improved about 37.3%. SiC material has a high third quadrant turn-on voltage due to its wide band gap characteristics. The use of heterojunction integration can take place of parasitic body diode and reduce its turn-on voltage, avoid the bipolar degradation effect, and improves the reverse recovery characteristics. To evaluate the dynamic performance, the reverse transmission capacitance ( $text{C}_{mathrm{ rss}}$ ) and gate-drain charge ( $text{Q}_{mathrm{ gd}}$ ) of the proposed structure have been studied in this paper via numerical simulations. Based on the simulation, the HF-FOM ( $text{C}_{mathrm{ rss}} {times }text{R}_{mathrm{ on,sp}}$ ) and HF-FOM2 ( $text{Q}_{mathrm{ gd}} {times }text{R}_{mathrm{ on,sp}}$ ) of the proposed structure are decreased by about 87% and 86%, respectively. Meanwhile, the reverse turn-on voltage -nd reverse recovery characteristics are also improved, and the total energy loss decreases by about 37.3%.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Special Section on ESSDERC 2021

    • Authors: Louis Hutin;
      Pages: 562 - 562
      Abstract: The current trend of applicative diversification in the semiconductor market, together with steepening technological challenges have stressed the need for increasingly holistic approaches based on co-optimization across the traditionally defined domains. In this context, our semiconductor research community benefits more than ever from international conferences such as ESSCIRC-ESSDERC, bringing together device physicists, semiconductor technologists, IC designers, and architects from academia and industry alike to showcase and exchange their latest results and innovative ideas.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • BEOL Process Effects on ePCM Reliability

    • Authors: A. Redaelli;A. Gandolfo;G. Samanni;E. Gomiero;E. Petroni;L. Scotti;A. Lippiello;P. Mattavelli;J. Jasse;D. Codegoni;A. Serafini;R. Ranica;C. Boccaccio;J. Sandrini;R. Berthelon;J.-C. Grenier;O. Weber;D. Turgis;A. Valery;S. Del Medico;V. Caubet;J.-P. Reynard;D. Dutartre;L. Favennec;A. Conte;F. Disegni;M. De Tomasi;A. Ventre;M. Baldo;D. Ielmini;A. Maurelli;P. Ferreira;F. Arnaud;F. Piazza;P. Cappelletti;R. Annunziata;R. Gonella;
      Pages: 563 - 568
      Abstract: The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Four-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as
           Artificial Synapses for Neuromorphic Applications

    • Authors: Fengben Xi;Yi Han;Andreas Grenmyr;Detlev Grützmacher;Qing-Tai Zhao;
      Pages: 569 - 574
      Abstract: In this paper, artificial synapses based on four terminal ferroelectric Schottky barrier field effect transistors (FE-SBFETs) are experimentally demonstrated. The ferroelectric polarization switching dynamics gradually modulate the Schottky barriers, thus programming the device conductance by applying negative or postive pulses to imitate the excitation and inhibition behaviors of the biological synapse. The excitatory post-synaptic current can be modulated by the back-gate bias, enabling the reconfiguration of the weight profile with high speed of 20 ns and low energy (< 1 fJ/spike) consumption. Besides, the tunable long term potentiation and depression show high endurance and very small cycle-to-cycle variations. Based on the good linearity, high symmetricity and large dynamic range of the synaptic weight updates, a high recognition accuracy (92.6%) is achieved for handwritten digits by multilayer perceptron artificial neural networks. These findings demonstrate FE-SBFET has high potential as an ideal synaptic component for the future intelligent neuromorphic network.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Optimum Functionalization of Si Nanowire FET for Electrical Detection of
           DNA Hybridization

    • Authors: R. Midahuen;B. Previtali;C. Fontelaye;G. Nonglaton;V. Stambouli;S. Barraud;
      Pages: 575 - 583
      Abstract: In this work, we demonstrate a wafer-scale fabrication of biologically sensitive Si nanowire FET for pH sensing and electrical detection of deoxyribonucleic acid (DNA) hybridization. Based on conventional “top-down” CMOS compatible technology, our bioFETs explore a wide range of design (nanowires (NW), nanoribbons (NR), and honeycomb (HC) structures) with opening access scaled down to only 120 nm. After device fabrication, IDS-VBG transfer and IDS-VDS output characteristics show a conventional n-type FET behavior with an ION/IOFF value higher than 105, as well as an increase of threshold voltage as the NW width is reduced. Then, using a capacitive coupling in our dually-gated Si bioFETs, the pH sensitivity is enhanced with a pH response up to 600 mV/pH. Finally, we successfully detected an increase of threshold voltage of n-type silicon nanowires (SiNWs) due to hybridized target DNA molecules.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Comprehensive Modeling and Characterization of Photon Detection Efficiency
           and Jitter Tail in Advanced SPAD Devices

    • Authors: Rémi Helleboid;Denis Rideau;Jeremy Grebot;Isobel Nicholson;Norbert Moussy;Olivier Saxod;Marie Basset;Antonin Zimmer;Bastien Mamdy;Dominique Golanski;Megan Agnew;Sara Pellegrini;Mathieu Sicre;Christel Buj;Guillaume Marchand;Jérôme Saint-Martin;Marco Pala;Philippe Dollfus;
      Pages: 584 - 592
      Abstract: A new method to reliably simulate the PDE and jitter tail for realistic three-dimensional SPAD devices is presented. The simulation method is based on the use of electric field lines to mimic the carriers’ trajectories, and on one-dimensional models for avalanche breakdown probability and charges transport. This approach allows treating a three-dimensional problem as several one-dimensional problems along each field line. The original approach is applied to the McIntyre model for avalanche breakdown probability to calculate PDE, but also for jitter prediction using a dedicated advection-diffusion model. The results obtained numerically are compared with an extensive series of measurements and show a good agreement on a wide variety of device designs.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Interplay Between Charge Trapping and Polarization Switching in
           BEOL-Compatible Bilayer Ferroelectric Tunnel Junctions

    • Authors: R. Fontanini;J. Barbot;M. Segatto;S. Lancaster;Q. Duong;F. Driussi;L. Grenouillet;L. Triozon;J. Coignus;T. Mikolajick;S. Slesazeck;D. Esseni;
      Pages: 593 - 599
      Abstract: We here report a joint experimental and theoretical analysis of polarization switching in ferroelectric tunnel junctions. Our results show that the injection and trapping of charge into the ferroelectric-dielectric stack has a large influence on the polarization switching. Our results are relevant to the physical understanding and to the design of the devices, and for both memory and memristor applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Characterization and Modeling of Quantum Dot Behavior in FDSOI Devices

    • Authors: S. Pati Tripathi;S. Bonen;A. Bharadwaj;T. Jager;C. Nastase;S. Iordănescu;G. Boldeiu;M. Păşteanu;A. Nicoloiu;I. Zdru;A. Müller;S. P. Voinigescu;
      Pages: 600 - 610
      Abstract: A compact analytical model is proposed along with a parameter extraction methodology to accurately capture the steady-state (DC) sequential tunneling current observed in the subthreshold region of the transfer $I_{DS}-V_{GS}$ characteristics of MOSFETs at cryogenic temperatures. The model is shown to match measurements of $p$ -MOSFETs and $n$ -MOSFETs manufactured in a commercial 22nm FDSOI foundry technology, with reasonable accuracy across bias conditions and temperature (2 K - 50 K). Furthermore, the extracted model parameters are used to analyze the impact of the gate and drain voltages and of layout geometry on the device characteristics.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Model Implementation of Lorentzian Spectra for Circuit Noise Simulations
           in the Frequency Domain

    • Authors: Angeliki Tataridou;Gérard Ghibaudo;Christoforos Theodorou;
      Pages: 611 - 619
      Abstract: This work presents a new method for the Verilog-A implementation of Lorentzian noise models, in a module called VERILOR, which can automatically generate either Lorentzian or 1/f-like noise spectra depending on the trap density and gate oxide area, for all bias conditions, in a one-step simulation. Based on statistical experimental data, we demonstrate the importance of Lorentzian noise modeling in contrast to classic frequency domain 1/f or time domain Random Telegraph Noise (RTN) modeling, in terms of PSD, total noise power, and device-to-device noise variability reproduction. Moreover, we validate the applicability of VERILOR in circuit simulators in both frequency and time domain, and how it can enable precise noise variability studies at a circuit level. Finally, fundamental digital and analog circuits such as the Ring Oscillator are used to showcase the usefulness and applicability of the VERILOR model in circuit noise simulations.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • High-Temperature Characterization of Multiple Silicon-Based Substrate for
           RF-IC Applications

    • Authors: Q. Courte;M. Rack;M. Nabet;P. Cardinael;J.-P. Raskin;
      Pages: 620 - 626
      Abstract: This paper focuses on the comparison of various advanced substrates such as trap-rich (TR), porous silicon (PSi), gold-doped (Au-Si) and smart-implants PN-junction (DP) in terms of RF performances. Both small- and large-signal measurements were performed, including the study of the influence of temperature and DC bias voltage. The purpose of this paper is to provide an overview, and a more in-depth analysis of DP substrate, of the characteristics of these multiple substrates to facilitate design choices for RF-IC applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A New IR-Drop Model That Improves Effectively the Brightness Uniformity of
           an AMOLED Panel

    • Authors: Paul C.-P. Chao;Shih-Song Cheng;Chiu-Hao Chen;Kuei-Yu Lee;
      Pages: 627 - 636
      Abstract: A new model characterizing the IR drop in an active-matrix organic light-emitting diode (AMOLED) display is built successfully by this study, which can be used to effectively improve brightness uniformity by adjusting gray levels addressed accordingly to pixels in the panel. The IR-drop refers to the voltage drops along the thin power lines from the external driver at panel edge to internal pixels. The built IR-drop model is in a form of vector and matrix with parameters and variables such as equivalent resistances of horizontal/vertical power lines and the current through the drive thin film transistors (TFTs) and OLEDs in pixels. With precisely calibrated parameters, the model can be solved for the voltage drops at given sub-pixels in the AMOLED panel. Based on the solved dropped voltages at each pixel, the gray level assigned to the pixel $V_{data}$ can be adjusted accordingly to restore the desired pixel luminance. The proposed compensation was implemented in a 14-inch AMOLED panel with FHD resolution for performance validation. The experimental results show less than 2.5% of prediction error on voltage drops, leading to effective compensations that improves the measured pixel currents from 66.1% to 89.7%, 70.3% to 92.9%, and 48.8% to 85.1% of the desired, non-dropped currents, respectively, for red, green, and blue illuminance at the L255 gray level. Also from experiments are substantial improvements of 21.7%, 21.5%, and 35.3% on the brightness uniformity of the panel displayed for red-, green-, blue-images at L255 gray, respectively.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine

    • Authors: Sourav De;Franz Müller;Hoang-Hiep Le;Maximilian Lederer;Yannick Raffel;Tarek Ali;Darsen Lu;Thomas Kämpfe;
      Pages: 637 - 641
      Abstract: This paper reports 2bits/cell ferroelectric FET (FeFET) devices with 500 ns write pulse of maximum amplitude 4.5V for inference-engine applications. FeFET devices were fabricated using GlobalFoundries 28nm high-k-metal-gate (HKMG) process flow on a 300mm wafer. The devices were characterized, and statistical modeling of variations in the fabricated devices was carried out based on experimental data. Furthermore, the model was applied to multi-layer perceptron (MLP) neural network (NN) simulations using the CIMulator software platform. The neural network (NN) was trained offline, and the weights were transferred to the synaptic devices for an inference-only operation. Device-to-device (D2D) and cycle-to-cycle (C2C) variations are limited by optimal process conditions and do not impact inference accuracy. However, due to short-term retention, read-to-read (R2R) variation significantly affects inference operation. This work proposes a synergistic READ-optimization approach to mitigate the impact of short-term retention and device variation issues. The optimization technique fostered immunity in the MLP-NN towards R2R variations, and the MLP-NN maintains inference accuracy of 97.01%, while the software baseline is 98%.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • O2 and H2O Barrier-Based High Reliability and Stability Using
           Polytetrafluoroethylene Passivation Layer for Solution Processed Indium
           Oxide Thin Film Transistors

    • Authors: Fei Shan;Han-Lin Zhao;Xiao-Lin Wang;Jae-Yun Lee;Sung-Jin Kim;
      Pages: 642 - 648
      Abstract: The excellent chemical stability and hydrophobicity of Polytetrafluoroethylene (PTFE) polymer lead to its applicability in high-performance flexible electronic appliances. Though the detailed investigation for PTFE passivated metal oxide thin-film transistors (TFTs) is still lacking. Here, we report the highly stable oxygen barrier based on the PTFE passivation layer (PVL) spin-coated upon the lowtemperature solution-processed indium oxide (In2O3) TFTs. Particularly, by using the solution-process method, fabrication cost and multiple time-consuming steps are eliminated in the counterpart of the radio frequency magnetron sputtering. The PTFE PVL can significantly suppress the adsorption of surrounding moisture and oxygen from environments owing to its most chemically robust carbon-fluorine bond. In addition, the comprehensive electrical performance in terms of the saturation mobility, on-off current ratio, threshold voltage, subthreshold swing, and interface trap density of the In2O3 TFTs passivated with different weight ratios of PTFE are compared. The results show that 1 wt.% PTFE passivated In2O3 TFT demonstrates a drastically reduced threshold voltage and highest stability under constant bias. Consequently, oxygen barrier-based PTFE is a promising PVL material for various emerging electronic devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Optimal Design and Noise Analysis of High-Performance DBR-Integrated
           Lateral Germanium (Ge) Photodetectors for SWIR Applications

    • Authors: Harshvardhan Kumar;Ankit Kumar Pandey;Chu-Hsuan Lin;
      Pages: 649 - 659
      Abstract: This work presents the high-performance Si/SiO2 distributed Bragg reflector (DBR)-integrated lateral germanium (Ge) p-i-n photodetectors (PDs) for atmospheric gas sensing and fiber-optic telecommunication networks in the short-wave infrared (SWIR) regime. In addition, this study also proposes an optoelectronic compact small-signal noise equivalent circuit model (SSNECM) of the designed device to compute the noise performance at the detectors’ output. Various figure-of merits including current under dark and illumination, responsivity, detectivity, bandwidth, and the noise of the proposed device are estimated at the room temperature (RT) for an incident optical power of ${0}.{5} {mu }{W}$ . Furthermore, the impact of width and height scaling on dark current, responsivity, and bandwidth are investigated to optimize the proposed device. The validation of the proposed model is done by comparing various parameters including dark current, responsivity, and detectivity of the designed device with other Ge PDs. The estimated results show the reduced trade-off between responsivity and bandwidth of the designed device. At ${lambda }=1550 nm$ , the proposed device achieves a high detectivity and SNR of $>2times {10}^{11}$ Jones and 120 dB (at 3 THz), respectively, with the bias voltage of −2V. These encouraging results pave the path for the future development of low-noise and high-speed detectors.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improved Electrical and Temporal Stability of In-Zn Oxide Semiconductor
           Thin-Film Transistors With Organic Passivation Layer

    • Authors: Kwan-Jun Heo;Gergely Tarsoly;Jae-Yun Lee;Seong Gon Choi;Jung-Hyuk Koh;Sung-Jin Kim;
      Pages: 660 - 665
      Abstract: Solution-processed In-Zn oxide (IZO) semiconductor thin-film transistors (TFTs) were fabricated with passivation layers of either poly(methyl methacrylate) (PMMA) or cyclic transparent optical polymer (CYTOP). According to the transfer curves obtained on the day of fabrication and after 200 days, the drain-source current of the IZO TFT without a passivation layer decreased by approximately 37 %. For the PMMA-passivated IZO TFT, it decreased by approximately 31 %. The current for the CYTOPpassivated IZO TFT showed significantly lower, only 7 % deterioration. Hence, the CYTOP-passivated IZO TFT exhibited improved electrical stability under long term ambient storage. This was attributed to the difference in the chemical composition of the two polymers, as CYTOP is a fluoropolymer, while PMMA is an ester group containing organic polymer. We show, passivation of the active layer with the proper organic film improves the stability of the high-performance solution-processed IZO TFTs.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Effect of Stochastic Resonance on Classification Accuracy of Neural
           Networks Utilizing Inherent Stochasticity in Threshold Voltage of Ovonic
           Threshold Switching Device

    • Authors: Wooseok Choi;Myonghoon Kwak;Donguk Lee;Sangmin Lee;Chuljun Lee;Seyoung Kim;Hyunsang Hwang;
      Pages: 666 - 669
      Abstract: In this study, stochastic resonance (SR) exploits the inherent stochastic characteristics of the OTS threshold voltage to enhance the inference performance of neural networks. First, the threshold switching of the OTS device is characterized, and a signal detection using an OTS device is proposed. Next, we investigate the impact of stochasticity in the threshold voltage on detecting weak signals in the SR system. Finally, by evaluating the inference performance of the artificial neural network, we confirm that the inherent stochasticity can effectively restore the degraded MNIST image in poor visibility conditions in the OTS device. As a result, the recognition accuracy was improved from 10.28% to 95.78% when the stochasticity characteristic was reflected. These results show that stochasticity in the device can improve system performance.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Temperature Effect Analysis of the Enzymatic RuO2 Biomedical Sensor for
           Ascorbic Acid Detection

    • Authors: Po-Yu Kuo;Wei-Hao Lai;Chun-Hung Chang;Tai-Hui Wang;
      Pages: 670 - 678
      Abstract: The temperature effect has been discussed in the past on pH sensors. In this study, the temperature effect is analyzed for the ascorbic acid (AA) biosensor based on enzymatic ascorbate oxidase (AO). To reduce this effect, a novel temperature compensation circuit was implemented by Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) 180 nm complementary metal-oxide-semiconductor (CMOS) process. By applying the proposed circuit, the temperature coefficients (TCs) with five concentrations of AA were suppressed below $201~mathbf {mu }text{V}/mathbf {^{circ} }text{C}$ . The TC of the normal level of AA concentration (0.0312 mM) in the human body was $188~mathbf {mu }text{V}/mathbf {^{circ} }text{C}$ , at the temperature range from 25°C to 55°C. The polyethylene terephthalate (PET) substrate was utilized. To confirm the stability of the fabricated AO/RuO2/PET AA biosensor, interference and hysteresis experiments were carried out. At present, the experiments were still in the stage of in vitro measurement. The results showed that the AO/RuO2/PET AA biosensor had good selectivity that effective against other interference that may exist in blood at either 25 °C or 37.5°C. Moreover, at the temperature of 37.5°C, the hysteresis voltage of the biosensor after applying the compensation circuit was reduced from 18.27 mV to 1.39 mV.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Study on Dominant Mechanism and Analytical Model of Low-Frequency Noise
           in FD-SOI pTFET

    • Authors: Hyun-Jin Shin;Sunil Babu Eadi;Seong-Hyun Kim;Tae-Gyu Ryu;Yeong-Jin An;Do-Woo Kim;Hi-Deok Lee;Hyuk-Min Kwon;
      Pages: 679 - 686
      Abstract: The origin of low-frequency noise (LFN) properties and the accuracy of LFN model were demonstrated in a fully depleted silicon-on-insulator p-type tunneling field-effect transistor (pTFET). We demonstrated that the origin of LFN properties in pTFET can be deduced and analyzed via the current fluctuation induced by tunneling in the pTFET operation region. Since the trap sites near the tunneling junction contributed to LFN, pTFET must consider the tunneling junction characteristics and channel transportation influences. The tunneling path was not formed at low $ V_{GS} $ and the carrier transport in pTFET crossed the energy band by Shockley–Read–Hall (SRH) generation–recombination or the trap-assisted tunneling (TAT) mechanism and not through band-to-band tunneling (BTBT). However, with the increase in $ V_{GS} $ , the tunneling path was formed and the carriers could flow through the energy band by BTBT. The correlation between the simulated model data and experimental data was examined, confirming that the proposed small-signal model accurately represents noise in pTFETs.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Comparison of Two in Pixel Source Follower Schemes for Deep Subelectron
           Noise CMOS Image Sensors

    • Authors: Assim Boukhayma;Andrea Kraxner;Antonino Caizzone;Minhao Yang;Daniel Bold;Christian Enz;
      Pages: 687 - 695
      Abstract: This paper compares two in-pixel source follower stage designs for low noise CMOS image sensors embedded both on a same 5 mm by 5 mm chip fabricated in a 180nm CIS process. The presented chip embeds two pixel variants, one based on a body-effect-canceled thin oxide PMOS and the other embeds a native thick oxide NMOS. On the other hand they share the same sense node, same amplification circuit and 11bit single slope analog to digital converter (SS-ADC). The imager characterization demonstrates a histogram peak noise of 0.34e $^{-}_{text{RMS}}$ with the PMOS SF pixel and 0.47e $^{-}_{text{RMS}}$ with the NMOS SF at maximum analog gain. This performance is obtained at room temperature and 119 frame per second. Both pixel variants demonstrate a full well capacity over 5600 electrons.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Impact of AlGaN Barrier Thickness and Substrate Material on the Noise
           Characteristics of GaN HEMT

    • Authors: Anwar Jarndal;Arivazhagan L;Eqab Almajali;Sohaib Majzoub;Talal Bonny;Soliman Mahmoud;
      Pages: 696 - 705
      Abstract: In this paper, the impact of AlGaN barrier thickness ( $text{t}_{mathrm{ AlGaN}}$ ) and substrate leakage on the noise conductance and noise figure in GaN High Electron Mobility Transistor (HEMT) is investigated. The investigation and analysis in this paper are targeting the Low Noise Amplifier (LNA) applications. The noise analysis is carried out using Technology Computer-Aided Design (TCAD) physical simulator. Initially, the DC, RF, and noise simulations are validated against measurements of a GaN device. AlGaN barrier thickness ( $text{t}_{mathrm{ AlGaN}}$ ) is varied and its impact on the minimum noise figure (NFmin) is analyzed. It is observed that the NFmin decreases with $text{t}_{mathrm{ AlGaN}}$ reduction at the typical bias conditions of LNA. This observation on the impact of $text{t}_{mathrm{ AlGaN}}$ on the NFmin follows Fukui’s model, which states that the NFmin decreases with the increase in transconductance. In addition, the impact of the substrate material on noise performance is analyzed. The substrates used for the investigation are Silicon (Si) and Silicon Carbide (SiC). At 40 GHz, it is found that the noise conductance and the NFmin of GaN HEMT on SiC substrate is reduced by 13% and 12%, respectively, in comparison with GaN HEMT on Si substrate. This could be attributed to the lower gate-to-substrate capacitance of the GaN HEMT on SiC substrate.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Physics-Based Model for Mobile-Ionic Field-Effect Transistors With Steep
           Subthreshold Swing

    • Authors: Jiajia Chen;Huan Liu;Chengji Jin;Xiaole Jia;Xiao Yu;Yue Peng;Ran Cheng;Bing Chen;Yan Liu;Yue Hao;Genquan Han;
      Pages: 706 - 711
      Abstract: A physics-based model and the corresponding simulation framework for the mobile-ionic field-effect transistor (MIFET) exhibiting the ferroelectric-like behaviors are innovatively proposed based on two-dimensional (2D) Poisson’s equation and non-equilibrium Green’s function (NEGF), coupling with ion drift-diffusion equations. The simulation framework captures the dynamic distribution of mobile ions’ concentrations within dielectric along the external electric field. TaN/amorphous-ZrO2/TaN capacitors are experimentally characterized for the model calibration. It is proved that the mobile ions dominate the ferroelectric-like behaviors in MIFETs. Sub-60 mV/decade can be achieved in MIFETs based on the proposed model, which is consistent with the experimental results.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Solid Phase Recrystallization in Arsenic Ion-Implanted
           Silicon-On-Insulator by Microsecond UV Laser Annealing

    • Authors: Toshiyuki Tabata;Fabien Rozé;Pablo Acosta Alba;Sebastien Halty;Pierre-Edouard Raynal;Imen Karmous;Sébastien Kerdilès;Fulvio Mazzamuto;
      Pages: 712 - 719
      Abstract: UV laser annealing (UV-LA) enables surface-localized high-temperature thermal processing to form abrupt junctions in emerging monolithically stacked devices, where the applicable thermal budget is restricted. In this work, UV-LA is performed to regrow a silicon-on-insulator wafer partially amorphized by arsenic ion implantation as well as to activate the dopants. In a microsecond scale ( $sim 10^{-6}$ s to $sim 10^{-5}$ s) UV-LA process, monocrystalline solid phase recrystallization and dopant activation without junction deepening are evidenced, thus opening various applications in low thermal budget integration flows. However, some concerns remain. First, the surface morphology is degraded after the regrowth, possibly because of the non-perfect uniformity of the used laser beam and/or the formation of defects near the surface involving the excess dopants. Second, many of the dopants are inactive and seem to form deep levels in the Si band gap, suggesting a further optimization of the ion implantation condition to manage the initial crystal damage and the heating profile to better accommodate the dopants into the substitutional sites.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Silicon Wafer Gettering Design for Advanced CMOS Image Sensors Using
           Hydrocarbon Molecular Ion Implantation: A Review

    • Authors: Kazunari Kurita;Takeshi Kadono;Ryosuke Okuyama;Ayumi Onaka-Masada;Satoshi Shigematsu;Ryo Hirose;Koji Kobayashi;Akihiro Suzuki;Hidehiko Okuda;Yoshihiro Koga;
      Pages: 720 - 727
      Abstract: We have developed silicon epitaxial wafers with high gettering capability using hydrocarbon molecular ion implantation for advanced Complementary Metal-Oxide-Semiconductor (CMOS) image sensors. These wafers have three unique silicon wafer characteristics for improvement of CMOS device electrical parameter such as high metallic impurity gettering, oxygen out-diffusion barrier effects from Czochralski silicon (CZ) substrate and hydrogen passivation effect for interface state defect at Si/SiO2. We demonstrate that double epitaxial growth silicon wafers have an extremely high gettering capability during CMOS device fabrication process. We also found that gettering capability strongly dependence on oxygen impurity amount in hydrocarbon molecular ion implantation projection range. We believe that this novel silicon wafer can drastically contribute to the improvement of CMOS image sensor device performance such as white spot defect and dark current.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Development of Ni₂P Contact Technology and Its Integration on III-V
           Materials for 300 mm Si Photonics Platform

    • Authors: Flore Boyer;Romain Famulok;Stéphane Minoret;Nicolas Coudurier;Christophe Jany;Patrice Gergaud;Philippe Rodriguez;
      Pages: 728 - 736
      Abstract: In order to assess their potential use as contact layers for Si photonics devices, Ni2P thin films were developed on a 300 mm platform. The Ni2P layers, obtained by magnetron sputtering of a Ni2P target, were stable and reproducible. The films were mainly composed of the hexagonal Ni2P phase with small amount of Ni12P5 impurities. The film density was 6.9 g/cm3 with a ratio of 62 at.% of Ni and 38 at.% of P. We implemented and integrated these Ni2P films on III-V structures to study their electrical properties on n-InP and p-InGaAs (i.e., n-doped and p-doped III-V/Si hybrid laser contact layers). The results obtained on p-InGaAs did not meet the requirements in terms of contact resistivity. On the other hand, due to its high thermal stability and low contact resistivities, Ni2P metallization exhibited the best results among the Ni-based metallizations studied for contacting n-InP layers, namely Ni, NiPt and Ni2P.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Flash Memory and Its Manufacturing Technology for Sustainable World

    • Authors: Kazunari Ishimaru;Makoto Fujiwara;Hidenori Miyagawa;Yuta Aiba;
      Pages: 737 - 743
      Abstract: In today’s data-driven society, memory is an unavoidable component. IoT and 5G are accelerating data generation exponentially, and the demands of high-capacity memory are increasing. Flash memory is a crucial infrastructure component and inevitable for Data Center. The advantages of a Solid-State Drive over a Hard Disk Drive are power consumption and volume per giga-byte. Low power consumption of storage devices, which are components of the data center itself, is critical in reducing power consumption, which has become a primary social concern. This paper describes current efforts and future trends in storage devices and their manufacturing technologies for realizing a sustainable society. New device structure which increases storage capacity with significant reduction of both materials and process steps, environmentally friendly and efficient manufacturing technologies and future technologies under consideration for even higher capacity will be shown. These technological innovations will make it possible to realize a society that enriches people’s lives.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Interface Structures and Electrical Properties of Micro-Fabricated
           Epitaxial Hf-Digermanide/n-Ge(001) Contacts

    • Authors: Kentaro Kasahara;Kazuki Senga;Mitsuo Sakashita;Shigehisa Shibayama;Osamu Nakatsuka;
      Pages: 744 - 750
      Abstract: We investigated the interface crystalline structures and electrical conduction properties of epitaxial Hf-digermanide(HfGe2)/ ${n}$ -Ge(001) contacts with different electrode sizes of 20, 45, and $90~{mu }text{m}$ prepared via microfabrication. It was found that the microfabrication process improved the interface uniformity of the HfGe2/ ${n}$ -Ge(001) contacts. Detailed transmission electron microscopy analysis confirmed the growth of epitaxial HfGe2 on Ge(001) and implied that microfabrication suppressed the strain relaxation of HfGe2. These results imply that the applied strain of the epitaxial HfGe2, which was controlled via microfabrication in this study, is a possible parameter that may be used to improve the interface uniformity HfGe2/ ${n}$ -Ge(001) contacts. The Schottky barrier heights (SBHs) of the HfGe2/ ${n}$ -Ge(001) contacts estimated from the capacitance–voltage characteristics were small and in the range of 0.4 to 0.5 eV independent of the electrode size. Furthermore, considering the temperature dependence of the current density–voltage characteristics, we found that both the thermionic field emission current and the tunneling current through the interface dipole layer were possibly flowed in series and that the SBH for the $20~{mu }text{m}$ sample was 0.24 eV, whereas those for both the 45 and $90~{mu }text{m}$ samples were 0.31 eV.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Cathodoluminescence Study of Damage Formation and Recovery in
           Si-ion-implanted β-Ga2O3

    • Authors: Ryuichi Sugie;Tomoyuki Uchida;Ai Hashimoto;Seishi Akahori;Koji Matsumura;Yoshiharu Tanii;
      Pages: 751 - 756
      Abstract: Ion implantation and activation annealing are key processes in the creation of an ideal free carrier distribution in semiconductor devices. Ultra-wide-bandgap (UWBG) semiconductors, such as gallium oxide (Ga2O3) and aluminum nitride (AlN), have many advantages suitable for power-device applications. We implanted silicon (Si) at doses ranging from $1 times 10^{11}$ to $1 times 10^{15} mathrm{~cm}^{-2}$ into $beta-mathrm{Ga}_2 mathrm{O}_3$ (−201) wafers, and annealed them at 800 and 1000° C in N2 atmosphere. Secondary ion mass spectrometry (SIMS) and cathodoluminescence (CL) were used to evaluate the dopant profile and damage resulting from ion implantation. The CL intensity decreased rapidly with the dose. Even at a dose of $1 times 10^{11} mathrm{~cm}^{-2}$ , the intensity dropped by nearly half of its value for the bare wafer. The CL intensity recovered after annealing at all doses; however, the CL intensity did not fully recover even after annealing at 1000°C. Moreover, the CL-depth profile at a dose of $1 times 10^{15} mathrm{~cm}^{-2}$ after annealing at 1000°C showed pronounced intensity decay near the Si-diffused region. The CL-intensity decay was strongly correlated with Si diffusion. This phenomenon suggests that high-temperature annealing at high dose not only activates the Si dopant through the interaction of the interstitial Si and Ga vacancies but also causes interstitial Si atoms to diffuse into deeper regions. CL spectroscopy is very sensitive to the implantation da-age and can be used for optimization of ion implantation and annealing processes in $beta_{-mathrm{Ga}_2 mathrm{O}_3}$ .
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Study of Dopant Activation in Silicon Employing Differential Hall Effect
           Metrology (DHEM)

    • Authors: Abhijeet Joshi;Bulent M. Basol;
      Pages: 757 - 760
      Abstract: Differential Hall Effect Metrology (DHEM) technique was used to characterize highly n-type doped Si epi layers deposited on p-type Si wafers. Total dopant concentration, doping depth profile and post deposition annealing condition were changed for various sample sets and influence of such changes on the resistivity, mobility and carrier concentration depth profiles were studied. It was determined that samples annealed at 900 °C had higher activation compared to those annealed at 700 °C. Gradation in doping depth profiles did not result in similar gradation in resistivity values. Carrier concentration at the near-surface region was found to be lower in all samples. It is shown that electrical properties of films forming ultra-shallow junctions can be studied in detail and correlated with process parameters using DHEM data obtained at sub-nm depth resolution.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Monitoring of Dose Dependent Damage in MeV Energy Hydrogen Implanted
           Silicon by Photo-Modulated Reflectance Measurements

    • Authors: J. Szívós;L. Balogh;I. Rajta;G. U. L. Nagy;Z. T. Gaál;V. Samu;K. Takefumi;Z. Zolnai;
      Pages: 761 - 768
      Abstract: High-energy low-mass proton implantation achieved considerable interest in semiconductor technology, due to much deeper penetration of hydrogen ions into silicon as compared to common dopants, boron, phosphorous, and arsenic. Accordingly, monitoring the accumulation kinetics and stability of proton-implantation induced defects and their influence on the optical and electrical properties of Si achieved increased attention both in technological process control and scientific research. We show that photo-modulated-reflectance (PMR) is effective technique to measure very low defect concentrations in the ppb-ppm range in high energy proton implanted silicon. After ion irradiation, the as-implanted dilute damage structure may lead to long term changes of the defect distribution and the formation of defect compounds due to mobility of point defects at room temperature. Moreover, low-mass hydrogen atoms may move significantly faster at room temperature compared to heavier dopants. We show that PMR is capable to detect differences in implanted proton dose with high sensitivity in a wide dose range, and, on a longer time scale, allows to follow changes in free carrier generation and recombination processes through the measurement of the long term decay of the PMR signal which is related to the sample response based on electro-optic and thermo-optic effects. Our experiments may pave the way toward high precision process control of device structure fabrication which utilizes the high-energy hydrogen implantation step. Also, our aim is to gain insight into the main processes underlying the dose dependent change and long-term decay of the PMR signal in high energy proton implanted Si.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Characterization of Plasma Process-Induced Low-Density Defect Creation by
           Lateral Junction Leakage

    • Authors: Yoshihiro Sato;Satoshi Shibata;Takayoshi Yamada;Kazuko Nishimura;Masayuki Yamasaki;Masashi Murakami;Keiichiro Urabe;Koji Eriguchi;
      Pages: 769 - 777
      Abstract: In the design of ultralow leakage devices such as image sensors, it is necessary to understand the influence of low-density defects during plasma processing—plasma-induced physical damage (PPD)—on device performance. Defects created by plasma exposure act as carrier conduction sites and induce an increase in leakage (e.g., dark) current. This study proposes a PPD evaluation scheme for low-density defect assessments, specifically defects created in the lateral direction due to lateral stochastic straggling (lateral PPD). Two test structures were designed: a single device with a leakage current ( ${I} _{mathrm{ leak}}$ ) and a complementary metal-oxide-semiconductor image sensor (CIS) circuit with a dark current ( ${I} _{mathrm{ dark}}$ ). The energy level and density of defects distributed in the lateral direction were estimated using the Shockley–Read–Hall (SRH) model. The energy level ( ${E} _{mathrm{ t}}$ ) was derived using the SRH model from the temperature dependence of ${I} _{mathrm{ leak}}$ and ${I} _{mathrm{ dark}}$ defined as the activation energy ${E} _{mathrm{ a}}$ . The trap density ( ${N} _{mathrm{ t}}$ ) was also determined. A comprehensive comparison of these parameters was conducted. Both ${I} _{mathrm{ leak}}$ and ${I} _{mathrm{ dark}}$ are dependent on the contact opening diameter after plasma exposure, which implies the presence of defects in the lateral direction via lateral PPD. From the analysis of the temperature dependence of ${I} _{mathrm{ leak}}$ and ${I} _{mathrm{ dark}}$ , the lateral PPD influenced the mean value of ${E} _{mathrm{ a}}$ . Moreover, we confirmed that an increase in ${I} _{mathrm{ dark}}$ indicates an increase in the number of trap sites, and more specifically, an increase in defects at shallow levels. The derived trap site density in the CIS circuit was consistent with that of a single device. The proposed evaluation scheme is useful for PPD evaluation in the presence of low-density defects, and is critical for the design of future low-leakage devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Reliability Study of 1T1C FeRAM Arrays With Hf0.5Zr0.5O₂ Thickness

    • Authors: Jun Okuno;Takafumi Kunihiro;Kenta Konishi;Yusuke Shuto;Fumitaka Sugaya;Monica Materano;Tarek Ali;Maximilian Lederer;Kati Kuehnel;Konrad Seidel;Thomas Mikolajick;Uwe Schroeder;Masanori Tsukamoto;Taku Umebayashi;
      Pages: 778 - 783
      Abstract: We have reported that film thickness scaling of ferroelectric Hf0.5Zr0.5O2(HZO) allows hafnium-based one- transistor and one-capacitor (1T1C) ferroelectric random-access memory (FeRAM) to obtain higher cycling tolerance for hard breakdown with lower voltage operation in prior reports. This paper is an extension of the previous works including a review of recent works on FeRAM-related devices from a film thickness scaling point of view. We experimentally verified the cycling tolerance advantage of film thickness scaling by 1T1C FeRAM array with different HZO thicknesses of 8 nm and 10 nm using different small capacitors areas (0.20, 0.40, and $1.00~mutext{m}^{2}$ ) at practical operation conditions for the first time, demonstrating higher reliability at the 8-nm sample with smaller capacitance area. To support the result, time zero dielectric breakdown (TZDB) and time dependent dielectric breakdown (TDDB) were conducted for both 8-nm and 10a-nm samples.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Multilayer Crossbar Array of Amorphous Metal-Oxide Semiconductor Thin
           Films for Neuromorphic Systems

    • Authors: Etsuko Iwagi;Takumi Tsuno;Takahito Imai;Yasuhiko Nakashima;Mutsumi Kimura;
      Pages: 784 - 790
      Abstract: A multilayer crossbar array has been developed using amorphous metal-oxide semiconductor (AOS) thin films and implemented into a neuromorphic system. The multilayer structure can be realized, because the AOS thin films can be deposited by a simple sputtering method without heat treatment, which does not damage the underlying structures. First, Au thin films are deposited by vapor evaporation as electrodes, an amorphous In-Ga-Zn-O ( $alpha$ -IGZO) thin film is deposited by a sputtering method as a conductance change layer, these processes are repeated, and a multilayer crossbar array is completed, where each of the three conductance change layers is sandwiched between the electrodes. Next, the multilayer crossbar array is implemented into a neuromorphic system with modified Hebbian learning, which enables autonomous learning without control circuitry, and an associative memory function is confirmed, which guarantees the possibility of further advanced functions. These results lead to astronomical large-scale integration (LSI) of synaptic elements in neuromorphic systems in the future.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Hybrid Soldering 2.3D Assembly With High Reliability and Low Cost

    • Authors: Han-Wen Hu;Yu-Wei Huang;Yi-Chieh Tsai;Meng-Kai Shih;Kuan-Neng Chen;
      Pages: 791 - 796
      Abstract: In this study, an advanced 2.3D solution was proposed to integrate RDL interposer and FR-4 substrate using the technique of hybrid soldering, which applies printing of epoxy solder paste to form the hybrid joint. The simulation was performed to evaluate warpage and von Mises stress of different joint structures, indicating that the hybrid joint structure is promising for the reliability of 2.3D assembly. In addition, hybrid soldering 2.3D assembly was successfully demonstrated, followed by SEM analyses, electrical measurements, warpage measurements, and thermal cycling tests for 5000 cycles. The experimental results validate that the packaging can achieve high reliability without the needs of underfill. Thus, this solution paves the way for large area 2.3D integration with low cost, high throughput, and high reliability.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • An Accurate Approach to Develop Small Signal Circuit Models for AlGaN/GaN
           HEMTs Using Rational Functions and Dependent Current Sources

    • Authors: Aakash Jadhav;Takashi Ozawa;Ali Baratov;Joel T. Asubar;Masaaki Kuzuhara;Akio Wakejima;Shunpei Yamashita;Manato Deki;Shugo Nitta;Yoshio Honda;Hiroshi Amano;Sourajeet Roy;Biplab Sarkar;
      Pages: 797 - 807
      Abstract: In this paper, a technique to develop small signal circuit (SSC) models of AlGaN/GaN high electron mobility transistors (HEMTs) using dependent current sources is presented. In this technique, experimentally measured broadband Y-parameters of AlGaN/GaN HEMTs are mathematically modeled as a sum of pole-residue terms. By representing each pole-residue term as a dependent current source, it is possible to develop an accurate SSC models for HEMTs which otherwise may not be possible using passive resistive-inductive-capacitive elements. The accuracy of the proposed SSC model is validated against the conventional SSC model using a 2nd, 3rd and 4th order rational function representation of the admittance branches of AlGaN/GaN HEMTs. Therefore, the proposed SSC model turns out to be highly robust in nature and can take care of any form of the transfer functions of the admittance branches between the gate, drain, and source terminal of an AlGaN/GaN HEMT.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • High-Voltage Polarization-Superjunction GaN HEMT With Built-In SBD for Low
           Reverse Conduction Loss

    • Authors: Tao Sun;Kemeng Yang;Jie Wei;Yanjiang Jia;Siyu Deng;Zhijia Zhao;Bo Zhang;Xiaorong Luo;
      Pages: 808 - 812
      Abstract: A GaN Reverse-Conducting HEMT (RC-HEMT) is proposed and fabricated on the GaN/AlGaN/GaN platform. It features an integrated Schottky barrier diode (SBD) to realize reverse conduction and the double-heterojunction to enhance breakdown voltage (BV). Compared with the inherent reverse conduction capability of the conventional HEMT (Con. HEMT), the built-in SBD exhibits a low reverse turn-on voltage ( $V_{text{RT}}$ ) and its $V_{text{RT}}$ is independent of the threshold voltage and gate bias. At the off-state, the fixed positive and negative polarization charges form the polarization superjunction (PSJ). Therefore, the depletion region is extended and more uniform E-field distribution is obtained. Experimental results show that the RC-PSJ-HEMT achieves a low $V_{text{RT}}$ of 0.68 V, which decreases 69.1% compared with that of the Con. HEMT. The BV of the RC-PSJ-HEMT (with $7.5 mu text{m}$ $V_{text{GD}}$ ) is increased to 723 V from 202 V of the Con. HEMT.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory

    • Authors: Jung Nam Kim;Jaehong Lee;Jo Eun Kim;Suck Won Hong;Minsuk Koo;Yoon Kim;
      Pages: 813 - 820
      Abstract: In this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neural network on a limited-size hardware chip. We designed a full array architecture including a stacked layer selection circuit. In addition, we investigated the synaptic characteristics of CTF device by using technology computer-aided design (TCAD) simulation. We demonstrated the feasibility of the synapse array for neural network accelerators through a system-level MATLAB simulation with the Modified National Institute of Standards and Technology (MNIST) database.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Low-Temperature Solution-Processed All Organic Integration for Large-Area
           and Flexible High-Resolution Imaging

    • Authors: Xiao Hou;Sujie Chen;Wei Tang;Jianghu Liang;Bang Ouyang;Ming Li;Yawen Song;Tong Shan;Chun-Chao Chen;Patrick Too;Xiaoqing Wei;Libo Jin;Gang Qi;Xiaojun Guo;
      Pages: 821 - 826
      Abstract: A facile blade-coating process is developed for large area deposition of uniform thick organic active layers in organic photodiodes (OPDs). Large-area semi-transparent top metal electrodes are thermally evaporated with an optimal deposition rate to achieve good balance between transparency and conductivity for top illumination integration structure with the organic thin-film transistor (OTFT) backplane. The maximum process temperature of the OPD is 85 °C, so that the performance of the OTFT underneath is not affected. Based on the developed integration structure and processes, an all-organic integrated flexible active-matrix imager is developed, having the largest size (130 mm ${times } 130$ mm), highest resolution ( $1536 {times } 1536$ pixels, 300 ppi) and lowest process temperature (100 °C) reported so far for the OPD based imagers.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Explore Luminance Attenuation and Optical Crosstalk of RGB Mini
           Light-Emitting Diode via Microscopic Hyperspectral Imaging

    • Authors: Lili Zheng;Ziquan Guo;Yijun Lu;Peixin Zeng;Shouqiang Lai;Guolong Chen;Yulin Gao;Lihong Zhu;Weijie Guo;Yi Lin;Zhong Chen;
      Pages: 827 - 832
      Abstract: In this article, we experimentally and quantitatively investigate the luminance attenuation for red, green, and blue mini light-emitting diodes (LEDs), and the optical crosstalk in the RGB mini-LED array under different working currents via the microscopic hyperspectral imaging technique. The evaluation metrics of luminance attenuation for one single mini-LED subpixel and luminance influence among all three colored mini-LEDs are well defined to quantitatively describe the optical crosstalk among three mini-LED subpixels in the array. We also compare the size-dependent behaviors of luminance attenuation for blue and green mini-LEDs with an emission peak of about 465 nm and 529 nm, respectively. The minimum pixel pitch of blue and green mini-LEDs with different chip sizes is obtained through optical simulation based on LightTools software, so that the optical crosstalk can be reduced. Finally, we believe that this study could provide a useful guidance for selecting suitable working current conditions while driving the mini-LED display with suitable pixel size and pixel pitch to reduce both the optical and color crosstalk in the mini-LED display.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • MPT Tool: A Parameter Extraction Tool for Accurate Modeling of Magnetic
           Tunnel Junction Devices

    • Authors: Manman Wang;Yanfeng Jiang;
      Pages: 833 - 842
      Abstract: Until now, many models of magnetic tunnel junction (MTJ) devices have been reported in the literatures, which are very helpful for behavior simulations in spintronic circuit design and simulation. However, there are few reports on how to obtain the accurate modeling parameters, as well as the accurate simulation of the complete flow from device parameters to device modeling and hybrid MTJ/CMOS circuits. One of the difficulties in obtaining the accurate MTJ modeling results is the lack of experimental parameters. The parameters in the MTJ models should be precisely identified to obtain accurate simulation results. However, in the reported models, many parameters are theoretically set instead of actual extraction. In this paper, a parameter extraction tool, named MPT tool, is proposed for the accurate modeling of the MTJ devices. In the MPT tool, the measured results of the MTJ devices are adopted as the input. There are two main functions of the MPT tool. One is the parameter extraction based on the input experimental results. The other is the parameter optimization based on the specific algorithm. In the tool, the simulated annealing (SA) optimization algorithm is applied to optimize the extracted parameters. The parameters of the extraction procedure and the modeling results based on the parameters of the optimization procedure are compared with the experimental data, respectively. The proposed extraction procedure and the optimization procedure together with the adopted MTJ model is as an efficient approach to improve the accuracy of the simulation result.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Direct-Triggering LTT With Monolithic Structure

    • Authors: Jinchao Yin;Yujie Bai;Kai Shi;Guipeng Liu;Ming Zhou;Jianhong Yang;
      Pages: 843 - 846
      Abstract: Light-triggered thyristor (LTT) has attracted considerable interest in power conversion and control systems because of its strong anti-interference ability and large power capacity. In this work, we propose a monolithic LTT that can be light-triggered directly without an amplifying gate (AG) design, to improve the device reliability and operating speed. The cathode structure is redesigned into an interdigitated structure with a relatively large light-incident area. The cathode shorts are re-arranged to balance the trigger intensity and the light incident depth, so as to ensure optimal $text{d}{V}/text{d}{t}$ capability. Devices are fabricated and adequate performances are obtained, verifying the feasibility of our design.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • The Gold Nanoparticles Enhanced ZnO/GaN UV Detector

    • Authors: Wenqing Song;Xiaobiao Dai;Yingkun He;Tao Li;
      Pages: 847 - 853
      Abstract: Ultraviolet detectors can be used in ultraviolet disinfection, missile guidance and short-wave communication fields. Here we have grown GaN (002) film by chemical vapor deposition (CVD), through depositing 100 nm ZnO film as buffer layers on sapphire substrates by magnetron sputtering. Using Ni as the electrode, the metal-semiconductor-metal (MSM) ultraviolet (UV) detector was prepared. The device dark current, photocurrent and UV on/off current ratio were $5.19 times 10^{-9}text{ A}$ , $2.52 times 10^{-7}text{A}$ and 54, under 2V bias. Then, using Au nanoparticles as plasmons, the photocurrent and photoresponsivity of the device were increased by 5.32 times and 5.25 times, respectively, and the UV on/off current ratio reached 176. The photoresponsivity of the device reaches the maximum value 0.42A/W at 370nm, the response time and relaxation time reach 0.1s and 0.12s, respectively.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • The Impact of Width Downscaling on the High-Frequency Characteristics of
           InGaAs Nanowire FETs

    • Authors: P. Huang;Q. H. Luc;A. Sibaja-Hernandez;H. L. Ko;J. Y. Wu;N. A. Tran;N. Collaert;E. Y. Chang;
      Pages: 854 - 859
      Abstract: This work demonstrates the high-frequency characteristics of In0.53Ga0.47As nanowire with scaled wire width by implementing TCAD simulations. The physical models and correlated parameters have been calibrated to the experiments (Ko et al., 2022). As the width of the nanowire is scaled to 10 nm, the electron density peaks are no longer located close to the oxide/semiconductor interface. Instead, the peaks merge and volume inversion effects appear due to the strong quantum confinement. The volume inversion effects lead to higher cut-off frequency due to the reduced total transport delay time. To have a better understanding of this phenomena, the high-frequency properties of nanowire were quantified with the assistance of small-signal analysis and delay time analysis using TCAD. It is found that the channel charging delay increases with narrower wire width due to the raise of source/drain resistance. Regarding the extrinsic and intrinsic delay, they increase with smaller wire width and drop at width of 10 nm due to the volume inversion effects. Electron distribution which aims to clarify the above-mentioned observation is also plotted.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Guest Editorial Special Section on EDTM 2022

    • Authors: Masumi Saitoh;
      Pages: 860 - 860
      Abstract: This Special Issue of the IEEE Journal of the Electron Devices Society is a selection of papers presented at the 2022 IEEE Electron Devices Technology and Manufacturing (EDTM) Conference. EDTM Conference was established by the IEEE Electron Devices Society (EDS) to enable further performance/functionality enhancement of semiconductor devices and systems with manufacturing innovations to overcome scaling challenges. EDTM provides the premier global forum for researchers and engineers from around the world coming to share new discoveries and discuss about any device/manufacturing-related topics, including but not limited to, materials, processes, devices, packaging, modeling, reliability, manufacturing and yield, tools, testing, and any emerging device technologies, as well as workforce training. EDTM rotates among Asian countries where hot-hubs of semiconductor manufacturing are located. The 6th EDTM Conference (EDTM 2022) was successfully held during March 6-9, 2022. The Theme for EDTM 2022 was Semiconductor Devices and Manufacturing Innovations for a More Sustainable World. Although EDTM 2022 was originally planned to be held in Oita, where many semiconductor companies have facilities, and called as silicon island in Japan, the conference was actually held in the fully virtual format with live sessions due to the pandemic. EDTM2022 was a four-day conference comprising a one-day tutorial/short course and a three-day technical program including 66 regular papers, 72 invited papers, 5 plenary talks, and a keynote lecture on the asteroid explorer. Special sessions on integrated materials were also held. This time we selected 8 excellent papers for the J-EDS special issue on EDTM 2022. We hope you enjoy the latest achievements on innovative technologies.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Stochastic Leaky-Integrate-and-Fire Neuron Model With Floating
           Gate-Based Technology for Fast and Accurate Population Coding

    • Authors: Akira Goda;Chihiro Matsui;Ken Takeuchi;
      Pages: 861 - 869
      Abstract: An analytical model has been developed for stochastic leaky-integrate-and-fire (LIF) neurons with floating gate (FG) technology. The stochastic behaviors have been modeled extensively for both individual neurons and populations of neurons. In the FG LIF neurons, the electron injection is governed by the tunneling process through the gate oxide, leading to the exponential distributions of the injection time and inter spike interval (ISI) stochasticity. The concept of the population coding is demonstrated by simulating the stochastic behaviors of the populations of the FG LIF neurons. The ISI stochasticity enables encoding of the input signals to the population outputs. Spike-to-spike stochasticity improves the signal-to-noise ratio of the population outputs. Moreover, the shape of the ISI distribution can be controlled by adjusting the number of electrons to spike (NES). Exponential-like ISI distributions are realized by reducing the NES. With the exponential-like ISI distributions, the population of fast spiking neurons increases significantly (more than 10% of neurons spiking twice faster than the mean ISI), potentially contributing to the fast computation. Finally, step-by-step procedures have been proposed to design the FG LIF neurons exhibiting the desired neuron characteristics including operation voltage (0.5 V to 3 V), leaky time constant $( { < } 1~ {mathrm {mu }}text{s}$ to >10 ms), ISI mean (in the range of 6 orders of magnitude) and stochasticity ~0 % to ~60 %) as well as the type of the distribution (exponential-like to Gaussian-like).
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Application of e-Beam Voltage Contrast Technique for Overlay Improvement
           and Process Window Control in Multi-Patterning Interconnect Scheme

    • Authors: Linrong Yang;Runling Li;Ikai Hsu;Haiqiong Zhang;Jiadong Ren;Wenzhan Zhou;Linlin Sun;Yawen Xue;Wenchao Yang;Ruilin Zhang;Yefang Zhu;Yan Zhang;Guifeng Zhang;Yingying Fu;Shan Yin;Yujie Jia;Bo Yu;Tomasz Brozek;
      Pages: 870 - 875
      Abstract: Interconnect development for the new technology node requires coordinated efforts of multiple module teams working to co-optimize patterning and metallization solutions to meet performance and yield, and reliability targets. This paper presents the results of interconnect patterning optimization to improve overlay and process window control using a novel methodology, Design-for-Inspection™ (DFI). Using design-assisted voltage contrast measurement techniques, the method enables in-line test and monitoring of process induced overlay and CD variation of back-end-of line (BEOL) features built with litho-etch-litho-etch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned directly, other combination of metal line and via colors may have uncontrolled misalignment risking open or short failures. The paper shows how the complete metrology coverage of multi-color combinations between dual patterned via and dual patterned metal lines helps driving the improvement of overlay and process margins in 14nm technology. The optimized process margin for via opens enables higher yields and better reliability.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Area-Efficient Power-Rail ESD Clamp Circuit With False-Trigger Immunity in
           28nm CMOS Process

    • Authors: Zilong Shen;Yize Wang;Xing Zhang;Yuan Wang;
      Pages: 876 - 884
      Abstract: In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid trigger mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed power clamp circuit is capable of achieving $mu text{s}$ -level transient response time with RC time constant of only 10 ns, thus greatly improving area efficiency. Compared to traditional transient circuit with same response time, the proposed one achieves a trigger circuit (TC) area reduction of over 90%. The proposed circuit achieves strong false-trigger immunity under fast power-on conditions. In addition, the circuit also has low standby leakage current of less than 10 nA at different BigFET widths. To verify the proposed circuit, the simulation and test results are analyzed in detail for this paper.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • A Retina-Inspired Image Sensor Array Based on Randomly-Accessible Active
           Pixel Sensor

    • Authors: Qi Yang;Zhenhao Feng;Chao Gao;Xiaolin Liu;Yihong Qi;Qian Li;Kuiren Su;Kai Wang;
      Pages: 885 - 892
      Abstract: Human retina is by nature a superior image sensor with a high sensitivity, wide dynamic range as well as low power consumption. In this paper, an image sensor array based on randomly-accessible active pixel design is studied where to mimic retinal photoreceptor, a photodiode-body-biased MOSFET (PD-MOS) with an adjustable gain of 10–420000 (higher than 105), a wide dynamic range of 140 dB and a spectral responsibility of 3-25000A/W from near UV to near IR wavelengths, is proposed. The image sensor array can capture images under light intensity ranging from 10nW/cm2 to 3mW/cm2 and its dynamic range is approximately 110dB.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Temperature Driven Current–Voltage Characteristics of Ionic Liquid Type
           Intelligent Connection Device

    • Authors: Masakazu Kobayashi;Yasumitsu Orii;Hisashi Shima;Yasuhisa Naitoh;Hiroyuki Akinaga;Dan Sato;Takuma Matsuo;Kentaro Kinoshita;Toshiki Nokami;Toshiyuki Itoh;
      Pages: 893 - 897
      Abstract: The temperature dependence of an intelligent connection (IConnect) device, in which an ionic liquid (IL) plays an essential role in a memristive function is presented in this study. An appropriate choice of IL and dissolved metal ion species can control the volatility of the IL-IConnect device. The temperature dependence of the IL-IConnect device was strong, although the change in current–voltage characteristics was reversible in response to temperature variations. The device’s potential as a physical reservoir-computing device is studied.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Liquid Metal-Based Microfluidic Metasurface for Controllable
           Electromagnetic Wave Reflection Attenuation

    • Authors: Xu Gao;Ping Li;Zhou Yang;Lingchun An;Zhenhai Wang;Jiarui Guo;Nuo Xu;Wei Wang;
      Pages: 898 - 906
      Abstract: We demonstrated a liquid metal based microfluidic chip that enabled consistent, continuous and large liquid metal unit structure array reconfiguration. The chips were assembled into a metasurface, which preliminary achieved controllable electromagnetic wave reflection attenuation. The chip contained a $5{times }6$ Galinstan split-ring resonator (SRR) array, and the SRRs could be reconfigured continuously by NaOH solution pressure driven. A fin shaped microvalve was designed and integrated onto the chip, which could withstand a high fluid driving pressure (over 210 kPa), so the SRRs could be reconfigured with a large split angle. The flow resistance of each SRR chamber was analyzed for consistent and robust SRRs deformation. The SRRs enabled more than 250° reconfiguration and showed consistent deformation with a standard derivation less than 8.5°. The metasurface showed 7.5 dB and 13.5 dB attenuation at 3 GHz and 4 GHz respectively. Also, with the different split angles, there could be three attenuation peaks that reach −10 dB when the frequency ranged from 2.9–3.1 GHz, 3.7–4.2 GHz and 4.8–5.0 GHz, respectively. The metasurface we proposed can be potentially used in multiband controllable electromagnetic wave absorption.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • BEOL Integrated Ferroelectric HfO₂-Based Capacitors for FeRAM:
           Extrapolation of Reliability Performance to Use Conditions

    • Authors: R. Alcala;M. Materano;P. D. Lomenzo;L. Grenouillet;T. Francois;J. Coignus;N. Vaxelaire;C. Carabasse;S. Chevalliez;F. Andrieu;T. Mikolajick;U. Schroeder;
      Pages: 907 - 912
      Abstract: Si doped HfO2 based ferroelectric capacitors integrated into Back-End-Of-Line (BEOL) 130 nm CMOS technology were investigated in regard to critical reliability parameters for their implementation in non-volatile one-transistor one-capacitor ferroelectric random-access memory applications. The assessed reliability parameters are electric field, capacitor area, and temperature and are evaluated on single and parallel structured capacitors to understand their respective impact on wake-up, fatigue, imprint, and retention.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

    • Authors: Soumajit Ghosh;M. Miura-Mattausch;T. Iizuka;Hafizur Rahaman;H. J. Mattausch;
      Pages: 913 - 919
      Abstract: Adaptive threshold-voltage controlling of thin-film multi-gate (MG) MOSFETs, using independent back-gate biasing, is applied for realizing latency and power optimization. The controlling-method validity for low-voltage operation is analyzed with the compact model HiSIM-MG, considering all internally induced charges specific for MG controlling. Current-drivability degradations, due to back-gate-charge contribution under positively-biased back-gate voltage and existence of an optimized operating condition, are confirmed. The optimized operating condition is shown to keep the back-gate charge under the weak inversion with a corresponding relatively small back-gate charge. It is also demonstrated, that an input-voltage optimization accompanies the back-gate-voltage optimization, sustaining the optimized low power loss with low input voltage. Circuit-performance improvement of 27% by about 30% reduction of substrate thickness, while keeping switching-power loss small, is also verified.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Characterization of Oxide Trapping in SiC MOSFETs Under Positive Gate Bias

    • Authors: Ye Liang;Yuanlei Zhang;Jingqun Zhang;Xiuyuan He;Yinchao Zhao;Miao Cui;Huiqing Wen;Mingxiang Wang;Wen Liu;
      Pages: 920 - 926
      Abstract: SiC MOSFETs devices with double-trench dominate the market due to their low on-resistance. However, studies on its temperature-dependent properties are not comprehensive. This work uses fast I-V and static I-V techniques to explore the location of electrons trapped in the device under moderate gate stress. Threshold voltage instability ( ${mathrm {V}}_{mathrm {TH}}$ hysteresis and $Delta{mathrm {V}}_{mathrm {TH}}$ ) and on-resistance degradation ( $Delta{mathrm {R}}_{mathrm {ON}}$ ) are used to characterize oxide trapping. Although the observation method is different, it can be found that the ${mathrm {V}}_{mathrm {TH}}$ instability and ${mathrm {R}}_{mathrm {ON}}$ degradation increase linearly with logarithmic time over a wide time range from $100~mu{mathrm {s}}$ to 104 s, suggesting that the direct tunneling mechanism dominates the electrons trapping in the oxide near the SiO2/SiC interface. The interface trap density is $3.8times 10^{12}$ cm−2 $cdot$ eV−1. In addition, a negative temperature dependence is shown in the test, and the fitting parameter $gamma$ from 0.16 to 0.18 indicated that these traps are concentrated in the oxide layer. These traps’ energy level at 0.68 eV below the conduction band was obtained in the recovery phase through the Arrhe-ius plot.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improvement in Instability of Transparent ALD ZnO TFTs Under Negative Bias
           Illumination Stress With SiO/AlO Bilayer Dielectric

    • Authors: Wanpeng Zhao;Ning Zhang;Xinyu Zhang;Chong Yao;Junfeng Zhang;Shurong Dong;Yang Liu;Zhi Ye;Jikui Luo;
      Pages: 927 - 932
      Abstract: The theory of oxygen vacancy related deep energy defects and valence band offset (VBO) between gate insulator and channel codetermining the threshold voltage shift $(Delta {V}_{mathbf {mathrm {TH}}})$ of ZnO thin film transistor under negative gate bias and illumination stress (NBIS) is proposed and investigated systematically. Two kinds of ZnO thin film transistors are fabricated by atomic layer deposition with different gate oxide structures, a control sample with Al2O3 gate oxide and an improved sample with SiO2/Al2 ${text{O}}_{3 }$ gate oxide structures. Among two kinds of devices, the device with SiO2/Al2 ${text{O}}_{3 }$ gate oxide achieves a smaller $mathbf {mathrm {Delta }}{V}_{mathbf {mathrm {TH}}}$ under the NBIS with SiO2 thin film acting as a holes-blocking layer, despite the existence of more defects than control device. The improvement in stability is attributed to large VBO up to 3.08 eV. Moreover, the device with SiO2/Al2 ${text{O}}_{3 }$ gate oxide is evaluated on a 500-nit LCD back light to simulate the practical working environment in displays, which exhibits good stability of ${mathbf {Delta }{V}}_{mathbf {mathrm {TH}}},,=,,-0.3$ V for 3600 seconds.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • -GaO Field Plate Schottky Barrier Diode With Superb Reverse Recovery for
           High-Efficiency DC–DC Converter

    • Authors: Wei Guo;Guangzhong Jian;Weibing Hao;Feihong Wu;Kai Zhou;Jiahong Du;Xuanze Zhou;Qiming He;Zhaoan Yu;Xiaolong Zhao;Guangwei Xu;Shibing Long;
      Pages: 933 - 941
      Abstract: β-Ga2O3 Schottky barrier diodes with field plate (FP-SBDs) are fabricated and their SPICEcompatible model are constructed for double-pulse test circuit and DC-DC boost converter simulations. The reverse recovery time ( $t_{{mathrm {rr}}}$ ) of the β-Ga2O3 SBD is 8.8 ns and its reverse recovery charge ( $Q_{{mathrm {rr}}}$ ) is 8.33 nC when switching from a forward current of 1 A to a reverse bias voltage of 100 V with a di/dt of 400 A/μs, which is analogous with the prediction of our model. Device with the radius of 500 μm was fabricated, a current of 2 A can be obtained at the forward voltage of 2 V, meanwhile, the breakdown voltage is 467 V. The Ga2O3-based converter module after device packaging with TO-220 reveals a comparative efficiency to that of the SiC-based converter under multiple conditions, and reached up to 95.62% at the input voltage of 200 V. The decent performance of Ga2O3 FP-SBD and its DC-DC converter indicates great potential in power application.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Low Interface Trapped Charge Density for AlO/β-GaO (001)
           Metal-Insulator-Semiconductor Capacitor

    • Authors: Qihao Zhang;Yisong Shen;Jiangwei Liu;Chunming Tu;Dongyuan Zhai;Min He;Jiwu Lu;
      Pages: 942 - 946
      Abstract: In this letter, high-performance Al2O3/ $beta$ -Ga2O3 (001) metal-insulator-semiconductor (MIS) capacitor has been demonstrated. The capacitance-voltage (C–V) curves of the Al2O3/ $beta$ -Ga2O3 (001) MIS capacitor remain stable under different measurement frequencies. The leakage current density is lower than $2.0 times 10^{-8}$ A/cm2 when the gate voltage is in the range of −5~13 V. The fixed charge and trapped charge densities in Al2O3 film are $4.4 times 10^{12}$ and $6.0 times 10^{11}$ cm−2, respectively. Average and minimum interface trapped charge density ( ${mathrm {D}}_{it}$ ) for Al2O3/ $beta$ -Ga2O3 (001) interface has been extracted to be as low as $3.3 times 10^{11}$ and $2.3 times 10^{11}$ cm−2 eV−1 via the Terman method, respectively. The low ${mathrm {D}}_{it}$ is probably attributed to the modification of vacancy defects and the introduction of hydroxyl groups at the Al2O3/ $beta$ -Ga2O3 (001) interface after piranha solution pretreatment for $beta$ -Ga2O3.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Ferroelectric Polarization Enhancement in Hafnium-Based Oxides Through
           Capping Layer Engineering

    • Authors: Hsuan-Han Chen;Ruo-Yin Liao;Wu-Ching Chou;Hsiao-Hsuan Hsu;Chun-Hu Cheng;Ching-Chien Huang;
      Pages: 947 - 952
      Abstract: In this work, we investigate that the capping layer (CL) engineering of aluminum oxide (AlOx) on the dopant-free hafnium oxide (HfOx) and the hafnium zirconium oxide (HfZrOx) ferroelectric metal-ferroelectric-metal (MFM) capacitors. The AlOx CL featuring large bandgap and excellent thermal stability offers a stable interface favorable for ferroelectric phase transition. Therefore, the ferroelectric polarization and high-temperature leakage current of HfZrOx MFM capacitor can be largely improved due to the combination of zirconium doping and AlOx capping effect. From the analysis of interface thermodynamic stability and leakage current mechanism, the AlOx CL effectively alleviates interface defect traps between electrode and ferroelectric HfZrOx, which lowers high-temperature leakage current, reduces ferroelectric domains pinning, enhances ferroelectric polarization, and stabilizes the long-term endurance cycling.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Pelgrom-Based Predictive Model to Estimate Metal Grain Granularity and
           Line Edge Roughness in Advanced Multigate MOSFETs

    • Authors: Julian G. Fernandez;Natalia Seoane;Enrique Comesaña;Antonio García-Loureiro;
      Pages: 953 - 959
      Abstract: The impact of different variability sources on the transistor performance increases as devices are scaled-down, being the metal grain granularity (MGG) and the line edge roughness (LER) some of the major contributors to this increase. Variability studies require the simulation of large samples of different device configurations to have statistical significance, increasing the computational cost. A novel Pelgrom-based predictive (PBP) model that estimates the impact of MGG and LER through the study of the threshold voltage standard deviation $left(sigma V_{T h}right)$ , is proposed. This technique is computationally efficient since once the threshold voltage mismatch is calculated, $sigma V_{T h}$ can be predicted for different gate lengths $left(L_{g}right)$ , cross-sections, and intrinsic variability parameters, without further simulations. The validity of the PBP model is demonstrated for three state-of-the-art architectures (FinFETs, nanowire FETs, and nanosheet FETs) with different $L_{g}$ , cross-sections, and drain biases $left(V_{D}right)$ . The relative errors between the predicted and simulated data are lower than 10%, in the 92% of the cases.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Comprehensive Study of Inversion Capacitance in
           Metal-Insulator-Semiconductor Capacitor With Existing Oxide Charges

    • Authors: Kung-Chu Chen;Kuan-Wun Lin;Sung-Wei Huang;Jian-Yu Lin;Jenn-Gwo Hwu;
      Pages: 960 - 969
      Abstract: The impact of oxide charges on the metal-insulator-semiconductor (MIS) device’s capacitance $({C})$ and conductance $({G})$ was studied in this work. A model to calculate MIS device’s ${C}$ and ${G}$ under the considerations of oxide charges, doping concentration, device dimension, and AC signal frequency $(omega)$ was proposed. A relation of ${C}-{C}_{textrm {D}}propto omega ^{-0.5}$ was found, where ${C}_{textrm {D}}$ is the depletion capacitance under the electrode. The relation is examined by the experimental and the TCAD simulation. The capacitance of a MIS device with oxide charges can be calculated according to the proposed model and is well-matched with the TCAD simulation under light to moderate doping concentration. For heavily doped substrates, the modeling deviates from the simulation results because of quantum confinement and concentration-dependent mobility. However, the trend of the capacitance value is still able to be estimated by our modeling. From the modeling, it was found that for $Q_{textrm {ox}}/textrm {q}=7.5times 10^{10} textrm {cm}^{textrm {-2}}$ , the MIS capacitor with substrate doping concentration $N_{textrm {A}}=1times 10^{15} textrm {cm}^{textrm {-3}}$ exhibits a long lateral AC signal decay length of $52~mu text{m}$ at 1 kHz under the inversion region. The findings of this work are fundamental and are helpful for device engineering.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Graphene–Silicon Diode for 2-D Heterostructure Electrical Failure

    • Authors: Muhammad Abid Anwar;Munir Ali;Dong Pu;Srikrishna Chanakya Bodepudi;Jianhang Lv;Khurram Shehzad;Xiaochen Wang;Ali Imran;Yuda Zhao;Shurong Dong;Huan Hu;Bin Yu;Yang Xu;
      Pages: 970 - 975
      Abstract: Two-dimensional materials have modernized a broad interest in electronic devices. Along with many advantages, their atomic-level thickness makes them sensitive under high electrical stress. This work proposes a protection design using a Graphene/Silicon (Gr/Si) Schottky diode as the protective device, which helps to improve the endurance for unwanted fluctuations in operating voltage of 2D heterostructure-based devices. In this scheme, the 2D heterostructure was configured parallel with the protective device (Gr/Si diode) for electrical measurements. It was found that Gr/Si diode handles a large portion of initial surge current peaks, which significantly increases the durability and lifetime of 2D material-based heterostructure devices. This scheme potentially bridges mature CMOS technology and novel 2D-based heterostructure applications for robust futuristic devices.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Experimental Investigation and Model Analysis on a GaN Electrostatic
           Discharge Clamp

    • Authors: Yijun Shi;Zhiyuan He;Yun Huang;Zongqi Cai;Yiqiang Chen;Chang Liu;Chao Liu;Wanjun Chen;Ruize Sun;Guoguang Lu;
      Pages: 976 - 982
      Abstract: This work carried out the experimental investigation and model analysis on a GaN electrostatic discharge (ESD) clamp, which features a discharge high electron mobility transistor (HEMT) and a voltage divider formed by a lateral field effect rectifier (L-FER) chain and a resistor in series. Firstly, it is found through the experimental investigation, the turn-on voltage ( $V_{mathrm {T}}$ ) of GaN ESD clamp’s static current is increased with the increase in L-FER’s number and the decrease in resistor’s value. Then, an analytical model is proposed to analyze the dependence of $V_{mathrm {T}}$ on L-FER’s number and resistor’s value. And the analytical model exhibits a good consistency with the experimentally measured results, which confirms the validity of the presented analytical model. Lastly, the dependence of GaN ESD clamp’s transmission line pulsing characteristics on the L-FER’s number and resistor’s value is also analyzed. Similarly, GaN ESD clamp’s triggering voltage is also increased with the increase in L-FER’s number and the decrease in resistor’s value. The experimental investigation and model analysis of this work can be used to direct the design of GaN ESD clamp, and help to save a lot of manpower, material resources and time costs.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • The Drift Region Width Modulation Technique for Breakdown Performance
           Enhancement of AlGaN/GaN HEMT

    • Authors: Jianhua Liu;Jun Zhang;Jiafei Yao;Man Li;Jing Chen;Maolin Zhang;Xiaoming Huang;Chenyang Huang;Weihua Tang;Yufeng Guo;
      Pages: 983 - 988
      Abstract: The breakdown performance of the AlGaN/GaN high electron mobility transistor (HEMT) is limited by the high electric field peaks in the device. To obtain a more uniform electric field distribution, the drift region width modulation (DWM) technique is proposed to reshape the charge distribution between the gate and drain electrodes. By applying the Gaussian box method, an effective designing guidance for the structure optimization of the AlGaN/GaN HEMT with adaptive-width drift region pillars (AWD-HEMT) is obtained. The fabricated AWD-HEMT demonstrated a significant improvement in breakdown performance. The Baliga’s figure of merit (BFOM) of AWD-HEMT improved 65.3% compared with the conventional HEMT, without introducing complicated processes. In addition, the mechanism of the AWD-HEMT is explored by numerical methods. The simulations indicate that a more uniform electric field distribution at AlGaN/GaN interfaces could be obtained, and the increased varying rate of the adaptive-width drift region (AWD) pillars results in a more obvious electric field modulation effect.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • The Effect of Deep JFET and P-Well Implant of 1.2kV 4H-SiC MOSFETs

    • Authors: Dongyoung Kim;Nick Yun;Adam J. Morgan;Woongje Sung;
      Pages: 989 - 995
      Abstract: 1.2kV 4H-SiC MOSFETs with different junction depths of JFET and P-well regions were fabricated. For each JFET/P-well depth combination, channel lengths and JFET widths were also varied to compare specific on-resistance, breakdown voltage, and short-circuit withstand time. It was discovered that deep JFET structure provides low specific on-resistance (12% lower) with high breakdown voltage. On the other hand, MOSFETs with deep P-well result in high breakdown voltage with low leakage current even in shorter channel length (0.4 $mu$ m). Moreover, trade-off relationship between Ron,sp and short-circuit withstand time is discussed for MOSFETs with different JFET widths and channel lengths; the deep JFET implant provides better trade-off relationship due to the feasibility of narrow JFET width. For the further improvement of trade-off relationship, MOSFETs with deep JFET and P-well implant are proposed. Lastly, the importance of high channel mobility for not only static characteristics but also short-circuit characteristics was investigated. The in-depth understanding of measured electrical characteristics was supported by 2D-device simulations.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improved Ferroelectricity in Cryogenic Phase Transition of Hf0.5Zr0.5O2

    • Authors: Yifan Xing;Yu-Rui Chen;Jer-Fu Wang;Zefu Zhao;Yun-Wen Chen;Guan-Hua Chen;Yuxuan Lin;Rachit Dobhal;C. W. Liu;
      Pages: 996 - 1002
      Abstract: Cryogenic transition from metastable tetragonal phase (t-phase) to orthorhombic phase (o-phase) is crucial in achieving the desired ferroelectric characteristics. Observing the reversible transition from anti-ferroelectricity (AFE) to ferroelectricity (FE) in electrical characteristics, the cryogenic phase transition is experimentally analyzed in Hf0.5Zr0.5O2 alloys. Furthermore, the stabilized o-phase formation is more favorable when applying cryogenics to superlattice Hf0.5Zr0.5O2, manifesting a 23% increase in remanent polarization (Pr) at 77K. To theoretically clarify the emergence of phase transition with decreasing temperatures, Landau–Ginzburg–Devonshire theory and first-principle study are combined in this work. Based on the detailed calculation, the increasing relative free energy of the t-phase contributes to lowering the energy barrier when decreasing the temperature, making the convenient transitional pathway from metastable t- to o-phase. This work exhibits the cryogenic phase transition model involving t- and o-phases in Hf0.5Zr0.5O2 and presents a method to boost ferroelectricity for emerging HfO2-based cryo-device.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Demonstration of Vertical GaN Schottky Barrier Diode With Robust
           Electrothermal Ruggedness and Fast Switching Capability by Eutectic
           Bonding and Laser Lift-Off Techniques

    • Authors: Qi Wei;Feng Zhou;Weizong Xu;Fangfang Ren;Dong Zhou;Dunjun Chen;Rong Zhang;Youdou Zheng;Hai Lu;
      Pages: 1003 - 1008
      Abstract: In this letter, we have successfully transferred the 4-inch crack-free GaN films from sapphire substrate to conductive silicon wafer by employing eutectic bonding and laser lift-off (LLO) techniques. The resultant 1-mm2 fully-vertical GaN Schottky barrier diodes (SBDs) exhibit a high current swing of 109, a low ideality factor of 1.03 and a high forward current of 10 A. Meanwhile, a decent breakdown voltage of 312 V is achieved, which is over 3 times higher than that of control device without performing epitaxial lift-off. Most importantly, such rectifiers show significantly enhanced electrothermal ruggedness, achieving a high surge-current density of 2.6 kA/cm2 and a low thermal resistance of 0.77 K·cm2/W. In addition, the excellent power rectification capability with a low reverse recovery time of 14 ns is obtained under high-speed switching condition with a high current ramp rate ( $di/dt$ ) of 275 ${mathrm {A/mu s}}$ , implying the desired functionality of the LLO-vertical device architecture. These results thus present the great potentials of the substrate-transferred GaN SBDs for high-power and high-efficiency applications.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improved Symmetry of Ferroelectric Switching in HZO Based MFM Capacitors
           Enabled by High Pressure Annealing

    • Authors: Qin Wang;Yefan Zhang;Peng Yang;Rongrong Cao;Haijun Liu;Hui Xu;Sen Liu;Qingjiang Li;
      Pages: 1009 - 1014
      Abstract: The interface difference between HZO and the upper and lower electrodes induced by the sequence of the process flow could lead to the general asymmetry in the structure and performance of metal-ferroelectric-metal (MFM) capacitors, which may cause serious reliability problems. In this letter, we have exploited a special high pressure annealing (HPA) process, called alcohol-thermal method (ATM), to improve the symmetry of TiN/HZO/TiN capacitors. The original control device exhibits asymmetric leakage current and coercive fields. This has been significantly improved by the ATM, which was performed at temperature of 240°C and atmospheric pressure of 70 atm, in C2H6O ambient. The enhancement of ferroelectricity can be attributed to the reduction of the thickness and defects of the non-ferroelectric layers in the device. The improvement of symmetry leads to the operation ability under low voltages, which is critical to the endurance of devices. Under the electric field of 2.4 MV/cm with 10 MHz frequency, the lifetime of the TiN/ HZO/TiN device after HPA process was measured up to 1010 cycles. This work provides an effective way to improve symmetry and ferroelectricity of hafnium-based ferroelectric capacitors.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Comprehensive Investigation and Comparative Analysis of Machine
           Learning-Based Small-Signal Modelling Techniques for GaN HEMTs

    • Authors: Saddam Husain;Mohammad Hashmi;Fadhel M. Ghannouchi;
      Pages: 1015 - 1032
      Abstract: A number of machine learning (ML) algorithm based small signal modeling of Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) have been reported in literature. However, these techniques rarely provide any inkling about their suitability in modeling GaN HEMTs under varied operating conditions. In this context, this paper thoroughly investigates various ML based techniques and identifies their suitability for specific application scenarios. At first, an array of commonly employed modeling techniques based around Artificial Neural Network, RANdom SAmple Consensus, Support Vector Regression, Gaussian Process Regression, Decision Tree, and Genetic algorithm assisted Artificial Neural Network are used for development of modeling framework to exploit the bias, frequency and geometry dependence on S-parameter based outputs. Subsequently, the ensemble techniques namely Bootstrap aggregating, Random Forests, Extremely Randomized Trees, AdaBoost, Gradient Tree Boosting, Histogram-based Gradient Boosting, and Extreme Gradient Boosting are also explored to understand the capability of these algorithms in the development of GaN HEMT small signal models. Thereafter, an exhaustive analysis of bias and variance is carried out to figure out the most appropriate algorithms for specific applications. The discrepancies during model development are removed by tuning the hyperparameters of the respective models using Random search optimization with 5-fold cross validation technique. Post tuning, the models are evaluated in terms of generalization capability, Advanced Design System compatibility, computational efficiency, training and simulation time, models’ capacity and parameters’tuning time.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Improved Monolayer MoS Performance With Two-Step Atomic Layer Deposited
           High- Dielectrics

    • Authors: Bo-Jhih Chou;Yu-Cheng Chang;Wen-Hao Chang;Chao-Hsin Chen;
      Pages: 1033 - 1039
      Abstract: Gate dielectric engineering is crucial to enable two-dimensional (2D) transition metal dichalcogenides (TMDs) for logic transistor applications. In this work, we demonstrate a uniform and pinhole-free bilayer high-κ fabricated on monolayer (1L) molybdenum disulfide (MoS2) through thermal atomic layer deposition (ALD) without surface pretreatment. A thin low- temperature (75 °C) AlOx film deposited directly on 1L-MoS2 mitigates 2D channel damage and serves as a nucleation and protection layer for high-temperature (250 °C) HfOx high-κ layer. The 1L-MoS2 back-gate (BG) devices with lowtemperature ALD capping show minor mobility degradation, less threshold voltage shift, smooth surface topography, and lower device variability compared to those with high-temperature ALD capping. These electrical differences are closely related to the coverage of the AlOx film at the initial ALD stage and the resultant quality of the AlOx-MoS2 interface after HfOx deposition. The underlying mechanism of ALD on the TMDs is proposed in terms of physical analysis and electrical findings. This work provides a practical and scalable ALD approach in gate dielectrics toward high performance 2D electronics.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Golden List of Reviewers for 2022

    • Pages: 1040 - 1045
      Abstract: Fernando Aguirre Universidad Tecnologica Nacional Facultad Regional Buenos Aires Argentina
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Materials, processing and integration for neuromorphic devices and
           in-memory computing

    • Pages: 1046 - 1047
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power

    • Pages: 1048 - 1049
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • From Mega to nano: Beyond one Century of Vacuum Electronics

    • Pages: 1050 - 1051
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Dielectrics for 2D electronics

    • Pages: 1052 - 1054
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • Semiconductor Device Modeling for Circuit and System Design

    • Pages: 1055 - 1057
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
  • 2022 Index IEEE Journal of the Electron Devices Society Vol. 10

    • Pages: 1058 - 1091
      Abstract: Presents the 2022 author/subject index for this issue of the publication.
      PubDate: 2022
      Issue No: Vol. 10 (2022)
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