A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

  Subjects -> ELECTRONICS (Total: 207 journals)
The end of the list has been reached or no journals were found for your choice.
Similar Journals
Journal Cover
Microelectronics and Solid State Electronics
Number of Followers: 27  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2324-643X - ISSN (Online) 2324-6456
Published by SAP Homepage  [105 journals]
  • Emitter Layer Formation by Spin on Doping on Mono-Crystalline Silicon
           Wafer

    • Abstract: Publication year: 2019Source: Microelectronics and Solid State Electronics , Volume 7, Number 1Nahid Akter, Suvrajit RoyThis paper focus on the standard and simplified spin on doping process for commercially available mono-crystalline silicon wafers. Commercial mono-crystalline silicon solar cell fabrication uses POCl3 (Phosphorus oxychloride) doping for emitter layer formation. This paper shows the P2O5 spin on dopant source used for emitter layer formation instead of widely used POCl3. Detailed fabrication and characterization results are presented. The pn junction sheet resistivity for doping temperature 875°C for 10 and 20 minutes doping were 60 Ω/sq and 45.6 Ω/sq respectively have been found. A series of other characterization found some correlation between processing steps and quality which can be considered as the contribution of the study.
       
  • In Search of the “Forever” Continued Scaling of CMOS Performance by
           Means of a Novel Monolithic 3-Dimensional System-on-top-of-System Approach
           

    • Abstract: Publication year: 2019Source: Microelectronics and Solid State Electronics , Volume 7, Number 1Ahmad Houssam Tarakji, Nirmal ChaudharyWe demonstrate the potential of monolithic Three-Dimensional (3D) Integrated-Circuits (IC’s) to enhance the performance and the power-efficiency of next generation Central Processing Units (CPU’s) and System On Chips (SOC’s). We demonstrate with established simulations that derived from design-rules set by the International Technology Roadmap for Semiconductors (ITRS) that it is feasible to clock these next generation monolithic 3D architectures for CPU’s and SOC’s at extreme frequencies above 30GHz provided the excessive heat generated from such ultra-fast switching is effectively managed. Simulations also specifically demonstrated that it is feasible to clock these systems at frequencies close to 30GHz without necessitating or requiring further heat management beyond what is presently adopted in today’s conventional two-dimensional (2D) Integrated-Circuits (IC’s). This is possible because the inline interconnects in our novel monolithic 3D architectures trim the dynamic power losses by up to four times relative to today’s conventional 2D IC’s. Additionally, the Fully-Depleted Silicon-On-Insulator MOS in our 3D monolithic architectures utilizes a software-controlled transistor back-biasing that dynamically cuts the transistors standby power by more than two orders of magnitude when transistors are off. The substantial reduction in standby power achieved through this approach will enable transistors to satisfy even higher dynamic losses with faster clocking without increasing the overall self-heating. This approach to monolithic 3D integration will enable the continuation of Moore’s law and is manufacturable in standard CMOS-like processes that rely on none other than “good old” Silicon and copper interconnects that are still among the very few materials to date that possess the flexibility to manufacture and produce large-scale integrated electronics in high-volumes. These novel monolithic 3D architectures for next generation CPU’s and SOC’s can dramatically trim the power consumptions in laptops, smartphones, servers, and from the computation intensive data mining and the data centres’ around the globe.
       
  • Analysis of a Novel Single Phase AC-DC CUK Converter with Low Input
           Current, THD to Improve the Overall Power Quality Using PFC

    • Abstract: Publication year: 2018Source: Microelectronics and Solid State Electronics , Volume 6, Number 1Shadman Sakib, Ahmed Jawad Kabir, Md. Shajal Khansur, Md. Jewel RanaSolid-state switch mode AC-DC converters having high frequency are used in improving power quality in terms of Power Factor Correction (PFC) at AC mains, reduced Total Harmonic Distortion (THD) of input current also precisely regulated DC output in buck, boost, buck-boost, and multilevel modes with unidirectional and bidirectional power flow. In this paper, analysis and design of a novel single phase AC-DC CUK converter circuit have been proposed where Power Factor Correction (PFC) controller scheme has been used in order to obtain better performance than conventional converters. Closed loop technique is applied to the bridgeless converter in order to achieve low input current, Total Harmonic Distortion (THD) at input AC mains along with near unity power factor. Performance comparison between the open loop and the closed loop of the proposed converter is made without filtering. The problems arise with the open loop is sufficiently minimized by using power factor correction controller. The performance comparison between proposed and conventional CUK AC-DC converter operating in Continuous Conduction Mode (CCM) is made based on circuit simulations using PSIM software.
       
  • Pulsed Bias and Its Effect on Heat-induced Degradation in GaN-based HEMTs
           that Incorporate Barriers Having High Aluminum Content

    • Abstract: Publication year: 2018Source: Microelectronics and Solid State Electronics , Volume 6, Number 1Ahmad Houssam TarakjiWe report on the pulsed bias operations of GaN-based High-Electron-Mobility-Transistors (HEMTs) that incorporate epitaxial barriers having high Aluminum content. These devices are known to suffer from irreversible permanent degradation of their currents at Drain biases that are higher than 12-15V. This is limiting their use nowadays in most practical applications. In this work we demonstrate with modelling and experimental data that excessive self-heating caused by LO phonons in the GaN 2DEG channel is major contributor to this degradation. We also demonstrate that one approach to alleviate this excessive self-heating is by weakening the lateral field in 2DEG channel between Drain and Source. We finally demonstrate the mechanism that limits the application of higher Drain biases to be caused by combined effect from this intense self-heating and an added bias-induced strain that appears to further strain the already strained and intensely heated GaN 2DEG and accelerate the increase of traps density in GaN. Our data further suggest that epitaxial barrier and its AlN-spacer remained virtually unaffected after prolonged application of high 45V DC bias and that most epitaxial damage appears to confine in GaN, particularly under the access region between Gate and Drain and at the Drain side in the channel under the Gate where both electric-field and the self-heating are highest. An accurate Physics-based model for these HEMTs was also developed and its simulations agreed with our experimental measurements and aided us to formulate these conclusions.
       
  • Fabrication and Analysis of Carbon Doped Hydrogenated Amorphous Silicon
           Thin Film Transistors

    • Abstract: Publication year: 2016Source: Microelectronics and Solid State Electronics , Volume 5, Number 1T. K. Subramanyam, Vinuth Nagendra, Goutham P., Pavan Kumar S., Subramanya K. N.Thin film transistors (TFT) are mainly used in display devices such as a LCD display or a LED display, as a current switch. This paper focuses on analysis of thin film transistors fabricated using carbon doped amorphous silicon as the semiconductor layer (a-Si:C:H). Radio Frequency Plasma Enhanced Chemical Vapour Deposition (RF-PECVD) technique was used to deposit the semiconductor active layer of a-Si:C: H as well as the dielectric silicon nitride layer. Thermal evaporation was used for depositing Aluminium as the gate, source and drain electrodes. Results from UV-VIS-NIR spectrophotometer suggests that the optimised semiconductor active layer with a thickness of 113 nm, exhibited a bandgap value of 1.88 eV. The TFT based on this a-Si:C:H showed linear I-V characteristics as measured using a semiconductor device analyser. Further a thin layer of diborone (B2H6) doped p type a-Si: H was added on top of the active layer (a-Si:C:H) and the TFT thus built showed diode characteristics at the Aluminium- p doped a-Si: H interface. It was thus learnt that using n–doped semiconductor layer with aluminium as the contact electrode provides better TFT characteristics than using Aluminium directly as the source drain material.
       
  • Design and Analysis of Low Power Universal Line Encoder & Decoder

    • Abstract: Publication year: 2016Source: Microelectronics and Solid State Electronics , Volume 5, Number 1Anjali Taya, Balwinder Singh, Hitesh PahujaCommunication plays an important role in day to day life. The information or data is transmitted through various techniques and line coding is one of the finest techniques for sending data. The selection of these techniques depends on the bandwidth requirement, DC level, bit error rate performance and the inbuilt error detection property. In this line coding techniques whose encoder and decoder have been designed and analyzed are Unipolar RZ, NRZ-I, NRZ-L, Manchester, Differential Manchester, AMI, Pseudoternary, B8ZS, HDB3 coding. Any one of these techniques can be access with the mode of selection. Switching activity is the one of the main factors that is responsible for the dynamic power dissipation. Power consumption by the encoders and decoders is directly proportional to switching activity. To optimize the power of the universal line encoder – decoder, Bus Shift (BS) coding scheme is applied that circularly shifts the data to minimize the transition. Simulation results show the average saving margin of power in universal encoder is 22% while in universal decoder saving margin is 35%.
       
  • Microcantilever Based RF MEMS Switch for Wireless Communication

    • Abstract: Publication year: 2016Source: Microelectronics and Solid State Electronics , Volume 5, Number 1Shaik Jani Basha, M. Hanu Sai Krishna, Ch Anish Praharsha, P. Harish Babu, V. Karthikeya, Y. Srinivas, D. Rajya Lakshmi, Srinivasa Rao K.Abstract MEMS (Microelectronic mechanical systems) enjoy wide range of applications in Medical, Biological and Communication engineering. Designing the Micro sensors and Microelectronic elements with high reliability is of high prominent in communication engineering. RF MEMS Switches with high reliability, low activation voltage, low insertion loss and high isolation are needed for high performance applications of Microwave and communication engineering. This paper mainly engrossed on improving performance and reliability of RF MEMS Switch. The proposed design consist of mechanical structure with microcantilever beam and capacitive contact type. RF MEMS Switch is designed and simulated in COMSOL Multiphysics, Finite Element Analysis (FEM) Tool. The Switch wants to connect or disconnect RF (Radio Frequency) Transmission line or any other RF microcircuitary network. The switching operation is based on electrostatic force induced between two electrodes of the design. This induced electrostatic force helps the surface of the cantilever beam to do deflections and the circuit will be closed so that RF line Transmission occurs. Deflection of the microcantilever beam depends upon the electrostatic force developed on the electrodes. This electrostatic force produced be influenced by the applied voltage across the electrode which needs to be smaller for high performance and high reliability criteria.
       
  • Gate Stack High-κ Materials for Si-Based MOSFETs Past, Present, and
           Futures

    • Abstract: Publication year: 2015Source: Microelectronics and Solid State Electronics , Volume 4, Number 1Saeed Mohsenifar, M. H. ShahrokhabadiAn extensive discussion on the High-κ Metal Gate (HKMG) Stack for Si-based MOSFETs has been reviewed in this paper. The implementation of High-κ oxides is a developing strategy to allow more miniaturization of microelectronic components, for the sake of scaling down that predicted by Moore's Law. The main advantage of Silica (SiO2) as a traditional gate oxide is that it can be thermally grown conveniently on Si-substrate whereas its dielectric is an issue compared to the state of the art oxides. The term of High-κ oxide refers to a material with a high dielectric constant of κ, as compared to Silica, that candidate to replace Silica gate dielectrics in advanced CMOS applications. However, many issues such as electrical quality, thermodynamic stability, kinetic stability, gate compatibility and process compatibility remain to be resolved in the terms of implementation and process integration.
       
  • KrF Excimer Laser Doping of Si into GaN

    • Abstract: Publication year: 2015Source: Microelectronics and Solid State Electronics , Volume 4, Number 1Essam Ali AL-NuaimySilicon doping in undoped GaN has been performed by irradiating amorphous silicon film deposited by ion beam sputtering on GaN using 248 nm KrF excimer laser. Sheet resistances and depth profiles of the Si-doped GaN as functions of a number of laser pulses and laser fluence have been measured in order to clarify the relation between properties of doped GaN and irradiation conditions. The minimum sheet resistance of about 60 Ω / □ was obtained. SIMS analysis showed that Si is successfully diffused into GaN. The depths of doped regions ranging from 38 nm to 110 nm were obtained and can be readily controlled by irradiation conditions. Temperature-dependent Hall measurements for doped regions were investigated as a function of laser fluence.
       
  • Concurrent Dual-Band Power Amplifier Using Coupling Matching Network for
           60 GHz WPAN Applications

    • Abstract: Publication year: 2015Source: Microelectronics and Solid State Electronics , Volume 4, Number 1Hanieh Aliakbari, Abdolali Abdipour, Rashid MirzavandA new fully-integrated concurrent dual band CMOS power amplifier (PA) which covers the first and third channels of IEEE 802.15.3c standard is presented. In order to achieve concurrent operation of the 60 GHz PA in two desired narrow frequency bands, the multi-frequency passive coupling matching networks design is proposed. The full wave electromagnetic analysis (by the conventional Method of Moments (MOM)) and circuit analysis (using Circuit Envelope (CE)) are performed for the passive and active parts, respectively, in order to completely characterize the PA structure. This PA model has also been used in system level simulations. The results have shown two fractional bandwidths of 5% and 3%, P1dB of 8.8 dBm and 7.9 dBm at 58.32 and 62.64 GHz, respectively. Maximum power added efficiency (PAE) of 13% is achieved in both targeted bands. Performance of this PA shows promising availability in the future dual band WPAN applications.
       
 
JournalTOCs
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Email: journaltocs@hw.ac.uk
Tel: +00 44 (0)131 4513762
 


Your IP address: 3.225.221.130
 
Home (Search)
API
About JournalTOCs
News (blog, publications)
JournalTOCs on Twitter   JournalTOCs on Facebook

JournalTOCs © 2009-