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Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [120 journals]
  • A High-Performance Low Complex Design and Implementation of QRS Detector
           

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      Authors: S. R. Malathi, P. Vijay Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Electrocardiogram (ECG) is considered as the important diagnostic tests in medical field for detecting the cardiac anomalies. But, the ECG signals are polluted with numerous noise from power line intrusion, muscle noise, baseline wander, motion artifacts, low frequency noise signals, high frequency noise signals and T-wave, which automatically affects the QRS profile. The existing method provides the result in lesser accuracy with higher rate of error detection. To overcome these issues, QRS detector using modified maximum mean minimum (MoMaMeMi) filter optimized with mayfly optimization algorithm (QRS-MoMaMeMi-MOA) is proposed in this paper for less computational cost along with resource requirements. The proposed filter design consists of two phases for detecting QRS detector, such as filtering process associated to the enhancement and detection phase. Initially, the ECG data are taken from MIT/BIH arrhythmia dataset (MIT-AD). For eradicating the baseline wander in ECG data, MaMeMi filter is used. For expanding the performance of the modified MaMeMi filter, filter parameters, such as [math] and [math] are optimized by MOA to accomplish the best values and measure the performance of the whole QRS detector. For high frequency noise suppression in ECG data, the range function, noise subtractors, modified triangular detector are used. Then, heart beat detection can be done with the help of adaptive thresholding technique. The proposed filter design is carried out in MATLAB and implemented on field programmable gate arrays (FPGAs). The proposed QRS-MoMaMeMi-MOA filter design had 0.93%, 0.12% and 0.19% higher accuracy and 89.32%, 50% and 62% low detection error rate, compared to the existing filters, like Kalman filtering based adaptive threshold algorithm for QRS complex detection (QRS-KF-ATA), QRS detection of ECG signal utilizing hybrid derivative with MaMeMi filter by efficiently removing the baseline wander (QRS-HD-MaMeMi), and knowledge-based QRS detection operated by cascade of moving average filters (QRS-CAF). Then, the device utilization of the proposed FPGA implementation of the QRS-MoMaMeMi-MOA filter provides 95.556% and 71.428% lower power usage compared with the existing algorithms, like Kalman filtering based adaptive threshold algorithm for QRS complex detection in FPGA (FPGA-QRS-KF-ATA), and efficient architecture for QRS detection in FPGA utilizing integer Haar wavelet transform (FPGA-QRS-IHWT).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-30T07:00:00Z
      DOI: 10.1142/S0218126623500561
       
  • An Enhanced Reactive Power Compensation Scheme using a Synthesis Segmental
           Multilevel Converted for Three-Phase Grid Systems

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      Authors: Rajendran Nirmala, Sundharajan Venkatesan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Solar photovoltaic (PV) systems have gained significant attention due to their easy implementation and availability, where proper energy management should be highly concentrated for a successful PV power utilization. In the traditional works, various controlling techniques have been developed for reactive power compensation. But, it lacks with the issues of reduced system performance, increased loss, and high harmonics. Hence, this paper aims to develop a new controlling methodology, named the Synthesis Segmental Multilevel Converter (SSMC) for reactive power compensation in a three-phase grid system. Initially, it extracts the maximum amount of power from the solar PV systems by using an Enhanced Perturb and Observe (EPO) method. Then, the panel separation is performed and the three-phase power input is given to the SSMC converter, where the synchronization and switching pulse generation processes are performed. During synchronization, integrated techniques such as Proportional Integral (PI), Fuzzy Logic Controller (FLC), and Improved Artificial Neural Network (IANN) are utilized to maintain the voltage, magnitude and phase angle in the same level. Consequently, the Inductance Capacitance (LC) filtering technique is applied to reduce the harmonics distortion in the signal. After that, the Park transformation is used to perform the dq0 to abc transformation, which is implemented for reducing the high volume of error. Finally, the error-free signal is fed to the three-phase grid system with reduced harmonics. During experimentation, both the simulation and analytical results have been taken for analyzing the performance of the proposed technique. Moreover, it is compared to the existing algorithms for proving the betterment of the proposed methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-30T07:00:00Z
      DOI: 10.1142/S021812662350069X
       
  • A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring
           Oscillator Frequency

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      Authors: Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([math]) is the main dominant source of frequency and gain ([math]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [math] times variation in [math] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[math]GHz is developed in 65[math]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [math] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[math]mW power from 1[math]V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500597
       
  • A Hyperparameter Adaptive Genetic Algorithm Based on DQN

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      Authors: Detian Zeng, Tianwei Yan, Zengri Zeng, Hao Liu, Peiyuan Guan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The hyperparameters of the metaheuristic algorithm are difficult to determine when solving optimization problems. The existing methods mainly adjust hyperparameters through preset rules or traditional RL. The performance of the above methods is unsatisfactory and the generalization is poor. This work proposes a deep Q-learning network (DQN)-based dynamic setting framework for combinatorial hyperparameters, and applies it to a Genetic algorithm (GA) to improve its performance. By defining the four elements of the environment, state, action and reward required for learning strategy in advance, the parametrized strategy can be trained offline and different DQN models can be studied. Our method was compared with other algorithms and achieved the shortest path on 14 of 15 public TSP instances. Meanwhile, the test results on our simulation TSP validation dataset revealed that Category DQN achieved the best performance. This means the proposed method can effectively solve the problem of combinatorial hyperparameters setting, and bring more solving advantages to the GA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500627
       
  • Design of DC–DC Buck Converter Based on Improved Voltage-Mode COT
           Control

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      Authors: Peirong Huang, Changyuan Chang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an improved voltage-mode constant on-time (COT) control DC–DC buck converter is designed, which makes the DC–DC buck converter have good stability. Firstly, an improved compensation scheme is introduced through the analysis and derivation of the traditional voltage-mode COT controlled buck converter model. Then, according to the application requirements of the design, Simplis software modeling is used to verify the correctness of the theoretical analysis. The 0.13[math][math]m BCD technology is used to tape out the DC–DC converter of the improved voltage mode COT. The input voltage is 3.7–5.5[math]V and the output voltage is 3.3[math]V. The chip test mainly includes heavy-load condition in CCM operation, light-load condition in DCM operation, and load transient response. The test results show that the chip can remain stable under heavy-load and light-load conditions. The overshoot and undershoot in transient response can be quickly restored to steady state during the recovery process. Finally, compared with chips of the same type, it shows that the DC–DC chip for portable electronic equipment designed in this paper adopts an internal compensation structure, which has good stability, simple design, small main chip area, simple peripheral equipment, and good application value.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500639
       
  • Reconfigurable Architecture for DNA Diffusion Technique-Based Medical
           Image Encryption

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      Authors: M. Devipriya, M. Brindha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this paper is to develop and test the features of reconfigurable architecture for its suitability for a secured medical image encryption. The image security has been ensured using three-level zigzag confusion, bit-level confusion, self-invertible matrix and DNA diffusion. The zigzag pixel-level and circular shift-based bit-level confusion offer a good scrambling to overcome the correlation among the pixels whereas the self-invertible matrix is used to have a better substitution effect. The DNA operations are performed to get new random-valued sequence for diffusion thereby the encryption process has been designed to get good protection with simple and effective coding. The concept of secured medical image encryption has been designed using verilog HDL and implemented using field programmable gate array (FPGA) with an intention to create a standalone embedded hardware for encryption. The analysis of the encryption includes correlation coefficient, entropy, Chi-square analysis, NPCR and UACI and so on, which gives a better result and conveysto us that it can resist the statistical and differential attacks. The synthesis report of the embedded hardware has been presented to understand the utilization of the FPGA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500652
       
  • A Subcircuit-Based Model for the Accumulation-Mode MOS Capacitor

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      Authors: Shahriar Jamasb, Mohammad Bagher Khodabakhshi, Rasool Baghbani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The accumulation-mode metal-oxide-semiconductor (MOS) capacitor is commonly employed to implement MOS varactors in frequency-tuning circuits for radio frequency (RF) and analog applications. A subcircuit model for the accumulation-mode MOS (AMOS) capacitor based on the Berkeley Short-channel IGFET Model (BSIM) for the MOS field effect transistor (MOSFET) is presented. The proposed model accurately fits the capacitance-voltage (C-V) characteristics of an AMOS capacitor fabricated in a submicron CMOS process over the full range of operating gate voltages. The model also accounts for the impact of the distributed series resistance on the transient response of the AMOS capacitor. Notably, the gate capacitance and the associated series resistance are modeled as a distributed resistor-capacitor (RC) network to derive a subcircuit-based model with the bias-dependent resistance of the accumulation layer modeled as a voltage-controlled resistor (VCR). The proposed model is evaluated based on SPICE simulation of the intrinsic transient response of the AMOS capacitor using a basic circuit, representing the distributed RC network associated with the MOS device structure. Fine tuning of the effective series resistance in the subcircuit model can be achieved by fitting the measured data characterizing the charge–discharge behavior of the AMOS capacitor to the simulated data characterizing the intrinsic transient response generated by SPICE.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-24T07:00:00Z
      DOI: 10.1142/S0218126623500548
       
  • Single MEXCCII-Based Grounded Immittance Functions Simulation and
           Applications

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      Authors: Atul Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component’s matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit’s performance is examined using 0.18-[math]m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-24T07:00:00Z
      DOI: 10.1142/S0218126623500603
       
  • Ultrasound Kidney Images with IKNN-Dependent FPGA Abnormality
           Classification

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      Authors: R. Vinoth, R. Sasireka
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Ultrasound imaging is commonly used to diagnose internal anomalies. Imaging for abnormality detection is a challenging process in today’s world. Even though there is an advancement in technology, tele-radiographers face difficulty in the accurate diagnosis of abnormalities. In order to resolve this issue, tele-radiology has paved a new way for doctors around the world to access the Internet to share the radiological images from one location to another. But frequent online access is one of the bottleneck issues. In order to overcome this drawback, Computer Assisted Diagnosis (CAD) is preferred in this proposed study and it uses VIRTEX-6 FPGA to clearly identify abnormality in the platform and also manual control is minimized in this condition. The proposed algorithm includes five steps: pre-processing, segmentation, feature extraction, selection and classification. The classification is performed using the Iterative K-Nearest Neighbor (IKNN) classifier based on the selected features. Unlike popular KNN, the proposed IKNN algorithm performs the similarity measurement on selective neighbors for a number of times where the number of neighbors has been dynamically selected at each iteration. Also, at each iteration, the method would select a subset of features in a random way. For the features selected and with the neighbors selected, the method computes the similarity value of Hist-sim which is being measured according to the features selected from the histogram features where the method computes the Haralick similarity with the features selected from the Haralick features. Using the features selected, the method computes the value of cumulative class drive similarity (CCDS). At each iteration the class with maximum similarity is selected and finally, the class being selected for the most number of times is selected as a result of classification. This improves the performance of classification. While comparing with the existing algorithms such as Support Vector Machine (SVM) with the linear, Radial Basis Function (RBF) and polynomial kernels, greater accuracy is achieved via IKNN classification. The specificity is found to be 95, 80 and 75 for normal, cystic and stone kidneys.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-24T07:00:00Z
      DOI: 10.1142/S0218126623500640
       
  • A Switched Capacitor-Based Multilevel Boost Inverter for Photovoltaic
           Applications

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      Authors: B. Hemanth Kumar, S. Prabhu, K. Janardhan, V. Arun, S. Vivekanandan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a single-phase 13-level switching capacitor multilevel boost inverter (SCMLBI) with less switches and a voltage boost gain of six times is presented. The main focus of this work is to present a single DC source SCMLBI topology, which can provide an AC output voltage with low harmonic distortion by suitable sinusoidal pulse modulation (SPWM) technique. The given SCMLBI boost topology is designed to provide 13 output voltage levels utilizing a single DC source and 14 power electronic switches, and it includes intrinsic capacitor self-voltage balancing. The presented SCMLBI inverter does not require any magnetic elements like inductors which do not make the system complex in IC fabrication. In this work, the DC source is provided with a solar PV array with maximum power point tracking (MPPT) algorithm. The proposed SCMLBI topology provides an output voltage larger than the input voltage by appropriately converting the capacitors in series and parallel combinations. Sinusoidal PWM technique is used to control the switches in SCMLBI. A solar PV array of 100 W with incremental and conductance MPPT algorithm is used in this work. The verification of the presented SCMLBI topology is simulated on MATLAB software. Hardware results are also presented for the validation of SCMLBI topology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-22T07:00:00Z
      DOI: 10.1142/S0218126623500573
       
  • Challenges of Agile–Crowd Software Development: A Systematic
           Literature Review

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      Authors: Shamaila Qayyum, Salma Imtiaz, Huma Hayat Khan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Crowdsourcing is an emerging approach in software development, where software is developed by unknown, heterogeneous people around the globe, via an open call by the employer. Crowdsourcing, when used with agile, faces challenges because of the different development methodologies. Agile development methodology has practices that involve face-to-face frequent interaction, whereas crowdsourcing is a distributed development with no or limited face-to-face interaction. Both concepts are actively being used in the software development industry due to their benefits. However, there is a need to explore the integration of both methodologies for an effective and efficient software development. In this regard, the first step is to identify the challenges of integrating crowdsourcing and agile. In this paper, we intend to identify the possible challenges that may be faced while executing agile along with crowdsourcing. For this, we have conducted a Systematic Literature Review. Five main categories of challenges are presented which are: team issues, coordination and communication issues, organizational issues, project-related issues and task-related issues. A list of possible challenges of Agile–Crowd Software Development (ACSD) is presented in this study.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-21T07:00:00Z
      DOI: 10.1142/S0218126623300015
       
  • Electronically Independent Gain Controllable Integrable Trans-Admittance
           Mode Universal Filter: An Application for Modern Radio Receiver

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      Authors: Sachin Tiwari, Tajinder Singh Arora
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper represents a new integrable trans-admittance mode universal filter employing an active building block, i.e., Voltage Differencing Current Conveyor, and all grounded passive elements. The proposed circuit can easily realize all five, widely used, filter responses, i.e., bandpass, high pass, low pass, all pass and band-reject. The designed circuit configuration provides favorable impedances at the input as well as output ports. Independent tunability of its gain parameter and orthogonal tunability of its quality factor and operating frequency are some of the noteworthy features of the designed circuit. The simulations of the designed filter are verified by 180-nm Complementary Metal Oxide Semiconductor (CMOS) technology in the SPICE simulation environment. Validation of the proposed design is done by experimental work along with the regular mathematical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-21T07:00:00Z
      DOI: 10.1142/S0218126623500615
       
  • Pricing Game of Smart Charging Services for Risk-Averse Users in the Smart
           Grid

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      Authors: Wenjing Shuai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Electric vehicles play a key role in the transition to an environmental-friendly transportation system and can meanwhile enhance the power system’s evolution to the smart grid. With the adoption of dynamic pricing and usage scheduling enabled by the smart grid equipment, a variety of smart charging strategies have been designed to make the most of flexibility contained in their considerable electricity demand, whereas less effort is devoted to users’ willingness to participate. In this paper, we model a noncooperative pricing game between two types of charging stations. One offers conventional fast charging and the other uses the electric vehicles’ onboard batteries to provide regulation service to the grid. With drivers’ risk attitudes and bounded rationality taken into consideration, we design a prospect theory-based decision model to calculate the proportion of users that would go for the regulation-providing charging option. The decision model of the customer base is a critical determinant of profitability and it enables two competitors to strategically set their prices that optimally balance between gaining in market share and growing in profit per client. We prove the existence of a pure strategy Nash equilibrium for the game proposed and compute the equilibrium prices in different circumstances with respect to market settings and user segments. A comprehensive analysis of the results gives insights into the key factors at play and provides the grid operators with indications of how to increase the penetration of electric vehicles in the ancillary service market.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-17T07:00:00Z
      DOI: 10.1142/S0218126623500524
       
  • A Modern VDCCTA Active Element and Its Electronic Application

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      Authors: Yumnam Shantikumar Singh, Ashish Ranjan, Shuma Adhikari, Benjamin A Shimray
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-17T07:00:00Z
      DOI: 10.1142/S0218126623500536
       
  • Text Coverless Information Hiding Based on the Combination of Chinese
           Character Components

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      Authors: Junyu Wang, Yani Zhu, Jiaming Ni, Hui Wang, Ye Yao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent research works on coverless text information hiding, there are two main problems to be solved: low hiding success rate and small hiding capacity caused by the small amount of redundant information in the cover text. In order to overcome these problems, a method of coverless information hiding based on the combination of Chinese character components is proposed. This method is based on the traditional “location tag [math] keywords” mode for coverless information hiding, but with an improved design to extend the scope of available keywords for data hiding beyond the original cover texts. In our proposed method, each Chinese character in the keyword is split into two components: radicals and independent Chinese character, which are collected and will be recombined in pairs to generate the new Chinese characters. This method increases the hiding success rate and hiding capacity by generating Chinese characters that do not exist in the original cover text. The experimental result shows that the proposed method can utilize less size of carrier text database for efficient information hiding. When the size of carrier text database is reduced to 198[math]MB, the highest hidden capacity and hidden success that can be achieved are 13.45 and 0.99, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-17T07:00:00Z
      DOI: 10.1142/S021812662350055X
       
  • An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling
           Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator

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      Authors: Abdul Muqueem, Shanky Saxena, Govind Singh Patel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Frequency-modulated continuous-wave (FMCW) signals-based radar systems can outrun the optical and ultrasound sensors in dark and severe weather conditions. FMCW radar systems require a fast settling frequency synthesizer to reduce the chirp signal’s inactive and modulation times. This work proposes a new C-B and FMCW Transmitter based on Fast Settling Fractional-N DPLL (FS-FNDPLL) and ring-based pulse injection locking oscillator (R-PILO). The proposed FS-FNDPLL generates an ultra-fast low-noise smooth narrowband chirp by introducing an automatic controller-based TDC switching (AC-TDCSw) scheme in the forward loop of FNDPLL. Also, the proposed FS-FNDPLL employs a new background gain calibrated digital-to-time converter (BGC-DTC) as a fractional divider in the feedback path for the quantization noise cancellation (QNC). The proposed FMCW transmitter uses an R-PILO to produce fast switching adjacent carriers after generating a narrowband chirp using FS-FNDPLL. The main features of the proposed FMCW to accelerate settling time with AC-TDCSw, BGC-DTC and the integration of spur suppressing pulse generator (SSPG) in R-PILO enable ultra-fast chirps with less phase noise and spur levels. The proposed transmitter up-converts the 500[math]MHz narrowband chirp signal onto four adjacent carriers for obtaining a 2[math]GHz chirp at the C-band. The simulation results prove that the proposed FMCW Transmitter consumes 79[math]mW power. Furthermore, the phase noise of the proposed FS-FNDPLL is reduced to [math][math]dBc/Hz at 1[math]MHz. The proposed FS-FNDPLL reduces the settling time to 1[math][math]s with the introduced AC-TDCSw scheme.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-16T07:00:00Z
      DOI: 10.1142/S0218126623500457
       
  • Voice Calibration Using Ambient Sensors

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      Authors: Jianhai Chen, Huapu Zeng, Yunming Pu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The voice sensor is the core part of voice monitoring devices, and it is commonly drifted in long-term running. For this reason, the voice calibration of monitoring devices is essential. Several calibration methods had been introduced by leveraging expensive referred instruments or manual calibration methods. However, these methods are not only dependent on high-cost instruments, but also is impractical on isolated occasions. To overcome these issues, the feature fusion-based neighbor (FbN) model is proposed to calibrate voice sensors, via real-time low-cost ambient sensors. The FbN consists of a real-time awareness stage, feature selection stage, feature fusion stage, and prediction stage. First, voice data and exogenous low-cost sensor (LCS) data are simultaneously collected. Second, those low-cost sensor data are treated as individual features. The irrelevant features are empirically filtered out. The adopted exogenous features are temperature, humidity and air pressure. Third, the selected features are fused to obtain more representative features. Finally, distances between sensor data and represented features are calculated and sorted. The top-[math] average distances are regarded as the predictive results. Experimental comparisons with several novelty methods show the effectiveness of the proposed FbN.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-15T07:00:00Z
      DOI: 10.1142/S0218126623500433
       
  • Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG
           and Multistage LFSR with Clock Gating Network

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      Authors: Mangal Deep Gupta, R. K. Chauhan, Sandeep Gulia
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S0218126623500391
       
  • Design of a Configurable Third-Order [math]-[math] Filter Using QFG and
           BD-QFG MOS-Based OTA for Fast Locking Speed PLL

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      Authors: Priti Gupta, Sanjay Kumar Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([math]-[math])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [math]-[math] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [math]-[math] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [math]3[math]dB cut-off frequency of 16.51[math]MHz and 17.22[math]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[math][math]s and 0.32[math][math]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[math][math]m CMOS process.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S0218126623500408
       
  • Extraction of Meaningful Information from Unstructured Clinical Notes
           Using Web Scraping

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      Authors: K. Sukanya Varshini, R. Annie Uthra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the medical field, the clinical notes taken by the doctor, nurse, or medical practitioner are considered to be one of the most important medical documents. These documents hold information regarding the patient including the patient’s current condition, family history, disease, symptoms, medications, lab test reports, and other vital information. Despite these documents holding important information regarding the patients, they cannot be used as the data are unstructured. Organizing a huge amount of data without any mistakes is highly impossible for humans, so ignoring unstructured data is not advisable. Hence, to overcome this issue, the web scraping method is used to extract the clinical notes from the Medical Transcription (MT) samples which hold many transcripted clinical notes of various departments. In the proposed method, Natural Language Processing (NLP) is used to pre-process the data, and the variants of the Term Frequency-Inverse Document Frequency (TF-IDF)-based vector model are used for the feature selection, thus extracting the required data from the clinical notes. The performance measures including the accuracy, precision, recall and F1 score are used in the identification of disease, and the result obtained from the proposed system is compared with the best performing machine learning algorithms including the Logistic Regression, Multinomial Naive Bayes, Random Forest classifier and Linear SVC. The result obtained proves that the Random Forest Classifier obtained a higher accuracy of 90% when compared to the other algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S021812662350041X
       
  • Optimum Transistor Sizing of CMOS Differential Amplifier using Tunicate
           Swarm Algorithm

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      Authors: V. Kamalkumar, R. Lal Raja Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S0218126623500512
       
  • Construction of Sports Rehabilitation Training Method Based on Virtual
           Reality

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      Authors: Yi Xu, Jinglun Huang, Yajuan Yao, Chaofan Zeng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The introduction of virtual reality technology into rehabilitation training can avoid various shortcomings of traditional rehabilitation training, and can efficiently complete training tasks. Based on the basic theory of virtual reality, this paper constructs a sports rehabilitation training method to achieve the consistency of the virtual upper limbs and the real upper limbs of the human body. The model provides a background environment in the virtual reality training, realizes the systematic maintenance of the patient’s training mode, provides the patient with a scientifically based training mode and evaluation results, solves the quantitative index problem of sports rehabilitation training, and builds a virtual upper limb platform at the same time. During the simulation process, the system used the Berg balance assessment scores to conduct four-stage assessments. Before treatment, the three-dimensional gait analysis, FMAL lower extremity function scores and Berg balance assessment results were not significantly different between the control group and the experimental group ([math]). The experimental results showed that the three-dimensional gait analysis was used to analyze the pace, left and right step length, left and right support percentage, and stride frequency. Compared with the evaluation data before treatment, the index values of the control group and the experimental group were significantly improved ([math]); after the treatment, the two groups of patients were evaluated for motor function, the evaluation values of the experimental group were higher than those of the control group when compared between the two groups. It effectively meets the human–computer interaction needs of rehabilitation training.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-12T07:00:00Z
      DOI: 10.1142/S0218126623500342
       
  • Intelligent Optimization Approaches for a Secured Dynamic Partial
           Reconfigurable Architecture-Based Health Monitoring System

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      Authors: R. Saravana Ram, M. Lordwin Cecil Prabhaker
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([math]), computation time ([math]) and area ([math]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([math]), computation time ([math]) and area ([math]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using CycloneⓇ V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-12T07:00:00Z
      DOI: 10.1142/S0218126623500470
       
  • Investigating the Impact of Test Case Density and Execution Variety on
           Fault Localization for Novice Programs

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      Authors: YingChun Wang, Lin He, Nannan Chen, Qi Zhai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Programming Online Verification Exam (OE) system has been widely used in algorithm education and practice since it can automatically analyze program results (e.g., correct or incorrect) after executing the submitted programs with corresponding test cases. OE systems can provide both execution results and error information so that novice programmers can get feedback quickly. If the submitted program cannot pass all the test cases, the novice programmers will get wrong-answer feedback, and they have to find and fix the errors in the program. Automated program fault localization techniques, which can locate the errors in programs under test automatically, thus help novice programmers fix the errors quickly. However, the performance of current automated fault localization techniques is limited due to the high-density test cases in novice programs of OE system. In this paper, we analyze the impact of test case density (TCD) and execution variety on fault localization performance and propose a method to reduce TCD to improve fault localization precision for novice programs. To evaluate the performance of our method, we conduct a number of empirical studies on 1199 real fault diagnosis algorithm related novice programs, and the experimental results show that using improved test cases through our method for fault localization in OE system can enhance the precision of fault localization for novice programs. Specifically, after decreasing the test cases’ density, the improvement of fault localization accuracy ranges from 0.6% to 17.34% in terms of the Expense metric, and from the Accuracy@N metrics, the number of faulty statements that can be found increases in most cases.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500159
       
  • Forensics Analysis of Resampling via ConvNeXt Block

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      Authors: Xiaogang Zhu, Shuaiqi Liu, Bing Fan, Xiangjun Li, Yiping Zhu, Haozheng Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Images play an important role in transmitting visual information in our life. It could lead to severe consequences if images are manipulated or tampered maliciously. Digital forensics is an important research area to secure multimedia information. Many forensics technologies are applied to protect our community from the abuse of digital information. In many cases, after tampering, attackers could apply operations such as resampling, JPEG compression, blurring, etc. to cover the traces of tampering. Therefore, it is necessary to detect these manipulations in image forensics before exposing forgeries. In this paper, we propose to employ the prediction error filters, ConvNeXt blocks and convolution modules to classify images with different compression quality factors and resampling rates. By tracing the inconsistencies of resampling rates and compression quality factors, it could provide supplementary information for forensics researchers to expose possible forgeries. The proposed method could achieve great classification performance regardless of the interpolation algorithms. Also, it is highly robust against JPEG compression. In addition, the proposed method can be applied for estimating quality factors of JPEG compression.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500330
       
  • Low-resolution Face Recognition and Sports Training Action Analysis Based
           on Wireless Sensors

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      Authors: Hongjun An, Heng Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper constructs a low-resolution model for face recognition and sports training actions based on wireless sensors. The model obtains the distribution of the information size in the face image by calculating the image entropy value, and assigns different weights according to the size of the information to perform face recognition calculation, so that the original module-based algorithm is simply based on image segmentation into one based on entropy. The size of the value is divided into blocks, which solves the problem of computational quantification of category information. In the test stage, the traditional orthogonal matching pursuit algorithm is used to solve the coding coefficients, and the excellent classification and recognition results are obtained by calculating the intra-class matrix of the face image and the inter-class matrix of the sports training action image. Methods that perform well on classification problems further improve face recognition rates. The specific processing process is to add Gaussian noise, salt and pepper noise to the input face image and reduce the size of the face image in the input image, so that the improved algorithms are improved. The experimental results show that the high-efficiency resolution sensing technology is used to learn the sports training actions corresponding to the two modalities, and the matrix coefficient between the obtained high-resolution modal and low-resolution modal images reaches 0.971, and the iteration rate is improved by 71.5%, effectively promoting the high recognition rate of faces and actions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500378
       
  • Application of Virtual Network Mapping Algorithm Based on Optimal Subnet
           in Enterprise Cost Accounting Platform

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      Authors: Haiyan Wu, Xiao Li, Yongjun Qi, HaiLin Tang, Shukun Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The price of the product has a great impact on the market competitiveness of the product. The manager can adjust the operation strategy according to the cost information of the product, cut costs, adjust the market decision and make the product more competitive in the market. Therefore, the research of product costing method has a very important significance. Considering that the physical resources in the processing of the virtual network mapping (VNM) fragment embedded in the request are rejected, and the problem of physical resource usage is weakened, a VNM algorithm based on the optimal subnet edge matching algorithm is proposed. After the VNM request is coarsened to the subnet, the breadth-first search algorithm is used to create the physical subnet candidate set, and the constraints of the virtual node and the coarsening network topology are complied with. The simulation results show that the proposed algorithm reduces the number of link mapping hops and can improve the acceptance rate and cost-benefit ratio of virtual networks. First of all, this paper analyzes the research background of manufacturing cost calculation and the research situation at home and abroad, discusses the advantages and disadvantages of standard cost calculation and studies and analyzes the principles, advantages and disadvantages of standard cost calculation in daily business activities. Second, design a new mathematical accounting model based on the mathematical model of standard cost calculation in daily business activities. This combines the advantages of standard costing and time-based activity costing, and provides theoretical support for manufacturing companies to use this accounting method. Finally, the research results of this paper are summarized, and the shortcomings of this paper are analyzed. Cost accounting method needs to be further studied.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500421
       
  • Real-Time Regulation of Physical Training Intensity Based on Fuzzy Neural
           Network

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      Authors: Jiale Qu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the fuzzy neural network model is studied, the real-time regulation model of physical training intensity is analyzed and a real-time regulation system based on a fuzzy neural network is designed. The real-time, accurate and effective regulation of the physiological load intensity in the body of the exerciser is consistent with the predetermined goals of the training program. In this paper, we propose an RBF neural network, combined with the plan and demand of physical training operation situation sensing, and considering that most of the biological training operation data is fuzzy, this paper connects a fuzzy logic inference system and a neural network and proposes a network operation situation sensing model based on an RBF neural network structure. The RBF neural network and the traditional fuzzy neural network are compared. The experiments prove that this paper’s fuzzy neural network model has a faster training speed. In this paper, we use time-realistic control equipment to monitor the physical training process of athletes so that we can grasp the training situation of athletes in real-time and ensure that athletes can achieve better training results by changing training methods and changing training loads in time for those athletes who cannot reach their sports goals. In the process of physical fitness training monitoring, an effective monitoring of training, time-accurate regulation monitoring has the advantage of timely feedback on the training situation. This model has a better convergence effect during exercise and a higher accuracy of posture prediction during testing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500445
       
  • Research on Fast Recognition of Vulnerable Traffic Participants in
           Intelligent Connected Vehicles on Edge Computing

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      Authors: Musong Gu, Jingjing Lyu, Zhongwen Li, Zihan Yan, Wenjie Fan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Real-time and fast recognition of all kinds of traffic participants in intelligent driving has always been a major difficulty in the research of internet of vehicles. With the advent of edge computing, we try to deploy an image recognition algorithm directly to the intelligent vehicles. However, the original image recognition algorithm is difficult to be directly deployed on the vehicles due to limited edge device resources. Based on this, a fast recognition model of vulnerable traffic participants based on depthwise separable convolutional neural network (DSCYOLO) is proposed in this paper. The algorithm can significantly reduce the convolutional parameter quantity and computing load, making it suitable for deployment on the vehicle-mounted edge embedded devices. In order to validate the effectiveness of the proposed method, its simulation results are compared with the main target detection models Faster R-CNN, SSD and YOLOv3. The results show that the recognition time of the proposed model is reduced by 80.28%, 66.80% and 86.74%, respectively, on the basis of a relatively high recognition precision. The model can realize real-time detection and fast recognition of vulnerable traffic participants, so as to avoid a large number of traffic accidents. It has significant social and economic benefits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500469
       
  • Knowledge Distillation for Lightweight 2D Single-Person Pose Estimation

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      Authors: Shihao Zhang, Baohua Qiang, Xianyi Yang, Mingliang Zhou, Ruidong Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The current state-of-the-art single-person pose estimation methods require heavily parameterized models for accurate predictions. A promising technique to achieve accurate yet lightweight pose estimation is knowledge distillation. However, existing pose knowledge distillation methods rely on the most common large basic building blocks and a complex multi-branch architecture. In this study, we propose a Single-branch Lightweight Knowledge Distillation method to increase pose distillation efficiency for 2D Single-person pose estimation, termed SLKD2S. First, we design a novel single-branch pose knowledge distillation framework, which is composed of connected lightweight pose estimation stages. Second, we utilize a special pose distillation loss based on the joint confidence map. Finally, we only keep the initial stage and the first refinement stage to achieve a good performance. Extensive experiments on two standard benchmark datasets show the superiority of the proposed SLKD2S in terms of cost and accuracy, and the average detection accuracies are increased by 1.43% and 2.74% compared with the top-performing pose distillation method, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500500
       
  • An Expansion Planning Approach for Intelligent Grids with Speculative
           Parallelism

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      Authors: Zhoukai Wang, Jiaqi Qi, Weigang Ma, Yang Lv, Dongfang Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Smart grid planning is a standard method used to reduce the net loss of distribution networks and improve the economic efficiency of power systems. As the distribution networks expand, the scale is getting more complex, leading to low efficiency and a long planning time when using traditional methods to implement new routes. To solve this problem, this paper proposed a new approach for intelligent grid expansion planning with speculative particle swarm optimization. First, the expansion planning model for the smart grid is established based on particle swarm optimization from the classical control system. Secondly, the model is parallelized with the speculative parallelism technique to overcome the influence of the internal control dependency and get rid of the original processing order. Finally, the parallel model is implemented on a distributed computing platform to improve the planning efficiency for complex intelligent grids significantly. Experiments show that the proposed approach can improve the efficiency by about 40% in an Apache Spark cluster consisting of 20 nodes compared with the conventional ones. Moreover, the proposed method can also fully utilize the distributed cluster’s computing resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-05T07:00:00Z
      DOI: 10.1142/S0218126623500366
       
  • FPGA Implementation of Expert System for Medical Diagnosis of Disc Hernia
           Diagnosis Based on Bayes Theorem

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      Authors: Tijana Šušteršič, Aleksandar Peulić
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this research is to create a medical expert system based on Bayes theorem to diagnose level of disc hernia based on real foot force measurement signals obtained using sensors and implement the whole system on field programable gate array (FPGA). We have created a database of attributes based on recorded foot force values of 33 patients pre-diagnosed with herniated disc on levels L4/L5 or L5/S1 on the left or right side. The results obtained by software (Matlab) and hardware (FPGA simulation) are matching well, achieving high accuracy, which shows that VHDL implementation of Naïve Bayes theorem for disc hernia diagnostics is adequate. The output on FPGA is easy to understand for any user, as it is implemented as four-bit output where the position of bit value 1 indicates the level of disc herniation. The system is able to distinguish between the healthy subjects and subjects with disc herniation and is able to detect if improvement in stability is present after surgery or physical therapy. Our proposed measurement platform can be coupled with FPGA to create a portable and not expensive tool for real time signal acquisition, processing and decision support system in disc hernia diagnosis and post-surgical recovery.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-31T07:00:00Z
      DOI: 10.1142/S021812662350038X
       
  • Genetic Algorithm with Local Search for the Multi-Target Scheduling in
           Flexible Manufacturing System

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      Authors: Hao Wang, Yujue Wang, Xianwei Lv, Chen Yu, Hai Jin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Traditional large-scale process manufacturing is gradually transformed into customized discrete manufacturing with the fierce global competition. Production planning has an important impact on improving manufacturing efficiency in the ever-changing from the view of engineering management. However, many nonprocessing-related factors in the flexible manufacturing system make it different between the formulation and implementation of the production plan. We established a multi-target optimization model based on the scheduling data of a discrete manufacturing company. In order to optimize the local effect of the scheduling model, we proposed an improved genetic algorithm with local search (GALS). The results of the experiments show that GALS is far superior to the current genetic algorithm scheduling in terms of the number and quality of scheduling solutions. Compared with the current scheduling strategy of the enterprise, the scheduling strategy given by GALS achieved an average improvement of 29.61% in minimizing completion time, achieved 44.8% in minimizing transportation time, and achieved 44.64% in machine load balancing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-30T07:00:00Z
      DOI: 10.1142/S0218126622502796
       
  • Retraction: Evolved Fuzzy NN Control for Discrete-Time Nonlinear Systems

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      Authors: Tim Chen, A. Babanin, Assim Muhammad, B. Chapron, C. Y. J. Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.

      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-29T07:00:00Z
      DOI: 10.1142/S021812662293001X
       
  • LiCAM: Long-Tailed Instance Segmentation with Real-Time Classification
           Accuracy Monitoring

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      Authors: Rongguang Ye, Yantong Guo, Xian Shuai, Rongye Ye, Siyang Jiang, Hui Jiang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, deep neural networks have achieved remarkable progress in class balancing instance segmentation. However, most applications in the real world have a long-tailed distribution, i.e., limited training examples in the majority of classes. The long-tailed challenge leads to a catastrophic drop in instance segmentation because the gradient of the head classes suppresses the gradient of the tail classes, leading to a bias towards the major classes. We propose LiCAM, a novel framework for long-tailed segmentation. It features an adaptive loss function named Moac Loss, which is adjustable during the training according to the monitored classification accuracy. LiCAM also cooperates with an oversampling technique named RFS, which alleviates the severe imbalance between head and tail classes. We conducted extensive experiments on the LVIS v1 dataset to evaluate LiCAM. With a coherent end-to-end training pipeline, LiCAM significantly outperforms other baselines.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-29T07:00:00Z
      DOI: 10.1142/S0218126623500329
       
  • Neural Network-Based Entropy: A New Metric for Evaluating Side-Channel
           Attacks

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      Authors: Jiafeng Cheng, Nengyuan Sun, Wenrui Liu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Yufei Wang, Yijian Bi, Yiming Wen, Hongliu Zhang, Pengcheng Zhang, Selcuk Kose, Weize Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623200013
       
  • Fault Diagnosis of Industrial Robots Based on Phase Difference Correction
           Method

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      Authors: Changgui Xie, Hao Xu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Aiming at the characteristics of the fault spectrum of industrial robots, a new phase difference correction method is proposed on the basis of Fourier transform, which combines autocorrelation technology and windowing technology to convert the original signal into a discrete spectrum with fault characteristics, which effectively improves the accuracy of fault spectrum correction and provides important help for robot fault diagnosis. Simulation analysis and example verification show that the new algorithm is quite effective in the extraction of industrial robot fault features, and the algorithm still has a smaller relative error than the traditional algorithm under noise conditions, with high estimation accuracy and strong compatibility and robustness. The algorithm not only has high theoretical value in pattern recognition, but also has great practical significance in engineering fields such as robot diagnosis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500135
       
  • Electricity Theft Detection Based on ReliefF Feature Selection Algorithm
           and BP Neural Network

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      Authors: Li Yang, Jinyu Wang, Nianrong Zhou, Zexin Wang, Chuan Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As China’s distributed energy is still in the development stage, energy transmission loss will inevitably occur in the transmission process from the source end to the load end. To reduce transmission energy loss, we should also beware of electricity theft. The principle of common electricity theft methods is analyzed to improve the accuracy of established electricity theft characteristics and electricity theft detection. The ReliefF multivariate characteristics selection algorithm optimizes the electricity theft characteristics. The back propagation (BP) neural network-based electricity theft detection model is built, and the optimized characteristics are selected as the model’s input. The experiment results show that the detection model has better electricity theft identification accuracy using the optimized characteristics for electricity theft detection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500147
       
  • A Robust, Compact and Efficient AMC-Enabled Dual-Band Antenna for Wearable
           Healthcare

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      Authors: Asma Ejaz, Humayun Shahid, Yasar Amin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper details an antenna design with a minuscule lateral footprint of [math][math]mm3. The antenna operates for the two bands of WiMAX 3.5[math]GHz (for wireless communication standard) and industrial, scientific and medical radio (ISM) 5.8[math]GHz (for healthcare applications). Optimization and computer-aided performance analysis of the proposed design are carried out using Computer Simulation Technology (CST) Microwave Studio. Required electromagnetic performance in close proximity to the human body is achieved by backing the primary CPW-fed antenna with a fabric-based dual-band AMC surface. Several prototypes of the formulated design are characterized experimentally to validate the computationally obtained performance parameters. The proposed AMC-integrated dual-band design readily meets directional radiation characteristics desired for off-body communication with 7.53-dB and 8.58-dB gains in the lower and upper resonance frequencies, respectively. Moreover, the antenna’s top layer consists of a semi-flexible laminate, while textile constitutes the bottom layer to maximize user comfort. Further analysis reveals a significant reduction in SAR by 16.7[math]W/kg at the lower band and by 13.5[math]W/kg at the upper band. The precedence of the reported structure demonstrated in the results endorses its application in robust wearable devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500238
       
  • Wien-Bridge Chaotic Oscillator Circuit with Inductive Memristor Bipole

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      Authors: K. Zourmba, C. Fischer, J. Y. Effa, B. Gambo, A. Mohamadou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      By diode bridging an inductor to implement a memristor bipole, with active Wien-bridge oscillator, a simple and feasible third-order autonomous memristive chaotic oscillator is presented. The dynamical characteristics of the proposed circuit are investigated both theoretically and numerically, from which it can be found that the circuit has one unstable equilibrium point. Through the analysis of the bifurcation diagram, Lyapunov exponent spectrum and the 0–1 test chaos detection, it is shown that this system displays limit cycle orbit with different periodicity, quasi-periodic behavior, chaotic behavior and bursting behavior. The bursting behavior found in this circuit is periodic, quasi-periodic and chaotic bursting. We confirm the feasibility of the proposed theoretical model using Pspice simulations and a physical realization based on an electronic analog implementation of the model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S021812662350024X
       
  • A General Methodology to Optimize Flagged Constant Addition

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      Authors: Aroondhati Bhure, P. Smriti, Vinay Dhanote, Uppugunduru Anil Kumar, Syed Ershad Ahmed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Addition is a ubiquitous operation frequently carried out in most computing applications. Traditionally, three-operand addition is done using either two adders or a carry–save adder. However, there exist applications such as digital signal processing, image processing, floating point arithmetic, etc. wherein among the three operands, one is constant. For such cases, we propose a flagged constant addition methodology, applicable to any constant, to compute the result with the least area, delay and power. The resulting architecture is referred to as general constant flagged adder (GCFA). We propose an Optimized Constant Generation (OCG) algorithm and a Hardware Optimization Algorithm (HOA) to achieve hardware-efficient constant flagged adder. These two algorithms are designed to lower the computational complexity. The OCG algorithm accepts the constant to be added and converts it into an optimized constant. This optimized constant then forms the input to the HOA where the hardware modifications are performed. Unlike the proposed work, the existing flagged adder structures do not provide a general methodology to obtain the optimized constant and hardware for all the constants, resulting from the presence of architectural customization for all constants and word lengths. Exhaustive hardware analyses have been carried out to prove the efficacy of the proposed architecture against the existing designs. Structural Verilog code is synthesized for each to obtain the area, delay and power. Synthesis results show up to 35.85% and 49.24% reductions in area–delay and power–delay products, respectively. The improved speed and lower hardware requirements make the proposed methodology a suitable choice for constant addition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500275
       
  • Fractal Feature Based Image Resolution Enhancement Using Wavelet–Fractal
           Transformation in Gradient Domain

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      Authors: Shyo Prakash Jakhar, Amita Nandal, Arvind Dhaka, Bojie Jiang, Liang Zhou, Vishnu Narayan Mishra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The fractal geometries are applied extensively in many applications like pattern recognition, texture analysis and segmentation. The application of fractal geometry requires estimation of the fractal features. The fractal dimension and fractal length are found effective to analyze and measure image features, such as texture, resolution, etc. This paper proposes a new wavelet–fractal technique for image resolution enhancement. The resolution of the wavelet sub-bands are improved using scaling operator and then it is transformed into texture vector. The proposed method then computes fractal dimension and fractal length in gradient domain which is used for resolution enhancement. It is observed that by using scaling operator in the gradient domain, the fractal dimension and fractal length becomes scale invariant. The major advantage of the proposed wavelet–fractal technique is that the feature vector retains fractal dimension and fractal length both. Thus, the resolution enhanced image restores the texture information well. The texture information has also been observed in terms of fractal dimension with varied sample size. We present qualitative and quantitative analysis of the proposed method with existing state of art methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500354
       
  • Energy Management of Parallel Hybrid Electric Vehicle Based on Fuzzy Logic
           Control Strategies

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      Authors: Naila Ben Halima, Naourez Ben Hadj, Mohamed Chaieb, Rafik Neji
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Currently, the parallel hybrid electric vehicle (PHEV) is the most common type of architecture on the hybrid vehicle market. Therefore, a PHEV can be a solution to reduce emission and fuel consumption. The main challenge in the development of HEVs is the power management between the components that ensure vehicle movement. Energy management is now highly necessary by applying a control strategy (CS) in the vehicle’s traction chain, which directly affects the PHEV emission and fuel economy. The CSs have different performances, namely the control of the different power sources operation mode and the control of the battery state of charge. For this purpose, we propose a fuzzy logic CS to optimize emissions (FLCS-em) for PHEV. To assess this approach, we compare it with the most commonly used and recent EMS, in particular the strategy to optimize fuel use (FLCS-f), the efficiency optimization strategy (FLCS-eff) and the electric assist CS (EACS), in urban and highway driving cycles. The results show that the elaborate FLCS-em, characterized by a limited number of rulers, provide significant advantage than CSs mentioned in terms of the efficiency of PHEV performance and emissions and fuel consumption minimization.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-24T07:00:00Z
      DOI: 10.1142/S021812662350007X
       
  • High-Performance Hardware Implementation of the KATAN Lightweight
           Cryptographic Cipher

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      Authors: Muntaser Al-Moselly, Ali Al-Haj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Lightweight cryptography has been proposed recently as an attractive solution to provide security for the ever-growing number of IoT resource-constrained devices. Many of the proposed lightweight cryptographic ciphers have been implemented in software. However, for practical embedded IoT applications, hardware implementations are preferred because they have small silicon area and low-power consumption. In this paper, we present a transistor-level hardware implementation of the well-known KATAN lightweight cipher. This cipher has been chosen due to its operational simplicity and high levels of security. Moreover, the structure of the KATAN cipher lends itself naturally for transistor-level hardware implementation. The design has been implemented at the transistor level using the advanced new 28-nm CMOS technology which facilitates optimized designs for the resource-constrained IoT devices. The proposed VLSI KATAN encryption and decryption circuits have been designed and simulated using the Synopsys Custom Designer Tool using 28-nm technology, 0.9 v supply voltage and a 1[math]GHz clock signal. The KATAN encryption circuit has 312 GE (Gate Equivalent) without key and irregular update registers, and 1081 GE for the overall design, and the decryption circuit has 390 GE without memory registers and 6867 GE for the overall design.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-24T07:00:00Z
      DOI: 10.1142/S0218126623500172
       
  • An Improved Long Short-Term Memory Neural Network Wind Power Forecast
           Algorithm Based on Temd Noise Reduction

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      Authors: Hong You, Zhixiong Li, Xiaolei Chen, Lingxiang Huang, Feng Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To accurately predict the wind power and adopt methods to balance the fluctuation of power grid, an improved long short-term memory (LSTM) neural network wind power forecast algorithm based on noise reduction by threshold empirical modal decomposition (TEMD) is proposed. First, the actual operation and maintenance data of wind farms are normalized and divided into a training set and a test set. Then, an LSTM structure is designed and a Sub-Grid Search (SGS) algorithm is proposed to optimize the hyperparameters of the LSTM network. Finally, the power data are decomposed and noise-reduced using TEMD is improved by the variable-point technique and the TEMD-LSTM power forecast model is constructed to predict the power in time. The predicted values obtained are restored and evaluated by the original size. The results show that compared with five other algorithms of the same kind, the proposed algorithm in this paper has a root mean square error (RMSE) of 30.40, a trend accuracy (TA) value of 67.23% and a training time of 886 s, with the best overall performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-24T07:00:00Z
      DOI: 10.1142/S0218126623500299
       
  • Low-Complexity I/Q Imbalance Calibration Algorithm Based on Zero-IF
           Receiver

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      Authors: Zhi Li, YaFeng Yao, QunQun Zhou, DongBin Fu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although the scheme of designing transceiver with zero-IF architecture reduces the design cost, complexity and power loss of the system, this architecture is more sensitive to the I/Q mismatch problem existing in the analog front-end and it is difficult to eliminate the image interference caused by the mismatch. Therefore, a fast and low-cost I/Q imbalance calibration algorithm is needed. As for the problem of I/Q imbalance in zero-IF receiver, a blind estimation algorithm for extracting the calibration parameters and signal compensation is proposed because of the complexity of calculation and hardware circuit, as well as the power consumption of resources under the traditional algorithm. Based on the statistical property of the signal, this algorithm has the specific characteristics of low computational complexity and being easy to implement in hardware circuit. Due to different ideas of parameters extraction, a special calibration model is designed. The result of simulation shows that the proposed algorithm has not only better performance in compensation parameters estimation, but also better calibration performance than the traditional algorithm. By comparing the calibration performance in the case of different gain imbalances or phase imbalances, we can see that the algorithm can maintain a good calibration performance under different imbalance conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-24T07:00:00Z
      DOI: 10.1142/S0218126623500305
       
  • An Electronically Tunable Meminductor Emulator and Its Application in
           Chaotic Oscillator and Adaptive Learning Circuit

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      Authors: Nisha Yadav, Shireesh Kumar Rai, Rishikesh Pandey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new design of meminductor emulator has been suggested using voltage differencing buffered amplifier (VDBA), current differencing buffered amplifier (CDBA), a resistor and two grounded capacitors. The key advantages of the proposed meminductor emulator circuits are their design simplicity, implementation without memristors and easily adjustable design for grounded/floating decremental to incremental configurations. The proposed circuits have been designed and simulated using 180-nm process technologies in the Mentor Graphics Eldo simulation tool. The nonvolatility and Monte Carlo analysis of the proposed meminductor emulators have been given. A comparison table has also been presented to discuss the benefits of the suggested meminductor emulator designs with existing designs. The operation of the designed emulator has been corroborated by using it in the chaotic oscillator and neuromorphic circuit applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-22T07:00:00Z
      DOI: 10.1142/S0218126623500317
       
  • A Compressed Model-Agnostic Meta-Learning Model Based on Pruning for
           Disease Diagnosis

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      Authors: Xiangjun Hu, Xiuxiu Ding, Dongpeng Bai, Qingchen Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Meta-learning has been widely used in medical image analysis. However, it requires a large amount of storage space and computing resources to train and use neural networks, especially model-agnostic meta-learning (MAML) models, making networks difficult to deploy on embedded systems and low-power devices for smart healthcare. Aiming at this problem, we explore to compress a MAML model with pruning methods for disease diagnosis. First, for each task, we find unimportant and redundant connections in MAML for its classification, respectively. Next, we find common unimportant connections for most tasks with intersections. Finally, we prune the common unimportant connections of the initial network. We conduct some experiments to assess the proposed model by comparison with MAML on Omniglot dataset and MiniImagenet dataset. The results show that our method reduces 40% parameters of the raw models, without incurring accuracy loss, demonstrating the potential of the proposed method for disease diagnosis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-20T07:00:00Z
      DOI: 10.1142/S0218126623500226
       
  • Dynamic First Access Isolation Cache to Eliminate Reuse-Based Cache Side
           Channel Attacks

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      Authors: Chong Wang, Hong Yu, Shuai Wei, Ke Song
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cache side channel attacks have been used to extract users’ sensitive information such as cryptographic keys. In particular, the reuse-based cache side channel attacks exploit the shared code or data between the attacker and the victim, which can steal the secret with high speed and precision. It has threatened not only the host level but also the cloud level severely. Previous defensive measures are either not flexible enough, or cause a high performance or storage overhead. In this work, we present a dynamic first access isolation cache that eliminates reuse-based cache side channel attacks by providing fine grained first access isolation to overcome these problems. First of all, there are [math] bits in each cache line to record the access information and prevent the first time cache hit state brought by the victim from being utilized by the attacker while keeping data shared. Second, we use hierarchy security levels and domains to achieve flexible one way isolation between different domains, and the domains can be a group of processes, a single process, or even a fraction of code. Finally, the monitoring-driven dynamic scheduling mechanism can change the level of a domain at run time, which improves the robustness of this new design. The solution works at all the cache levels and defends against attackers running both on local and cloud. Our implementation in the Zsim simulator demonstrates that the performance overhead for standard performance evaluation corporation 2017 is less than 0.1%, and 0.21% for the multi-thread benchmarks. It performs better than the original first time miss design because of the one way isolation in our design. The only hardware modification is the [math] bits per cache line, and several security registers per hardware context, which only brings 3.71% storage overhead.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-19T07:00:00Z
      DOI: 10.1142/S0218126623500263
       
  • Sensitivity Assessment of Electrically Doped Cavity on Source Junctionless
           Tunnel Field-Effect Transistor-Based Biosensor

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      Authors: Mukesh Kumar Bind, Kaushal Nigam, Sajai Vir Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The tunnel field-effect transistor (TFET) has emerged as a promising device for biosensing applications due to band-to-band tunneling (BTBT) operation mechanism and a steep subthreshold swing. In this paper, an electrically doped cavity on source junctionless tunnel field-effect transistor (ED-CS-JLTFET)-based biosensor is proposed for label-free detection of biomolecules. In the proposed model, the electrically doped concept is enabled to reduce fabrication complexity and cost. In order to create a nano-cavity at the source region, some portion of the dielectric oxide of the polarity gate terminal is etched away. To perceive the presence of biomolecules, two important properties of biomolecules, such as dielectric constant and charge density, are incorporated throughout the simulation. The sensing performance of the proposed ED-CS-JLTFET-based biosensor has been analyzed in terms of transfer characteristics, threshold voltage and subthreshold swing. In addition, the sensitivity of the proposed biosensor has also been analyzed with respect to different fill factors (FFs), varying nano-cavity dimension and work-function of the control gate. It is found from the simulated results that the proposed ED-CS-JLTFET-based biosensor offers higher current sensitivities with neutral, positively charged and negatively charged biomolecules of [math] (at k [math]), [math] (at [math] and [math] C[math]cm[math]) and [math] (at k [math] and [math] C[math]cm[math]), respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-17T07:00:00Z
      DOI: 10.1142/S0218126623500184
       
  • Transformation Invariant Pashto Handwritten Text Classification and
           Prediction

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      Authors: Muhammad Shabir, Naveed Islam, Zahoor Jan, Inayat Khan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The use of handwritten recognition tools has increased yearly in various commercialized fields. Due to this, handwritten classification, recognition, and detection have become an exciting research subject for many scholars. Different techniques have been provided to improve character recognition accuracy while reducing time for languages like English, Arabic, Chinese and European languages. The local or regional languages need to consider for research to increase the scope of handwritten recognition tools to the global level. This paper presents a machine learning-based technique that provides an accurate, robust, and fast solution for handwritten Pashto text classification and recognition. Pashto belongs to cursive script division, which has numerous challenges to classify and recognize. The first challenge during this research is developing efficient and full-fledged datasets. The efficient recognition or prediction of Pashto handwritten text is impossible by using ordinary feature extraction due to natural transformations and handwriting variations. We propose some useful invariant features extracting techniques for handwritten Pashto text, i.e., radial, orthographic grid, perspective projection grid, retina, the slope of word trajectories, and cosine angles of tangent lines. During the dataset creation, salt and pepper noise was generated, which was removed using the statistical filter. Another challenge to face was the invalid disconnected handwritten stroke trajectory of words. We also proposed a technique to minimize the problem of disconnection of word trajectory. The proposed approach uses a linear support vector machine (SVM) and RBF-based SVM for classification and recognition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-17T07:00:00Z
      DOI: 10.1142/S0218126623500202
       
  • 10-Bit 200[math]kHz/8-Channel Incremental ADC for Biosensor Applications

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      Authors: Priya Gupta, Aruj Earnest, Srinjoy Mitra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a second-order discrete-time (DT) modulator for 8-channel Incremental Sigma-Delta analog-to-digital converter (IADC) is presented for biomedical applications ranging from kHz. The proposed DT modulator with input bandwidth of 25[math]kHz on each channel is sampled at 51.2[math]MHz, with oversampling ratio of 128 implemented at 180[math]nm technology. The proposed IADC has high resolution, multichannel A/D conversion, simple architecture, low offset, low gain error and low area over the standard ADCs available. Measured results show that the SNR, DR, ENOB, power consumption and chip area of the proposed IADC are 63.9[math]dB, 62.2[math]dB, 10.11 bits, 0.832[math]mW and 0.032[math]mm2, respectively, at 1.8V power supply. For testing purpose, the noncoherent sampling is done to get the FFT plot of the output signal. For further validation, the proposed second-order IADC was also designed and compared in MATLAB/Simulink.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-17T07:00:00Z
      DOI: 10.1142/S0218126623500251
       
  • Simulated Annealing Algorithm-Aided SC Decoder for Polar Codes

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      Authors: Guiping Li, Ye Tang, Liu He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-13T07:00:00Z
      DOI: 10.1142/S0218126622503042
       
  • Inter-Turn Short-Circuit Faults Detection and Monitoring of Induction
           Machines Using WPT-Fuzzy Logic Approach Based on Online Condition

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      Authors: Raja Rajeswari Indiran, Albert Alexander Stonier
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes an efficient fuzzy logic-based fault detection scheme for diagnosing the inter-turn short-circuit (ITSC) faults in induction motors (IMs). The proposed approach utilizes the fast Fourier transforms (FFTs) and wavelet packet transform (WPT) for this detection of fault. To improve the efficiency and secure the operation, the proposed approach is detecting the fault in online manner. The WPT is utilized to extract the stator current signal into time-frequency domain characteristics. The variation in the amplitude of the vibration spectrum at different characteristic frequencies by FFT is utilized to identify the stator ITSC. The vibration signal is dignified by a MEMS accelerometer. The performance of the fuzzy logic fault detector (FLFD) for online condition is monitored with stator current, vibration and input speed. The performance of the proposed approach is performed at MATLAB/Simulink working site, and then the performance is compared to other existing works. The accuracy, precision, recall and specificity of the proposed approach are analyzed. Similarly, the statistical measures like root mean square error (RMSE), mean absolute percentage error (MAPE), mean bias error (MBE) and consumption time are analyzed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-13T07:00:00Z
      DOI: 10.1142/S0218126623500019
       
  • Design and Implementation of Face Detection Architecture for Heterogeneous
           System-on-Chip

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      Authors: Nidhi Panda, Supratim Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The seminal work of Viola and Jones for automatic face detection is widely used in many human–computer interaction and computer vision applications. On analyzing the existing face detection architectures, we observed that integral image calculation, feature computation in cascaded classifier, and recursive scanning of image with sliding window at multiple scales are the major reasons which increase the memory and time complexity of the algorithm. Therefore, in this paper, we have proposed a hardware–software co-design of Viola–Jones face detector for System-on-Chip (SoC). In the proposed architecture, integral image computation and cascaded classifier sub-modules are implemented on the hardware — Programmable Logic FPGA (PL-FPGA), while the image scaling and nonmaximum suppression sub-modules are implemented on the software — Processing System ARM (PS-ARM). Concepts of pipelining, folding, and parallel processing are effectively utilized to produce an optimum design architecture. The proposed architecture has been tested on PYNQ-Z1 board. The implementation results in a processing speed of [math] fps with PL and PS clocks of [math][math]MHz and [math][math]MHz, respectively, for an image of QVGA resolution. Results analysis demonstrates that the proposed architecture has minimum resource requirement as compared to state-of-the-art implementations, which facilitates and promotes the usage of resource-constrained low-cost ZYNQ SoC for face detection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-13T07:00:00Z
      DOI: 10.1142/S0218126623500214
       
  • CMOS Transistors Based First-Order Voltage-Mode All-Pass Filter with
           Tunable Transformation Possibility

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      Authors: Shiv Narain Gupta, Bhartendu Chaturvedi, Jitendra Mohan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel complementary metal-oxide semiconductor (CMOS) transistors based first-order voltage-mode all-pass filter is proposed. The filter circuit employs six metal-oxide semiconductor (MOS) transistors and minimal number of passive components, i.e., a resistor and a capacitor. The core of the proposed filter is a CMOS inverting amplifier with unity gain. The proposed circuit exhibits some attractive features such as compact design, high input impedance and ability to provide non-inverting and inverting all-pass responses simultaneously. Additionally, it does not require any kind of passive element matching constraints. Furthermore, by replacing the passive resistor with an active negative channel metal-oxide semiconductor (NMOS) transistor, the proposed filter is enriched with the much-desired feature of tunability. The theoretical behavior is tested and demonstrated by carrying SPICE simulations using TSMC 0.18[math][math]m level-7 CMOS process parameters.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-11T07:00:00Z
      DOI: 10.1142/S0218126622502942
       
  • Bullet Train Motion Video-Based Noise-Barrier Defects Inspection Method

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      Authors: Hongwei Zhao, Huating Xu, Yidong Li, Rui Dong, Junbo Liu, Shengchun Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Vision-based automatic noise-barrier inspection of high-speed railway, instead of manual patrol, remains a great challenge. Even though many supervised learning-based methods have been developed, massive redundant video frames and scarce defective samples are the main obstacles to leverage the performance of the noise-barrier inspection task. To tackle the problems, we present a novel Vision-based Noise-barrier Inspection System (VNIS), which is deployed on the bullet train to inspect the noise-barrier defects by using motion video. VNIS uses the proposed panorama generation model based on motion video to obtain panoramic images from massive redundant video sequences. Then, we employ a self-supervised learning deep network to solve the problem of the scarce defective samples. Comprehensive experiments are conducted on a large-scale video dataset of bullet train. VNIS yields competitive performance on noise-barrier defects inspection. Specifically, an average accuracy of 99.14% is achieved for noise-barrier defects inspection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-10T07:00:00Z
      DOI: 10.1142/S0218126623500044
       
  • An Improved Switched-Inductor and Switched-Capacitor Networks-Based
           High-Step-Up-Ratio DC–DC Converter

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      Authors: Ramu Bhukya, N. Shanmugasundaram
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Achieving higher voltage at load side is essential in many applications, especially in small-scale solar PV systems. Traditional boost converter fails to lift the voltage level beyond five times due to saturation in the passive elements. In order to attain high voltage gain ratio, a novel switched-inductor and switched-capacitor networks-based high-gain step-up converter is proposed in this paper. It can attain higher voltage gain at lower duty ratios, thereby reducing the losses associated with the converter and enhancing the efficiency. The detailed analysis of the proposed converter has been made under the CCM and DCM conditions. Moreover, investigation on device stresses is carried out and the results are compared with recently derived converters. Also, the performance comparison of the proposed converter with other published topologies is presented in this paper. In order to validate the operation details, the measured results are presented and the same have been confirmed with the theoretical approach. Furthermore, experimental works have been carried out and the results are presented to confirm the feasibility of the operation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-10T07:00:00Z
      DOI: 10.1142/S021812662350010X
       
  • A C-Band Broadband Asymmetric Doherty Power Amplifier Using Phase
           Compensation and Low Q Technology

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      Authors: Ligong Sun, Deyong Wang, Jincan Zhang, Juwei Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a monolithic microwave-integrated circuit (MMIC) asymmetric Doherty power amplifier (ADPA) using 0.25[math][math]m gallium-nitride (GaN) process with a compact chip size of [math] in wireless transmitters. Two different power amplifiers are adopted to solve the contradiction between the output power and efficiency of the conventional Doherty power amplifier (CDPA). In addition, phase compensation and low Q impedance inverting network (IIN) technology are used in the input and output matching networks, respectively, to expand the bandwidth of the entire ADPA. The post-layout simulation results show that the designed ADPA has a saturation output power 42.5[math]dBm with 800[math]MHz bandwidth from 6.6 to 7.4[math]GHz. The ADPA demonstrates 36.8–41.8% power-added efficiency (PAE), whereas 44–54% drain efficiency (DE) is achieved at saturation power.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-10T07:00:00Z
      DOI: 10.1142/S0218126623500160
       
  • Prognosis of Cervical Cancer Disease by Applying Machine Learning
           Techniques

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      Authors: Gaurav Kumawat, Santosh Kumar Vishwakarma, Prasun Chakrabarti, Pankaj Chittora, Tulika Chakrabarti, Jerry Chun-Wei Lin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cervical cancer is one of the deadliest diseases in women worldwide. It is caused by long-term infection of the skin cells and mucosal cells of the genital area of women. The most disturbing thing about this cancer is the fact that it does not show any symptoms when it occurs. In the diagnosis and prognosis of cervical cancer disease, machine learning has the potential to help detect it at an early stage. In this paper, we analyzed different supervised machine learning techniques to detect cervical cancer at an early stage. To train the machine learning model, a cervical cancer dataset from the UCI repository was used. The different methods were evaluated using this dataset of 858 cervical cancer patients with 36 risk factors and one outcome variable. Six classification algorithms were applied in this study, including an artificial neural network, a Bayesian network, an SVM, a random tree, a logistic tree, and an XG-boost tree. All models were trained with and without a feature selection algorithm to compare the performance and accuracy of the classifiers. Three feature selection algorithms were used, namely (i) relief rank, (ii) wrapper method and (iii) LASSO regression. The maximum accuracy of 94.94% was recorded using XG Boost with complete features. It is also observed that for this dataset, in some cases, the feature selection algorithm performs better. Machine learning has been shown to have advantages over traditional statistical models when it comes to dealing with the complexity of large-scale data and uncovering prognostic features. It offers much potential for clinical use and for improving the treatment of cervical cancer. However, the limitations of prediction studies and models, such as simplified, incomplete information, overfitting, and lack of interpretability, suggest that further efforts are needed to improve the accuracy, reliability, and practicality of clinical outcome prediction.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-10T07:00:00Z
      DOI: 10.1142/S0218126623500196
       
  • Cybersecurity for Battlefield of Things — A Comprehensive
           Review

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      Authors: Anuraj Singh, Gaurav Sharma, Rajalakshmi Krishnamurthi, Adarsh Kumar, Surbhi Bhatia, Arwa Mashat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Battlefield of Things (BoT) is a modern defense network that connects smart military devices to strategic networks. Cybersecurity plays a vital role in maintaining the security of BoT networks and provides encrypted communication networks with combat devices on an end-to-end or peer-to-peer basis. This paper proposes approaches to BoT networks that operate on a three-tier architecture, starting with an application and service layer, a network and cybersecurity layer, and finally, a battlefield layer; implements CNN-YOLO-based target detection; and also formulates information security policies, privacy, and IT laws to maintain algorithmic data access and authorization. It connects a battlefield combat equipment network to a command data center’s ground base station wireless, Bluetooth, sensor, radio, and ethernet cable. This paper analyzes prior Internet of Things (IoT) device attack strategies by collecting data sets of IoT security breaches from external sources. How the system security works, what breach techniques an attacker can use, how to avoid these, and how our systems can be strengthened to protect us from future attacks are discussed in detail.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126622300100
       
  • Fault Tolerance Method for Memory Based on Inner Product Similarity and
           Experimental Study on Heavy Ion Irradiation

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      Authors: Cuiping Shao, Huiyun Li, Guanghua Du, Jinlong Guo, Zujia Miao, Hongmei Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As the feature sizes of integrated circuits are reduced to the nanometer scale, the total soft error rate (SER) in memory and the proportion of multiple bit upsets (MBUs) are significantly increasing. In order to ensure the information reliability, many error correction codes with strong error correction ability were proposed, such as Reed–Somolon (RS) code and Bose–Chaudhuri–Hocquenghem (BCH) code. However, these error correction codes have limited error correction capability, high algorithm complexity and large data redundancy. In this paper, a novel fault tolerance method for locating and correcting multiple bit errors in memory is proposed based on data similarity. The proposed method uses the inner product as the metric to analyze the similarity of the pre-protected data from the vertical and horizontal dimensions, respectively, and to construct the model of error location and correction. This method performs encoding and decoding in units of blocks and detecting and correcting in units of words, so it can correct any number of bits in a corrupted word with low redundancy overhead. Finally, irradiation tests were conducted on a commercial SRAM, and the feasibility of the proposed method is verified by using heavy ion [math]Kr[math] as irradiation source.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126622400060
       
  • A Robust, Scalable, and Energy-Efficient Routing Strategy for UWSN Using a
           Novel Vector-Based Forwarding Routing Protocol

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      Authors: D. Santhi Jeslet, V. Balaji Vijayan, R. Thiagarajan, I. Mohan, R. Kalpana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The Underwater Wireless Sensor Network (UWSN) is capable of supporting a wide range of low-data-rate acoustic sensor networks, as well as scalability and energy-efficient routing algorithms. Furthermore, because of the lower bandwidth and longer propagation delays, energy consumption is a major concern with underwater networks. Because radio transmissions are unstable in deep water, a UWSN often communicates via acoustic channels. UWSN features create constraints on data packet transmission and energy-efficient routing. The hardest challenge is creating an effective routing protocol for UWSNs that uses sensor node localization. There have been several routing algorithms reported for identifying nodes via a localization process. This paper proposes a novel vector-based forwarding (NVBF) and efficient depth-based routing (DBR) protocol to provide robust, scalable, and energy-efficient routing. Efficient DBR is a stochastic model that can survive even in acoustic channels with substantial transmission loss. An adjacent node table is created to decrease the energy consumption and end-to-end delay by limiting the adjacent node request generated every single time. The redundant packet transmission is reduced by creating a packet queue which also minimizes the energy. The NVBF algorithm uses a random waiting time to overcome the collision that occurs while sending the acknowledgment packets. Based on the previous sender’s depth and the depth of the own node, the DBR makes packet transmission decisions. The experiments are conducted using the NS3 simulator and the efficiency of the proposed approach is evaluated in terms of propagation delay, network lifetime, energy consumption, and delivery ratio. When compared to the existing techniques such as DBR, VBF, and energy-efficient DBR (EDBR), the proposed methodology offers improvement up to 40% and 30% in terms of propagation delay and delivery ratio.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126622502656
       
  • Hardware-Based Built-In Security Module in System on Chip (SoC) without
           System Slowdowns or Loss of Productivity

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      Authors: Pradeep Dharane, Ulhas D. Shiurkar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The system environments are built with extensible, flexible, extensible and feature-rich platforms that provide consumers with the benefits of several services, applications and devices. However, the evolution of the internet and shared networks has changed the computing systems more vulnerable to attacks based on the operating system, software and hardware levels. Due to this, there is a growing need to ensure the software and hardware platforms are being secured from viruses or other unauthorized operations. In this paper, a new Hardware-based built-in security module has been proposed in System on Chip (SoC) without loss of productivity and system slowdown. The proposed process integrates a Hardware security module within the SoC, and it establishes higher visibility and controllability of the SoC than achieved from an external device. First, the proposed method allows the SoC to check without dependency on other unsecured elements within the system. Then, the method can examine some components within the SoC on its own to test from time-to-time that no unauthorized access or attempts to bypass the integrity of the system or SoC has been made. After, it allows the SoC to be controlled without any dependency on other unsecured components or communication via unsecured external interfaces. IxChariot is used to carry out the performance test, and then the hardware-based security is proved using Atheros Mini PCIeXB112 cards. As a result, better TCP throughputs of 571, 571 and 604 have been determined in normal mode, and in burst mode, 580, 572 and 619 throughputs have been determined. Finally, the security hardware provides security without system slowdown or lost productivity and burdening the host processor.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126622503170
       
  • Chaotic RF Generator for Sub-1-GHz Chaos-Based Communication Systems:
           Mathematical Modeling and Experimental Validation

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      Authors: Moundher Messaadi, Said Sadoudi, Achour Ouslimani, Djamal Teguig, Hichem Bendecheche
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we have studied, designed and realized a single-transistor chaotic generator with a smooth power spectrum of about [math]35[math]dBm in frequency bandwidth up to 1[math]GHz. The chaos generator model is described by a continuous-time six-dimensional autonomous system assuming an exponential nonlinearity. Chaotic behavior is characterized by bifurcation diagrams, Lyapunov exponents, phase portraits of the attractors and spectra of the oscillations, using both numerical and circuit simulations. Advanced Design System (ADS)-based simulations were carried out to support the theoretical analysis, and to validate the mathematical model. The simulations are carried out using real transistor parameters and taking into account the properties of the substrate, the influence of the board topology and the characteristics of the layout material. This simulation method known as EM/Circuit Co-Simulation allows the simulation results to approach as closely as possible to those of the experiments. In the light of the positive simulation results, the proposed structure is realized to demonstrate its feasibility, and to confirm the numerical results. The prototype is manufactured and mounted on a breadboard using the surface-mount devices and BFP193 bipolar junction transistor. After realizing the generator, we pushed it further towards perfection, through the proposal and realization of a broadband amplifier, in order to gain more bandwidth to improve the spectral characteristic of the generator, which makes it promising for many communication applications such as spread spectrum communication, direct chaotic communication, etc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126623500020
       
  • Cooperative Autonomous Driving for Urban Intersections Assisted by
           Vehicular Sensor Networks

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      Authors: Momiao Zhou, Pengcheng Wang, Zhizhong Ding, Zhengqiong Liu, Jian Niu, Jie Shen, Liu He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The current autonomous driving vehicles cannot collaborate with each other due to the disconnection of sensors between vehicles, which leads to poor performance in traffic efficiency and safety. Recently, with the development of wireless intelligent sensors, vehicular sensor network (VSN) is emerging to provide information sharing between vehicles, so that cooperative autonomous driving (CAD) can be enabled. This paper especially investigates the VSN-assisted straight-going CAD at urban intersections under the rule of traffic signals. First, the function of VSN is presented, and the information sharing mechanism is designed. Then distributed stop-and-go strategies with maintaining the optimal safety spacing between adjacent vehicles are proposed for multiple traffic cases. With the proposed strategies, every vehicle can get an exact time to decelerate or accelerate at signalized intersections. Finally, we use the model predictive control (MPC) scheme to actuate our strategies, and it is demonstrated that vehicles perform well in both passage safety and efficiency as expected.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126623500056
       
  • TS Model-LMI Based Observer for Improving Active Power Filter Performance

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      Authors: R. A. de J. Terán, J. Pérez, J. A. Beristáin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To avoid the negative effects of using a control signal with a ripple, which is generated by the feedback of measured active power filter (APF) variables, a nonlinear observer is employed in this paper. The observer design, through the use of exact TS models and Lyapunov-based LMI conditions, is achieved. Both the APF output current and the DC voltage are estimated by the observer, and they are used in the cascade control feedback. In this way, high gains in the inner control loop are employed, giving place to a control signal without undesired harmonic components or overmodulation. This allows an APF performance improvement for compensation tasks and for reducing the undesired components injection to the mains. A simulation and experimental comparison between APF results using observer and APF results without using observer is presented. Better results are achieved for the observer version case, reducing the THD from 47.6% to 4.8% in experimental conditions, satisfying the IEEE Standard 519TM-2014. Also, load change tests are carried out, where the stability of the system is kept. Moreover, by using the observer, a DC voltage sensor was not required, reducing the number of system sensors.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126623500081
       
  • Channel Characterization for Hyperloops Using the Nonstationary
           Geometry-Based Model

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      Authors: Kai Wang, Liu Liu, Jiachi Zhang, Tao Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As a novel means of high-speed transportation, the Hyperloop can proceed at an ultra-high speed (more than 1000[math]km/h) in the long and narrow pipelines. In this paper, the channel characteristic of the Hyperloop wireless communication systems is the main objective. Based on the geometric scattering theories, a novel nonstationary channel model is proposed to investigate the channel characteristics for Hyperloop train-to-ground communications. According to this model, the channel impulse response (CIR) is obtained, and the closed-form expressions of the multi-link spatial-temporal correlation functions, including the spatial cross-correlation function (CCF) and the temporal autocorrelation function (ACF) are derived and analyzed. Simulation results show that a high correlation between the multi-link channels in vacuum tube scenario can be observed. The relevant research results will contribute to the design of future Hyperloop wireless communication system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-06T07:00:00Z
      DOI: 10.1142/S0218126623500123
       
  • Resilience Assessment of Multimodal Urban Transport Networks

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      Authors: Yishui Chen, Xiaoya Wang, Xuewang Song, Jianlin Jia, Yanyan Chen, Wen-Long Shang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the development of urbanization and the evolution of urban network systems, multimodal urban transport network (MUTN) systems play a vital role in improving network effects and operational efficiency. However, urban transport networks are easily affected by natural disasters and traffic incidents, which can lead to significant human and economic losses. Accordingly, it is vital to be able to assess the resilience of transport networks in the face of various disruptions. This study, therefore, utilizes complex network theory to analyze the resilience of multimodal urban transport networks, with the resilience accessed based on topological indices. The MUTN in Beijing is selected as a case study for simulation analysis. Based on the road network and subway network, a model MUTN is established, and the Monte Carlo method is used to simulate random attacks. The results show that the MUTN in Beijing has good resilience against disruptions. This study guides the evaluation of the overall resilience of multimodal urban transport networks and will be useful for transportation planners and decision-makers in dealing with emergencies and natural disasters in the future.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-30T07:00:00Z
      DOI: 10.1142/S0218126622503108
       
  • A Graph-Based Clustering Algorithm for the Internet of Vehicles

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      Authors: Fan Yang, ShiLong Zhang, Jie Huang, Yang Cao, Xun Zuo, Chuan Yang, Bo Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the large-scale and ultra-dense Internet of Vehicles (IoVs), constructing the simplest backbone network is an urgent problem to be solved. In fact, constructing the simplest backbone network is an NP-hard problem, and at present, there is no effective solution. In this paper, we propose a graph-based clustering algorithm to solve this problem and construct the simplest backbone network in the large-scale and ultra-dense IoV. We establish a backbone network model for the large-scale and ultra-dense IoV and optimize the backbone network by employing a novel local search iterative algorithm. Simulation results show that with the increase in node density, the number of clusters selected by the proposed algorithm tends to be stable, while the number of optimized clusters decreases by 28.87% on an average. Thus, the proposed algorithm can effectively simplify the backbone network.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-30T07:00:00Z
      DOI: 10.1142/S0218126623500111
       
  • Simulation Analysis of Influencing Factors of fsQCA Calibration Membership

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      Authors: Haiwen Yang, Haifeng Jiang, Yingya Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Based on the analysis of the reasons, principles and classification of fuzzy set data calibration, we analyze that the fuzzy set data calibration membership is influenced by different data distribution, the crossover anchored points setting and transformation selection. Starting from the common problems existing in the current fuzzy-set qualitative comparative analysis (fsQCA) application research, this paper analyzes the possible reasons for ignoring the data calibration research, divides the relationship between the three dimensions of original data distribution, the crossover anchored points setting and calibration transformation and data calibration, and makes a visual analysis on their influence relationship through simulated data. Data distribution, crossover points anchored setting and transformation selection all have a significant impact on fsQCA calibration membership. The distribution of the original data will be a skew attribute consistent with the calibration membership. The cross combination of the high, medium and low setting of the crossover points and the selection of the calibration transformation will produce a significantly different calibration membership, and the crossover points anchored setting has a more obvious impact on the calibration membership than the selection of the calibration transformation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-29T07:00:00Z
      DOI: 10.1142/S0218126622502930
       
  • A Novel, Efficient, Green and Real-Time Load Balancing Algorithm for 5G
           Network Measurement Report Collecting Clusters

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      Authors: Pengfei Zhang, Junhuai Li, Ye Tang, Huaijun Wang, Ting Cao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the wide application of data mining and deep learning in mobile cellular network operation and maintenance, network measurement report (MR) plays an increasingly important role in artificial intelligence for IT operations (AIOps). For the integrity of MR reported by the operation and maintenance (OM) proxy of base station, existing collecting methods are typically based on static distributed clustering. Due to the lack of effective load balancing scheme, nevertheless, these methods typically result in some issues, e.g., low collecting efficiency, poor scalability, and excessive number of servers. Thus, in this work, leveraging the historical law of uploading MR for load forecasting, we propose the weighted least-connection load balancing algorithm (LPWLC) based on load forecasting. First, the historical law of reported MR is utilized to predict the load. Second, using the strategy of static binding and dynamic load adjustment, we bind OM with the assigned server in one cycle, calculate the server load in real-time, and evaluate the server weight by the load of each server. Finally, real-time load adjustment is carried out in line with the number of request connections and the weight of servers. Compared with the existing ones, the proposed algorithm could remove backup servers, thereby effectively reducing the cost and power consumption. Compared with the existing methods, this method has improved the load balancing degree by 28%, and reduced the energy consumption by 104[math]W per hour.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-29T07:00:00Z
      DOI: 10.1142/S0218126622503133
       
  • Improved Read/Write Stability-Based Level Shift 5T Ternary SRAM Cell
           Design using Enhanced Gate Diffusion Input BWGCNTFET

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      Authors: Gopavaram Suneel Kumar, Gannera Mamatha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, CNTFET introduced the complexity of SRAM design along with the stability. To overcome these complexities, an enhanced Gate Diffusion Input technique-based Ballistic wrap gate CNTFET (EGDI-BWGCNTFET) technology with ternary static random-access memory (T-SRAM) is proposed in this paper. The aim of the proposed technique is “to give higher stability with less stagnant power consumption, voltage drop and store appropriate read/write value of the SRAM cells”. Here, level shift 5T ternary SRAM cell design using Enhanced Gate Diffusion Input Ballistic wrap gate CNTFET (level shift EGDI-BWGCNTFET 5T-ternary SRAM) is proposed for improving read and write stability. It uses two cross-coupled EGDI-BWGCNTFET ternary inverter, which is used for data storage elements along with one access transistor which is connected with bit line (BL) and word line (WL) with minimum supply voltage resulting in leakage current that is decreased. By this, proposed method reduces delay in the write cycles and read cycles. It provides good read static noise margin (RSNM) and controls precharge voltage. The proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM is done in HSPICE platform. The performance of the proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM design is measured in terms of lower Read Delay 23.25%, 22.94%, 18.38%, 23.97%, lower Write Delay 33.92%, 28.94%, 42.83%, 31.98% compared with the existing methods, such as 8T CNTFET-Ternary SRAM, 24T CNTFET-2Ternary SRAM, 18T CNTFET-Ternary SRAM and 17T CNTFET-Ternary SRAM, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-29T07:00:00Z
      DOI: 10.1142/S0218126623500032
       
  • MSK-UNET: A Modified U-Net Architecture Based on Selective Kernel with
           Multi-Scale Input for Pavement Crack Detection

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      Authors: Xiaoliang Jiang, Jinyun Jiang, Jianping Yu, Jun Wang, Ban Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Pavement crack condition is a vitally important indicator for road maintenance and driving safety. However, due to the interference of complex environment, such as illumination, shadow and noise, the automatic crack detection solution cannot meet the requirements of accuracy and efficiency. In this paper, we present an extended version of U-Net framework, named MSK-UNet, for pavement crack to solve these challenging problems. Specifically, first, the U-shaped network structure is chosen as the framework to extract more hierarchical representation. Second, we introduce selective kernel (SK) units to replace U-Net’s standard convolution blocks for obtaining the receptive fields with distinct scales. Third, multi-scale input layer establishes an image pyramid to retain more image context information at the encoder stage. Finally, a hybrid loss function including generalized Dice loss with Focal loss is employed. In addition, a regularization term is defined to reduce the impact of imbalance between positive and negative samples. To evaluate the performance of our algorithm, some tests were conducted on DeepCrack dataset, AsphaltCrack300 dataset and Crack500 dataset. Experimental results show that our approach can detect various crack types with diverse conditions, obtains a better performance in precision, recall and [math]-score, with 97.43%, 96.95% and 97.01% precision values, 82.51%, 93.33% and 87.58% recall values and 95.33%, 99.24% and 98.55% [math]-score values, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-28T07:00:00Z
      DOI: 10.1142/S0218126623500068
       
  • Design and Realization of a Broadband Multi-Beam [math] Array Antenna
           Based on [math] Butler Matrix for 2.45 GHz RFID Reader Applications

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      Authors: Abdelaaziz El Ansari, Sudipta Das, Ikram Tabakh, B. T. P. Madhav, Abdelhak Bendali, Najiba El Amrani El Idrissi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents design and analysis of a beam switchable [math] array patch antenna fed by a [math] Butler matrix based hybrid coupler for 2.45[math]GHz radio frequency identification (RFID) reader applications in the ISM band. The proposed beam switchable array antenna arrangement consists of two identical patch elements, a pleated quarter-wavelength impedance transformer (PQWIT), and a hybrid coupler. The concept of PQWIT has been utilized to reduce the overall implementation area of the patch elements. The overall area of the patch element is miniaturized by 50% due to the implementation of PQWIT. This miniaturized antenna is used as a radiating element for designing a beam switchable [math] array antenna fed by a hybrid coupler. The proposed antenna prototype has been fabricated on a 1.56[math]mm thick Rogers RT/duroid 5880 substrate with a physical area of [math][math]mm2. The simulation and measured results exhibit good agreements. The designed antenna offers a broad bandwidth of 844[math]MHz (1.956–2.80[math]GHz), peak gain of 8.86 dB, peak radiation efficiency of 99.52% and has two switchable beams in the directions [math] and [math]. The suggested switched beam array antenna is suitable for RFID reader applications at 2.45[math]GHz for tracking of moving objects.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-27T07:00:00Z
      DOI: 10.1142/S0218126622503054
       
  • Reconfigurable Turbo and Low-Density Parity-Check (LDPC) Decoding
           Accelerators for Powerline Communications

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      Authors: Cheng-Hung Lin, Jin-Kun Shen, Cheng-Kai Lu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This study presents two reconfigurable turbo/low-density parity-check (LDPC) decoding kernels for the two powerline communication standards, HomePlug and G.hn. Two architectures are presented, both of which use the radix-4 double-binary enhanced max-log maximum a posteriori probability algorithm with next-iteration initialization in turbo decoding. In LDPC decoding, the two architectures employ the normalized min-sum and the layered radix-4 forward and backward algorithms. The two algorithms cause differences in the architecture and throughput rate. Consequently, the proposed decoding kernels have different architectures when combined with the turbo decoding algorithm, and the two proposed decoding kernels each have their own advantages and disadvantages in terms of throughput and area cost. To make the features of two kernels more evident, we have implemented the proposed decoding kernels that lead to significant throughput gains and better area efficiency compared with other studies. The proposed decoding kernels can be operated in all modes specified in the HomePlug and G.hn standards using a 40-nm complementary metal-oxide-semiconductor (CMOS) process. Moreover, the proposed decoding kernels provide different solutions to achieve the expected throughput rates of the G.hn and HomePlug standards.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503091
       
  • A Novel Morphological Feature Extraction Approach for ECG Signal Analysis
           Based on Generalized Synchrosqueezing Transform, Correntropy Function and
           Adaptive Heuristic Framework in FPGA

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      Authors: Miloni M. Ganatra, Chandresh H. Vithalani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, a computer-aided diagnosis system is required to monitor the cardiac patients continuously and detecting the heart diseases automatically. In this paper, a new field programmable gate array-based morphological feature extraction approach is proposed for electrocardiogram signal analysis. The proposed architecture is mainly based on the Generalized Synchrosqueezing transform but a detrended fluctuation analyzer is applied in the reconstruction stage for capturing the maximum information of QRS complexes and P-waves by eliminating a set of noisy intrinsic modes. Then, a correntropy envelope is determined from the QRS enhanced signal for localizing the QRS region accurately. Also, an adaptive heuristic framework is introduced to detect the true P-wave from the P-wave enhanced reconstructed signal by analyzing both the positive and negative amplitudes. In addition, a root mean square Error estimation-based adaptive thresholding approach is used to estimate the T-wave after removing the P-QRS complexes. The proposed architecture has been implemented on field programmable gate array using the Xilinx Vertex 7 platform. The performance of the proposed architecture is validated by performing a comparative study between the resultant performances and those attained with state-of-the-art feature descriptors, in terms of Sensitivity, accuracy, positive prediction, error rate and field programmable gate array resources estimation. The proposed sensitivity, accuracy and positive prediction are 99.84%, 99.85% and 99.86% for QRS detection approach. The proposed sensitivity, accuracy and positive prediction are 99.45%, 99.23% and 99.78% for P-wave detection approach. The proposed sensitivity, accuracy and positive prediction are 99.58%, 99.65% and 100% for T-wave detection approach. The simulation results show that the proposed architecture overtakes existing designs and minimizes hardware complexity, which proves the suitability of this approach on real-time applications of electrocardiogram signals.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503121
       
  • Efficient Federated Learning Using Layer-Wise Regulation and Momentum
           Aggregation

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      Authors: Fan Zhang, Zekuan Fang, Yiming Li, Mingsong Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Federated Learning (FL) enables multiple parties to train a global model collaboratively without sharing local data. However, a key challenge of FL is data distribution heterogeneity across participants, which causes model drift in local training and significantly reduces the model performance. To address this challenge, we analyze the inconsistency differences between different model layers of local models and further propose Layer-wise Distance Regularization (LWDR) and Layer-wise Momentum Aggregation (LWMA). The proposed LWDR and LWMA optimize the local training and model aggregation processes, respectively, to improve the convergence performance of FL on data in the nonindependent and identically distributed (Non-IID) scenarios. Our experiments on well-known datasets show that our algorithm significantly outperforms the state-of-the-art FL algorithms in convergence speed, accuracy, and stability in different Non-IID scenarios.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503145
       
  • An Optimal Dead Time Compensator Design for Nonsquare Process with
           Disturbance Rejection

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      Authors: Neelbrata Roy, Anindita Sengupta, Ashoke Sutradhar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work aims to establish an optimal design of the Smith dead-time compensator for a nonsquare multivariable system with a transfer function matrix containing first-order dead time elements. The scheme has a set point tracking controller along with disturbance rejection using an optimal estimator. An inverse signal from the estimator eliminates the disturbance. The proposed method significantly improves the disturbance rejection and performance index compared to the other established methods. The common evolutionary algorithms such as the grey wolf optimization technique and teaching learning based algorithm have been used to tune the controllers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503169
       
  • Single-CFOA-Single-External-Capacitor-Based Partially-Active-R SRCOs: The
           Fourth Missing Circuit

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      Authors: Dharmesh Kumar Srivastava, Raj Senani, Data Ram Bhaskar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new single-resistance-controlled-oscillator (SRCO) is presented which employs a single current feedback-operational amplifier (CFOA) along with four resistors but needs only a single external capacitor due to the incorporation of the CFOA-pole in the design. It provides independent control of the condition of oscillation and the frequency of oscillation through two separate resistors. To the best knowledge of the authors, this single-CFOA-based partially active-[math] SRCO has not been reported explicitly in the technical literature earlier and hence is the fourth missing circuit of this class of SRCOs. Experimental results confirming the validity of the new proposition have been included and the comparative features of all the four circuits have been highlighted.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622200043
       
  • Simulation and Structure Optimization of Grounding Circuit Model for Power
           Transmission Line Tower

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      Authors: Yuanchao Hu, Yan Cheng, Zhipeng Jiang, Yunzhu An, Seunggil Jeon, Wen Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The lightning current dispersion process through the steel bar inside the concrete pile foundation of the transmission line tower is impeded by the high concrete resistivity. In order to improve the current dispersion performance of the pile foundation, this paper proposes a method to place flexible graphite grounding electrode along the shaft wall of the tower foundation and verified its feasibility. Both single-pile and four-pile foundations are applied to build vertical grounding models of transmission line tower with three different grounding structures, respectively, including flexible graphite grounding line, flexible graphite grounding fabric and combined graphite electrode. The effect of three grounding structures on the current dispersion and resistance reduction is studied by finite-element method. Simulation results indicate that by applying the above three grounding structures on the vertical pile foundation can significantly improve the current density distribution of the excavated pile foundation and reduce the grounding resistance. When the grounding resistance is [math], the resistance reduction efficiencies of the above three methods can reach 48.56%, 53.86% and 54.53%, respectively. Considering the limited construction area, this paper compares the foundation that is placed combined graphite grounding electrode with square-ray grounding grid, and it can be seen that by placing vertical grounding electrode can save the land area of 295.99[math]m2. This paper can provide reference for the design of excavation pile foundation grounding structure under limited construction area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502784
       
  • A New Secure Crowdfunding Transaction Scheme Based on Blockchain

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      Authors: Guangshun Li, Guopeng Liang, Junhua Wu, Zhenyu Jin, Wenzhen Feng, Kan Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Online crowdfunding, an innovative model based on “[math]”, is a hot spot for financing via Internet. Crowdfunding based on blockchain is an emerging economic phenomenon and becomes one of the most advanced risk financing strategies. However, crowdfunding transactions face security threats due to identity leaks, quantum attacks and the untraceable nature of blind signatures, which facilitate criminal activity. Different from the previous works, which ignored the importance of traceability, in this paper, we establish a blockchain-empowered secure crowdfunding architecture and propose an anti-quantum partially blind signature algorithm based on the verifiable identity of both sides. Specially, for one thing, the private key decided by user identity is generated by lattice-based sample matrix, and the privacy of user identity can be ensured and traced by the rejection sampling theorem. For another thing, we design an improved krill herd algorithm (IKHA) to increase the credit factor of fundraisers for dealing with project investment issues. The simulation evaluates the correctness and effectiveness of our theoretical analyses. Compared with the current popular schemes, the proposed IKH algorithm has a higher convergence speed and can optimize investment efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502826
       
  • Design and Implementation of Low Power, High-Speed Configurable
           Approximation 8-Bit Booth Multiplier

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      Authors: Sampath Kumar, Minakshi Poonia, Rahul Kumar, Gaurav Sharma, Somesh Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502966
       
  • Droplet Routing Based on Double Deep Q-Network Algorithm for Digital
           Microfluidic Biochips

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      Authors: Kolluri Rajesh, Sumanta Pyne
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Digital microfluidic biochips (DMFBs) are emerging as an alternative to the cumbersome traditional laboratories for biochemical analysis. DMFBs come under micro-electro-mechanical systems and are a class of lab-on-a-chip devices. DMFBs provide automation, miniaturization and software programmability. The droplet routing algorithm determines concurrent routes for a set of droplets from their source cells to individual target cells on a DMFB. In this paper, a double deep Q-network (DDQN)-based droplet routing algorithm has been proposed. DDQN is a temporal difference-based deep reinforcement algorithm that combines Double Q-learning with a deep neural network algorithm. In the proposed work, routes for droplets are determined by DDQN, and later collisions are resolved using stalling and/or detouring. The latest arrival time of droplets arriving last at its target and cell utilization is taken as objectives for routing algorithm performance evaluation. The proposed method is evaluated on two standard benchmark suites. Simulation results show that the proposed DDQN-based droplet routing algorithm produces competitive results compared to state-of-the-art algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502991
       
  • A Fully Integrated Mixed-Mode LDO Regulator with Fast Transient Response
           Performance

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      Authors: Khaldoon Abugharbieh, Basel Yaseen, Abdullah Deeb, Hani Ahmad, Ayman Jeit
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2[math]V and produces an output voltage of 1.2[math]V. In simulations, the LDO regulator achieves 143-[math] A quiescent current, [math]56-dB PSRR @ 1-kHz noise frequency and an output voltage drop of around 200[math]mV for a load current step of 100[math]mA. The LDO can provide a maximum load current of 200[math]mA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622503005
       
  • Time Domain Optimize in an Urban Rail Transit Line Based on Passenger Flow
           Spatial and Temporal Distribution

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      Authors: Jinjin Tang, Chao Li, Yuran Liu, Siyang Wu, Linghao Luo, Wen-Long Shang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Focusing on the time domain optimization problem of an urban rail transit line, this paper constructs a passenger travel network with OD passenger flow data as input, by using a multi-path search algorithm based on dynamic cost to deduce the passenger space-time path. The passenger travel path is restored and the spatial and temporal distribution of passenger flow is calculated. Based on this, considering the influence of passenger flow spatial and temporal distribution on the time domain division, the orderly clustering method is used to optimize the time domain. Factoring in the influence of line capacity constraint, train running sequentially on time domain division and bidirectional time domain, a time domain optimization framework for an urban rail line is proposed in this study to integrate the time domain optimization results and improve the adaptability of optimization method. A practical line is taken as an example to verify the effectiveness of the proposed framework. Compared with the traditional time domain division method, the time domain division result accuracy is significantly improved and lays a foundation for the formulation of train service scheme which accurately matches transport capacity to demand.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S021812662250308X
       
  • Image Super-Resolution Method Based on Dual Learning

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      Authors: Zhao Qiu, Chunyu Zhuang, Lihao Liu, Jiale Lin, Sheng Yuan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Existing super-resolution methods convert high-resolution images into low-resolution images, and use the synthesized images as input to train the model. However, it is difficult for synthetic low-resolution images to reflect the characteristics of real low-resolution images, resulting in poor model performance in practical applications. To address this problem, we propose a recurrent super-resolution framework, which consists of a degradation model and a reconstruction model. The degradation model degenerates the real high-resolution image into a more real low-resolution image, which is used as the input of the super-resolution reconstruction network, and then uses the reconstruction model to reconstruct the low-resolution image, and calculates the error with the original image. The generated high-resolution image is input into the degradation model again for degradation processing, forming a symmetrical and cyclic network structure, so that the super-resolution model has a better effect when reconstructing the real low-scoring image. In addition, the spatial attention mechanism is introduced into the generator network, which expands the receptive field of the convolution kernel, better extracts long-distance image features and improves the texture details of super-resolution images, which is consistent with the global.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-22T07:00:00Z
      DOI: 10.1142/S0218126622502838
       
  • A Predictive Noise Shaping SAR ADC with Redundancy

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      Authors: Shuang Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a predictive noise shaping (NS) Successive Approximation (SAR) Analog-to-Digital Converter (ADC), which improves its conversion speed by 25%, compared to its counterpart with 0.3% less redundancy. It begins by investigating the Signal to Noise and Distortion Ratio (SNDR) degradation when using a lower Oversampling Ratio (OSR, e.g., 8) than required in the prior state-of-the-art works, when predicting the first 4 MSBs with a second-order predictor. Later, it compares the SNDR for the same predictor with and without the bit weight redundancy in the capacitor array. In addition, designs with various levels of redundancies and OSRs are compared on their SNDRs. Both MATLAB and Cadence simulation results verified that by introducing 0.3% more redundant bit weight, either 8[math]dB more SNDR at the same bandwidth, or 25% speed improvement can be obtained while maintaining its SNDR.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-22T07:00:00Z
      DOI: 10.1142/S0218126622503078
       
  • A High-Frequency Multi-Mode Universal Filter for GHz Applications in CNFET
           Technology

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      Authors: Mostafa Parvizi, Rana Haratian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new circuit structure of a multi-mode active filter, using only 16 transistors and 2 grounded capacitors in carbon nanotube field-effect transistor (CNFET) technology which is biased at [math][math]V supply. The proposed multi-input, single-output (MISO) filter has the capability of working as low-pass, band-pass, high-pass, band-stop and all-pass filters in all the operating modes (voltage, current, transconductance and transresistance). In addition, the quality factor ([math]) parameter can be tuned electronically independent of the center frequency ([math]). The HSPICE simulation results show that the proposed filter consumes only 971[math][math]W at 1[math]GHz center frequency, assuming [math][math]pF and the nanotube pitch parameter of ([math] nm) and the chiral vector of (22,0), while the number of nanotubes is considered as [math] for all the transistors. Moreover, the main circuit performances such as the center frequency and the power consumption of the circuit vary by 5.4% and 11.6%, respectively, for the standard temperature variation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622502887
       
  • An Adaptive Regulatory Approach to Improve the Power Quality in Solar
           PV-Integrated Low-Voltage Utility Grid

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      Authors: Ch. Phani Kumar, E. B. Elanchezhian, S. Pragaspathy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Solar PV-connected distributed utility grid often faces several issues due to variable penetration of the generated power. It creates frequent disturbance in load side and increases the voltage instability. It is a great challenge to maintain the stability at distributed low-voltage grid and improve the quality of power. In order to overcome this problem, this paper proposes an adaptive voltage and current regulatory approach to improve the power quality in a solar PV-integrated low-voltage utility grid. It supplies auto-adjustable reactive power during the small and large voltage deviations in the grid. The proposed approach assures that the load bus voltage is maintained at 1 p.u. under variable environmental conditions. In addition, the power quality gets improved by injecting the power with improved quality. Three cases of standalone mode, grid-connected modes with and without STATCOM have been investigated and reported in this paper. To validate the proposed adaptive voltage and current regulatory approach, the dynamic results of regulated grid voltage under poor environmental conditions are analyzed and the measured results are presented in this paper. Furthermore, the obtained results are evaluated with the existing approaches such as BAT, firefly and elephant herding optimization (EHO) algorithms and reported in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622503017
       
  • Probabilistic Buckshot-Driven Cluster Head Identification and Accumulative
           Data Encryption in WSN

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      Authors: Parvathaneni Naga Srinivasu, Ranjit Panigrahi, Ashish Singh, Akash Kumar Bhoi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Several nonterminal nodes in the ad-hoc sensor network architecture are involved in effectively communicating data. There are not enough nodes other than the terminals to process sensor data and send it between nodes. Because of this, the exchange of sensor data relies on devices capable of predicting events and responding quickly. Identifying the cluster head is essential to the network’s long-term viability and operational efficiency. This paper proposes a robust probabilistic buckshot approach to identify the appropriate nodes, and the smooth handover mechanism in the corresponding cycles is mechanized. The proposed model also employs a heuristic algorithm named HARIS to identify the best cluster head by analyzing the residual energy associated with each sensor node over multiple iterations. The data exchanged among the nodes is encrypted using a lightweight accumulative data encryption model to ensure the confidentiality of the data. The proposed model is evaluated using various statistical analysis metrics like node availability, computational delay, throughput, and network lifetime. The proposed model outperforms the existing energy-sensitive sensor network models by 20–23%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622503030
       
  • Energy Efficiency Optimization with SINR Constraints in Downlink MIMO-NOMA
           Systems

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      Authors: Fuyuan Xu, Hailin Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In downlink multiple-input, multiple-output, (MIMO) and non-orthogonal multiple access (NOMA) systems, the inter-cluster interference can be cancelled by optimizing pre-coding and detection matrices. Thus, the MIMO-NOMA channel is decomposed into multiple single-input, single-output and (SISO)-MOMA channels. Then, we formulate an energy efficiency (EE) optimization problem subject to the signal-to-interference-plus-noise ratio (SINR) constraints which is non-convex. To solve the problem, we propose the algorithm based on one-dimensional linear search and first-order Taylor expansion. Moreover, as in conventional communication systems, EE and spectrum efficiency (SE) cannot always be improved simultaneously. Thus, the trade-off between EE and SE is investigated based on the formulated problem. Numerical analyses and simulation results verify the proposed algorithm. In addition, the performance in terms of EE and the EE-SE trade-off can be improved by optimizing the user pairing method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622503157
       
  • A Deep Convolutional Neural Network Stacked Ensemble for Malware Threat
           Classification in Internet of Things

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      Authors: Hamad Naeem, Xiaochun Cheng, Farhan Ullah, Sohail Jabbar, Shi Dong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Malicious attacks to software applications are on the rise as more people use Internet of things (IoT) devices and high-speed internet. When a software system crash happens caused by malicious action, a malware imaging method can examine the application. In this study, we present a novel malware classification method that captures suspected operations in a variety of discrete size image features, allowing us to identify such IoT device malware families. To decrease deep neural network training time, essential local and global image features are selected using a combined local and global feature descriptor (LBP-GLCM). The classification performance of the proposed deep learning model is improved by combining the predictions of weak learners (CNNs) and using them as knowledge input to a multi-layer perceptron meta learner. This is a neural network ensemble with stacked generalization that is used to improve network generalization ability. The public dataset used for performance evaluation contains 5472 samples from 11 different malware families. In order to compare the proposed methodology to current malware detection systems, we developed a baseline experiment. The proposed approach improved malware classification results to 98.5% accuracy and 98.4% accuracy when using [math] and [math] image sizes, respectively. Overall, the results showed that the stacked generalization ensemble with multi-step extracting features is a more effective method for classification performance and response time.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-18T07:00:00Z
      DOI: 10.1142/S0218126622503029
       
  • Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma
           ADC

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      Authors: Jinhui Tan, Jishun Kuang, Xing Hu, Lin Xiao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 [math]m BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of [math] for a load capacitance of 2 pF. Output voltage swings are [math] V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162[math][math]m[math][math][math]200.82[math][math]m. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-18T07:00:00Z
      DOI: 10.1142/S0218126622503066
       
  • Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using
           Modified 32-Bit Square Root Carry Select Adder

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      Authors: Raju Ganna, Shanky Saxena, Govind Singh Patel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer’s performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636[math][math]m2, the power is achieved as 50.125[math][math]W and delay is attained to be 1.280[math]ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-15T07:00:00Z
      DOI: 10.1142/S0218126622502929
       
  • Deep Learning-Based Multi-classification for Malware Detection in IoT

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      Authors: Zhiqiang Wang, Qian Liu, Zhuoyue Wang, Yaping Chi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the open-source and versatility of the Android operating system, Android malware has exploded, and the malware detection of Android IoT devices has become a research hotspot in recent years. Static analysis technology cannot effectively analyze obfuscated malware. Without decomposing, the existing detection methods are mainly based on grayscale images and single files without analyzing and verifying their anti-obfuscation performance. In addition, the current detection of Android malware using deep learning is concentrated in the field of binary classification. This paper proposes a multi-classification method of the Android malware family based on multi-class feature files and RGB images to solve these problems. The method proposed in this paper does not need to decompile the Android APK installation package. However, it extracts the DEX file and XML file in batch from the APK installation package. Then, it converts the file into an RGB image using the conversion algorithm that converts Android software into images. Finally, the deep neural network automatically obtains the RGB image texture features to realize the multiple classifications of the Android malware family. Experimental data show that the proposed method has high detection performance, and the accuracy of multiple classifications of the Android malware family is as high as 99.84%. In addition, the method based on RGB image is better than the grayscale image in detection accuracy, and the effect of RGB image combined with DEX and XML is better than that of separate DEX file image and separate XML file image. Therefore, the method proposed in this paper can effectively detect the obfuscated Android malware, and the detection accuracy of 99.23% can be achieved for the obfuscated sample data. Furthermore, this method has good anti-obfuscation ability. The proposed method is compared with those based on Multi-Layer Perceptron, Long Short-Term Memory, bidirectional Long Short-Term Memory and Deep Belief Network. The experimental results show the proposed method’s effectiveness and high generalization performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-15T07:00:00Z
      DOI: 10.1142/S0218126622502978
       
  • Efficient Uncertain Sequence Pattern Mining Based on Hadoop Platform

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      Authors: Jimmy Ming-Tai Wu, Shuo Liu, Jerry Chun-Wei Lin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the Internet of Things (IoT) era, information is collected by sensor devices, resulting in data loss or uncertain data and other consequences. We need to represent the uncertain data collected using probabilities to extract the useful information for production and application from a huge indeterminate data warehouse. The data in the database has a particular order in time or space, so the High-Utility Probability Sequential Pattern Mining (HUPSPM) has become a new investigation and analysis topic in data processing. After the progress of timestamp, many efficient algorithms for sequential mining have been developed. However, these algorithms have a limitation: they can only be executed in a stand-alone environment and are only suitable for small datasets. Therefore, introducing an advanced graph framework for processing large datasets addresses the shortcomings of the existing methods. The proposed algorithm can avoid repeated database searching, splitting the database, and improve the parallel computing capability. The initial database is pruned according to the existing pruning strategy to effectively reduce the number of candidate sets effectively. Experiments show that the algorithm presented in this paper has excellent advantages in mining high-utility probability sequences in large datasets.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-12T07:00:00Z
      DOI: 10.1142/S0218126622502619
       
  • Dual Channel Multiplier for First-Order Piecewise Approximation for GPU

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      Authors: Dina M. Ellaithy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper demonstrates an energy-efficient implementation of piecewise polynomial approximation to evaluate the complex functions of graphical processing units (GPUs). A novel approach is employed to implement the first-order piecewise approximation serially which leads to high savings in power and area. Dual channel multiplier (DCM) scheme is proposed to simplify the hardware architecture of the piecewise polynomial approximation. The proposed methodology is implemented with 90[math]nm CMOS technology and it can perform different complex functions using a simple multiplier hardware structure. DCM achieves improvement in energy saving by up to 81% at a penalty cost of 10 clock cycles. Simulation results confirm that this work attains at least 83%, and 55% saving in power and area as compared to the traditional techniques, respectively. The proposed methodology can implement any degree of the piecewise polynomial approximation utilizing the DCM.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-12T07:00:00Z
      DOI: 10.1142/S021812662250298X
       
  • Controlling a 4D Chaotic Oscillator with a Quadratic Memductance and its
           Implementation

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      Authors: Abdullah Gokyildirim, Abdullah Yesil, Yunus Babacan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Following the experimental realization of memristors, researchers have focused on memristor-based circuits. Chaotic circuits can be implemented easily using a memristor due to its nonvolatile and nonlinear behavior. This study presents a memristor-based four-dimensional (4D) chaotic oscillator with a line equilibria. A memristor having quadratic memductance was utilized to implement the proposed chaotic oscillator. The 4D chaotic oscillator with quartic nonlinearity was designed as a result of the quadratic memductance. In terms of communication security, random number generation and image and audio encryption, systems with quartic nonlinearity or that are higher-dimensional are better than systems that are lower-dimensional or possess quadratic/cubic nonlinearity. The performance of the proposed chaotic circuit was investigated according to properties such as phase portraits, Jacobian matrices, equilibrium points, Lyapunov exponents and bifurcation analyses. Furthermore, the proposed system is multistable and its solutions tend to appear as twin attractors when initial conditions approach their equilibria. The Lyapunov-based nonlinear controller was constructed for controlling the proposed system having a line equilibria. The effect of the initial conditions on the controlling indicators was also studied. In conclusion, by using discrete circuit elements, the proposed circuit was constructed, and its experimental results demonstrated a good agreement with the simulation results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-09T07:00:00Z
      DOI: 10.1142/S0218126622502875
       
  • Current-Mode PID Controller Using Second-Generation Voltage Conveyor
           (VCII)

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      Authors: Emre Özer, Fırat Kaçar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a current-mode (CM) proportional integral derivative (PID) controller based on second-generation voltage conveyor (VCII) is presented. The proposed circuit consists of two-plus type VCIIs, two resistors, and two capacitors. There is no need of critical matching condition. Considering the parasitic impedance, the operating frequency ranges of the proposed PID network are examined. The magnitude and phase responses, Monte Carlo, temperature and input-output noise analyses have been simulated. The simulation results are obtained with the LTspice program using AD844 SPICE macro-model under [math]9[math]V DC supply voltages. The total power consumption of the proposed CM PID controller is 235[math]mW.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-08T07:00:00Z
      DOI: 10.1142/S0218126622502954
       
  • Response of Commercial P-Channel Power VDMOS Transistors to Ionizing
           Irradiation and Bias Temperature Stress

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      Authors: Sandra Veljković, Nikola Mitrović, Vojkan Davidović, Snežana Golubović, Snežana Djorić-Veljković, Albena Paskaleva, Dencho Spassov, Srboljub Stanković, Marko Andjelković, Zoran Prijić, Ivica Manić, Aneta Prijić, Goran Ristić, Danijel Danković
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ([math]) and interface traps ([math]) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of [math] neutralization and [math] passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622400035
       
  • Multimodal Remote Sensing Image Registration Algorithm Based on a New Edge
           Descriptor

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      Authors: Zhili Song, Chaopeng Shi, Fanmei Liu, Boyu Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Image registration of multimodal remote sensing images plays a vital role in remote sensing image analysis. However, there are significant nonlinear intensity differences between multimodal remote sensing image pairs, making it difficult for most traditional image registration algorithms to meet the registration requirements. In this paper, we propose a novel edge descriptor utilizing edge information, which has not only affine invariance but is also insensitive to nonlinear intensity differences. Moreover, we utilize the proposed descriptor to design a multimodal image registration algorithm. We use several different multimodal image pairs to evaluate the proposed algorithm. The experimental results show that the proposed algorithm holds a stable performance and can still achieve accurate spatial alignment even with the huge nonlinear intensity differences.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622502851
       
  • RNA: A Flexible and Efficient Accelerator Based on Dynamically
           Reconfigurable Computing for Multiple Convolutional Neural Networks

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      Authors: Chen Yang, Jia Hou, Yizhou Wang, Haibo Zhang, Xiaoli Wang, Li Geng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The increasingly complicated and versatile convolutional neural networks (CNNs) models bring challenges to hardware acceleration in terms of performance, energy efficiency and flexibility. This paper proposes a reconfigurable neural accelerator (RNA) for flexible and efficient CNN acceleration. To provide hardware flexibility, RNA employs dynamically reconfigurable computing framework to rapidly configure data path between processing elements (PE) at run-time, as well as an interlaced data access mechanism for multi-bank RAM. To achieve high energy efficiency, three optimization mechanisms, including image row broadcasting dataflow (IRBD), tile-by-tile computing (TTC), and zero detection technology (ZDT), are dedicatedly designed for RNA to exploit data reuse and decrease memory bandwidth requirement, which is the key to improving performance and saving power consumption. To save hardware overhead, an online dynamic adaptive data truncation (DADT) mechanism is designed to compensate accuracy loss of multiplication results so that the computational precision in RNA can be reduced from 16-bit to 8-bit, which contributes to reducing the area of data path. The RNA architecture is implemented on Xilinx XC7Z100 FPGA and works at 250[math]MHz. Experimental results show that the performance of running LeNet, AlexNet and VGG are 500 GOPS, 598 GOPS and 660 GOPS, respectively. Compared to previous FPGA-based designs, RNA achieves [math] performance speedup and [math] improvements on energy efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622502899
       
  • Medical Text Classification Based on an Optimized Machine Learning and
           External Semantic Resource

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      Authors: Karim Gasmi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Automatic classification of texts is a well-known topic in natural language processing (NLP), and it involves categorizing unstructured texts into specific groups. Classification algorithms for a given problem are searched for, as well as the appropriate features to use as input. These models have been used for analysis of data with a large number of sparse dimensions. In medical field, categorization of medical texts is a difficult task because these types of texts contain several terminologies that define medical ideas and words. Medical data also lack proper sentence structure and do not adhere to the standard rules of natural language grammar. The main problem in this classification task is to choose an appropriate representation as input. To solve the representation problem, we propose a new extension model for medical text personification. Our model starts with the preprocessing of medical text. Then, we use external terminology resources to expand the text. After that, we use a combination of different text vector representations. To speed up the process, we try to increase the accuracy while selecting the optimal classification parameters. In this topic, we use an adaptive particle swarm optimization (PSO) algorithm to select the best parameters of a machine learning model. The PubMed, Hallmarks and AIM dataset were used to test our model. Our categorization text model outperforms the competition and provides much higher retrieval accuracy than previous models.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622502917
       
  • Analytical Delay Model and Stability Analysis for MLGNR Interconnects

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      Authors: Himanshu Sharma, Karmjit Singh Sandha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper analyzes the signal delay and relative stability of multilayer graphene nanoribbon (MLGNR) interconnects dependent on temperature at global lengths. A thermally aware driver interconnect load (DIL) system, constituted by equivalent single conductor (ESC) model along with mathematical equations, is proposed to convert multi-conductor transmission circuit into single transmission line of MLGNR. The temperature-dependent analytical delay model of MLGNR is evaluated and the obtained outcomes are compared with the simulated results. The analytical and simulated results are obtained at global interconnect length (2000-[math]m) for 32[math]nm, 22[math]nm and 16[math]nm nodes of technology under 200–500[math]K temperature range of MLGNR. The simulation and analytical results reveal that the outcomes of the two models correspond well. The trend of the models shows the increase in delay with the rising temperature levels (200–500[math]K) for three different nodes of technology. Further, relative stability analysis of MLGNR as interconnect line at three different technological nodes from 500–2000-[math]m lengths is examined.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-05T07:00:00Z
      DOI: 10.1142/S0218126622502607
       
  • Design of a 1.29–1.61[math]GHz LC-VCO with Improved Phase Noise and
           Figure-of-Merit (FoM[math]) for GPS and Satellite Navigation

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      Authors: Keshab Das, Anup Dandapat, Sanjay Kumar Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper demonstrates a low-phase noise and high FoMT differential CMOS LC-VCO working at 1.29–1.61[math]GHz. An RC filter tail current source is used in this design to reduce the second-harmonic oscillation phase noise. The VCO is implemented in 180[math]nm process technology. The post-layout simulation results indicate that this proposed VCO operates faithfully in the 1.29–1.61[math]GHz band with a frequency tuning range (FTR) of 320[math]MHz. By using inversion mode N-MOSFET varactor, the designed VCO obtains 22.06% FTR. The phase noise of the VCO is [math]130.21[math]dBc/Hz at 1[math]MHz offset frequency. It consumes 4.01[math]mW average power from 1.3[math]V supply. The cell area occupied by the design is [math]. Figure-of-merit considering FTR (FoM[math] is [math]194.14[math]dBc/Hz at 1[math]MHz offset frequency, phase noise and average power consumption. The proposed VCO can be used for low-phase noise GPS and satellite navigation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-05T07:00:00Z
      DOI: 10.1142/S0218126622502747
       
  • Gradient Guided Dual-Branch Network for Image Dehazing

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      Authors: Mingliang Gao, Qingyu Mao, Qilei Li, Xiangyu Guo, Gwanggil Jeon, Lina Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, massive deep learning-based image dehazing methods have sprung up. These methods can effectively remove most of the haze and obtain far better results than the traditional methods. With the removal of the haze, however, edge details of the image are also lost, which is usually more noticeable in the gradient space. This paper proposes a gradient guided dual-branch network (GGDB-Net) for image dehazing. Specifically, we explore the hazy image gradient map to guide our model to focus on the hazy regions and edge restoration. We implement two parallel branches with a comprehensive loss function, which collaborate to dehaze and repair the lost edges in haze images. Moreover, the gradient-guided approach can potentially be applied to existing learning-based image dehazing models to boost their performance. Experimental results indicate that our results have good visual perceptions and are comparable to state-of-the-art methods in quantitative metrics.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-29T07:00:00Z
      DOI: 10.1142/S0218126622502905
       
  • Leaf Disease Classification in Smart Agriculture using Deep Neural Network
           Architecture and IoT

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      Authors: Kadiyala Ramana, Rajanikanth Aluvala, Madapuri Rudra Kumar, G. Nagaraja, Akula Vijaya Krishna, Pidugu Nagendra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The Internet of Things (IoT) is bringing a new dimension to the smart farming market. This helps the user to collect the data from the agricultural fields in real time and move it to remote areas for processing. With the available sensor data and the image taken from the fields, automated disease prediction is possible. Deep neural network is used for classification of disease using the leaf images. Agriculture is the backbone of our country, but our output is poor when compared to the global standards due to lack of using technologies in the fields. In this work, various sensors like humidity sensor, pH level monitoring sensor, Temperature sensor, and Soil moisture sensor are used in the agricultural fields for collecting the real-time data. Multiple Sensors are installed in various locations of farms with one common controller Raspberry PI 3 module (RPI3), which was used to control all these sensors. Camera interfacing with RPI can be observed on leaf disease. Convolutional neural network architecture is used for leaf disease detection and classification. The accuracy of the disease classification system using convolutional neural network is 96% when the system is iterated for 50 epochs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-27T07:00:00Z
      DOI: 10.1142/S0218126622400047
       
  • Graph Convolutional Neural Network Gesture Recognition Based on Pooling
           Algorithm

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      Authors: Hong Chen, Baoqiang Qi, Hongdong zhao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The era of new human–computer interaction has accelerated, and gesture recognition is one of the development trends of human–computer interaction system in the future. The emerging graph neural network can capture the interdependence between instances and infer the complete information of the image based on local features, which is helpful to the recognition of human gestures. Therefore, the combination of graph neural network and convolutional neural network (CNN) is applied to the research of gesture recognition and it has important research significance. This paper uses the Mixup method to perform data enhancement processing on the collected image data set, applies the pyramid pooling method to the EigenPooL model to achieve efficient capture of image features and selects the Sigmoid function and the PReLU function as the activation function of the network model to meet the model’s requirements, such as long time training and strong fitting ability. This paper introduces the structure and algorithm of EigenPooL model in detail. The algorithm uses hypergraph learning method instead of simple graph learning method. On the gesture picture test set, the average accuracy of the algorithm is 86.50%, the recall rate is 94.87% and the average detection time per frame is 421[math]ms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-27T07:00:00Z
      DOI: 10.1142/S0218126622502711
       
  • An Improved TCN Considering Data Augmentation in Enabling Load
           Classification

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      Authors: Ding Han, Hongkun Bai, Yuanyuan Wang, Shiqian Wang, Jie Zhang, Yang Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In modern power system, along with the developments of the data collecting technologies, the intensive and high-dimensional load data collection can be achieved. Therefore, to deeply reveal the patterns and behaviors hidden in the load dataset using load classification is of great significance for improving the service quality and the user experience of the power system. However, inevitable issues, for example the data missing and class imbalance are frequently reported in the present load dataset, which deteriorates the performance of the classification algorithms. Also, due to the special features, for example the time series, periodicity, and fluctuation of the load data, the traditional data classification algorithms also encounter performance defects. Therefore, this paper presents a data augmentation based enhanced temporal convolutional network (TCN) algorithm in enabling load classification. In the data augmentation phase, first an LRTC-TSVD algorithm is presented to implement the missing data completion. Second, a WGAN based class balancing approach is further presented to solve the class imbalance issue. Then, in the enhanced TCN phase, a WeightNorm, exponential linear unit (ELU) activation function, residual connection, and bidirectional feature fusion techniques based improved TCN (ITCN) algorithm is presented to carry out the accurate load data classification. Combining the data augmentation and the enhanced TCN phases, the ITCN algorithm is finally conducted. Based on the benchmark load datasets, the performances of the presented ITCN are evaluated. The experimental results report that the presented data augmentations can improve the quality of the dataset, moreover the classification algorithm is able to achieve the satisfied classification accuracy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S021812662250284X
       
  • An Efficient Corner Detector Using Ratio of Center Distance of Symmetric
           Contour Technique

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      Authors: Shizheng Zhang, Shan Liu, Qian Zheng, Min Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Feature detection is one of the basic research topics in the fields of image processing and corner that has been widely applied on vehicle detection, UAV image matching, camera calibration and so on. Particularly, a fast corner detector is of much benefit to many real-time tasks. A novel discrete curvature estimation method for corner detection based on the ratio of center distances of symmetric contour (RCDSC) is proposed in this paper. Benefiting from calculating the Euclidean distance twice only to estimate the discrete curvature at each point on a contour, RCDSC is much fast compared with other corner detectors. In addition, by choosing a relatively large radius of region of support and employing relative distance instead of absolute distance for constructing corner response function, RCDSC is also much robust to noises and local variations of contour. Extensive experiments exhibit the effectiveness and the efficiency of RCDSC in terms of average repeatability (AR), accuracy (ACU) and localization error (LE).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S0218126622502863
       
  • Event-Triggered Neural Network Control for Uncertain Nonlinear Systems
           Without State Observer

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      Authors: Hui Hu, Yuebiao Wang, Wei Yi, Yang Li, Jiande Yan, Wei Xiao, Junqi Yuan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A robust approximation-based event-triggered control method is presented for single input single output (SISO) nonlinear continuous-time systems with unmeasurable states and external disturbance. In the whole system, just one neural network (NN) is designed to approximate the unknown part in the controller, and output errors are directly used to construct the system controller and event-triggered mechanism to relieve the burden of system communication. The controller with a simple structure is easier to be realized in practical engineering. The system control signals and adaptive parameters are updated only if the event trigger condition is met, and this way further reduces the waste of network resources caused by frequent system sampling. The application of stability theory of Lyapunov proves that the weight estimation of the NN and tracking errors are ultimate and uniform boundedness, and the efficacy of the proposed scheme is verified with numerical results on a robot.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S0218126622502632
       
  • Simulation and Analysis of a Digitally Controlled Differential Delay
           Circuit Under Process, Voltage, Temperature and Noise Due to Injection of
           High Current

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      Authors: Mithilesh Kumar, Alak Majumder, Abir J Mondal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0[math]A) to 10 or 30[math]A or else 50[math]A in 10[math]ns. Simulated in a 0.09-[math]m CMOS process and power supply voltage ([math]) of 1.1[math]V, the proposed circuit in post-layout can operate from 435.5[math]ps to 152.2[math]ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5[math]ps for NN and SS process corner, respectively, following a [math]C change in temperature. But an abrupt high current [math] pumped into the chip causes the voltage ([math]) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp [math] of 0–50[math]A in 10[math]ns for the two vector CBA happens to be around 5.0 and 4.4[math]ps, respectively. The current ramp also generates power supply noise of 0.468[math]V occurring close to the silicon chip. This, in turn, corresponds to a [math] of 0.642[math]V near the die, appearing to be much less than the required [math] of 1.1[math]V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642[math]V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S0218126622502760
       
  • Mobile Robot Path Planning Method Based on Deep Reinforcement Learning
           Algorithm

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      Authors: Haitao Meng, Hengrui Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Path planning is an important part of the research field of mobile robots, and it is the premise for mobile robots to complete complex tasks. This paper proposes a reflective reward design method based on potential energy function, and combines the ideas of multi-agent and multi-task learning to form a new training framework. The reflective reward represents the quality of the agent’s current decision relative to the past historical decision sequence, using the second-order information of the historical reward sequence. The policy or value function update of the master agent is then assisted by the reflective agent. The method proposed in this paper can easily extend the existing deep reinforcement learning algorithm based on value function and policy gradient, and then form a new learning method, so that the agent has the reflective characteristics in human learning after making full use of the reward information. It is good at distinguishing the optimal action in the corresponding state. Experiments in pathfinding scenarios verify the effectiveness of the algorithm in sparse reward scenarios. Compared with other algorithms, the deep reinforcement learning algorithm has higher exploration success rate and stability. Experiments in survival scenarios verify the improvement effect of the reward feature enhancement method based on the auxiliary task learning mechanism on the original algorithm. Simulation experiments confirm the effectiveness of the proposed algorithm for solving the path planning problem of mobile robots in dynamic environments and the superiority of deep reinforcement learning algorithms. The simulation results show that the algorithm can accurately avoid unknown obstacles and reach the target point, and the planned path is the shortest and the energy consumed by the robot is the least. This demonstrates the effectiveness of deep reinforcement learning algorithms for local path planning and real-time decision making.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S0218126622502589
       
  • A High Speed Phase Detection Circuit with No Dead Zone Suitable for
           Minimal Jitter and Low Power Applications

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      Authors: Jyoti Sharma, Gaurav Kumar Sharma, Tarun Varma, Dharmendar Boolchandani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit’s robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of [math][math]dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25[math][math]W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275[math][math]m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S021812662250267X
       
  • Evolution of Labor Relations in the Development of Human Resources Based
           on Improved Genetic Algorithm

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      Authors: Min Qin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper systematically constructs a multi-project and a multi-objective human resource scheduling mathematical model in construction projects and puts forward an improved genetic algorithm to solve it by aiming at the problems existing in the process of human resource scheduling and optimization. Specifically, first, the basic mathematical models of GPRs and resource-constrained construction project human resource scheduling problem (RCWSP/GPRs) are established, and the multi-project equilibrium problem is extended. Then, an improved inter-cluster separation (ICS) algorithm is proposed and used to solve the RCWSP/GPRs problem. Finally, on this basis, the mathematical model of multi-project and multi-objective human resource scheduling problem and the solution method based on multi-objective-integrated circuit are proposed. At the same time, the resource-constrained multi-project and multi-skill human resource scheduling problem and the integer programming mathematical model under the generalized priority relationship are proposed. Also, the simulation results verify the accuracy of the proposed algorithm and model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S0218126622502723
       
  • Monitoring and Locating Oceanic Sailors Through Wireless Sensor Network

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      Authors: Shruti Gupta, Shailendra Narayan Singh, Vineet Kansal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A systematic oceanographic monitoring and management requires an effective marine tracking system. It helps the localization of different marine assets, their border control and in encountering emergency situations. Thus, a reliable marine tracking system is always required to ensure a safe marine environment for shippers, fishers, sailors and other marine assets. Nowadays due to the evolution in wireless sensor network (WSN) technology, their easy and inexpensive deployment can be seen in different fields such as agriculture, medical, industries and IoT. The implementation of WSN in the marine environment comes with various issues due to the complex behavior of the marine environment and thus affects the reliability of the system. In this paper, a WSN-based marine tracking protocol sailing is presented, which identifies the location of marine assets reliably through the genetic firefly (GEFIR) algorithm. The system comprises sensor nodes, sink nodes, server-client terminals and a base station. The protocol uses the application and contact layers to create a group of beacon nodes (boats) based on the geographical location to conserve energy and increase data reliability. GEFIR algorithm is implemented to give a precise and more convenient data to the WSN for the mariners. The results show a better performance for latency calculation through the WSN- and GEFIR-based sailing protocol. The system generates the alert to nodes (sailors) in case they are moving out from a specified region and sends their location for further communication.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-18T07:00:00Z
      DOI: 10.1142/S0218126622502693
       
  • DM-Pages: Improving Energy Efficiency of Disk Storage Systems and Cache
           Performance Using Deduplication-based Mixed Pages

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      Authors: Lei Si, Shujie Pang, Yuhui Deng, Weiheng Zhu, Yi Zhou, Yifeng Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a deduplication-based mixed page strategy, called DM-Pages, to improve the energy efficiency of disk storage systems and the cache performance. DM-Pages strives to improve the cache hit rate, simultaneously reduce the number of power-state transitions of a disk storage system and keep it in a low-power state as long as possible. DM-Pages deploys three innovative techniques. It adjusts the size of huge pages dynamically to maximize the cache hit rate. Meantime, content-aware deduplication is applied to eliminate redundant cache pages, targeting to enhance cache utilization. In addition, DM-Pages incorporates a mixed page mechanism into disk energy management to save energy. Our experimental results show that DM-Pages significantly improves the energy efficiency of disk storage systems and achieves a high cache hit rate. In particular, compared with traditional disk storage systems, DM-Pages conserves 6.59 times energy and improves the cache hit rate up to 3.36 times.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-18T07:00:00Z
      DOI: 10.1142/S0218126622502759
       
  • Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT

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      Authors: AbdolVahab Khalili Sadaghiani, Samad Sheikhaei, Behjat Forouzandeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator’s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-17T07:00:00Z
      DOI: 10.1142/S0218126622200031
       
  • Double Differential Blocks Based Frequency Compensation: A Four-Stage CMOS
           Amplifier

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      Authors: Ali Mohammad Sanaei, Ali Biabanifard, Mohammad Saeed Khadem, Toktam Aghaee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18[math][math]m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-17T07:00:00Z
      DOI: 10.1142/S0218126622502735
       
  • The Effect of Using Multi-Scroll Chaotic Systems on Chaos-Based Random
           Number Generators’ Performance

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      Authors: Serdar Çiçek
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Chaotic and hyper-chaotic systems are used in various engineering applications such as encryption, communication, and artificial intelligence. Also, chaotic systems are widely used in chaos-based random number generator (RNG) designs as chaotic system signals are not periodic and produce different values continuously. Since multi-scroll chaotic systems (MSCSs) produce more than one scroll, the output values can take more different values than chaotic systems. In this study, the effects of different directional values and/or different numbers of scrolls of multi-scroll chaotic systems on chaos-based random number generators’ performance are investigated with NIST 800-22 (National Institute of Standards and Technology) and correlation coefficient tests. As a result of the research, it has been concluded that the use of multi-scroll chaotic systems with different directional values and/or different numbers of scrolls does not always have a direct positive effect on the performance of chaos-based random number generators. Thus, it is necessary to use a special pre-process method that will vary according to the multi-scroll chaotic system to be used for chaos-based RNG designs with good performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502590
       
  • A Novel Design of High-Performance Hybrid Multiplier

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      Authors: Jugal Kishore Bhandari, Yogesh Kumar Verma, Laxman Singh, Santosh Kumar Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502681
       
  • DC Voltage Inversion Estimation Method of MMC Submodule Based on Current
           Information

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      Authors: Yang Zhang, Ran Zhao, Yunmin Xie, Jianbing Liu, Jing Sheng, Huijun Xu, Fanxing Rao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      DC voltage detection of sub-modules is very important for the stability of cascaded multilevel converters. Operation and maintenance personnel need a detection algorithm to supplement the uncertainty and risk caused by the traditional redundancy scheme. This paper presented a DC voltage indirect estimation method based on current transformer. The method uses the AC side current value, as well as the sub-module equivalent circuit model and switching state to estimate the DC voltage of the sub-module of the cascade system. The estimation models are established and can be used to the sub-modules of three topologies, i.e., half-bridge, H bridge topology and clamp double sub-module. Simulation and experimental systems are built to testify the proposed method. The results showed that, when [math] or 12, the indirect detection model based on AC current met the requirements of detection accuracy within 1% under different calculation steps, and the sampling error had little influence on it. The indirect estimation method could reduce the use of DC transformers and improve equipment reliability and maintainability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S021812662250270X
       
  • Emergency Response System Combining the Internal and External Domains
           (ERSCIED)

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      Authors: Wei Liang, Yanyan Huang, Jianyu Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Agent-based modeling is a promising approach for developing simulation tools for natural hazards in different areas, such as during urban search and rescue (USAR) operations. The previous studies aimed to develop a dynamic agent-based simulation model in post-earthquake emergency response operations combining rescuers and victims using geospatial information systems and multi-agent systems (GISs and MASs, respectively). We use multi-agent system engineering (MaSE) to construct this model and cluster points are proposed to assemble rescuers and victims. We also proposed an approach for dynamic task allocation and for establishing collaboration among agents based on contract net protocol (CNP) and the [math]-means clustering method. Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS) and expert evaluation is used to sort the priorities of cluster points. The experimental background is set in the central area of Chengdu, Sichuan Province, China. 200 victims with different demands and 30 rescuers with the same rescue capability are randomly distributed in this area. We use different victim speeds to simulate different degrees of seismic damage. Compared with normal search and rescue, the ERSCIED can make some use of the capabilities of the victims for the improvement of emergency effectiveness when the victims and rescuers have a similar speed (1:1) or the victims are not much slower than the rescuers (1:2). When the victims are much slower than the rescuers (1:10), the rescuers have to wait for a long time at the cluster points and it will lead to a waste of resources. The parameters of rescuers and victims can be changed to meet different emergencies and the ERSCIED can provide effective auxiliary decision-making information for decision-makers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502814
       
  • Approximate Multipliers Design Using Approximate Adders for Image
           Processing Applications

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      Authors: S. P. Joy Vasantha Rani, J. R. Lourdu Jennifer, P. Sudhanya
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Addition and multiplication are some of the most broadly adopted arithmetic operations in a wide range of applications. This paper proposes new structures of approximate multipliers to optimize the area, delay, and power without affecting the accuracy metrics. Multipliers and adders play a significant role in the functioning of any digital circuit or system. The overall performance of a processor highly depends on the speed of adders and the energy consumption. In this paper, two types of compact error-tolerant approximate adders are designed and used along with approximate 4:2 compressors to improvise the efficiency of the approximate multipliers. The proposed approximate multipliers show good results when compared to the existing structures in terms of area, delay, power, and accuracy. The approximate multipliers are applied to image sharpening and image multiplication applications. The error-tolerant adder’s performance is evaluated in the practical domain using the image blending application. Peak signal-to-noise ratio (PSNR) performance and the structural similarity index metric (SSIM) are used to assess the modeled designs. The proposed approximate multipliers and adders exhibit better performance in terms of PSNR and SSIM and are found to be an optimized design to apply effectively in various error-tolerant image processing applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-11T07:00:00Z
      DOI: 10.1142/S0218126622502565
       
  • SDN Framework for Mitigating Time-Based Delay Attack

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      Authors: Sagar V. Ramani, Rutvij H. Jhaveri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to recent cyberattacks on the Cyber-Physical Systems, the traditional security schemes face difficulties in dealing with such attacks as the attackers nowadays have adopted many intelligent mechanisms involving advanced information and communication technologies to launch attacks. This recent type of attack provides a significant impact on the resiliency of the software-defined networks. In this paper, we present a real-time delay attack on fault-resilient software-defined networks. The main objective of the time delay attack is to reduce the resiliency in the SDN-RM by adding a delay in the LLDP packets in the OpenFlow Switch. This addition of delay causes degradation in the network performance resulting in a low success rate in the SDN-RM mechanisms. In this paper, we present a machine learning-based detection system for detecting the attacks. The integration of machine learning techniques with network resilience solutions can effectively address the issue of predicting and classifying the LLDP packets that are delayed at a particular switch. Another issue is the detection of the malicious switch at the controller side which results in the improvement of the resiliency in SDN-RM. We propose a machine learning solution to detect the anomalies that are present in the topology and can be detected at the controller side. We use machine learning models such as k-nearest neighbors, support vector machines (SVM), Random Forest, and decision trees to detect the poisonous switches. The delay-based time attack detection system (DTA-DS) helps the controller to take a reactive decision to improve resilience by detecting poisonous network switches. With the help of the preventive approach, we achieve high-fault resiliency in fault resilient-based software-defined networks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-09T07:00:00Z
      DOI: 10.1142/S0218126622502644
       
  • Vertical Negative Effect Suppression of In-Wheel Electric Vehicle Based on
           Hybrid Variable-Universe Fuzzy Control

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      Authors: Zhengtong Zhu, Xinfeng Ge
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To suppress a negative effect brought by introducing hub motor in vertical vibration of the body and that of a hub motor, a suppressing vertical negative effect algorithm of in-wheel electric vehicle is proposed based on hybrid variable universe fuzzy control (VUFC). Vertical accelerations of the body and that of the hub motor are taken as optimization objects, and to control the main suspension damper and in-wheel damper simultaneously, the semi-actively VUFC algorithm is adopted to improve vertical vibration characteristics effectively. The simulated results show that the peak and root mean square (RMS) of body vertical acceleration (VA) are optimized by 21.0% and 19.6%, respectively, after optimization compared to the original in-wheel electric model, the peak and RMS of hub motor VA are optimized by 30.1% and 32.5%, respectively, and the vertical negative effect is suppressed significantly.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-04T07:00:00Z
      DOI: 10.1142/S0218126622502577
       
  • Temporal Sequence of Data Fluctuation-Based Approach for Tor Program
           Classification

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      Authors: Hao Zhang, Weidong Zhang, Wei Zhao, Xuangou Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the continuous development of encryption technology, the share of encrypted traffic in the network is increasing, which brings great challenges to the traditional methods of rule-based traffic identification. Deep learning is becoming an inspiring methodology to solve the problem. Previous studies have confirmed that time characteristics play an important role in Tor traffic classification. We find that there is a similarity of time characteristics among different programs. This paper proposes an end-to-end classification framework: the temporal sequence of data fluctuation network (TSDFN). It first extracts the temporal sequence of data fluctuation in the original flow and then uses the GRU network to learn the hidden temporal features. Experiments on public data sets validate the effectiveness of our proposal over other methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622400023
       
 
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