A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

  Subjects -> ELECTRONICS (Total: 207 journals)
The end of the list has been reached or no journals were found for your choice.
Similar Journals
Journal Cover
Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [120 journals]
  • Resilience Assessment of Multimodal Urban Transport Networks

    • Free pre-print version: Loading...

      Authors: Yishui Chen, Xiaoya Wang, Xuewang Song, Jianlin Jia, Yanyan Chen, Wen-Long Shang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the development of urbanization and the evolution of urban network systems, multimodal urban transport network (MUTN) systems play a vital role in improving network effects and operational efficiency. However, urban transport networks are easily affected by natural disasters and traffic incidents, which can lead to significant human and economic losses. Accordingly, it is vital to be able to assess the resilience of transport networks in the face of various disruptions. This study, therefore, utilizes complex network theory to analyze the resilience of multimodal urban transport networks, with the resilience accessed based on topological indices. The MUTN in Beijing is selected as a case study for simulation analysis. Based on the road network and subway network, a model MUTN is established, and the Monte Carlo method is used to simulate random attacks. The results show that the MUTN in Beijing has good resilience against disruptions. This study guides the evaluation of the overall resilience of multimodal urban transport networks and will be useful for transportation planners and decision-makers in dealing with emergencies and natural disasters in the future.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-30T07:00:00Z
      DOI: 10.1142/S0218126622503108
       
  • A Graph-Based Clustering Algorithm for the Internet of Vehicles

    • Free pre-print version: Loading...

      Authors: Fan Yang, ShiLong Zhang, Jie Huang, Yang Cao, Xun Zuo, Chuan Yang, Bo Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the large-scale and ultra-dense Internet of Vehicles (IoVs), constructing the simplest backbone network is an urgent problem to be solved. In fact, constructing the simplest backbone network is an NP-hard problem, and at present, there is no effective solution. In this paper, we propose a graph-based clustering algorithm to solve this problem and construct the simplest backbone network in the large-scale and ultra-dense IoV. We establish a backbone network model for the large-scale and ultra-dense IoV and optimize the backbone network by employing a novel local search iterative algorithm. Simulation results show that with the increase in node density, the number of clusters selected by the proposed algorithm tends to be stable, while the number of optimized clusters decreases by 28.87% on an average. Thus, the proposed algorithm can effectively simplify the backbone network.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-30T07:00:00Z
      DOI: 10.1142/S0218126623500111
       
  • Simulation Analysis of Influencing Factors of fsQCA Calibration Membership

    • Free pre-print version: Loading...

      Authors: Haiwen Yang, Haifeng Jiang, Yingya Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Based on the analysis of the reasons, principles and classification of fuzzy set data calibration, we analyze that the fuzzy set data calibration membership is influenced by different data distribution, the crossover anchored points setting and transformation selection. Starting from the common problems existing in the current fuzzy-set qualitative comparative analysis (fsQCA) application research, this paper analyzes the possible reasons for ignoring the data calibration research, divides the relationship between the three dimensions of original data distribution, the crossover anchored points setting and calibration transformation and data calibration, and makes a visual analysis on their influence relationship through simulated data. Data distribution, crossover points anchored setting and transformation selection all have a significant impact on fsQCA calibration membership. The distribution of the original data will be a skew attribute consistent with the calibration membership. The cross combination of the high, medium and low setting of the crossover points and the selection of the calibration transformation will produce a significantly different calibration membership, and the crossover points anchored setting has a more obvious impact on the calibration membership than the selection of the calibration transformation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-29T07:00:00Z
      DOI: 10.1142/S0218126622502930
       
  • A Novel, Efficient, Green and Real-Time Load Balancing Algorithm for 5G
           Network Measurement Report Collecting Clusters

    • Free pre-print version: Loading...

      Authors: Pengfei Zhang, Junhuai Li, Ye Tang, Huaijun Wang, Ting Cao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the wide application of data mining and deep learning in mobile cellular network operation and maintenance, network measurement report (MR) plays an increasingly important role in artificial intelligence for IT operations (AIOps). For the integrity of MR reported by the operation and maintenance (OM) proxy of base station, existing collecting methods are typically based on static distributed clustering. Due to the lack of effective load balancing scheme, nevertheless, these methods typically result in some issues, e.g., low collecting efficiency, poor scalability, and excessive number of servers. Thus, in this work, leveraging the historical law of uploading MR for load forecasting, we propose the weighted least-connection load balancing algorithm (LPWLC) based on load forecasting. First, the historical law of reported MR is utilized to predict the load. Second, using the strategy of static binding and dynamic load adjustment, we bind OM with the assigned server in one cycle, calculate the server load in real-time, and evaluate the server weight by the load of each server. Finally, real-time load adjustment is carried out in line with the number of request connections and the weight of servers. Compared with the existing ones, the proposed algorithm could remove backup servers, thereby effectively reducing the cost and power consumption. Compared with the existing methods, this method has improved the load balancing degree by 28%, and reduced the energy consumption by 104[math]W per hour.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-29T07:00:00Z
      DOI: 10.1142/S0218126622503133
       
  • Improved Read/Write Stability-Based Level Shift 5T Ternary SRAM Cell
           Design using Enhanced Gate Diffusion Input BWGCNTFET

    • Free pre-print version: Loading...

      Authors: Gopavaram Suneel Kumar, Gannera Mamatha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, CNTFET introduced the complexity of SRAM design along with the stability. To overcome these complexities, an enhanced Gate Diffusion Input technique-based Ballistic wrap gate CNTFET (EGDI-BWGCNTFET) technology with ternary static random-access memory (T-SRAM) is proposed in this paper. The aim of the proposed technique is “to give higher stability with less stagnant power consumption, voltage drop and store appropriate read/write value of the SRAM cells”. Here, level shift 5T ternary SRAM cell design using Enhanced Gate Diffusion Input Ballistic wrap gate CNTFET (level shift EGDI-BWGCNTFET 5T-ternary SRAM) is proposed for improving read and write stability. It uses two cross-coupled EGDI-BWGCNTFET ternary inverter, which is used for data storage elements along with one access transistor which is connected with bit line (BL) and word line (WL) with minimum supply voltage resulting in leakage current that is decreased. By this, proposed method reduces delay in the write cycles and read cycles. It provides good read static noise margin (RSNM) and controls precharge voltage. The proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM is done in HSPICE platform. The performance of the proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM design is measured in terms of lower Read Delay 23.25%, 22.94%, 18.38%, 23.97%, lower Write Delay 33.92%, 28.94%, 42.83%, 31.98% compared with the existing methods, such as 8T CNTFET-Ternary SRAM, 24T CNTFET-2Ternary SRAM, 18T CNTFET-Ternary SRAM and 17T CNTFET-Ternary SRAM, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-29T07:00:00Z
      DOI: 10.1142/S0218126623500032
       
  • MSK-UNET: A Modified U-Net Architecture Based on Selective Kernel with
           Multi-Scale Input for Pavement Crack Detection

    • Free pre-print version: Loading...

      Authors: Xiaoliang Jiang, Jinyun Jiang, Jianping Yu, Jun Wang, Ban Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Pavement crack condition is a vitally important indicator for road maintenance and driving safety. However, due to the interference of complex environment, such as illumination, shadow and noise, the automatic crack detection solution cannot meet the requirements of accuracy and efficiency. In this paper, we present an extended version of U-Net framework, named MSK-UNet, for pavement crack to solve these challenging problems. Specifically, first, the U-shaped network structure is chosen as the framework to extract more hierarchical representation. Second, we introduce selective kernel (SK) units to replace U-Net’s standard convolution blocks for obtaining the receptive fields with distinct scales. Third, multi-scale input layer establishes an image pyramid to retain more image context information at the encoder stage. Finally, a hybrid loss function including generalized Dice loss with Focal loss is employed. In addition, a regularization term is defined to reduce the impact of imbalance between positive and negative samples. To evaluate the performance of our algorithm, some tests were conducted on DeepCrack dataset, AsphaltCrack300 dataset and Crack500 dataset. Experimental results show that our approach can detect various crack types with diverse conditions, obtains a better performance in precision, recall and [math]-score, with 97.43%, 96.95% and 97.01% precision values, 82.51%, 93.33% and 87.58% recall values and 95.33%, 99.24% and 98.55% [math]-score values, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-28T07:00:00Z
      DOI: 10.1142/S0218126623500068
       
  • Design and Realization of a Broadband Multi-Beam [math] Array Antenna
           Based on [math] Butler Matrix for 2.45 GHz RFID Reader Applications

    • Free pre-print version: Loading...

      Authors: Abdelaaziz El Ansari, Sudipta Das, Ikram Tabakh, B. T. P. Madhav, Abdelhak Bendali, Najiba El Amrani El Idrissi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents design and analysis of a beam switchable [math] array patch antenna fed by a [math] Butler matrix based hybrid coupler for 2.45[math]GHz radio frequency identification (RFID) reader applications in the ISM band. The proposed beam switchable array antenna arrangement consists of two identical patch elements, a pleated quarter-wavelength impedance transformer (PQWIT), and a hybrid coupler. The concept of PQWIT has been utilized to reduce the overall implementation area of the patch elements. The overall area of the patch element is miniaturized by 50% due to the implementation of PQWIT. This miniaturized antenna is used as a radiating element for designing a beam switchable [math] array antenna fed by a hybrid coupler. The proposed antenna prototype has been fabricated on a 1.56[math]mm thick Rogers RT/duroid 5880 substrate with a physical area of [math][math]mm2. The simulation and measured results exhibit good agreements. The designed antenna offers a broad bandwidth of 844[math]MHz (1.956–2.80[math]GHz), peak gain of 8.86 dB, peak radiation efficiency of 99.52% and has two switchable beams in the directions [math] and [math]. The suggested switched beam array antenna is suitable for RFID reader applications at 2.45[math]GHz for tracking of moving objects.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-27T07:00:00Z
      DOI: 10.1142/S0218126622503054
       
  • A Transient-Enhanced Low-Dropout Regulator in 0.18-[math]m CMOS Technology
           

    • Free pre-print version: Loading...

      Authors: Baolin Wei, Yuanyuan Li, Weilin Xu, Xueming Wei, Jihai Duan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a low-dropout voltage regulator (LDO) with a slew-rate enhancement circuit. The proposed slew-rate enhancement circuit was utilized to generate a large current for driving a large pass transistor and quicker charge and discharge of the parasitic capacitance. Hence, the transient response of the LDO was significantly enhanced owing to the improvement in the slew rate at the gate of the pass transistor. The proposed LDO regulator was designed and fabricated using the SMIC 0.18-[math]m standard CMOS process, and its core area occupation was only 0.012[math]mm2. The measurement results show that the output overshoot/undershoot voltages and settling times of the proposed LDO with SRE are 190[math]mV/267[math]ns and 174[math]mV/233[math]ns when the load current changes between 100[math][math]A and 100[math]mA. It has a moderate figure-of-merit (FOM) of 0.267[math]ns.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-27T07:00:00Z
      DOI: 10.1142/S021812662250311X
       
  • Reconfigurable Turbo and Low-Density Parity-Check (LDPC) Decoding
           Accelerators for Powerline Communications

    • Free pre-print version: Loading...

      Authors: Cheng-Hung Lin, Jin-Kun Shen, Cheng-Kai Lu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This study presents two reconfigurable turbo/low-density parity-check (LDPC) decoding kernels for the two powerline communication standards, HomePlug and G.hn. Two architectures are presented, both of which use the radix-4 double-binary enhanced max-log maximum a posteriori probability algorithm with next-iteration initialization in turbo decoding. In LDPC decoding, the two architectures employ the normalized min-sum and the layered radix-4 forward and backward algorithms. The two algorithms cause differences in the architecture and throughput rate. Consequently, the proposed decoding kernels have different architectures when combined with the turbo decoding algorithm, and the two proposed decoding kernels each have their own advantages and disadvantages in terms of throughput and area cost. To make the features of two kernels more evident, we have implemented the proposed decoding kernels that lead to significant throughput gains and better area efficiency compared with other studies. The proposed decoding kernels can be operated in all modes specified in the HomePlug and G.hn standards using a 40-nm complementary metal-oxide-semiconductor (CMOS) process. Moreover, the proposed decoding kernels provide different solutions to achieve the expected throughput rates of the G.hn and HomePlug standards.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503091
       
  • A Novel Morphological Feature Extraction Approach for ECG Signal Analysis
           Based on Generalized Synchrosqueezing Transform, Correntropy Function and
           Adaptive Heuristic Framework in FPGA

    • Free pre-print version: Loading...

      Authors: Miloni M. Ganatra, Chandresh H. Vithalani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, a computer-aided diagnosis system is required to monitor the cardiac patients continuously and detecting the heart diseases automatically. In this paper, a new field programmable gate array-based morphological feature extraction approach is proposed for electrocardiogram signal analysis. The proposed architecture is mainly based on the Generalized Synchrosqueezing transform but a detrended fluctuation analyzer is applied in the reconstruction stage for capturing the maximum information of QRS complexes and P-waves by eliminating a set of noisy intrinsic modes. Then, a correntropy envelope is determined from the QRS enhanced signal for localizing the QRS region accurately. Also, an adaptive heuristic framework is introduced to detect the true P-wave from the P-wave enhanced reconstructed signal by analyzing both the positive and negative amplitudes. In addition, a root mean square Error estimation-based adaptive thresholding approach is used to estimate the T-wave after removing the P-QRS complexes. The proposed architecture has been implemented on field programmable gate array using the Xilinx Vertex 7 platform. The performance of the proposed architecture is validated by performing a comparative study between the resultant performances and those attained with state-of-the-art feature descriptors, in terms of Sensitivity, accuracy, positive prediction, error rate and field programmable gate array resources estimation. The proposed sensitivity, accuracy and positive prediction are 99.84%, 99.85% and 99.86% for QRS detection approach. The proposed sensitivity, accuracy and positive prediction are 99.45%, 99.23% and 99.78% for P-wave detection approach. The proposed sensitivity, accuracy and positive prediction are 99.58%, 99.65% and 100% for T-wave detection approach. The simulation results show that the proposed architecture overtakes existing designs and minimizes hardware complexity, which proves the suitability of this approach on real-time applications of electrocardiogram signals.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503121
       
  • Efficient Federated Learning Using Layer-Wise Regulation and Momentum
           Aggregation

    • Free pre-print version: Loading...

      Authors: Fan Zhang, Zekuan Fang, Yiming Li, Mingsong Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Federated Learning (FL) enables multiple parties to train a global model collaboratively without sharing local data. However, a key challenge of FL is data distribution heterogeneity across participants, which causes model drift in local training and significantly reduces the model performance. To address this challenge, we analyze the inconsistency differences between different model layers of local models and further propose Layer-wise Distance Regularization (LWDR) and Layer-wise Momentum Aggregation (LWMA). The proposed LWDR and LWMA optimize the local training and model aggregation processes, respectively, to improve the convergence performance of FL on data in the nonindependent and identically distributed (Non-IID) scenarios. Our experiments on well-known datasets show that our algorithm significantly outperforms the state-of-the-art FL algorithms in convergence speed, accuracy, and stability in different Non-IID scenarios.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503145
       
  • An Optimal Dead Time Compensator Design for Nonsquare Process with
           Disturbance Rejection

    • Free pre-print version: Loading...

      Authors: Neelbrata Roy, Anindita Sengupta, Ashoke Sutradhar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work aims to establish an optimal design of the Smith dead-time compensator for a nonsquare multivariable system with a transfer function matrix containing first-order dead time elements. The scheme has a set point tracking controller along with disturbance rejection using an optimal estimator. An inverse signal from the estimator eliminates the disturbance. The proposed method significantly improves the disturbance rejection and performance index compared to the other established methods. The common evolutionary algorithms such as the grey wolf optimization technique and teaching learning based algorithm have been used to tune the controllers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-25T07:00:00Z
      DOI: 10.1142/S0218126622503169
       
  • Single-CFOA-Single-External-Capacitor-Based Partially-Active-R SRCOs: The
           Fourth Missing Circuit

    • Free pre-print version: Loading...

      Authors: Dharmesh Kumar Srivastava, Raj Senani, Data Ram Bhaskar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new single-resistance-controlled-oscillator (SRCO) is presented which employs a single current feedback-operational amplifier (CFOA) along with four resistors but needs only a single external capacitor due to the incorporation of the CFOA-pole in the design. It provides independent control of the condition of oscillation and the frequency of oscillation through two separate resistors. To the best knowledge of the authors, this single-CFOA-based partially active-[math] SRCO has not been reported explicitly in the technical literature earlier and hence is the fourth missing circuit of this class of SRCOs. Experimental results confirming the validity of the new proposition have been included and the comparative features of all the four circuits have been highlighted.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622200043
       
  • Designing a Compact Microstrip Dual-Band Filter with Two T-Shaped
           Resonators and Suitable Frequency Selectivity

    • Free pre-print version: Loading...

      Authors: F. Shiri, M. Dousti, F. Shama
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A miniaturized microstrip dual-band bandpass filter (DBPF) with two T-shaped resonators is proposed. The two T-shaped resonators lead to multiple transmission zeros in the stopband and higher filter selectivity. The filter is analyzed using LC and even/odd mode analyses to determine the transmission zeros. The LC equivalent circuit and transfer function are presented. The proposed filter is symmetrical, so the electrical length and impedance values are used for odd/even mode analysis. The designed DBPF is centered at 1.9/5.54[math]GHz and is suitable for WLAN applications. The insertion loss of the filter is less than 0.5[math]dB and its return loss is more than [math][math]dB in each band. Five transmission zeros are created with an attenuation greater than [math][math]dB. The total area of the proposed filter is [math][math]mm2. To validate the proper performance of the proposed filter, it is fabricated and measured.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502474
       
  • Simulation and Structure Optimization of Grounding Circuit Model for Power
           Transmission Line Tower

    • Free pre-print version: Loading...

      Authors: Yuanchao Hu, Yan Cheng, Zhipeng Jiang, Yunzhu An, Seunggil Jeon, Wen Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The lightning current dispersion process through the steel bar inside the concrete pile foundation of the transmission line tower is impeded by the high concrete resistivity. In order to improve the current dispersion performance of the pile foundation, this paper proposes a method to place flexible graphite grounding electrode along the shaft wall of the tower foundation and verified its feasibility. Both single-pile and four-pile foundations are applied to build vertical grounding models of transmission line tower with three different grounding structures, respectively, including flexible graphite grounding line, flexible graphite grounding fabric and combined graphite electrode. The effect of three grounding structures on the current dispersion and resistance reduction is studied by finite-element method. Simulation results indicate that by applying the above three grounding structures on the vertical pile foundation can significantly improve the current density distribution of the excavated pile foundation and reduce the grounding resistance. When the grounding resistance is [math], the resistance reduction efficiencies of the above three methods can reach 48.56%, 53.86% and 54.53%, respectively. Considering the limited construction area, this paper compares the foundation that is placed combined graphite grounding electrode with square-ray grounding grid, and it can be seen that by placing vertical grounding electrode can save the land area of 295.99[math]m2. This paper can provide reference for the design of excavation pile foundation grounding structure under limited construction area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502784
       
  • A New Secure Crowdfunding Transaction Scheme Based on Blockchain

    • Free pre-print version: Loading...

      Authors: Guangshun Li, Guopeng Liang, Junhua Wu, Zhenyu Jin, Wenzhen Feng, Kan Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Online crowdfunding, an innovative model based on “[math]”, is a hot spot for financing via Internet. Crowdfunding based on blockchain is an emerging economic phenomenon and becomes one of the most advanced risk financing strategies. However, crowdfunding transactions face security threats due to identity leaks, quantum attacks and the untraceable nature of blind signatures, which facilitate criminal activity. Different from the previous works, which ignored the importance of traceability, in this paper, we establish a blockchain-empowered secure crowdfunding architecture and propose an anti-quantum partially blind signature algorithm based on the verifiable identity of both sides. Specially, for one thing, the private key decided by user identity is generated by lattice-based sample matrix, and the privacy of user identity can be ensured and traced by the rejection sampling theorem. For another thing, we design an improved krill herd algorithm (IKHA) to increase the credit factor of fundraisers for dealing with project investment issues. The simulation evaluates the correctness and effectiveness of our theoretical analyses. Compared with the current popular schemes, the proposed IKH algorithm has a higher convergence speed and can optimize investment efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502826
       
  • Design and Implementation of Low Power, High-Speed Configurable
           Approximation 8-Bit Booth Multiplier

    • Free pre-print version: Loading...

      Authors: Sampath Kumar, Minakshi Poonia, Rahul Kumar, Gaurav Sharma, Somesh Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502966
       
  • Droplet Routing Based on Double Deep Q-Network Algorithm for Digital
           Microfluidic Biochips

    • Free pre-print version: Loading...

      Authors: Kolluri Rajesh, Sumanta Pyne
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Digital microfluidic biochips (DMFBs) are emerging as an alternative to the cumbersome traditional laboratories for biochemical analysis. DMFBs come under micro-electro-mechanical systems and are a class of lab-on-a-chip devices. DMFBs provide automation, miniaturization and software programmability. The droplet routing algorithm determines concurrent routes for a set of droplets from their source cells to individual target cells on a DMFB. In this paper, a double deep Q-network (DDQN)-based droplet routing algorithm has been proposed. DDQN is a temporal difference-based deep reinforcement algorithm that combines Double Q-learning with a deep neural network algorithm. In the proposed work, routes for droplets are determined by DDQN, and later collisions are resolved using stalling and/or detouring. The latest arrival time of droplets arriving last at its target and cell utilization is taken as objectives for routing algorithm performance evaluation. The proposed method is evaluated on two standard benchmark suites. Simulation results show that the proposed DDQN-based droplet routing algorithm produces competitive results compared to state-of-the-art algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622502991
       
  • A Fully Integrated Mixed-Mode LDO Regulator with Fast Transient Response
           Performance

    • Free pre-print version: Loading...

      Authors: Khaldoon Abugharbieh, Basel Yaseen, Abdullah Deeb, Hani Ahmad, Ayman Jeit
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2[math]V and produces an output voltage of 1.2[math]V. In simulations, the LDO regulator achieves 143-[math] A quiescent current, [math]56-dB PSRR @ 1-kHz noise frequency and an output voltage drop of around 200[math]mV for a load current step of 100[math]mA. The LDO can provide a maximum load current of 200[math]mA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S0218126622503005
       
  • Time Domain Optimize in an Urban Rail Transit Line Based on Passenger Flow
           Spatial and Temporal Distribution

    • Free pre-print version: Loading...

      Authors: Jinjin Tang, Chao Li, Yuran Liu, Siyang Wu, Linghao Luo, Wen-Long Shang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Focusing on the time domain optimization problem of an urban rail transit line, this paper constructs a passenger travel network with OD passenger flow data as input, by using a multi-path search algorithm based on dynamic cost to deduce the passenger space-time path. The passenger travel path is restored and the spatial and temporal distribution of passenger flow is calculated. Based on this, considering the influence of passenger flow spatial and temporal distribution on the time domain division, the orderly clustering method is used to optimize the time domain. Factoring in the influence of line capacity constraint, train running sequentially on time domain division and bidirectional time domain, a time domain optimization framework for an urban rail line is proposed in this study to integrate the time domain optimization results and improve the adaptability of optimization method. A practical line is taken as an example to verify the effectiveness of the proposed framework. Compared with the traditional time domain division method, the time domain division result accuracy is significantly improved and lays a foundation for the formulation of train service scheme which accurately matches transport capacity to demand.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-23T07:00:00Z
      DOI: 10.1142/S021812662250308X
       
  • Image Super-Resolution Method Based on Dual Learning

    • Free pre-print version: Loading...

      Authors: Zhao Qiu, Chunyu Zhuang, Lihao Liu, Jiale Lin, Sheng Yuan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Existing super-resolution methods convert high-resolution images into low-resolution images, and use the synthesized images as input to train the model. However, it is difficult for synthetic low-resolution images to reflect the characteristics of real low-resolution images, resulting in poor model performance in practical applications. To address this problem, we propose a recurrent super-resolution framework, which consists of a degradation model and a reconstruction model. The degradation model degenerates the real high-resolution image into a more real low-resolution image, which is used as the input of the super-resolution reconstruction network, and then uses the reconstruction model to reconstruct the low-resolution image, and calculates the error with the original image. The generated high-resolution image is input into the degradation model again for degradation processing, forming a symmetrical and cyclic network structure, so that the super-resolution model has a better effect when reconstructing the real low-scoring image. In addition, the spatial attention mechanism is introduced into the generator network, which expands the receptive field of the convolution kernel, better extracts long-distance image features and improves the texture details of super-resolution images, which is consistent with the global.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-22T07:00:00Z
      DOI: 10.1142/S0218126622502838
       
  • A Predictive Noise Shaping SAR ADC with Redundancy

    • Free pre-print version: Loading...

      Authors: Shuang Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a predictive noise shaping (NS) Successive Approximation (SAR) Analog-to-Digital Converter (ADC), which improves its conversion speed by 25%, compared to its counterpart with 0.3% less redundancy. It begins by investigating the Signal to Noise and Distortion Ratio (SNDR) degradation when using a lower Oversampling Ratio (OSR, e.g., 8) than required in the prior state-of-the-art works, when predicting the first 4 MSBs with a second-order predictor. Later, it compares the SNDR for the same predictor with and without the bit weight redundancy in the capacitor array. In addition, designs with various levels of redundancies and OSRs are compared on their SNDRs. Both MATLAB and Cadence simulation results verified that by introducing 0.3% more redundant bit weight, either 8[math]dB more SNDR at the same bandwidth, or 25% speed improvement can be obtained while maintaining its SNDR.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-22T07:00:00Z
      DOI: 10.1142/S0218126622503078
       
  • A High-Frequency Multi-Mode Universal Filter for GHz Applications in CNFET
           Technology

    • Free pre-print version: Loading...

      Authors: Mostafa Parvizi, Rana Haratian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new circuit structure of a multi-mode active filter, using only 16 transistors and 2 grounded capacitors in carbon nanotube field-effect transistor (CNFET) technology which is biased at [math][math]V supply. The proposed multi-input, single-output (MISO) filter has the capability of working as low-pass, band-pass, high-pass, band-stop and all-pass filters in all the operating modes (voltage, current, transconductance and transresistance). In addition, the quality factor ([math]) parameter can be tuned electronically independent of the center frequency ([math]). The HSPICE simulation results show that the proposed filter consumes only 971[math][math]W at 1[math]GHz center frequency, assuming [math][math]pF and the nanotube pitch parameter of ([math] nm) and the chiral vector of (22,0), while the number of nanotubes is considered as [math] for all the transistors. Moreover, the main circuit performances such as the center frequency and the power consumption of the circuit vary by 5.4% and 11.6%, respectively, for the standard temperature variation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622502887
       
  • An Adaptive Regulatory Approach to Improve the Power Quality in Solar
           PV-Integrated Low-Voltage Utility Grid

    • Free pre-print version: Loading...

      Authors: Ch. Phani Kumar, E. B. Elanchezhian, S. Pragaspathy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Solar PV-connected distributed utility grid often faces several issues due to variable penetration of the generated power. It creates frequent disturbance in load side and increases the voltage instability. It is a great challenge to maintain the stability at distributed low-voltage grid and improve the quality of power. In order to overcome this problem, this paper proposes an adaptive voltage and current regulatory approach to improve the power quality in a solar PV-integrated low-voltage utility grid. It supplies auto-adjustable reactive power during the small and large voltage deviations in the grid. The proposed approach assures that the load bus voltage is maintained at 1 p.u. under variable environmental conditions. In addition, the power quality gets improved by injecting the power with improved quality. Three cases of standalone mode, grid-connected modes with and without STATCOM have been investigated and reported in this paper. To validate the proposed adaptive voltage and current regulatory approach, the dynamic results of regulated grid voltage under poor environmental conditions are analyzed and the measured results are presented in this paper. Furthermore, the obtained results are evaluated with the existing approaches such as BAT, firefly and elephant herding optimization (EHO) algorithms and reported in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622503017
       
  • Probabilistic Buckshot-Driven Cluster Head Identification and Accumulative
           Data Encryption in WSN

    • Free pre-print version: Loading...

      Authors: Parvathaneni Naga Srinivasu, Ranjit Panigrahi, Ashish Singh, Akash Kumar Bhoi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Several nonterminal nodes in the ad-hoc sensor network architecture are involved in effectively communicating data. There are not enough nodes other than the terminals to process sensor data and send it between nodes. Because of this, the exchange of sensor data relies on devices capable of predicting events and responding quickly. Identifying the cluster head is essential to the network’s long-term viability and operational efficiency. This paper proposes a robust probabilistic buckshot approach to identify the appropriate nodes, and the smooth handover mechanism in the corresponding cycles is mechanized. The proposed model also employs a heuristic algorithm named HARIS to identify the best cluster head by analyzing the residual energy associated with each sensor node over multiple iterations. The data exchanged among the nodes is encrypted using a lightweight accumulative data encryption model to ensure the confidentiality of the data. The proposed model is evaluated using various statistical analysis metrics like node availability, computational delay, throughput, and network lifetime. The proposed model outperforms the existing energy-sensitive sensor network models by 20–23%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622503030
       
  • Energy Efficiency Optimization with SINR Constraints in Downlink MIMO-NOMA
           Systems

    • Free pre-print version: Loading...

      Authors: Fuyuan Xu, Hailin Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In downlink multiple-input, multiple-output, (MIMO) and non-orthogonal multiple access (NOMA) systems, the inter-cluster interference can be cancelled by optimizing pre-coding and detection matrices. Thus, the MIMO-NOMA channel is decomposed into multiple single-input, single-output and (SISO)-MOMA channels. Then, we formulate an energy efficiency (EE) optimization problem subject to the signal-to-interference-plus-noise ratio (SINR) constraints which is non-convex. To solve the problem, we propose the algorithm based on one-dimensional linear search and first-order Taylor expansion. Moreover, as in conventional communication systems, EE and spectrum efficiency (SE) cannot always be improved simultaneously. Thus, the trade-off between EE and SE is investigated based on the formulated problem. Numerical analyses and simulation results verify the proposed algorithm. In addition, the performance in terms of EE and the EE-SE trade-off can be improved by optimizing the user pairing method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-21T07:00:00Z
      DOI: 10.1142/S0218126622503157
       
  • A Deep Convolutional Neural Network Stacked Ensemble for Malware Threat
           Classification in Internet of Things

    • Free pre-print version: Loading...

      Authors: Hamad Naeem, Xiaochun Cheng, Farhan Ullah, Sohail Jabbar, Shi Dong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Malicious attacks to software applications are on the rise as more people use Internet of things (IoT) devices and high-speed internet. When a software system crash happens caused by malicious action, a malware imaging method can examine the application. In this study, we present a novel malware classification method that captures suspected operations in a variety of discrete size image features, allowing us to identify such IoT device malware families. To decrease deep neural network training time, essential local and global image features are selected using a combined local and global feature descriptor (LBP-GLCM). The classification performance of the proposed deep learning model is improved by combining the predictions of weak learners (CNNs) and using them as knowledge input to a multi-layer perceptron meta learner. This is a neural network ensemble with stacked generalization that is used to improve network generalization ability. The public dataset used for performance evaluation contains 5472 samples from 11 different malware families. In order to compare the proposed methodology to current malware detection systems, we developed a baseline experiment. The proposed approach improved malware classification results to 98.5% accuracy and 98.4% accuracy when using [math] and [math] image sizes, respectively. Overall, the results showed that the stacked generalization ensemble with multi-step extracting features is a more effective method for classification performance and response time.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-18T07:00:00Z
      DOI: 10.1142/S0218126622503029
       
  • Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma
           ADC

    • Free pre-print version: Loading...

      Authors: Jinhui Tan, Jishun Kuang, Xing Hu, Lin Xiao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 [math]m BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of [math] for a load capacitance of 2 pF. Output voltage swings are [math] V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162[math][math]m[math][math][math]200.82[math][math]m. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-18T07:00:00Z
      DOI: 10.1142/S0218126622503066
       
  • Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using
           Modified 32-Bit Square Root Carry Select Adder

    • Free pre-print version: Loading...

      Authors: Raju Ganna, Shanky Saxena, Govind Singh Patel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer’s performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636[math][math]m2, the power is achieved as 50.125[math][math]W and delay is attained to be 1.280[math]ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-15T07:00:00Z
      DOI: 10.1142/S0218126622502929
       
  • Deep Learning-Based Multi-classification for Malware Detection in IoT

    • Free pre-print version: Loading...

      Authors: Zhiqiang Wang, Qian Liu, Zhuoyue Wang, Yaping Chi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the open-source and versatility of the Android operating system, Android malware has exploded, and the malware detection of Android IoT devices has become a research hotspot in recent years. Static analysis technology cannot effectively analyze obfuscated malware. Without decomposing, the existing detection methods are mainly based on grayscale images and single files without analyzing and verifying their anti-obfuscation performance. In addition, the current detection of Android malware using deep learning is concentrated in the field of binary classification. This paper proposes a multi-classification method of the Android malware family based on multi-class feature files and RGB images to solve these problems. The method proposed in this paper does not need to decompile the Android APK installation package. However, it extracts the DEX file and XML file in batch from the APK installation package. Then, it converts the file into an RGB image using the conversion algorithm that converts Android software into images. Finally, the deep neural network automatically obtains the RGB image texture features to realize the multiple classifications of the Android malware family. Experimental data show that the proposed method has high detection performance, and the accuracy of multiple classifications of the Android malware family is as high as 99.84%. In addition, the method based on RGB image is better than the grayscale image in detection accuracy, and the effect of RGB image combined with DEX and XML is better than that of separate DEX file image and separate XML file image. Therefore, the method proposed in this paper can effectively detect the obfuscated Android malware, and the detection accuracy of 99.23% can be achieved for the obfuscated sample data. Furthermore, this method has good anti-obfuscation ability. The proposed method is compared with those based on Multi-Layer Perceptron, Long Short-Term Memory, bidirectional Long Short-Term Memory and Deep Belief Network. The experimental results show the proposed method’s effectiveness and high generalization performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-15T07:00:00Z
      DOI: 10.1142/S0218126622502978
       
  • Efficient Uncertain Sequence Pattern Mining Based on Hadoop Platform

    • Free pre-print version: Loading...

      Authors: Jimmy Ming-Tai Wu, Shuo Liu, Jerry Chun-Wei Lin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the Internet of Things (IoT) era, information is collected by sensor devices, resulting in data loss or uncertain data and other consequences. We need to represent the uncertain data collected using probabilities to extract the useful information for production and application from a huge indeterminate data warehouse. The data in the database has a particular order in time or space, so the High-Utility Probability Sequential Pattern Mining (HUPSPM) has become a new investigation and analysis topic in data processing. After the progress of timestamp, many efficient algorithms for sequential mining have been developed. However, these algorithms have a limitation: they can only be executed in a stand-alone environment and are only suitable for small datasets. Therefore, introducing an advanced graph framework for processing large datasets addresses the shortcomings of the existing methods. The proposed algorithm can avoid repeated database searching, splitting the database, and improve the parallel computing capability. The initial database is pruned according to the existing pruning strategy to effectively reduce the number of candidate sets effectively. Experiments show that the algorithm presented in this paper has excellent advantages in mining high-utility probability sequences in large datasets.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-12T07:00:00Z
      DOI: 10.1142/S0218126622502619
       
  • Dual Channel Multiplier for First-Order Piecewise Approximation for GPU

    • Free pre-print version: Loading...

      Authors: Dina M. Ellaithy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper demonstrates an energy-efficient implementation of piecewise polynomial approximation to evaluate the complex functions of graphical processing units (GPUs). A novel approach is employed to implement the first-order piecewise approximation serially which leads to high savings in power and area. Dual channel multiplier (DCM) scheme is proposed to simplify the hardware architecture of the piecewise polynomial approximation. The proposed methodology is implemented with 90[math]nm CMOS technology and it can perform different complex functions using a simple multiplier hardware structure. DCM achieves improvement in energy saving by up to 81% at a penalty cost of 10 clock cycles. Simulation results confirm that this work attains at least 83%, and 55% saving in power and area as compared to the traditional techniques, respectively. The proposed methodology can implement any degree of the piecewise polynomial approximation utilizing the DCM.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-12T07:00:00Z
      DOI: 10.1142/S021812662250298X
       
  • Controlling a 4D Chaotic Oscillator with a Quadratic Memductance and its
           Implementation

    • Free pre-print version: Loading...

      Authors: Abdullah Gokyildirim, Abdullah Yesil, Yunus Babacan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Following the experimental realization of memristors, researchers have focused on memristor-based circuits. Chaotic circuits can be implemented easily using a memristor due to its nonvolatile and nonlinear behavior. This study presents a memristor-based four-dimensional (4D) chaotic oscillator with a line equilibria. A memristor having quadratic memductance was utilized to implement the proposed chaotic oscillator. The 4D chaotic oscillator with quartic nonlinearity was designed as a result of the quadratic memductance. In terms of communication security, random number generation and image and audio encryption, systems with quartic nonlinearity or that are higher-dimensional are better than systems that are lower-dimensional or possess quadratic/cubic nonlinearity. The performance of the proposed chaotic circuit was investigated according to properties such as phase portraits, Jacobian matrices, equilibrium points, Lyapunov exponents and bifurcation analyses. Furthermore, the proposed system is multistable and its solutions tend to appear as twin attractors when initial conditions approach their equilibria. The Lyapunov-based nonlinear controller was constructed for controlling the proposed system having a line equilibria. The effect of the initial conditions on the controlling indicators was also studied. In conclusion, by using discrete circuit elements, the proposed circuit was constructed, and its experimental results demonstrated a good agreement with the simulation results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-09T07:00:00Z
      DOI: 10.1142/S0218126622502875
       
  • Current-Mode PID Controller Using Second-Generation Voltage Conveyor
           (VCII)

    • Free pre-print version: Loading...

      Authors: Emre Özer, Fırat Kaçar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a current-mode (CM) proportional integral derivative (PID) controller based on second-generation voltage conveyor (VCII) is presented. The proposed circuit consists of two-plus type VCIIs, two resistors, and two capacitors. There is no need of critical matching condition. Considering the parasitic impedance, the operating frequency ranges of the proposed PID network are examined. The magnitude and phase responses, Monte Carlo, temperature and input-output noise analyses have been simulated. The simulation results are obtained with the LTspice program using AD844 SPICE macro-model under [math]9[math]V DC supply voltages. The total power consumption of the proposed CM PID controller is 235[math]mW.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-08T07:00:00Z
      DOI: 10.1142/S0218126622502954
       
  • Response of Commercial P-Channel Power VDMOS Transistors to Ionizing
           Irradiation and Bias Temperature Stress

    • Free pre-print version: Loading...

      Authors: Sandra Veljković, Nikola Mitrović, Vojkan Davidović, Snežana Golubović, Snežana Djorić-Veljković, Albena Paskaleva, Dencho Spassov, Srboljub Stanković, Marko Andjelković, Zoran Prijić, Ivica Manić, Aneta Prijić, Goran Ristić, Danijel Danković
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ([math]) and interface traps ([math]) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of [math] neutralization and [math] passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622400035
       
  • Multimodal Remote Sensing Image Registration Algorithm Based on a New Edge
           Descriptor

    • Free pre-print version: Loading...

      Authors: Zhili Song, Chaopeng Shi, Fanmei Liu, Boyu Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Image registration of multimodal remote sensing images plays a vital role in remote sensing image analysis. However, there are significant nonlinear intensity differences between multimodal remote sensing image pairs, making it difficult for most traditional image registration algorithms to meet the registration requirements. In this paper, we propose a novel edge descriptor utilizing edge information, which has not only affine invariance but is also insensitive to nonlinear intensity differences. Moreover, we utilize the proposed descriptor to design a multimodal image registration algorithm. We use several different multimodal image pairs to evaluate the proposed algorithm. The experimental results show that the proposed algorithm holds a stable performance and can still achieve accurate spatial alignment even with the huge nonlinear intensity differences.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622502851
       
  • RNA: A Flexible and Efficient Accelerator Based on Dynamically
           Reconfigurable Computing for Multiple Convolutional Neural Networks

    • Free pre-print version: Loading...

      Authors: Chen Yang, Jia Hou, Yizhou Wang, Haibo Zhang, Xiaoli Wang, Li Geng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The increasingly complicated and versatile convolutional neural networks (CNNs) models bring challenges to hardware acceleration in terms of performance, energy efficiency and flexibility. This paper proposes a reconfigurable neural accelerator (RNA) for flexible and efficient CNN acceleration. To provide hardware flexibility, RNA employs dynamically reconfigurable computing framework to rapidly configure data path between processing elements (PE) at run-time, as well as an interlaced data access mechanism for multi-bank RAM. To achieve high energy efficiency, three optimization mechanisms, including image row broadcasting dataflow (IRBD), tile-by-tile computing (TTC), and zero detection technology (ZDT), are dedicatedly designed for RNA to exploit data reuse and decrease memory bandwidth requirement, which is the key to improving performance and saving power consumption. To save hardware overhead, an online dynamic adaptive data truncation (DADT) mechanism is designed to compensate accuracy loss of multiplication results so that the computational precision in RNA can be reduced from 16-bit to 8-bit, which contributes to reducing the area of data path. The RNA architecture is implemented on Xilinx XC7Z100 FPGA and works at 250[math]MHz. Experimental results show that the performance of running LeNet, AlexNet and VGG are 500 GOPS, 598 GOPS and 660 GOPS, respectively. Compared to previous FPGA-based designs, RNA achieves [math] performance speedup and [math] improvements on energy efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622502899
       
  • Medical Text Classification Based on an Optimized Machine Learning and
           External Semantic Resource

    • Free pre-print version: Loading...

      Authors: Karim Gasmi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Automatic classification of texts is a well-known topic in natural language processing (NLP), and it involves categorizing unstructured texts into specific groups. Classification algorithms for a given problem are searched for, as well as the appropriate features to use as input. These models have been used for analysis of data with a large number of sparse dimensions. In medical field, categorization of medical texts is a difficult task because these types of texts contain several terminologies that define medical ideas and words. Medical data also lack proper sentence structure and do not adhere to the standard rules of natural language grammar. The main problem in this classification task is to choose an appropriate representation as input. To solve the representation problem, we propose a new extension model for medical text personification. Our model starts with the preprocessing of medical text. Then, we use external terminology resources to expand the text. After that, we use a combination of different text vector representations. To speed up the process, we try to increase the accuracy while selecting the optimal classification parameters. In this topic, we use an adaptive particle swarm optimization (PSO) algorithm to select the best parameters of a machine learning model. The PubMed, Hallmarks and AIM dataset were used to test our model. Our categorization text model outperforms the competition and provides much higher retrieval accuracy than previous models.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-07T07:00:00Z
      DOI: 10.1142/S0218126622502917
       
  • Analytical Delay Model and Stability Analysis for MLGNR Interconnects

    • Free pre-print version: Loading...

      Authors: Himanshu Sharma, Karmjit Singh Sandha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper analyzes the signal delay and relative stability of multilayer graphene nanoribbon (MLGNR) interconnects dependent on temperature at global lengths. A thermally aware driver interconnect load (DIL) system, constituted by equivalent single conductor (ESC) model along with mathematical equations, is proposed to convert multi-conductor transmission circuit into single transmission line of MLGNR. The temperature-dependent analytical delay model of MLGNR is evaluated and the obtained outcomes are compared with the simulated results. The analytical and simulated results are obtained at global interconnect length (2000-[math]m) for 32[math]nm, 22[math]nm and 16[math]nm nodes of technology under 200–500[math]K temperature range of MLGNR. The simulation and analytical results reveal that the outcomes of the two models correspond well. The trend of the models shows the increase in delay with the rising temperature levels (200–500[math]K) for three different nodes of technology. Further, relative stability analysis of MLGNR as interconnect line at three different technological nodes from 500–2000-[math]m lengths is examined.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-05T07:00:00Z
      DOI: 10.1142/S0218126622502607
       
  • Design of a 1.29–1.61[math]GHz LC-VCO with Improved Phase Noise and
           Figure-of-Merit (FoM[math]) for GPS and Satellite Navigation

    • Free pre-print version: Loading...

      Authors: Keshab Das, Anup Dandapat, Sanjay Kumar Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper demonstrates a low-phase noise and high FoMT differential CMOS LC-VCO working at 1.29–1.61[math]GHz. An RC filter tail current source is used in this design to reduce the second-harmonic oscillation phase noise. The VCO is implemented in 180[math]nm process technology. The post-layout simulation results indicate that this proposed VCO operates faithfully in the 1.29–1.61[math]GHz band with a frequency tuning range (FTR) of 320[math]MHz. By using inversion mode N-MOSFET varactor, the designed VCO obtains 22.06% FTR. The phase noise of the VCO is [math]130.21[math]dBc/Hz at 1[math]MHz offset frequency. It consumes 4.01[math]mW average power from 1.3[math]V supply. The cell area occupied by the design is [math]. Figure-of-merit considering FTR (FoM[math] is [math]194.14[math]dBc/Hz at 1[math]MHz offset frequency, phase noise and average power consumption. The proposed VCO can be used for low-phase noise GPS and satellite navigation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-07-05T07:00:00Z
      DOI: 10.1142/S0218126622502747
       
  • Deep Transfer Learning-Based Fall Detection Approach Using IoMT-Enabled
           Thermal Imaging-Assisted Pervasive Surveillance and Big Health Data

    • Free pre-print version: Loading...

      Authors: Khosro Rezaee, Mohammad R. Khosravi, Najmeh Neshat, Mohammad Kazem Moghimi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      People’s need for healthcare capacity has become increasingly critical as the elderly population continues to grow in most communities. Approximately 25–47% of seniors fall annually, and early detection of poor balance can significantly reduce their risk. Automated fall detection with big data analytics is key to maintaining the safety of the elderly in smart cities. Visible image systems (VIS) in smart buildings, on the other hand, visible image systems (VIS) in smart buildings may compromise the privacy of seniors by enabling technologies for intelligent big data analytics (IBDA). Thermal imaging (TI) is less obtrusive than visual imaging and can be used in combination with machine vision to perform a wide range of IBDAs. In this study, we present a novel two-step method for detecting falls in TI frames using deep learning (DL). As the first step, tracking tools are used to locate people’s locations. A novel modified deep transfer learning (TL) technique is used to classify the trajectory created by the tracking approach for people who are at risk of falling. Fall detection by the IBDA will be connected to the Internet of medical things (IoMT) and used as smart technology in the process of big data-assisted pervasive surveillance and health analytics. According to an analysis of the publicly available thermal fall dataset, our method outperforms traditional fall detection methods, with an average error of less than 3%. Additionally, IoMT platforms facilitate data processing, real-time monitoring and healthcare management. Our smart scheme for using big data analytics to enable intelligent decisions is compatible with the various spaces and provides a comfortable and safe environment for current and future elderly people.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-29T07:00:00Z
      DOI: 10.1142/S0218126622400059
       
  • Gradient Guided Dual-Branch Network for Image Dehazing

    • Free pre-print version: Loading...

      Authors: Mingliang Gao, Qingyu Mao, Qilei Li, Xiangyu Guo, Gwanggil Jeon, Lina Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, massive deep learning-based image dehazing methods have sprung up. These methods can effectively remove most of the haze and obtain far better results than the traditional methods. With the removal of the haze, however, edge details of the image are also lost, which is usually more noticeable in the gradient space. This paper proposes a gradient guided dual-branch network (GGDB-Net) for image dehazing. Specifically, we explore the hazy image gradient map to guide our model to focus on the hazy regions and edge restoration. We implement two parallel branches with a comprehensive loss function, which collaborate to dehaze and repair the lost edges in haze images. Moreover, the gradient-guided approach can potentially be applied to existing learning-based image dehazing models to boost their performance. Experimental results indicate that our results have good visual perceptions and are comparable to state-of-the-art methods in quantitative metrics.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-29T07:00:00Z
      DOI: 10.1142/S0218126622502905
       
  • Leaf Disease Classification in Smart Agriculture using Deep Neural Network
           Architecture and IoT

    • Free pre-print version: Loading...

      Authors: Kadiyala Ramana, Rajanikanth Aluvala, Madapuri Rudra Kumar, G. Nagaraja, Akula Vijaya Krishna, Pidugu Nagendra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The Internet of Things (IoT) is bringing a new dimension to the smart farming market. This helps the user to collect the data from the agricultural fields in real time and move it to remote areas for processing. With the available sensor data and the image taken from the fields, automated disease prediction is possible. Deep neural network is used for classification of disease using the leaf images. Agriculture is the backbone of our country, but our output is poor when compared to the global standards due to lack of using technologies in the fields. In this work, various sensors like humidity sensor, pH level monitoring sensor, Temperature sensor, and Soil moisture sensor are used in the agricultural fields for collecting the real-time data. Multiple Sensors are installed in various locations of farms with one common controller Raspberry PI 3 module (RPI3), which was used to control all these sensors. Camera interfacing with RPI can be observed on leaf disease. Convolutional neural network architecture is used for leaf disease detection and classification. The accuracy of the disease classification system using convolutional neural network is 96% when the system is iterated for 50 epochs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-27T07:00:00Z
      DOI: 10.1142/S0218126622400047
       
  • Graph Convolutional Neural Network Gesture Recognition Based on Pooling
           Algorithm

    • Free pre-print version: Loading...

      Authors: Hong Chen, Baoqiang Qi, Hongdong zhao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The era of new human–computer interaction has accelerated, and gesture recognition is one of the development trends of human–computer interaction system in the future. The emerging graph neural network can capture the interdependence between instances and infer the complete information of the image based on local features, which is helpful to the recognition of human gestures. Therefore, the combination of graph neural network and convolutional neural network (CNN) is applied to the research of gesture recognition and it has important research significance. This paper uses the Mixup method to perform data enhancement processing on the collected image data set, applies the pyramid pooling method to the EigenPooL model to achieve efficient capture of image features and selects the Sigmoid function and the PReLU function as the activation function of the network model to meet the model’s requirements, such as long time training and strong fitting ability. This paper introduces the structure and algorithm of EigenPooL model in detail. The algorithm uses hypergraph learning method instead of simple graph learning method. On the gesture picture test set, the average accuracy of the algorithm is 86.50%, the recall rate is 94.87% and the average detection time per frame is 421[math]ms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-27T07:00:00Z
      DOI: 10.1142/S0218126622502711
       
  • An Improved TCN Considering Data Augmentation in Enabling Load
           Classification

    • Free pre-print version: Loading...

      Authors: Ding Han, Hongkun Bai, Yuanyuan Wang, Shiqian Wang, Jie Zhang, Yang Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In modern power system, along with the developments of the data collecting technologies, the intensive and high-dimensional load data collection can be achieved. Therefore, to deeply reveal the patterns and behaviors hidden in the load dataset using load classification is of great significance for improving the service quality and the user experience of the power system. However, inevitable issues, for example the data missing and class imbalance are frequently reported in the present load dataset, which deteriorates the performance of the classification algorithms. Also, due to the special features, for example the time series, periodicity, and fluctuation of the load data, the traditional data classification algorithms also encounter performance defects. Therefore, this paper presents a data augmentation based enhanced temporal convolutional network (TCN) algorithm in enabling load classification. In the data augmentation phase, first an LRTC-TSVD algorithm is presented to implement the missing data completion. Second, a WGAN based class balancing approach is further presented to solve the class imbalance issue. Then, in the enhanced TCN phase, a WeightNorm, exponential linear unit (ELU) activation function, residual connection, and bidirectional feature fusion techniques based improved TCN (ITCN) algorithm is presented to carry out the accurate load data classification. Combining the data augmentation and the enhanced TCN phases, the ITCN algorithm is finally conducted. Based on the benchmark load datasets, the performances of the presented ITCN are evaluated. The experimental results report that the presented data augmentations can improve the quality of the dataset, moreover the classification algorithm is able to achieve the satisfied classification accuracy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S021812662250284X
       
  • An Efficient Corner Detector Using Ratio of Center Distance of Symmetric
           Contour Technique

    • Free pre-print version: Loading...

      Authors: Shizheng Zhang, Shan Liu, Qian Zheng, Min Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Feature detection is one of the basic research topics in the fields of image processing and corner that has been widely applied on vehicle detection, UAV image matching, camera calibration and so on. Particularly, a fast corner detector is of much benefit to many real-time tasks. A novel discrete curvature estimation method for corner detection based on the ratio of center distances of symmetric contour (RCDSC) is proposed in this paper. Benefiting from calculating the Euclidean distance twice only to estimate the discrete curvature at each point on a contour, RCDSC is much fast compared with other corner detectors. In addition, by choosing a relatively large radius of region of support and employing relative distance instead of absolute distance for constructing corner response function, RCDSC is also much robust to noises and local variations of contour. Extensive experiments exhibit the effectiveness and the efficiency of RCDSC in terms of average repeatability (AR), accuracy (ACU) and localization error (LE).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S0218126622502863
       
  • Event-Triggered Neural Network Control for Uncertain Nonlinear Systems
           Without State Observer

    • Free pre-print version: Loading...

      Authors: Hui Hu, Yuebiao Wang, Wei Yi, Yang Li, Jiande Yan, Wei Xiao, Junqi Yuan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A robust approximation-based event-triggered control method is presented for single input single output (SISO) nonlinear continuous-time systems with unmeasurable states and external disturbance. In the whole system, just one neural network (NN) is designed to approximate the unknown part in the controller, and output errors are directly used to construct the system controller and event-triggered mechanism to relieve the burden of system communication. The controller with a simple structure is easier to be realized in practical engineering. The system control signals and adaptive parameters are updated only if the event trigger condition is met, and this way further reduces the waste of network resources caused by frequent system sampling. The application of stability theory of Lyapunov proves that the weight estimation of the NN and tracking errors are ultimate and uniform boundedness, and the efficacy of the proposed scheme is verified with numerical results on a robot.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S0218126622502632
       
  • Simulation and Analysis of a Digitally Controlled Differential Delay
           Circuit Under Process, Voltage, Temperature and Noise Due to Injection of
           High Current

    • Free pre-print version: Loading...

      Authors: Mithilesh Kumar, Alak Majumder, Abir J Mondal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0[math]A) to 10 or 30[math]A or else 50[math]A in 10[math]ns. Simulated in a 0.09-[math]m CMOS process and power supply voltage ([math]) of 1.1[math]V, the proposed circuit in post-layout can operate from 435.5[math]ps to 152.2[math]ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5[math]ps for NN and SS process corner, respectively, following a [math]C change in temperature. But an abrupt high current [math] pumped into the chip causes the voltage ([math]) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp [math] of 0–50[math]A in 10[math]ns for the two vector CBA happens to be around 5.0 and 4.4[math]ps, respectively. The current ramp also generates power supply noise of 0.468[math]V occurring close to the silicon chip. This, in turn, corresponds to a [math] of 0.642[math]V near the die, appearing to be much less than the required [math] of 1.1[math]V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642[math]V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-24T07:00:00Z
      DOI: 10.1142/S0218126622502760
       
  • Genetic Evolution-Based Feature Selection for Software Defect Prediction
           Using SVMs

    • Free pre-print version: Loading...

      Authors: Somya Goyal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Software Defect Prediction (SDP) involves the early detection of fault-prone modules and reduces the testing efforts and cost. Support Vector Machine (SVM)-based SDP classifiers use large amount of high-dimensional data, and hence feature selection (FS) is applied for better accuracy. Search-based feature selection is found effective to improve the efficiency of predictors. This paper proposes a genetic evolution (GeEv) technique to select features. The GeEv technique involves introduction of diversity at intermediate level by the genetic evolution of random offspring with better survival capability. GeEv searches the feature space for an optimal feature subset using the performance of classification and number of features selected as the fitness function. The FS is modeled as an optimization problem and optimal solution is sought using GeEv. The performance is compared with baseline technique. From the experimental results, it is shown GeEv outperforms the competing FS approach and can achieve better accuracy than others statistically.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-23T07:00:00Z
      DOI: 10.1142/S0218126622501614
       
  • Remu-Net: Multi-Branch Net Framework for 3D Brain Tumor Segmentation

    • Free pre-print version: Loading...

      Authors: Zu-Min Wang, Lei Dong, Min Zhang, Bing Gao, Zong-Kang Jiang, Yu-Cong Duan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As one of the fatal human diseases, early detection of brain tumors can effectively save patients’ lives. Brain tumor image segmentation is of great practical importance for physicians to perform brain tumor diagnoses quickly. Due to the data complexity of 3D brain images, it is impractical to segment out tumor regions manually, so automatic and reliable methods can be utilized instead of manual work to achieve accurate segmentation of tumor regions. In this paper, we propose an end-to-end, more efficient brain tumor MRI segmentation model, REMU-Net, for the problems of multi-scale feature extraction and difficulty in small target feature extraction in 3D brain tumor image segmentation. Firstly, design and use the multi-channel parallel M-RepVGG module as a decoder to achieve multi-scale feature fusion. Secondly, embedding dilated convolution with different dilated rates in the DM-RepVGG module of the encoder to better extract features at different scales. Finally, introduce the expectation-maximizing attention in the network to better extract the features of the internal details of the tumor. The experimental results on the BraTS2018 validation dataset are Dice scores of 80.93%, 90.13%, and 86.15%, respectively. Experimental results on the BraTS2019 validation dataset can be achieved with Dice scores of 78.29%, 90.65%, and 82.77%, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S0218126622502164
       
  • Mobile Robot Path Planning Method Based on Deep Reinforcement Learning
           Algorithm

    • Free pre-print version: Loading...

      Authors: Haitao Meng, Hengrui Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Path planning is an important part of the research field of mobile robots, and it is the premise for mobile robots to complete complex tasks. This paper proposes a reflective reward design method based on potential energy function, and combines the ideas of multi-agent and multi-task learning to form a new training framework. The reflective reward represents the quality of the agent’s current decision relative to the past historical decision sequence, using the second-order information of the historical reward sequence. The policy or value function update of the master agent is then assisted by the reflective agent. The method proposed in this paper can easily extend the existing deep reinforcement learning algorithm based on value function and policy gradient, and then form a new learning method, so that the agent has the reflective characteristics in human learning after making full use of the reward information. It is good at distinguishing the optimal action in the corresponding state. Experiments in pathfinding scenarios verify the effectiveness of the algorithm in sparse reward scenarios. Compared with other algorithms, the deep reinforcement learning algorithm has higher exploration success rate and stability. Experiments in survival scenarios verify the improvement effect of the reward feature enhancement method based on the auxiliary task learning mechanism on the original algorithm. Simulation experiments confirm the effectiveness of the proposed algorithm for solving the path planning problem of mobile robots in dynamic environments and the superiority of deep reinforcement learning algorithms. The simulation results show that the algorithm can accurately avoid unknown obstacles and reach the target point, and the planned path is the shortest and the energy consumed by the robot is the least. This demonstrates the effectiveness of deep reinforcement learning algorithms for local path planning and real-time decision making.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S0218126622502589
       
  • A High Speed Phase Detection Circuit with No Dead Zone Suitable for
           Minimal Jitter and Low Power Applications

    • Free pre-print version: Loading...

      Authors: Jyoti Sharma, Gaurav Kumar Sharma, Tarun Varma, Dharmendar Boolchandani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit’s robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of [math][math]dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25[math][math]W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275[math][math]m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S021812662250267X
       
  • Evolution of Labor Relations in the Development of Human Resources Based
           on Improved Genetic Algorithm

    • Free pre-print version: Loading...

      Authors: Min Qin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper systematically constructs a multi-project and a multi-objective human resource scheduling mathematical model in construction projects and puts forward an improved genetic algorithm to solve it by aiming at the problems existing in the process of human resource scheduling and optimization. Specifically, first, the basic mathematical models of GPRs and resource-constrained construction project human resource scheduling problem (RCWSP/GPRs) are established, and the multi-project equilibrium problem is extended. Then, an improved inter-cluster separation (ICS) algorithm is proposed and used to solve the RCWSP/GPRs problem. Finally, on this basis, the mathematical model of multi-project and multi-objective human resource scheduling problem and the solution method based on multi-objective-integrated circuit are proposed. At the same time, the resource-constrained multi-project and multi-skill human resource scheduling problem and the integer programming mathematical model under the generalized priority relationship are proposed. Also, the simulation results verify the accuracy of the proposed algorithm and model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-22T07:00:00Z
      DOI: 10.1142/S0218126622502723
       
  • Monitoring and Locating Oceanic Sailors Through Wireless Sensor Network

    • Free pre-print version: Loading...

      Authors: Shruti Gupta, Shailendra Narayan Singh, Vineet Kansal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A systematic oceanographic monitoring and management requires an effective marine tracking system. It helps the localization of different marine assets, their border control and in encountering emergency situations. Thus, a reliable marine tracking system is always required to ensure a safe marine environment for shippers, fishers, sailors and other marine assets. Nowadays due to the evolution in wireless sensor network (WSN) technology, their easy and inexpensive deployment can be seen in different fields such as agriculture, medical, industries and IoT. The implementation of WSN in the marine environment comes with various issues due to the complex behavior of the marine environment and thus affects the reliability of the system. In this paper, a WSN-based marine tracking protocol sailing is presented, which identifies the location of marine assets reliably through the genetic firefly (GEFIR) algorithm. The system comprises sensor nodes, sink nodes, server-client terminals and a base station. The protocol uses the application and contact layers to create a group of beacon nodes (boats) based on the geographical location to conserve energy and increase data reliability. GEFIR algorithm is implemented to give a precise and more convenient data to the WSN for the mariners. The results show a better performance for latency calculation through the WSN- and GEFIR-based sailing protocol. The system generates the alert to nodes (sailors) in case they are moving out from a specified region and sends their location for further communication.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-18T07:00:00Z
      DOI: 10.1142/S0218126622502693
       
  • DM-Pages: Improving Energy Efficiency of Disk Storage Systems and Cache
           Performance Using Deduplication-based Mixed Pages

    • Free pre-print version: Loading...

      Authors: Lei Si, Shujie Pang, Yuhui Deng, Weiheng Zhu, Yi Zhou, Yifeng Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a deduplication-based mixed page strategy, called DM-Pages, to improve the energy efficiency of disk storage systems and the cache performance. DM-Pages strives to improve the cache hit rate, simultaneously reduce the number of power-state transitions of a disk storage system and keep it in a low-power state as long as possible. DM-Pages deploys three innovative techniques. It adjusts the size of huge pages dynamically to maximize the cache hit rate. Meantime, content-aware deduplication is applied to eliminate redundant cache pages, targeting to enhance cache utilization. In addition, DM-Pages incorporates a mixed page mechanism into disk energy management to save energy. Our experimental results show that DM-Pages significantly improves the energy efficiency of disk storage systems and achieves a high cache hit rate. In particular, compared with traditional disk storage systems, DM-Pages conserves 6.59 times energy and improves the cache hit rate up to 3.36 times.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-18T07:00:00Z
      DOI: 10.1142/S0218126622502759
       
  • Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT

    • Free pre-print version: Loading...

      Authors: AbdolVahab Khalili Sadaghiani, Samad Sheikhaei, Behjat Forouzandeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator’s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-17T07:00:00Z
      DOI: 10.1142/S0218126622200031
       
  • Double Differential Blocks Based Frequency Compensation: A Four-Stage CMOS
           Amplifier

    • Free pre-print version: Loading...

      Authors: Ali Mohammad Sanaei, Ali Biabanifard, Mohammad Saeed Khadem, Toktam Aghaee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18[math][math]m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-17T07:00:00Z
      DOI: 10.1142/S0218126622502735
       
  • Novel Brain Tumor Classification Model with MLPNN Using UNET

    • Free pre-print version: Loading...

      Authors: M. Vimala, P. Ranjith Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The detection and assessment of brain tumor are crucial for medical diagnosis. The MRI study supports radiologists and surgeons in the development of strategies for patient care in medical imaging. Accurate classification and segmentation of abnormal tissue over normal tissue are a key element. The proposed research work focused on an efficient Brain Tumor Segmentation and Classification approach named Multi-Feature Frequency Similarity Multi-Layer Perceptron Neural Network (MFFS-MLPNN). The proposed model considers both low- and high-grade features of glioblastoma present in MR images and varying features of tumors according to their size, contrast and texture. The MRI brain image is preprocessed by applying contrast curvature-based iterative shearlet filter and histogram equalization technique for enhancement. Followed by preprocessing, the denoised image has been segmented using the U-NET segmentation methodology. After segmentation, the tumors are extracted by using the cross-multi-linear local embedding method. The extracted features including Gray–White (GW) features were trained with multi-layer perception neural network for classification. The tumor has been classified into malignant and benign based on the result of multi-layer perceptron neural network. Based on the value of MFFS value, the algorithm performs classification. The effectiveness of the proposed MFFS-MPLNN algorithms has been verified over BRATS 2018 and 2019 datasets and compared with other state-of-the-art techniques. The experimental results show that average dice score is 85.47% for BRATS 2018 dataset whereas average dice score is 75.4% for BRATS 2019. It is observed that the dice score value is increased from 73.3% to 85.47% for BRATS 2018 and 64.3% to 75.4% for BRATS 2019 dataset. The average Hausdorff distance value has been decreased from 9.6% to 4.98% for BRATS 2018 dataset and 14.3% to 6.24% for BRATS 2019 dataset. Similarly, the sensitivity of the proposed algorithm has been increased from 70.7% to 89% and 61% to 82.1% for both BRATS 2018 and BRATS 2019 datasets, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502450
       
  • The Effect of Using Multi-Scroll Chaotic Systems on Chaos-Based Random
           Number Generators’ Performance

    • Free pre-print version: Loading...

      Authors: Serdar Çiçek
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Chaotic and hyper-chaotic systems are used in various engineering applications such as encryption, communication, and artificial intelligence. Also, chaotic systems are widely used in chaos-based random number generator (RNG) designs as chaotic system signals are not periodic and produce different values continuously. Since multi-scroll chaotic systems (MSCSs) produce more than one scroll, the output values can take more different values than chaotic systems. In this study, the effects of different directional values and/or different numbers of scrolls of multi-scroll chaotic systems on chaos-based random number generators’ performance are investigated with NIST 800-22 (National Institute of Standards and Technology) and correlation coefficient tests. As a result of the research, it has been concluded that the use of multi-scroll chaotic systems with different directional values and/or different numbers of scrolls does not always have a direct positive effect on the performance of chaos-based random number generators. Thus, it is necessary to use a special pre-process method that will vary according to the multi-scroll chaotic system to be used for chaos-based RNG designs with good performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502590
       
  • A Novel Design of High-Performance Hybrid Multiplier

    • Free pre-print version: Loading...

      Authors: Jugal Kishore Bhandari, Yogesh Kumar Verma, Laxman Singh, Santosh Kumar Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502681
       
  • DC Voltage Inversion Estimation Method of MMC Submodule Based on Current
           Information

    • Free pre-print version: Loading...

      Authors: Yang Zhang, Ran Zhao, Yunmin Xie, Jianbing Liu, Jing Sheng, Huijun Xu, Fanxing Rao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      DC voltage detection of sub-modules is very important for the stability of cascaded multilevel converters. Operation and maintenance personnel need a detection algorithm to supplement the uncertainty and risk caused by the traditional redundancy scheme. This paper presented a DC voltage indirect estimation method based on current transformer. The method uses the AC side current value, as well as the sub-module equivalent circuit model and switching state to estimate the DC voltage of the sub-module of the cascade system. The estimation models are established and can be used to the sub-modules of three topologies, i.e., half-bridge, H bridge topology and clamp double sub-module. Simulation and experimental systems are built to testify the proposed method. The results showed that, when [math] or 12, the indirect detection model based on AC current met the requirements of detection accuracy within 1% under different calculation steps, and the sampling error had little influence on it. The indirect estimation method could reduce the use of DC transformers and improve equipment reliability and maintainability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S021812662250270X
       
  • Emergency Response System Combining the Internal and External Domains
           (ERSCIED)

    • Free pre-print version: Loading...

      Authors: Wei Liang, Yanyan Huang, Jianyu Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Agent-based modeling is a promising approach for developing simulation tools for natural hazards in different areas, such as during urban search and rescue (USAR) operations. The previous studies aimed to develop a dynamic agent-based simulation model in post-earthquake emergency response operations combining rescuers and victims using geospatial information systems and multi-agent systems (GISs and MASs, respectively). We use multi-agent system engineering (MaSE) to construct this model and cluster points are proposed to assemble rescuers and victims. We also proposed an approach for dynamic task allocation and for establishing collaboration among agents based on contract net protocol (CNP) and the [math]-means clustering method. Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS) and expert evaluation is used to sort the priorities of cluster points. The experimental background is set in the central area of Chengdu, Sichuan Province, China. 200 victims with different demands and 30 rescuers with the same rescue capability are randomly distributed in this area. We use different victim speeds to simulate different degrees of seismic damage. Compared with normal search and rescue, the ERSCIED can make some use of the capabilities of the victims for the improvement of emergency effectiveness when the victims and rescuers have a similar speed (1:1) or the victims are not much slower than the rescuers (1:2). When the victims are much slower than the rescuers (1:10), the rescuers have to wait for a long time at the cluster points and it will lead to a waste of resources. The parameters of rescuers and victims can be changed to meet different emergencies and the ERSCIED can provide effective auxiliary decision-making information for decision-makers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-16T07:00:00Z
      DOI: 10.1142/S0218126622502814
       
  • CMOS Compatible First-Order Current Mode Universal Filter Structure and
           its Possible Tunable Variant

    • Free pre-print version: Loading...

      Authors: Jitendra Mohan, Bhartendu Chaturvedi, Jitender
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel first-order universal filter structure supporting current mode operation is proposed in this paper. The filter has a single active building block based realization and utilizes an extra-X second-generation current conveyor as an active building block. Additionally, the proposed circuit employs a grounded resistor and a grounded capacitor as passive components. The circuit has the ability to deliver the all-pass, high-pass, and low-pass functionalities simultaneously without meeting any passive components matching constraint. High output impedance and load insensitive outputs are other remarkable signal processing features offered by the proposed filter structure. Theoretical behavior of the proposed filter is described by presenting ideal, non-ideal, parasitic, and stability analyses. Additionally, the resistorless variant of the proposed filter is also shown to impart the tunability feature. Personal simulation program with integrated circuit emphasis (PSPICE) simulation results are presented to verify the theoretically described performance of the proposed universal filter. Complementary metal oxide semiconductor (CMOS) realization of extra-X second-generation current conveyor is utilized for the purpose of simulations, therefore, the filter is CMOS compatible.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-15T07:00:00Z
      DOI: 10.1142/S0218126622502425
       
  • Approximate Multipliers Design Using Approximate Adders for Image
           Processing Applications

    • Free pre-print version: Loading...

      Authors: S. P. Joy Vasantha Rani, J. R. Lourdu Jennifer, P. Sudhanya
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Addition and multiplication are some of the most broadly adopted arithmetic operations in a wide range of applications. This paper proposes new structures of approximate multipliers to optimize the area, delay, and power without affecting the accuracy metrics. Multipliers and adders play a significant role in the functioning of any digital circuit or system. The overall performance of a processor highly depends on the speed of adders and the energy consumption. In this paper, two types of compact error-tolerant approximate adders are designed and used along with approximate 4:2 compressors to improvise the efficiency of the approximate multipliers. The proposed approximate multipliers show good results when compared to the existing structures in terms of area, delay, power, and accuracy. The approximate multipliers are applied to image sharpening and image multiplication applications. The error-tolerant adder’s performance is evaluated in the practical domain using the image blending application. Peak signal-to-noise ratio (PSNR) performance and the structural similarity index metric (SSIM) are used to assess the modeled designs. The proposed approximate multipliers and adders exhibit better performance in terms of PSNR and SSIM and are found to be an optimized design to apply effectively in various error-tolerant image processing applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-11T07:00:00Z
      DOI: 10.1142/S0218126622502565
       
  • Runtime Assurance of Learning-based Lane Changing Control for Autonomous
           Driving Vehicles

    • Free pre-print version: Loading...

      Authors: Qiang Wang, Guang Kou, Longquan Chen, Ying He, Weipeng Cao, Geguang Pu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Learning techniques such as deep reinforcement learning have been increasingly used in the controller design for autonomous vehicles, e.g., lane changing controllers. Although the use of learning techniques can remarkably increase the level of autonomy, their presence poses a great challenge for safety assurance due to the black-box and data-driven nature of learning techniques. In this work, we study the problem of how to safeguard the learning-based lane changing controller for collision avoidance. Our solution leverages on the runtime assurance framework, in particular the Simplex architecture to bound the behavior of the learning-based controller and to provide safety guarantees. The basic idea is to encompass the learning-based controller with a safety-by-construction controller and a decision module, which monitors the output of the learning-based controller at runtime and implements a switching logic between these two controllers according to the changing environment. We present the detailed design of the decision module and formally prove its correctness for collision avoidance. We also carry out a comprehensive experimental evaluation in a set of realistic highway scenarios using the SUMO simulator. The simulation results show that our proposed solution can not only provide safety guarantee for the learning-based lane changing controller, but also maintain a considerable level of efficiency in different volumes of traffic flow.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-10T07:00:00Z
      DOI: 10.1142/S0218126622502498
       
  • Low Power Squaring Circuit Using Single Voltage Differencing Buffered
           Amplifier

    • Free pre-print version: Loading...

      Authors: Priyanka Gupta, Rajeshwari Pandey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a squaring circuit is proposed using a voltage differencing buffered amplifier (VDBA). The squaring circuit consists of a VDBA, two NMOS transistors and one resistor. The proposed structure facilitates easy cascading without any requirement of additional buffer. The behavior of the proposed structure is analyzed in the presence of nonidealities of VDBA and the corresponding mathematical formulations are also presented. The workability of the proposed circuit is verified through Cadence Virtuoso Analog Design Environment tool using 0.18[math][math]m generic process design kit parameters. Both pre- and post-layout simulation results have been included to confirm the functionality of the proposed circuit. The 3-dB frequency of the proposed circuit using schematic and post-layout-driven simulations is observed to be 3.77 and 3.72[math]MHz, respectively. The power consumption of the proposed squaring circuit is found to be 110[math][math]W. The process, voltage and temperature (PVT) analysis has also been carried out to check the robustness of the proposed circuit. Total harmonic distortion for the entire input range is found to be less than 3%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-10T07:00:00Z
      DOI: 10.1142/S021812662250253X
       
  • Improved State-Space All-Digital Filters via Series Approximations

    • Free pre-print version: Loading...

      Authors: Ibrahim Rahmani, Lahcene Mitiche, Amel Baha Houda Adamou-Mitiche
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, variable digital filters (VDFs) have become an essential research topic. This paper presents a simple method for the design of infinite impulse response (IIR) VDFs with high tuning accuracy. First, VDFs were created using a state-space model based on a frequency transformation, which requires the inverse matrix and the square root that leads to high computational cost. Then a new algorithm was implemented to generate the same VDFs absent the complex calculations that utilized negative binomial and Taylor series approximations in a simple state-space formulation. This algorithm provides high-accuracy approximations of the inverse matrix and square root compared to other algorithms that have been developed. Thus, the proposed VDFs have high tuning accuracy with respect to finite wordlength effects.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-09T07:00:00Z
      DOI: 10.1142/S0218126622502383
       
  • How Does Consumer Privacy Affect Personalized Pricing' Analysis Based
           on Intertemporal Dynamic Game Model

    • Free pre-print version: Loading...

      Authors: Biao Ma, Xuefen Wang, Li Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of e-commerce and big data technology, firms can increase profits by implementing personalized pricing for specific consumers. However, this is affected by the externality of consumer privacy. To address this problem, this study establishes an intertemporal dynamic game model. Switching costs, firms’ personalized pricing orientation costs, and consumer privacy costs are then introduced into the model, and the effect of consumer privacy on personalized pricing is analyzed. The results show that improving firms’ pricing accuracy will aggravate market price competition, reduce firms’ profits, and improve consumer surplus. Consumer switching costs make it impossible for a firm to poach the loyal consumers of a rival firm through unified pricing, but poaching can also be achieved through group pricing. However, if the pricing accuracy of both firms is improved through personalization, poaching will not occur. Switching costs enhance the effect of improved pricing accuracy on the profit loss of both firms. Firms’ personalized pricing orientation costs and consumer privacy costs enhance the effect of personalized pricing strategies. Our research provides decision-making reference for enterprise pricing strategy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-09T07:00:00Z
      DOI: 10.1142/S0218126622502516
       
  • SDN Framework for Mitigating Time-Based Delay Attack

    • Free pre-print version: Loading...

      Authors: Sagar V. Ramani, Rutvij H. Jhaveri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to recent cyberattacks on the Cyber-Physical Systems, the traditional security schemes face difficulties in dealing with such attacks as the attackers nowadays have adopted many intelligent mechanisms involving advanced information and communication technologies to launch attacks. This recent type of attack provides a significant impact on the resiliency of the software-defined networks. In this paper, we present a real-time delay attack on fault-resilient software-defined networks. The main objective of the time delay attack is to reduce the resiliency in the SDN-RM by adding a delay in the LLDP packets in the OpenFlow Switch. This addition of delay causes degradation in the network performance resulting in a low success rate in the SDN-RM mechanisms. In this paper, we present a machine learning-based detection system for detecting the attacks. The integration of machine learning techniques with network resilience solutions can effectively address the issue of predicting and classifying the LLDP packets that are delayed at a particular switch. Another issue is the detection of the malicious switch at the controller side which results in the improvement of the resiliency in SDN-RM. We propose a machine learning solution to detect the anomalies that are present in the topology and can be detected at the controller side. We use machine learning models such as k-nearest neighbors, support vector machines (SVM), Random Forest, and decision trees to detect the poisonous switches. The delay-based time attack detection system (DTA-DS) helps the controller to take a reactive decision to improve resilience by detecting poisonous network switches. With the help of the preventive approach, we achieve high-fault resiliency in fault resilient-based software-defined networks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-09T07:00:00Z
      DOI: 10.1142/S0218126622502644
       
  • End-to-End Deep Policy Feedback-Based Reinforcement Learning Method for
           Quantization in DNNs

    • Free pre-print version: Loading...

      Authors: R. Logesh Babu, Sasikumar Gurumoorthy, B. D. Parameshachari, S. Christalin Nelson, Qiaozhi Hua
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the resource-constrained embedded systems, the designing of efficient deep neural networks is a challenging process, due to diversity in the artificial intelligence applications. The quantization in deep neural networks superiorly diminishes the storage and computational time by reducing the bit-width of networks encoding. In order to highlight the problem of accuracy loss, the quantization levels are automatically discovered using Policy Feedback-based Reinforcement Learning Method (PF-RELEQ). In this paper, the Proximal Policy Optimization with Policy Feedback (PPO-PF) technique is proposed to determine the best design decisions by choosing the optimum hyper-parameters. In order to enhance the sensitivity of the value function to the change of policy and to improve the accuracy of value estimation at the early learning stage, a policy update method is devised based on the clipped discount factor. In addition, specifically the loss functions of policy satisfy the unbiased estimation of the trust region. The proposed PF-RELEQ effectively balances quality and speed compared to other deep learning methods like ResNet-1202, ResNet-32, ResNet-110, GoogLeNet and AlexNet. The experimental analysis showed that PF-RELEQ achieved 20% computational work-load reduction compared to the existing deep learning methods on ImageNet, CIFAR-10, CIFAR-100 and tomato leaf disease datasets and achieved approximately 2% of improvisation in the validation accuracy. Additionally, the PF-RELEQ needs only 0.55 Graphics Processing Unit on an NVIDIA GTX-1080Ti to develop DNNs that delivers better accuracy improvement with fewer cycle counts for image classification.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-08T07:00:00Z
      DOI: 10.1142/S0218126622502322
       
  • An Intelligent Decision Framework for Loan Allocation Schemes

    • Free pre-print version: Loading...

      Authors: Min Hu, Qiao Li, Ling Pan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the constant development of economy, how to reasonably allocate limited loans to enterprises has been an interesting issue. As a result, adaptive decision for optimal loan allocation schemes is well worth investigating. Although some researchers had utilized machine learning-based techniques to deal with such issue, they cannot handle well the scenarios where total capital amount is limited. To bridge such gap, this paper proposes an intelligent decision framework for loan allocation schemes in complex social systems. First of all, the expressions about profit and risk of the bank side are deduced, separately. On this basis, the dynamic planning approach is adopted to formulate a set of optimization model. Specifically, such model is established from two aspects: profit maximization and risk minimization. Hence, two groups of decision results can be reached from two different perspectives by searching optimal solution of the planning model. This work also gives a case study on a real-world dataset to present process of the planning model. Thus, two referential results are provided with use of optimization solution tool.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-08T07:00:00Z
      DOI: 10.1142/S0218126622502504
       
  • Safety Risk Assessment of Electric Power Operation Site Based On Variable
           Precision Rough Set

    • Free pre-print version: Loading...

      Authors: Zhengwei Chang, Yuanshi Deng, Jie Wu, Xingzhong Xiong, Mingju Chen, Hong Wang, Xiaona Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to improve the intelligent informatization level of electric power production safety and reduce the accidents, the paper constructs a dynamic perception scheme of electric power production site that utilizes multi-dimensional information such as personnel location, equipment status, and image information. This method uses a multi-sensor network to realize the real-time perception of the image and position information of dynamic power work objects, then uses object identification and intelligent analysis to acquire the dynamic factors. Static factors are selected through questionnaire and historical data, and variable precision fuzzy theory is used to calculate the weight of static factors at dynamic power operation sites. A comprehensive evaluation is established to perceive risk and estimate security probability based on static factors and dynamic scene information. The application system can present the situation of the operation scene, and then realize safety assessment and early warning of the dangerous situation in the case of dynamic power monitoring. This method can prevent safety accidents and enhance the overall safety of power operations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-08T07:00:00Z
      DOI: 10.1142/S0218126622502541
       
  • Complexity-Reduced Parallel Time-Interleaved Delta–Sigma Modulator for
           Transmitter Applications

    • Free pre-print version: Loading...

      Authors: Nasser Erfani Majd, Rezvan Fani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High sampling frequency requirement in delta–sigma modulator (DSM) is one of the limiting factors toward its employment in high-frequency application, such as software-defined radio (SDR) transmitters. In this paper, a complexity-reduced parallel time-interleaved DSM is proposed to reduce the clock speed requirement of DSM transmitters. The complexity of the proposed parallel time-interleaved DSM is reduced by input delay blocks and input downsampler blocks in comparison to conventional time-interleaved DSMs. Simulation results show that the clock speed requirement of DSM transmitter is reduced four times by using the proposed four-branch complexity-reduced time-interleaved DSM, while signal quality is maintained.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-04T07:00:00Z
      DOI: 10.1142/S0218126622502413
       
  • A Time and Reliability Optimization Algorithm for Workflow Scheduling in
           Heterogeneous Distributed Computing System

    • Free pre-print version: Loading...

      Authors: Junqiang Jiang, Hailin Cai, Lunxin Xie, Zhifang Sun, Li Pan, Zhihe Yang, Ruiqi Lu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the heterogeneous distributed computing systems, efficient task scheduling is necessary for high performance. System reliability and completion time are generally the two important metrics. In this paper, we proposed an algorithm named Merging and Duplication for Makespan and Reliability (MDMR) which combines task merging and task duplication to achieve single-objective constrained optimization of workflow reliability and completion time. The MDMR algorithm is divided into three phases: task merging, entry task duplication and reliability detection with nonentry task duplication. In the task merging phase, two tasks with a sole parent–child relationship are merged into a single task, then this process is iterated until no tasks satisfy the merging condition, thus simplifying the directed acyclic graph. In the entry task duplication phase, the entry task with the lowest reliability is duplicated on the processors, which are available at that moment to increase the reliability while reducing the workflow completion time. In the reliability detection and nonentry task duplication phase, the current workflow scheduling reliability is first calculated, then the result is directly output if the reliability is higher than the target value, otherwise the nonentry task duplication is executed with the aim of increasing the reliability until the value surpasses the target. According to the experimental results, MDMR dominates the compared algorithms and ensures that the entire workflow achieves the target reliability and shortens the workflow makespan as much as possible.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-04T07:00:00Z
      DOI: 10.1142/S0218126622502528
       
  • Vertical Negative Effect Suppression of In-Wheel Electric Vehicle Based on
           Hybrid Variable-Universe Fuzzy Control

    • Free pre-print version: Loading...

      Authors: Zhengtong Zhu, Xinfeng Ge
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To suppress a negative effect brought by introducing hub motor in vertical vibration of the body and that of a hub motor, a suppressing vertical negative effect algorithm of in-wheel electric vehicle is proposed based on hybrid variable universe fuzzy control (VUFC). Vertical accelerations of the body and that of the hub motor are taken as optimization objects, and to control the main suspension damper and in-wheel damper simultaneously, the semi-actively VUFC algorithm is adopted to improve vertical vibration characteristics effectively. The simulated results show that the peak and root mean square (RMS) of body vertical acceleration (VA) are optimized by 21.0% and 19.6%, respectively, after optimization compared to the original in-wheel electric model, the peak and RMS of hub motor VA are optimized by 30.1% and 32.5%, respectively, and the vertical negative effect is suppressed significantly.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-04T07:00:00Z
      DOI: 10.1142/S0218126622502577
       
  • Design of a High Performance 1 Kb SRAM Array Using Proposed Soft Error
           Hardened 12T SRAM Cell

    • Free pre-print version: Loading...

      Authors: R. Manoj Kumar, P. V. Sridevi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The shrinking of technology node and supply voltage has a profound effect on various design metrics of the SRAM cell. Available SRAM designs in the literature suffer from half-select issue, increased write delay, leakage power, read power, and lower critical charge. Considering the above concerns, a new P12T SRAM cell was proposed incorporating the cross-point selection to remove half-select issue, adding the inverter between the storage nodes to enhance critical charge, High-[math] transistors in read path to reduce the read power and leakage power. The critical charge of P12T SRAM cell is 9.13% and 15.21% higher than the 8T and 10T SRAM cells, respectively, at 0.9[math]V [math]. P12T SRAM cell has 41.61% and 21.4% decrease in read power than 8T and AS10T SRAM cells, respectively, at SS corner for 0.9[math]V [math]. In P12T SRAM cell, write 1 PDP at worst case corner SS is [math], [math], [math], [math], and [math] lower than 8T, AS8T, AS10T, 10T, and 12T SRAM cells, respectively, at 0.9[math]V [math]. Monte Carlo simulation has been done to study variability and half-select issue. 1[math]Kb bit interleaving SRAM array is designed using P12T SRAM cell and 12T SRAM cell. 1[math]Kb SRAM array using P12T SRAM cell has superior write PDP than 12T SRAM cell. Postlayout simulation has been carried out on all the SRAM cells to estimate different metrics in 45[math]nm technology using the Cadence Virtuoso.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-03T07:00:00Z
      DOI: 10.1142/S0218126622502401
       
  • SCASA: A Spark-Based Parallel Approach for Net Primary Productivity
           Calculation with CASA Model

    • Free pre-print version: Loading...

      Authors: Hui Zhang, Kaijun Ren, Xiaoyong Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Net primary productivity (NPP) research is an essential aspect of carbon cycle research. Remote sensing combined with CASA (Carnegie–Ames–Stanford Approach) model is a mainstream method to calculate the NPP, which is generally based on the ENVI or ArcGIS in the standalone mode. However, with the enhancement of spatial and temporal resolution of remote sensing images, the volume of data has also grown rapidly, which makes the centralized methods not well adapted to the NPP calculation. In this paper, we propose SCASA, a Spark-based parallel approach for NPP calculation with CASA model. Based on the distributed storage characteristics of HDFS, we propose a storage strategy specifically for CASA model. Based on the characteristics of CASA model and Spark’s parallel computing rules, we redesign the computation process to maximize parallelism to further improve the calculation speed. Extensive comparative experiments based on ArcGIS and Spark demonstrate the proposed approach outperform the existing CASA model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-03T07:00:00Z
      DOI: 10.1142/S0218126622502449
       
  • Boosting the Quality Factor of the Shadow Bandpass Filter

    • Free pre-print version: Loading...

      Authors: Seangrawee Buakaew, Chariya Wongtaychatham
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new method to increase the quality factor of the shadow bandpass filter. The proposed circuit topology is simple, with the use of conventional biquad cell along with external amplifiers. The major advantageous feature is that the quality factor of the filter is boosted up whereas the gain of the external amplifier is significantly reduced. Moreover, the presented idea can be applied to the shadow filter in both current and voltage modes. The proposed scheme is justified via circuit performance. The performance is compared with the previous research works in the same arena. The results show that a feedback signal and a properly chosen gain incredibly boost up the quality factor of the shadow bandpass filter. Simulations by PSpice using 0.18-[math]m CMOS-level parameters confirm the validity of the proposed work.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-03T07:00:00Z
      DOI: 10.1142/S0218126622502486
       
  • On Shielding Android’s Pending Intent from Malware Apps Using a Novel
           Ownership-Based Authentication

    • Free pre-print version: Loading...

      Authors: S. Pradeepkumar Duraisamy, S. Geetha, Xiaochun Cheng, Seifedine Kadry
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      PendingIntent (PI) is an authority to use the sender’s permissions and identity by the receiver. Unprotected broadcast and PI s with an empty base intent are some of the vulnerable features that a malware utilizes to perform unauthorized access and privilege escalation (PE) attacks on the PI. To protect the PI from the above attacks, this paper proposes Sticky[math]tent, an application-layer solution that uses ownership-based authentication to dynamically control the accessibility of the PI. Sticky[math]tent is the first holistic work to use ownership-types to protect PI s from malware attacks. Some of the existing solutions follow static analysis of binary to identify the PI vulnerability. Through our empirical study using 23,922 apps, we found [math]17% of PI-based vulnerabilities leads to unauthorized access and privilege escalation, which can be solved by using Sticky[math]tent. We tested our model on the state-of-art applications and found an impressive harmonic mean (F1-score) value of 0.95–0.97 for intra and inter component analysis, which is 0.4–0.18 percentage more from the existing RAICC’s (a static analysis model instrumented with IccTA/Amandroid) result. As a proof-of-concept, we have taken a few real-world PI-based applications and replaced the PI with Sticky[math]tent library. By comparing the result with RAICC, we can see that Sticky[math]tent performs better in protecting PI dynamically from malware access. Though the proposed solution has an overhead of 0.005% per 5[math]min application test, the end-user suffers only negligible execution overhead in the screen response and notification delays.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-02T07:00:00Z
      DOI: 10.1142/S0218126622502243
       
  • Utility-Prioritized Differential Privacy for Quantitative Biomedical Data

    • Free pre-print version: Loading...

      Authors: Muqing He, Deqing Zou, Weizhong Qiang, Wenbo Wu, Shouhuai Xu, Xianjun Deng, Hai Jin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the context of heavy investments in life sciences, one consequence of rapid biotechnical developments is the generation of very large amounts of biological data that not only support bioinformatics research used in medical and health services by data analysis but also cause genetic privacy breaches for the data originators, limiting biomedical data sharing. However, the original intention of medical informatization is to improve medical efficiency and break the information barriers between medical institutions, which is also limited by genetic privacy risks from growing bioinformatics data. To share biomedical data correlated with genes usefully under the premise of ensuring genetic privacy, with the concept of medical reference interval, we design a query strategy based on a flexible differential privacy algorithm that setting weights for noise added according to the purpose of the inquirer. We generate a series of biomedical data to test the effectiveness of our query system, the test results show that our algorithm ensures data’s utility with acceptable privacy breaches that addresses the problem of biomedical data sharing to a certain extent.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-02T07:00:00Z
      DOI: 10.1142/S021812662250236X
       
  • Power and Noise Reduction of High-Frequency Variable Gain Amplifier

    • Free pre-print version: Loading...

      Authors: C. S. Sajin, T. A. Shahul Hameed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[math]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[math]GHz, while less than 0.78[math]mW is consumed from a 1.5-V supply. A noise figure of 23.7[math]dB is measured. Also, the VGA achieves a gain control range of 19[math]dB with a gain error less than [math][math]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-06-02T07:00:00Z
      DOI: 10.1142/S0218126622502437
       
  • A New Three-Level Design of Nano-Scale Subtractor Based on Coulomb
           Interaction of Quantum Dots

    • Free pre-print version: Loading...

      Authors: Qinghua Han, Mingdeng Shi, Bayan Omar Mohammed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The quantum-dot cellular automata (QCA) is popular nanotechnology to process at deep sub-micron levels. In recent years, in QCA technology, numerous multi-layer circuits of adders and subtractors have been developed. However, little attention has been made to the QCA circuit’s instantiation of the subtractors schemes. This paper gives a three-layered subtractor with simple access to inputs and outputs as an essential block in QCA technology. This design was created, optimized, and simulated using QCADesigner-E. The results revealed that the suggested proposal effectively reached a higher level of efficiency, speed, and cost, owing primarily to the use of the three layers’ design. Also, this architecture offers a platform to access the input and output lines more easily. The multi-layer crossover technique is used to build this design. According to the simulation findings, the suggested subtractor in QCA technology employs 22 QCA cells. The simulation findings demonstrated that the proposed design surpasses the majority of previous results in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-31T07:00:00Z
      DOI: 10.1142/S0218126622502371
       
  • Sub-10[math]pA/V Transconductance Amplifier Using 0.9[math]V, 32[math]nm
           Carbon Nanotube Field Effect Transistor

    • Free pre-print version: Loading...

      Authors: S. K. Tripathi, Amit M. Joshi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper attempts to propose a pico-A/V transconductance amplifier using carbon nanotube-FETs. It presents a [math] reduction technique which depends on the gain factor of the amplifier. The transconductance of 2.59 pico-A/V is achieved with the linear range of 766.8[math]mV.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-30T07:00:00Z
      DOI: 10.1142/S021812662220002X
       
  • High-Throughput and Power-Efficient Convolutional Neural Network Using
           One-Pass Processing Elements

    • Free pre-print version: Loading...

      Authors: B. Sivasankari, M. Shunmugathammal, Ahilan Appathurai, M. Kavitha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent decades, convolutional neural network (CNN) has become essential in many real-time applications due to its massive computational ability. But its use in portable devices is limited due to its high computation requirements. This paper proposes a novel One-Pass Processing Element (OPPE) to mitigate this limitation. The proposed OPPE removes redundant computations by eliminating those with zeros that leads to low area as well as low power consumption. The proposed OPPE model is evaluated with the help of VGG-16-based CNN accelerator. The proposed OPPE design reduces the number of four-input LUTs by 5.19%, 15.91%, 10.06% and 4.93% and the power consumption by 4.26%, 7.36%, 5.81% and 1.55% when compared with the conventional processing element (PE), activation gating PE, weight gating PE and zero gating PE, respectively. The proposed CNN accelerator design using OPPE achieves high throughput with less resource utilization.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-30T07:00:00Z
      DOI: 10.1142/S0218126622502267
       
  • Heuristic Analysis of Multiplierless Desensitized Half-Band Decimation
           Filter for Wireless Applications

    • Free pre-print version: Loading...

      Authors: A. Abinaya, M. Maheswari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper elucidates the half-band FIR filter, which plays an important role when applying decimation by a factor of two. When the down-conversion is applied in sampling rate, this digital filter is frequently employed in conjunction with down-samplers. Despite the fact that numerous approaches have been proposed for designing half-band FIR filters, this paper proposes an utterly unique method for designing and implementing multiplierless half-band FIR filters, which minimizes the coefficient sensitivity and also reduces hardware complexity of the conventional half-band FIR filter. The proposed desensitized and further desensitized multiplierless half-band FIR filters are analyzed with four high-speed parallel prefix adders in Xilinx Vivado development tool and built on Kintex 7 FPGA for exploring power consumption, number of LUTs and delay. The proposed half-band structure is compared with the classical half-band architecture with respect to power consumption, path delay and number of LUTs. Based on the attained results on Kintex 7 FPGA, the proposed low-sensitivity filter structure outperforms with a 41.09% reduction in the number of LUTs, a 11.91% reduction in delay and a 38.35% reduction in power consumption in contrast to the existing desensitized half-band filter. Subsequently, the proposed further desensitized filter provides a 4.87% reduction in stopband ripple than the desensitized structure and an 8.84% reduction than the existing half-band decimation filter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-30T07:00:00Z
      DOI: 10.1142/S0218126622502462
       
  • XSS Armor: Constructing XSS Defensive Framework for Preserving Big Data
           Privacy in Internet-of-Things (IoT) Networks

    • Free pre-print version: Loading...

      Authors: Pooja Chaudhary, B. B. Gupta, A. K. Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Big data characterizes superfluity of voluminous data that may be in unstructured, structured and/or semi-structured format. Internet of Things networks emerged as one of the biggest sources of big data, stored at the cloud servers. Thereby, it inflates the threats of security attacks such as cross-site scripting (XSS) for stealing the sensitive information and violates the user’s privacy. It leverages an adversary to intervene into user’s individual space. Thus, in this paper, we propose an XSS defensive framework, named as Big IoT Data XSS Armor, to protect user’s privacy in IoT networks. It is a server-side framework that mitigates nonpersistent and persistent XSS attack. Former attack is detected by measuring the similarities in request and response URL with the XSS attack strings. To identify persistent XSS attack, the proposed framework operates by unveiling the irregularities between the genuine features and generated features. The experimental outcomes yield that this framework performs efficiently in shielding against XSS attack and surpasses the detection rate of other existing XSS thwarting techniques because it attains an accuracy of 98.9% and F-measure of 98.4%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-23T07:00:00Z
      DOI: 10.1142/S021812662250222X
       
  • An Energy- and Reliability-Aware Task Scheduling in Real-Time MPSoC
           Systems

    • Free pre-print version: Loading...

      Authors: Mohammad Reza Saberikia, Hakem Beitollahi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Reliability and energy efficiency are two hostile objectives considered in designing task scheduling in most real-time multiprocessor systems on chip (MPSoC). Addressing and improving one of them may affect and degrade the efficiency of the other one and vice versa. In this paper, we intend to examine these challenges and ultimately achieve an optimal energy consumption and reliability state. This paper presents a novel scheduling technique that can adapt to the limitations of real-time systems and have optimal energy consumption and reliability. This is done by minimizing the overlap of tasks, adjusting the speed of processors and the number of backups of each task. The proposed scheme reduces energy consumption on average by 11% to 42% compared to the previous state-of-the-art techniques and keeps the reliability at a high level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502255
       
  • A Multi-objective Current Compensation Strategy for Photovoltaic
           Grid-Connected Inverter

    • Free pre-print version: Loading...

      Authors: Shengqing Li, Zhijian Wang, Wang Han
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper aims at resolving problems of harmonic, reactive power and current imbalance. In the process of photovoltaic grid connection, a multi-objective control strategy is proposed, in which the three-phase network controller simultaneously controls the harmonic and realizes the reactive power and current balance. The [math], [math] current detection method, which is based on the current reactive power characteristic theory, can detect the compensation current. In order to reduce the measurement error of PLL, a software PLL based on decoupled double synchronous reference coordinate transformation is introduced, and the principle of multi-objective rule of three-stage network inverter is also given. The simulation and test results show that the harmonic distortion rate decreases from 2.57% to 1.10% with the proposed strategy, and the unbalance between reactive power and current is compensated, which verifies the correctness and feasibility of the strategy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502309
       
  • Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust
           C-Elements

    • Free pre-print version: Loading...

      Authors: Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Glitch at the input can increase the power consumption of flip-flop greatly. To solve this problem effectively, a Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements (LARC) is proposed in this paper. The proposed Latch Multiplexer-A Double-edge Triggered Flip-flop (LARC-DET) can effectively block the glitch at the input and prevent the redundant transition at internal nodes. As a result, the extra power consumption caused by the glitch at the input is effectively reduced. The simulation was performed using HSPICE under 32[math]nm complementary metal oxide semiconductor (CMOS) process. The simulation results show that, compared with 12 double edge flip-flops, the proposed LARC-DET is the lowest in terms of power consumption and power delay product. Process voltage temperature (PVT) variation analysis shows its insensitivity to voltage variation, temperature variation and process variation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502310
       
  • Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET
           Technology

    • Free pre-print version: Loading...

      Authors: M. Elangovan, M. Muthukrishnan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502334
       
  • Mixed-Mode Electronically-Tunable First-Order Universal Filter Structure
           Employing Operational Transconductance Amplifiers

    • Free pre-print version: Loading...

      Authors: Ajishek Raj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-14T07:00:00Z
      DOI: 10.1142/S0218126622502346
       
  • A Framework for Wireless Sensor Network Optimization Using Fuzzy-Based
           Fractal Clustering to Enhance Energy Efficiency

    • Free pre-print version: Loading...

      Authors: Neha Sharma, Vishal Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor networks’ energy consumption is the major challenge to be handled. Clustering is one of the techniques majorly used for reducing energy consumption. During the course of time, many methodologies are being proposed and the existing ones are hybrid. Still, the energy can be reduced more. The scope of optimization is always there. Existing approaches either reduce energy consumption or work on routing or only on data gathering capabilities. But the technique proposed increases the lifetime of the wireless sensor network (WSN) by reducing energy consumption and improves routing efficiency. This paper proposes an approach based upon Fractal Clustering to improve the lifetime of the sensor nodes. The proposed approach named Enhanced Energy Efficient Fuzzy-based Fractal Clustering (EEFFC) algorithm optimizes the performance of WSN. First, fractal clustering is used on sensor nodes to find the location of the sensors. Then, a fuzzy inference system (FIS) is applied to results produced by fractal clustering. Applying FIS on cluster heads generated will optimize the results. As a result, the cost of data transmission will reduce, and hence, the lifetime of the network will improve. FIS generates multi-level clustering, which will result in a better routing path for sensor nodes. Hence, routing will also be improved. MATLAB 2020 is the simulation tool. The results of the simulation depict that EEFFC shows optimized results and it works better than LEACH, LEACH-SF, TEEN and DEEC. The energy consumption is being reduced by reducing the listening time of a node and by reducing the communication distance, for which clustering is optimized. The energy consumption has been reduced by 2% as compared to the algorithms it is compared with. Also, the node’s time of death has been delayed by 3% in total.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-13T07:00:00Z
      DOI: 10.1142/S0218126622502231
       
  • Random Interference Signal Decomposition and the Normalized Filtering
           Method of an Optical Fiber Current Transducer

    • Free pre-print version: Loading...

      Authors: Fubin Pang, Lihui Wang, Long Wan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Focusing on the problem of characteristic decomposition and filtering of random interference information measured by an optical fiber current transducer (OFCT), a signal filtering algorithm by combing complete ensemble empirical mode decomposition (CEEMD) with normalized autocorrelation function, is proposed. The CEEMD feature decomposition model of the OFCT signal is established and multiple eigenmode functions of the measured signal are extracted. The normalized autocorrelation function models of different types of intrinsic mode function (IMF) are established. By extracting the characteristics of the autocorrelation function, high-weight IMFs are selected. After the mean filtering process is performed on other IMFs, the signal reconstruction is performed together with the effective modal components. With the premise of signal statistical learning and structural risk minimization principles, a support vector regression model is established to classify the data by linear fitting. The more reliable current information after filtered is obtained. Experiment results demonstrate that the proposed signal filtering algorithm by combining the advantages of CEEMD and normalized autocorrelation function decomposes the signal according to the time-scale characteristics of OFCT data itself, without pre-setting any basis functions. The root mean square error of optimized data is reduced by 39.3%, and the signal quality is greatly improved.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-13T07:00:00Z
      DOI: 10.1142/S0218126622502292
       
  • Towards Fast and Accurate Federated Learning with Non-IID Data for
           Cloud-Based IoT Applications

    • Free pre-print version: Loading...

      Authors: Tian Liu, Jiahao Ding, Ting Wang, Miao Pan, Mingsong Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As a promising method of central model training on decentralized device data while securing user privacy, Federated Learning (FL) is becoming popular in the Internet of Things (IoT) design. However, when the data collected by IoT devices are highly skewed in a non-independent and identically distributed (non-IID) manner, the accuracy of the vanilla FL method cannot be guaranteed. Although there exist various solutions that try to address the bottleneck of FL with non-IID data, most of them suffer from extra intolerable communication overhead and low model accuracy. To enable fast and accurate FL, this paper proposes a novel data-based device grouping approach that can effectively reduce the disadvantages of weight divergence during the training of non-IID data. However, since our grouping method is based on the similarity of extracted feature maps from IoT devices, it may incur additional risks of privacy exposure. To solve this problem, we propose an improved version by exploiting similarity information using the Locality-Sensitive Hashing (LSH) algorithm without exposing extracted feature maps. Comprehensive experimental results on well-known benchmarks show that our approach can not only accelerate the convergence rate, but also improve the prediction accuracy for FL with non-IID data.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-13T07:00:00Z
      DOI: 10.1142/S0218126622502358
       
  • Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems
           — A Review

    • Free pre-print version: Loading...

      Authors: K. Aneesh, G. Manoj, S. Shylu Sam
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators, cochlear implants, visual prosthesis etc. have gained immense importance in the personal health monitoring system. Most of these devices are battery powered. The life span of a pacemaker is expected to be between 10 and 12 years. This shows the importance of having an ultra-low power design technique to improve the reliability and battery life of the system. To achieve this, power draws from the battery must be kept low. Analog-to-Digital Convertor (ADC) is a main block in the front-end sensing unit of an implant for measurements of various biophysiological signals. This is the most power consuming unit in the system. ADC alone consumes about 30%–35% of the total power. This work surveys various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit. The different switching schemes for capacitive DAC are also surveyed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622300094
       
  • Bug-Transformer: Automated Program Repair Using Attention-Based Deep
           Neural Network

    • Free pre-print version: Loading...

      Authors: Jie Yao, Bingbing Rao, Weiwei Xing, Liqiang Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a novel transformer-based deep neural network model to learn semantic bug patterns from a corpus of buggy/fixed codes, then generate correct ones automatically. Transformer is a deep learning model relying entirely on attention mechanism to model global dependencies between input and output. Although there are a few endeavors to repair programs by learning neural language models (NLM), many special program properties, such as structure and semantics of an identifier, are not considered in embedding input sequence and designing model effectively, which results in undesired performance. In the proposed Bug-Transformer, we design a novel context abstraction mechanism to better support neural language models. Specifically, it is capable of 1) compressing code information but preserving the key structure and semantics, which provides more thorough information for NLM models, 2) renaming identifiers and literals based on their lexical scopes, structural and semantic information, to reduce code vocabulary size and 3) reserving keywords and selected idioms (domain- or developer-specific vocabularies) for better understanding code structure and semantics. Hence, Bug-Transformer adequately embeds code structural and semantic information into input data and optimize attention-based transformer neural network to well handle code features in order to improve learning tasks for bug repair. We evaluate the performance of the proposed work comprehensively on three datasets (Java code corpora) and generate patches to buggy code using a beam search decoder. The experimental results show that our proposed work outperforms the-state-of-art techniques: Bug-Transformer can successfully predict 54.81%, 34.45%, and 42.40% of the fixed code in these three datasets, respectively, which outperform the baseline models. These success rates steadily increase along with the increase of beam size. Besides, the overall syntactic correctness of all patches remains above 97%, 96%, and 50% on the three benchmarks, respectively, regardless of the beam size.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622502103
       
  • Design and Implementation of Time-Frequency Distributions for Real-Time
           Applications Using Field Programmable Gate Array

    • Free pre-print version: Loading...

      Authors: B. Murali Krishna, B. T. Krishna, K. Babulu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, time-frequency distributions (TFDs) and their hardware implementation on FPGA are presented. TFDs are evolved due to disadvantage of Fourier Transform (FT), which cannot provide time information in spectrum representation. Time-Frequency Representations (TFRs) are helpful in providing simultaneous information about spectral contents of a signal with respect to time period axis. The major problem associated with hardware implementation of TFDs is limited on-board memory. Forward and backward register allocation method (FBRA) is employed to obtain the optimum register occupation. A register of length 32-bit is considered for the input signal representation. The stored register values are applied to the proposed TFDs and computed using real-time hardware. FBRA is implemented during the computation of FFT in all TFDs. All the transforms are modeled using Verilog code and implemented on SPARTA-6 FPGA. A real-time ECG, earthquake and a quad chirp signals are taken as input to test the designed TFDs. Finally, a comparison of different hardware resources utilized on FPGA with earlier conventional methods for better real-time applications was made.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622502176
       
  • Research on Short-Term Low-Voltage Distribution Network Line Loss
           Prediction Based on Kmeans-Lightgbm

    • Free pre-print version: Loading...

      Authors: Zhu Tang, Yuhang Xiao, Yang Jiao, Xinyu Li, Caixia Zhang, Jun Sun, Peng Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the lack of data quality in real production environment, the traditional line loss calculation method cannot be applied, thus through the investigation of various information systems’ operation in power supply enterprises, a short-term low-voltage distribution network line loss prediction algorithm based on Kmeans-LightGBM is proposed. Operating data quality evaluation system of low-voltage distribution network was set up based on Hadoop platform, the feature dimensions were expanded by feature engineering, then those with no multicollinearity and high correlation with the line loss were selected, data normalization was again performed, Kmeans clustering algorithm was used to cluster the area and then, LightGBM algorithm was used to predict the classes within the area of line loss. Finally, the line loss of the numerical inverse normalization was found and validated with Beijing Power Grid of a low-voltage distribution network. By comparison, the model’s prediction accuracy is found to be higher than BPNN, FOA-SVR and traditional LightGBM.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622502280
       
  • Mathematical and Circuit Level Analysis Interpretation and Recommendations
           on Neuron Models

    • Free pre-print version: Loading...

      Authors: I. Munavar Sheriff, R. Sakthivel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Contrary to von Neumann computer architecture, neuromorphic computing is a biologically inspired method for building several sorts of brain-inspired computers. This computer technology uses silicon neurons and synapses to solve difficult machine learning and AI challenges. The goal of neuromorphic computing is to build a brain-like ability to compute, learn, and adapt. Building an appropriate neuroscience model, establishing a new architecture, modeling new devices, finding new materials for the devices, programming framework, and applications for these neuromorphic devices are major technological challenges. This study covers numerous neuron models from Hodgkin–Huxley to I&F, mathematical equations, circuit level analysis and motivations for neuromorphic computing. Here some of the most useful silicon neuron models are discussed in terms of biological plausibility, computational efficiency, and temperature dependency. This survey shows that more than 52 transistors make up the silicon HH neuron, which occupies less than 0.01[math][math] and consumes 60[math]uW of power. On the other hand, an I&F neuron needs less than 20 transistors, occupies 442[math][math] and consumes 40[math]pW of power.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-07T07:00:00Z
      DOI: 10.1142/S0218126622300082
       
  • A Multiserver Configuration and Request Distribution Framework for Profit
           Maximization in a Three-Tier Cloud Service Architecture

    • Free pre-print version: Loading...

      Authors: Tian Wang, Mingyue Zhang, Wei Shen, Linli Xu, Gongxuan Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The rapid development of cloud computing has generated numerous cloud service providers. In a three-tier cloud service architecture, maximizing the cloud service profit is not only a goal pursued by cloud service providers but also a potent force that drives the continuous development of cloud computing technology. The traditional methods of maximizing cloud service profits are either limited to cloud resource management or service request distribution. Few work contributes to maximizing the profit of cloud service providers while considering both resource management and request distribution. Besides, the heterogeneity of servers is also an important concern when configuring the multiserver system. Therefore, this paper proposes a multiserver configuration and request distribution framework oriented to a three-tier cloud service architecture for maximizing the profit of cloud service providers. Compared with the benchmark method, extensive numerical simulation experiments show that our proposed framework can not only maximize the profit of cloud service providers, but also has a well-time efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-30T07:00:00Z
      DOI: 10.1142/S0218126622502218
       
  • LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area
           for Network-on-Chip Architectures

    • Free pre-print version: Loading...

      Authors: Anil Kumar, Basavaraj Talawar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from [math] to [math] are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is [math] to [math] with respect to BookSim simulator.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-29T07:00:00Z
      DOI: 10.1142/S0218126622501961
       
  • An Underground Abnormal Behavior Recognition Method Based On An Optimized
           Alphapose-ST-GCN

    • Free pre-print version: Loading...

      Authors: Xiaonan Shi, Jian Huang, Bo Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the complex underground environment of coal mines, the unsafe behaviors of miners are likely to lead safety accidents. Therefore, research on underground abnormal behavior recognition methods based on video images is gradually gaining attention. This paper proposes an underground abnormal behavior recognition method based on an optimized Alphapose-ST-GCN. First, an image set captured in underground monitoring video is defogged and enhanced by the CycleGAN. Second, the Alphapose target detection is optimized using the LTWOA-Tiny-YOLOv3 model. Third, the ST-GCN is used for abnormal behavior recognition. The image quality of the dataset before and after a CycleGAN enhancement is compared, the convergence curves of LTWOA under four test functions are compared, and the mean average accuracy mAP of the LTWOA-Tiny-YOLOv3 model is evaluated. Finally, the performance of the proposed method is compared with other detection algorithms. The results show that CycleGAN significantly improves the quality of the dataset images. The whale optimization algorithm improved by the logistic-tent chaos mapping has a more significant convergence effect than the other optimization algorithms, and the LTWOA-Tiny-YOLOv3 model has a better recognition accuracy of 9.1% in mAP compared with the unoptimized model. The underground abnormal detection model proposed in this paper achieves an 82.3% accuracy on the coal mine underground behavior dataset.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-29T07:00:00Z
      DOI: 10.1142/S0218126622502140
       
  • Temporal Sequence of Data Fluctuation-Based Approach for Tor Program
           Classification

    • Free pre-print version: Loading...

      Authors: Hao Zhang, Weidong Zhang, Wei Zhao, Xuangou Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the continuous development of encryption technology, the share of encrypted traffic in the network is increasing, which brings great challenges to the traditional methods of rule-based traffic identification. Deep learning is becoming an inspiring methodology to solve the problem. Previous studies have confirmed that time characteristics play an important role in Tor traffic classification. We find that there is a similarity of time characteristics among different programs. This paper proposes an end-to-end classification framework: the temporal sequence of data fluctuation network (TSDFN). It first extracts the temporal sequence of data fluctuation in the original flow and then uses the GRU network to learn the hidden temporal features. Experiments on public data sets validate the effectiveness of our proposal over other methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622400023
       
  • Learning-Based Health Prediction Method for Airborne DME Receiver with
           Signal Processing Techniques in 6G Networks

    • Free pre-print version: Loading...

      Authors: Yuhao Zhong, Guocheng Yang, Hua Xu, Xue Qin, Dajiang Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Accurate aircraft positioning is the key to construct a reliable network topology when aircrafts are used to assist 6G cellular networks in ground communications. Distance Measuring Equipment (DME) has been widely used in aircraft positioning with the help of multiple ground-based radar stations. In this paper, a learning-based health prediction method for airborne DME receiver is proposed by using signal processing techniques to achieve quantitative health status assessment and failure degradation trend prediction, when the DME is used to measure the distance between ground-based radar stations and airborne DME. First, a quantitative airborne DME device receiving channel health evaluation model is established, which takes the Automatic Gain Control (AGC) attenuation value and the collected distance between the ground beacon station and the airborne DME receiver with DME device as input, to calculate the receiving channel AGC attenuation value deviation and gain loss. The model can be used to build the mapping relationship between the receiver channel gain loss and the DME function range, and further establish the calculation model of the receiving channel’s health index. Second, a multi-model fusion fault prediction framework based on the Deep Belief Network (DBN) techniques is proposed. In this framework, the problem of insufficient generalization and robustness of the traditional DBN model is solved by introducing the Dropout mechanism into the DBN structure, and an improved weighted voting method is utilized as a model fusion algorithm to eliminate the deviation of prediction results caused by environmental load differences and improve the accuracy of fault prediction. Finally, extensive experiments are conducted to show the feasibility of the proposed method, and the results show that the proposed method has a good performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502073
       
  • A Gated Convolution and Self-Attention-Based Pyramid Image Inpainting
           Network

    • Free pre-print version: Loading...

      Authors: Hong-an Li, Guanyi Wang, Kun Gao, Haipeng Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Aiming at the problems of imperfect inpainting edges, mismatching inpainting content and slow training caused by large network model parameters and high requirements for image inpainting edge consistency and semantic integrity, this paper designs a gated convolution and self-attention-based pyramid network (GAP-Net), the network is based on U-Net, and it integrates the gated convolution method and the pyramid loss and changes the feature extraction strategy. In addition, we design a self-attention mechanism module and an attention transfer module for the network, designing and adding content loss and perceptual loss for the network, generating a new data distribution between generated and real images. The comparative analysis of experiment with the PEN-Net method and the Gated method is conducted in the same experimental environment. The experimental results show that our method can increase the extraction of useful information from damaged image areas by gated convolution and pyramid loss. Self-attention mechanism module and the attention transfer module can guide the conversion process of high-level semantic features to image information more accurately, and the content and perceptual loss can accelerate and improve the learning ability of the network, this method improves the repair effect and accelerates the network learning speed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502085
       
  • Image Inpainting Based on Contextual Coherent Attention GAN

    • Free pre-print version: Loading...

      Authors: Hong-an Li, Liuqing Hu, Qiaozhi Hua, Meng Yang, Xinpeng Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to address the problems of traditional inpainting algorithm models, such as the inability to automatically identify the specific location of the area to be restored, the cost of inpainting and the difficulty of inpainting, and the problems of structural and texture discontinuity and poor model stability in deep learning-based image inpainting, this paper proposes an image inpainting based on a contextual coherent attention. This paper designs a network model based on generative adversarial networks. First, to improve the global semantic continuity and local semantic continuity of images in image inpainting, a contextual coherent attention layer is added to the network; second, to solve the problems of slow convergence and insufficient training stability of the model, a cross-entropy loss function is used; finally, the trained generator is used to repair images. The experimental results are compared using PSNR and SSIM metrics, compared with the traditional GAN model, our model has a 3.782dB improvement in peak signal-to-noise ratio and a 0.025% improvement in structural similarity. The experimental results show that the image inpainting method in this paper has better performance in terms of image edge processing, pixel continuity and overall image structure.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502097
       
  • Application Optimization of Cloud Management Mode in Information
           Technology in Sudden Social Security Incidents

    • Free pre-print version: Loading...

      Authors: Haining Huang, Lihua Xu, Haomin Lu, Zhencheng Lin, Wei Yan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the change of social structure and management mode, emergency social security incidents have become the focus of social security management. In order to solve the problems of insufficient overall performance and low security in the practical application of cloud management mode in traditional social security emergencies. With the use of improved pick-KX load balancing algorithm and RSA encryption algorithm, this paper optimizes the cloud computing model and applies it to the cloud management mode of emergent social security events. Then the optimized cloud management model is simulated and evaluated by the multi-level fuzzy comprehensive evaluation model. The simulation results reflect that the proposed cloud management model in this paper is able to effectively improve the management effect of social security events.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502127
       
  • Clustering-Based Semi-Supervised Cross-Modal Retrieval Using Scene Graph

    • Free pre-print version: Loading...

      Authors: Yixue Kong, Yong Feng, Mingliang Zhou, Xiancai Xiong, Yongheng Wang, Baohua Qiang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a clustering-based semi-supervised cross-modal retrieval method to relieve the problem of insufficient annotation in cross-modal datasets. First, we reconstruct cross-modal data as scene graph structure to filter meaningless information. Second, we extract embedding representation features of images and texts to put them into a common space. Finally, we propose a clustering-based classification method with modality-independent constraint to discriminate samples. According to our experimental results, significant improvement on performance shows the accuracy of our method in terms of three widely used cross-modal datasets compared with the state-of-the-art methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502139
       
  • The Industrial Internet of Things (IIoT): An Anomaly Identification and
           Countermeasure Method

    • Free pre-print version: Loading...

      Authors: Usman Tariq, Tariq Ahamed Ahanger, Atef Ibrahim, Yassine Saleh Bouteraa
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Networked devices benefit enterprises to gain far-reaching control over their industrial processes, which encourages them to conduct routine operations in a smart manner. Rapidly expanding interconnected sensor devices are eligible to aggregate, process and disseminate wide-ranging data. This paper proposed an extended anomaly discovery and response framework. We argued the prospective security anomalies to the IoT equipped industrial-floor and examined the numerous attacks that are conceivable on the modules in the Industrial Internet of Things (IIoT) architecture. IIoT service layer architecture was designed in consideration of high-volume device connectivity, management and security enforcement. Collection of geospatial service and device data aided the proposed framework to bridge the gap between anomaly identification and context-aware node behavior. Framework evaluation considered design principles such as node interpretability, decentralization, real-time data relay, modularity and required service alignment. Emulation outcomes specify that the malware discovery performance is better if the anomaly recognition model used the applied utility for the yield layer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S021812662250219X
       
  • A Dynamic Load Balancing Algorithm for IoV CoMP Communications

    • Free pre-print version: Loading...

      Authors: Derong Du, Linlin Jiang, Tan Guo, Lingqian Wu, Long Li, Xiaoping Zeng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to uneven space–time distribution of vehicles, Internet of Vehicles (IoV) has problems with load imbalance and low resource utilization of Base Stations (BSs) in the Coordinated Multi-Point (CoMP) communication scenario. This paper proposes a dynamic load balancing algorithm based on vehicle prediction. It is assumed that the number of vehicles arriving at the BSs obeys the segmented Poisson distribution to determine the current and predicted load statuses of BSs. First, analyze the load status of each BS and the location of users (vehicles). Then, screen out BSs whose load below the full load threshold as a switchable low-load cooperative cluster, which can convert interference signals into useful signals and reduce the interference between adjacent BSs. Finally, complete load balancing by redistributing the communication service of edge users through sharing channel information and user date among coordinated BSs. Because IoV is a dynamic network, the proposed algorithm runs dynamically in cycles. Simulation results show that the algorithm can perform balance the load of BSs well, the overload rates of BSs during the traffic off-peak period and peak period are reduced significantly, and the average information rate of users is greatly improved.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502206
       
  • A Magnetically Coupled-Inductor Boost Converter with High Bandwidth and
           Fast Dynamic Response

    • Free pre-print version: Loading...

      Authors: Alireza Goudarzian, Ehsan Adib
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Transient modeling analysis of the traditional DC/DC converters shows their worse effect of nonminimum-phase characteristics due to right-half-plane (RHP) zero existence in their plant transfer function. This RHP zero restricts the bandwidth of the switching converters and, that is the main reason for slower response. The motivation of this paper is to present a new technique for eliminating the RHP zero from the dynamics of a conventional boost converter that can solve the problems associated with the nonminimum phase converters and, to focus on its analysis, design and modeling to achieve a high voltage gain as well as the RHP zero cancellation. The proposed technique uses a transformer combined with switching capacitor cells. The striking feature of the suggested topology is its minimum-phase structure, further enhancement of the voltage gain, switching stress reduction, achievement of an improved frequency response and easiness for the design of a closed-loop control scheme to perform the voltage trajectory tracking task. First, the operation of the proposed converter is identified and then, the corresponding circuit performance is evaluated. By using a suitable design, the control-to-output-voltage transfer function is completely free from the RHP zero. The significant advantages of the proposed converter are established via comparisons. To confirm the design approach and theoretical findings, the simulations are introduced and, numerical experimental results such as Bode diagrams are presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S021812662250205X
       
  • Neuron Network with a Synapse of CMOS transistor and Anti-Parallel
           Memristors for Low power Implementations

    • Free pre-print version: Loading...

      Authors: V. Keerthy Rai, R. Sakthivel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The bio-mimetic structure of a neuron is taken into account for utilizing the electrophysiological data. These neuron circuits are entertained for the use in digital computers. At the end of Moore’s law, conventional technology is striking different difficulties, such as power consumption, area utilization, and energy efficiency. To conquer these hurdles, a nanoscale, the nonvolatile memristor used in the proposed neuron modified from the refined AH neuron. Synapses are also built using anti-parallel memristors. These neurons and synapse are joined together such that the performance metrics are analyzed the energy consumption is reduced by 89.656%. Besides, power consumption is limited by 37.568% and the spike frequency is measured as 10.263[math]kHz when compared with the traditional CMOS synapse connected with the proposed neuron. Moreover, the measured energy per spike is 3.37[math]fJ. The implementation of the neuron network is done by 45[math]nm technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S0218126622502061
       
  • Blind Image Inpainting Using Low-Dimensional Manifold Regularization

    • Free pre-print version: Loading...

      Authors: Mei Gao, Baosheng Kang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a novel method for blind image inpainting, which can restore images with missing or corrupted pixels, or images where the location of the damaged pixels is unknown. The method applies weighted nonlocal Laplacian to address the problem of blind image inpainting using low-dimensional manifold model (LDMM) regularization, and uses semi-local blocks instead of point integrals to implement constraints in LDMM. This solves the problem of low solution efficiency caused by the asymmetry of the linear equations solved by point integration, and the problem of the high iteration count to get good restoration effect. Experiments show that our method is competitive with latest methods in terms of both repairing images with large missing pixels rate and inpainting speed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S0218126622502115
       
  • Bifurcation Fusion Network for RGB-D Salient Object Detection

    • Free pre-print version: Loading...

      Authors: Zhi-Hua Zhao, Li Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of sensor technology, multi-modal data fusion methods based on deep neural networks provide a reliable guarantee for object recognition and detection in complex scenarios. Most of the existing RGB-D image salient object detection methods improve the salient object detection methods in 2D scenes, which have many problems, such as ineffective fusion of feature information, incomplete image feature extraction and so on. Aiming at these problems, we proposed a salient object detection method based on bifurcated fusion network. First, we use the high- level features of the global context to locate the salient object, then we use the low-level features of the local details to extract the edge information. Second, we model the RGB information and depth information through the gate channel transformation control mechanism, and construct the bifurcation backbone network model and generate the initial salient map. Finally, based on the initial salient map and low-level features, the final salient map is generated. Experimental results show that the proposed method can fully utilize the multi-layer feature information of the image and effectively detect the salient object.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S0218126622502152
       
  • Analysis and Design Optimization of a 2-Path Sigma Delta Modulator

    • Free pre-print version: Loading...

      Authors: Reyhaneh Barzegar, Hossein Miar Naimi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new design for the optimization of analog to digital sigma delta-coupling noise annotations. The proposed technique increases the level of the signal-to quantization-noise-ratio (SQNR) by improving the zero of the noise transfer function, which leads to an increase in signal to noise. In the new SQNR design, the modulator rises up to 8.5 db. The proposed structure of the first-order dual-channel sigma-delta modulator is also presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-20T07:00:00Z
      DOI: 10.1142/S0218126622502036
       
  • A Compact Planar Multi-Resonant Multi-Broadband Fractal Monopole Antenna
           for Wi-Fi, WLAN, Wi-MAX, Bluetooth, LTE, S, C, and X Band Wireless
           Communication Systems

    • Free pre-print version: Loading...

      Authors: Ibrahime Hassan Nejdi, Sudipta Das, Youssef Rhazi, Boddapati Taraka Phani Madhav, Seddik Bri, Mustapha Aitlafkih
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a highly efficient tree-shaped fractal antenna with multi-broadband resonance characteristics is proposed. The proposed antenna exhibits broad operating bandwidth, high gain, and high efficiency characteristics due to the suggested modifications in the antenna geometry. The suggested circular patch is modified by introducing slots in the form of a tree-shaped fractal structure, and the partial ground plane is modified by incorporating a narrow rectangular slot. The proposed antenna is designed on an FR4 substrate of [math][math]mm3. The prototype of the proposed antenna has been fabricated and tested to justify the simulation results. The measurement results are in good agreement with the simulation that validates the multi-broadband design approach of the proposed fractal antenna. As per the measurement results, the proposed antenna operates at four distinct bands with [math]10[math]dB impedance bandwidths of 600[math]MHz (2.2–2.8) GHz, 1070[math]MHz (3.3–4.37) GHz, 2550[math]MHz (4.75–7.3) GHz, and 2200[math]MHz (9.7–11.9) GHz. Furthermore, a high peak gain of 10.23[math]dB and a peak radiation efficiency of 96.65% are recorded for the suggested fractal antenna. The suggested compact bandwidth enhanced multi-band antenna can be useful for several wireless communication systems such as wireless fidelity (Wi-Fi), wireless local area network (WLAN), Bluetooth, long-term evolution (LTE), C, S and X bands.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-20T07:00:00Z
      DOI: 10.1142/S0218126622502048
       
  • Wireless Multimedia Sensor Network QoS Bottleneck Alert Mechanism Based on
           Fuzzy Logic

    • Free pre-print version: Loading...

      Authors: Achyut Shankar, K. Sumathi, P. Pandiaraja, Thompson Stephan, Xiaochun Cheng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless Multimedia Sensor Networks (WMSNs) are mostly affected by bottleneck issues, high packet loss, increased delay, and minimum throughput. One of the most effective schemes towards controlling the bottleneck on the web is traffic control. The WMSNs handle different types of data, hence QoS is essential to afford trustworthy as well as reasonable services towards these kinds of data. The existing congestion control methods, FTLP and FEWPBRC consider the frequency of packet transmission and decide on the output transmission rate of the sink. In the Fuzzy-Based QoS Alert Bottleneck Mechanism, the probability of congestion is predicted by using a fuzzy inference system with three special congestion indicators, and the traffic rate is adjusted based on the priority of the real-time and non-real-time applications. The FBQACC is simulated using the NS2 simulator and it gives an improvement in the average throughput FTLP and FEWPBRC by 7.1499% and 6.3327%, respectively. Similarly, FBQACC reduces average delay compared to FTLP and FEWPBRC by 11.074% and 7.8128%, respectively. The proposed work also gives a minimized average packet loss percentage compared to the existing congestion control methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-18T07:00:00Z
      DOI: 10.1142/S0218126622501985
       
  • Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide
           Reliability

    • Free pre-print version: Loading...

      Authors: Dharmaray Nedalgi, Saroja V. Siddamal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a [math] tolerant I/O buffer with low voltage (VDD) devices. A novel bootstrap circuit for mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and gate oxide reliability issues. The proposed circuit is designed using 1.8[math]V thick gate devices in 22-nm FinFET technology with 1.8[math]V signaling and tolerant to 3.3[math]V. The structure can be used in any CMOS technology for [math] tolerant I/O buffer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-18T07:00:00Z
      DOI: 10.1142/S0218126622502024
       
  • Artificial Intelligence in the Auxiliary Guidance Function of Athletes’
           Movement Standard Training in Physical Education

    • Free pre-print version: Loading...

      Authors: Zhenzhen Su
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Artificial Intelligence (AI) is a new technical science that studies and develops theories, methods, techniques and application systems for simulating, extending and expanding human intelligence. This paper is based on the research of AI in the auxiliary guidance function of athletes’ standard training in physical education. It aims to conduct data mining from different aspects such as different joint angular speeds, motion injury screening and different parts of sports injuries and then integrate these aspects. Create a way to reduce athletes’ injuries and scientific training. In order to improve the recognition efficiency of athletes’ movement patterns, nonlinear auto regressive neural networks are used to recognize the movement patterns of athletes’ limb surface signals. Through this research work, it can provide a certain reference basis and practice platform for the research on the auxiliary guidance role of AI in the sports standard training of athletes in physical education. Performance design and implementation include four modules: Image acquisition, preprocessing, motion detection and human motion recognition. Between them, the image acquisition module uses a memory mapping path to determine the format of the camera frame image, and the image format conversion is completed through channel conversion. Experimental data shows that athletes’ strength quality, speed of action response, technical continuity, psychological stability and physical control ability have all been greatly improved. Among them, the most obvious is that with the assistance of AI technology, the psychological stability has reached 9.2; the strength quality has reached 9.1.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S0218126622400011
       
  • Analysis of Injection Locking in Ring-Based Divide-By-Two Frequency
           Dividers

    • Free pre-print version: Loading...

      Authors: Lazhar Fekih-Ahmed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we introduce a unified nonlinear injection locking model of a large class of 1:2 frequency dividers. The model is valid for two-stage dividers, injected with two-phase or single-phase current or voltage sources. We show that this class of dividers can be rigorously analyzed using the theory of planar nonlinear dynamical systems. We provide accurate compact expressions for the locking range, amplitude, frequency and phase noise. The formulas are validated for two types of frequency dividers using simulations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S021812662250195X
       
  • Identity Authentication Based on Music-Induced Autobiographical Memory EEG

    • Free pre-print version: Loading...

      Authors: Xin Xu, Lan Jiang, Tingting Xu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The need for identity authentication has become essential in various aspects of people’s life. In this paper, we propose a novel biometric authentication strategy based on music-induced autobiographical memory electroencephalogram (EEG). Specific music is used to induce the stable autobiographical memory, while the EEG signals are collected through the memory process. Users can authenticate themselves by recollecting their minds when listening to the music, which is closely related to their long-term memory. Based on six types of EEG features from 12 subjects, mean F1 score of 0.937, 0.936 and 0.968 are achieved using Logistic Regression, Support Vector Machine and RUSBoost classifier, respectively. This promising result indicates the high distinctive characteristics in music-induced autobiographical memory EEG, which is suitable for identity authentication applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S0218126622502012
       
  • A PFC Scheme for the Inverse Watkins Johnson Converter for Polarity
           Reversible Buck Boost DC Output Voltage

    • Free pre-print version: Loading...

      Authors: V. Jothi Arulkumar Austin, A. Ravi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A power factor correction (PFC) scheme for the Inverse Watkins Johnson Converter (IWJC) drawing power from a single-phase AC source, delivering polarity reversible DC voltage output is presented in this paper. The IWJC is basically a DC-to-DC converter which can deliver a boosted positive output voltage or a negative output voltage with buck or boost feature. It is suitable for driving DC loads, typically, DC motors in forward or reverse direction. Unlike the conventional four quadrant DC chopper, the IWJC can boost the input voltage and deliver a voltage higher than the source voltage with duty cycle controlled polarity reversible feature. This paper presents the methodology of including a PFC strategy for the IWJC, when fed from a single-phase AC supply. The proposed methodology has established that the AC source side power factor is unity and that the source current is maintained sinusoidal. Simulations and experimental verifications validate the proposed idea.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-11T07:00:00Z
      DOI: 10.1142/S0218126622501997
       
  • Mathematical Modeling of Buck Converter with Relay Feedback

    • Free pre-print version: Loading...

      Authors: R. Ramaprabha, Anjana Ethirajan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes the idea of mathematical modeling of the buck converter. The modified approach is achieved through the relay feedback (RF) method and the changes are introduced on the converter output with a soft start. Mathematical modeling of the buck converter is achieved by the state-space model (SSM) and converter’s transfer function (TF) to attain stability. By iteration, the proportional-integral (PI) parameters are tuned by a controller that is incorporated in the RF. The output voltage changes are introduced by maintaining the relay-tuned PI control. The concept requires small tuning times which is obtained at a reduced cost. The effectiveness of buck converter using RF is validated in simulation and hardware.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-09T07:00:00Z
      DOI: 10.1142/S0218126622501912
       
  • TCA: Telecom Credit Assessment Assisted by Edge Intelligence

    • Free pre-print version: Loading...

      Authors: Hao Hu, Xu Du, Feier Qiu, Shiwei Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With China’s economic transformation into a high-quality development stage, the importance of credit system construction has become increasingly prominent. The problems existing in the current telecom credit system include: (1) insufficient coverage of credit features; (2) traditional credit assessment models are difficult to reflect user credit status objectively, comprehensively and timely; (3) user demand for credit management and credit services are ignored. Due to these deficiencies, a new multi-level credit system is necessary to meet the rapid development of market economy. Telecom operators have large amount of precious data, with the advantages of large-scale, high-precision and data-diversity, which can provide new ideas for the construction of credit system. This work focuses on the current problems and conducts research as follows: design a Telecom Credit Assessment Model based on Boosting and Stacking ensemble techniques, called TCAMBS, to improve the evaluation accuracy, and to select the best model according to the experimental results. On the one hand, this work can promote the innovation of telecom credit assessment models and provide new ideas for the construction of the credit system. On the other hand, this work will also help telecom operations to improve the quality of telecom credit services.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-08T07:00:00Z
      DOI: 10.1142/S0218126622501973
       
  • High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid
           PTL/CMOS Logic

    • Free pre-print version: Loading...

      Authors: Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-08T07:00:00Z
      DOI: 10.1142/S0218126622502000
       
  • A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery
           Circuit

    • Free pre-print version: Loading...

      Authors: Shuxiang Song, Zefa Liu, Mingcan Cen, Chaobo Cai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5[math]Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector’s phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit’s total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40[math]nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5[math]Gb/s. With a pseudo-random bit sequence (PRBS) of [math], the measured result shows that the bit error rate (BER) is [math], and the root mean square jitter recovered in the output is 0.302 [math]. The circuit’s jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8[math]mW with a 5.98[math]pJ/bit energy efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-04T07:00:00Z
      DOI: 10.1142/S0218126622501900
       
  • Tree-Like Branching Network for Single Image Super-Resolution with
           Divide-and-Conquer

    • Free pre-print version: Loading...

      Authors: Ying Zhao, Zeliang Zhao, Kun Shao, Shu Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a tree-like branching network for image super-resolution. Specifically, the network consists of information divide-and-conquer groups (IDCG) to preserve the low-frequency structure of images as well as restore high-frequency information. The kernel of IDCG contains several essential components: (a) a simple attention module and an effective residual attention module to maintain low-frequency structures and restore high-frequency information, (b) a novel local merge cell alleviates information redundancy that flexibly and adaptively fuses multiple informative features from different states. Lastly, a multi-scale aggregation unit is designed to improve the final reconstruction. Through a series of experiments, we prove that our method is more effective than previous state-of-the-art results in both quantitative and qualitative evaluation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-01T07:00:00Z
      DOI: 10.1142/S0218126622501924
       
  • Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS
           Technology

    • Free pre-print version: Loading...

      Authors: Dina M. Ellaithy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-01T07:00:00Z
      DOI: 10.1142/S0218126622501936
       
  • Short-Term Load Forcasting for Smart Power Systems Using Swarm
           Intelligence Algorithm

    • Free pre-print version: Loading...

      Authors: N. Prakash, B. Vaikundaselvan, S. S. Sivaraju
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to succeed in our everyday life, efficient performance of the power system is of utmost importance, and hence, all the sub-sectors of the power system should be analyzed for the purpose of achieving efficiency and accuracy. It must also be remembered that load forecasting assists a lot to improve the power system. Moreover, it contributes substantially to formulate logical approaches for emerging short-term load forecasting (STLF) for all days including the distinct days and make them follow a uniform standard. Of all the techniques which have been applied so far, honey bee-optimized Euclidean norm, based on fuzzy inference system, is used for identifying the problems, and in addition, support vector classifier is utilized to prepare the STLF models. Parameters — temperature, humidity, monsoons, wind, cloud density, dew point, season, hour of the day, day of the week, distinct day, and holiday — have been taken into account for the current study. A well-prepared database can be used for regression which will be of immense help to forecast the load using artificial intelligence. For every day of a month, the MAPE is computed (using the forecasted and actual hourly values) in order to observe the accuracy of STLF. The planned method has been very successful for the load forecast of all days for all seasons. The forecast has been done using the technique for a real time data of one year (test forecast year) with a historical dataset collected for a period of two years, and the results obtained for all seasons have been found to be satisfactory. STLF has helped to find better values due to its pace, and become healthier than other methods already in practice. With the advent of smart grid, the data will be accessible at more granular level as smart meters have capability to provide consumer load, usage data on-line and this facility will be of great help to utility operators and planners for operations on-line. How to use the data available from smart meters for better STLF is a challenging task and it would draw much attention for future research.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-30T07:00:00Z
      DOI: 10.1142/S0218126622501894
       
 
JournalTOCs
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Email: journaltocs@hw.ac.uk
Tel: +00 44 (0)131 4513762
 


Your IP address: 18.204.56.185
 
Home (Search)
API
About JournalTOCs
News (blog, publications)
JournalTOCs on Twitter   JournalTOCs on Facebook

JournalTOCs © 2009-