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Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [121 journals]
  • Lightweight CNN-Based Image Recognition with Ecological IoT Framework for
           Management of Marine Fishes

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      Authors: Lulu Jia, Xikun Xie, Junchao Yang, Fukun Li, Yueming Zhou, Xingrong Fan, Yu Shen, Zhiwei Guo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the development of emerging information technology, the traditional management methods of marine fishes are slowly replaced by new methods due to high cost, time-consumption and inaccurate management. The update of marine fishes management technology is also a great help for the creation of smart cities. However, some new methods have been studied that are too specific, which are not applicable for the other marine fishes, and the accuracy of identification is generally low. Therefore, this paper proposes an ecological Internet of Things (IoT) framework, in which a lightweight Deep Neural Networks model is implemented as a image recognition model for marine fishes, which is recorded as Fish-CNN. In this study, multi-training and evaluation of Fish-CNN is accomplished, and the accuracy of the final classification can be fixed to 89.89%–99.83%. Moreover, the final evaluation compared with Rem-CNN, Linear Regression and Multilayer Perceptron also verify the stability and advantage of our method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-25T08:00:00Z
      DOI: 10.1142/S0218126623501694
       
  • High Selectivity, Dual-Mode Substrate Integrated Waveguide Cavity Bandpass
           Filter Loaded Using CCSRR

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      Authors: N. Praveena, N. Gunavathi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a third-order, high selectivity Substrate Integrated Waveguide (SIW) bandpass filter (BPF) loaded with Circular Complementary Split-Ring Resonator (CCSRR) is proposed for C band applications. The SIW cavity BPF comprises two stepped resonators ([math] and [math]) and one CSRR ([math]) engraved on the top metal plate. Initially, the cavity loaded with stepped resonators ([math] and [math]) alone does not make a good selectivity on the lower out of band. Hence, the CCSRR is introduced between the stepped resonators ([math] and [math]) to improve the filter’s selectivity and enhance the filter’s bandwidth. The introduction of CCSRR enhances the selectivity on the lower out-of-band at 5.5[math]GHz, and the extra pole increases the bandwidth. The metamaterial behavior of CCSRR is validated by permittivity extraction. The 3[math]dB bandwidth of the third-order SIW filter is 840 MHz with a center frequency of 6.18[math]GHz. The designed filter uses RTDuroid 5880 substrate of [math] = 2.2 with a size of 28.4 [math] 28.4 [math] 0.51[math]mm3. The proposed filter measurement and simulated results agree with each other.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-25T08:00:00Z
      DOI: 10.1142/S0218126623501906
       
  • THD Minimization and Reliability Analysis of Cascaded Multilevel Inverter

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      Authors: R. Kavitha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Inverters are DC to AC power converters that are widely used in AC motor drives and distributed energy generation systems. Multi-Level Inverters (MLIs) have emerged as the preferred inverter technology because of their advantages of reduced switching losses and better harmonic profile. This paper deals with the Minimization of Total Harmonic Distortion (MTHD) of Symmetric Cascaded H-bridge Multi-Level Inverter (SCMLI) and Asymmetric Cascaded H-bridge Multi-Level Inverter (ACMLI). A hybrid memetic algorithm composed of heuristic PSO (Particle Swarm Optimization) algorithm and traditional MAS (Mesh Adaptive direct Search) is proposed to optimize the switching angles. In Photo Voltaic (PV) system, the input DC voltage generally varies from its nominal value due to the change in temperature and irradiance. Thus, the sensitivity analysis of THD and harmonics is also carried out considering the variations with non-integer magnitudes of input DC sources. The experimental prototype of SCMLI and ACMLI topology is developed and validated with simulation results. The reliability and Mean Time to Failure (MTTF) of SCMLI and ACMLI are investigated based on power losses of the MOSFET and thermal parameters.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-18T08:00:00Z
      DOI: 10.1142/S0218126623501815
       
  • Urban Digital Transformation and Enterprise Personal Data Protection

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      Authors: Wanyi Chen, Luqi Miao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the continuous digital transformation of Shanghai, the problem of illegal use of data has become prominent. This study examines the relationship between urban digital transformation and enterprises’ personal data protection from both micro- and macro-viewpoints. Enterprises establishing personal data protection system (PDPS) can gain public support in the process of urban digital transformation, accelerate urban digital transformation, and develop the whole market. Public support, corporate governance, and government guidance interact to provide the impetus for urban digital transformation. This study provides a theoretical basis for the establishment of a smart city under emerging markets. Meanwhile, it provides practical implications for governance guidelines for promoting the digital transformation of cities.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-12T08:00:00Z
      DOI: 10.1142/S0218126623501803
       
  • An Artificial Neural Network-Based Intelligent Prediction Model for
           Financial Credit Default Behaviors

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      Authors: Zhuo Chen, Zihao Wu, Wenwei Ye, Shuang Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of intelligent techniques, smart finance has become a hot topic in daily life. Currently, financial credit is facing increasing business volume, and it is expected that investigating the intelligent algorithms can help reduce human labors. In this area, the prediction of latent credit default behaviors can help deal with loan approval affairs, and it is the most important research topic. Machine learning-based methods have received much attention in this area, and they can achieve proper performance in some scenarios. However, machine learning-based models cannot have resilient objective function, which can cause failure in having stable performance in different problem scenarios. This work introduces deep learning that has the objective function with high freedom degree, and proposes an artificial neural network-based intelligent prediction model for financial credit default behaviors. The whole technical framework is composed of two stages: information encoding and backbone network. The former makes encoding toward initial features, and the latter builds a multi-layer perceptron to output prediction results. Finally, the experiments are conducted on a real-world dataset to evaluate the efficiency of the proposed approach.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-11T08:00:00Z
      DOI: 10.1142/S0218126623501748
       
  • Statement-Level Software Defect Prediction Based on Improved R-Transformer

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      Authors: Yulei Zhu, Yufeng Zhang, Zhenbang Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Engineers use software defect prediction (SDP) to locate vulnerable areas of software. Recently, statement-level SDP has attracted the attention of researchers due to its ability to localize faulty code areas. This paper proposes DP-Tramo, a new model dedicated to improving the state-of-the-art statement-level SDP. We use Clang to extract abstract syntax trees from source code and extract 32 statement-level metrics as static features for each sentence. Then we feed static features and token sequences as inputs to our improved R-Transformer to learn the syntactic and semantic features of the code. Furthermore, we use label smoothing and weighted loss to improve the performance of DP-Tramo. To evaluate DP-Tramo, we perform a 10-fold cross-validation on 119,989 C/C++ programs selected from Code4Bench. Experimental results show that DP-Tramo can classify the dataset with an average performance of 0.949, 0.602, 0.734 and 0.737 regarding the recall, precision, accuracy and F1-measure, respectively. DP-Tramo outperforms the baseline method on F1-measure by 1.2% while maintaining a high recall rate.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-11T08:00:00Z
      DOI: 10.1142/S0218126623501839
       
  • A 40% PAE and 34[math]dBm Peak OIP3 CMOS Power Amplifier with Integrated
           Zero Power Consumption Phase Linearizer

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      Authors: Premmilaah Gunasegaran, Jagadheswaran Rajendran, Selvakumar Mariappan, Yusman Yusof, Zulfiqar Ali Abd Aziz, Narendra Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an Integrated Phase Linearizer (IPL) technique is designed to improve the linearity performance of a CMOS power amplifier (PA). The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source ([math]) capacitance of the main transistor is compensated by the linearizer. Thus, it improves the 3rd-order intermodulation point (OIP3) without trading-off the power added efficiency (PAE). The proposed solution is designed and fabricated in an 180[math]nm CMOS technology process consuming the chip area of 2.25[math]mm2. At the operating frequency of 2.45[math]GHz, it exhibits a gain of 11.14[math]dB with unconditional stability characteristics from 1[math]GHz to 10[math]GHz. Biased quiescent current of 19.35[math]mA, the IPL-PA delivers a maximum output power of 15.20[math]dBm with 40.86% peak PAE, 34.91[math]dBm of peak OIP3 and maximum power consumption of 63.65[math]mW at 2.45[math]GHz with supply voltage headroom of 1.8[math]V. The proposed linearization scheme proved to be an excellent solution for low-power transceivers integration.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-11T08:00:00Z
      DOI: 10.1142/S021812662350189X
       
  • [math] Filtering Controller for Discrete Time-Varying Delay System with
           Missing Measurements

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      Authors: Fatima Zahra Darouiche, El Houssaine Tissir
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this paper is to address the analysis and design problem of [math] filtering for discrete time-varying delay systems with missing measurements. Our attention is focused on the filter design, using Scaled Small Gain (SSG) approach, guaranteeing the asymptotic stability of the augmented system. A transformation model is obtained via three-term approximation method and Input–Output (IO) approach based on the SSG theorem. The use of SSG theorem for the stability of discrete time-varying delayed systems with missing measurements has not been studied elsewhere in the literature. This represents the main innovation of this paper. Less conservative results are obtained, compared with previous results, and are established in terms of LMIs. Numerical examples illustrate the applicability of the proposed methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-11T08:00:00Z
      DOI: 10.1142/S0218126623501463
       
  • An Efficient Channel Attention-Enhanced Lightweight Neural Network Model
           for Metal Surface Defect Detection

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      Authors: Xikun Xie, Changjiang Li, Yang Liu, Junjie Song, Jonghyun Ahn, Zhong Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      There are problems of low model detection accuracy, low detection speed and difficulty in deploying online inspection in industrial surface defect detection relying on deep learning object detection algorithms. In order to effectively solve this problem, an efficient channel attention-enhanced lightweight neural network model named as EMV2-YOLOX is proposed in this paper. The algorithm incorporates the ECA module into the lightweight backbone extraction network MobileNetV2 to achieve adaptive adjustment of channel information weights, which can improve the extraction capability of the algorithm. The YOLOX model is also introduced to enhance the model’s identification and localization of tiny defects. The improved algorithm can guarantee the model’s accuracy and improve the model detection performance, as well as the carrying capacity of hardware devices. The experimental results show that the highest accuracy is achieved on the GCT10 and NEU public defect datasets with mean Average Precision values of 0.86 and 0.68, respectively, which is higher than the accuracy of the EMV2yoloV4 model. The parametric model number is only 10.24[math]M in size, and the detection rate is 54.25[math]f/s, which is the highest performance in embedded devices. EMV2-YOLOX, combined with the attention mechanism, can efficiently extract the location and semantic information of hard-to-detect defects and plays a vital role in the intelligent detection methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-07T08:00:00Z
      DOI: 10.1142/S0218126623501785
       
  • Research on Calibration Method of Rail Profile Measurement System

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      Authors: Ning Wang, Hao Wang, Shengchun Wang, Xinxin Zhao, Fan Wang, Jinfei Hao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The rail profile measurement system is used to obtain the full section profile of the rail, which is the core of the wheel/rail interaction, based on the principle of infrared structured light. The system calibration is the key as to whether the accuracy is high enough to guide the railway maintenance. In this study, we propose a convenient and efficient checkerboard plane target calibration method based on the partition-based calibration. This method can theoretically solve the three unavoidable factors that affect the accuracy in the traditional method and is very easy to use in the field with the designed equipment. The test shows that this method has higher accuracy. We propose a correction method for the stitching calibration of double-sided cameras. Based on the standard block and high-precision stitching of rail, full section profile is achieved. Finally, through ingeniously designed field tests, it is proved that the original accuracy is significantly improved from 0.3[math]mm to 0.1[math]mm, and the repeatability is obviously improved as well. The method proposed in this study can also be extended to similar systems, improving system accuracy and simplifying the calibration procedures.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2023-01-06T08:00:00Z
      DOI: 10.1142/S0218126623501736
       
  • Impacts of Electric Vehicle Connected with Charging Station using Student
           Psychology Optimization Algorithm (SPOA) and AdaBoost Algorithm

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      Authors: M. Murugan, S. Satheesh Kumar, M. Panneer Selvam, P. Rajesh, Francis H. Shajin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an electric vehicle connected to a charging station based on the proposed method. The proposed technique is the joint execution of the Student Psychology Optimization Algorithm (SPOA) and the AdaBoost algorithm and is therefore called the SPOA-AdaBoost algorithm. In particular, the annualized social cost depends on CS and EVCS set from the objective function of the allocation model. The EVCS is linked with the CS and allows the charging service for electric vehicles. The vehicle-to-grid functions of electric vehicles are properly considered under the present optimization model. The load demands are considered as controllable resources, and EV optimal optimization problems are connected with allocation problems. When EV arrives at the charging station, it reports its own energy demand and expected departure time using the EVCS operator. Every EVCS could attack the details of electric vehicles via the proposed method. With this proper action, this method manages the energy demand and the total supply. The constraints are the power flow equations, equivalent load demands on the buses, branch current constraints, discrete size restrictions for CS, constraints on CS outputs, EV participation on V2G activities, mutual exclusivity of the EV charge and discharge statuses, EV Owner charge satisfaction, EV Owner satisfaction charge, EV SOC restrictions, Occupied CF quantities, and EVCS CF sufficiency. Among these, the execution of the present model done by the MATLAB/Simulink platform and the performance of the proposed model is likened with other systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-31T08:00:00Z
      DOI: 10.1142/S0218126623501530
       
  • Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit
           Degradation Prediction

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      Authors: Hui Xu, Rui Zhu, Xia Sun, Xianjin Fang, Pan Qi, Huaguo Liang, Zhengfeng Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of semiconductor technology, chip integration is getting beyond imagination. Aging has become one of the main threats to circuit reliability. In order to develop aging degradation prediction, it is critical to evaluate aging to avoid circuit failures. At present, the research on aging prediction is mainly focused at the transistor and gate levels: at transistor level, the precision is high, but the speed is low; whereas, the gate-level accuracy is not high, but the speed is very fast. In this paper, a path-level aging prediction framework based on the novel critical gate is proposed. The 10-year Negative Bias Temperature Instability (NBTI) aging delay of the critical subcircuit extracted by the novel critical gate is obtained, and the aging delay trend is learnt by using a linear regression model. Then the critical path aging delay can be obtained quickly based on the framework developed by machine learning using the linear regression model. The experimental results of ISCAS’85 and ISCAS’89 benchmark circuits based on 45-nm PTM show that the proposed framework is superior to the existing methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-31T08:00:00Z
      DOI: 10.1142/S021812662350175X
       
  • Wireless Communication for Drilling Using Acoustic Wave Based on MIMO-OFDM

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      Authors: Yanfeng Geng, Zhong Zheng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Underground data transmission methods are divided into wired and wireless. Wired transmission includes traditional cable and optical fiber. Wireless transmission includes pressure wave and electromagnetic wave. The limitation of the down-hole data upload rate has become the bottleneck. The wireless transmission system of an acoustic wave using a drilling fluid channel is studied. Drilling fluid channel is a multi-path channel with frequency selective fading characteristics. In the process of drilling, the shape of drill string is spatial spiral bending. This paper provides an exhaustive research in OFDM-MIMO for drilling acoustic telemetry system. The characteristics of drilling fluid channel are discussed. The performances of multiple input multiple output (MIMO), multiple input single output (MISO) and single input single output (SISO) wireless acoustic transmission systems are compared. Acoustic waves transmitted along the drilling fluid channel can realize underground wireless communication with a high transmission rate and a low bit error rate.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-31T08:00:00Z
      DOI: 10.1142/S0218126623501773
       
  • An Integrated XI-UNet for Accurate Retinal Vessel Segmentation

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      Authors: C. Aruna Vinodhini, S. Sabena
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Segmentation of blood vessels captured using a fundus camera is the cornerstone for the medical examination of several retinal vascular disorders. In recent research studies, vessel segmentation models focus on deep neural learning. To overlook the segmentation of the toughest retinal vessels like thin vessels, a new neural network architecture is developed based on U-Net integrated with the idea of depth-wise separable convolution and the Inception network incorporated with the sparsity of information. The developed XI-UNet network is trained and tested on DRIVE, STARE and CHASE_DB1 public datasets. The performance and the achievements of the XI-UNet network are greater compared to the prevalent methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-31T08:00:00Z
      DOI: 10.1142/S0218126623501827
       
  • Unison Sound Separation Using Localized Extended Common Amplitude
           Modulation

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      Authors: Yukai Gong, Longquan Dai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Musical source separation isolates one or more musical instruments from a polyphonic mixture. The main challenge is to separate the source partials overlapped in the same time–frequency region. For the unison case, the source separation task is quite difficult because no source has nonoverlapping partials. Owing to the lack of effective methods in monaural unison sound separation, this paper proposes a localized extended common amplitude modulation (LECAM) method. Our strategy assumes that partials from the same source have correlated amplitude envelopes in a period of time and use a multi-band co-processing way for separating each source partial. Extensive experiments are conducted on unison mixture samples drawn from the Iowa University Musical Instrument Database. Results demonstrate that our LECAM achieves the overall best separation performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-28T08:00:00Z
      DOI: 10.1142/S0218126623500925
       
  • A Space-Efficient Universal and Multi-Operative Reversible Gate Design
           Based on Quantum-Dots

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      Authors: Saeid Seyedi, Nima Jafari Navimipour
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Because of the high speed, low-power consumption, low latency and possible use at the atomic and molecular levels, Quantum-dot Cellular Automata (QCA) technology is one of the future nanoscale technologies that can replace the present transistor-based technology. For the purpose of creating QCA circuits, reversible logic can be regarded as an appropriate candidate. In this research, a new structure for multi-operative reversible designs is suggested. The Saeid Nima Gate (SNG), proposed in this research study, is a brand-new, incredibly effective, multi-operative, universal reversible gate implemented in QCA nanotechnology employing both majority and inverter gates. Reversible gates, also known as reversible logic gates, are gates that have n inputs and n outputs, which is an equal number of inputs and outputs. The amount of energy lost during computations will be reduced if the numbers of inputs and outputs are identical. The proposed gate is modified and reorganized to optimize further, employing exact QCA cell interaction. All fundamental logic gates are implemented using it to demonstrate the universality of the proposed SNG. Reversible logic has advanced, and as a result, our suggested solution has a lower quantum cost than previously reported systems. The suggested design is simulated using the QCADesigner-E tools.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-28T08:00:00Z
      DOI: 10.1142/S0218126623501669
       
  • Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving
           Energy Efficiency

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      Authors: Neetika Yadav, Neeta Pandey, Deva Nand
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approach offers maximum PDP reduction of 33.52%, 99.39% and 96.61% for 2-input gates as compared to their footed DML, DMPL and DMTGDI counterparts, respectively. The reduction in PDP is quite significant in 1-bit full adder circuit where the corresponding values are 94.18%, 99.41% and 99.79%, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-28T08:00:00Z
      DOI: 10.1142/S0218126623501712
       
  • Congestion Detection and Alleviation Mechanism Using a Multi-Level Cluster
           Based Cuckoo Hosted Rider Search Multi-Hop Hierarchical Routing Protocol
           in Wireless Sensor Networks

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      Authors: Kavita K. Patil, T. Senthil Kumaran
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor networks congestion occurs easily due to its centralized traffic pattern. Normally, mono-sync wireless sensor network experiences multiple traffic flow congestion in the dense environment of the network, which leads to excess energy consumption and severe packet loss. To overcome these issues, a congestion detection and alleviation mechanism using cluster based heuristic optimized hierarchical routing protocol is proposed in this paper. Here, congestion detection and alleviation utilize the features of sensor nodes. The congestion is categorized into two types: (i) node level congestion and (ii) link level congestion. The node level congestion is detected by assessing the buffer utilization and the interval amid the consecutive data packets. The link level congestion is considered with computing link usage utilizing back-off step of round robin carrier sense multi-access with collision avoidance. Congestion detection and alleviation reactively affected node/link through cuckoo hosted rider search multi-hop routing algorithm. It has two phases: the cluster head selection and multi-path routing. Cluster head selection is performed through Taylor multiple random forest kernel fuzzy C-means clustering algorithm and multi-path routing is performed through cuckoo hosted rider search multi-hop routing algorithm. The simulation of the proposed method is done in network simulator tool. Here, the performance metrics, like packet delivery ratio, delay, energy consumption, packet drop, overhead, network lifetime and throughput are calculated. The experimental outcomes of the proposed technique shows 11.6%, 18.4% and 28.1% lower delay, 78.2%, 65.4% and 52.6% higher packet delivery ratio, and 29.2%, 37.4% and 40.8% lower packet drop compared with the existing methods, like congestion detection and alleviation using multi-attribute decision-making in optimization-based hybrid congestion alleviation routing protocol in wireless sensor networks, congestion detection and alleviation using hybrid K-means with greedy best first search algorithms in packet rate reduction utilizing adaptive weight firefly algorithm ant colony optimization based routing protocol in wireless sensor networks and congestion detection and alleviation using multi-input time on task optimization algorithm for altered gravitational search algorithm routing protocol in wireless sensor networks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-23T08:00:00Z
      DOI: 10.1142/S0218126623501621
       
  • A Hybrid Neural Network-Based Intelligent Forecasting Approach for
           Capacity of Photovoltaic Electricity Generation

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      Authors: Yinjuan Zhang, Yongke Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent years, photovoltaic power generation technology has become the key planning direction of the country. It is important to effectively predict photovoltaic (PV) electricity generation capacity, so that the administrators can well schedule resource allocation. Currently, most of the photovoltaic electricity generation forecasting models took meteorological data as the input parameters of neural network. However, the input parameters and redundant data cause neural network to converge difficultly. Besides, single types of neural network models cannot well capture the comprehensive characteristics, which may influence forecasting effect in evolving process. As a result, we propose a hybrid neural network-based intelligent forecasting approach for PV electricity generation capacity. First, convolution neural network (CNN) is adopted to extract the connection between features and data from the perspective of convolution operations. And then, the extracted feature vector of time series is sent into the long short-term memory (LSTM) model. Finally, the forecasting values are predicated by training the outlined LSTM network. The experimental results indicate that such a hybrid CNN-LSTM model can significantly improve the precision of PV electricity generation prediction and provide an effective way to forecast generation power of PV system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-23T08:00:00Z
      DOI: 10.1142/S0218126623501724
       
  • Network Aware Resource Optimization Using Nature Inspired Optimization
           Algorithm for Task Scheduling in Cloud Infrastructure

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      Authors: Punit Gupta, Dinesh Kumar Saini, Abhilasha Choudhary, Vibhor Sharma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cloud is a pay-per use infra-structed which has invited huge clients to cloud, in order to get reliable services without extra maintenance or infrastructure cost. Growing cloud services and migration of small business to cloud have led to high load on cloud service providers, which leads to the need of better optimization algorithm in order to manage the machine better performance and meet better quality of services to the client. Cloud broker or agent plays an important role to achieve this using intelligent task scheduling algorithm to manage the task in such a way to optimize the performance of the cloud services and data center. Currently various optimization algorithms are proposed but most of them take execution time into consideration but not the network delay between the client and the data center. Hence, to overcome this, an optimization algorithm is proposed in this work using execution time and network delay as the optimization parameters. The nature inspired grasshopper optimization is proposed which is compared with the exiting PSO and ACO models to study the performance. The results show that the proposed algorithm out performs the existing models with execution time, total time and network delay as performance metrics. It demonstrates how the suggested, naturally inspired GOA algorithm beats the existing ACO and PSO algorithms for task scheduling in the cloud with scaling loads requiring 5 virtual machines and 2 data centers. More objective functions, such as power and cost-effective algorithms, can be added to the work to further expand it. This study compares the efficacy of several algorithms based on the predetermined criteria while also examining related algorithms. To determine the best algorithm possible, it is intended to offer each approach individually, analyze the results, and plot the resulting graphs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-21T08:00:00Z
      DOI: 10.1142/S0218126623501323
       
  • Multiple Objective Fairness Scheduling Optimization Algorithms Based on
           Multiple DAGs in Heterogeneous Edge Computing

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      Authors: Fan Yang, Kelei Zhan, Jiayi Du, Zhilin Huang, Guoqi Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The rapid development of edge computing has promoted the growing demand of applications. Quality of service (QoS) must be improved because this index involves issues such as unfairness and short Directed Acyclic Graph (DAG) schedule length. We propose a new algorithm named Multiple DAGs Depth Fairness Task Scheduling (MDDF) in this study to solve the multi-DAG task unfairness problem effectively, the algorithm on the basis of the measured depth of the task in the DAG, improves the fairness of multiple DAG, enhance the user QoS and obtain a fast response. The proposed algorithm is then compared with four common heuristic scheduling methods to verify its effectiveness. We propose another algorithm called Fast Multi-DAG Depth Fairness Task Scheduling (FMDDF) with high average slowdown to reduce the schedule length of short DAG and accelerate the response time. Experimental results show that FMDDF can improve scheduling and shorten the schedule length of short DAG by about 5% and MDDF can enhance fairness by about 2% while reducing the short DAG schedule length compared with other algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-19T08:00:00Z
      DOI: 10.1142/S0218126623501414
       
  • A New Radio Frequency Distortion Dynamic Range Index for Performance
           Evaluation

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      Authors: Desheng Wang, Yangjie Wei, Dong Ji, Yi Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Dynamic range and spurious-free dynamic range are two of the most critical performance indexes in the field of radio frequency (RF). However, the definitions of both the indexes are ambiguous, and their characterization ability is insufficient, resulting in unfair, and even mutually incompatible, performance evaluation in practice. In this study, a new index named radio frequency distortion dynamic range and its corresponding evaluation method are proposed to achieve a fair and detailed dynamic range evaluation by unifying the existing definitions and improving the performance resolution ability. First, the sliding threshold selection method is introduced to replace the classification-based method of dynamic range definition to characterize more details of the dynamic range. Second, a dynamic range evaluation method of “performance body” is proposed to obtain a more comprehensive evaluation by generalizing the current evaluation from being based on a single condition to the one based on scanning critical conditions. Experiments show that the proposed radio frequency distortion dynamic range index with the proposed evaluation method reduces the ambiguity of dynamic range evaluation and can distinguish the performance difference that the current indexes cannot do.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-19T08:00:00Z
      DOI: 10.1142/S0218126623501608
       
  • FPGA-Based Implementation of an Error-Controllable and Resource-Efficient
           Approximation Method for Transcendental Functions

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      Authors: Zhenyu Zhang, Guangsen Wang, Qing Liu, Zhiwei Wang, Kang Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Transcendental functions cannot be expressed algebraically, which brings a big challenge to efficient and accurate approximation. Lookup table (LUT) and piecewise fitting are common traditional methods. However, they either trade approximate accuracy for computation and storage or require unaffordable resources when the expected accuracy is high. In this paper, we have developed a high-precision approximation method, which is error-controllable and resource-efficient. The method originally divides a transcendental function into two parts based on their slope. The steep slope part is approximated by the method of LUT with the interpolation, while the gentle slope part is approximated by the range-addressable lookup table (RALUT) algorithm. The boundary of two parts can be adjusted adaptively according to the expected accuracy. Moreover, we analyzed the error source of our method in detail, and proposed an optimal selection method for table resolution and data bit-width. The proposed algorithm is verified on an actual FPGA board and the results show that the proposed method’s error can achieve arbitrarily low. Compared to other methods, the proposed algorithm has a more stable increase in resource consumption as the required accuracy grows, which consumes fewer hardware resources especially at the middle accuracy, with at least 30% LUT slices saved.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-19T08:00:00Z
      DOI: 10.1142/S0218126623501633
       
  • A Neural Network-Based Method for Surface Metallization of Polymer
           Materials

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      Authors: Lina Liu, Yuhao Qiao, Dongxia Wang, Xiaoguang Tian, Feiyue Qin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      It’s no secret that polymers have been employed extensively in a variety of industries. Polymers, on the other hand, have faced difficulties in their development because of their complicated chemical composition and structure. Data-driven approaches in polymer science and technology have resulted in new directions in research leading to the implementation of deep learning models and vast data assets. In the growing area of polymer informatics, deep learning methods based on factual data are being used to speed up the performance assessment and process improvement of new polymers. Using a deep neural network (DNN), we can now forecast the surface metallization properties of polymer materials, which we describe in this research. First, we collect a raw dataset of polymer materials’ characteristics. The raw data are filtered and normalized using the min–max normalization approach. To convert normalized data into numerical characteristics, principal component analysis (PCA) is employed. Polymer surface metallization characteristics can then be predicted using a suggested DNN technique. The proposed and conventional approaches are also compared so that our research can be done to its full potential.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-19T08:00:00Z
      DOI: 10.1142/S0218126623501670
       
  • Long-Range Technology-Enabled Smart Communication: Challenges and
           Comparison

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      Authors: Sneha, Praveen Malik, Sudipta Das, Syed Inthiyaz
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Among other technologies, the Internet of Things (IoT) is one of the promising technologies that will help us to make our environment smarter and gather, analyze and process sensor data without any human intervention. Low Power Wide Area Network (LPWAN) is a technology that is part of the IoT, in which is the long-range (LoRa) technology that can provide wide coverage at a cost of very low power and that can boost data communication in our smart environment. The ease of their integration with the electronic system has opened a lot of new scope in the field of low-power wide-area networks in IoT applications. This paper provides a well-rounded review of LPWAN technology and in-depth details of LoRa technology. A good insight is given into the implementation of LoRa technology to design smart cities and the types of antenna technology used in LoRa data communications. Finally, a few open issues, possible solutions and future development are pointed out.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-15T08:00:00Z
      DOI: 10.1142/S021812662350161X
       
  • Object Detection in 3D Point Cloud Based on ECA Mechanism

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      Authors: Xinkai Wang, Xu Jia, Miyuan Zhang, Houda Lu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Aiming at the problems of high complexity and low detection accuracy of single-stage three-dimensional (3D) detection method, a vehicle object detection algorithm based on the Efficient Channel Attention (ECA) mechanism is proposed. This paper provides a good solution to the problems of low object recognition accuracy and high model complexity in the field of 3D object detection. First, we voxelized the original point cloud data, taking the average coordinates and intensity values as the initial features. By entering into the Voxel Feature Encoding (VFE) layer, we can extract the features of each voxel. Then, referring to the VoxelNet model, the ECA mechanism is introduced, which reduces the complexity of the model while maintaining the good performance in the model. Finally, experiments on the widely used KITTI dataset show that the algorithm performs well, and the accuracy of the proposed ECA algorithm has reached 87.75%. Compared with the current mainstream algorithm SE-SSD of object detection, the accuracy is increased by 0.21%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-14T08:00:00Z
      DOI: 10.1142/S0218126623500809
       
  • Transformer-Less Novel Hybrid Converter Based Solar PV fed UPS System

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      Authors: P. Naveen, B. Baskaran, R. V. D. Rama Rao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The uninterrupted power supply (UPS) plays a dominant role in domestic appliances and also the growth rate of solar roof top system implementation is massively increasing day by day. To minimize the cost on the converters, solar PV power is directly connected with existing UPS with separate MPPT controller. However, due to the presence of nominal frequency transformer, the size and cost of UPS becomes more. In addition, it consumes the power with poor power quality to charge the battery. Apart this, the current supplied from the battery is much higher due to the lower voltage level of battery, which makes voltage dip during peak load condition and resulting to shorten the battery life and degrades its performances. In order to overcome all these drawbacks, this particular paper proposes a transformer-less novel hybrid converter based solar PV fed UPS system. In the hybrid structure, the gain can be achieved higher with minimum components counts. The novelty of the proposed transformer-less hybrid converter is that the regeneration of switched capacitor voltage is applied to input of switched inductor network in DC–DC converter, due to this hybrid structure the gain has been extended drastically with minimum number of devices. Also the coordinated control algorithm is implemented in solar PV fed UPS to take the decision according to the situation of generation, load and battery back-up. The detailed operation of the proposed coordinated control algorithm has been addressed in this paper. Moreover, the detailed simulation study is carried out for each mode of operation and measured results are obtained and presented in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-12T08:00:00Z
      DOI: 10.1142/S0218126623501335
       
  • A Switched-Capacitor, Integrator-Multiplexing, Second-Order Delta-Sigma
           Modulator Featuring a Single Differential Difference Amplifier for
           Portable EEG Application

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      Authors: Quanzhen Duan, Dameng Kong, Chenxi Lin, Shengming Huang, Zhen Meng, Yuemin Ding
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We present a novel switched-capacitor, integrator-multiplexing, second-order delta-sigma modulator (DSM) featuring a single differential difference amplifier (DDA). Power consumption is low and resolution is high when this DSM is used for portable electroencephalographic applications. A single DDA (rather than a conventional operational transconductance amplifier) with appropriate switch and capacitor architectures is used to create the second-order switched-capacitor DSM. The configuration ensures that the resolution is high. The modulator was implemented using a standard 180[math]nm complementary metal–oxide–silicon process. At a supply voltage of 1.8[math]V, a signal bandwidth of 250[math]Hz and a sampling frequency of 200[math]kHz, simulations demonstrated that the modulator achieved an 82[math]dB peak signal-to-noise–distortion ratio and an effective number of bits of 14.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-12T08:00:00Z
      DOI: 10.1142/S0218126623501554
       
  • A Wireless Virtual Reality-Based Multimedia-Assisted Teaching System
           Framework under Mobile Edge Computing

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      Authors: Wei Cui, Ding Eng Na, Yuting Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent years, virtual reality (VR) has gradually entered the daily education and teaching activities from pure scientific research. In the area of assistance teaching, some typical computer softwares still play some important roles. This makes remote teaching activities can just learn voice, yet cannot possess the feeling of realistic existence. Especially in scenario of COVID-19, remote teaching activities with proper perceptibility are in urgent demand. To deal with the current challenge, this paper proposes a wireless VR-based multimedia-assisted teaching system framework under mobile edge computing networks. In this framework, cooperative edge caching and adaptive streaming based on viewport prediction are adopted to jointly improve the quality of experience (QoE) of VR users. First, we investigated the resource management problem of caching and adaptive streaming in this framework. Considering the complexity of the formulated problem, a distributed learning scheme is proposed to solve the problem. The experimental data are verified and the experimental results prove that the studied methods improve the performance of user QoE.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-10T08:00:00Z
      DOI: 10.1142/S0218126623501165
       
  • An Improved Sparrow Search Algorithm for Location Optimization of
           Logistics Distribution Centers

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      Authors: Yaqin Ou, Lei Yu, Ailing Yan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In modern society where business development is booming, it is of great importance to investigate location optimization of logistics distribution centers. In order to achieve greater efficiency of distribution system, save the distribution costs and the construction cost of logistics distribution center, good point set method and decreasing nonlinear inertia weight are proposed to improve sparrow search algorithm (SSA) to solve the mathematical model for logistics distribution center location. First, in order to prevent SSA falling in local optimal, while improving the convergence speed and efficiency of SSA, good point set method and decreasing nonlinear inertia weight are applied to improve the SSA. The test results of eight benchmark functions show that the fitness value and convergence speed of the proposed ISSA are smaller and faster. Second, compared with SSA, WOSA and PSO, the ISSA has the lowest total cost for solving the mathematical model of logistics distribution center.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-10T08:00:00Z
      DOI: 10.1142/S0218126623501505
       
  • DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable
           Reconfigurable Array Architecture

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      Authors: Kangle Li, Lin Jiang, Xingjie Huang, Kun Yang, Xiaoyan Xie, Junyong Deng, Rui Shan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To improve the performance and power efficiency of various algorithms in specific applications, reconfigurable architecture has become an effective choice in academia and industry. However, due to the slow context updates and the insufficient flexibility, the existing reconfigurable architectures suffer from performance bottlenecks. Therefore, this paper proposed a dynamic reconfiguration mechanism applied to dual-mode programmable reconfigurable array architecture. This mechanism adopts Huffman-like coding and mask addressing, and through the H-tree transmission network, it can transmit the reconfiguration instruction/context to a specific processing element or processing element cluster in unicast, multicast, or broadcast modes within a clock cycle and shut down unnecessary processing elements or processing element clusters according to the current configuration. Meanwhile, a homogeneous reconfigurable array is designed to verify the correctness and effectiveness of the proposed dynamic reconfiguration mechanism. In this array, the processing element supports both instruction flow and data flow modes. Finally, the proposed work is implemented in register transfer level synthesis and a field-programmable gate array prototype, and its performance is verified using high-efficiency video coding algorithm. The results show that the proposed reconfiguration mechanism can effectively improve the hardware resource utilization and reconfiguration efficiency, it also can achieve the performance breakthrough of the reconfigurable architecture.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-10T08:00:00Z
      DOI: 10.1142/S0218126623501578
       
  • Optimization of Performance Parameters of Phase Frequency Detector Using
           Taguchi DoE and Pareto ANOVA Techniques

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      Authors: Jyoti Sharma, Gaurav Kumar Sharma, Tarun Varma, Dharmendar Boolchandani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ([math], [math], and [math]) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters [math], [math], and [math] are likewise determined using this procedure to maximize the circuit’s overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180[math]nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are [math][math]dBc/Hz, 9.83[math][math]W, and 10.21[math]GHz, respectively, and it occupies a chip area of 300.41[math][math]. The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59[math][math]s.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-10T08:00:00Z
      DOI: 10.1142/S021812662350158X
       
  • Fault Detection in Electrical Equipment by Infrared Thermography Images
           Using Spiking Neural Network Through Hybrid Feature Selection

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      Authors: Shanmugam Chellamuthu, E. Chandira Sekaran, Sivakumar Annamalai, A. R. Palanisamy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The Spiking Neural Network (SNN) model is a third-generation neural network model that uses spike pulse trains to detect and classify electrical problems in the electrical equipment under consideration. To diagnose the thermal issue in the early stages, it is required to evaluate and monitor the electrical components. The detection method in Infrared Thermography (IRT) is hybrid optimization, which is a Dragonfly Algorithm (DA)–Ant Colony Optimization (ACO) technique that produces a higher exploration and exploitation rate while moving toward an optimal solution with a higher convergence rate. The innovative hybrid DA–ACO method used in this study aims to find the best weights for the SNN model while also extracting the most useful characteristics for defect detection in electrical equipment. To improve classification accuracy, the optimum features picked using the created hybrid DA–ACO are provided to the SNN model. Based on conventional and other optimization methods, the proposed method provided superior results from the execution results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501396
       
  • Construction Technique and Evaluation of High Performance [math]-bit Burst
           Error Correcting Codes for Protecting MCUs

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      Authors: Raj Kumar Maity, Jagannath Samanta, Jaydeb Bhaumik
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance [math]-bit Burst Error Correcting (BEC) codes. Parity check matrices ([math]) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting [math]-bit burst errors caused by MCUs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501426
       
  • Design and Implementation of a Sense Amplifier for Low-Power Cardiac
           Pacemaker

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      Authors: Pavankumar Bikki, Yenduri Dhiraj, R. V. S.  Nivas Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the implementation of a sense amplifier for a low-power cardiac pacemaker using the Differential Voltage Current Conveyor (DVCC). Two significant aspects of the pacemaker are sensing and pacing. The pulse generator, which is the heart of the pacemaker, consists of a sense amplifier, a logic unit and a timing control unit. The sense amplifier comprises an instrumentation amplifier, a bandpass filter and a comparator that are used to detect the QRS complex wave from the cardiac signal. Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501487
       
  • On-Chip GaN Planar Transformer Design for Highly Integrated RF Systems

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      Authors: Mokhtaria Derkaoui, Yamina Benhadda, Ghacen Chaabene, Pierre Spiteri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The work presented in this paper concerns the design of an on-chip GaN transformer. The integrated transformer is composed of two planar stacked coils with spiral octagonal geometry. A comparison is done on different analytical methods to calculate the inductance of the transformer spiral planar coils. Three transformers with different outer diameters are compared to illustrate the influence of the coil geometry. The estimated inductance and dc series resistance are evaluated. Using COMSOL Multiphysics 5.3 software, the thermal effect is illustrated in the integrated transformer operating at high frequencies. The different parasitic effects created by the planar stacked layers are validated by the equivalent electrical circuit, and the different electrical parameters are calculated.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501499
       
  • The Construction of an Intelligent Service System for Students’
           Physique and Health

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      Authors: Huan Zhai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The development of young people’s physique and health is the core element of national manpower reserves, which is related to the rise and fall of national power in the future. In recent years, a large-scale physical fitness test for students has been carried out by the state every year; thus, abundant data have been accumulated. However, for a long time, the collection, integration, analysis and utilization of these data resources have been seriously insufficient; thus, it is difficult to meet the needs of student health services. Wireless devices are emerging rapidly due to their sensing, computing and communication capabilities and are gradually being applied to physique and health research. This is expected to improve the traditional service model. Personalized physique and health information of students can be obtained via wearable devices. However, to effectively analyze and utilize these data and improve the effectiveness of corresponding health management decisions, intelligent analysis methods are needed. Machine learning, as the core of artificial intelligence technology, can learn from big data and mine the potential value of data in order to predict events and propose countermeasures. This paper aims to collect and transmit various kinds of physique and health data of students through wireless communication technology and to realize intelligent analysis and management of these data based on a machine learning algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501517
       
  • GPS Receivers Spoofing Detection Based on Subtractive, FCM and DBSCAN
           Clustering Algorithms

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      Authors: Z. Sarpanah, M. R. Mosavi, E. Shafiee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      GPS receivers have a wide range of applications, but are not always secure. A spoofing attack is one source of conscious errors in which the counterfeit signal overcomes the authentic GPS signal and takes control of the receiver’s operation. Recently, GPS spoofing attack detection based on computational algorithms, such as machine learning, classification, wavelet transform and clustering, has been developing. This paper proposes multiple clustering algorithms for accurately clustering the authentic and spoofing signals, called subtractive, FCM and DBSCAN clustering. The spoofing attack is recognized using two distinct features: moving phase detector variance and norms of correlators. Spoofing and authentic signals have different patterns in the proposed features. According to the Dunn and Silhouette indexes, the validation of the results is investigated. The Dunn values for the proposed approaches are 0.8592, 0.5285 and 0.6039 for DBSCAN, FCM and subtractive clustering, respectively. Also, the DBSCAN algorithm is implemented at the RTL level because of its highest value for the Dunn index and algorithm verifiability. Using the Vivado tools, this algorithm is implemented and designed on a Xilinx Virtex 7 xc7vx690tffg1930-3 hardware device for two-dimensional data with 32-bit accuracy and 130 data points.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501529
       
  • Validation of the Hospital Score as Predictor of 30-Day Potentially
           Avoidable Readmissions in a Brazilian Population: Retrospective Cohort
           Study

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      Authors: Nayara Cristina da Silva, Marcelo Keese Albertini, André Ricardo Backes, Geórgia das Graças Pena
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Background: Hospital readmissions are associated with several negative health outcomes and higher hospital costs. The HOSPITAL score is one of the tools developed to identify patients at high risk of hospital readmission, but its predictive capacity in more heterogeneous populations involving different diagnoses and clinical contexts is poorly understood. Objective: The aim of this study is to externally validate the HOSPITAL score in a hospitalized Brazilian population. Methods: A retrospective cohort study was carried out with patients over the age of 18 years in a tertiary university hospital. We performed a refitted HOSPITAL score with the same definitions and predictive variables included in the original HOSPITAL score and compared the predictive capacity of both. The receiver operating characteristic was constructed by comparing the performance risk forecasting tools measuring the area under the curve (AUC). Results: Of the 47,464 patients, 50.9% were over 60 years and 58.4% were male. The frequency of 30-day potentially avoidable readmission was 7.70%. The accuracy of original and refitted HOSPITAL scores was close, although statistically different ([math]), AUC: 0.733 (CI 95%: 0.718, 0.748) and 0.7401 (CI 95%: 0.7256, 0.7547), respectively. The frequency of 60, 90, 180, and 365-days readmissions ranged from 10.60% to 18.30%. Conclusion: The original and refitted HOSPITAL score is a useful tool to identify patients at high risk of 30-day potentially avoidable readmission, in patients with different diagnoses in public tertiary hospitals. In this sense, our study expands and reinforces the usefulness of the HOSPITAL score as a tool that can be used as part of intervention strategies to reduce the rate of hospital readmission.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-08T08:00:00Z
      DOI: 10.1142/S0218126623501542
       
  • Prediction Model of Ischemic Stroke Based on Machine Learning

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      Authors: Zhijie Zhang, Zhihong Zou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Machine learning (ML) can be used for deep mining and analysis of multidimensional medical data. At present, it has been widely used in medical diagnosis and prognosis prediction. This paper aims to make the existing research no longer focus on identifying key risk factors of stroke, and predict stroke risk more accurately. We collected the data of 3,962 cerebral apoplexy patients from 2019 to 2020, according to gender (male: 2,613; female: 1,349) and age (16–40 years old; 41–54 years old; 55–69 years old; 70 years old and above) layered. After data preprocessing, a stroke risk prediction model was built using principal component analysis (PCA) and extreme learning institutions (ELM). The prediction accuracy of PCA-ELM was as high as 97%. In this model, total cholesterol and high density lipoprotein are taken as 10 important factors that affect the incidence of stroke. This method can timely and efficiently mine the factors influencing the incidence of cerebral apoplexy from the data, and can predict the incidence of cerebral apoplexy. It has high value in practical application. This paper has great reference value in the research of brain death.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-07T08:00:00Z
      DOI: 10.1142/S0218126623500883
       
  • Analysis on Millimeter-Wave Channel Dispersion Over Nonreciprocal Beam
           Patterns Based on the Propagation-Graph Model

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      Authors: Jiachi Zhang, Liu Liu, Zhenhui Tan, Kai Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Millimeter-wave (mmWave) together with multiple-input multiple-output (MIMO)-enabled beamforming technology offers greater bandwidths than previously available and overcomes the high propagation loss. Nonreciprocal beam patterns, i.e., transceivers using beams with different beamwidths, can not only reduce the hardware cost but also make the beam alignment more efficient. In this paper, we use the propagation-graph (PG) model to fully investigate the channel characterization over nonreciprocal beam patterns at 45 GHz. Specifically, we propose a beam-enabled propagation-graph channel model by considering the spatial filter effect of beams. Moreover, the propagation gain of each path with certain angular information is filtered by the array response. Then, channel dispersions in delay and frequency domains are analyzed over nonreciprocal beam patterns. Simulation results reveal that the downlink in a macrocell scenario covers more important scatterers than those of the uplink, leading to an evident dispersion effect in delay, frequency, and angular domains consequently. Whereas, the uplink, with little or no dispersion effect, can be approximated as a line-of-sight (LoS) scenario with a single propagation path.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-07T08:00:00Z
      DOI: 10.1142/S0218126623501153
       
  • Research on Output Power of Series–Series Resonance Wireless Power
           Transmission System

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      Authors: Haokun Chi, Chunxiao Mu, Yingjie Wang, Fei Wang, Yongchao Hou, Feixiang Gong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The popularization of smart mobile devices has led to the research on wireless power transfer (WPT) technology. Previous research shows that increasing the excitation coil or the energy transfer coil can increase the energy transmission distance of the WPT system. But the mutual inductance calculation of coils is not accurate enough when the distance is close. This paper presents an improved formula to calculate the mutual inductance between two round inductance coils. Contrasts with the previous calculation methods, computer simulation and experimental results are done to validate the accuracy of the formula, especially when the two inductance coils are close together. On the basis of this formula, the maximum output power (MOP) and the maximum output power distance (MOPD) of the two-, three- and four-coil series–series resonance WPT systems based on circuit models are studied and compared. The simulation and experimental results show a high consistency with the theoretical calculation results. We can find that the farther the MOPD of the system is, the smaller the MOP is. Moreover, when the operating frequency increases, the MOPD of the two-coil conformation increases, while the four-coil conformation is just opposite.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-07T08:00:00Z
      DOI: 10.1142/S0218126623501177
       
  • Analog Compatible Logic Functions Using EXCCIIs and an Extended
           Application for Sigmoid Activation Function

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      Authors: Sudhanshu Maheshwari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces the use of an extra X current conveyor (EXCCII) for realizing logic operations, suited for mixed signal design, without necessitating separate digital blocks. The NOR and OR logic functions are thus shown to be realized using the current-mode analog building block operable at a low voltage. The use of [math][math]V supply makes the new circuits operable at low voltage. The EXCCII bias current used in the design is 25[math][math]A. The input currents for defining logic 0 and logic 1 are, respectively, taken as 0[math]mA and 0.5[math]mA. The proposed circuits’ delay is found to be 10[math]ns for low-to-high transition, while 2[math]ns for high-to-low transition for NOR gate under capacitive loading conditions. The use of the current-mode approach makes the new proposed circuit apt for current-mode signal processing. The new proposed logic function circuits are compatible with analog circuits, thus providing an easy merger for mixed signal systems design, paving the way to a modular design approach. As an extended application in artificial neural networks, the proposed circuit is shown to generate a sigmoid activation function with convincing results. Several results are included by varying the reference current, and the circuit’s robustness aspect is also tested in the presence of fluctuation in the bias current of EXCCII. The novel approach of utilizing an analog building block for realizing digital functions is, therefore, verified with promising future applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-07T08:00:00Z
      DOI: 10.1142/S0218126623501475
       
  • Impact of Negative Solar Resistance on DC Microgrid Stability: Virtual
           Damping Voltage and Current Solar Droop Emulated Controller

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      Authors: Mukh Raj Yadav, Navdeep Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The negative solar resistance, is highly dependent on the solar operating point. The system will become sluggish and unstable during low irradiance. It is reported that the impact of negative solar resistance is nullified by parallel impedance emulated condition (PIEC). During low irradiance, the system stability has been moved to an unstable position which is not fully resolved by PIEC. In this paper, a virtual inertia-damping voltage and current solar droop emulated controller is proposed to improve the voltage oscillation profile, inertia problem and damping of the DC microgrid system. In DC microgrids, the inherent inertia from DC capacitors is low, thus affecting the bus voltage oscillation during a reduction of irradiance. The oscillation of the system has been increased due to the equivalent impedance by negative solar resistance at lower irradiance. Oscillation’s issue and voltage instability of the PV system have been enhanced by the inner current controller. In addition, the steady-state error of the PV voltage is minimized by the virtual inertia-damping voltage restoration droop controller with PIEC. Performance analysis and dynamic characteristics are discussed through a pole-zero plot for the various conditions of negative solar resistance using virtual inertia-damping voltage and current Solar Droop Emulated Controller. This paper focuses on stability analysis to strengthen the DC microgrid. The performance of the solar controller with bidirectional converter (BDC) controller has been discussed to verify the power management between the system to manage the power for the unbalanced load.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-05T08:00:00Z
      DOI: 10.1142/S0218126623501268
       
  • Development of RF-Photonic System for Automatic Targets’ Nonlinear
           Rotational/Flapping/Gliding Signatures Imaging Applications

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      Authors: Nargis Akhter, Harish C. Kumawat, A Arockia Bazil Raj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, developing the radio frequency (RF)-photonic sensors suitable for several Defence and civil applications is emerging due to its various unique advantages. In today’s scientific world, the involvement of low radar cross-section (RCS) airspace targets, such as unman aerial vehicles, drones, mini-helicopters, ornithopters, bionic birds, etc., is more for the purpose of airspace traffic management/guidance, materials delivery, legal/illegal surveillance and Defence/offense applications. The detection and recognition of such targets using the conventional RF sensors (which process only the main Doppler) is almost impossible. Therefore, extracting the distinctive micro-Doppler (m-D) signatures of these low-RCS targets and using them to image/differentiate/recognize their postures become significant which is the main contribution in this paper. A C-band continuous wave RF-photonic sensor is developed and different low-RCS targets: 2/3 blades rotating propeller system (drones), cone like structure (warhead) and a bionic-bird (spy-bird); are operated in front of it. The different nonlinear postures, of these targets, covered in our experimental measurements are m-D extraction of a slowly moving propeller system, detection of back-and-forth movements of a rotational propeller system, discerning the moving and static rotational propeller systems, simultaneous extraction of m-D signatures of a rotational and moving targets and recognition of flapping/gliding motions of bionic-bird. The analysis and recognition of all these postures using the experimentally generated m-D signatures are described.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-02T08:00:00Z
      DOI: 10.1142/S0218126623501311
       
  • GOKA: A Network Partition and Cluster Fusion Algorithm for Controller
           Placement Problem in SDN

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      Authors: Changwei Xiao, Jue Chen, Xihe Qiu, Dun He, Hanmin Yin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Software Defined Networking (SDN) is a new promising network architecture, with the property of decoupling the data plane from the control plane and centralizing the network topology logically, making the network more agile than traditional networks. However, with the continuous expansion of network scales, the single-controller SDN architecture is unable to meet the performance requirements of the network. As a result, the logically centralized and physically separated SDN multi-controller architecture comes into being, and thereupon the Controller Placement Problem (CPP) is proposed. In order to minimize the propagation latency in Wide Area Network (WAN), we propose Greedy Optimized K-means Algorithm (GOKA) which combines K-means with greedy algorithm. The main thought is to divide the network into multiple clusters, merge them greedily and iteratively until the given number of controllers is satisfied, and place a controller in each cluster through the K-means algorithm. With the purpose of proving the effectiveness of GOKA, we conduct experiments to compare with Pareto Simulated Annealing (PSA), Adaptive Bacterial Foraging Optimization (ABFO), K-means and K-means[math] on 6 real topologies from the Internet Topology Zoo and Internet2 OS3E. The results demonstrate that GOKA has a better and more stable solution than other four heuristic algorithms, and can decrease the propagation latency by up to [math], [math], [math] and [math] in contrast to PSA, ABFO, K-means and K-means[math], respectively. Moreover, the error rate between GOKA and the best solution is always less than [math], which promises the precision of our proposed algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-02T08:00:00Z
      DOI: 10.1142/S021812662350144X
       
  • A CMOS Relaxation Oscillator with Process and Temperature Variation
           Compensation

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      Authors: Zhenyan Huang, Kewei Hu, Yi Ding, Nick Nianxiong Tan, Hanming Wu, Xiao-Peng Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a CMOS relaxation oscillator with trimming and temperature compensation is presented for the on-chip multi-sensor systems which need MHz level frequency source. The proposed scheme uses a single current branch to charge the capacitor to generate the oscillation with voltage average feedback (VAF) circuit. Binary-weight current trimming array is adopted to reduce the frequency variation caused by the process variation under different process corners. A compensation calibration resistor array with Kelvin connection is utilized to improve the frequency variation with temperature. With the help of VAF, the frequency spread caused by the comparator delay is suppressed. This relaxation oscillator with a typical frequency of 13.4[math]MHz is implemented in a standard 180[math]nm CMOS process. Simulation results show that it achieves a frequency temperature coefficient of 28.3[math]ppm/∘C from [math]C to 125∘C and a 0.074%/0.1[math]V frequency variation when supply voltage changes from 2.9 to 3.7[math]V.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-12-02T08:00:00Z
      DOI: 10.1142/S0218126623501451
       
  • Delay Boundary Analysis of RC Flows in the TTE Switch

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      Authors: Wei Xu, Ruiqi Lu, Fei Peng, Ran Li, Jianmei Lei, Guoqi Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of advanced driver assistance systems (ADASs) and infotainment systems, automotive networks have higher requirements for bandwidth and real-time than before. Time-triggered Ethernet (TTE) supports real-time time-triggered communication and event-triggered communication coexistence. TTE is used as a backbone network in intelligent connected vehicles to meet the growing real-time and reliability requirements. To design a real-time TTE switch, the time delay of data streams needs to be analyzed. Most of the recent works analyze end-to-end latency, which is usually based on a particular integration policy and ignores the impact of BE flows. In this paper, we analyze the delay bounds of RC flows in the TTE switch using delay reachability techniques. We consider the impacts of TT flows, RC flows and BE flows on RC flows based on three integration policies: shuffling, preemption and timely blocking, respectively. We obtain a secure upper limit of delay through analysis. Experiments illustrate the degree of influence of each factor on the delay bound of RC flow, which provides a reference for the optimal design of the TTE switch in intelligent connected vehicles.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-30T08:00:00Z
      DOI: 10.1142/S0218126623501116
       
  • Smooth Nonlinearity Generation with lnCosh and Realization of Chaotic
           Oscillator

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      Authors: Garima Shukla, Sajal K. Paul
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, a new cubic-like smooth nonlinearity is generated by modifying Chua’s piecewise-linear segmental nonlinear function using logarithmic cos-hyperbolic function implementation. A logarithmic cos-hyperbolic function possessing smooth symmetric nonlinear characteristics is implemented through CMOS-based circuit design using the current mode approach. The nonlinear design is then incorporated in a new third-order chaotic oscillator configuration to produce chaotic oscillations. This chaotic circuit is tuned to develop different attractors through the bifurcation parameter. Moreover, the dynamics of chaos such as antimonotonicity and coexistence of attractors are also depicted in circuit simulation by tuning various controlling parameters. Additionally, some numerical analyses are performed on this dynamic system to justify the existence of chaoticity and attractors’ development. This design has been optimized for low-voltage and moderately high dominant frequency of oscillations. Simulations are done using 180-nm CMOS technology in Cadence Virtuoso. Experimental results are presented to verify the workability of the proposed chaotic system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-30T08:00:00Z
      DOI: 10.1142/S0218126623501359
       
  • Frequency Compensation Network for Three-Stage CMOS Operational Amplifier

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      Authors: Masoud Soltani Zanjani, Ali Biabanifard
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The rapid advancements of CMOS integrated circuits technologies lead designers to cascade structures and avoiding cascode amplifiers. As a result, frequency compensation becomes the most important issue since multi-stage amplifiers are highly potential to instability. Here in this work, two differential stages are exploited to form frequency compensation network. These stages realize four Miller loops and share each Miller capacitor in two loops simultaneously. This intensifies Miller effect to improve frequency response due to pole-zero cancellation. The proposed three stage amplifier is modeled symbolically via a transfer function (TF) while 0.18um CMOS technology is used for circuit simulation. Good agreement between theoretical calculation and simulation results shows validity and accuracy of the TF. Also ample simulations are performed to exhibit the proposed amplifier performance against parameters mismatches. The proposed three stage amplifier expresses 105 dB as DC-gain, 4.8 MHz as Gain Band Width and 72 degree as Phase Margin. The amplifier consumes 360 uW as power consumption. This performance obviously is an improvement of Nested Miller Compensation (NMC) while Figure of Merits (FoMs) are enhunced.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-30T08:00:00Z
      DOI: 10.1142/S0218126623501360
       
  • Erratum: Prediction of Elephant Movement Using Intellectual Virtual
           Fencing Model

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      Authors: R. Vasanth, A. Pandian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.

      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-30T08:00:00Z
      DOI: 10.1142/S0218126623920019
       
  • CCII-Based Lossless Floating Frequency-Dependent Negative Resistor with
           Minimum Passive Elements

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      Authors: Tolga Yucehan, Erkan Yuce, Zafer Dicle
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new lossless floating frequency-dependent negative resistor (FDNR). The proposed floating FDNR circuit is designed with two dual output second-generation current conveyors (DO-CCIIs) and a minimum number of passive elements. The first DO-CCII behaves like a minus-type second-generation current conveyor, while the other is modified DO-CCII. The proposed floating FDNR does not require any passive element matching conditions, but all the passive elements are floating. The simulations are made through the SPICE program. A second-order high-pass filter (HPF) is given as an application example. In addition, some experimental results are included for the second-order HPF in which AD844s are utilized.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-28T08:00:00Z
      DOI: 10.1142/S0218126623501244
       
  • Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm
           FINFET Technology for MIMO Applications

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      Authors: A. Venkatesan, P. T. Vanathi, M. Elangovan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7[math]nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7[math]nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-28T08:00:00Z
      DOI: 10.1142/S0218126623501347
       
  • MOSFET-C Shadow Filters Based on FDCCII for Cognitive Communications

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      Authors: Hasan Serdar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In cognitive communications, it is very important to be able to use data in different standards with a single receiver for reducing the cost. In order to achieve this, the application of shadow filters in cognitive communications provides an advantage in terms of having both a wide frequency range and an easy reconfiguration. In this paper, new MOSFET-C shadow filters based on the Fully Differential Second-Generation Current Conveyor (FDCCII) are proposed for cognitive communications. To facilitate electronic tuning of the filter parameters, MOSFET-C-based implementation is used. Fully differential applications increase the dynamic range of analog blocks. Also, fully differential implementations with MOSFET-C filters are useful in analog signal processing. The presented filters have the least number of components and no additional summing circuit. This study presents new FDCCII-based MOSFET-C shadow filters for cognitive communications design that provide HP, LP and BP transfer functions at the same time. In this study, two MOSFET-C shadow filters based on FDCCII are designed for single gain and double gain. The presented filters offer circuit simplicity compared to past shadow filter designs. The features of these new shadow filters are explained. Simulation results are presented to confirm the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-28T08:00:00Z
      DOI: 10.1142/S0218126623501372
       
  • A Novel DDCC-Based Current-Mode Two-Integrator-Loop Active-C Biquad

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      Authors: Remzi Arslanalp
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this study, a novel DDCC-based two-integrator-loop universal active-C biquad with a companding process scheme is proposed. The proposed filter employs some processing blocks such as integrators and summing blocks. The use of the block diagram design procedure is attractive and systematic. The state space synthesis technique is utilized for the topology of the integrator design. Several advantages of the proposed filter are briefly expressed as: simultaneously realizing five second-order filter functions such as low-pass, high-pass, band-pass, all-pass and notch filter responses; offering resistorless realization; dissipating low power; having electronic tunability feature of its pole frequency and quality factor orthogonally; not suffering from disadvantages of the passive element matching problems. Some simulation results including frequency and time domain analysis results by using the PSpice program are carried out to confirm the theoretical ones. All the obtained simulation results are discussed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-28T08:00:00Z
      DOI: 10.1142/S0218126623501402
       
  • Optimization Approach in Window Function Design for Real-Time Filter
           Applications

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      Authors: Fatmanur Serbet, Turgay Kaya
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Eliminating the Gibbs oscillations that occur during the Finite Impulse Response (FIR) digital filter design with the Fourier Series method will ensure correct filtering. For this reason, the development of the window improves the performance of the filter and, therefore, the system. In this study, the cosh window function is designed using Particle Swarm Optimization, which is a preferred optimization method in many areas. Thus, alternatives to the standard results obtained from the existing traditional calculations will be produced, and different windows that perform the same function will be obtained. In addition, exponential and cosh window functions were designed in LabVIEW environment, which is a graphical programming language-based program, and the designed windows were analyzed at different parameter values. LabVIEW provides a fast and easy programming environment, and it provides the opportunity to realize real-time applications with its external hardware. Utilizing this feature, the amplitude spectrum of cosh window designed in LabVIEW is displayed in real time for different window parameter values. As a result, FIR digital filters were designed using cosh window based on optimization and the cosh window designed in LabVIEW, and the distorted EEG signal was filtered using these filters and displayed in real time.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-28T08:00:00Z
      DOI: 10.1142/S0218126623501438
       
  • Simple Yet Secure Encoder Architecture and Ultralightweight Mutual
           Authentication Protocol for RFID Tags in IoT

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      Authors: Manikandan Nagarajan, Muthaiah Rajappa
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Internet of things (IoT) has evolved as the internet of everything, and it has grabbed the interest of all the researchers in recent days. Almost all the objects, including nonelectronics devices, can also be connected with the internet through radio frequency identification (RFID) technology. The security of the perception layer is crucial to secure the entire IoT network. RFID-enabled IoT perception layer has secured reader-to-server channel and unsecured tag to reader channel. Hence, securing the unsecured communication channel between the reader and the tag is the need of the hour. This work proposes a simple yet secure permutation approximate adder (SYSPXA)-based RFID mutual authentication protocol to address the need. The proposed protocol dramatically reduces the tag’s storage and computational overhead. It needs 40% less storage and 66.7% less permutation operation in comparison with the existing protocols. Nondisclosure of the key and freshness of key, IDS and random numbers at every mutual authentication process gives resistance to the protocol against de-synchronization attack, disclosure attack, tag tracking, replay attack. The SYSPXA protocol is validated for its security features using Burrows–Abadi–Needham (BAN) logic formal verification. The performance and security of the proposed protocol are contrasted with various futuristic permutation-based protocols, and its superiority over other protocols is highlighted. We have simulated the SYSPXA protocol with ModelSim tool for verifying its functionality. The protocol encoder architecture is implemented in the Intel cyclone IV Field Programmable Gate Array (FPGA) EP4CE115F29C7 device.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-25T08:00:00Z
      DOI: 10.1142/S0218126623501189
       
  • A Novel Random Number Generator and Its Application in Sound Encryption
           Based on a Fractional-Order Chaotic System

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      Authors: Ömer Faruk Akmeşe
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Random number generator design is one of the practical applications of nonlinear systems. This study used random number generation and sound encryption application with a fractional chaotic system. Random numbers were generated with the Langford chaotic system, and a sound encryption application was carried out for the secure transmission of voice messages. Randomization performance of numbers was evaluated by employing NIST-800-22 statistical tests, which meet the highest international requirements. It was observed that the distributions of these generated random numbers reached the desired level of randomness after the examination. Unlike the integer-order random number generators widely used in the literature, the fractional-order Langford chaotic system was employed to generate and analyze random numbers and demonstrate their utilization in sound encryption. Random numbers generated from a fractional degree-based chaotic system developed in this study can be used in cryptology, secret writing, stamping, statistical sampling, computer simulations, dynamic information compression and coding.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-25T08:00:00Z
      DOI: 10.1142/S021812662350127X
       
  • Implementation of a New Versatile Bio-Potential Measurement System

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      Authors: Hafed-Eddine Bendib, Mebarek Bahri, Mohamed Boumehraz, Ali Mallem, Marwa Hamzi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel system for measuring bio-potentials, including electroencephalography (EEG), electrocardiography (ECG) and electromyography (EMG) signals, was implemented. This system is based on the high-precision (24-bit) analog front-end ADS1299 with eight input channels. The aim of this work is to provide a low-cost platform for researchers in neuroscience, brain–computer interfaces, ECG pattern recognition and myoelectric control for Robotic Hand-Assisted Training, etc. Compared to the existing systems, this design uses a module called ESP-WROOM-32 based on a 32-bit dual-core Xtensa LX6 microprocessor in which all control and communication functions have been integrated into a single package, giving the possibility to interface the system with the Raspberry Pi via the USB interface or via the wireless interface (Wi-Fi and Bluetooth). The paper presents a detailed study of the system in terms of hardware and software implementation. In addition, an experimental process has been conducted with the aim of evaluating the proposed prototype. With a common mode rejection ratio higher than 110[math]dB and an input referred noise less than 2[math][math]V (peak-to-peak) as well as the good quality of the measured biopotentials during all the proposed scenarios, the model can be qualified to be functioning properly following the recommendations of the ADS1299 manufacturer. Finally, a conclusion is made to summarize the results achieved while highlighting the future study and the suggestions for improving the presented design.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-25T08:00:00Z
      DOI: 10.1142/S0218126623501281
       
  • Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in
           Modern FPGA

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      Authors: Vivek Kumar Singh, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to technological advancements and voltage scaling, leakage power has become an important concern in CMOS design. The implementation of a field-programmable gate array (FPGA) circuit utilizes a portion of the FPGA’s resources as compared to an application-specific integrated circuit (ASIC). Both the utilized and unutilized parts of the FPGA dissipate leakage power. In this work, two dynamic power gating techniques, PSG-1 and PSG-2, are proposed, which are able to reduce the leakage power of the 6-input look-up table (LUT) used in the Xilinx Spartan-6 series. The obtained results show that the proposed approaches PSG-1 and PSG-2 reduce average leakage power by 54.61% and 66.69%, respectively, at the expense of nominal area and delay overhead. The proposed method is also capable of lowering the average total power of the 6-input LUT. The suggested PSG-1 and PSG-2 approaches reduce average power by 53.75% and 60.83%, respectively. However, header-based power supply gating is extremely vulnerable to the negative-bias temperature instability (NBTI) aging effect and, due to this, the lifetime of the circuit is reduced considerably. Therefore, in this work, lifetime estimation-based analysis is performed by varying the stress probability of the sleep transistor. The results show that the LUT with PSG-1 and PSG-2 techniques has a lifetime of 4.55 years and 11.13 years, respectively. The stress time of the sleep transistor is 50% for the PSG-1 technique and 25% for the PSG-2 technique, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-24T08:00:00Z
      DOI: 10.1142/S021812662350113X
       
  • Dimensionality Reduction with Weighted Voting Ensemble Classification
           Model Using Speech Data Based Parkinson’s Disease Diagnosis

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      Authors: A. Manjula, P. K. Vaishali, P. Pranitha, S. Ashok Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Parkinson’s disease (PD) is a progressive neurodegenerative illness that frequently affects phonation, articulation, fluency, and prosody of speech. Speech impairment is a major sign of PD which can be employed for the earlier identification of the disease and provide proper treatment. Besides, the machine learning (ML) models can be commonly employed for PD detection and classification by the use of speech data. Since the speech data has the features of maximum data redundancy, high aliasing, and small sample sizes, dimensionality reduction (DR) techniques become essential for effective PD diagnosis. Therefore, this paper presents a new DR with weighted voting ensemble classification (DR-WVEC) model for PD diagnosis. The presented DR-WVEC model operates on different stages such as pre-processing, DR, classification, and voting process. Primarily, the speech data undergoes min–max normalization process in order to normalize the speech data. Besides, linear discriminant analysis (LDA) technique is applied for reducing the dimensionality of the features. In addition, an ensemble of two ML models, namely extreme learning machine (ELM) and Adaboost models, is employed for classification. Finally, a weighted voting-based classification process is carried out where the integration of two ML models takes place and the highest outcome is chosen as the final results. In order to assess the effective PR diagnostic outcome, an extensive set of simulations were carried out on Parkinson’s telemonitoring dataset. The obtained experimental results reported the betterment of the DR-VWEC technique over the other compared methods in terms of different aspects.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-24T08:00:00Z
      DOI: 10.1142/S0218126623501207
       
  • Differential Input First-Order Universal Filter with Two DVCC+s

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      Authors: Tayfun Unuk, Erkan Yuce, Shahram Minaei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a differential-input plus-type differential voltage current conveyor-based first-order universal filter is designed. This voltage-mode filter uses a grounded capacitor. In addition, it can provide all the noninverting and inverting first-order universal filter responses. The circuit provides high common-mode rejection ratio of about 76.5[math]dB. Nevertheless, it needs a single matching problem and comprises two floating resistors. Quadrature oscillator (QO) design is obtained using this filter as an application example. The designed filter and QO circuits are simulated through the SPICE program, and some experimental studies are carried out using AD844 ICs to verify the theory.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-24T08:00:00Z
      DOI: 10.1142/S0218126623501220
       
  • Characteristic Analysis of a Square Diaphragm Capacitive Pressure Sensor
           with Linkage Film

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      Authors: P. K. Sreekanth, Sumit Kumar Jindal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Capacitive pressure sensors (CPSs) have become more prevalent compared to the piezoresistive pressure sensors because they generate superior sensitivity and better linearity for the same application. Due to the innumerable use cases of the CPSs, it is becoming increasingly critical to carry out efficient analysis for their modeling. The higher sensitivity of a square diaphragm for the same side length in comparison to a circular diaphragm makes it ideal for sensor design. In this work, a complete formulation for analysis of a CPS with a square diaphragm having a linkage film has been presented. A comprehensive study of sensor parameters like capacitance, deflection of the diaphragms, capacitive and mechanical sensitivity has been formulated to aid the choice of sensor characteristics. This work also focuses on the method to determine the fundamental design parameters for optimal operation. Complex and resource-expensive methods have been used in the past for the analysis of MEMS capacitive pressure sensors. MATLAB and ANSYS have been used to compute and simulate the results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-24T08:00:00Z
      DOI: 10.1142/S021812662350130X
       
  • Design and Development of Microbial Fuel Cells Based Low Power Energy
           Harvesting Mechanism for Ecological Monitoring and Farming of Agricultural
           Applications

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      Authors: P Suganya, J Divya Navamani, A Lavanya, Rishabh Mrinal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Energy harvesting from the microbial fuel cells have a significant attention in the recent days, due to their cost efficiency, simple designing structure and self-powered system. Also, the emergence of internet of things plays a vital role in many real time application scenarios like agricultural purposes and activities. But, the incorporation of these techniques is one of challenging and interesting tasks in the research field. In the conventional works, the internet of things has been utilized as a cloud storage domain for activating the sensors used for environmental monitoring and controlling purposes. The main intention of this paper is to design a robust and cost-effective sludge water based microbial fuel cells, and utilize it for an internet of things incorporated ecological monitoring and farming applications by activating the smart sensors. It discusses about the various electrode combination with several mixture of substrate to study about the optimum performance of microbial fuel cells. To ease the comparative study, Thing Speak platform is used along with the necessary sensors for continuous monitoring. In addition to that, the efficiency of single and dual chamber microbial fuel cell is analyzed based on the set of parameters such as cost, size, and construction. In this work, the microbial fuel cell-based energy harvesting scheme is also developed with switched capacitance-based metal oxide semiconductor field effect transistor and relay-based charge pump circuit which can be incorporated to the internet of things based agriculture applications. Here, the cost analysis of microbial fuel cell with and without DC–DC converter have been compared for selecting the most suitable one for the application system. Moreover, the digital temperature and humidity sensor can be utilized with the proposed microbial fuel cell system for gathering the inputs of the ecological system, which acts as an interface of the microbial fuel cell and cloud systems. During experimentation, the results of both the energy harvesting schemes are evaluated and compared by using various performance indicators.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-23T08:00:00Z
      DOI: 10.1142/S0218126623501128
       
  • A Novel Training Quantitative Evaluation Method Based on Virtual Reality

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      Authors: Baotong Jia, Xiaoli Wu, Chunmei Zhao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Quantitative training virtualization can be applied in the fields of human–computer interaction, virtual reality and motion analysis, and has attracted much attention. Based on the virtual reality theory, this paper constructs a training quantitative evaluation method, evaluates the trainer’s ergonomics, and finally compares the evaluation method with the simulation results. According to the collected training data, this paper uses the methods of model reuse and feature parameter adjustment in the Jack software to quickly generate a 3D training model with the required percentages, and performs data reorganization and analysis on the captured training data, which solves the problem of training quantitative evaluation and the problem of uncertainty of results. During the simulation process, according to its reorganized data, a large number of comparative experiments and evaluations were performed on the performance of the model proposed in this paper on multiple indicators of multiple public data sets. The experimental results show that the cycle is reduced by 10 times, the mini-batch is 32, and the sequence length is 16. In this way, the spatial characteristics of the channel coupling relationship can be better analyzed, and the effect of spatial cognitive training can be effectively evaluated. The training pose and shape estimation model and the corresponding data set and multiple indicators have reached the performance of the existing state-of-the-art models. The integrated model of accurate training pose and shape sequence in the camera coordinate system can be reconstructed, which effectively enhances the effectiveness of the virtual scene parameter adjustment strategy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623500706
       
  • A Novel Nonisolated Quasi Z-Source Multilevel Inverter for Solar
           Photovoltaic Energy System Using Robust Technique: An ICSA–RPNN
           Technique

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      Authors: R. Santhi, A. Srinivasan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An efficient method primarily depending on nonisolated quasi Z-source (QZS) novel multilevel inverter (NIQZS-NMLI) topology to interconnect photovoltaic (PV) system is proposed in this paper. The proposed hybrid system is the combination of improved chameleon swarm algorithm (ICSA) and recurrent perceptron neural network (RPNN), hence it is named as ICSA–RPNN. Usually, the interface among the PV DC supply, the load is achieved through an NIQZS-NMLI topology. Here, the NIQZS-NMLI topology modeling design is increased with the new storage device to supply the largest amount of power from the PV power production system. The number of switches and full harmonic distortion of the machine are reduced through the NMLI topology, and it is used to achieve better upgrading capability, and reduce the voltage pressure on the entire active switching device has a better modulation index. At first, the objective function is described primarily depending on its controller parameters and control voltages, current, power, and modulation code. These parameters are useful to the inputs of the proposed ICSA-RPNN approach. The ICSA-RPNN methodology enhanced the voltage profile, reducing power distribution, power oscillations simultaneously distributing power to the load. The modulation load is controlled by proposed artificial intelligence (AI) mainly depends on the NIQZS-NMLI topography. In addition, the ICSA-RPNN methodology reduces the injected power, controls the voltage, current and frequency conditions of the DC hyperlink. The ICSA-RPNN approach is performed at MATLAB/Simulink site and the general performance of the output is compared to the existing systems for different load conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623501049
       
  • Fast Bipartite Synchronization of Complex Networks with Signed Graph Based
           on TS Fuzzy System by Fixed-Time Technique

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      Authors: Dongmei Ruan, Shiju Yang, Qin Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper mainly discusses the problem of fast fixed-time bipartite synchronization in the complex networks with signed graph that is based on TS fuzzy system. By designing suitable and effective controller, the synchronization of the considered complex networks has been achieved successfully in this paper, whose convergence rate is superior to the great majority of existing results. With the assistance of a comparison system being built and using the theory of Lyapunov stability, this paper has established sufficient criteria successfully that are able to achieve fast fixed-time bipartite synchronization. And a numerical simulation example displays the performance of the obtained new results at the end of this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623501190
       
  • Distributed Logistics Resources Allocation with Blockchain, Smart
           Contract, and Edge Computing

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      Authors: Junhua Chen, Jiatong Zhang, Chenggen Pu, Ping Wang, Min Wei, Seungho Hong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The traditional centralized logistics resources allocation method can no longer adapt to the new business model of decentralized e-commerce, requiring transaction security for all parties involved in the logistics process. Utilizing blockchain and smart contract technologies to build logistics resources allocation network foundation and edge computing technology to assist the resource-constrained transport nodes in implementing complex computation, this paper proposes a distributed logistics resources allocation chain (DLRAChain) concept and designs a DLRAChain network that supports independent decision-making, fair bidding, and secure allocation of interests for all resources allocation participants. The corresponding system models are constructed according to the different roles of DLRAChain participants. Furthermore, the logistics resources requester–provider negotiation process is formulated as a two-stage Stackelberg game. To resolve the optimization problem of the game, the iterative game algorithm (IGA) and distributed logistics resources allocation algorithm (DLRAA) are proposed. Finally, the utility of warehouse and transport nodes and reward of mobile edge computing (MEC) nodes are analyzed with experimental simulation results. The results demonstrate that the proposed models adequately address the DLRA problem, and that the proposed game and corresponding algorithms efficiently achieve the optimal strategy, saving the response time of resources allocation participants.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623501219
       
  • New FTFN-Based Tunable Memristor Emulator Circuit and its Mutation to
           Meminductor and Memcapacitor Emulators

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      Authors: Kapil Bhardwaj, Ravuri Narayana, Mayank Srivastava
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      For the first time, a new memristor emulator structure using a single four-terminal floating nullor (FTFN) and a transconductance stage has been presented with tunable circuit configuration. Along with that the circuit requires only a single grounded capacitance and two external MOS transistors to realize both incremental and decremental types of memductance functions. The use of the FTFN block has been demonstrated for the first time to build such a compact memristor emulator, which fully utilizes the employed circuit resources. The wide-band operating frequency range (1[math]kHz–3[math]MHz) is another attractive feature of the proposed emulator. Moreover, the mutation of the proposed memristor emulator into meminductor and memcapacitor emulators is also presented by the mutators based on FTFN. All the presented circuits have been tested by performing simulations using PSPICE with 0.18-[math]m CMOS technology. The generated simulation results clearly show the ideal nonvolatile nature of the realized memristor, which has also been utilized in an op-amp-based circuit designed to exhibit associative learning phenomena. The proposed FTFN-based memristor has been implemented using commercially available ICs, LM13700, and AD844, and the generated PHL plot is discussed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623501232
       
  • Multi-Modal Emotion Recognition Combining Face Image and EEG Signal

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      Authors: Ying Hu, Feng Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Face expression can be used to identify human emotions, but it is easy to misjudge when hidden artificially. In addition, the sentiment recognition of a single mode often results in low recognition rate due to the characteristics of the single mode itself. In order to solve the mentioned problems, the spatio-temporal neural network and the separable residual network proposed by fusion can realize the emotion recognition of EEG and face. The average recognition rates of EEG and face data sets are 78.14% and 70.89%, respectively, and the recognition rates of decision fusion on DEAP data sets are 84.53%. Experimental results show that compared with the single mode, the proposed two-mode emotion recognition architecture has better performance, and can well integrate the emotional information contained in human face visual signals and EEG signals.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623501256
       
  • A Robust Two-Step Modulus-Based Matrix Splitting Iteration Method for
           Mixed-Size Cell Circuit Legalization Problem

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      Authors: Chen-Can Zhou, Yang Cao, Quan Shi, Jie Qiu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As semiconductor manufacturing moves into the nanotechnology era, mixed-size standard cell circuit designs have become mainstream, but they also pose significant challenges to placement. To address the mixed-size standard cell circuit legalization problem, in this paper, we first formulate it as a quadratic programming problem with nonnegative constraints, resulting in an equivalent linear complementarity problem (LCP). In particular, the system matrix involved in the LCP is positive semi-definite, so we perturb it to a positive-definite matrix. Then, we cast the linear complementarity problem as an equivalent implicit fixed-point equation. To improve the convergence rate of the class of modulus-based matrix splitting iteration method (MMS), we develop a robust two-step MMS to solve the fixed-point equation. Finally, we analyze the convergence property and illustrate the approximation of the solution between the perturbed LCP and the original LCP. Numerical experiments for the legalization problem are provided, and the results reveal that our approach is competitive with the existing state-of-the-art methods for solving mixed-size cell circuit legalization problems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-19T08:00:00Z
      DOI: 10.1142/S0218126623501293
       
  • An On-Board Task Scheduling Method Based on Evolutionary Optimization
           Algorithm

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      Authors: Feng Dan, Liu Bo, Gong Jian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to meet the requirements of task scheduling in on-board distributed computing environment, an evolutionary optimization scheduling method for on-board tasks was proposed based on the on-board dynamic heterogeneous computing resource model and task model. In this method, task scheduling priority coding was used to adapt to dynamic changes of computing resources. Heuristic critical path for comprehensive index balance was adopted to implement the evaluation, so as to achieve a balance between task makespan, power consumption and reliability. Multi-group neighborhood search strategy was applied to avoid the algorithm falling into local optimization and simplify the complexity of scheduling algorithm. Fault-tolerant strategy of convergence monitoring and stop loss reconfiguration were designed for scheduling unit fault tolerance. Scheduling strategy based on active and backup redundant subtasks was used for computing unit fault tolerance. The simulation results showed the efficiency of this method to deal with the scenario of on-board distributed computing resources and implement the optimal scheduling of on-board tasks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-16T08:00:00Z
      DOI: 10.1142/S0218126623501001
       
  • Intrusion Detection for In-Vehicle CAN Bus Based on Lightweight Neural
           Network

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      Authors: Defeng Ding, Yehua Wei, Can Cheng, Jing Long
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of automobile intelligent and networking, substantial information is exchanged between in-vehicle network system and the outside world, thereby threatening the automobile security. Intrusion detection is an important technology to realize the security of in-vehicle networks. The existing research on in-vehicle network intrusion detection mainly focuses on the improvement of detection accuracy, but it lacks consideration of timeliness, whereas the in-vehicle network is a time-sensitive system. This study proposes an anomaly detection method for in-vehicle Controller Area Network (CAN) based on lightweight neural network to reduce the operation time while maintaining the detection accuracy. The redundant neuron screening method and model compression algorithm for layer-by-layer neuron pruning are designed. This presented method can delete the neurons with small contribution and obtain lightweight neural network model. The detection performance of model compression and noncompression is compared through experiments. Results show that under the two real in-vehicle datasets, the detection time is accelerated by 47.7 times and 34.2 times at most, and the average accuracy is increased by 14.5% and 15.7%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-16T08:00:00Z
      DOI: 10.1142/S0218126623501104
       
  • Risk Assessment and Prediction of Underground Utility Tunnels Based on
           Bayesian Network: A Case Study in Beijing, China

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      Authors: Yongjun Chen, Xiaojian Li, Wenjuan Wang, Guangye Wu, Lulin Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The underground utility tunnels accommodate various types of urban lifelines, which are of great significance for improving the living standards of the citizens. With the rapid development of underground utility tunnels, the large-scale underground utility tunnel systems are gradually becoming the operational lifeblood of China’s large cities. Currently, most of the underground utility tunnels’ risks are estimated and analyzed from a static perspective, and the analysis results are one-sided. This study proposes a dynamic risk evaluation framework. A risk assessment and sensitivity analysis framework based on Bayesian network is established in this study. Combined with the groundwater and electric tunnel risk accident case study, the operation and maintenance data of Beijing Future Science and Technology City from 2010 to 2018 are collected for learning to obtain the conditional probability of the Bayesian network node by using the K2 algorithm. The overall evolution process from the beginning to the end of groundwater tunnel accidents is clearly described and displayed. Through sensitivity analysis and critical path analysis, the critical points of an accident and the probabilities of risk occurrence are identified and predicted. This proposed framework could facilitate the underground utility tunnel management for controlling risk resources, mitigating risk damage and reducing risk losses.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623500962
       
  • 2.4 GHz LoRa Wireless Technology for Internet of Things: An Experimental
           Study

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      Authors: Haibo Luo, Zhiqiang Ruan, Lianghui Xiao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      LoRa is a new low data-rate modulation technology for wireless communication, which uses spread spectrum communications to increase transmission distance. At present, sub-GHz LoRa is mainly used to build LoRaWAN and is applied to the monitoring and data collection of the Internet of Things (IoT). Focusing on the latest 2.4 GHz LoRa technology, this study introduces the characteristics of 2.4 GHz LoRa in the physical layer and experimentally analyzes the basic performance of communication, energy consumption, and ranging. Meanwhile, for the deficiencies of time on air in the evaluation of effective data rate, this study proposes the concepts of time on PHY and time of transmission (ToT). Then, the ToT duration of 2.4 GHz LoRa under different parameter configurations is calculated. Finally, combined with the physical-layer characteristics of 2.4[math]GHz LoRa, four potential networking topologies of the 2.4[math]GHz LoRa are listed, and their characteristics and application scenarios are analyzed. Compared with sub-GHz LoRa, 2.4[math]GHz LoRa is more applicable for building self-organized networks and worldwide IoT solutions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623501013
       
  • A Secure Two-Tier Domain Verification and Certificate Validation
           Integrating Intermediate Certificate Authorities and Secure Certificate
           Box

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      Authors: P. P. Rahoof, Latha R. Nair, V. P. Thafasal Ijyas
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Digital certificates play a key role in the public key infrastructure (PKI). They are mainly used to secure communication between a browser and a webserver to keep the transmitted data safe from interception. Digital certificates are issued by certificate authorities (CAs). Numerous CAs serve as root CAs around the world. Moreover, root CAs can delegate intermediate CAs (ICAs). Any CA can issue a certificate for any entity on the internet world. However, it will be difficult for an end user to identify which authorities are trustworthy and genuine. In addition, adversaries can quickly induce fraudulent certificates due to a lack of rigorous background checks for domain possession at the time of certificate issuance. Our work is primarily oriented towards incorporating the domain validation and certificate validity check from the client side as an additional security fortification. This is in addition to a novel associative approach for domain validation using ICAs. This paper presents a novel two-tier system for domain validation of servers. The system operates at two levels. At the first level, an associative validation of the domains by making use of multiple ICAs is employed. A set of CAs validates domain ownership before issuing the certificate to prevent false issuance of the certificate. In addition to this, during the initiation of the client–server connection, the client itself validates the certificate to make sure that the certificate received securely from any webserver is a genuine one.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623501037
       
  • An Integrated Circuit Based, Single-Inductor-Dual-Output Buck LED Driver
           for Dimmable and Color Temperature Tunable Indoor Lighting Application

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      Authors: Biswadeep Gupta Bakshi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Tunability of correlated color temperature (CCT) and dimmability are the two major sought after features of functional solid-state lighting. This paper presents a low-cost, efficient, single-inductor-dual-output buck driver that facilitates CCT-control and dimming of a light emitting diode (LED) module composed of cool-white and warm-white chips. The proposed driver is designed based on two familiar integrated circuits (ICs), namely LM2596 and NE556. LM2596 serves as the main switching regulator and amplitude modulation (AM) controller whereas NE556 serves as the constant-frequency, dual-output pulse-width-modulation (PWM) controller. The exponential model of LED is exploited for improved estimation of the design parameters of the LED module and the driver circuit. The developed driver prototype is tested for its electrical, photometric, and colorimetric performances. The driver offers a full-load efficiency of about 90% for a 12-W test LED module. Under different operating modes, the LED system can produce warm, cool, or neutral white light and at the same time, the produced illuminance can be varied over a wide range. Moreover, the light flicker is imperceptible since the PWM frequency is set according to IEEE-1789 guideline.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623501062
       
  • Improved Seven-Level Multilevel DC-Link Inverter with Novel Carrier PWM
           Technique

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      Authors: Sreelakshmi Sanka, M. S. Sujatha, Jammy Ramesh Rahul
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multilevel inverters have emerged as a viable alternative for various power electronic applications. It offers significant features in terms of reduced total harmonic distortion (THD) due to more number of output voltage levels, lower filter size, and voltage stress and reduced switching losses when compared to conventional two-level inverters. The classical topologies such as neutral point clamped, flying capacitor and cascaded H-bridge (CHB) are very popular for industrial applications. All these topologies have limitations in terms of more component count, capacitor voltage balancing for increased number of voltage levels. In this regard, multi-level DC link (MLDCL) inverter has been introduced as an improvement with respect to CHB MLI in terms of reduced switch count and is considered here for the study. This paper presents a single-phase MLDC link inverter with a modified carrier-based level-shifted phase disposition sinusoidal pulse width modulation (LS-PD-SPWM) technique. The proposed novel carrier PWM is compared with the conventional modulation techniques in terms of THD. The performance of the proposed modulation technique is analyzed through simulation studies in MATLAB software. A laboratory prototype model is developed in order to validate the experimental results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623501086
       
  • A Parallel Text Recognition in Electrical Equipment Nameplate Images Based
           on Apache Flink

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      Authors: Zhen Liu, Lin Li, Da Zhang, Liangshuai Liu, Ze Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Information on the equipment nameplate is important for the storage, transportation, verification and maintenance of electrical equipment. However, because a natural image of the device on the text nameplate may be multidirectional, curved, noisy or blurry, automatically recognizing the image from the device nameplate can be difficult. Meanwhile, image preprocessing methods are carried out in a serial manner, so the processing speed with regard to the above problems is slower and takes a longer time. Accordingly, this study proposes a parallel and deep-learning-based text automatic recognition method. In the proposed method, a pretreatment method comprising edge detection, morphological manipulation and projection transformation is used to obtain the corrected nameplate region. The connectionist text proposal network (CTPN) is then activated to detect text lines on the corrected nameplate area. Next, a deep-learning method is proposed to study the classification methods of convolutional recurrent neural networks and connectionist time classification for identifying text in each line of text detected by CTPN. Finally, we use Apache Flink to parallelize the above processes, including parallelization preprocessing and bidirectional long short-term memory parallelization in the process of text line detection and text recognition. Experimental results on the collected nameplate show that the proposed imaging processing method has a good recognition performance and that the parallelization method significantly reduces the data processing time cost.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623501098
       
  • Framework for QCA Layout Generation and Rules for Rotated Cell Design

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      Authors: Raja Sekar Kumaresan, Marshal Raj, Lakshminarayanan Gopalakrishnan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Quantum-dot Cellular Automata (QCA) is a nontransistor-based nanotechnology circuit design paradigm. The circuits are implemented by using cells having quantum dots and electrons. There are several cell configurations with varying combinations of electrons and quantum dots. But the widely used cells have the four-dot two-electron structure. Circuits are realized and validated by using QCADesigner. However, the layouts are developed manually by using this tool. Layouts are not entirely automated in QCA. Hence, in this work, the existing QCA tools and the different techniques proposed in the literature to improve the QCA layout generation are analyzed and a complete framework for QCA layout generation is proposed. It also explores the gap that needs to be filled to achieve a reliable CAD tool for QCA layout generation. In addition to that, to design circuits using rotated cells, design rules and cost functions are proposed. Novel circuits of multiplexer and D-flip-flop are also proposed using rotated cells. The proposed designs have better output polarization compared to other designs. Verification is done in QCADesigner.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-14T08:00:00Z
      DOI: 10.1142/S0218126623501141
       
  • An Online Education Course Recommendation Method Based on Knowledge Graphs
           and Reinforcement Learning

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      Authors: Honglei Guan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an in-depth study and analysis of online education course recommendations through a knowledge graph combined with reinforcement learning, and proposes a deep learning-based joint extraction method of course knowledge entities and relations in the education domain. This joint extraction method can extract both course knowledge entities and their relationships from the unstructured text of online courses, thus alleviating the problem of error propagation. On the other hand, since some parameters in the joint model can be shared by the entity identification task and the relationship classification task, this helps the model to capture the interaction between the two subtasks. Similar courses are judged based on the extracted course knowledge points, while course knowledge chains are generated based on the relationships between course knowledge points. In terms of user learning behavior, by analyzing user online learning behavior data, this paper uses five variables, namely the number of learning hours, the number of discussions, the number of visits, the number of task points completed, and the number of learning courses, to judge and cluster user similarity using an information entropy-based learner behavior weight assignment method. Based on the course knowledge map, this paper firstly constructs a learner model with four dimensions of basic learner profile, cognitive level, learning style, and historical learning records. Secondly, it predicts the target knowledge points of learners based on their learning data using the Armorial algorithm and maps them in the knowledge map, then uses natural language processing related techniques to find the conceptual similarity between knowledge points and proposes a deep recommendation strategy based on the knowledge graph correlations. At the same time, the recommended courses based on learners’ behavioral data are more relevant and accurate, which greatly improves learners’ efficiency and satisfaction in the learning process.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-10T08:00:00Z
      DOI: 10.1142/S0218126623500998
       
  • An SM9-Based Secondary Authentication Framework for 5G Technology

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      Authors: Rui Wang, Xin Liu, Donglan Liu, Hao Zhang, Lei Ma, Yong Wang, Han Liu, Jianfei Chen, Zhenghao Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As the latest generation of cellular mobile communication technology, the fifth-generation (5G) mobile communication technology is proposed to build a network-based society. As a result, industry and academia are placing great emphasis on security research for 5G technology. 5G technology has higher security requirements than previous systems and the secondary authentication is an important technology to ensure the security of 5G. In this paper, we propose to incorporate the SM9 encryption algorithm with 5G secondary authentication to provide higher security assurance. Due to the high computational overhead of the SM9 algorithm, we further propose an acceleration strategy for the SM9 algorithm based on the non-adjacent form (NAF) representation method to improve the performance of the entire system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-09T08:00:00Z
      DOI: 10.1142/S0218126623500949
       
  • Application of Uncertain Programming in Hardware/Software Partitioning:
           Model and Algorithm

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      Authors: Si Chen, Lida Huang, Guoqi Xie, Renfa Li, Keqin Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Hardware/software partitioning is a typical multi-stage decision optimization problem; most existing hardware/software partitioning methods ignore a fact that real-life decisions are usually made in an uncertain state. We should model the hardware/software partitioning problem in uncertain environments and deal with uncertainty. The state-of-the-art work proposed an uncertainty conversion method for hardware/software partitioning, but this method does not include the equivalent deterministic model and is not suitable for dealing with different types of uncertainties. In order to cope with different situations with various uncertainties, we should apply uncertain programming to build a model in uncertain environments and give different equivalent deterministic models to convert different uncertainties theoretically. In this paper, we present the process of applying uncertain programming to solve the hardware/software partitioning problem, including the model and algorithm. We convert the uncertain programming model into its equivalent deterministic models, including the expected value model and the chance-constrained programming model; we give details for the conversion methods of these two models. We present the custom genetic algorithm to solve the converted model, by incorporating a greedy idea in two steps of the genetic algorithm. Experimental results show that the custom genetic algorithm can find a high-quality approximate solution while running much faster for large input scales, compared with the exact algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-09T08:00:00Z
      DOI: 10.1142/S0218126623501050
       
  • Prediction of Elephant Movement Using Intellectual Virtual Fencing Model

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      Authors: R. Vasanth, A. Pandian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The capability to navigate and orientate is crucially a significant factor to determine the survival of all migratory animals like elephants. The sustainability of animals is constrained with a limited amount of techniques available for analysis of complex animals’ behavioral responses. Various approaches are used to track animals’ movement like elephants crossing the railway track, roads have to be varied based on the degree of accuracy that is needed essentially. However, the existing approaches fail to trigger an alert in some cases. To overcome these limitations, a novel Intellectual Inertial Measurement Unit (IIMU) is proposed where the data are acquired from the aerial elephant dataset with a set of training and testing image samples. Data collected with these dataset are analyzed for triggering Virtual Fencing (VF) and to alert animals to avoid danger. This work attempts to validate that this IIMU installed with animals’ bodies can be used to evaluate patterns related to the animal’s movement. The collected data are provided for filtering using Levenberg Marquardt Algorithm to reduce the noise over the data and to enhance the prediction accuracy. The pattern set undergoes training with Artificial Neural Network (ANN) and optimized with Elephant Optimization to evaluate the prediction accuracy. Based on the evaluation, the model shows better prediction accuracy in case of emergency and alert is triggered to save the life of elephants. Here, some performance metrics like accuracy, precision, F-measure, recall, ROC are evaluated to show the significance of EPO-ANN model. The model outperforms the existing standard SVM model and gives higher prediction accuracy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-11-09T08:00:00Z
      DOI: 10.1142/S0218126623501074
       
  • A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency
           Ranges

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      Authors: Yushi Chen, Yiqi Zhuang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A radiation-hardened delay-locked loop (DLL) applied for multiple frequency ranges is proposed in this paper. Novel and effective radiation-hardened techniques are applied in charge pump (CP) and voltage-controlled delay line (VCDL) to avoid inverted lock error and missing pulses error caused by single-event transient (SET). In order to ensure a wide operation frequency range, a frequency detection module is designed to detect the frequency of input signals and adjust the current source array of VCDL so as to change its delay time. Besides, an accelerate module is designed to reduce the lock time of DLL by providing an extra discharge current. According to the simulation results, the proposed DLL shows good performance when ion strikes occur and can work properly in a wide operation frequency range from 3.7[math]GHz to 7.4[math]GHz. Also, the proposed accelerate module helps to reduce lock time by 22.2%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-29T07:00:00Z
      DOI: 10.1142/S0218126623500974
       
  • A Comparative Study on CORDIC Algorithms and Applications

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      Authors: Ankur Changela, Mazad Zaveri, Deepak Verma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Jack Edward Volder had introduced the CORDIC (COordinate Rotation DIgital Computer) in 1959. This year, critical development and advancement of the CORDIC algorithm have reached 62 years. The VLSI implementation of the CORDIC requires simple hardware (of the form add–shift), which makes CORDIC the most suitable building block for many real-time applications. The sequential nature of the CORDIC computation and scale factor are crucial aspects to be considered as they limit the overall performance of the algorithm. In this work, we have studied the various CORDIC algorithms and their architectures which improve the performance of the standard radix-2 CORDIC algorithm. This comparative study aims to provide first-order information on CORDIC algorithm implementations, including their potential applications. In addition, the study also reflected the works done by numerous researchers and highlighted the limitations of the existing architectures and algorithms, and executed the assessment using various parameters such as convergence range, number of iterations required to achieve the complete rotation, and hardware resource complexity to implement [math]/[math] rotator, [math] rotator, and scale factor compensation. We have also carried out error analysis of various CORDIC algorithms in terms of root-mean-squared error (RMSE) and peak signal-to-noise ratio (PSNR). The number of iterations, scale factor, and the sequential computing of the micro-rotations can be identified as significant improvement areas of the CORDIC algorithm and modifications are required for real-time applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623300027
       
  • Computer Vision-Based Cashew Nuts Grading System Using Machine Learning
           Methods

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      Authors: A. Sivaranjani, S. Senthilrani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a computer vision-based cashew nut grading system has been designed and implemented for classifying different grades of cashew nuts using combined features and machine learning approaches. The important task in the cashew nut grading system is to classify the whole and split down cashew nuts. Since these cashew nuts look very similar from the top view, it is a challenging task to classify the whole cashew nut and split down cashew nuts. Hence, a single-view image of cashew nut has been captured by placing a camera with a distance of 17[math]cm (from the right side of the conveyor belt). The captured red, blue and green images are normalized and converted into hue, saturation and value color space. S channel from HSV image is used for segmentation process using Otsu threshold technique. The total numbers of features extracted are 275 and the features are texture (180), color (90), and shape (5). The constrained optimization-based feature selection method is used and 30 features are selected for further process. The Support Vector Machine (SVM) classifier is used for the classification, and the results obtained from different kernel functions are computed and compared. The 8-layer convolutional neural network (CNN) has been developed in this work for classification and to analyze the performance and accuracy. The accuracy of different machine learning classifiers like SVM 1-1, SVM 1-All and CNN model is also evaluated and compared. The overall accuracy obtained by SVM 1-All with kernel function radial basis for classification is 98.93%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623500494
       
  • Research on Regional Basic Education Quality Assessment Based on Deep
           Convolutional Neural Network

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      Authors: Taotang Liu, Jie Zhao, Shuping Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      At present, the informatization of basic education quality assessment has become a hot topic in the field of education and is playing an increasingly important role. Based on the theory of deep convolutional neural network, this paper adopts the methods of mathematical analysis and experimental research to construct a regional basic education quality assessment model. The model solves the data informatization problem of education quality assessment. In the simulation process, two key modules of data self-assessment and expert assessment of the deep convolutional neural network are realized by ASENET+SQL SERVER, and the assessment results are integrated by using the weighted average method and the fuzzy comprehensive assessment method. The experimental results show that the quantitative analysis of the quality assessment is carried out by using the logic and support relationship, and the results of comprehensive qualitative analysis and quantitative analysis are realized and segmented when the threshold level is 9, the MIOU obtains the highest value of 0.7501, and the MIOU of the multi-stage method of the quality evaluation model proposed in this paper is 0.8116, which is 6.15% points higher than the traditional multi-stage algorithm, which effectively improves the current stage area quality of basic education.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S021812662350072X
       
  • A Deep Learning-Based Text Detection and Recognition Approach for Natural
           Scenes

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      Authors: Xuexiang Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we design a natural scene text detection and recognition model based on deep learning by model construction and in-depth study of wild scene text detection and recognition. This paper proposes a scene text recognition method based on connection time classification and attention mechanism for the situation where natural scene text is challenging to recognize due to the high complexity of text and background. The method converts the text recognition problem in natural scenes into a sequence recognition problem, avoiding the drawback of overall recognition performance degradation due to the difficulty of character segmentation. At the same time, the attention mechanism introduced can reduce the network complexity and improve the recognition accuracy. The performance of the improved PSE-based text detection algorithm in this paper is tested on the curved text datasets SCUT-ctw1500 and ICDAR2017 in natural scenes for comparison. The results show that the proposed algorithm achieves 88.5%, 77%, and 81.3% in the three indexes of accuracy, recall, and F1 value, respectively, without adding the pre-training module. The algorithm can detect text in any direction well without adding the pre-training module; the improved text recognition algorithm based on CRNN in this paper is tested on the natural scene dataset ICDAR2017, and the results show that the accuracy rate reaches 94.5% under the condition of no constraint, which is a good performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623500731
       
  • Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic
           Networks Sensor Nodes

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      Authors: Ashish Sachdeva
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the present scenario, the devices supporting neighbor discovery are going through the renovation phase, and crossing the classical barrier such as the trade-off between power dissipation and access time. The presence of opportunistic nodes in place of static nodes has presented multiple challenges for such devices. Therefore, the focus of neighbor discovery has mostly shifted toward such issues where power dissipation and latency of mobile nodes need to be simultaneously improved to achieve uninterrupted and quality communication. Since static random-access memory (SRAM) is an integral part of all such sensor nodes and directly impacts power dissipation and latency, therefore in this paper, we have introduced a novel SRAM cell for such nodes. The proposed eleven transistors (11T) SRAM cell is compared with six recently reported designs to check the improvement of SRAM key design parameters. The compared designs include Standard 6T (S6T), tunable 8T(TU8T), PPN-based 10T (PN10T), Schmitt trigger-based 10T (S10T), bit-line-dependent 11T (DP11T) bit-cell and stable low power 11T (SP11T). The improvement in write ability and read stability of proposed 11T cell is represented by [math] and [math] enhancement of write and read static margins, respectively, in comparison to S6T/TU8T/PN10T/S10T/DP11T/SP11T. Further, the leakage power dissipation is reduced by [math] as compared to S6T/TU8T/S10T/PN10T/DP 11T/SP11T. Additionally, power dissipation and delay of proposed 11T cell during read operation is reduced by [math] and [math], respectively, as compared to S6T/TU8T/PN10T/S10T/DP11T/SP11T. It is worth mentioning here that the proposed 11T also shows narrower variability in power dissipation and current values during read operation comparing S6T. The proposed 11T design successfully mitigates the half-select issue and allows the SRAM array to attain the bit-interleaved architecture implementation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623500780
       
  • Nonisolated Boost Converter with New Active Snubber Structure and Energy
           Recovery Capability

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      Authors: Omid Sharifiyana, Majid Dehghani, Ghazanfar Shahgholian, Sayyed Mohammad Mehdi Mirtalaei, Masoud Jabbari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The boost converters have become one of the most important part of renewable energy plants. The two parameters of boost converters, high voltage gain and high efficiency, have received more attention. In this paper, a boost converter with high voltage gain and high efficiency was used. The proposed topology is a boost converter with high transmission power and reduced voltage stress on the converter components, especially voltage stress on the main switch of the converter. This boost converter has a high efficiency using a new loss reduction technique called active snubber circuit with energy recovery. The proposed nonisolated topology converter was designed with a power of about 500[math]W, an input voltage of 48[math]V and an output voltage of 380[math]V and efficiency of more than 97%. The simulation results of the proposed converter showed different modes of the boost converter. A laboratory model was constructed and the claims of the proposed boost converter were proved.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623500846
       
  • Electronic Circuit Implementations of a Fractional-Order Chaotic System
           and Observing the Escape from Chaos

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      Authors: Akif Akgul, Yusuf Adiyaman, Abdullah Gokyildirim, Burak Aricioglu, Muhammed Ali Pala, Murat Erhan Cimen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Studies on fractional-order chaotic systems have increased significantly in the last decade. This paper presents Rucklidge chaotic system’s dynamical analyses and its fractional-order circuit implementations. Component values required for realizing the circuit of the fractional-order system are calculated for different fractional-orders. The feasibility of the attractor is examined by implementing its electronic circuit with a fractional-order module. The module is constructed based on the Diyi-Chen model since it is easier to implement and cost-effective. In electronic circuit implementations, it is observed that the system’s chaotic state disappears as the fractional degree decreases. Numerical and circuit simulation results are consistent well with the hardware experimental results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623500858
       
  • Ensemble Learning of Lightweight Deep Convolutional Neural Networks for
           Crop Disease Image Detection

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      Authors: Mehdhar S. A. M. Al-Gaashani, Fengjun Shang, Ahmed A. Abd El-Latif
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The application of convolutional neural networks (CNNs) to plant disease recognition is widely considered to enhance the effectiveness of such networks significantly. However, these models are nonlinear and have a high bias. To address the high bias of the single CNN model, the authors proposed an ensemble method of three lightweight CNNs models (MobileNetv2, NasNetMobile and a simple CNN model from scratch) based on a stacking generalization approach. This method has two-stage training, first, we fine-tuned and trained the base models (level-0) to make predictions, then we passed these predictions to XGBoost (level-1 or meta-learner) for training and making the final prediction. Furthermore, a search grid algorithm was used for the hyperparameter tuning of the XGBoost. The proposed method is compared to the majority voting approach and all base learner models (MobileNetv2, NasNetMobile and simple CNN model from scratch). The proposed ensemble method significantly improved the performance of plant disease classification. Experiments show that the ensemble approach achieves higher prediction accuracy (98% for majority voting and 99% for staking method) than a single CNN learner. Furthermore, the proposed ensemble method has a lightweight size (e.g., 10[math] smaller than VGG16), allowing farmers to deploy it on devices with limited resources such as cell phones, internet of things (IoT) devices, unmanned aerial vehicles (UAVs) and so on.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S021812662350086X
       
  • High-Speed and Energy-Efficient Sense Amplifier

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      Authors: Yogendra Kumar Upadhyaya, Mohd Hasan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Sense amplifier is a key element of memory and a CMOS-based spin hybrid circuit. Magnetic tunnel junction (MTJ) is a key spintronic device used in spin-based memory and hybrid circuits. This paper presents a design of a voltage-controlled magnetic anisotropy MTJ-based sense amplifier (VCMA-SA) that offers better reliability, power efficiency and high-speed performance. MTJ switching between different resistive states in this paper takes place through the faster and energy-efficient voltage-controlled magnetic anisotropy (VCMA) scheme rather than the traditional spin-transfer torque (STT)-based magnetization switching. This paper demonstrates that SA based on VCMA-MTJ switching is faster, reliable and more energy-efficient compared with iPMA-based STT switching.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-27T07:00:00Z
      DOI: 10.1142/S0218126623500986
       
  • A Deep Learning-Based Fast Route Planning Model for Location-Based Social
           Networks

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      Authors: Dongfang Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, location-based social networks (LBSN) are a kind of popular media in cyberspace. The LBSN provide geography-aware social services to users, so as to create special social network activities. For users, where to go and how to arrange following positions are the most intuitive problems. As a result, many researchers began to pay attention to the position recommendation in LBSN, in the past decade. However, existing position recommendation methods in LBSN are mostly oriented with situations involving single positions or not many positions. In fact, many scenarios require suggestion of series positions, which is usually ignored by the current research works. To deal with this problem, this paper proposes a deep learning-based fast route planning model for LBSN. Specifically, dependency inside position sequences for each user is modeled with the use of recurrent deep learning model. Then, such deep learning model is used to output prediction results for series future positions for a user. Hence, series positions can constitute the routes for users. Finally, experiments on a real LBSN dataset show the efficiency of the proposed route planning model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623500287
       
  • Defect Detection of Metro Wheel Set Tread Based on Image Recognition

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      Authors: Jun Ma, Chunguang Zhang, Bingzhi Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the operation of railway vehicles, the quality of bogies directly affects the operation quality and driving safety. Wheel set is one of the most important components in bogie, so the maintenance of wheel set is very important. For a long time, the detection of train wheel sets in China is still in the stage of manual measurement with backward technology and low efficiency. A new automatic detection method of wheel flange tread based on fuzzy neural network image processing technology is proposed in this paper. This method can accurately detect the defects of wheel flange tread. It collects the original image of the tested wheel set through the digital camera, inputs it into the computer, through certain calculation and processing, and compares it with the model established based on fuzzy neural network, so as to detect the defects of wheel flange and tread. First, the research status of wheel tread defect detection is summarized. Second, the basic principles of digital image technology are studied, the image processing models are confirmed, and the image processing method based on fuzzy neural network is established. Finally, eight wheel set treads are selected to carry out defect detection, and the analysis results show that the proposed method can obtain the better inspection precision.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623500871
       
  • A Rice Pest Identification Method Based on a Convolutional Neural Network
           and Migration Learning

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      Authors: Pingxia Hu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we construct models for convolutional neural networks and migration learning, conduct in-depth research on rice pest recognition methods, and design a plan based on convolutional neural networks and migration learning. The weight parameters obtained from the VGG16 model trained on the image dataset Image Net are migrated to recognize rice pests through the migration learning method. The convolutional and pooling layers of VGG16 are used as feature extraction layers. In contrast, the top layer is redesigned as a global average pooling layer and a SoftMax output layer, and some of the convolutional layers are frozen during training. The proposed method effectively improves the recognition accuracy of water to pest images and significantly reduces the number of model parameters.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623500895
       
  • Optimal Scheduling Strategy for Power Systems Containing Offshore Wind
           Farms Considering Wind Power Uncertainty

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      Authors: Jinhua Zhang, Yuerong Zhu, Zhengyang Zhao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The wind power interval prediction of offshore wind farms and power plan arrangement of conventional thermal power units are of vital importance in the consumption of offshore wind power, the reduction of greenhouse gas impact on the environment, and the electric power system safe and economic operating. With the purpose of selecting the appropriate Copula function on the basis of the results of wind speed and wind power normal test, establish the mathematical model of wind-fire joint optimal scheduling, and optimize coal-fired power units power generation after comparing the convergence performance of particle swarm optimization method and crow search algorithm. Results indicate that the selected Copula function meets the expected criteria, and the optimized thermal unit climbs more smoothly and through the optimization of CSA the complete economic consumption of running is lessened. An idea is presented by this paper, which considers the uncertainties of offshore wind power generation, and the basis for the operational performance of CSA over PSO, and which provides a joint wind-thermal economic optimal dispatch strategy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623500901
       
  • Optimized Fault-Tolerant Adder Design Using Error Analysis

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      Authors: Sakali Raghavendra Kumar, P Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Noor Mahammad Sk
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Field Programmable Gate Arrays (FPGAs) are often used in space, military, and commercial applications due to their re-programmable feature. FPGAs are semiconductor components susceptible to soft errors due to radiation effects. Fault tolerance is a critical feature for improving the reliability of electronic and computational components in high-safety applications. Triple Modular Redundancy (TMR) is electronic systems’ most commonly used fault-tolerant technique. TMR is reliable and efficient to recover the single-event upsets. However, the limitation of this technique is the area overhead. Prior work has proposed many conventional fault-tolerant approaches that have been unable to avoid area overhead. This paper introduces a novel work related to an error analysis-based technique. This technique works with an error percentage, and a preferential algorithm, which is also proposed to reduce the hardware complexity in the existing works. This technique can be applied on various types of arithmetic circuits. The proposed technique is applied to the adder circuit to verify the hardware usage, power consumption, and delay; it has been implemented on the Proasic3e 3000 FPGA. The simulated results were observed as 39.89% fewer IO cells, 47.10% fewer core cells, and 5.32% less power as compared to the TMR-based adder.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623500913
       
  • Various Unity-Bounded Functions for Designing Recursive Digital Filters
           with Variable Notch-Frequency and Guaranteed Stability

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      Authors: Tian-Bo Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Digital notch filters are useful for removing sinusoidal signals with a single frequency or multi-frequencies. For some applications, the sinusoidal signals being processed may change frequencies, and thus the notch filter must also have a variable notch frequency. Such a digital filter with a variable notch-frequency (VNF) is called variable notch-frequency (VNF) digital filter. Generally speaking, a VNF filter has the ability to change its notch frequency continuously, and can remove sinusoidal signals with variable frequencies. To design a recursive VNF filter, guaranteeing its stability is the top-priority issue. In this paper, a recursive VNF filter is designed by utilizing the least Lp-norm criterion, and the stability is guaranteed through adopting the stability-guarantee methodology based on parameter transformations. To perform the parameter transformations, a function that meets a special condition is required, and such a function is called unity-bounded function. In this paper, various unity-bounded functions are developed for the parameter-transformation-based stability guarantee. The unity-bounded functions play a crucial role in the stability guarantee. This paper details how to design a stable VNF filter by incorporating the parameter transformations employing the unity-bounded functions into the Lp-norm minimization of the magnitude response. Theoretically, the stability of the recursive VNF filter resulting from the design is definitely guaranteed. Moreover, since the coefficients of the designed VNF are variable, changing the filter coefficients enables the user to get a VNF filter with updated notch frequency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623500950
       
  • Travelling Route Recommendation Method Based on Graph Neural Network for
           Improving Travel Experience

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      Authors: Lang Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of Internet technology, people can learn all kinds of travel information anytime and anywhere. However, the serious information overload causes travelers to be unable to make accurate and reasonable travel routes that meet tourists’ tastes for a while, thus reducing the quality of travel. The recommendation system as the mainstream solution to the information explosion of two means has received the attention of the majority of scholars and industry. Based on the research theory of tourist route recommendation, this paper analyzes the characteristics of attractions, factors affecting travelers’ travel experience when touring attractions and factors affecting travelers’ travel experience along tourist routes. Furthermore, we propose a tourist route recommendation model that meets tourists’ preferences. Then, this paper uses the graph neural network (GNN) algorithm to build a framework for tourist route recommendations based on the GNN using the relationship of preference and commonality existing among groups, tourists and attractions. The GNN algorithm is optimized and improved using multiple graphs and an attention mechanism. Finally, the effectiveness of this paper’s algorithm is verified by conducting experiments on different data sets.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-25T07:00:00Z
      DOI: 10.1142/S0218126623501025
       
  • A Frequency Adaptive Data Collection Method for Internet of Things Nodes

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      Authors: Bo Liu, Aiqiang Yang, Xuyang Tan, Mengyao Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this paper is to solve the problem of a large amount of redundant data in the process of large-scale acquisition of Internet of Things sensors. This paper proposes a frequency adaptive data sensing method based on revolving gate algorithm for STM32 power safety data acquisition system. The method realizes the intelligent control of current protection terminal through three-stage current protection algorithm and frequency adaptive data acquisition algorithm. First, the three-stage current protection algorithm is used to protect the circuit, which can trip quickly in case of overload, and reduce the peak current caused by some equipment when starting up, so as to avoid damage to the equipment. Second, the arithmetic mean of each statistic is compared with the last value reported to the server. If the absolute value of the difference between the two exceeds the specified threshold range, the reported value is updated. Otherwise, it is filtered out, and the data smoothness is calculated according to the rules. The data collection interval is dynamically adjusted according to the data smoothness, which can greatly reduce the collection of redundant data and the traffic consumption of Internet of Things devices. On the server side, the inverse algorithm is used for interpolation and reconstruction to recover the collected data. This method is applied to the developed electricity safety equipment, and the electricity consumption is monitored and collected continuously for 24 h. After filtering by the frequency adaptive algorithm, only 108 pieces of data records are reported for 28,713 pieces of original data, and the compression ratio reaches 99.49[math]. Compared with other data collection strategies, this method significantly reduces the amount of redundant data collection and the energy consumption of terminal nodes. Furthermore, this method realizes the real-time perception of line data and environmental data through current, residual current, temperature sensor and electric energy metering chip, and controls the opening and closing of wire controlled micro circuit breaker through PC817 optocoupler to protect the safety of the circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-15T07:00:00Z
      DOI: 10.1142/S0218126623500664
       
  • Construction and Application of Piano to Intelligent Teaching System Based
           on Multi-Source Data Fusion

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      Authors: Zhen Jing
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of modern information technology represented by the Internet, cloud computing and big data, education and teaching have gradually realized the deep integration of the Internet, which has changed people’s way of life, study and work to a certain extent. Intelligence [math] education provides a new information-based teaching method for the development of education. From the perspective of improving the accuracy of data fusion results, this paper proposes a new multi-source data fusion method based on a set pair analysis connection degree for the situation that multiple sensors with unknown prior knowledge detect the same target feature parameters multiple times. By using the advantages of the set pair analysis feature function, the degree of opposition, the identity and difference between the measurement data are mined to adjust the degree of connection between the data. According to the existing signal-to-noise ratio weighting method in the fusion process, the weight of the measurement data is reasonably allocated to realize the weighted fusion of multi-source data, and the effectiveness and reliability of the algorithm are verified through simulation experiments. Through the summary of the questions, it can be seen that the learners are very satisfied with the mobile piano learning mode based on the intelligent teaching system, and they believe that this learning mode is conducive to the learner’s mastery of the basic knowledge of piano, and effectively improves the learners’ learning ability. It also improves the individual’s self-directed learning ability and academic performance. Through the research, it is concluded that the students’ piano mobile learning mode based on the intelligent teaching system is more conducive to the learner’s mastery of knowledge, and improves the learning interest and academic performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-15T07:00:00Z
      DOI: 10.1142/S0218126623500718
       
  • A Novel Hybrid Hexagonal Star Topology for On-Chip Interconnection
           Networks

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      Authors: V. Lakshmi Kiranmai, B. K. N. Srinivasarao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network-on-Chip (NoC) is an emerging and efficient on-chip interconnection network. NoC is expected to be the communication backbone of next-generation Multi-processor System-on-Chip (MPSoC) architectures. Topology is a crucial design aspect of NoC, as it affects the performance of the interconnection network. This paper proposes a novel, scalable, hybrid Hexagonal Star (HS) topology for on-chip interconnection networks. Properties of the proposed topology have been explored and compared with those of Mesh, Torus and Honeycomb Mesh topologies. The performance of the Hexagonal Star topology has been evaluated and compared with that of Mesh topology for different scenarios. The comparative studies of topological properties have indicated that the proposed topology can be a potential choice for on-chip interconnection networks. The simulation results have shown that the proposed topology outperforms Mesh topology in terms of latency for low traffic loads. For different traffic patterns and traffic loads, HS topology has registered a reduction of packet latency ranging from 15% to 50% and from 9% to 23% for 18 nodes and 32 nodes, respectively, compared to Mesh topology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-15T07:00:00Z
      DOI: 10.1142/S0218126623500767
       
  • Research on Personalized Recommendation Method of Educational Resources
           Based on Learner Behavior Analysis

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      Authors: Jiaguo Han
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The explosion of online learning resources makes the research on personalized recommendation of educational resources increasingly prominent. Based on the theory of learner behavior analysis, this paper analyzes the learning behavior logs of the online learning platform, and constructs a personalized recommendation method for educational resources. It analyzes the learner behavior from the three dimensions of basic attributes, behavior characteristics and result characteristics, and solves the problem of resource analysis. In the simulation process, the method uses the vector space model to complete the modeling of learner behavior, and realizes the division of learner groups based on learner behavior, and further evaluates and optimizes the division of learner groups. In order to further verify the clustering effect in combination with the actual data, the classification results are used for example analysis: the experimental results show that the sample points in the educational resource space are divided into 23 categories according to the distance relationship, and [math] is the best. The silhouette coefficient value is 0.54436, and the Calinski–Harabasz score value is 1464.9, which effectively improves the clustering effect of the personalized recommendation method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-15T07:00:00Z
      DOI: 10.1142/S0218126623500792
       
  • Dynamical Analysis of Hyperbolic Sinusoidal Nonlinear Multi-Wing Chaotic
           Systems, Synchronization Methods and Analog Electronic Circuit Design

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      Authors: Jie Zhang, Xiaopeng Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Chaotic systems contain nonlinear functions that have received much attention. This paper introduces a new four-dimensional chaotic system with multi-winged attractors, containing hyperbolic sinusoidal functions with unique quadratic curves that cause the attractors to change dramatically. When the single parameter is changed, single, double and quadruple wing chaotic attractors will be generated. The dynamical behavior of chaotic systems is analyzed and it is found that the system has coexistent attractors. Based on preparing the error system asymptotically stable at the origin, an adaptive control method is derived to achieve chaotic synchronization with unknown parameters. A new electronic circuit for chaotic systems is designed and implemented in FPGA hardware to illustrate the accuracy and validity of its existence.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-15T07:00:00Z
      DOI: 10.1142/S0218126623500810
       
  • DCM–RPL: A Distributed Competition Mobility Management Scheme for
           RPL/6LoWPAN

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      Authors: Chenggen Pu, Zhimou Zou, Ping Wang, Maosheng Wang, Zhao Yang, Junhua Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The IPv6 Routing Protocol for Low-Power and Lossy Networks (RPL) as a reliable and energy-efficient routing mechanism has become the de facto standard routing protocol of IPv6 over Low-powered Wireless Personal Area Network (6LoWPAN). However, it is designed for static wireless sensor networks and is not suitable for mobile scenarios. When mobile nodes (MNs) exist in the 6LoWPAN network, repeated link disruptions and topology changes lead to data packets loss and affect network stability. An increasing number of mobile applications force the improvement of RPL protocols for supporting mobility. In this study, a distributed competition and mobility-aware RPL routing protocol (DCM–RPL) is proposed to carry out mobility management and alleviate the network burden in the mobile scenario. A new preferred parent-discovering mechanism for MNs based on a distributed competition algorithm integrated with Objective Function is designed, which can dramatically reduce power consumption in the new parent node (PN)-discovering phase. To reduce data loss during the node-moving process, a packet-caching mechanism is proposed in the PN update phase. Finally, test-beds are set up and simulated in the Cooja simulator. Comparing the performance of the DCM–RPL in terms of switching delay, energy consumption, and PDR with the RPL and its mobility-aware variant (mRPL and EC–MRPL); the simulation results show that the proposed scheme maintains efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-15T07:00:00Z
      DOI: 10.1142/S0218126623500834
       
  • A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse
           Extension Logic

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      Authors: Ravi Kumar, Pooja Bohara, Krishna Thakur, Santosh Kumar Vishvakarma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new optimized high-speed divide-by-8/9 dual modulus prescaler. Simulation results show 54% reduction in power consumption, 40% of speed improvement and almost 48% area reduction as compared to the conventional architecture. Power consumption in the proposed prescaler is reduced by eliminating one True-Single-Phase Clocked (TSPC) D Flip-Flop (DFF) from the standard divide-by-2/3 prescaler, replacing it with Pulse Extension Logic (PEL) circuit. Redundant stages from asynchronous divide-by-2 units were also removed to save more power and reduce more delay. The simulation results show that the prescaler is capable of running at 5.5[math]GHz of maximum frequency with 1.9[math]mW power consumption. The divider is implemented in 0.18[math][math]m CMOS technology with 1.8[math]V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-13T07:00:00Z
      DOI: 10.1142/S0218126623500688
       
  • A New Technique Based on AMID Using Adaptive Thresholding for Ultrasound
           Speckle Reduction

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      Authors: Bhawna Gupta, Vineet Khandelwal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new technique based on adaptive multi-resolution image decomposition (AMID) using adaptive thresholding for ultrasound speckle reduction has been proposed in this paper. The noisy image is first filtered to reduce large multiplicative noise. The image is then log-transformed before decomposing it to its approximation and detailed coefficients using AMID algorithm. The approximation coefficients are appropriately filtered while adaptive thresholding is applied to the detail coefficients. The image is reconstructed back from all the modified coefficients to obtain the denoised image. This method combining adaptive decomposition with adaptive thresholding makes it adaptive to both signal and noise components, thereby retaining the edge details in the denoised image effectively. The proposed technique performance is tested on synthetic as well as real ultrasound images with the noise of different variances. The experimental results show that the proposed algorithm gives better performance than the other state-of-the-art methods in terms of edge keeping index (EKI), correlation coefficient (CC), figure of merit (FOM), peak signal-to-noise ratio (PSNR), structural similarity (SSIM) and signal-to-noise ratio (SNR) for synthetic images. The algorithm gives better performance in terms of equivalent number of looks (ENL) and mean-to-variance ratio (MVR) for real ultrasound images.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-13T07:00:00Z
      DOI: 10.1142/S0218126623500779
       
  • QCA-Based Pulse/Bit Sequence Detector Using Low Quantum Cost [math]-Flip
           Flop

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      Authors: Enaul Haq Shaik, Balagopendra Rao Mannava, Mahaboob Subani Shaik, Nakkeeran Rangaswamy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a Quantum-Dot Cellular Automata (QCA)-based [math]-flip flop is designed with low quantum cost to propose a 3-bit sequence detector which detects a bit pattern 101 in both overlapping and non-overlapping forms. Initially, a level to edge-triggered clock converter is proposed to convert clock signal levels into edge defining signals. Later, [math]-flip flops of both level and edge triggered clock inputs are developed. Compared with the recently reported designs in the literature, it is observed that the quantum cost of the proposed [math]-flip flops is decreased by more than 28% with a cell count of 34, which in turn defines the low area too. Also, latency of the same is reduced by one-fourth with a value of [math] s. As far as the sequence detector is concerned, it is smaller in size at 0.16[math][math]m2 than the existing sequential circuits with a reduction in area and quantum cost by 30%. Further, from the bit stream it detects, the proposed sequence detector can also be used as negative pulse detector and interrupt handler circuit in the future QCA-based digital systems to detect the external interrupts.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-13T07:00:00Z
      DOI: 10.1142/S0218126623500822
       
  • AHDNN: Attention-Enabled Hierarchical Deep Neural Network Framework for
           Enhancing Security of Connected and Autonomous Vehicles

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      Authors: Koyel Datta Gupta, Deepak Kumar Sharma, Rinky Dwivedi, Gautam Srivastava
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The usage of the Internet of Things (IoT) in the field of transportation appears to have immense potential. Intelligent vehicle systems can exchange seamless information to assist cars to ensure better traffic control and road safety. The dynamic topology of this network, connecting a large number of vehicles, makes it vulnerable to several threats like authentication, data integrity, confidentiality, etc. These threats jeopardize the safety of vehicles, riders, and the entire system. Researchers are developing several approaches to combat security threats in connected and autonomous vehicles. Artificial Intelligence is being used by both scientists and hackers for protecting and attacking the networks, respectively. Nevertheless, wirelessly coupled cars on the network are in constant peril. This motivated us to develop an intrusion detection model that can be run in low-end devices with low processing and memory capacity and can prevent security threats and protect the connected vehicle network. This research paper presents an Attention-enabled Hierarchical Deep Neural Network (AHDNN) as a solution to detect intrusion and ensure autonomous vehicles’ security both at the nodes and at the network level. The proposed AHDNN framework has a very low false negative rate of 0.012 ensuring a very low rate of missing an intrusion in normal communication. This enables enhanced security in vehicular networks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-05T07:00:00Z
      DOI: 10.1142/S0218126623500585
       
  • A Deep Learning-Based Robust Automatic Modulation Classification Scheme
           for Next-Generation Networks

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      Authors: Vinoth Babu Kumaravelu, Vishnu Vardhan Gudla, Arthi Murugadass, Hindavi Jadhav, P. Prakasam, Agbotiname Lucky Imoize
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to stochastic wireless environment, the process of modulation classification has become a challenging task. Because of its powerful feature extraction ability and promising performance over the conventional schemes, deep learning (DL) models are employed to automatic modulation classification (AMC) problems. Most of the conventional models proposed are tested for the limited set of modulation schemes transmitted over additive white Gaussian noise (AWGN) channels without considering the effect of multipath fading and Doppler shift. The next-generation networks use adaptive and higher-order quadrature amplitude modulation (QAM) schemes for higher spectral efficiency. The classification accuracy of conventional DL-based AMC schemes drastically reduces, when different order QAM modulation schemes are accommodated. In this work, different scaling factors are selected for the generation of [math]-QAM frames. The combination of scaling factors, which maximize the classification accuracy is chosen. A convolutional neural network (CNN) with six stages is employed for AMC. The simulation results show that the classification accuracy of proposed scheme is higher than the conventional DL-based schemes under various signal-to-noise ratio (SNR) conditions. The proposed scheme shows at least 4% improvement in classification accuracy over the other DL-based schemes.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-05T07:00:00Z
      DOI: 10.1142/S0218126623500676
       
  • A Resource Efficient CNN Accelerator for Sensor Signal Processing Based on
           FPGA

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      Authors: Ruidong Wu, Bing Liu, Ping Fu, Haolin Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the use of Convolutional Neural Network (CNN) in the application of sensor signal processing system, it usually faces the urgent requirements of system integration, high throughput, hardware resource and energy efficiency. This paper introduces a resource efficient accelerator with general two-dimensional multiply-add array operator to focus on the characteristic of sensor signal processing, which can be applied to standard CNN, depth-wise CNN, Fully Connected (FC) layer for varied networks. Meanwhile, resource estimation model is also constructed to provide the exploration of parallel parameters for computing efficiency. Finally, a board-level verification is implemented to demonstrate the efficiency of proposed accelerator with common scene of LeNet and complex scene of MobileNetV1. Experimental results show that the Inferences Per Second (IPS) of 332225 and 1498 is realized with 100[math]MHz frequency. The corresponding efficiency is 88.84% and 61.09%, which outperforms other related works about CNN accelerator design in terms of signal processing. This paper is also applicable and scalable to other fields about effective acceleration research.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-10-05T07:00:00Z
      DOI: 10.1142/S0218126623500755
       
  • A High-Performance Low Complex Design and Implementation of QRS Detector
           

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      Authors: S. R. Malathi, P. Vijay Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Electrocardiogram (ECG) is considered as the important diagnostic tests in medical field for detecting the cardiac anomalies. But, the ECG signals are polluted with numerous noise from power line intrusion, muscle noise, baseline wander, motion artifacts, low frequency noise signals, high frequency noise signals and T-wave, which automatically affects the QRS profile. The existing method provides the result in lesser accuracy with higher rate of error detection. To overcome these issues, QRS detector using modified maximum mean minimum (MoMaMeMi) filter optimized with mayfly optimization algorithm (QRS-MoMaMeMi-MOA) is proposed in this paper for less computational cost along with resource requirements. The proposed filter design consists of two phases for detecting QRS detector, such as filtering process associated to the enhancement and detection phase. Initially, the ECG data are taken from MIT/BIH arrhythmia dataset (MIT-AD). For eradicating the baseline wander in ECG data, MaMeMi filter is used. For expanding the performance of the modified MaMeMi filter, filter parameters, such as [math] and [math] are optimized by MOA to accomplish the best values and measure the performance of the whole QRS detector. For high frequency noise suppression in ECG data, the range function, noise subtractors, modified triangular detector are used. Then, heart beat detection can be done with the help of adaptive thresholding technique. The proposed filter design is carried out in MATLAB and implemented on field programmable gate arrays (FPGAs). The proposed QRS-MoMaMeMi-MOA filter design had 0.93%, 0.12% and 0.19% higher accuracy and 89.32%, 50% and 62% low detection error rate, compared to the existing filters, like Kalman filtering based adaptive threshold algorithm for QRS complex detection (QRS-KF-ATA), QRS detection of ECG signal utilizing hybrid derivative with MaMeMi filter by efficiently removing the baseline wander (QRS-HD-MaMeMi), and knowledge-based QRS detection operated by cascade of moving average filters (QRS-CAF). Then, the device utilization of the proposed FPGA implementation of the QRS-MoMaMeMi-MOA filter provides 95.556% and 71.428% lower power usage compared with the existing algorithms, like Kalman filtering based adaptive threshold algorithm for QRS complex detection in FPGA (FPGA-QRS-KF-ATA), and efficient architecture for QRS detection in FPGA utilizing integer Haar wavelet transform (FPGA-QRS-IHWT).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-30T07:00:00Z
      DOI: 10.1142/S0218126623500561
       
  • An Enhanced Reactive Power Compensation Scheme using a Synthesis Segmental
           Multilevel Converted for Three-Phase Grid Systems

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      Authors: Rajendran Nirmala, Sundharajan Venkatesan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Solar photovoltaic (PV) systems have gained significant attention due to their easy implementation and availability, where proper energy management should be highly concentrated for a successful PV power utilization. In the traditional works, various controlling techniques have been developed for reactive power compensation. But, it lacks with the issues of reduced system performance, increased loss, and high harmonics. Hence, this paper aims to develop a new controlling methodology, named the Synthesis Segmental Multilevel Converter (SSMC) for reactive power compensation in a three-phase grid system. Initially, it extracts the maximum amount of power from the solar PV systems by using an Enhanced Perturb and Observe (EPO) method. Then, the panel separation is performed and the three-phase power input is given to the SSMC converter, where the synchronization and switching pulse generation processes are performed. During synchronization, integrated techniques such as Proportional Integral (PI), Fuzzy Logic Controller (FLC), and Improved Artificial Neural Network (IANN) are utilized to maintain the voltage, magnitude and phase angle in the same level. Consequently, the Inductance Capacitance (LC) filtering technique is applied to reduce the harmonics distortion in the signal. After that, the Park transformation is used to perform the dq0 to abc transformation, which is implemented for reducing the high volume of error. Finally, the error-free signal is fed to the three-phase grid system with reduced harmonics. During experimentation, both the simulation and analytical results have been taken for analyzing the performance of the proposed technique. Moreover, it is compared to the existing algorithms for proving the betterment of the proposed methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-30T07:00:00Z
      DOI: 10.1142/S021812662350069X
       
  • A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring
           Oscillator Frequency

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      Authors: Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([math]) is the main dominant source of frequency and gain ([math]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [math] times variation in [math] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[math]GHz is developed in 65[math]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [math] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[math]mW power from 1[math]V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500597
       
  • A Hyperparameter Adaptive Genetic Algorithm Based on DQN

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      Authors: Detian Zeng, Tianwei Yan, Zengri Zeng, Hao Liu, Peiyuan Guan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The hyperparameters of the metaheuristic algorithm are difficult to determine when solving optimization problems. The existing methods mainly adjust hyperparameters through preset rules or traditional RL. The performance of the above methods is unsatisfactory and the generalization is poor. This work proposes a deep Q-learning network (DQN)-based dynamic setting framework for combinatorial hyperparameters, and applies it to a Genetic algorithm (GA) to improve its performance. By defining the four elements of the environment, state, action and reward required for learning strategy in advance, the parametrized strategy can be trained offline and different DQN models can be studied. Our method was compared with other algorithms and achieved the shortest path on 14 of 15 public TSP instances. Meanwhile, the test results on our simulation TSP validation dataset revealed that Category DQN achieved the best performance. This means the proposed method can effectively solve the problem of combinatorial hyperparameters setting, and bring more solving advantages to the GA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500627
       
  • Design of DC–DC Buck Converter Based on Improved Voltage-Mode COT
           Control

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      Authors: Peirong Huang, Changyuan Chang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an improved voltage-mode constant on-time (COT) control DC–DC buck converter is designed, which makes the DC–DC buck converter have good stability. Firstly, an improved compensation scheme is introduced through the analysis and derivation of the traditional voltage-mode COT controlled buck converter model. Then, according to the application requirements of the design, Simplis software modeling is used to verify the correctness of the theoretical analysis. The 0.13[math][math]m BCD technology is used to tape out the DC–DC converter of the improved voltage mode COT. The input voltage is 3.7–5.5[math]V and the output voltage is 3.3[math]V. The chip test mainly includes heavy-load condition in CCM operation, light-load condition in DCM operation, and load transient response. The test results show that the chip can remain stable under heavy-load and light-load conditions. The overshoot and undershoot in transient response can be quickly restored to steady state during the recovery process. Finally, compared with chips of the same type, it shows that the DC–DC chip for portable electronic equipment designed in this paper adopts an internal compensation structure, which has good stability, simple design, small main chip area, simple peripheral equipment, and good application value.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500639
       
  • Reconfigurable Architecture for DNA Diffusion Technique-Based Medical
           Image Encryption

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      Authors: M. Devipriya, M. Brindha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this paper is to develop and test the features of reconfigurable architecture for its suitability for a secured medical image encryption. The image security has been ensured using three-level zigzag confusion, bit-level confusion, self-invertible matrix and DNA diffusion. The zigzag pixel-level and circular shift-based bit-level confusion offer a good scrambling to overcome the correlation among the pixels whereas the self-invertible matrix is used to have a better substitution effect. The DNA operations are performed to get new random-valued sequence for diffusion thereby the encryption process has been designed to get good protection with simple and effective coding. The concept of secured medical image encryption has been designed using verilog HDL and implemented using field programmable gate array (FPGA) with an intention to create a standalone embedded hardware for encryption. The analysis of the encryption includes correlation coefficient, entropy, Chi-square analysis, NPCR and UACI and so on, which gives a better result and conveysto us that it can resist the statistical and differential attacks. The synthesis report of the embedded hardware has been presented to understand the utilization of the FPGA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-28T07:00:00Z
      DOI: 10.1142/S0218126623500652
       
  • A Subcircuit-Based Model for the Accumulation-Mode MOS Capacitor

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      Authors: Shahriar Jamasb, Mohammad Bagher Khodabakhshi, Rasool Baghbani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The accumulation-mode metal-oxide-semiconductor (MOS) capacitor is commonly employed to implement MOS varactors in frequency-tuning circuits for radio frequency (RF) and analog applications. A subcircuit model for the accumulation-mode MOS (AMOS) capacitor based on the Berkeley Short-channel IGFET Model (BSIM) for the MOS field effect transistor (MOSFET) is presented. The proposed model accurately fits the capacitance-voltage (C-V) characteristics of an AMOS capacitor fabricated in a submicron CMOS process over the full range of operating gate voltages. The model also accounts for the impact of the distributed series resistance on the transient response of the AMOS capacitor. Notably, the gate capacitance and the associated series resistance are modeled as a distributed resistor-capacitor (RC) network to derive a subcircuit-based model with the bias-dependent resistance of the accumulation layer modeled as a voltage-controlled resistor (VCR). The proposed model is evaluated based on SPICE simulation of the intrinsic transient response of the AMOS capacitor using a basic circuit, representing the distributed RC network associated with the MOS device structure. Fine tuning of the effective series resistance in the subcircuit model can be achieved by fitting the measured data characterizing the charge–discharge behavior of the AMOS capacitor to the simulated data characterizing the intrinsic transient response generated by SPICE.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-24T07:00:00Z
      DOI: 10.1142/S0218126623500548
       
  • Single MEXCCII-Based Grounded Immittance Functions Simulation and
           Applications

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      Authors: Atul Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component’s matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit’s performance is examined using 0.18-[math]m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-24T07:00:00Z
      DOI: 10.1142/S0218126623500603
       
  • Ultrasound Kidney Images with IKNN-Dependent FPGA Abnormality
           Classification

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      Authors: R. Vinoth, R. Sasireka
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Ultrasound imaging is commonly used to diagnose internal anomalies. Imaging for abnormality detection is a challenging process in today’s world. Even though there is an advancement in technology, tele-radiographers face difficulty in the accurate diagnosis of abnormalities. In order to resolve this issue, tele-radiology has paved a new way for doctors around the world to access the Internet to share the radiological images from one location to another. But frequent online access is one of the bottleneck issues. In order to overcome this drawback, Computer Assisted Diagnosis (CAD) is preferred in this proposed study and it uses VIRTEX-6 FPGA to clearly identify abnormality in the platform and also manual control is minimized in this condition. The proposed algorithm includes five steps: pre-processing, segmentation, feature extraction, selection and classification. The classification is performed using the Iterative K-Nearest Neighbor (IKNN) classifier based on the selected features. Unlike popular KNN, the proposed IKNN algorithm performs the similarity measurement on selective neighbors for a number of times where the number of neighbors has been dynamically selected at each iteration. Also, at each iteration, the method would select a subset of features in a random way. For the features selected and with the neighbors selected, the method computes the similarity value of Hist-sim which is being measured according to the features selected from the histogram features where the method computes the Haralick similarity with the features selected from the Haralick features. Using the features selected, the method computes the value of cumulative class drive similarity (CCDS). At each iteration the class with maximum similarity is selected and finally, the class being selected for the most number of times is selected as a result of classification. This improves the performance of classification. While comparing with the existing algorithms such as Support Vector Machine (SVM) with the linear, Radial Basis Function (RBF) and polynomial kernels, greater accuracy is achieved via IKNN classification. The specificity is found to be 95, 80 and 75 for normal, cystic and stone kidneys.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-24T07:00:00Z
      DOI: 10.1142/S0218126623500640
       
  • A Switched Capacitor-Based Multilevel Boost Inverter for Photovoltaic
           Applications

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      Authors: B. Hemanth Kumar, S. Prabhu, K. Janardhan, V. Arun, S. Vivekanandan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a single-phase 13-level switching capacitor multilevel boost inverter (SCMLBI) with less switches and a voltage boost gain of six times is presented. The main focus of this work is to present a single DC source SCMLBI topology, which can provide an AC output voltage with low harmonic distortion by suitable sinusoidal pulse modulation (SPWM) technique. The given SCMLBI boost topology is designed to provide 13 output voltage levels utilizing a single DC source and 14 power electronic switches, and it includes intrinsic capacitor self-voltage balancing. The presented SCMLBI inverter does not require any magnetic elements like inductors which do not make the system complex in IC fabrication. In this work, the DC source is provided with a solar PV array with maximum power point tracking (MPPT) algorithm. The proposed SCMLBI topology provides an output voltage larger than the input voltage by appropriately converting the capacitors in series and parallel combinations. Sinusoidal PWM technique is used to control the switches in SCMLBI. A solar PV array of 100 W with incremental and conductance MPPT algorithm is used in this work. The verification of the presented SCMLBI topology is simulated on MATLAB software. Hardware results are also presented for the validation of SCMLBI topology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-22T07:00:00Z
      DOI: 10.1142/S0218126623500573
       
  • Challenges of Agile–Crowd Software Development: A Systematic
           Literature Review

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      Authors: Shamaila Qayyum, Salma Imtiaz, Huma Hayat Khan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Crowdsourcing is an emerging approach in software development, where software is developed by unknown, heterogeneous people around the globe, via an open call by the employer. Crowdsourcing, when used with agile, faces challenges because of the different development methodologies. Agile development methodology has practices that involve face-to-face frequent interaction, whereas crowdsourcing is a distributed development with no or limited face-to-face interaction. Both concepts are actively being used in the software development industry due to their benefits. However, there is a need to explore the integration of both methodologies for an effective and efficient software development. In this regard, the first step is to identify the challenges of integrating crowdsourcing and agile. In this paper, we intend to identify the possible challenges that may be faced while executing agile along with crowdsourcing. For this, we have conducted a Systematic Literature Review. Five main categories of challenges are presented which are: team issues, coordination and communication issues, organizational issues, project-related issues and task-related issues. A list of possible challenges of Agile–Crowd Software Development (ACSD) is presented in this study.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-21T07:00:00Z
      DOI: 10.1142/S0218126623300015
       
  • Electronically Independent Gain Controllable Integrable Trans-Admittance
           Mode Universal Filter: An Application for Modern Radio Receiver

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      Authors: Sachin Tiwari, Tajinder Singh Arora
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper represents a new integrable trans-admittance mode universal filter employing an active building block, i.e., Voltage Differencing Current Conveyor, and all grounded passive elements. The proposed circuit can easily realize all five, widely used, filter responses, i.e., bandpass, high pass, low pass, all pass and band-reject. The designed circuit configuration provides favorable impedances at the input as well as output ports. Independent tunability of its gain parameter and orthogonal tunability of its quality factor and operating frequency are some of the noteworthy features of the designed circuit. The simulations of the designed filter are verified by 180-nm Complementary Metal Oxide Semiconductor (CMOS) technology in the SPICE simulation environment. Validation of the proposed design is done by experimental work along with the regular mathematical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-21T07:00:00Z
      DOI: 10.1142/S0218126623500615
       
  • A Modern VDCCTA Active Element and Its Electronic Application

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      Authors: Yumnam Shantikumar Singh, Ashish Ranjan, Shuma Adhikari, Benjamin A Shimray
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-17T07:00:00Z
      DOI: 10.1142/S0218126623500536
       
  • Text Coverless Information Hiding Based on the Combination of Chinese
           Character Components

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      Authors: Junyu Wang, Yani Zhu, Jiaming Ni, Hui Wang, Ye Yao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent research works on coverless text information hiding, there are two main problems to be solved: low hiding success rate and small hiding capacity caused by the small amount of redundant information in the cover text. In order to overcome these problems, a method of coverless information hiding based on the combination of Chinese character components is proposed. This method is based on the traditional “location tag [math] keywords” mode for coverless information hiding, but with an improved design to extend the scope of available keywords for data hiding beyond the original cover texts. In our proposed method, each Chinese character in the keyword is split into two components: radicals and independent Chinese character, which are collected and will be recombined in pairs to generate the new Chinese characters. This method increases the hiding success rate and hiding capacity by generating Chinese characters that do not exist in the original cover text. The experimental result shows that the proposed method can utilize less size of carrier text database for efficient information hiding. When the size of carrier text database is reduced to 198[math]MB, the highest hidden capacity and hidden success that can be achieved are 13.45 and 0.99, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-17T07:00:00Z
      DOI: 10.1142/S021812662350055X
       
  • An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling
           Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator

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      Authors: Abdul Muqueem, Shanky Saxena, Govind Singh Patel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Frequency-modulated continuous-wave (FMCW) signals-based radar systems can outrun the optical and ultrasound sensors in dark and severe weather conditions. FMCW radar systems require a fast settling frequency synthesizer to reduce the chirp signal’s inactive and modulation times. This work proposes a new C-B and FMCW Transmitter based on Fast Settling Fractional-N DPLL (FS-FNDPLL) and ring-based pulse injection locking oscillator (R-PILO). The proposed FS-FNDPLL generates an ultra-fast low-noise smooth narrowband chirp by introducing an automatic controller-based TDC switching (AC-TDCSw) scheme in the forward loop of FNDPLL. Also, the proposed FS-FNDPLL employs a new background gain calibrated digital-to-time converter (BGC-DTC) as a fractional divider in the feedback path for the quantization noise cancellation (QNC). The proposed FMCW transmitter uses an R-PILO to produce fast switching adjacent carriers after generating a narrowband chirp using FS-FNDPLL. The main features of the proposed FMCW to accelerate settling time with AC-TDCSw, BGC-DTC and the integration of spur suppressing pulse generator (SSPG) in R-PILO enable ultra-fast chirps with less phase noise and spur levels. The proposed transmitter up-converts the 500[math]MHz narrowband chirp signal onto four adjacent carriers for obtaining a 2[math]GHz chirp at the C-band. The simulation results prove that the proposed FMCW Transmitter consumes 79[math]mW power. Furthermore, the phase noise of the proposed FS-FNDPLL is reduced to [math][math]dBc/Hz at 1[math]MHz. The proposed FS-FNDPLL reduces the settling time to 1[math][math]s with the introduced AC-TDCSw scheme.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-16T07:00:00Z
      DOI: 10.1142/S0218126623500457
       
  • Voice Calibration Using Ambient Sensors

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      Authors: Jianhai Chen, Huapu Zeng, Yunming Pu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The voice sensor is the core part of voice monitoring devices, and it is commonly drifted in long-term running. For this reason, the voice calibration of monitoring devices is essential. Several calibration methods had been introduced by leveraging expensive referred instruments or manual calibration methods. However, these methods are not only dependent on high-cost instruments, but also is impractical on isolated occasions. To overcome these issues, the feature fusion-based neighbor (FbN) model is proposed to calibrate voice sensors, via real-time low-cost ambient sensors. The FbN consists of a real-time awareness stage, feature selection stage, feature fusion stage, and prediction stage. First, voice data and exogenous low-cost sensor (LCS) data are simultaneously collected. Second, those low-cost sensor data are treated as individual features. The irrelevant features are empirically filtered out. The adopted exogenous features are temperature, humidity and air pressure. Third, the selected features are fused to obtain more representative features. Finally, distances between sensor data and represented features are calculated and sorted. The top-[math] average distances are regarded as the predictive results. Experimental comparisons with several novelty methods show the effectiveness of the proposed FbN.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-15T07:00:00Z
      DOI: 10.1142/S0218126623500433
       
  • Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG
           and Multistage LFSR with Clock Gating Network

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      Authors: Mangal Deep Gupta, R. K. Chauhan, Sandeep Gulia
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S0218126623500391
       
  • Design of a Configurable Third-Order [math]-[math] Filter Using QFG and
           BD-QFG MOS-Based OTA for Fast Locking Speed PLL

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      Authors: Priti Gupta, Sanjay Kumar Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([math]-[math])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [math]-[math] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [math]-[math] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [math]3[math]dB cut-off frequency of 16.51[math]MHz and 17.22[math]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[math][math]s and 0.32[math][math]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[math][math]m CMOS process.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S0218126623500408
       
  • Extraction of Meaningful Information from Unstructured Clinical Notes
           Using Web Scraping

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      Authors: K. Sukanya Varshini, R. Annie Uthra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the medical field, the clinical notes taken by the doctor, nurse, or medical practitioner are considered to be one of the most important medical documents. These documents hold information regarding the patient including the patient’s current condition, family history, disease, symptoms, medications, lab test reports, and other vital information. Despite these documents holding important information regarding the patients, they cannot be used as the data are unstructured. Organizing a huge amount of data without any mistakes is highly impossible for humans, so ignoring unstructured data is not advisable. Hence, to overcome this issue, the web scraping method is used to extract the clinical notes from the Medical Transcription (MT) samples which hold many transcripted clinical notes of various departments. In the proposed method, Natural Language Processing (NLP) is used to pre-process the data, and the variants of the Term Frequency-Inverse Document Frequency (TF-IDF)-based vector model are used for the feature selection, thus extracting the required data from the clinical notes. The performance measures including the accuracy, precision, recall and F1 score are used in the identification of disease, and the result obtained from the proposed system is compared with the best performing machine learning algorithms including the Logistic Regression, Multinomial Naive Bayes, Random Forest classifier and Linear SVC. The result obtained proves that the Random Forest Classifier obtained a higher accuracy of 90% when compared to the other algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S021812662350041X
       
  • Optimum Transistor Sizing of CMOS Differential Amplifier using Tunicate
           Swarm Algorithm

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      Authors: V. Kamalkumar, R. Lal Raja Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-14T07:00:00Z
      DOI: 10.1142/S0218126623500512
       
  • Construction of Sports Rehabilitation Training Method Based on Virtual
           Reality

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      Authors: Yi Xu, Jinglun Huang, Yajuan Yao, Chaofan Zeng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The introduction of virtual reality technology into rehabilitation training can avoid various shortcomings of traditional rehabilitation training, and can efficiently complete training tasks. Based on the basic theory of virtual reality, this paper constructs a sports rehabilitation training method to achieve the consistency of the virtual upper limbs and the real upper limbs of the human body. The model provides a background environment in the virtual reality training, realizes the systematic maintenance of the patient’s training mode, provides the patient with a scientifically based training mode and evaluation results, solves the quantitative index problem of sports rehabilitation training, and builds a virtual upper limb platform at the same time. During the simulation process, the system used the Berg balance assessment scores to conduct four-stage assessments. Before treatment, the three-dimensional gait analysis, FMAL lower extremity function scores and Berg balance assessment results were not significantly different between the control group and the experimental group ([math]). The experimental results showed that the three-dimensional gait analysis was used to analyze the pace, left and right step length, left and right support percentage, and stride frequency. Compared with the evaluation data before treatment, the index values of the control group and the experimental group were significantly improved ([math]); after the treatment, the two groups of patients were evaluated for motor function, the evaluation values of the experimental group were higher than those of the control group when compared between the two groups. It effectively meets the human–computer interaction needs of rehabilitation training.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-12T07:00:00Z
      DOI: 10.1142/S0218126623500342
       
  • Intelligent Optimization Approaches for a Secured Dynamic Partial
           Reconfigurable Architecture-Based Health Monitoring System

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      Authors: R. Saravana Ram, M. Lordwin Cecil Prabhaker
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([math]), computation time ([math]) and area ([math]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([math]), computation time ([math]) and area ([math]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using CycloneⓇ V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-12T07:00:00Z
      DOI: 10.1142/S0218126623500470
       
  • Forensics Analysis of Resampling via ConvNeXt Block

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      Authors: Xiaogang Zhu, Shuaiqi Liu, Bing Fan, Xiangjun Li, Yiping Zhu, Haozheng Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Images play an important role in transmitting visual information in our life. It could lead to severe consequences if images are manipulated or tampered maliciously. Digital forensics is an important research area to secure multimedia information. Many forensics technologies are applied to protect our community from the abuse of digital information. In many cases, after tampering, attackers could apply operations such as resampling, JPEG compression, blurring, etc. to cover the traces of tampering. Therefore, it is necessary to detect these manipulations in image forensics before exposing forgeries. In this paper, we propose to employ the prediction error filters, ConvNeXt blocks and convolution modules to classify images with different compression quality factors and resampling rates. By tracing the inconsistencies of resampling rates and compression quality factors, it could provide supplementary information for forensics researchers to expose possible forgeries. The proposed method could achieve great classification performance regardless of the interpolation algorithms. Also, it is highly robust against JPEG compression. In addition, the proposed method can be applied for estimating quality factors of JPEG compression.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500330
       
  • Low-resolution Face Recognition and Sports Training Action Analysis Based
           on Wireless Sensors

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      Authors: Hongjun An, Heng Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper constructs a low-resolution model for face recognition and sports training actions based on wireless sensors. The model obtains the distribution of the information size in the face image by calculating the image entropy value, and assigns different weights according to the size of the information to perform face recognition calculation, so that the original module-based algorithm is simply based on image segmentation into one based on entropy. The size of the value is divided into blocks, which solves the problem of computational quantification of category information. In the test stage, the traditional orthogonal matching pursuit algorithm is used to solve the coding coefficients, and the excellent classification and recognition results are obtained by calculating the intra-class matrix of the face image and the inter-class matrix of the sports training action image. Methods that perform well on classification problems further improve face recognition rates. The specific processing process is to add Gaussian noise, salt and pepper noise to the input face image and reduce the size of the face image in the input image, so that the improved algorithms are improved. The experimental results show that the high-efficiency resolution sensing technology is used to learn the sports training actions corresponding to the two modalities, and the matrix coefficient between the obtained high-resolution modal and low-resolution modal images reaches 0.971, and the iteration rate is improved by 71.5%, effectively promoting the high recognition rate of faces and actions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500378
       
  • Application of Virtual Network Mapping Algorithm Based on Optimal Subnet
           in Enterprise Cost Accounting Platform

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      Authors: Haiyan Wu, Xiao Li, Yongjun Qi, HaiLin Tang, Shukun Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The price of the product has a great impact on the market competitiveness of the product. The manager can adjust the operation strategy according to the cost information of the product, cut costs, adjust the market decision and make the product more competitive in the market. Therefore, the research of product costing method has a very important significance. Considering that the physical resources in the processing of the virtual network mapping (VNM) fragment embedded in the request are rejected, and the problem of physical resource usage is weakened, a VNM algorithm based on the optimal subnet edge matching algorithm is proposed. After the VNM request is coarsened to the subnet, the breadth-first search algorithm is used to create the physical subnet candidate set, and the constraints of the virtual node and the coarsening network topology are complied with. The simulation results show that the proposed algorithm reduces the number of link mapping hops and can improve the acceptance rate and cost-benefit ratio of virtual networks. First of all, this paper analyzes the research background of manufacturing cost calculation and the research situation at home and abroad, discusses the advantages and disadvantages of standard cost calculation and studies and analyzes the principles, advantages and disadvantages of standard cost calculation in daily business activities. Second, design a new mathematical accounting model based on the mathematical model of standard cost calculation in daily business activities. This combines the advantages of standard costing and time-based activity costing, and provides theoretical support for manufacturing companies to use this accounting method. Finally, the research results of this paper are summarized, and the shortcomings of this paper are analyzed. Cost accounting method needs to be further studied.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500421
       
  • Real-Time Regulation of Physical Training Intensity Based on Fuzzy Neural
           Network

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      Authors: Jiale Qu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the fuzzy neural network model is studied, the real-time regulation model of physical training intensity is analyzed and a real-time regulation system based on a fuzzy neural network is designed. The real-time, accurate and effective regulation of the physiological load intensity in the body of the exerciser is consistent with the predetermined goals of the training program. In this paper, we propose an RBF neural network, combined with the plan and demand of physical training operation situation sensing, and considering that most of the biological training operation data is fuzzy, this paper connects a fuzzy logic inference system and a neural network and proposes a network operation situation sensing model based on an RBF neural network structure. The RBF neural network and the traditional fuzzy neural network are compared. The experiments prove that this paper’s fuzzy neural network model has a faster training speed. In this paper, we use time-realistic control equipment to monitor the physical training process of athletes so that we can grasp the training situation of athletes in real-time and ensure that athletes can achieve better training results by changing training methods and changing training loads in time for those athletes who cannot reach their sports goals. In the process of physical fitness training monitoring, an effective monitoring of training, time-accurate regulation monitoring has the advantage of timely feedback on the training situation. This model has a better convergence effect during exercise and a higher accuracy of posture prediction during testing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500445
       
  • Research on Fast Recognition of Vulnerable Traffic Participants in
           Intelligent Connected Vehicles on Edge Computing

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      Authors: Musong Gu, Jingjing Lyu, Zhongwen Li, Zihan Yan, Wenjie Fan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Real-time and fast recognition of all kinds of traffic participants in intelligent driving has always been a major difficulty in the research of internet of vehicles. With the advent of edge computing, we try to deploy an image recognition algorithm directly to the intelligent vehicles. However, the original image recognition algorithm is difficult to be directly deployed on the vehicles due to limited edge device resources. Based on this, a fast recognition model of vulnerable traffic participants based on depthwise separable convolutional neural network (DSCYOLO) is proposed in this paper. The algorithm can significantly reduce the convolutional parameter quantity and computing load, making it suitable for deployment on the vehicle-mounted edge embedded devices. In order to validate the effectiveness of the proposed method, its simulation results are compared with the main target detection models Faster R-CNN, SSD and YOLOv3. The results show that the recognition time of the proposed model is reduced by 80.28%, 66.80% and 86.74%, respectively, on the basis of a relatively high recognition precision. The model can realize real-time detection and fast recognition of vulnerable traffic participants, so as to avoid a large number of traffic accidents. It has significant social and economic benefits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500469
       
  • Knowledge Distillation for Lightweight 2D Single-Person Pose Estimation

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      Authors: Shihao Zhang, Baohua Qiang, Xianyi Yang, Mingliang Zhou, Ruidong Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The current state-of-the-art single-person pose estimation methods require heavily parameterized models for accurate predictions. A promising technique to achieve accurate yet lightweight pose estimation is knowledge distillation. However, existing pose knowledge distillation methods rely on the most common large basic building blocks and a complex multi-branch architecture. In this study, we propose a Single-branch Lightweight Knowledge Distillation method to increase pose distillation efficiency for 2D Single-person pose estimation, termed SLKD2S. First, we design a novel single-branch pose knowledge distillation framework, which is composed of connected lightweight pose estimation stages. Second, we utilize a special pose distillation loss based on the joint confidence map. Finally, we only keep the initial stage and the first refinement stage to achieve a good performance. Extensive experiments on two standard benchmark datasets show the superiority of the proposed SLKD2S in terms of cost and accuracy, and the average detection accuracies are increased by 1.43% and 2.74% compared with the top-performing pose distillation method, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-09T07:00:00Z
      DOI: 10.1142/S0218126623500500
       
  • An Expansion Planning Approach for Intelligent Grids with Speculative
           Parallelism

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      Authors: Zhoukai Wang, Jiaqi Qi, Weigang Ma, Yang Lv, Dongfang Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Smart grid planning is a standard method used to reduce the net loss of distribution networks and improve the economic efficiency of power systems. As the distribution networks expand, the scale is getting more complex, leading to low efficiency and a long planning time when using traditional methods to implement new routes. To solve this problem, this paper proposed a new approach for intelligent grid expansion planning with speculative particle swarm optimization. First, the expansion planning model for the smart grid is established based on particle swarm optimization from the classical control system. Secondly, the model is parallelized with the speculative parallelism technique to overcome the influence of the internal control dependency and get rid of the original processing order. Finally, the parallel model is implemented on a distributed computing platform to improve the planning efficiency for complex intelligent grids significantly. Experiments show that the proposed approach can improve the efficiency by about 40% in an Apache Spark cluster consisting of 20 nodes compared with the conventional ones. Moreover, the proposed method can also fully utilize the distributed cluster’s computing resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-09-05T07:00:00Z
      DOI: 10.1142/S0218126623500366
       
  • FPGA Implementation of Expert System for Medical Diagnosis of Disc Hernia
           Diagnosis Based on Bayes Theorem

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      Authors: Tijana Šušteršič, Aleksandar Peulić
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this research is to create a medical expert system based on Bayes theorem to diagnose level of disc hernia based on real foot force measurement signals obtained using sensors and implement the whole system on field programable gate array (FPGA). We have created a database of attributes based on recorded foot force values of 33 patients pre-diagnosed with herniated disc on levels L4/L5 or L5/S1 on the left or right side. The results obtained by software (Matlab) and hardware (FPGA simulation) are matching well, achieving high accuracy, which shows that VHDL implementation of Naïve Bayes theorem for disc hernia diagnostics is adequate. The output on FPGA is easy to understand for any user, as it is implemented as four-bit output where the position of bit value 1 indicates the level of disc herniation. The system is able to distinguish between the healthy subjects and subjects with disc herniation and is able to detect if improvement in stability is present after surgery or physical therapy. Our proposed measurement platform can be coupled with FPGA to create a portable and not expensive tool for real time signal acquisition, processing and decision support system in disc hernia diagnosis and post-surgical recovery.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-31T07:00:00Z
      DOI: 10.1142/S021812662350038X
       
  • LiCAM: Long-Tailed Instance Segmentation with Real-Time Classification
           Accuracy Monitoring

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      Authors: Rongguang Ye, Yantong Guo, Xian Shuai, Rongye Ye, Siyang Jiang, Hui Jiang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, deep neural networks have achieved remarkable progress in class balancing instance segmentation. However, most applications in the real world have a long-tailed distribution, i.e., limited training examples in the majority of classes. The long-tailed challenge leads to a catastrophic drop in instance segmentation because the gradient of the head classes suppresses the gradient of the tail classes, leading to a bias towards the major classes. We propose LiCAM, a novel framework for long-tailed segmentation. It features an adaptive loss function named Moac Loss, which is adjustable during the training according to the monitored classification accuracy. LiCAM also cooperates with an oversampling technique named RFS, which alleviates the severe imbalance between head and tail classes. We conducted extensive experiments on the LVIS v1 dataset to evaluate LiCAM. With a coherent end-to-end training pipeline, LiCAM significantly outperforms other baselines.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-29T07:00:00Z
      DOI: 10.1142/S0218126623500329
       
  • Neural Network-Based Entropy: A New Metric for Evaluating Side-Channel
           Attacks

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      Authors: Jiafeng Cheng, Nengyuan Sun, Wenrui Liu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Yufei Wang, Yijian Bi, Yiming Wen, Hongliu Zhang, Pengcheng Zhang, Selcuk Kose, Weize Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623200013
       
  • A Robust, Compact and Efficient AMC-Enabled Dual-Band Antenna for Wearable
           Healthcare

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      Authors: Asma Ejaz, Humayun Shahid, Yasar Amin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper details an antenna design with a minuscule lateral footprint of [math][math]mm3. The antenna operates for the two bands of WiMAX 3.5[math]GHz (for wireless communication standard) and industrial, scientific and medical radio (ISM) 5.8[math]GHz (for healthcare applications). Optimization and computer-aided performance analysis of the proposed design are carried out using Computer Simulation Technology (CST) Microwave Studio. Required electromagnetic performance in close proximity to the human body is achieved by backing the primary CPW-fed antenna with a fabric-based dual-band AMC surface. Several prototypes of the formulated design are characterized experimentally to validate the computationally obtained performance parameters. The proposed AMC-integrated dual-band design readily meets directional radiation characteristics desired for off-body communication with 7.53-dB and 8.58-dB gains in the lower and upper resonance frequencies, respectively. Moreover, the antenna’s top layer consists of a semi-flexible laminate, while textile constitutes the bottom layer to maximize user comfort. Further analysis reveals a significant reduction in SAR by 16.7[math]W/kg at the lower band and by 13.5[math]W/kg at the upper band. The precedence of the reported structure demonstrated in the results endorses its application in robust wearable devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500238
       
  • Wien-Bridge Chaotic Oscillator Circuit with Inductive Memristor Bipole

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      Authors: K. Zourmba, C. Fischer, J. Y. Effa, B. Gambo, A. Mohamadou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      By diode bridging an inductor to implement a memristor bipole, with active Wien-bridge oscillator, a simple and feasible third-order autonomous memristive chaotic oscillator is presented. The dynamical characteristics of the proposed circuit are investigated both theoretically and numerically, from which it can be found that the circuit has one unstable equilibrium point. Through the analysis of the bifurcation diagram, Lyapunov exponent spectrum and the 0–1 test chaos detection, it is shown that this system displays limit cycle orbit with different periodicity, quasi-periodic behavior, chaotic behavior and bursting behavior. The bursting behavior found in this circuit is periodic, quasi-periodic and chaotic bursting. We confirm the feasibility of the proposed theoretical model using Pspice simulations and a physical realization based on an electronic analog implementation of the model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S021812662350024X
       
  • A General Methodology to Optimize Flagged Constant Addition

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      Authors: Aroondhati Bhure, P. Smriti, Vinay Dhanote, Uppugunduru Anil Kumar, Syed Ershad Ahmed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Addition is a ubiquitous operation frequently carried out in most computing applications. Traditionally, three-operand addition is done using either two adders or a carry–save adder. However, there exist applications such as digital signal processing, image processing, floating point arithmetic, etc. wherein among the three operands, one is constant. For such cases, we propose a flagged constant addition methodology, applicable to any constant, to compute the result with the least area, delay and power. The resulting architecture is referred to as general constant flagged adder (GCFA). We propose an Optimized Constant Generation (OCG) algorithm and a Hardware Optimization Algorithm (HOA) to achieve hardware-efficient constant flagged adder. These two algorithms are designed to lower the computational complexity. The OCG algorithm accepts the constant to be added and converts it into an optimized constant. This optimized constant then forms the input to the HOA where the hardware modifications are performed. Unlike the proposed work, the existing flagged adder structures do not provide a general methodology to obtain the optimized constant and hardware for all the constants, resulting from the presence of architectural customization for all constants and word lengths. Exhaustive hardware analyses have been carried out to prove the efficacy of the proposed architecture against the existing designs. Structural Verilog code is synthesized for each to obtain the area, delay and power. Synthesis results show up to 35.85% and 49.24% reductions in area–delay and power–delay products, respectively. The improved speed and lower hardware requirements make the proposed methodology a suitable choice for constant addition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500275
       
  • Fractal Feature Based Image Resolution Enhancement Using Wavelet–Fractal
           Transformation in Gradient Domain

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      Authors: Shyo Prakash Jakhar, Amita Nandal, Arvind Dhaka, Bojie Jiang, Liang Zhou, Vishnu Narayan Mishra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The fractal geometries are applied extensively in many applications like pattern recognition, texture analysis and segmentation. The application of fractal geometry requires estimation of the fractal features. The fractal dimension and fractal length are found effective to analyze and measure image features, such as texture, resolution, etc. This paper proposes a new wavelet–fractal technique for image resolution enhancement. The resolution of the wavelet sub-bands are improved using scaling operator and then it is transformed into texture vector. The proposed method then computes fractal dimension and fractal length in gradient domain which is used for resolution enhancement. It is observed that by using scaling operator in the gradient domain, the fractal dimension and fractal length becomes scale invariant. The major advantage of the proposed wavelet–fractal technique is that the feature vector retains fractal dimension and fractal length both. Thus, the resolution enhanced image restores the texture information well. The texture information has also been observed in terms of fractal dimension with varied sample size. We present qualitative and quantitative analysis of the proposed method with existing state of art methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-26T07:00:00Z
      DOI: 10.1142/S0218126623500354
       
  • An Improved Long Short-Term Memory Neural Network Wind Power Forecast
           Algorithm Based on Temd Noise Reduction

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      Authors: Hong You, Zhixiong Li, Xiaolei Chen, Lingxiang Huang, Feng Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To accurately predict the wind power and adopt methods to balance the fluctuation of power grid, an improved long short-term memory (LSTM) neural network wind power forecast algorithm based on noise reduction by threshold empirical modal decomposition (TEMD) is proposed. First, the actual operation and maintenance data of wind farms are normalized and divided into a training set and a test set. Then, an LSTM structure is designed and a Sub-Grid Search (SGS) algorithm is proposed to optimize the hyperparameters of the LSTM network. Finally, the power data are decomposed and noise-reduced using TEMD is improved by the variable-point technique and the TEMD-LSTM power forecast model is constructed to predict the power in time. The predicted values obtained are restored and evaluated by the original size. The results show that compared with five other algorithms of the same kind, the proposed algorithm in this paper has a root mean square error (RMSE) of 30.40, a trend accuracy (TA) value of 67.23% and a training time of 886 s, with the best overall performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-24T07:00:00Z
      DOI: 10.1142/S0218126623500299
       
  • Low-Complexity I/Q Imbalance Calibration Algorithm Based on Zero-IF
           Receiver

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      Authors: Zhi Li, YaFeng Yao, QunQun Zhou, DongBin Fu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although the scheme of designing transceiver with zero-IF architecture reduces the design cost, complexity and power loss of the system, this architecture is more sensitive to the I/Q mismatch problem existing in the analog front-end and it is difficult to eliminate the image interference caused by the mismatch. Therefore, a fast and low-cost I/Q imbalance calibration algorithm is needed. As for the problem of I/Q imbalance in zero-IF receiver, a blind estimation algorithm for extracting the calibration parameters and signal compensation is proposed because of the complexity of calculation and hardware circuit, as well as the power consumption of resources under the traditional algorithm. Based on the statistical property of the signal, this algorithm has the specific characteristics of low computational complexity and being easy to implement in hardware circuit. Due to different ideas of parameters extraction, a special calibration model is designed. The result of simulation shows that the proposed algorithm has not only better performance in compensation parameters estimation, but also better calibration performance than the traditional algorithm. By comparing the calibration performance in the case of different gain imbalances or phase imbalances, we can see that the algorithm can maintain a good calibration performance under different imbalance conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-24T07:00:00Z
      DOI: 10.1142/S0218126623500305
       
  • An Electronically Tunable Meminductor Emulator and Its Application in
           Chaotic Oscillator and Adaptive Learning Circuit

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      Authors: Nisha Yadav, Shireesh Kumar Rai, Rishikesh Pandey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new design of meminductor emulator has been suggested using voltage differencing buffered amplifier (VDBA), current differencing buffered amplifier (CDBA), a resistor and two grounded capacitors. The key advantages of the proposed meminductor emulator circuits are their design simplicity, implementation without memristors and easily adjustable design for grounded/floating decremental to incremental configurations. The proposed circuits have been designed and simulated using 180-nm process technologies in the Mentor Graphics Eldo simulation tool. The nonvolatility and Monte Carlo analysis of the proposed meminductor emulators have been given. A comparison table has also been presented to discuss the benefits of the suggested meminductor emulator designs with existing designs. The operation of the designed emulator has been corroborated by using it in the chaotic oscillator and neuromorphic circuit applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-22T07:00:00Z
      DOI: 10.1142/S0218126623500317
       
  • A Compressed Model-Agnostic Meta-Learning Model Based on Pruning for
           Disease Diagnosis

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      Authors: Xiangjun Hu, Xiuxiu Ding, Dongpeng Bai, Qingchen Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Meta-learning has been widely used in medical image analysis. However, it requires a large amount of storage space and computing resources to train and use neural networks, especially model-agnostic meta-learning (MAML) models, making networks difficult to deploy on embedded systems and low-power devices for smart healthcare. Aiming at this problem, we explore to compress a MAML model with pruning methods for disease diagnosis. First, for each task, we find unimportant and redundant connections in MAML for its classification, respectively. Next, we find common unimportant connections for most tasks with intersections. Finally, we prune the common unimportant connections of the initial network. We conduct some experiments to assess the proposed model by comparison with MAML on Omniglot dataset and MiniImagenet dataset. The results show that our method reduces 40% parameters of the raw models, without incurring accuracy loss, demonstrating the potential of the proposed method for disease diagnosis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-20T07:00:00Z
      DOI: 10.1142/S0218126623500226
       
  • Dynamic First Access Isolation Cache to Eliminate Reuse-Based Cache Side
           Channel Attacks

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      Authors: Chong Wang, Hong Yu, Shuai Wei, Ke Song
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cache side channel attacks have been used to extract users’ sensitive information such as cryptographic keys. In particular, the reuse-based cache side channel attacks exploit the shared code or data between the attacker and the victim, which can steal the secret with high speed and precision. It has threatened not only the host level but also the cloud level severely. Previous defensive measures are either not flexible enough, or cause a high performance or storage overhead. In this work, we present a dynamic first access isolation cache that eliminates reuse-based cache side channel attacks by providing fine grained first access isolation to overcome these problems. First of all, there are [math] bits in each cache line to record the access information and prevent the first time cache hit state brought by the victim from being utilized by the attacker while keeping data shared. Second, we use hierarchy security levels and domains to achieve flexible one way isolation between different domains, and the domains can be a group of processes, a single process, or even a fraction of code. Finally, the monitoring-driven dynamic scheduling mechanism can change the level of a domain at run time, which improves the robustness of this new design. The solution works at all the cache levels and defends against attackers running both on local and cloud. Our implementation in the Zsim simulator demonstrates that the performance overhead for standard performance evaluation corporation 2017 is less than 0.1%, and 0.21% for the multi-thread benchmarks. It performs better than the original first time miss design because of the one way isolation in our design. The only hardware modification is the [math] bits per cache line, and several security registers per hardware context, which only brings 3.71% storage overhead.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-19T07:00:00Z
      DOI: 10.1142/S0218126623500263
       
  • Transformation Invariant Pashto Handwritten Text Classification and
           Prediction

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      Authors: Muhammad Shabir, Naveed Islam, Zahoor Jan, Inayat Khan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The use of handwritten recognition tools has increased yearly in various commercialized fields. Due to this, handwritten classification, recognition, and detection have become an exciting research subject for many scholars. Different techniques have been provided to improve character recognition accuracy while reducing time for languages like English, Arabic, Chinese and European languages. The local or regional languages need to consider for research to increase the scope of handwritten recognition tools to the global level. This paper presents a machine learning-based technique that provides an accurate, robust, and fast solution for handwritten Pashto text classification and recognition. Pashto belongs to cursive script division, which has numerous challenges to classify and recognize. The first challenge during this research is developing efficient and full-fledged datasets. The efficient recognition or prediction of Pashto handwritten text is impossible by using ordinary feature extraction due to natural transformations and handwriting variations. We propose some useful invariant features extracting techniques for handwritten Pashto text, i.e., radial, orthographic grid, perspective projection grid, retina, the slope of word trajectories, and cosine angles of tangent lines. During the dataset creation, salt and pepper noise was generated, which was removed using the statistical filter. Another challenge to face was the invalid disconnected handwritten stroke trajectory of words. We also proposed a technique to minimize the problem of disconnection of word trajectory. The proposed approach uses a linear support vector machine (SVM) and RBF-based SVM for classification and recognition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-17T07:00:00Z
      DOI: 10.1142/S0218126623500202
       
  • 10-Bit 200[math]kHz/8-Channel Incremental ADC for Biosensor Applications

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      Authors: Priya Gupta, Aruj Earnest, Srinjoy Mitra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a second-order discrete-time (DT) modulator for 8-channel Incremental Sigma-Delta analog-to-digital converter (IADC) is presented for biomedical applications ranging from kHz. The proposed DT modulator with input bandwidth of 25[math]kHz on each channel is sampled at 51.2[math]MHz, with oversampling ratio of 128 implemented at 180[math]nm technology. The proposed IADC has high resolution, multichannel A/D conversion, simple architecture, low offset, low gain error and low area over the standard ADCs available. Measured results show that the SNR, DR, ENOB, power consumption and chip area of the proposed IADC are 63.9[math]dB, 62.2[math]dB, 10.11 bits, 0.832[math]mW and 0.032[math]mm2, respectively, at 1.8V power supply. For testing purpose, the noncoherent sampling is done to get the FFT plot of the output signal. For further validation, the proposed second-order IADC was also designed and compared in MATLAB/Simulink.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-17T07:00:00Z
      DOI: 10.1142/S0218126623500251
       
  • Design and Implementation of Face Detection Architecture for Heterogeneous
           System-on-Chip

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      Authors: Nidhi Panda, Supratim Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The seminal work of Viola and Jones for automatic face detection is widely used in many human–computer interaction and computer vision applications. On analyzing the existing face detection architectures, we observed that integral image calculation, feature computation in cascaded classifier, and recursive scanning of image with sliding window at multiple scales are the major reasons which increase the memory and time complexity of the algorithm. Therefore, in this paper, we have proposed a hardware–software co-design of Viola–Jones face detector for System-on-Chip (SoC). In the proposed architecture, integral image computation and cascaded classifier sub-modules are implemented on the hardware — Programmable Logic FPGA (PL-FPGA), while the image scaling and nonmaximum suppression sub-modules are implemented on the software — Processing System ARM (PS-ARM). Concepts of pipelining, folding, and parallel processing are effectively utilized to produce an optimum design architecture. The proposed architecture has been tested on PYNQ-Z1 board. The implementation results in a processing speed of [math] fps with PL and PS clocks of [math][math]MHz and [math][math]MHz, respectively, for an image of QVGA resolution. Results analysis demonstrates that the proposed architecture has minimum resource requirement as compared to state-of-the-art implementations, which facilitates and promotes the usage of resource-constrained low-cost ZYNQ SoC for face detection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-08-13T07:00:00Z
      DOI: 10.1142/S0218126623500214
       
 
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