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  Subjects -> ELECTRONICS (Total: 207 journals)
Showing 1 - 200 of 277 Journals sorted by number of followers
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 281)
Control Systems     Hybrid Journal   (Followers: 236)
IEEE Transactions on Geoscience and Remote Sensing     Hybrid Journal   (Followers: 174)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 165)
Electronic Design     Partially Free   (Followers: 125)
Electronics     Open Access   (Followers: 125)
Advances in Electronics     Open Access   (Followers: 122)
Electronics For You     Partially Free   (Followers: 114)
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 112)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 90)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 88)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 87)
IEEE Transactions on Industrial Electronics     Hybrid Journal   (Followers: 85)
IEEE Transactions on Software Engineering     Hybrid Journal   (Followers: 84)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 79)
IET Power Electronics     Open Access   (Followers: 76)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 65)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 62)
IEEE Embedded Systems Letters     Hybrid Journal   (Followers: 60)
IEEE Transactions on Industry Applications     Hybrid Journal   (Followers: 57)
Advances in Power Electronics     Open Access   (Followers: 56)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 52)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 50)
IEEE Nanotechnology Magazine     Hybrid Journal   (Followers: 45)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 45)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 41)
IET Microwaves, Antennas & Propagation     Open Access   (Followers: 35)
IEEE Transactions on Biomedical Engineering     Hybrid Journal   (Followers: 35)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 31)
International Journal of Power Electronics     Hybrid Journal   (Followers: 30)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 27)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 27)
Microelectronics and Solid State Electronics     Open Access   (Followers: 27)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 26)
Journal of Sensors     Open Access   (Followers: 25)
Electronics Letters     Open Access   (Followers: 25)
International Journal of Aerospace Innovations     Full-text available via subscription   (Followers: 23)
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 22)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 19)
IEEE Reviews in Biomedical Engineering     Hybrid Journal   (Followers: 19)
IEEE/OSA Journal of Optical Communications and Networking     Hybrid Journal   (Followers: 19)
Journal of Artificial Intelligence     Open Access   (Followers: 18)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 18)
IET Wireless Sensor Systems     Open Access   (Followers: 17)
Circuits and Systems     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 16)
IEEE Transactions on Signal and Information Processing over Networks     Hybrid Journal   (Followers: 14)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 14)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 14)
Archives of Electrical Engineering     Open Access   (Followers: 14)
International Journal of Control     Hybrid Journal   (Followers: 13)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 13)
Advances in Microelectronic Engineering     Open Access   (Followers: 12)
IEEE Transactions on Learning Technologies     Full-text available via subscription   (Followers: 12)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 12)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 12)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 12)
IEEE Solid-State Circuits Magazine     Hybrid Journal   (Followers: 11)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 11)
IEEE Women in Engineering Magazine     Hybrid Journal   (Followers: 11)
IEEE Transactions on Broadcasting     Hybrid Journal   (Followers: 11)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 10)
International Journal of Advanced Electronics and Communication Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 10)
IETE Journal of Research     Open Access   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
IETE Technical Review     Open Access   (Followers: 9)
Batteries     Open Access   (Followers: 8)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 8)
IEEE Transactions on Autonomous Mental Development     Hybrid Journal   (Followers: 8)
Journal of Power Electronics     Hybrid Journal   (Followers: 8)
China Communications     Full-text available via subscription   (Followers: 8)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 8)
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Metrology and Measurement Systems     Open Access   (Followers: 8)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 8)
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 8)
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 8)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 8)
Solid-State Electronics     Hybrid Journal   (Followers: 7)
Nanotechnology, Science and Applications     Open Access   (Followers: 7)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 7)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
IEEE Magnetics Letters     Hybrid Journal   (Followers: 7)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 7)
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 6)
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Annals of Telecommunications     Hybrid Journal   (Followers: 6)
Electronic Markets     Hybrid Journal   (Followers: 6)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 6)
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 6)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 6)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access   (Followers: 5)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Field Robotics     Hybrid Journal   (Followers: 5)
Energy Storage Materials     Full-text available via subscription   (Followers: 5)
IEEE Pulse     Hybrid Journal   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Batteries & Supercaps     Hybrid Journal   (Followers: 5)
IEEE Transactions on Services Computing     Hybrid Journal   (Followers: 5)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 4)
Wireless and Mobile Technologies     Open Access   (Followers: 4)
Superconductivity     Full-text available via subscription   (Followers: 4)
IEEE Transactions on Haptics     Hybrid Journal   (Followers: 4)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 4)
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Networks: an International Journal     Hybrid Journal   (Followers: 4)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Sensors International     Open Access   (Followers: 3)
Nature Electronics     Hybrid Journal   (Followers: 3)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
EPE Journal : European Power Electronics and Drives     Hybrid Journal   (Followers: 3)
Machine Learning with Applications     Full-text available via subscription   (Followers: 3)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 3)
Informatik-Spektrum     Hybrid Journal   (Followers: 3)
IETE Journal of Education     Open Access   (Followers: 3)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 2)
Power Electronics and Drives     Open Access   (Followers: 2)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal   (Followers: 2)
Advancing Microelectronics     Hybrid Journal   (Followers: 2)
Transactions on Electrical and Electronic Materials     Hybrid Journal   (Followers: 2)
Energy Storage     Hybrid Journal   (Followers: 2)
Journal of Information and Telecommunication     Open Access   (Followers: 2)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 2)
Advanced Materials Technologies     Hybrid Journal   (Followers: 2)
EPJ Quantum Technology     Open Access   (Followers: 2)
e-Prime : Advances in Electrical Engineering, Electronics and Energy     Open Access   (Followers: 2)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 2)
IET Smart Grid     Open Access   (Followers: 2)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 2)
Journal of Nuclear Cardiology     Hybrid Journal   (Followers: 1)
Transactions on Cryptographic Hardware and Embedded Systems     Open Access   (Followers: 1)
ACS Applied Electronic Materials     Open Access   (Followers: 1)
Frontiers in Electronics     Open Access   (Followers: 1)
IEEE Letters on Electromagnetic Compatibility Practice and Applications     Hybrid Journal   (Followers: 1)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 1)
IET Energy Systems Integration     Open Access   (Followers: 1)
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 1)
International Journal of Hybrid Intelligence     Hybrid Journal   (Followers: 1)
Open Electrical & Electronic Engineering Journal     Open Access   (Followers: 1)
Ural Radio Engineering Journal     Open Access   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Електротехніка і Електромеханіка     Open Access   (Followers: 1)
Edu Elektrika Journal     Open Access   (Followers: 1)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 1)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
Automatika : Journal for Control, Measurement, Electronics, Computing and Communications     Open Access  
npj Flexible Electronics     Open Access  
Elektronika ir Elektortechnika     Open Access  
Emitor : Jurnal Teknik Elektro     Open Access  
IEEE Solid-State Circuits Letters     Hybrid Journal  
IEEE Open Journal of Industry Applications     Open Access  
IEEE Open Journal of the Industrial Electronics Society     Open Access  
IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology     Hybrid Journal  
IEEE Open Journal of Circuits and Systems     Open Access  
Journal of Electronic Science and Technology     Open Access  
Australian Journal of Electrical and Electronics Engineering     Hybrid Journal  
Solid State Electronics Letters     Open Access  
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Journal of Engineered Fibers and Fabrics     Open Access  
Jurnal Teknologi Elektro     Open Access  
IET Nanodielectrics     Open Access  
Elkha : Jurnal Teknik Elektro     Open Access  
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Jurnal Teknik Elektro     Open Access  
IACR Transactions on Symmetric Cryptology     Open Access  
Acta Electronica Malaysia     Open Access  
Bioelectronics in Medicine     Hybrid Journal  
Chinese Journal of Electronics     Open Access  
Problemy Peredachi Informatsii     Full-text available via subscription  
Technical Report Electronics and Computer Engineering     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Visión Electrónica : algo más que un estado sólido     Open Access  
Telematique     Open Access  
International Journal of Nanoscience     Hybrid Journal  
International Journal of High Speed Electronics and Systems     Hybrid Journal  

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Similar Journals
Journal Cover
Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [120 journals]
  • An Energy- and Reliability-Aware Task Scheduling in Real-Time MPSoC
           Systems

    • Free pre-print version: Loading...

      Authors: Mohammad Reza Saberikia, Hakem Beitollahi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Reliability and energy efficiency are two hostile objectives considered in designing task scheduling in most real-time multiprocessor systems on chip (MPSoC). Addressing and improving one of them may affect and degrade the efficiency of the other one and vice versa. In this paper, we intend to examine these challenges and ultimately achieve an optimal energy consumption and reliability state. This paper presents a novel scheduling technique that can adapt to the limitations of real-time systems and have optimal energy consumption and reliability. This is done by minimizing the overlap of tasks, adjusting the speed of processors and the number of backups of each task. The proposed scheme reduces energy consumption on average by 11% to 42% compared to the previous state-of-the-art techniques and keeps the reliability at a high level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502255
       
  • A Multi-objective Current Compensation Strategy for Photovoltaic
           Grid-Connected Inverter

    • Free pre-print version: Loading...

      Authors: Shengqing Li, Zhijian Wang, Wang Han
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper aims at resolving problems of harmonic, reactive power and current imbalance. In the process of photovoltaic grid connection, a multi-objective control strategy is proposed, in which the three-phase network controller simultaneously controls the harmonic and realizes the reactive power and current balance. The [math], [math] current detection method, which is based on the current reactive power characteristic theory, can detect the compensation current. In order to reduce the measurement error of PLL, a software PLL based on decoupled double synchronous reference coordinate transformation is introduced, and the principle of multi-objective rule of three-stage network inverter is also given. The simulation and test results show that the harmonic distortion rate decreases from 2.57% to 1.10% with the proposed strategy, and the unbalance between reactive power and current is compensated, which verifies the correctness and feasibility of the strategy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502309
       
  • Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust
           C-Elements

    • Free pre-print version: Loading...

      Authors: Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Glitch at the input can increase the power consumption of flip-flop greatly. To solve this problem effectively, a Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements (LARC) is proposed in this paper. The proposed Latch Multiplexer-A Double-edge Triggered Flip-flop (LARC-DET) can effectively block the glitch at the input and prevent the redundant transition at internal nodes. As a result, the extra power consumption caused by the glitch at the input is effectively reduced. The simulation was performed using HSPICE under 32[math]nm complementary metal oxide semiconductor (CMOS) process. The simulation results show that, compared with 12 double edge flip-flops, the proposed LARC-DET is the lowest in terms of power consumption and power delay product. Process voltage temperature (PVT) variation analysis shows its insensitivity to voltage variation, temperature variation and process variation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502310
       
  • Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET
           Technology

    • Free pre-print version: Loading...

      Authors: M. Elangovan, M. Muthukrishnan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-20T07:00:00Z
      DOI: 10.1142/S0218126622502334
       
  • Mixed-Mode Electronically-Tunable First-Order Universal Filter Structure
           Employing Operational Transconductance Amplifiers

    • Free pre-print version: Loading...

      Authors: Ajishek Raj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-14T07:00:00Z
      DOI: 10.1142/S0218126622502346
       
  • A Framework for Wireless Sensor Network Optimization Using Fuzzy-Based
           Fractal Clustering to Enhance Energy Efficiency

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      Authors: Neha Sharma, Vishal Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor networks’ energy consumption is the major challenge to be handled. Clustering is one of the techniques majorly used for reducing energy consumption. During the course of time, many methodologies are being proposed and the existing ones are hybrid. Still, the energy can be reduced more. The scope of optimization is always there. Existing approaches either reduce energy consumption or work on routing or only on data gathering capabilities. But the technique proposed increases the lifetime of the wireless sensor network (WSN) by reducing energy consumption and improves routing efficiency. This paper proposes an approach based upon Fractal Clustering to improve the lifetime of the sensor nodes. The proposed approach named Enhanced Energy Efficient Fuzzy-based Fractal Clustering (EEFFC) algorithm optimizes the performance of WSN. First, fractal clustering is used on sensor nodes to find the location of the sensors. Then, a fuzzy inference system (FIS) is applied to results produced by fractal clustering. Applying FIS on cluster heads generated will optimize the results. As a result, the cost of data transmission will reduce, and hence, the lifetime of the network will improve. FIS generates multi-level clustering, which will result in a better routing path for sensor nodes. Hence, routing will also be improved. MATLAB 2020 is the simulation tool. The results of the simulation depict that EEFFC shows optimized results and it works better than LEACH, LEACH-SF, TEEN and DEEC. The energy consumption is being reduced by reducing the listening time of a node and by reducing the communication distance, for which clustering is optimized. The energy consumption has been reduced by 2% as compared to the algorithms it is compared with. Also, the node’s time of death has been delayed by 3% in total.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-13T07:00:00Z
      DOI: 10.1142/S0218126622502231
       
  • Random Interference Signal Decomposition and the Normalized Filtering
           Method of an Optical Fiber Current Transducer

    • Free pre-print version: Loading...

      Authors: Fubin Pang, Lihui Wang, Long Wan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Focusing on the problem of characteristic decomposition and filtering of random interference information measured by an optical fiber current transducer (OFCT), a signal filtering algorithm by combing complete ensemble empirical mode decomposition (CEEMD) with normalized autocorrelation function, is proposed. The CEEMD feature decomposition model of the OFCT signal is established and multiple eigenmode functions of the measured signal are extracted. The normalized autocorrelation function models of different types of intrinsic mode function (IMF) are established. By extracting the characteristics of the autocorrelation function, high-weight IMFs are selected. After the mean filtering process is performed on other IMFs, the signal reconstruction is performed together with the effective modal components. With the premise of signal statistical learning and structural risk minimization principles, a support vector regression model is established to classify the data by linear fitting. The more reliable current information after filtered is obtained. Experiment results demonstrate that the proposed signal filtering algorithm by combining the advantages of CEEMD and normalized autocorrelation function decomposes the signal according to the time-scale characteristics of OFCT data itself, without pre-setting any basis functions. The root mean square error of optimized data is reduced by 39.3%, and the signal quality is greatly improved.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-13T07:00:00Z
      DOI: 10.1142/S0218126622502292
       
  • Towards Fast and Accurate Federated Learning with Non-IID Data for
           Cloud-Based IoT Applications

    • Free pre-print version: Loading...

      Authors: Tian Liu, Jiahao Ding, Ting Wang, Miao Pan, Mingsong Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As a promising method of central model training on decentralized device data while securing user privacy, Federated Learning (FL) is becoming popular in the Internet of Things (IoT) design. However, when the data collected by IoT devices are highly skewed in a non-independent and identically distributed (non-IID) manner, the accuracy of the vanilla FL method cannot be guaranteed. Although there exist various solutions that try to address the bottleneck of FL with non-IID data, most of them suffer from extra intolerable communication overhead and low model accuracy. To enable fast and accurate FL, this paper proposes a novel data-based device grouping approach that can effectively reduce the disadvantages of weight divergence during the training of non-IID data. However, since our grouping method is based on the similarity of extracted feature maps from IoT devices, it may incur additional risks of privacy exposure. To solve this problem, we propose an improved version by exploiting similarity information using the Locality-Sensitive Hashing (LSH) algorithm without exposing extracted feature maps. Comprehensive experimental results on well-known benchmarks show that our approach can not only accelerate the convergence rate, but also improve the prediction accuracy for FL with non-IID data.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-13T07:00:00Z
      DOI: 10.1142/S0218126622502358
       
  • Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems
           — A Review

    • Free pre-print version: Loading...

      Authors: K. Aneesh, G. Manoj, S. Shylu Sam
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators, cochlear implants, visual prosthesis etc. have gained immense importance in the personal health monitoring system. Most of these devices are battery powered. The life span of a pacemaker is expected to be between 10 and 12 years. This shows the importance of having an ultra-low power design technique to improve the reliability and battery life of the system. To achieve this, power draws from the battery must be kept low. Analog-to-Digital Convertor (ADC) is a main block in the front-end sensing unit of an implant for measurements of various biophysiological signals. This is the most power consuming unit in the system. ADC alone consumes about 30%–35% of the total power. This work surveys various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit. The different switching schemes for capacitive DAC are also surveyed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622300094
       
  • Bug-Transformer: Automated Program Repair Using Attention-Based Deep
           Neural Network

    • Free pre-print version: Loading...

      Authors: Jie Yao, Bingbing Rao, Weiwei Xing, Liqiang Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a novel transformer-based deep neural network model to learn semantic bug patterns from a corpus of buggy/fixed codes, then generate correct ones automatically. Transformer is a deep learning model relying entirely on attention mechanism to model global dependencies between input and output. Although there are a few endeavors to repair programs by learning neural language models (NLM), many special program properties, such as structure and semantics of an identifier, are not considered in embedding input sequence and designing model effectively, which results in undesired performance. In the proposed Bug-Transformer, we design a novel context abstraction mechanism to better support neural language models. Specifically, it is capable of 1) compressing code information but preserving the key structure and semantics, which provides more thorough information for NLM models, 2) renaming identifiers and literals based on their lexical scopes, structural and semantic information, to reduce code vocabulary size and 3) reserving keywords and selected idioms (domain- or developer-specific vocabularies) for better understanding code structure and semantics. Hence, Bug-Transformer adequately embeds code structural and semantic information into input data and optimize attention-based transformer neural network to well handle code features in order to improve learning tasks for bug repair. We evaluate the performance of the proposed work comprehensively on three datasets (Java code corpora) and generate patches to buggy code using a beam search decoder. The experimental results show that our proposed work outperforms the-state-of-art techniques: Bug-Transformer can successfully predict 54.81%, 34.45%, and 42.40% of the fixed code in these three datasets, respectively, which outperform the baseline models. These success rates steadily increase along with the increase of beam size. Besides, the overall syntactic correctness of all patches remains above 97%, 96%, and 50% on the three benchmarks, respectively, regardless of the beam size.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622502103
       
  • Design and Implementation of Time-Frequency Distributions for Real-Time
           Applications Using Field Programmable Gate Array

    • Free pre-print version: Loading...

      Authors: B. Murali Krishna, B. T. Krishna, K. Babulu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, time-frequency distributions (TFDs) and their hardware implementation on FPGA are presented. TFDs are evolved due to disadvantage of Fourier Transform (FT), which cannot provide time information in spectrum representation. Time-Frequency Representations (TFRs) are helpful in providing simultaneous information about spectral contents of a signal with respect to time period axis. The major problem associated with hardware implementation of TFDs is limited on-board memory. Forward and backward register allocation method (FBRA) is employed to obtain the optimum register occupation. A register of length 32-bit is considered for the input signal representation. The stored register values are applied to the proposed TFDs and computed using real-time hardware. FBRA is implemented during the computation of FFT in all TFDs. All the transforms are modeled using Verilog code and implemented on SPARTA-6 FPGA. A real-time ECG, earthquake and a quad chirp signals are taken as input to test the designed TFDs. Finally, a comparison of different hardware resources utilized on FPGA with earlier conventional methods for better real-time applications was made.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622502176
       
  • Research on Short-Term Low-Voltage Distribution Network Line Loss
           Prediction Based on Kmeans-Lightgbm

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      Authors: Zhu Tang, Yuhang Xiao, Yang Jiao, Xinyu Li, Caixia Zhang, Jun Sun, Peng Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the lack of data quality in real production environment, the traditional line loss calculation method cannot be applied, thus through the investigation of various information systems’ operation in power supply enterprises, a short-term low-voltage distribution network line loss prediction algorithm based on Kmeans-LightGBM is proposed. Operating data quality evaluation system of low-voltage distribution network was set up based on Hadoop platform, the feature dimensions were expanded by feature engineering, then those with no multicollinearity and high correlation with the line loss were selected, data normalization was again performed, Kmeans clustering algorithm was used to cluster the area and then, LightGBM algorithm was used to predict the classes within the area of line loss. Finally, the line loss of the numerical inverse normalization was found and validated with Beijing Power Grid of a low-voltage distribution network. By comparison, the model’s prediction accuracy is found to be higher than BPNN, FOA-SVR and traditional LightGBM.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-09T07:00:00Z
      DOI: 10.1142/S0218126622502280
       
  • Mathematical and Circuit Level Analysis Interpretation and Recommendations
           on Neuron Models

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      Authors: I. Munavar Sheriff, R. Sakthivel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Contrary to von Neumann computer architecture, neuromorphic computing is a biologically inspired method for building several sorts of brain-inspired computers. This computer technology uses silicon neurons and synapses to solve difficult machine learning and AI challenges. The goal of neuromorphic computing is to build a brain-like ability to compute, learn, and adapt. Building an appropriate neuroscience model, establishing a new architecture, modeling new devices, finding new materials for the devices, programming framework, and applications for these neuromorphic devices are major technological challenges. This study covers numerous neuron models from Hodgkin–Huxley to I&F, mathematical equations, circuit level analysis and motivations for neuromorphic computing. Here some of the most useful silicon neuron models are discussed in terms of biological plausibility, computational efficiency, and temperature dependency. This survey shows that more than 52 transistors make up the silicon HH neuron, which occupies less than 0.01[math][math] and consumes 60[math]uW of power. On the other hand, an I&F neuron needs less than 20 transistors, occupies 442[math][math] and consumes 40[math]pW of power.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-05-07T07:00:00Z
      DOI: 10.1142/S0218126622300082
       
  • A Multiserver Configuration and Request Distribution Framework for Profit
           Maximization in a Three-Tier Cloud Service Architecture

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      Authors: Tian Wang, Mingyue Zhang, Wei Shen, Linli Xu, Gongxuan Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The rapid development of cloud computing has generated numerous cloud service providers. In a three-tier cloud service architecture, maximizing the cloud service profit is not only a goal pursued by cloud service providers but also a potent force that drives the continuous development of cloud computing technology. The traditional methods of maximizing cloud service profits are either limited to cloud resource management or service request distribution. Few work contributes to maximizing the profit of cloud service providers while considering both resource management and request distribution. Besides, the heterogeneity of servers is also an important concern when configuring the multiserver system. Therefore, this paper proposes a multiserver configuration and request distribution framework oriented to a three-tier cloud service architecture for maximizing the profit of cloud service providers. Compared with the benchmark method, extensive numerical simulation experiments show that our proposed framework can not only maximize the profit of cloud service providers, but also has a well-time efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-30T07:00:00Z
      DOI: 10.1142/S0218126622502218
       
  • LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area
           for Network-on-Chip Architectures

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      Authors: Anil Kumar, Basavaraj Talawar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from [math] to [math] are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is [math] to [math] with respect to BookSim simulator.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-29T07:00:00Z
      DOI: 10.1142/S0218126622501961
       
  • An Underground Abnormal Behavior Recognition Method Based On An Optimized
           Alphapose-ST-GCN

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      Authors: Xiaonan Shi, Jian Huang, Bo Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the complex underground environment of coal mines, the unsafe behaviors of miners are likely to lead safety accidents. Therefore, research on underground abnormal behavior recognition methods based on video images is gradually gaining attention. This paper proposes an underground abnormal behavior recognition method based on an optimized Alphapose-ST-GCN. First, an image set captured in underground monitoring video is defogged and enhanced by the CycleGAN. Second, the Alphapose target detection is optimized using the LTWOA-Tiny-YOLOv3 model. Third, the ST-GCN is used for abnormal behavior recognition. The image quality of the dataset before and after a CycleGAN enhancement is compared, the convergence curves of LTWOA under four test functions are compared, and the mean average accuracy mAP of the LTWOA-Tiny-YOLOv3 model is evaluated. Finally, the performance of the proposed method is compared with other detection algorithms. The results show that CycleGAN significantly improves the quality of the dataset images. The whale optimization algorithm improved by the logistic-tent chaos mapping has a more significant convergence effect than the other optimization algorithms, and the LTWOA-Tiny-YOLOv3 model has a better recognition accuracy of 9.1% in mAP compared with the unoptimized model. The underground abnormal detection model proposed in this paper achieves an 82.3% accuracy on the coal mine underground behavior dataset.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-29T07:00:00Z
      DOI: 10.1142/S0218126622502140
       
  • Temporal Sequence of Data Fluctuation-Based Approach for Tor Program
           Classification

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      Authors: Hao Zhang, Weidong Zhang, Wei Zhao, Xuangou Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the continuous development of encryption technology, the share of encrypted traffic in the network is increasing, which brings great challenges to the traditional methods of rule-based traffic identification. Deep learning is becoming an inspiring methodology to solve the problem. Previous studies have confirmed that time characteristics play an important role in Tor traffic classification. We find that there is a similarity of time characteristics among different programs. This paper proposes an end-to-end classification framework: the temporal sequence of data fluctuation network (TSDFN). It first extracts the temporal sequence of data fluctuation in the original flow and then uses the GRU network to learn the hidden temporal features. Experiments on public data sets validate the effectiveness of our proposal over other methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622400023
       
  • Learning-Based Health Prediction Method for Airborne DME Receiver with
           Signal Processing Techniques in 6G Networks

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      Authors: Yuhao Zhong, Guocheng Yang, Hua Xu, Xue Qin, Dajiang Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Accurate aircraft positioning is the key to construct a reliable network topology when aircrafts are used to assist 6G cellular networks in ground communications. Distance Measuring Equipment (DME) has been widely used in aircraft positioning with the help of multiple ground-based radar stations. In this paper, a learning-based health prediction method for airborne DME receiver is proposed by using signal processing techniques to achieve quantitative health status assessment and failure degradation trend prediction, when the DME is used to measure the distance between ground-based radar stations and airborne DME. First, a quantitative airborne DME device receiving channel health evaluation model is established, which takes the Automatic Gain Control (AGC) attenuation value and the collected distance between the ground beacon station and the airborne DME receiver with DME device as input, to calculate the receiving channel AGC attenuation value deviation and gain loss. The model can be used to build the mapping relationship between the receiver channel gain loss and the DME function range, and further establish the calculation model of the receiving channel’s health index. Second, a multi-model fusion fault prediction framework based on the Deep Belief Network (DBN) techniques is proposed. In this framework, the problem of insufficient generalization and robustness of the traditional DBN model is solved by introducing the Dropout mechanism into the DBN structure, and an improved weighted voting method is utilized as a model fusion algorithm to eliminate the deviation of prediction results caused by environmental load differences and improve the accuracy of fault prediction. Finally, extensive experiments are conducted to show the feasibility of the proposed method, and the results show that the proposed method has a good performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502073
       
  • A Gated Convolution and Self-Attention-Based Pyramid Image Inpainting
           Network

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      Authors: Hong-an Li, Guanyi Wang, Kun Gao, Haipeng Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Aiming at the problems of imperfect inpainting edges, mismatching inpainting content and slow training caused by large network model parameters and high requirements for image inpainting edge consistency and semantic integrity, this paper designs a gated convolution and self-attention-based pyramid network (GAP-Net), the network is based on U-Net, and it integrates the gated convolution method and the pyramid loss and changes the feature extraction strategy. In addition, we design a self-attention mechanism module and an attention transfer module for the network, designing and adding content loss and perceptual loss for the network, generating a new data distribution between generated and real images. The comparative analysis of experiment with the PEN-Net method and the Gated method is conducted in the same experimental environment. The experimental results show that our method can increase the extraction of useful information from damaged image areas by gated convolution and pyramid loss. Self-attention mechanism module and the attention transfer module can guide the conversion process of high-level semantic features to image information more accurately, and the content and perceptual loss can accelerate and improve the learning ability of the network, this method improves the repair effect and accelerates the network learning speed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502085
       
  • Image Inpainting Based on Contextual Coherent Attention GAN

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      Authors: Hong-an Li, Liuqing Hu, Qiaozhi Hua, Meng Yang, Xinpeng Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to address the problems of traditional inpainting algorithm models, such as the inability to automatically identify the specific location of the area to be restored, the cost of inpainting and the difficulty of inpainting, and the problems of structural and texture discontinuity and poor model stability in deep learning-based image inpainting, this paper proposes an image inpainting based on a contextual coherent attention. This paper designs a network model based on generative adversarial networks. First, to improve the global semantic continuity and local semantic continuity of images in image inpainting, a contextual coherent attention layer is added to the network; second, to solve the problems of slow convergence and insufficient training stability of the model, a cross-entropy loss function is used; finally, the trained generator is used to repair images. The experimental results are compared using PSNR and SSIM metrics, compared with the traditional GAN model, our model has a 3.782dB improvement in peak signal-to-noise ratio and a 0.025% improvement in structural similarity. The experimental results show that the image inpainting method in this paper has better performance in terms of image edge processing, pixel continuity and overall image structure.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502097
       
  • Application Optimization of Cloud Management Mode in Information
           Technology in Sudden Social Security Incidents

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      Authors: Haining Huang, Lihua Xu, Haomin Lu, Zhencheng Lin, Wei Yan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the change of social structure and management mode, emergency social security incidents have become the focus of social security management. In order to solve the problems of insufficient overall performance and low security in the practical application of cloud management mode in traditional social security emergencies. With the use of improved pick-KX load balancing algorithm and RSA encryption algorithm, this paper optimizes the cloud computing model and applies it to the cloud management mode of emergent social security events. Then the optimized cloud management model is simulated and evaluated by the multi-level fuzzy comprehensive evaluation model. The simulation results reflect that the proposed cloud management model in this paper is able to effectively improve the management effect of social security events.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502127
       
  • Clustering-Based Semi-Supervised Cross-Modal Retrieval Using Scene Graph

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      Authors: Yixue Kong, Yong Feng, Mingliang Zhou, Xiancai Xiong, Yongheng Wang, Baohua Qiang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a clustering-based semi-supervised cross-modal retrieval method to relieve the problem of insufficient annotation in cross-modal datasets. First, we reconstruct cross-modal data as scene graph structure to filter meaningless information. Second, we extract embedding representation features of images and texts to put them into a common space. Finally, we propose a clustering-based classification method with modality-independent constraint to discriminate samples. According to our experimental results, significant improvement on performance shows the accuracy of our method in terms of three widely used cross-modal datasets compared with the state-of-the-art methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502139
       
  • The Industrial Internet of Things (IIoT): An Anomaly Identification and
           Countermeasure Method

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      Authors: Usman Tariq, Tariq Ahamed Ahanger, Atef Ibrahim, Yassine Saleh Bouteraa
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Networked devices benefit enterprises to gain far-reaching control over their industrial processes, which encourages them to conduct routine operations in a smart manner. Rapidly expanding interconnected sensor devices are eligible to aggregate, process and disseminate wide-ranging data. This paper proposed an extended anomaly discovery and response framework. We argued the prospective security anomalies to the IoT equipped industrial-floor and examined the numerous attacks that are conceivable on the modules in the Industrial Internet of Things (IIoT) architecture. IIoT service layer architecture was designed in consideration of high-volume device connectivity, management and security enforcement. Collection of geospatial service and device data aided the proposed framework to bridge the gap between anomaly identification and context-aware node behavior. Framework evaluation considered design principles such as node interpretability, decentralization, real-time data relay, modularity and required service alignment. Emulation outcomes specify that the malware discovery performance is better if the anomaly recognition model used the applied utility for the yield layer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S021812662250219X
       
  • A Dynamic Load Balancing Algorithm for IoV CoMP Communications

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      Authors: Derong Du, Linlin Jiang, Tan Guo, Lingqian Wu, Long Li, Xiaoping Zeng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to uneven space–time distribution of vehicles, Internet of Vehicles (IoV) has problems with load imbalance and low resource utilization of Base Stations (BSs) in the Coordinated Multi-Point (CoMP) communication scenario. This paper proposes a dynamic load balancing algorithm based on vehicle prediction. It is assumed that the number of vehicles arriving at the BSs obeys the segmented Poisson distribution to determine the current and predicted load statuses of BSs. First, analyze the load status of each BS and the location of users (vehicles). Then, screen out BSs whose load below the full load threshold as a switchable low-load cooperative cluster, which can convert interference signals into useful signals and reduce the interference between adjacent BSs. Finally, complete load balancing by redistributing the communication service of edge users through sharing channel information and user date among coordinated BSs. Because IoV is a dynamic network, the proposed algorithm runs dynamically in cycles. Simulation results show that the algorithm can perform balance the load of BSs well, the overload rates of BSs during the traffic off-peak period and peak period are reduced significantly, and the average information rate of users is greatly improved.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-27T07:00:00Z
      DOI: 10.1142/S0218126622502206
       
  • A Magnetically Coupled-Inductor Boost Converter with High Bandwidth and
           Fast Dynamic Response

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      Authors: Alireza Goudarzian, Ehsan Adib
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Transient modeling analysis of the traditional DC/DC converters shows their worse effect of nonminimum-phase characteristics due to right-half-plane (RHP) zero existence in their plant transfer function. This RHP zero restricts the bandwidth of the switching converters and, that is the main reason for slower response. The motivation of this paper is to present a new technique for eliminating the RHP zero from the dynamics of a conventional boost converter that can solve the problems associated with the nonminimum phase converters and, to focus on its analysis, design and modeling to achieve a high voltage gain as well as the RHP zero cancellation. The proposed technique uses a transformer combined with switching capacitor cells. The striking feature of the suggested topology is its minimum-phase structure, further enhancement of the voltage gain, switching stress reduction, achievement of an improved frequency response and easiness for the design of a closed-loop control scheme to perform the voltage trajectory tracking task. First, the operation of the proposed converter is identified and then, the corresponding circuit performance is evaluated. By using a suitable design, the control-to-output-voltage transfer function is completely free from the RHP zero. The significant advantages of the proposed converter are established via comparisons. To confirm the design approach and theoretical findings, the simulations are introduced and, numerical experimental results such as Bode diagrams are presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S021812662250205X
       
  • Neuron Network with a Synapse of CMOS transistor and Anti-Parallel
           Memristors for Low power Implementations

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      Authors: V. Keerthy Rai, R. Sakthivel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The bio-mimetic structure of a neuron is taken into account for utilizing the electrophysiological data. These neuron circuits are entertained for the use in digital computers. At the end of Moore’s law, conventional technology is striking different difficulties, such as power consumption, area utilization, and energy efficiency. To conquer these hurdles, a nanoscale, the nonvolatile memristor used in the proposed neuron modified from the refined AH neuron. Synapses are also built using anti-parallel memristors. These neurons and synapse are joined together such that the performance metrics are analyzed the energy consumption is reduced by 89.656%. Besides, power consumption is limited by 37.568% and the spike frequency is measured as 10.263[math]kHz when compared with the traditional CMOS synapse connected with the proposed neuron. Moreover, the measured energy per spike is 3.37[math]fJ. The implementation of the neuron network is done by 45[math]nm technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S0218126622502061
       
  • Blind Image Inpainting Using Low-Dimensional Manifold Regularization

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      Authors: Mei Gao, Baosheng Kang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a novel method for blind image inpainting, which can restore images with missing or corrupted pixels, or images where the location of the damaged pixels is unknown. The method applies weighted nonlocal Laplacian to address the problem of blind image inpainting using low-dimensional manifold model (LDMM) regularization, and uses semi-local blocks instead of point integrals to implement constraints in LDMM. This solves the problem of low solution efficiency caused by the asymmetry of the linear equations solved by point integration, and the problem of the high iteration count to get good restoration effect. Experiments show that our method is competitive with latest methods in terms of both repairing images with large missing pixels rate and inpainting speed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S0218126622502115
       
  • Bifurcation Fusion Network for RGB-D Salient Object Detection

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      Authors: Zhi-Hua Zhao, Li Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of sensor technology, multi-modal data fusion methods based on deep neural networks provide a reliable guarantee for object recognition and detection in complex scenarios. Most of the existing RGB-D image salient object detection methods improve the salient object detection methods in 2D scenes, which have many problems, such as ineffective fusion of feature information, incomplete image feature extraction and so on. Aiming at these problems, we proposed a salient object detection method based on bifurcated fusion network. First, we use the high- level features of the global context to locate the salient object, then we use the low-level features of the local details to extract the edge information. Second, we model the RGB information and depth information through the gate channel transformation control mechanism, and construct the bifurcation backbone network model and generate the initial salient map. Finally, based on the initial salient map and low-level features, the final salient map is generated. Experimental results show that the proposed method can fully utilize the multi-layer feature information of the image and effectively detect the salient object.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-22T07:00:00Z
      DOI: 10.1142/S0218126622502152
       
  • Analysis and Design Optimization of a 2-Path Sigma Delta Modulator

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      Authors: Reyhaneh Barzegar, Hossein Miar Naimi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new design for the optimization of analog to digital sigma delta-coupling noise annotations. The proposed technique increases the level of the signal-to quantization-noise-ratio (SQNR) by improving the zero of the noise transfer function, which leads to an increase in signal to noise. In the new SQNR design, the modulator rises up to 8.5 db. The proposed structure of the first-order dual-channel sigma-delta modulator is also presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-20T07:00:00Z
      DOI: 10.1142/S0218126622502036
       
  • A Compact Planar Multi-Resonant Multi-Broadband Fractal Monopole Antenna
           for Wi-Fi, WLAN, Wi-MAX, Bluetooth, LTE, S, C, and X Band Wireless
           Communication Systems

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      Authors: Ibrahime Hassan Nejdi, Sudipta Das, Youssef Rhazi, Boddapati Taraka Phani Madhav, Seddik Bri, Mustapha Aitlafkih
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a highly efficient tree-shaped fractal antenna with multi-broadband resonance characteristics is proposed. The proposed antenna exhibits broad operating bandwidth, high gain, and high efficiency characteristics due to the suggested modifications in the antenna geometry. The suggested circular patch is modified by introducing slots in the form of a tree-shaped fractal structure, and the partial ground plane is modified by incorporating a narrow rectangular slot. The proposed antenna is designed on an FR4 substrate of [math][math]mm3. The prototype of the proposed antenna has been fabricated and tested to justify the simulation results. The measurement results are in good agreement with the simulation that validates the multi-broadband design approach of the proposed fractal antenna. As per the measurement results, the proposed antenna operates at four distinct bands with [math]10[math]dB impedance bandwidths of 600[math]MHz (2.2–2.8) GHz, 1070[math]MHz (3.3–4.37) GHz, 2550[math]MHz (4.75–7.3) GHz, and 2200[math]MHz (9.7–11.9) GHz. Furthermore, a high peak gain of 10.23[math]dB and a peak radiation efficiency of 96.65% are recorded for the suggested fractal antenna. The suggested compact bandwidth enhanced multi-band antenna can be useful for several wireless communication systems such as wireless fidelity (Wi-Fi), wireless local area network (WLAN), Bluetooth, long-term evolution (LTE), C, S and X bands.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-20T07:00:00Z
      DOI: 10.1142/S0218126622502048
       
  • Wireless Multimedia Sensor Network QoS Bottleneck Alert Mechanism Based on
           Fuzzy Logic

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      Authors: Achyut Shankar, K. Sumathi, P. Pandiaraja, Thompson Stephan, Xiaochun Cheng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless Multimedia Sensor Networks (WMSNs) are mostly affected by bottleneck issues, high packet loss, increased delay, and minimum throughput. One of the most effective schemes towards controlling the bottleneck on the web is traffic control. The WMSNs handle different types of data, hence QoS is essential to afford trustworthy as well as reasonable services towards these kinds of data. The existing congestion control methods, FTLP and FEWPBRC consider the frequency of packet transmission and decide on the output transmission rate of the sink. In the Fuzzy-Based QoS Alert Bottleneck Mechanism, the probability of congestion is predicted by using a fuzzy inference system with three special congestion indicators, and the traffic rate is adjusted based on the priority of the real-time and non-real-time applications. The FBQACC is simulated using the NS2 simulator and it gives an improvement in the average throughput FTLP and FEWPBRC by 7.1499% and 6.3327%, respectively. Similarly, FBQACC reduces average delay compared to FTLP and FEWPBRC by 11.074% and 7.8128%, respectively. The proposed work also gives a minimized average packet loss percentage compared to the existing congestion control methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-18T07:00:00Z
      DOI: 10.1142/S0218126622501985
       
  • Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide
           Reliability

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      Authors: Dharmaray Nedalgi, Saroja V. Siddamal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a [math] tolerant I/O buffer with low voltage (VDD) devices. A novel bootstrap circuit for mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and gate oxide reliability issues. The proposed circuit is designed using 1.8[math]V thick gate devices in 22-nm FinFET technology with 1.8[math]V signaling and tolerant to 3.3[math]V. The structure can be used in any CMOS technology for [math] tolerant I/O buffer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-18T07:00:00Z
      DOI: 10.1142/S0218126622502024
       
  • Artificial Intelligence in the Auxiliary Guidance Function of Athletes’
           Movement Standard Training in Physical Education

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      Authors: Zhenzhen Su
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Artificial Intelligence (AI) is a new technical science that studies and develops theories, methods, techniques and application systems for simulating, extending and expanding human intelligence. This paper is based on the research of AI in the auxiliary guidance function of athletes’ standard training in physical education. It aims to conduct data mining from different aspects such as different joint angular speeds, motion injury screening and different parts of sports injuries and then integrate these aspects. Create a way to reduce athletes’ injuries and scientific training. In order to improve the recognition efficiency of athletes’ movement patterns, nonlinear auto regressive neural networks are used to recognize the movement patterns of athletes’ limb surface signals. Through this research work, it can provide a certain reference basis and practice platform for the research on the auxiliary guidance role of AI in the sports standard training of athletes in physical education. Performance design and implementation include four modules: Image acquisition, preprocessing, motion detection and human motion recognition. Between them, the image acquisition module uses a memory mapping path to determine the format of the camera frame image, and the image format conversion is completed through channel conversion. Experimental data shows that athletes’ strength quality, speed of action response, technical continuity, psychological stability and physical control ability have all been greatly improved. Among them, the most obvious is that with the assistance of AI technology, the psychological stability has reached 9.2; the strength quality has reached 9.1.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S0218126622400011
       
  • 0.4-V Bulk Driven Logarithmic Amplifier for Ultra-Low-Power Biomedical
           Applications

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      Authors: Dipesh Panchal, Amisha Naik
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a design and simulation of a low-noise, low-voltage, and low-power complementary metal oxide semiconductor (CMOS) logarithmic amplifier for biomedical applications like digital hearing aid applications. The amplifier block of analog front end is used as a logarithmic amplifier, based on the progressive-compression parallel-summation architecture with DC offset cancelation by adding an off-chip coupling capacitor at each stage. A fully nontailed differential limiting amplifier with bulk-driven input pair is used to achieve larger voltage gain and low voltage operation. The proposed logarithmic amplifier was designed and simulated with process parameters variation in standard 0.18-[math]m CMOS technology. The circuit operates with a single 0.4-V power supply voltage and dissipates 0.832[math][math]W. The simulated input dynamic range is about 60[math]dB, which covers the input amplitudes ranging from 1[math][math]V to 10[math]mV, and the [math]3-dB bandwidth of the amplifier is from 400[math]Hz to 8.27[math]kHz with simulated total input-referred noise is 0.731[math][math]V@8 kHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S0218126622501882
       
  • Analysis of Injection Locking in Ring-Based Divide-By-Two Frequency
           Dividers

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      Authors: Lazhar Fekih-Ahmed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we introduce a unified nonlinear injection locking model of a large class of 1:2 frequency dividers. The model is valid for two-stage dividers, injected with two-phase or single-phase current or voltage sources. We show that this class of dividers can be rigorously analyzed using the theory of planar nonlinear dynamical systems. We provide accurate compact expressions for the locking range, amplitude, frequency and phase noise. The formulas are validated for two types of frequency dividers using simulations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S021812662250195X
       
  • Identity Authentication Based on Music-Induced Autobiographical Memory EEG

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      Authors: Xin Xu, Lan Jiang, Tingting Xu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The need for identity authentication has become essential in various aspects of people’s life. In this paper, we propose a novel biometric authentication strategy based on music-induced autobiographical memory electroencephalogram (EEG). Specific music is used to induce the stable autobiographical memory, while the EEG signals are collected through the memory process. Users can authenticate themselves by recollecting their minds when listening to the music, which is closely related to their long-term memory. Based on six types of EEG features from 12 subjects, mean F1 score of 0.937, 0.936 and 0.968 are achieved using Logistic Regression, Support Vector Machine and RUSBoost classifier, respectively. This promising result indicates the high distinctive characteristics in music-induced autobiographical memory EEG, which is suitable for identity authentication applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-13T07:00:00Z
      DOI: 10.1142/S0218126622502012
       
  • A PFC Scheme for the Inverse Watkins Johnson Converter for Polarity
           Reversible Buck Boost DC Output Voltage

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      Authors: V. Jothi Arulkumar Austin, A. Ravi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A power factor correction (PFC) scheme for the Inverse Watkins Johnson Converter (IWJC) drawing power from a single-phase AC source, delivering polarity reversible DC voltage output is presented in this paper. The IWJC is basically a DC-to-DC converter which can deliver a boosted positive output voltage or a negative output voltage with buck or boost feature. It is suitable for driving DC loads, typically, DC motors in forward or reverse direction. Unlike the conventional four quadrant DC chopper, the IWJC can boost the input voltage and deliver a voltage higher than the source voltage with duty cycle controlled polarity reversible feature. This paper presents the methodology of including a PFC strategy for the IWJC, when fed from a single-phase AC supply. The proposed methodology has established that the AC source side power factor is unity and that the source current is maintained sinusoidal. Simulations and experimental verifications validate the proposed idea.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-11T07:00:00Z
      DOI: 10.1142/S0218126622501997
       
  • Mathematical Modeling of Buck Converter with Relay Feedback

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      Authors: R. Ramaprabha, Anjana Ethirajan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes the idea of mathematical modeling of the buck converter. The modified approach is achieved through the relay feedback (RF) method and the changes are introduced on the converter output with a soft start. Mathematical modeling of the buck converter is achieved by the state-space model (SSM) and converter’s transfer function (TF) to attain stability. By iteration, the proportional-integral (PI) parameters are tuned by a controller that is incorporated in the RF. The output voltage changes are introduced by maintaining the relay-tuned PI control. The concept requires small tuning times which is obtained at a reduced cost. The effectiveness of buck converter using RF is validated in simulation and hardware.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-09T07:00:00Z
      DOI: 10.1142/S0218126622501912
       
  • TCA: Telecom Credit Assessment Assisted by Edge Intelligence

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      Authors: Hao Hu, Xu Du, Feier Qiu, Shiwei Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With China’s economic transformation into a high-quality development stage, the importance of credit system construction has become increasingly prominent. The problems existing in the current telecom credit system include: (1) insufficient coverage of credit features; (2) traditional credit assessment models are difficult to reflect user credit status objectively, comprehensively and timely; (3) user demand for credit management and credit services are ignored. Due to these deficiencies, a new multi-level credit system is necessary to meet the rapid development of market economy. Telecom operators have large amount of precious data, with the advantages of large-scale, high-precision and data-diversity, which can provide new ideas for the construction of credit system. This work focuses on the current problems and conducts research as follows: design a Telecom Credit Assessment Model based on Boosting and Stacking ensemble techniques, called TCAMBS, to improve the evaluation accuracy, and to select the best model according to the experimental results. On the one hand, this work can promote the innovation of telecom credit assessment models and provide new ideas for the construction of the credit system. On the other hand, this work will also help telecom operations to improve the quality of telecom credit services.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-08T07:00:00Z
      DOI: 10.1142/S0218126622501973
       
  • High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid
           PTL/CMOS Logic

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      Authors: Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-08T07:00:00Z
      DOI: 10.1142/S0218126622502000
       
  • A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery
           Circuit

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      Authors: Shuxiang Song, Zefa Liu, Mingcan Cen, Chaobo Cai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5[math]Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector’s phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit’s total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40[math]nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5[math]Gb/s. With a pseudo-random bit sequence (PRBS) of [math], the measured result shows that the bit error rate (BER) is [math], and the root mean square jitter recovered in the output is 0.302 [math]. The circuit’s jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8[math]mW with a 5.98[math]pJ/bit energy efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-04T07:00:00Z
      DOI: 10.1142/S0218126622501900
       
  • Tree-Like Branching Network for Single Image Super-Resolution with
           Divide-and-Conquer

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      Authors: Ying Zhao, Zeliang Zhao, Kun Shao, Shu Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a tree-like branching network for image super-resolution. Specifically, the network consists of information divide-and-conquer groups (IDCG) to preserve the low-frequency structure of images as well as restore high-frequency information. The kernel of IDCG contains several essential components: (a) a simple attention module and an effective residual attention module to maintain low-frequency structures and restore high-frequency information, (b) a novel local merge cell alleviates information redundancy that flexibly and adaptively fuses multiple informative features from different states. Lastly, a multi-scale aggregation unit is designed to improve the final reconstruction. Through a series of experiments, we prove that our method is more effective than previous state-of-the-art results in both quantitative and qualitative evaluation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-01T07:00:00Z
      DOI: 10.1142/S0218126622501924
       
  • Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS
           Technology

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      Authors: Dina M. Ellaithy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-04-01T07:00:00Z
      DOI: 10.1142/S0218126622501936
       
  • SNN Simulation Performance Prediction: A Nonempirical Method

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      Authors: Guoliang Zhu, Xia Hua, Gongjian Yu, Zhilei Chai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As a third generation artificial neural network, spiking neuron network is expected to expand the artificial intelligence world. However, as a more detailed simulation of brain, a single run of spiking neural networks (SNNs) simulation can take hours to days. To get a better prediction of SNN simulation performance, existing work requires gathering result of actual runs to conduct accurate modeling. In this paper, we propose a nonempirical SNN simulation performance prediction method, prototyped in a hybrid CPU-FPGA cluster. Experiments show that our method, without actual simulation run, can get comparable accuracy with orders of magnitude less runtime cost.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-30T07:00:00Z
      DOI: 10.1142/S0218126622501833
       
  • Design of Voltage Level Shifter Using CNTFET and Analysis of Process
           Voltage Temperature Variation

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      Authors: Vikash Prasad, Debaprasad Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, we have presented the design of voltage level shifter using carbon nanotube field effect transistors (CNTFETs). The proposed design is capable of converting two input voltage levels to two output voltage levels. The threshold voltage of CNTFETs is suitably chosen to achieve the desired output. The proposed design can perform both up and down shifting which is very useful in the system-on-a-chip design to interface with other peripherals. It exhibits lower delay and power delay product in comparison with the existing complementary metal–oxide–semiconductor-based voltage level shifters. The proposed circuit is very effective as it eliminates the requirement of additional voltage level shifter for designing systems with multi-power supply voltage domain in the nanoscale regime. The design has been analyzed for different process, voltage and temperature corners. It has been shown that the design works perfectly with [math] variation in the diameter of the carbon nanotubes used in the CNTFET. The performance varies slightly with [math] variation in operating voltage. Our analysis shows that the design is thermally stable for a wide variation in operating temperature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-30T07:00:00Z
      DOI: 10.1142/S0218126622501857
       
  • Short-Term Load Forcasting for Smart Power Systems Using Swarm
           Intelligence Algorithm

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      Authors: N. Prakash, B. Vaikundaselvan, S. S. Sivaraju
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to succeed in our everyday life, efficient performance of the power system is of utmost importance, and hence, all the sub-sectors of the power system should be analyzed for the purpose of achieving efficiency and accuracy. It must also be remembered that load forecasting assists a lot to improve the power system. Moreover, it contributes substantially to formulate logical approaches for emerging short-term load forecasting (STLF) for all days including the distinct days and make them follow a uniform standard. Of all the techniques which have been applied so far, honey bee-optimized Euclidean norm, based on fuzzy inference system, is used for identifying the problems, and in addition, support vector classifier is utilized to prepare the STLF models. Parameters — temperature, humidity, monsoons, wind, cloud density, dew point, season, hour of the day, day of the week, distinct day, and holiday — have been taken into account for the current study. A well-prepared database can be used for regression which will be of immense help to forecast the load using artificial intelligence. For every day of a month, the MAPE is computed (using the forecasted and actual hourly values) in order to observe the accuracy of STLF. The planned method has been very successful for the load forecast of all days for all seasons. The forecast has been done using the technique for a real time data of one year (test forecast year) with a historical dataset collected for a period of two years, and the results obtained for all seasons have been found to be satisfactory. STLF has helped to find better values due to its pace, and become healthier than other methods already in practice. With the advent of smart grid, the data will be accessible at more granular level as smart meters have capability to provide consumer load, usage data on-line and this facility will be of great help to utility operators and planners for operations on-line. How to use the data available from smart meters for better STLF is a challenging task and it would draw much attention for future research.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-30T07:00:00Z
      DOI: 10.1142/S0218126622501894
       
  • High Dimensional Convolution Acceleration via Tensor Decomposition

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      Authors: Xinyu Du, Zichen Gu, Longquan Dai, Jinhui Tang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The high-dimensional convolution, in either linear or nonlinear form, has been employed in a wide range of computer vision solutions due to its beneficial smoothing property. However, its full-kernel implementation is extremely slow. We do need a fast algorithm for this important operation. To solve this problem, we propose an acceleration pipeline assembled by three steps: [math]-D nonlinear convolution [math] [math]-D linear convolution [math] 1-D dimensional convolution [math] 1-D recursive box filter. Thanks to the low computational complexity of box filtering, we speed up the computation significantly. Roughly speaking, our contribution is two-fold: (1) establishing the connection between the high-dimensional convolution acceleration algorithm and tensor decomposition; (2) propose total four acceleration technologies including demultiplexing–blurring–multiplexing framework, convolution decomposition, periodic tensorization and recursively box filtering to compose our acceleration pipeline under the line of the above connection. The effectiveness of these techniques is demonstrated in various comparisons and experiments. The running times of various applications are largely shortened from several minutes to fewer seconds or less.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-28T07:00:00Z
      DOI: 10.1142/S0218126622501870
       
  • First-Order All-Pass Filters Comprising One Modified DDCC-

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      Authors: Ahmet Abaci, Halil Alpaslan, Erkan Yuce
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, two new first-order voltage-mode all-pass filters (APFs) are proposed. Each of the proposed APFs comprises a single modified DDCC-, and has high input impedance. The first and second APFs can provide first-order noninverting and inverting APF responses, respectively. As passive elements, the first APF comprises two grounded capacitors, and a floating resistor while the second one uses a grounded resistor, a floating resistor and a grounded capacitor. However, both of the APFs suffer from a matching problem. Two quadrature oscillators (QOs) obtained from the APFs are presented. Simulations of the APF and QO circuits are fulfilled via the SPICE program. Besides, diverse experiments for the APFs are made to verify the performances.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-25T07:00:00Z
      DOI: 10.1142/S0218126622501845
       
  • Theory of Extended Forms of Switching Function

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      Authors: Yavuz Can
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In switching algebra, there exist standard forms of Boolean functions such as the disjunctive or conjunctive form. This paper discusses the theory of the extended standard forms of Boolean functions. In addition to the four existing standard forms, two further forms are introduced and thus expanded to six basic forms. On the one hand, the existence of the extended forms is presented and on the other hand new formulas and equations are illustrated. Equations relating to the resolution and/or solution of conjunction/disjunctions are detailed and proven to be valid. In addition, equations for conversion between forms are exemplified. Finally, certain formal relations between the basic forms that are valid under certain conditions are featured.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-25T07:00:00Z
      DOI: 10.1142/S0218126622501869
       
  • Resolution-Selective and Resolution-Adaptive 2 to 8-Bit Flash ADC for
           High-Speed Application-Independent IC (HS-AIIC)

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      Authors: Sarfraz Hussain
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512[math]mW of power with an ENOB of 7.56 bits and SNDR of 46.27[math]dB for 1[math]GHz sampling clock pulse.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S0218126622501699
       
  • The Comparison, Analysis and Circuit Implementation of the Chaotic Systems

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      Authors: Shaohui Yan, Qiyu Wang, Xi Sun, Ertong Wang, Zhenlong Song, Wanlin Shi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A four-dimensional chaotic system with complex dynamical properties is constructed. The complexity of the system was evaluated by equilibrium point, Lyapunov exponential spectrum and bifurcation model. The coexistence of Lyapunov exponential spectrum and bifurcation model proves the coexistence of attractors. [math] and SE complexity algorithms are used to compare and analyze the corresponding complexity characteristics of the system, and the most complex integer-order system is obtained. In addition, the circuit to switch between different chaotic attractors is novel. In particular, more complex parameters are selected for the fractional-order chaotic system through the analysis of parameter complexity, and the rich dynamics of the system are analyzed. Experimental results based on Field-Programmable Gate Array (FPGA) platform verify the feasibility of the system. Finally, the most complex integer-order system is compared with its corresponding fractional-order system in image encryption, so that the fractional-order system has a better application prospect.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S0218126622501705
       
  • Single Active Element Based Electronically Controllable Capacitance
           Multiplier

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      Authors: Winai Jaikla, Pintira Huaihongthong, Surapong Siripongdee, Amornchai Chaichana, Peerawut Suwanjan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor ([math] and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current ([math] and control voltage ([math] without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18[math][math]m TSMC technology with [math][math]V power supplies. The multiplication factor is designed to be [math] by choosing [math][math]V, [math][math][math]A and [math] pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz–8.91[math]MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with [math][math]V power supplies. The experiment is conducted under the same multiplication factor ([math]) as the simulation by choosing [math] k[math] (1% passive resistor), [math][math][math]A and [math][math]nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1[math]kHz–1.25[math]MHz). By adjusting the bias current from 17.67[math][math]A to 400 [math]A, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39[math][math]A. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S0218126622501754
       
  • An Improved Multi Objective Mayfly Algorithm for Solving Optimal Power
           Flow Problem Considering Different Loading Conditions

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      Authors: S. Ramesh, K. Vijaya Bhaskar, K. Karunanithi, M. Ettappan, P. Chandrasekar, S. P. Raja
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an improved multi-objective mayfly algorithm (IMOMA) to resolve the optimal power flow (OPF) problem in a regulated power system network with different loading conditions. The OPF problem, considered a multi-objective optimization problem, comprises multiple objective functions related to economic, technical, operational and security aspects. The IMOMA algorithm has been developed by implementing the simulated binary crossover (SBX), polynomial mutation and dynamic crowding distance (DCD) operators in the original multi-objective mayfly algorithm (MOMA).The OPF problem is analyzed by considering multiple objective functions in the IEEE30-bus test system, the IEEE118-bus test system and the 62-bus Indian utility system. The hypervolume performance metric is used to compare the performance of the MOMA and IMOMA with respect to different operating scenarios. Further, loading conditions ranging between 150% and 50% of the base load are considered for the evaluation. The effectiveness of the IMOMA over the MOMA is observed from the results of the different loads. The best compromise solution is obtained from a set of pareto optimal solutions by implementing the TOPSIS method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S0218126622501778
       
  • Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable
           Computing

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      Authors: Nirupma Pathak, Bandan Kumar Bhoi, Neeraj Kumar Misra, Santosh Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and low-power consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the first time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S021812662250178X
       
  • Instantaneous Lane-Changing Type Aware Lane Change Prediction Based on
           LSTM in Mixed Traffic Scenario

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      Authors: Kai Gao, Xunhao Li, Lin Hu, Di Yan, Binren Luo, Ronghua Du
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development and application of autonomous technology in vehicles, we are going to see more autonomous vehicles on the roads in a foreseeable future. While autonomous vehicles may have the advantage of reducing traffic accidents caused by human drivers’ neglect and/or fatigue, one of the challenges is how to develop autonomous driving algorithms such that autonomous vehicles can be safely deployed in a mixed traffic environment with both autonomous vehicles and human-driven vehicles. Instantaneous lane-changing type may be significantly different for human drivers, which would lead to traffic accidents with other vehicles including autonomous vehicles. In this paper, we propose a resilient algorithm for the prediction of the human driver’s lane-changing behaviors. The proposed algorithm uses a long-short term memory (LSTM) classifier to identify the conservative lane change and the aggressive lane changing and accordingly makes the accurate prediction on lane changes in the driving of vehicles by human drivers. The proposed method provides a useful addition in facilitating the design of more advanced driving algorithms for autonomous vehicles. Using the vehicle trajectory data in the NGSIM data set for a large number of simulations, the effectiveness of this method has been confirmed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S0218126622501808
       
  • A Framework for Solving the Source Localization of the EEG Measurements
           with the Application of Particle Filtering with Branching Resampling

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      Authors: Santhosh Kumar Veeramalla, V. Hindumathi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Inverse algorithms are used to assess EEG source parameters. This involves identifying unknown voxels in hundreds of different regions, giving an incomplete picture of the brain. There are no uniform solutions since the same sensor output may come from many source configurations. To overcome the lack of uniqueness, one must consider previous information and parameters inherent in the source. Our goal is to predict the location of brain sources from the recorded EEG signal without any prior knowledge of sources. We applied a particle filter to locate the brain sources in this article. The degeneracy of particle weights limits the particle filter’s performance. Various resampling techniques are suggested to address this problem. The performance of the branching resampling approach is compared to a systematic resampling method for brain source localization. To perform assessment and comparison studies, both simulated and real EEG data are used.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S021812662250181X
       
  • Improving the Performance of a Doping-Less Carbon Nanotube FET with Dual
           Junction Source and Drain Regions: Numerical Studies

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      Authors: Maryam Ghodrati, Ali Mir
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new structure using dual junctions in the source and drain regions is proposed to improve the electronic characteristics of the doping less carbon nanotube FET. To simulate the proposed structure, the Poisson–Schrodinger equation self-consistent solution method through the nonequilibrium Green’s function (NEGF) procedure has been used. The proposed structure is formed by dividing the source and drain regions into two parts with the same lengths and different work function for each part. The simulation results show that the short channel effects (SCEs) including the sub-threshold swing (SS) and the drain-induced barrier lowering (DIBL) are improved. Also, OFF current has a significant reduction, which in turn increases the current ratio. Besides, improving the ambipolar behavior and leakage current are other benefits of the proposed structure.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-24T07:00:00Z
      DOI: 10.1142/S0218126622501821
       
  • A Two-Step Horizon Optimum Switching Vector-Model Predictive Control with
           a Novel Shunt Active Filter Reference Current Extraction

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      Authors: Kumar Reddy Cheepati, Marco Rivera, Patrick Wheeler, Vivekanandan Subburaj, Suresh Krishnan, Suresh Babu Daram, Karnam Amaresh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Shunt active filters (SAFs) can be used for harmonic mitigation, reactive power compensation and power factor control in electrical distribution networks. Model predictive controller (MPC) can be used to give optimum performance for SAF’s due to its inherent cost function optimization. The SAF’s reference current extraction technique in finite control set-MPC (FCS-MPC) plays a vital role in the effectiveness of the SAF’s operation. The advantage of FCS-MPC is that it closely tracks the reference and injects the required compensating currents by optimizing the SAF’s switching vector and it does not require an external modulator for pulse generation. FCS-MPC can be implemented as either an optimal switching vector MPC (OSV-MPC) or an optimal switching sequence MPC (OSS-MPC) technique. The OSV-MPC technique is simple and efficient for SAF applications. In this paper, a novel reference current extraction technique, the inverse matrix average pq-synchronous reference frame (SRF) (IMApq-SRF) technique, is proposed along with the OSV-MPC technique. Practically a two-step delay compensation is essential in the implementation of the technique for the control of an SAF. Hence in this paper a two-step horizon OSV-MPC technique is proposed along with an IMApq-SRF reference current extraction technique to improve the power quality in distribution networks. The presented results show that the proposed methodology gives optimum SAF performance under a large range of supply and load conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-19T07:00:00Z
      DOI: 10.1142/S0218126622501742
       
  • A Sub-1-V CMOS Voltage Reference with High PSRR and High Accuracy

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      Authors: Arvind Thakur, Rishikesh Pandey, Shireesh Kumar Rai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85[math]mV with a temperature coefficient of 29.5[math]ppm/∘C for the temperatures ranging from [math]C to 125∘C at a supply voltage of 0.8[math]V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8[math]V to 5[math]V at nominal temperature (27∘C). A PSRR of [math]91.69[math]dB is observed for the frequencies ranging from 1[math]Hz to 10[math]kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1[math]Hz and 10[math]kHz are obtained as 2.37[math][math]V/[math]Hz and 45.26[math]nV/[math]Hz, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-19T07:00:00Z
      DOI: 10.1142/S0218126622501766
       
  • A Low-Power and High-Stability 8T SRAM Cell with Diode-Connected
           Transistors

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      Authors: M. Elangovan, M. Muthukrishnan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([math][math]V and [math][math]V or 200[math]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([math][math]V and [math][math]V). A [math] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [math] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-16T07:00:00Z
      DOI: 10.1142/S0218126622501547
       
  • Deep [math]-Network with Reinforcement Learning for Fault Detection in
           Cyber-Physical Systems

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      Authors: J. Stanly Jayaprakash, M. Jasmine Pemeena Priyadarsini, B. D. Parameshachari, Hamid Reza Karimi, Sasikumar Gurumoorthy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cyber-Physical System (CPS) is an integration of physical components like actuators, sensors and various types of equipment with the Internet possessing computational ability for efficient communication. A Heterogeneous Independent Network (HINT) is a realistic model that is used for the analysis of inter-dependability between the power grid and communications network. In the traditional Deep [math]-Learning method, action needs to be stored in the [math] table for the prediction. In real case studies, many state and action values affect the performance of the model. Existing Deep [math]-Network (DQN) model generates all possible actions for the [math]-values and this involves the generation of excessive information that causes the model to overfit. In this research, the Neural Network is applied to estimate the state–action in the DQN and to store the particular state–action value instead of storing all the state–action values as followed in the traditional method. The HINT model provides realistic failure propagation in the network and its state–action value overfits the existing DQN method due to the presence of more information. The proposed DQN with reinforcement learning stores selected state–action values in the [math] tables and eliminates irrelevant information that helps to increase the accuracy and reduce the computational time. The DQN with reinforcement learning is applied to adaptively learn the system to select the optimal action in a continuous interaction with a stochastic environment. The proposed DQN model involves the application of reward function to store state–action value with higher probability based on prediction and eliminates other state–action values. Features such as intra-degree, inter-betweenness, substation-betweenness, relay-betweenness and feature vector are extracted and given as input to the DQN to characterize the critical nodes. The proposed DQN method is evaluated on the HINT network and synthetic network to analyze its efficiency in fault detection. The result shows that the HINT network has a lower prediction error compared to the existing Deep Neural Network (DNN) method. The proposed DQN and LSTM models have accuracies of 98% and 93% in fault prediction, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-16T07:00:00Z
      DOI: 10.1142/S0218126622501584
       
  • A UAV-Based Energy-Efficient and Real-Time Object Detection System with
           Multi-Source Image Fusion

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      Authors: Mei Chen, Xiaoyan Wang, Hong Wang, Shufang Zhao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Deep-learning-based object detection is widely used in unmanned aerial vehicle (UAV) systems. However, existing methods can only perform the object detection algorithm on visible images. In many scenarios, the infrared image performs better than the visible image because it can represent more invisible features. This paper proposes an object detection algorithm using image fusion to fully use the advantages of both visible light images and infrared images. Moreover, we optimize and re-design the standard object detection algorithm, YOLO V2, to improve its performance on embedded platforms. By evaluating the performance of the proposed method, we found that the recognition accuracy rate is 97.43%, while the recognition accuracy rate of the visible image is 91.09% and the recognition accuracy rate of the infrared image is 91.39%. The experimental results indicate that the proposed method can increase the recognition accuracy rate of the visible image by 6.34% and increase the recognition accuracy rate of the infrared image by 6.04%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-16T07:00:00Z
      DOI: 10.1142/S0218126622501663
       
  • An Efficient Design of Scalable Reversible Multiplier with Testability

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      Authors: Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new architecture of 4-bit reversible multiplier with scalability factor of order [math] is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-14T07:00:00Z
      DOI: 10.1142/S0218126622501791
       
  • Novel Pehlivan–Uyarŏglu Chaotic System Variants and their CFOA
           Based Realization

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      Authors: Kriti Suneja, Neeta Pandey, Rajeshwari Pandey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, four variants of Pehlivan–Uyarŏglu chaotic system (PUCS) have been proposed. The properties of the proposed PUCSs are examined through numerical simulations and the parameter values are obtained by observing the bifurcation diagrams for state variables. Further, the convergence/divergence of nearby orbits is investigated by noticing the evolution of Lyapunov exponents with time. It is found that the values of Lyapunov exponents are negative, zero and positive for all proposed variants thus confirming the chaoticity of the proposals. The strangeness of the proposed variants is also studied. The stability of PUCS and its proposed variants is examined using Jacobi stability analysis. A current feedback operational amplifier (CFOA) based circuit is put forward that can realize the existing PUCS and its proposed variants, by simply adjusting the component values. The proposed realization is compact (23% saving in overall component count) in comparison to its operational amplifier (OpAmp) based counterpart. The behavior of the proposed variants in time domain, frequency domain and phase space have been examined through simulations in LTspice design environment. Furthermore, the feasibility of the proposed variants is also discussed through presenting the electronic circuit implementation of two of the variants and the results obtained are in good agreement with the LTspice simulations. Monte Carlo (MC) simulations are also included to show the robustness of the proposed circuit against parameter variations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-10T08:00:00Z
      DOI: 10.1142/S0218126622501717
       
  • Sensor Array Optimization to Design and Develop an Electronic Nose System
           for the Detection of Water Stress in Khasi Mandarin Orange

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      Authors: Chayanika Sharma, Rajdeep Choudhury, Utpal Sarma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Drought stress is one of the most significant abiotic stresses, adversely affecting the economy by tumbling or even eliminating agricultural productivity, development, and yield. Adverse effects of water scarcity can be reduced if certain precautionary actions could be taken in advance. Therefore, monitoring and early detection of the drought can be helpful for preparing a well-developed response plan. In response to the stresses, an intricate response system of the plants is involved which emits a range of Volatile Organic Compounds (VOCs) from different parts, such as flowers, leaves, roots and stems. These VOCs can be used as fingerprints for categorizing stressed and nonstressed plants. This paper addresses the optimization of an array of gas sensors used in an in-situ stress diagnosis system, and the data obtained after optimization have been used for the detection of induced stresses in plants by recording the VOCs emitted by the plants. The flow characteristics of the gas chamber were modeled using the Finite Element method before fabrication. The temperature modulation of the gas sensors used in the designed electronic nose system was accomplished. The optimization of the sensor array was performed using the radar plot and Wilks’ Lambda technique. The optimum operating temperatures for each gas sensor were selected using a radar plot. Furthermore, the number of the sensors in the sensor array was reduced by choosing the sensors having higher discriminant ability using the Wilks’ Lambda optimization technique. Twelve healthy Khasi Mandarin Orange saplings were considered for the investigation. Three different levels of water stresses are induced in the plants artificially for the experiments. The overall response and the optimized response of the developed electronic nose system are compared using Linear Discriminant Analysis (LDA) and bootstrap ensemble K-Nearest Neighbors (KNN) classifier. The Leaf Relative Water Content (LRWC) of the leaves is also measured concurrently to confirm the stress induction in the plants.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-10T08:00:00Z
      DOI: 10.1142/S0218126622501729
       
  • A Novel GA-BP Neural Network for Wireless Diagnosis of Rolling Bearing

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      Authors: Zhiliang Zhu, Xiaofeng Xu, Lujia Li, Yuxing Dai, Zhiqiang Meng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Rolling bearings are pivotal components in industrial rotating equipment and the issue of fault will occur inevitably due to long-term abrasion. This study proposes a novel GA-BP neural network (GA-BPNN) algorithm to improve the accuracy of fault diagnosis of industrial rolling bearings. The genetic algorithm (GA) is employed to optimize the structure, initial weight and threshold of BP neural network, which can improve the ability of diagnosis and reduce the time of network training. At first, the structure of network is determined so that the optimal parameters of GA can be given, then the population of GA will be encoded. At second, the individual fitness function is calculated based on the test error norm of the BP neural network, as a criterion for distinguishing the individual from individual. The optimal weight and threshold are obtained by means of the corresponding selection, cross and variation, etc. Finally, the simulation experiment is carried out in Matlab and massive vibration experimental data of industrial rolling bearing are utilized. To verify the ability of the proposed novel GA-BPNN, compared with BP neural network algorithm (BPNN), the convergence speed and accuracy of GA-BPNN are better. The results of experiment illustrate that the optimized GA-BPNN method can identify the fault-type quicker, and has higher feasibility, which can be used to assist diagnosis of industrial bearing and improve efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-10T08:00:00Z
      DOI: 10.1142/S0218126622501730
       
  • VC-YOLO: Towards Real-time Object Detection in Aerial Images

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      Authors: Bo Jiang, Ruokun Qu, Yandong Li, Chenglong Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Object detection for aerial images is a crucial and challenging task in the field of computer vision. Previous CNN-based methods face problems related to extreme variation of object scales and the complex background in aerial images, which vary significantly from natural scenes. On the other hand, a great many of existing detectors highly rely on computational performance and cannot handle real-time tasks. To address this problems, we propose a lightweight real-time object detection network which is named VC-YOLO. In the backbone part, we introduce a receptive field extended backbone with limited number of convolution layers to learn the features and context information of various objects. In the detection part, channel attention module and spatial attention module are used to generate discriminative feature representation. To make full use of semantic feature maps in backbone network, we improve the feature pyramid network (FPN) with more lateral connections to reuse the features in each convolution stage. We evaluate VC-YOLO on NWPU VHR-10 and VisDrone benchmark datasets. Experimental results show that VC-YOLO achieves superior detection accuracy with high efficiency compared with the existing methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-07T08:00:00Z
      DOI: 10.1142/S021812662250147X
       
  • Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT

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      Authors: Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, Pseudo-Boolean Satisfiability (PB-SAT)-based congestion reduction and overflow minimization techniques are introduced for constructing congestion-aware rectilinear Steiner trees for global routing in IC design. Since congestion in different routing channels is a big issue in routing nets, various congestion minimization approaches have been proposed by many researchers. However, the increasing complexity of integrated circuits and the reduction of their size make the congestion problem more complicated. The proposed method can produce a congestion-free routing solution by generating a suitable rectilinear Steiner tree for circuit nets. To reduce the complexity of the problem, the nets are solved individually using a Minimum Bounding Box (MBB)-based heuristic technique. The algorithm is validated by utilizing the well-known ISPD 98 global routing benchmarks. Experimental results prove that the methodology is capable of routing most of the nets within the given routing capacity satisfying all the routing parameters. The results also show that the algorithm can produce congestion-aware Steiner trees efficiently within a nominal time-bound.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-05T08:00:00Z
      DOI: 10.1142/S0218126622501651
       
  • Global Fixed-Priority Scheduling for Parallel Real-Time Tasks with
           Constrained Parallelism

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      Authors: Lei Qiao, Maolin Yang, Zewei Chen, Yong Liao, Hang Lei, Nan Sang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of parallel programming techniques and the widespread use of multiprocessors, scheduling and analysis techniques supporting parallel real-time tasks become a critical topic for multiprocessor real-time systems. Global scheduling that allows the vertices of a parallel task to execute on any processor is a promising scheduling approach with guaranteed theoretical bounds and wide use in practice. However, the complex internal structure of parallel tasks leads to extensive inner- and inter-task interference, which leads to significant pessimism in the worst-case timing analysis. In this paper, a global fixed-priority (G-FP) scheduling with constrained parallelism for parallel real-time tasks based on the sporadic directed acyclic graph (DAG) model is proposed. Each DAG task is assigned a parallel threshold, such that the number of processors occupied by the task is limited to the parallel threshold of the task at a time. We propose a heuristic algorithm to set the parallel threshold and present a response-time analysis (RTA) to exploit the feature of the constrained parallel scheduling. Experiments with randomly generated tasks show that the proposed approach improves the schedulability upon G-FP and federated scheduling in terms of acceptance ratio.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-03T08:00:00Z
      DOI: 10.1142/S021812662250150X
       
  • A Comprehensive Review on Automatic Mobile Robots: Applications,
           Perception, Communication and Control

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      Authors: Nian Ding, Chunrong Peng, Min Lin, Celimuge Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent years, automatic mobile robots (AMRs) have been widely concerned in various fields, such as material handling, unmanned aerial vehicle (UAV) cruise, automatic factories and so forth. Compared with traditional robots, an AMR system brings several challenges such as adaptation to the environment, stable communication and robust control. For example, in a complex environment, AMR has to observe the surrounding environment in real time to avoid obstacles, and track the target in real time to change its trajectory until the task is completed, based on an efficient integration of the perception, communication and control. AMR systems require support from various technologies including real-time positioning and navigation, trajectory planning, target tracking, multi-agent systems, robot monitoring and so forth. In order to enable more enhanced applications of AMRs, the geometric adaptability, design characteristics, mobility, flexibility, obstacle avoidance and fault-tolerant control should be further discussed. This paper provides a comprehensive elaboration on the four aspects of AMR systems, namely AMR applications, perception technologies, robot communications and control mechanisms. Future research directions are also pointed out.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-03T08:00:00Z
      DOI: 10.1142/S0218126622501535
       
  • An Ultra-Fast Authenticated Encryption Scheme with Associated Data Using
           AES-OTR

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      Authors: Cuauhtemoc Mancillas-López, Brisbane Ovilla-Martínez
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Applications relying on the Ethernet IEEE 802.3ba and IEEE802.3b standards require secure data encryption and authentication at extremely high speeds (at least 100 Gbit/s). The Galois/Counter Mode (GCM) is currently considered the de facto standard for hardware high-speed authenticated encryption, although other algorithms have been proposed in the literature such as the Offset Codebook Mode (OCB). The challenge in terms of providing security for high-speed applications is to achieve implementations that explore the parallelism of these algorithms; however, this translates into area cost. In this work, we propose an alternative to GCM and OCB. We show that a combination of the Offset Two-Round authenticated-encryption scheme with the AES block cipher (known as AES-OTR) is exceptionally well suited for exploiting fine-grained parallelism, and can therefore be used to achieve ultra-high-speed data encryption rates. The experiments reported in this paper show that our pipeline-parallel implementation of AES-OTR outperforms the GCM and OCB schemes in terms of throughput per area while using almost half of the logic resources. Our implementation used a Stratix 4 FPGA device as well as several devices from the Virtex family. Implementations of AES-OTR on Stratix 4 used 11kALMs and achieved a throughput of 143.65 Gbit/s. On the Virtex Ultrascale, our design used 31,859 LUTs with a throughput of 204.92 Gbit/s.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-03T08:00:00Z
      DOI: 10.1142/S0218126622501675
       
  • A Hybrid Method for Equivalence Checking Between System Level and RTL

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      Authors: Jian Hu, Minhui Hu, Kuang Zhao, Yun Kang, Haitao Yang, Jie Cheng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Deep State Sequence-based (DSS) equivalence checking and path-based equivalence checking have been successfully applied for verification of digital designs between System Level Model (SLM) and Register Transfer Level (RTL). The DSS-based equivalence checking method can validate designs without mapping information, but the query size for each DSS is large compared with path-based verification. The query size for path-based methods is small, but the number of comparisons is large. In this work, we combine the advantages of DSS-based methods and path-based methods. We use DSS-based methods to find the corresponding paths and use cut-points like in path-based methods to split the DSS to reduce the query size. Finite State Machine with Datapath (FSMD) is used to represent the SLM and RTL models. Experimental results demonstrate that our method can effectively validate the designs and reduce the query size for DSS-based equivalence checking method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-03T08:00:00Z
      DOI: 10.1142/S0218126622501687
       
  • Calibration of Mismatches in Time-Interleaved ADCs Using Teacher
           Learner-Based Optimization Algorithm

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      Authors: M. V. N. Chakravarthi, B. Chandramohan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Sampling a signal at elevated sampling rates can be easily achieved by using time-interleaved analog-to-digital converters (TIADCs). TIADCs have more than one ADC in parallel. Each ADC samples the signal with a time gap of one sampling period and hence known as TIADC. The samples from all these ADCs are combined to reconstruct the signal. But the disadvantage of TIADCs is that they have mismatches like sampling time, gain and phase offset. The proposed work focuses on estimation and correction of these mismatches. For estimation of mismatches, teacher learner-based optimization (TLBO) algorithm was used and the estimated mismatches were used for correction by applying suitable operations. The proposed algorithm was applied for four-channel TIADCs. For estimation, a pilot signal is used which in this case is a monotonic sinusoidal signal. The estimation of mismatches was accurate and the correction was implemented for TIADCs with a sinusoidal input signal and the enhancement in signal quality was evaluated by finding signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). There is a significant enhancement in SNR and SNDR. The average enhancements in SNR and SNDR are 50 and 46[math]dB, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-03-02T08:00:00Z
      DOI: 10.1142/S0218126622501638
       
  • Gain and Bandwidth Programmable Fourth-Order Multiple Feedback Butterworth
           Low-Pass Filter for C–V2X Applications

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      Authors: Furkan Barin, Ertan Zencir
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A gain and bandwidth tunable active-RC multiple-feedback (MFB) fourth-order low-pass filter is presented, which exhibits four different bandwidths of 10, 20, 30 and 40[math]MHz and four different gain settings of 0, 4, 8 and 12[math]dB to meet the requirements of the cellular vehicle-to-everything (C-V2X) standards. The filter uses the cascade of two biquad MFB cells. Gain and bandwidth programmability is achieved by using programmable capacitor and resistor arrays. A logic block is implemented in the filter to adjust the gain transfer function for every tuning option. Also, two-stage miller op-amp topology is chosen to implement biquad MFB cells for minimum complexity and maximum efficiency in low voltage operation. The filter is designed in 65-nm CMOS technology and occupies a 0.181[math]mm2 area and it totally consumes 13.41[math]mW from the 1.2[math]V supply voltage. To the best of the author’s knowledge, this work is the first CMOS baseband filter design that includes both gain and bandwidth programmability implemented for C-V2X applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-28T08:00:00Z
      DOI: 10.1142/S021812662250164X
       
  • Big Educational Data Analytics, Prediction and Recommendation: A Survey

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      Authors: Xuegeng Sun, Yuan Fu, Weiyi Zheng, Yanxia Huang, Yuqi Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The development of mobile Internet, Internet of Things, and cloud computing has contributed to the unprecedented growth of information data. Big data plays a very important role in education. Currently, the literature review and in-depth research on big educational data are not very extensive, mainly involved in two fields: education mining and learning analysis. For a perfect research about education big data, this paper comprehensively reviewed three major aspects (Predictive Analytics, Learning Analytics, and Recommendation Systems) of educational data analytics for an intensive investigation and analysis: (1) Predictive Analytics: It predicts students’ learning performance by tracking students’ learning information and then analyzes students’ learning competence to build an academic early warning system; teachers can be allowed to intervene in students in time and adopts different teaching ways for different students. Therefore, both students’ learning and ability can be individualized and improved; (2) Learning Analytics: This part can identify the learners’ behavior patterns and obtain more implicit learner characteristics by studying the hidden meaning behind learning behaviors and strategies; (3) Recommendation Systems: It can match the needs of learners and recommend appropriate learning resources through different methods. All the above proved that the application of big data technology in education provides powerful data support for the development of education.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-25T08:00:00Z
      DOI: 10.1142/S0218126622300070
       
  • Thwarting Cache Side Channel Attacks with Encryption Address-Based Set
           Balance Cache

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      Authors: Chong Wang, Shuai Wei, Ke Song, Fan Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The deterministic memory-to-cache mapping used by cache side channel attack causes the leakage of sensitive information such as secret keys, which seriously threatens user security and highlights the need to defend against this kind of attack. Recent table-based secure cache design requires more space to store the entry while a purely encryption-based design needs complex encryption units to ensure robustness. What is more, the newer attack algorithm enabling faster eviction set discovery may still break such defenses. Even though increasing the association of cache can be a potential solution, it introduces too much redundancy cache access and storage overhead. In this paper, we eliminate this problem. We present Encryption address-based Set Balance Cache (ESBC), a novel cache design to mitigate cache-based side channel attack. ESBC encrypts an address into two-level sets and displaces the data from a primary set into the secondary set when the primary set is full. The two-level mapping structure increases the complexity for attackers to build eviction sets, which is a vital step for the conflict-based attack. Furthermore, we adopt two different optimized variants from a temporal perspective, ESBC with remapping (ESBCR), which serves dynamic-remapping, and spatial perspective, ESBC with multi-mapping (ESBCM), which performs multi-mapping to improve the robustness. Our security analysis reveals that these designs can confuse the exploitation of conflicting addresses. Simulation-based evaluation on SPEC2017 shows 0.24% instruction per cycle (IPC) degradation for ESBCR with 1% remap rate. While the reduction of ESBCM that has five potential secondary sets is 0.69%. What is exciting is that both miss per kilo instructions (MPKI) and miss rates are even reduced because of the efficient cache usage. The storage overhead of these two variants is only 0.87%. By comparing the two schemes, we can observe that though ESBCR brings less performance overhead, the ESBCM has better scalability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-25T08:00:00Z
      DOI: 10.1142/S0218126622501626
       
  • Power and Delay Efficient Haar Wavelet Transform for Image Processing
           Application

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      Authors: Gundugonti Kishore Kumar, Mahammad Firose Shaik, Vikram Kulkarni, Rambabu Busi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication [math] is implemented with [math] multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A [math] multiplier with 4:2 compressor technique is used to improve energy and delay. Compared to the previous architectures, the proposed architecture gives reduction in area, power, and delay. The proposed Haar wavelet architecture is implemented in gate-level Verilog HDL and synthesized with UMC 90-nm technology using Cadence RC compiler. When compared to the existing designs, the proposed architecture Haar DWT architecture synthesis results show reduction in latency of 32.32% and 31.46% of circuit area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-23T08:00:00Z
      DOI: 10.1142/S0218126622200018
       
  • Frequent Itemset Generation Using Association Rule Mining Based on Hybrid
           Neural Network Based Billiard Inspired Optimization

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      Authors: N. Lakshmi, M. Krishnamurthy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The concept based on data mining has drawn considerable attention from various database professionals and research scholars. The progression of computer-based advancements, namely database management and data storage has facilitated the storage of large data and the data mining approaches are employed to gain valuable information from huge databases. Recently, several techniques to association rule mining (ARM) and frequent itemset mining (FIM) have been established; yet the efficiency based on execution time and scalability continues to be seen as a significant limitation that results in poor solution quality. Therefore, it is necessary to enhance the consistency that signifies the total number of frequently discovered frequent itemsets. This paper proposes three different phases namely the pre-processing phase, FIM phase and ARM phase. In the first pre-processing phase, the Twitter databases are pre-processed and converted into a suitable format for FIM. Here, the tweets are converted into related feature sets and items. In the second FIM phase, an improved Apriori algorithm is 1utilized in mining and extracting the frequent Then in the final phase, an adaptive billiard inspired optimization (ABIO) algorithm which is the integration of neural network (NN) optimization algorithm and billiard inspired optimization (BIO) algorithm is proposed for the optimal generation of association rules with minimum support and confidence from the huge itemsets. Finally, the recent tweets based on covidvaccine, BTSlivestreaming, KFC, McDonald’s as well as lockdown achieved using the hashtag is evaluated for various performance measures, like precision, recall, [math]-measure, execution time and memory utilization. Also, comparative analyses are performed to evaluate the efficiency of the proposed technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-21T08:00:00Z
      DOI: 10.1142/S0218126622501389
       
  • Hardware Fuzzy Scheduler for Real-Time Independent Tasks

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      Authors: Khaled Slimani, Rebiha Hadaoui, Mustapha Lalam
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Several scheduling algorithms that have been proposed for Real-Time Operating System (RTOS) are supposed to be optimal. However, optimal scheduling is only theoretical due to the possibility of system overload where it cannot meet the deadlines of tasks. Besides, these algorithms are implemented in the RTOS, which generates additional overheads that can lead to the “nonscheduling” of certain independent tasks. In this paper, we propose an original solution for nonschedulable independent tasks in embedded systems. This solution, named Hybrid Fuzzy Earliest Deadline First Scheduling algorithm (HFEDFS), is based on the Earliest Deadline First algorithm (EDF) and Fuzzy Logic. It is characterized by a rejection policy and a rescheduling mechanism. The experimental results show that our proposed algorithm improves the system’s performance. To reduce extra overheads of RTOS, this algorithm is implemented on a Field-Programmable Gate Array (FPGA) circuit (Xilinx Virtex-5 LX50T-1156 board from DIGILENT).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-21T08:00:00Z
      DOI: 10.1142/S0218126622501559
       
  • Locality-Sensitive Hashing-based Link Prediction Process on Smart Campus
           Education or Online Social Platform

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      Authors: Hanwen Liu, Shunmei Meng, Jun Hou, Shuo Wang, Qianmu Li, Chanying Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the development of the Internet, smart campus education and online social platforms have become the mainstream of establishing social relationships. Although many users communicate by social networks, the social networks are caught in the problem of relationship sparsity, which severely impedes users’ communication space. More fatally, in the course of building social relationships, the disclosure of sensitive information will cause users’ privacy vulnerable to be compromised by attackers. Therefore, this paper proposes a potential social relationships prediction approach based on locality-sensitive hashing (LSH) to address the above issues. Specifically, the LSH clusters similar users into the same bucket, and the fuzzy computing method is developed to predict the types of social relationships among these similar users. To further alleviate the relationship sparsity problem, the existing social network structure is utilized to predict users’ social relationships and relationship types. Furthermore, the rationality of prediction results is verified by using the social balance theory (SBT). Finally, massive experiments are executed on Epinions, and the experimental results further confirmed the efficiency and accuracy of our methodology in terms of link prediction while guaranteeing privacy-preservation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-21T08:00:00Z
      DOI: 10.1142/S0218126622501602
       
  • Self-Supervised Multi-Label Transformation Prediction for Video
           Representation Learning

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      Authors: Maregu Assefa, Wei Jiang, Getinet Yilma, Bulbula Kumeda, Melese Ayalew, Mohammed Seid
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Self-supervised learning is a promising paradigm to address the problem of manual-annotation through effectively leveraging unlabeled videos. By solving self-supervised pretext tasks, powerful video representations can be discovered automatically. However, recent pretext tasks for videos rely on utilizing the temporal properties of videos, ignoring the crucial supervisory signals from the spatial subspace of videos. Therefore, we present a new self-supervised pretext task called Multi-Label Transformation Prediction (MLTP) to sufficiently utilize the spatiotemporal information in videos. In MLTP, all videos are jointly transformed by a set of geometric and color-space transformations, such as rotation, cropping, and color-channel split. We formulate the pretext as a multi-label prediction task. The 3D-CNN is trained to predict a composition of underlying transformations as multiple outputs. Thereby, transformation invariant video features can be learned in a self-supervised manner. Experimental results verify that 3D-CNNs pre-trained using MLTP yield video representations with improved generalization performance for action recognition downstream tasks on UCF101 ([math]) and HMDB51 ([math]) datasets.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-18T08:00:00Z
      DOI: 10.1142/S0218126622501596
       
  • Conformance Testing for Finite State Machines Guided by Deep Neural
           Network

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      Authors: Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a Finite State Machine (FSM) testing technique based on deep neural network (DNN). This technique verifies the correctness of an implementation FSM-B of a specification FSM-A. Using the back-propagation algorithm, a deep neural network is trained with the input–output patterns for a given set of transition functions that specify an FSM. Initially, for FSM-A, the input patterns and the corresponding output patterns (I/O pairs) are generated. Then most of the patterns are used to train the DNN. Once the training is over, the DNN is validated with the remaining I/O pairs (around 20%). The model can be used for verifying the correctness of FSM-B after training and validation of the DNN. Some inputs are applied to FSM-B and the generated output patterns are compared with the predicted values of the proposed DNN. The difference of accuracy percentages between FSM-A and FSM-B is recorded and zero difference between them indicates the fault-free condition of the implementation FSM-B. To check the effectiveness of the scheme, the output- and state-type faults are injected to derive mutant FSMs. Experimental results performed on the MCNC FSM benchmarks prove the efficacy of the proposed method. Only a few numbers of tests are needed to detect the presence of anomaly, if any. Hence, the test time reduces significantly — resulting in an average test time reduction of 85.67% compared to the conventional techniques. To the best of our knowledge, for the first time a DNN-driven testing scheme is being proposed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-17T08:00:00Z
      DOI: 10.1142/S0218126622501560
       
  • A Security Multi-Dimensional Range Query Protocol Based on Left 0-1
           Encoding in Two-Tiered Wireless Sensor Networks

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      Authors: Yun Deng, Jinyu Chen, Yu Wang, Fanfan Shen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this research on range query technology for two-tiered wireless sensor networks, the existing researches still need improvement in privacy security and communication cost of the sensor node. In this paper, a security multi-dimensional range query protocol is proposed. The left 0-1 encoding mechanism (a new and optimized encoding mechanism), HMAC algorithm, and BASE64 encoding are employed to optimize the calculation of comparison factor. The encryption index chain is constructed by using AES algorithm to replace the long encryption constraint chain, so as to lower the energy consumption of computation and communication. The base station can verify the authenticity and integrity of query results on the basis of continuity of storage time and encryption index chain. The experiment has been conducted in the real systems. The protocol is compared and analyzed with the latest proposed Communication-Efficient Secure Range Queries (CSRQ). The results have shown that the proposed protocol can gain a better performance in terms of four aspects, i.e., the length of sensing data, the number of data collected in each cycle, the number of data dimensions and the number of sensor nodes in each unit. Meanwhile, compared with CSRQ, the communication cost of the proposed protocol is reduced by at least 10%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-17T08:00:00Z
      DOI: 10.1142/S0218126622501572
       
  • Timing-Oriented Task Offloading Algorithms for Internet-of-Vehicles

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      Authors: Yifan He, Jing Xu, Bo Zheng, Jianqiang Hu, Yong Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The emergence of computation intensive automotive applications poses significant challenges on computation capacity of automotive electronic systems, thus vehicular edge computing (VEC) is introduced as a new computing paradigm into the internet of vehicle (IoV) to improve its data processing capability. However, as the computation capacity is limited in VEC servers, efficient task offloading algorithms need to be proposed. This paper first proposes a multi-task offloading model and gives the related task response time analysis method, and then, both a mixed-integer linear programming (MILP)-based algorithm and a simulated annealing-based heuristic algorithm are proposed to minimize the task response time. By comparing with a baseline algorithm, the MILP-based offloading algorithm can reduce the average task response time by 91.45%, and the heuristic offloading algorithm can reduce the average task response time by 70%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-16T08:00:00Z
      DOI: 10.1142/S0218126622501511
       
  • Level-Crossing Sampling with Multiple Temporal Resolutions for Speech
           Signals

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      Authors: B. Premanand, V. S. Sheeba
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Level-crossing sampling (LCS) is an alternative to the uniform sampling method and is suitable for sparse and bursty signals. LCS, which is adaptive to amplitude variations of the signals, mainly focuses on reducing the total number of samples. Presently, speech signals are sampled with LCS methods that have a constant temporal resolution, and they require time-to-digital converters (TDC) with a wide dynamic range. A long sequence of overflow counts of the TDC counter may be generated during silence regions if the dynamic range is reduced. This paper proposes level-crossing samplers with multiple temporal resolutions for speech signals. Frequency scaling is applied to standard LCS, adaptive LCS and peak sampling. During the silence region, the frequency of the TDC clock is scaled down, which enables the representation of longer intervals with smaller words. The number of bits per sample and hence the total number of samples generated are decreased due to the reduction in the dynamic range of the TDC. Simulation results indicate that the proposed method outperforms the conventional level-crossing samplers, which do not employ frequency scaling. In addition to a significant reduction in data size, this method can also be used for real-time automatic detection of silence regions in a speech signal.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-11T08:00:00Z
      DOI: 10.1142/S0218126622501493
       
  • Keyword-Covered Group Enlargement Community Search

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      Authors: Xiaoxu Song, Zhigao Zhang, Fanfei Song, Bin Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The goal of community search across attributed graphs is to locate the community that takes both attribute cohensiveness and constrained structure into account. The keyword closeness of subgraph is usually measured by similarity distance. However, existing works focus on how to find a community that has most relevant to the keywords of the query vertex through the similarity score, whereas we pay more attention to a community that can jointly cover keywords and find subgraph with the maximum core. To address this problem, we propose a novel query keyword-covered group enlargement community search [math]. Given an initial subgraph and a set of query keywords, the [math] search aims to find the community which satisfies the following conditions: (1) it jointly covers all query keywords; (2) it is a subgraph with the maximum core; (3) it is added the minimum vertex set that meets the conditions (1) and (2). We design a baseline enumerateKGEC algorithm ([math]), which enumerates all the vertex combinations that cover the remaining query keywords. To further accelerate the search speed, we propose two heuristic algorithms candidate set-based algorithm [math] and candidate set and keyword combination algorithm [math], which can effectively speed up the search and find a feasible solution. Finally, we evaluate the performance of our algorithms on two real datasets and show effectiveness and efficiency of our algorithms for [math] problem.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-10T08:00:00Z
      DOI: 10.1142/S0218126622501523
       
  • Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full
           Adder Based on LIM Structure

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      Authors: Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-02-04T08:00:00Z
      DOI: 10.1142/S0218126622501468
       
  • A Low Power, Low Phase Noise, 11.8 GHz LC-VCO in 65 nm CMOS for 5G NR
           Based C-V2X Applications

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      Authors: Toprak Kayanselçuk, Ertan Zencir
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An 11.8-GHz low-power, low phase noise, 65-nm CMOS LC-VCO for V2X communication standards is presented in this work. To achieve low-phase noise performance to fulfill the 5G NR C-V2X standards, several adjustments are made to the conventional LC-VCO topologies. These adjustments are briefly explained in this work. Presented VCO consumes 3.046[math]mA current from a 1.2-V power supply. It has [math]116.13[math]dBc/Hz phase noise at 1[math]MHz offset and tuning range between 11.64[math]GHz and 11.94[math]GHz. A frequency divider circuit is designed and implemented to the presented VCO to satisfy the frequency spectrum of V2X radio access technologies. To the best of authors’ knowledge, this work is the first VCO implemented at 11.8 GHz in a 65-nm CMOS process with the reported phase noise number for 5G NR C-V2X applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-31T08:00:00Z
      DOI: 10.1142/S0218126622501407
       
  • Multi-Scale Correlation for Deep Homography Estimation

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      Authors: Nan Ke, Zhaowei Shang, Lingzhi Zhao, Yingxin Wang, Mingling Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a novel multi-scale correlation network (MSCNet) for homography estimation from coarse to fine. First, we extract multi-scale features through a siamese network to generate global and local correlations from feature maps of different scales. Second, we use a group dilated deconvolution block to capture global mapping by increasing the receptive fields in terms of different levels. Third, we employ the channel and spatial attention mechanism to achieve local refinement for small displacements. Finally, we adopt a knowledge distillation strategy to lightweight our model while maintaining relatively high estimation performance. Experimental results on Microsoft Common Objects in Context (MSCOCO) dataset show that our proposed MSCNet outperforms the state-of-the-art approaches in terms of accuracy and parameter count.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-31T08:00:00Z
      DOI: 10.1142/S0218126622501456
       
  • Architectural Design of a Fast Search Algorithm and Implementation to
           Intra-Mode Decision Block of Still Image Coding

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      Authors: Serap Cekli, Ali Akman
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As a requirement of many modern image compression standards faced today, a computational complexity is observed due to the best mode selection in the intra-prediction stage. This computational complexity is tried to be reduced by various techniques without affecting the performance criteria of the image. In this study, a fast search algorithm, which simplifies the mode selection process of the intra-prediction algorithm and provides calculation with less number of modes is proposed. The hardware architecture of this proposed algorithm is implemented for realization. There are two main sections of the intra-prediction algorithm in image compression, namely the image prediction process and the mode selection process. In this study, main objective is to reduce the process time of the mode selection and the simplification of the hardware design. Sum of absolute difference (SAD) is a frequently used criterion to simplify hardware design. The algorithm searches for the most suitable mode in a single step, where the decision is based on the SAD criterion preferred for the simplicity. The proposed algorithm and related hardware architecture is tested by using various experiments. The number of the modes calculated is reduced effectively, while the process is kept within the acceptable limits in terms of peak signal to noise ratio (PSNR) and compression rate (CR) performance criteria. Therefore, the number of clock cycles observed is considerably reduced. The designed architecture is synthesized for the field programmable gate arrays (FPGA) board and the obtained results are given. In addition, these results are compared with the HM reference software where the corresponding results are in accordance with the reference software.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-31T08:00:00Z
      DOI: 10.1142/S0218126622501481
       
  • Efficient and Scalable Hardware Implementation of Montgomery Modular
           Multiplication

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      Authors: M. Issad, M. Anane, B. Boudraa, A. M. Bellemou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modular multiplication (MM) is an important arithmetic operation in public key cryptography (PKC). In this paper, we present the FPGA implementation of the MM using Montgomery MM (MMM) algorithm. The execution performances of this operation depend on the radix-[math] and the operands length. In fact, when increasing the radix-[math], the MMM algorithm requires multiplications of digit by operand. On the other hand, when a long modulus is used, the hardware implementation of the MMM needs a large area. Our objective in this work is to realize a scalable architecture able to support any operands length. In order to achieve a best trade-off between computation throughput and hardware resources, our implementation approach is based on the execution of the basic arithmetic operations in serial way. In addition, efficient parallel and pipelined strategies are realized at low-level abstraction for the optimization of the execution time. The implementations results on Virtex-7 circuit show that a 1024-bit MMM runs in 2.09[math][math]s and consumes 581 slices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-24T08:00:00Z
      DOI: 10.1142/S0218126622501377
       
  • Improved FunkSVD Algorithm based on RMSProp

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      Authors: Xiaochen Yue, Qicheng Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To solve the problem of low accuracy in the traditional FunkSVD recommendation algorithm, an improved FunkSVD algorithm (RM-FS) is proposed. RM-FS is an improvement of the traditional FunkSVD algorithm, using RMSProp, a deep learning optimization algorithm. The RM-FS algorithm can not only solve the problem of reduced accuracy of the traditional FunkSVD algorithm because of iterative oscillations but also alleviate the impact of data sparseness on the accuracy of the algorithm, achieving the effect of improving the accuracy of the traditional algorithm. The experimental results show that the RM-FS algorithm proposed in this paper effectively improves the accuracy of the recommendation algorithm, which is better than the traditional FunkSVD recommendation algorithm and other improved FunkSVD algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-24T08:00:00Z
      DOI: 10.1142/S0218126622501390
       
  • A 7–9 GHz I/Q Up-Conversion Mixer Employing a Linear Voltage-to-Current
           Converting Baseband Input Stage for 5G New Radio Cellular Applications

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      Authors: Beomyu Park, Donggu Lee, Jeongwoo Lee, Junghwan Han, Kuduck Kwon
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work presents a 7–9[math]GHz in-phase/quadrature (I/Q) direct up-conversion mixer employing a linear voltage-to-current converting baseband input stage for 5G new radio frequency range 2 cellular applications. The proposed baseband stage improves both the large-signal handling capability and small-signal linearity at the input stage of the mixer. The designed double-balanced I/Q up-conversion mixer, which is based on Gilbert-cell mixer, consists of a voltage-to-current converting input stage, switching stages, and an RLC tank. Simulated in a 40-nm CMOS process, the up-conversion mixer achieves a conversion gain of 5[math]dB, input-referred third-order intercept point of 9.6[math]dBm, and input 1-dB gain compression point of –0.8[math]dBm. It draws a DC bias current of 15.8[math]mA from a nominal supply voltage of 1.1[math]V, and the active area is 0.129[math]mm2.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-24T08:00:00Z
      DOI: 10.1142/S0218126622501432
       
  • Research on Obstacle Avoidance Method of Robot Based on Region Location

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      Authors: Yuwan Gu, Qiuyuan Yang, Zhitao Zhu, Shoukun Xu, Hui Qian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In order to solve the problem of environment generalization in continuous state space, an obstacle avoidance method based on region location is proposed. The method is divided into three steps: (1) Using Region Proposal Network (RPN) to localize the obstacle area; (2). The environment map is established by the regional position mapping relation; and (3). The Deep Q-Learning Network (DQN) is used to realize collision detection of the robot, then pixel collision detection module is introduced and finally the pixel collision simulation distance sensor is combined to obtain the distance between the robot and obstacle and whether the collision or not. In this paper, the experiments were carried out in static obstacle environment and in dynamic and static obstacle environment for robot obstacle avoidance tasks. Experimental results show that the problem of environment generalization can be effectively solved by introducing pixel collision detection in the process of robot obstacle avoidance, and the network model trained in a dynamic environment has some generalization ability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-24T08:00:00Z
      DOI: 10.1142/S0218126622501444
       
  • Analysis on the Method of Enhanced Transient State of DLDO

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      Authors: Mingyuan Ren, Tianhang Gao, Changchun Dong, Tian Han, Zhu Zhang, Xiaolin Jiang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As an important unit of power management system, traditional analog low-dropout regulator (ALDO) is widely used in System-on-Chip (SoC) design to provide stable and pure power for each sub-circuit block. However, in ultra-low-power design applications, low quiescent current greatly affects the loop gain of ALDO. Digital low-dropout regulator (DLDO) has good low-voltage working ability, process scalability and diversified control schemes, which is more suitable for low-power SoC design. However, a large number of digital circuits with fast switching devices will produce large load current changes, so DLDO needs fast transient response speed to adjust load changes. In recent years, DLDO can be divided into synchronous DLDO and asynchronous DLDO according to different control methods. Among them, the design structure of synchronous DLDO is relatively simple. It depends on an independent global clock, and there is a tradeoff between speed, accuracy and power consumption. When the clock frequency increases, the system needs fast transient response, but the power consumption will increase proportionally, and the current efficiency and loop stability will decrease. Using large output capacitor to deal with load transient is not conducive to improve chip integration. Although asynchronous DLDO can improve the response speed based on the advantages of asynchronous control scheme, the stability of DLDO will face greater risks. Therefore, this paper will introduce several transient response enhancement technologies that do not sacrifice system power consumption, accuracy or stability. It includes adaptive frequency technology and fast response algorithm to improve the transient response speed of synchronous DLDO, event-driven solution and coarse and fine adjustment technology to improve the transient response speed of asynchronous DLDO. On this basis, a typical DLDO structure with excellent performance in the recent 10 years is given.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-21T08:00:00Z
      DOI: 10.1142/S0218126622300069
       
  • A Fully Integrated S-Band Phase-Array Receiver in 0.13 [math]m CMOS SOI

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      Authors: Yangyang Zhou, Hao Zhang, Lei Zhu, Yuan Zhao, Tian Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13[math][math]m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2[math]W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28[math]dB with an NF about 2.3[math]dB and an IP1 dB above [math]14[math]dBm. The state error of attenuator is less than [math][math]dB with step error less than [math][math]dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of [math][math]mm2. This receiver draws only 128[math]mA with a 3.3[math]V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2022-01-17T08:00:00Z
      DOI: 10.1142/S0218126622501419
       
 
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