 Subjects -> ELECTRONICS (Total: 207 journals)
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- JLPEA, Vol. 13, Pages 42: FTFNet: Multispectral Image Segmentation
Authors: Justin Edwards, Mohamed El-Sharkawy
First page: 42
Abstract: Semantic segmentation is a machine learning task that is seeing increased utilization in multiple fields, from medical imagery to land demarcation and autonomous vehicles. A real-time autonomous system must be lightweight while maintaining reasonable accuracy. This research focuses on leveraging the fusion of long-wave infrared (LWIR) imagery with visual spectrum imagery to fill in the inherent performance gaps when using visual imagery alone. This approach culminated in the Fast Thermal Fusion Network (FTFNet), which shows marked improvement over the baseline architecture of the Multispectral Fusion Network (MFNet) while maintaining a low footprint.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-06-30
DOI: 10.3390/jlpea13030042
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 43: An Extended Range Divider Technique for
Multi-Band PLL
Authors: Rizwan Shaik Peerla, Ashudeb Dutta, Bibhu Datta Sahoo
First page: 43
Abstract: This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional 2/3 divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The 2/3 divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625 μA when powered with a 1 V supply. A dual voltage controlled oscillator (VCO), L5/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-07-05
DOI: 10.3390/jlpea13030043
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 44: Electromigration-Aware Memory Hierarchy
Architecture
Authors: Freddy Gabbay, Avi Mendelson
First page: 44
Abstract: New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon area and power consumption, they also introduce new reliability challenges through the complex design rules they impose, creating a significant hurdle in the design process. In this paper, we focus on electromigration (EM), which is a crucial factor impacting IC reliability. EM refers to the degradation process of IC metal nets when used for both power supply and interconnecting signals. Typically, EM concerns have been addressed at the backend, circuit, and layout levels, where EM rules are enforced assuming extreme conditions to identify and resolve violations. This study presents new techniques that leverage architectural features to mitigate the effect of EM on the memory hierarchy of modern microprocessors. Architectural approaches can reduce the complexity of solving EM-related violations, and they can also complement and enhance common existing methods. In this study, we present a comprehensive simulation analysis that demonstrates how the proposed solution can significantly extend the lifetime of a microprocessor’s memory hierarchy with minimal overhead in terms of performance, power, and area while relaxing EM design efforts.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-07-11
DOI: 10.3390/jlpea13030044
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 45: BFT—Low-Latency Bit-Slice Design of
Discrete Fourier Transform
Authors: Cataldo Guaragnella, Agostino Giorgio, Maria Rizzi
First page: 45
Abstract: Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation of the discrete Fourier transform is proposed, based on a bit-slice approach and on the exploitation of the input sequence finite word length. Input samples of the sequence to be transformed are split into binary sequences and each one is Fourier transformed using only complex sums. An FPGA-based solution characterized by low latency and low power consumption is designed. Simulations have been carried out, first in the Matlab environment, then emulated in Quartus IDE with Intel. The hardware implementation of the conceived system and the test for the functional accuracy verification have been performed, adopting the DE2-115 development board from Terasic, which is equipped with the Cyclone IV EP4CE115F29C7 FPGA by Intel.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-07-18
DOI: 10.3390/jlpea13030045
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 46: Review of Orthogonal Frequency Division
Multiplexing-Based Modulation Techniques for Light Fidelity
Authors: Rahmayati Alindra, Purnomo Sidi Priambodo, Kalamullah Ramli
First page: 46
Abstract: Light Fidelity (LiFi) technology has gained attention and is growing rapidly today. Utilizing light as a propagation medium allows LiFi to promise a wider bandwidth than existing Wireless Fidelity (WiFi) technology and enables the implementation of cellular technology to improve bandwidth utilization. In addition, LiFi is very attractive because it can utilize lighting facilities consisting of light-emitting diodes (LEDs). A LiFi system that uses intensity modulation and direct detection requires the signal of orthogonal frequency division multiplexing (OFDM) to have a real and non-negative value; therefore, certain adjustments must be made. The proposed methods for generating unipolar signals vary from adding a direct current, clipping the signal, superposing several unipolar signals, and hybrid methods as in DC-biased optical (DCO)-OFDM, asymmetrically clipped optical (ACO)-OFDM, layered ACO (LACO)-OFDM, and asymmetrically clipped DC-biased optical (ADO)-OFDM, respectively. In this paper, we review and compare various modulation techniques to support the implementation of LiFi systems using commercial LEDs. The main objective is to obtain a modulation technique with good energy efficiency, efficient spectrum utilization, and low computational complexity so that it is easy for us to apply it in experiments on a laboratory scale.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-07-26
DOI: 10.3390/jlpea13030046
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 47: Programmable Energy-Efficient Analog Multilayer
Perceptron Architecture Suitable for Future Expansion to Hardware
Accelerators
Authors: Jeff Dix, Jeremy Holleman, Benjamin J. Blalock
First page: 47
Abstract: A programmable, energy-efficient analog hardware implementation of a multilayer perceptron (MLP) is presented featuring a highly programmable system that offers the user the capability to create an MLP neural network hardware design within the available framework. In addition to programmability, this implementation provides energy-efficient operation via analog/mixed-signal design. The configurable system is made up of 12 neurons and is fabricated in a standard 130 nm CMOS process occupying approximately 1 mm2 of on-chip area. The system architecture is analyzed in several different configurations with each achieving a power efficiency of greater than 1 tera-operations per watt. This work offers an energy-efficient and scalable alternative to digital configurable neural networks that can be built upon to create larger networks capable of standard machine learning applications, such as image and text classification. This research details a programmable hardware implementation of an MLP that achieves a peak power efficiency of 5.23 tera-operations per watt while consuming considerably less power than comparable digital and analog designs. This paper describes circuit elements that can readily be scaled up at the system level to create a larger neural network architecture capable of improved energy efficiency.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-07-31
DOI: 10.3390/jlpea13030047
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 48: TCI Tester: A Chip Tester for Inductive Coupling
Wireless Through-Chip Interface
Authors: Hideto Kayashima, Hideharu Amano
First page: 48
Abstract: The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-08-04
DOI: 10.3390/jlpea13030048
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 49: An Improved Lightweight Network Using Attentive
Feature Aggregation for Object Detection in Autonomous Driving
Authors: Priyank Kalgaonkar, Mohamed El-Sharkawy
First page: 49
Abstract: Object detection, a more advanced application of computer vision than image classification, utilizes deep neural networks to predict objects in an input image and determine their locations through bounding boxes. The field of artificial intelligence has increasingly focused on the demands of autonomous driving, which require both high accuracy and fast inference speeds. This research paper aims to address this demand by introducing an efficient lightweight network for object detection specifically designed for self-driving vehicles. The proposed network, named MobDet3, incorporates a modified MobileNetV3 as its backbone, leveraging its lightweight convolutional neural network algorithm to extract and aggregate image features. Furthermore, the network integrates altered techniques in computer vision and adjusts to the most recent iteration of the PyTorch framework. The MobDet3 network enhances not only object positioning ability but also the reusability of feature maps across different scales. Extensive evaluations were conducted to assess the effectiveness of the proposed network, utilizing an autonomous driving dataset, as well as large-scale everyday human and object datasets. These evaluations were performed on NXP BlueBox 2.0, an advanced edge development platform designed for autonomous vehicles. The results demonstrate that the proposed lightweight object detection network achieves a mean precision of up to 58.30% on the BDD100K dataset and a high inference speed of up to 88.92 frames per second on NXP BlueBox 2.0, making it well-suited for real-time object detection in autonomous driving applications.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-08-10
DOI: 10.3390/jlpea13030049
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 50: Address Obfuscation to Protect against Hardware
Trojans in Network-on-Chips
Authors: Thomas Mountford, Abhijitt Dhavlle, Andrew Tevebaugh, Naseef Mansoor, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
First page: 50
Abstract: In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-09-06
DOI: 10.3390/jlpea13030050
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 51: An Investigation of the Operating Principles and
Power Consumption of Digital-Based Analog Amplifiers
Authors: Anna Richelli, Paolo Faustini, Andrea Rosa, Luigi Colalongo
First page: 51
Abstract: Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-09-08
DOI: 10.3390/jlpea13030051
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 52: FFC-NMR Power Supply with Hybrid Control of the
Semiconductor Devices
Authors: António Roque, Duarte M. Sousa, Pedro J. Sebastião, Vítor Silva, Elmano Margato
First page: 52
Abstract: The performance of FFC-NMR power supplies is evaluated not only considering the technique requirements but also comparing efficiencies and power consumption. Since the characteristics of FFC-NMR power supplies depend on the power circuit topology and on the control solutions, the control design is a core aspect for the development of new FFC systems. A new hybrid solution is described that allows controlling the power of semiconductors by switches (ON/OFF mode) or as a linear device. The approach avoids over-design of the power supply and makes it possible to implement new low power solutions constituting a novel design by joining a continuous match between the ON/OFF mode and the linear control of the power semiconductor devices.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-09-19
DOI: 10.3390/jlpea13030052
Issue No: Vol. 13, No. 3 (2023)
- JLPEA, Vol. 13, Pages 23: A Ka-Band SiGe BiCMOS Quasi-F−1 Power
Amplifier Using a Parasitic Capacitance Cancellation Technique †
Authors: Vasileios Manouras, Ioannis Papananos
First page: 23
Abstract: This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simplified model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with fT/fmax=250/370 GHz and it is suitable for 5G applications. It achieves 33% peak power-added efficiency (PAE), 18.8 dBm saturation output power Psat, and 14.7 dB maximum large-signal power gain G at the operating frequency of 38 GHz. The PA’s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is 0.605×0.712 mm2 including all pads.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-24
DOI: 10.3390/jlpea13020023
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 24: A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with
Non-Tailed Differential Pair
Authors: Andrea Ballo, Alfio Dario Grasso, Salvatore Pennisi
First page: 24
Abstract: This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-28
DOI: 10.3390/jlpea13020024
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 25: First Review of Conductive Electrets for
Low-Power Electronics
Authors: D. D. L. Chung
First page: 25
Abstract: This is the first review of conductive electrets (unpoled carbons and metals), which provide a new avenue for low-power electronics. The electret provides low DC voltage (μV) while allowing low DC current (μA) to pass through. Ohm’s Law is obeyed. The voltage scales with the inter-electrode distance. Series connection of multiple electret components provides a series voltage that equals the sum of the voltages of the components if there is no bending at the connection between the components. Otherwise, the series voltage is below the sum. Bending within the component also diminishes the voltage because of the polarization continuity decrease. The electret originates from the interaction of a tiny fraction of the carriers with the atoms. This interaction results in the charge in the electret. Dividing the electret charge by the electret voltage V’ provides the electret-based capacitance C’, which is higher than the permittivity-based capacitance (conventional) by a large number of orders of magnitude. The C’ governs the electret energy (1/2 C’V’2) and electret discharge time constant (RC’, where R = resistance), as shown for metals. The discharge time is promoted by a larger inter-electrode distance. The electret discharges occur upon short-circuiting and charge back upon subsequent opencircuiting. The discharge or charge of the electret amounts to the discharge or charge of C’.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-06
DOI: 10.3390/jlpea13020025
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 26: Innovative Characterization and Comparative
Analysis of Water Level Sensors for Enhanced Early Detection and Warning
of Floods
Authors: Rula Tawalbeh, Feras Alasali, Zahra Ghanem, Mohammad Alghazzawi, Ahmad Abu-Raideh, William Holderbaum
First page: 26
Abstract: In considering projections that flooding will increase in the future years due to factors such as climate change and urbanization, the need for dependable and accurate water sensors systems is greater than ever. In this study, the performance of four different water level sensors, including ultrasonic, infrared (IR), and pressure sensors, is analyzed based on innovative characterization and comparative analysis, to determine whether or not these sensors have the ability to detect rising water levels and flash floods at an earlier stage under different conditions. During our exhaustive tests, we subjected the device to a variety of conditions, including clean and contaminated water, light and darkness, and an analogue connection to a display. When it came to monitoring water levels, the ultrasonic sensors stood out because of their remarkable precision and consistency. To address this issue, this study provides a novel and comparative examination of four water level sensors to determine which is the most effective and cost-effective in detecting floods and water level fluctuations. The IR sensor delivered accurate findings; however, it demonstrated some degree of variability throughout the course of the experiment. In addition, the results of our research show that the pressure sensor is a legitimate alternative to ultrasonic sensors. This presents a possibility that is more advantageous financially when it comes to the development of effective water level monitoring systems. The findings of this study are extremely helpful in improving the dependability and accuracy of flood detection systems and, eventually, in lessening the devastation caused by natural catastrophes.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-11
DOI: 10.3390/jlpea13020026
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 27: Buck-Boost Charge Pump Based DC-DC Converter
Authors: Evi Keramida, George Souliotis, Spyridon Vlassis, Fotis Plessas
First page: 27
Abstract: This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltage, respectively, compared to the input. To achieve each mode, only a switching of the input–output connections is needed without any other modification in the design of the DC-DC converter. The dual-mode configuration aims to merge two different functions into one circuit, minimizing the design time and the area the DC-DC converter occupies on the die. The proposed buck-boost CP has been designed using TSMC 65 nm complementary metal–oxide–semiconductor (CMOS) technology. The functional input voltage range of the CP in boost mode is 1.2 V to 1.8 V and the typical output voltage is 1.8 V. For the buck mode, the input voltage range is 3.2 V to 3.6 V and the output is 1.5 V. For both modes, the output can be easily modified to new values by changing the comparator configuration. Efficiency results are also provided for the two modes.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-21
DOI: 10.3390/jlpea13020027
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 28: Class AB Voltage Follower and Low-Voltage
Current Mirror with Very High Figures of Merit Based on the Flipped
Voltage Follower
Authors: Jaime Ramírez-Angulo, Anindita Paul, Manaswini Gangineni, Jose Maria Hinojo-Montero, Jesús Huerta-Chua
First page: 28
Abstract: The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180nm CMOS (Complementary Metal Oxide Semiconductor) technology.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-24
DOI: 10.3390/jlpea13020028
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 29: Battery Parameter Analysis through
Electrochemical Impedance Spectroscopy at Different State of Charge Levels
Authors: Yuchao Wu, Sneha Sundaresan, Balakumar Balasingam
First page: 29
Abstract: This paper presents a systematic approach to extract electrical equivalent circuit model (ECM) parameters of the Li-ion battery (LIB) based on electrochemical impedance spectroscopy (EIS). Particularly, the proposed approach is suitable to practical applications where the measurement noise can be significant, resulting in a low signal-to-noise ratio. Given the EIS measurements, the proposed approach can be used to obtain the ECM parameters of a battery. Then, a time domain approach is employed to validate the accuracy of estimated ECM parameters. In order to investigate whether the ECM parameters vary as the battery’s state of charge (SOC) changes, the EIS experiment was repeated at nine different SOCs. The experimental results show that the proposed approach is consistent in estimating the ECM parameters. It is found that the battery parameters, such as internal resistance, capacitance and inductance, remain the same for practical SOC ranges starting from 20% until 90%. The ECM parameters saw a significant change at low SOC levels. Furthermore, the experimental data show that the resistive components estimated in the frequency domain are very close to the internal resistance estimated in the time domain. The proposed approach was applied to eight different battery cells consisting of two different manufacturers and produced consistent results.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-26
DOI: 10.3390/jlpea13020029
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 30: Energy-Efficient Audio Processing at the Edge
for Biologging Applications
Authors: Jonathan Miquel, Laurent Latorre, Simon Chamaillé-Jammes
First page: 30
Abstract: Biologging refers to the use of animal-borne recording devices to study wildlife behavior. In the case of audio recording, such devices generate large amounts of data over several months, and thus require some level of processing automation for the raw data collected. Academics have widely adopted offline deep-learning-classification algorithms to extract meaningful information from large datasets, mainly using time-frequency signal representations such as spectrograms. Because of the high deployment costs of animal-borne devices, the autonomy/weight ratio remains by far the fundamental concern. Basically, power consumption is addressed using onboard mass storage (no wireless transmission), yet the energy cost associated with data storage activity is far from negligible. In this paper, we evaluate various strategies to reduce the amount of stored data, making the fair assumption that audio will be categorized using a deep-learning classifier at some point of the process. This assumption opens up several scenarios, from straightforward raw audio storage paired with further offline classification on one side, to a fully embedded AI engine on the other side, with embedded audio compression or feature extraction in between. This paper investigates three approaches focusing on data-dimension reduction: (i) traditional inline audio compression, namely ADPCM and MP3, (ii) full deep-learning classification at the edge, and (iii) embedded pre-processing that only computes and stores spectrograms for later offline classification. We characterized each approach in terms of total (sensor + CPU + mass-storage) edge power consumption (i.e., recorder autonomy) and classification accuracy. Our results demonstrate that ADPCM encoding brings 17.6% energy savings compared to the baseline system (i.e., uncompressed raw audio samples). Using such compressed data, a state-of-the-art spectrogram-based classification model still achieves 91.25% accuracy on open speech datasets. Performing inline data-preparation can significantly reduce the amount of stored data allowing for a 19.8% energy saving compared to the baseline system, while still achieving 89% accuracy during classification. These results show that while massive data reduction can be achieved through the use of inline computation of spectrograms, it translates to little benefit on device autonomy when compared to ADPCM encoding, with the added downside of losing original audio information.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-27
DOI: 10.3390/jlpea13020030
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 31: Batteryless Sensor Devices for Underground
Infrastructure—A Long-Term Experiment on Urban Water Pipes
Authors: Manuel Boebel, Fabian Frei, Frank Blumensaat, Christian Ebi, Marcel Louis Meli, Andreas Rüst
First page: 31
Abstract: Drinking water is becoming increasingly scarce as the world’s population grows and climate change continues. However, there is great potential to improve drinking water pipelines, as 30% of fresh water is lost between the supplier and consumer. While systematic process monitoring could play a crucial role in the early detection and repair of leaks, current practice requires manual inspection, which is both time-consuming and costly. This project envisages maintenance-free measurements at numerous locations within the underground infrastructure, a goal that is to be achieved through the use of a harvesting device mounted on the water pipe. This device extracts energy from the temperature difference between the water pipe and the soil using a TEG (thermoelectric generator), takes sensor measurements, processes the data and transmits it wirelessly via LoRaWAN. We built 16 harvesting devices, installed them in four locations and continuously evaluated their performance throughout the project. In this paper, we focus on two devices of a particular type. The data for a full year show that enough energy was available on 94% of the days, on average, to take measurements and transmit data. This study demonstrates that it is possible to power highly constrained sensing devices with energy harvesting in underground environments.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-29
DOI: 10.3390/jlpea13020031
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 32: A Time-Mode PWM 1st Order Low-Pass Filter
Authors: Konstantinos P. Pagkalos, Orfeas Panetas-Felouris, Spyridon Vlassis
First page: 32
Abstract: In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-06
DOI: 10.3390/jlpea13020032
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 33: In-Pipeline Processor Protection against Soft
Errors
Authors: Ján Mach, Lukáš Kohútka, Pavel Čičák
First page: 33
Abstract: The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-10
DOI: 10.3390/jlpea13020033
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 34: Evaluation of Polylactic Acid Polymer as a
Substrate in Rectenna for Ambient Radiofrequency Energy Harvesting
Authors: Pangsui Usifu Linge, Tony Gerges, Pascal Bevilacqua, Jean-Marc Duchamp, Philippe Benech, Jacques Verdier, Philippe Lombard, Michel Cabrera, Pierre Tsafack, Fabien Mieyeville, Bruno Allard
First page: 34
Abstract: This work details the design and experimental characterization of a 2D rectenna for scavenging radio frequency energy at 2.45 GHz (WiFi band), fabricated on polylactic acid polymer (PLA) using a plastronics approach. PLA is the RF substrate of both antenna and rectifier. The two transmission line (TTL) approach is used to characterize the substrate properties to be considered during design. A linearly polarized patch antenna with microstrip transmission feeding is connected to a single series diode rectifier through a T-matching network. The antenna has simulated and measured gain of 7.6 dB and 7.5 dB, respectively. The rectifier has a measured DC output power of 0.96 μW at an optimal load of 2 kΩ under RF input power of −20 dBm at 2.45 GHz. The power conversion efficiency is 9.6% in the latter conditions for a 54 × 36 mm patch antenna of a 1.5 mm thick PLA substrate obtained from additive manufacturing. The power conversion efficiency reaches a value of 28.75% when the input power is −10 dBm at 2.45 GHz. This corresponds to a peak DC power of 28.75 μW when the optimal load is 1.5 kΩ. The results compare significantly with the ones of a similar rectenna circuit manufactured on preferred RF substrate.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-12
DOI: 10.3390/jlpea13020034
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 35: A 0.15-to-0.5 V Body-Driven Dynamic Comparator
with Rail-to-Rail ICMR
Authors: Riccardo Della Sala, Valerio Spinogatti, Cristian Bocciarelli, Francesco Centurelli, Alessandro Trifiletti
First page: 35
Abstract: In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-11
DOI: 10.3390/jlpea13020035
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 36: AMA: An Ageing Task Migration Aware for
High-Performance Computing
Authors: Emmanuel Ofori-Attah, Michael Opoku Agyeman
First page: 36
Abstract: The dark-silicon challenge poses a design problem for future many-core systems. As a result of this, several techniques have been introduced to improve the number of processing elements that can be powered on. One of the techniques employed by many is Task Migration. In this paper, an Ageing Task Migration Aware for High-Performance Computing (AMA) is proposed to improve the lifetime of nodes. The proposed method determines which clusters applications are mapped to and migrates high-demand tasks amongst nodes to improve the lifetime at every epoch. Experimental results show that the proposed method outperforms state-of-the-art techniques by more than 10%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-22
DOI: 10.3390/jlpea13020036
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 37: Ultra-Low Power Programmable Bandwidth
Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply
for Biomedical Applications
Authors: Xuan Thanh Pham, Xuan Thuc Kieu, Manh Kha Hoang
First page: 37
Abstract: This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-24
DOI: 10.3390/jlpea13020037
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 38: Ultra-Low-Power ICs for the Internet of Things
Authors: Orazio Aiello
First page: 38
Abstract: The collection of research works in this Special Issue focuses on Ultra-Low-Power (ULP) Integrated Circuits (ICs) operating under a tight budget of power as a criterion to build electronic devices relying less and less on batteries [...]
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-26
DOI: 10.3390/jlpea13020038
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 39: Nanomaterial-Based Sensor Array Signal
Processing and Tuberculosis Classification Using Machine Learning
Authors: Chenxi Liu, Israel Cohen, Rotem Vishinkin, Hossam Haick
First page: 39
Abstract: Tuberculosis (TB) has long been recognized as a significant health concern worldwide. Recent advancements in noninvasive wearable devices and machine learning (ML) techniques have enabled rapid and cost-effective testing for the real-time detection of TB. However, small datasets are often encountered in biomedical and chemical engineering domains, which can hinder the success of ML models and result in overfitting issues. To address this challenge, we propose various data preprocessing methods and ML approaches, including long short-term memory (LSTM), convolutional neural network (CNN), Gramian angular field-CNN (GAF-CNN), and multivariate time series with MinCutPool (MT-MinCutPool), for classifying a small TB dataset consisting of multivariate time series (MTS) sensor signals. Our proposed methods are compared with state-of-the-art models commonly used in MTS classification (MTSC) tasks. We find that lightweight models are more appropriate for small-dataset problems. Our experimental results demonstrate that the average performance of our proposed models outperformed the baseline methods in all aspects. Specifically, the GAF-CNN model achieved the highest accuracy of 0.639 and the highest specificity of 0.777, indicating its superior effectiveness for MTSC tasks. Furthermore, our proposed MT-MinCutPool model surpassed the baseline MTPool model in all evaluation metrics, demonstrating its viability for MTSC tasks.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-29
DOI: 10.3390/jlpea13020039
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 40: Efficient GEMM Implementation for Vision-Based
Object Detection in Autonomous Driving Applications
Authors: Fatima Zahra Guerrouj, Sergio Rodríguez Flórez, Mohamed Abouzahir, Abdelhafid El Ouardi, Mustapha Ramzi
First page: 40
Abstract: Convolutional Neural Networks (CNNs) have been incredibly effective for object detection tasks. YOLOv4 is a state-of-the-art object detection algorithm designed for embedded systems. It is based on YOLOv3 and has improved accuracy, speed, and robustness. However, deploying CNNs on embedded systems such as Field Programmable Gate Arrays (FPGAs) is difficult due to their limited resources. To address this issue, FPGA-based CNN architectures have been developed to improve the resource utilization of CNNs, resulting in improved accuracy and speed. This paper examines the use of General Matrix Multiplication Operations (GEMM) to accelerate the execution of YOLOv4 on embedded systems. It reviews the most recent GEMM implementations and evaluates their accuracy and robustness. It also discusses the challenges of deploying YOLOv4 on autonomous vehicle datasets. Finally, the paper presents a case study demonstrating the successful implementation of YOLOv4 on an Intel Arria 10 embedded system using GEMM.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-06-06
DOI: 10.3390/jlpea13020040
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 41: Resonator Arrays for Linear Position Sensors
Authors: Mattia Simonazzi, Leonardo Sandrolini, Andrea Mariscotti
First page: 41
Abstract: A contactless position sensor based on an array of magnetically coupled resonators and an external single coil cell is discussed for both stationary and dynamic applications. The simple structure allows the sensor to be adapted to the system in which it is installed and can be used to detect the positions of objects in motion that bear an external resonator coil that does not necessitate a supply. By exploiting the unique behaviour of the array input impedance, it is possible to identify the position of the external resonator by exciting the first array cell with an external voltage source and measuring the resulting input current. The system is robust and suitable for application in harsh environments. The sensitivity of the measured input impedance to the space variation is adjustable with the definition of the array geometry and is analysed. Different configurations of the array and external resonator are considered, and the effects of various termination conditions and the resulting factor of merit after changing the coil resistance are discussed. The proposed procedure is numerically validated for an array of ten identical magnetically coupled resonators with 15 cm side lengths. Simulations carried out for a distance of up to 20 cm show that, with a quality factor lower than 100 and optimal terminations of both the array and external coil, it is possible to detect the position of the latter.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-06-07
DOI: 10.3390/jlpea13020041
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 4: Simple Technique to Improve Essentially the
Performance of One-Stage Op-Amps in Deep Submicrometer CMOS Technologies
Authors: Jaime Ramirez-Angulo, Alejandra Diaz-Armendariz, Jesus E. Molinar-Solis, Alejandro Diaz-Sanchez, Jesus Huerta-Chua
First page: 4
Abstract: A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-04
DOI: 10.3390/jlpea13010004
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 5: A Bottom-Up Methodology for the Fast Assessment
of CNN Mappings on Energy-Efficient Accelerators
Authors: Guillaume Devic, Gilles Sassatelli, Abdoulaye Gamatié
First page: 5
Abstract: The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads on accelerators, however, is a very challenging task. In this paper, we propose a design methodology by combining different abstraction levels to quickly address the mapping of convolutional neural networks on ML accelerators. Starting from an open-source core adopting the RISC-V instruction set architecture, we define in RTL a more flexible and powerful multiply-and-accumulate (MAC) unit, compared to the native MAC unit. Our proposal contributes to improving the energy efficiency of the RISC-V cores of PULPino. To effectively evaluate its benefits at system level, while considering CNN execution, we build a corresponding analytical model in the Timeloop/Accelergy simulation and evaluation environment. This enables us to quickly explore CNN mappings on a typical RISC-V system-on-chip model, manufactured under the name of GAP8. The modeling flexibility offered by Timeloop makes it possible to easily evaluate our novel MAC unit in further CNN accelerator architectures such as Eyeriss and DianNao. Overall, the resulting bottom-up methodology assists designers in the efficient implementation of CNNs on ML accelerators by leveraging the accuracy and speed of the combined abstraction levels.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-05
DOI: 10.3390/jlpea13010005
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 6: FPGA-Based Decision Support System for ECG
Analysis
Authors: Agostino Giorgio, Cataldo Guaragnella, Maria Rizzi
First page: 6
Abstract: The high mortality rate associated with cardiac abnormalities highlights the need of accurately detecting heart disorders in the early stage so to avoid severe health consequence for patients. Health trackers have become popular in the form of wearable devices. They are aimed to perform cardiac monitoring outside of medical clinics during peoples’ daily lives. Our paper proposes a new diagnostic algorithm and its implementation adopting a FPGA-based design. The conceived system automatically detects the most common arrhythmias and is also able to evaluate QT-segment lengthening and pulmonary embolism risk often caused by myocarditis. Debug and simulations have been carried out firstly in Matlab environment and then in Quartus IDE by Intel. The hardware implementation of the embedded system and the test for the functional accuracy verification have been performed adopting the DE1_SoC development board by Terasic, which is equipped with the Cyclone V 5CSEMA5F31C6 FPGA by Intel. Properly modified real ECG signals corrupted by a mixture of muscle noise, electrode movement artifacts, and baseline wander are used as a test bench. A value of 99.20% accuracy is achieved by taking into account 0.02 mV for the root mean square value of noise voltage. The implemented low-power circuit is suitable as a wearable decision support device.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-07
DOI: 10.3390/jlpea13010006
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 7: Electromigration-Aware Architecture for Modern
Microprocessors
Authors: Freddy Gabbay, Avi Mendelson
First page: 7
Abstract: Reliability is a fundamental requirement in microprocessors that guarantees correct execution over their lifetimes. The reliability-related design rules depend on the process technology and device operating conditions. To meet reliability requirements, advanced process nodes impose challenging design rules, which place a major burden on the VLSI implementation flow because they impose severe physical constraints. This paper focuses on electromigration (EM), one of the critical factors affecting semiconductor reliability. EM is the aging process of on-die wires in integrated circuits (ICs). Traditionally, EM issues have been handled at the physical design level, which enforces reliability rules using worst-case scenario analysis to detect and solve violations. In this paper, we offer solutions that exploit architectural characteristics to reduce EM impact. The use of architectural methods can simplify EM solutions, and such methods can be incorporated with standard physical-design-based solutions to enhance current methods. Our comprehensive physical simulation results show that, with minimal area, power, and performance overhead, the proposed solution can relax EM design efforts and significantly extend a microprocessor’s lifetime.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-11
DOI: 10.3390/jlpea13010007
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 8: Numerical Optimization of a Nonlinear Nonideal
Piezoelectric Energy Harvester Using Deep Learning
Authors: Andreas Hegendörfer, Paul Steinmann, Julia Mergheim
First page: 8
Abstract: This contribution addresses the numerical optimization of the harvested energy of a mechanically and electrically nonlinear and nonideal piezoelectric energy harvester (PEH) under triangular shock-like excitation, taking into account a nonlinear stress constraint. In the optimization problem, a bimorph electromechanical structure equipped with the Greinacher circuit or the standard circuit is considered and different electrical and mechanical design variables are introduced. Using a very accurate coupled finite element-electronic circuit simulator method, deep neural network (DNN) training data are generated, allowing for a computationally efficient evaluation of the objective function. Subsequently, a genetic algorithm using the DNNs is applied to find the electrical and mechanical design variables that optimize the harvested energy. It is found that the maximum harvested energy is obtained at the maximum possible mechanical stresses and that the optimum storage capacitor for the Greinacher circuit is much smaller than that for the standard circuit, while the total harvested energy by both configurations is similar.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-12
DOI: 10.3390/jlpea13010008
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 9: Acknowledgment to the Reviewers of Journal of Low
Power Electronics and Applications in 2022
Authors: JLPEA Editorial Office JLPEA Editorial Office
First page: 9
Abstract: High-quality academic publishing is built on rigorous peer review [...]
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-16
DOI: 10.3390/jlpea13010009
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 10: A Power-Efficient Neuromorphic Digital
Implementation of Neural–Glial Interactions
Authors: Angeliki Bicaku, Maria Sapounaki, Athanasios Kakarountas, Sotiris K. Tasoulis
First page: 10
Abstract: Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate area- and power-efficient circuits. Motivated by studies that outline the indispensable role of astrocytes in the dynamic regulation of synaptic transmission and their active contribution to neural information processing in the CNS, in this work we propose a digital implementation of neuron–astrocyte bidirectional interactions. In order to describe the neuronal dynamics and the astrocytes’ calcium dynamics, a modified version of the original Izhikevich neuron model was combined with a linear approximation of the Postnov functional neural–glial interaction model. For the implementation of the neural–glial computation core, only three pipeline stages and a 10.10 fixed point representation were utilized. Regarding the results obtained from the FPGA implementation and the comparisons to other works, the proposed neural–glial circuit reported significant savings in area requirements (from 22.53% up to 164.20%) along with considerable savings in total power consumption of 28.07% without sacrificing output computation accuracy. Finally, an RMSE analysis was conducted, confirming that this particular implementation produces more accurate results compared to previous studies.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-18
DOI: 10.3390/jlpea13010010
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 11: Study of Nitrogen-Doped Carbon Nanotubes for
Creation of Piezoelectric Nanogenerator
Authors: Marina V. Il’ina, Olga I. Soboleva, Soslan A. Khubezov, Vladimir A. Smirnov, Oleg I. Il’in
First page: 11
Abstract: The creation of sustainable power sources for wearable electronics and self-powered systems is a promising direction of modern electronics. At the moment, a search for functional materials with high values of piezoelectric coefficient and elasticity, as well as non-toxicity, is underway to generate such power sources. In this paper, nitrogen-doped carbon nanotubes (N-CNTs) are considered as a functional material for a piezoelectric nanogenerator capable of converting nanoscale deformations into electrical energy. The effect of defectiveness and of geometric and mechanical parameters of N-CNTs on the current generated during their deformation is studied. It was established that the piezoelectric response of N-CNTs increased nonlinearly with an increase in the Young’s modulus and the aspect ratio of the length to diameter of the nanotube and, on the contrary, decreased with an increase in defectiveness not caused by the incorporation of nitrogen atoms. The advantages of using N-CNT to create energy-efficient piezoelectric nanogenerators are shown.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-22
DOI: 10.3390/jlpea13010011
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 12: Energy Autonomous Wireless Sensing Node Working
at 5 Lux from a 4 cm2 Solar Cell
Authors: Marcel Louis Meli, Sebastien Favre, Benjamin Maij, Stefan Stajic, Manuel Boebel, Philip John Poole, Martin Schellenberg, Charalampos S. Kouzinopoulos
First page: 12
Abstract: Harvesting energy for IoT nodes in places that are permanently poorly lit is important, as many such places exist in buildings and other locations. The need for energy-autonomous devices working in such environments has so far received little attention. This work reports the design and test results of an energy-autonomous sensor node powered solely by solar cells. The system can cold-start and run in low light conditions (in this case 20 lux and below, using white LEDs as light sources). Four solar cells of 1 cm2 each are used, yielding a total active surface of 4 cm2. The system includes a capacitive sensor that acts as a touch detector, a crystal-accurate real-time clock (RTC), and a Cortex-M3-compatible microcontroller integrating a Bluetooth Low Energy radio (BLE) and the necessary stack for communication. A capacitor of 100 μF is used as energy storage. A low-power comparator monitors the level of the energy storage and powers up the system. The combination of the RTC and touch sensor enables the MCU load to be powered up periodically or using an asynchronous user touch activity. First tests have shown that the system can perform the basic work of cold-starting, sensing, and transmitting frames at +0 dBm, at illuminances as low as 5 lux. Harvesting starts earlier, meaning that the potential for full function below 5 lux is present. The system has also been tested with other light sources. The comparator is a test chip developed for energy harvesting. Other elements are off-the-shelf components. The use of commercially available devices, the reduced number of parts, and the absence of complex storage elements enable a small node to be built in the future, for use in constantly or intermittently poorly lit places.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-01
DOI: 10.3390/jlpea13010012
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 13: Minimum Active Component Count Design of a
PIλDμ Controller and Its Application in a Cardiac Pacemaker
System
Authors: Julia Nako, Costas Psychalinos, Ahmed S. Elwakil
First page: 13
Abstract: A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as the Foster and Cauer networks. The main offered benefit, with regards to the corresponding convectional implementations, is the reduced active and, also, passive component count. To demonstrate the versatility of the proposed concept, a controller suitable for implementing a cardiac pacemaker control system is designed. The evaluation of the performance of the system is performed through circuit simulation results, using a second-generation voltage conveyor as the active element.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-02
DOI: 10.3390/jlpea13010013
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 14: Wideband Cascaded and Stacked Receiver
Front-Ends Employing an Improved Clock-Strategy Technique
Authors: Arash Abbasi, Frederic Nabki
First page: 14
Abstract: A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-02
DOI: 10.3390/jlpea13010014
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 15: A 1.1 V 25 ppm/°C Relaxation Oscillator with
0.045%/V Line Sensitivity for Low Power Applications
Authors: Yizhuo Liao, Pak Kwong Chan
First page: 15
Abstract: A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-07
DOI: 10.3390/jlpea13010015
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 16: Exploring Topological Semi-Metals for
Interconnects
Authors: Satwik Kundu, Rupshali Roy, M. Saifur Rahman, Suryansh Upadhyay, Rasit Onur Topaloglu, Suzanne E. Mohney, Shengxi Huang, Swaroop Ghosh
First page: 16
Abstract: The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-09
DOI: 10.3390/jlpea13010016
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 17: Decoding Algorithms and HW Strategies to
Mitigate Uncertainties in a PCM-Based Analog Encoder for Compressed
Sensing
Authors: Carmine Paolino, Alessio Antolini, Francesco Zavalloni, Andrea Lico, Eleonora Franchi Scarselli, Mauro Mangia, Alex Marchioni, Fabio Pareschi, Gianluca Setti, Riccardo Rovatti, Mattia Luigi Torres, Marcella Carissimi, Marco Pasotti
First page: 17
Abstract: Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. The same concept can be readily applied to the encoding stage in Compressed Sensing (CS) systems, where an MVM operation maps input signals into compressed measurements. With a focus on an encoder built on top of a Phase-Change Memory (PCM) AIMC platform, the effects of device non-idealities, namely programming spread and drift over time, are observed in terms of the reconstruction quality obtained for synthetic signals, sparse in the Discrete Cosine Transform (DCT) domain. PCM devices are simulated using statistical models summarizing the properties experimentally observed in an AIMC prototype, designed in a 90 nm STMicroelectronics technology. Different families of decoders are tested, and tradeoffs in terms of encoding energy are analyzed. Furthermore, the benefits of a hardware drift compensation strategy are also observed, highlighting its necessity to prevent the need for a complete reprogramming of the entire analog array. The results show >30 dB average reconstruction quality for mid-range conductances and a suitably selected decoder right after programming. Additionally, the hardware drift compensation strategy enables robust performance even when different drift conditions are tested.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-13
DOI: 10.3390/jlpea13010017
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 18: Self-Parameterized Chaotic Map for Low-Cost
Robust Chaos
Authors: Partha Sarathi Paul, Anurag Dhungel, Maisha Sadia, Md Razuan Hossain, Md Sakib Hasan
First page: 18
Abstract: This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-13
DOI: 10.3390/jlpea13010018
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 19: Radio-Frequency Energy Harvesting Using Rapid 3D
Plastronics Protoyping Approach: A Case Study
Authors: Xuan Viet Linh Nguyen, Tony Gerges, Pascal Bevilacqua, Jean-Marc Duchamp, Philippe Benech, Jacques Verdier, Philippe Lombard, Pangsui Usifu Linge, Fabien Mieyeville, Michel Cabrera, Bruno Allard
First page: 19
Abstract: Harvesting of ambient radio-frequency energy is largely covered in the literature. The RF energy harvester is considered most of the time as a standalone board. There is an interest to add the RF harvesting function on an already-designed object. Polymer objects are considered here, manufactured through an additive process and the paper focuses on the rapid prototyping of the harvester using a plastronic approach. An array of four antennas is considered for circular polarization with high self-isolation. The RF circuit is obtained using an electroless copper metallization of the surface of a 3D substrate fabricated using stereolithography printing. The RF properties of the polymer resin are not optimal; thus, the interest of this work is to investigate the potential capabilities of such an implementation, particularly in terms of freedom of 3D design and ease of fabrication. The electromagnetic properties of the substrate are characterized over a band of 0.5–2.5 GHz applying the two-transmission-line method. A circular polarization antenna is experimented as a rapid prototyping vehicle and yields a gain of 1.26 dB. A lab-scale prototype of the rectifier and power management unit are experimented with discrete components. The cold start-up circuit accepts a minimum voltage of 180 mV. The main DC/DC converter operates under 1.4 V but is able to compensate losses for an input DC voltage as low as 100 mV (10 μW). The rectifier alone is capable of 3.5% efficiency at −30 dBm input RF power. The global system of circularly polarized antenna, rectifier, and voltage conversion features a global experimental efficiency of 14.7% at an input power of −13.5 dBm. The possible application of such results is discussed.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-17
DOI: 10.3390/jlpea13010019
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 20: Efficient Dual Output Regulating Rectifier and
Adiabatic Charge Pump for Biomedical Applications Employing Wireless Power
Transfer
Authors: Noora Almarri, Peter Langlois, Dai Jiang, Andreas Demosthenous
First page: 20
Abstract: A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-04
DOI: 10.3390/jlpea13010020
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 21: DycSe: A Low-Power, Dynamic Reconfiguration
Column Streaming-Based Convolution Engine for Resource-Aware Edge AI
Accelerators
Authors: Weison Lin, Yajun Zhu, Tughrul Arslan
First page: 21
Abstract: Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator brings a customized design to meet the requirements of the edge environment. The requirements include real-time processing, low-power consumption, and resource-awareness, including resources on field programmable gate array (FPGA) or limited application-specific integrated circuit (ASIC) area. The system’s reliability (e.g., permanent fault tolerance) is essential if the devices target radiation fields such as space and nuclear power stations. This paper proposes a dynamic reconfigurable column streaming-based convolution engine (DycSe) with programmable adder modules for low-power and resource-aware edge AI accelerators to meet the requirements. The proposed DycSe design does not target the FPGA platform only. Instead, it is an intellectual property (IP) core design. The FPGA platform used in this paper is for prototyping the design evaluation. This paper uses the Vivado synthesis tool to evaluate the power consumption and resource usage of DycSe. Since the synthesis tool is limited to giving the final complete system result in the designing stage, we compare DycSe to a commercial edge AI accelerator for cross-reference with other state-of-the-art works. The commercial architecture shares the competitive performance within the low-power ultra-small (LPUS) edge AI scopes. The result shows that DycSe contains 3.56% less power consumption and slight resources (1%) overhead with reconfigurable flexibility.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-16
DOI: 10.3390/jlpea13010021
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 22: Extreme Path Delay Estimation of Critical Paths
in Within-Die Process Fluctuations Using Multi-Parameter Distributions
Authors: Miikka Runolinna, Matthew Turnquist, Jukka Teittinen, Pauliina Ilmonen, Lauri Koskinen
First page: 22
Abstract: Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distributions outperform the normal distribution in goodness-of-fit statistics for simulated path delay data derived from a fabricated microcontroller, with the six-term metalog distribution offering the best fit. Furthermore, 99.7% confidence intervals are calculated for some extreme quantiles on each dataset using the previous distributions. Considering the six-term metalog distribution estimates as the golden standard, the relative errors in single paths vary between 4 and 14% for the normal distribution. Finally, the within-die (WID) variation maximum critical path delay distribution for multiple critical paths is derived under the assumption of independence between the paths. Its density function is then used to compute different maximum delays for varying numbers of critical paths, assuming each path has one of the previous distributions with the metalog estimates as the golden standard. For 100 paths, the relative errors are at most 14% for the normal distribution. With 1000 and 10,000 paths, the corresponding errors extend up to 16 and 19%, respectively.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-20
DOI: 10.3390/jlpea13010022
Issue No: Vol. 13, No. 1 (2023)
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