 Subjects -> ELECTRONICS (Total: 207 journals)
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- JLPEA, Vol. 13, Pages 23: A Ka-Band SiGe BiCMOS Quasi-F−1 Power
Amplifier Using a Parasitic Capacitance Cancellation Technique †
Authors: Vasileios Manouras, Ioannis Papananos
First page: 23
Abstract: This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simplified model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with fT/fmax=250/370 GHz and it is suitable for 5G applications. It achieves 33% peak power-added efficiency (PAE), 18.8 dBm saturation output power Psat, and 14.7 dB maximum large-signal power gain G at the operating frequency of 38 GHz. The PA’s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is 0.605×0.712 mm2 including all pads.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-24
DOI: 10.3390/jlpea13020023
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 24: A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with
Non-Tailed Differential Pair
Authors: Andrea Ballo, Alfio Dario Grasso, Salvatore Pennisi
First page: 24
Abstract: This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-28
DOI: 10.3390/jlpea13020024
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 25: First Review of Conductive Electrets for
Low-Power Electronics
Authors: D. D. L. Chung
First page: 25
Abstract: This is the first review of conductive electrets (unpoled carbons and metals), which provide a new avenue for low-power electronics. The electret provides low DC voltage (μV) while allowing low DC current (μA) to pass through. Ohm’s Law is obeyed. The voltage scales with the inter-electrode distance. Series connection of multiple electret components provides a series voltage that equals the sum of the voltages of the components if there is no bending at the connection between the components. Otherwise, the series voltage is below the sum. Bending within the component also diminishes the voltage because of the polarization continuity decrease. The electret originates from the interaction of a tiny fraction of the carriers with the atoms. This interaction results in the charge in the electret. Dividing the electret charge by the electret voltage V’ provides the electret-based capacitance C’, which is higher than the permittivity-based capacitance (conventional) by a large number of orders of magnitude. The C’ governs the electret energy (1/2 C’V’2) and electret discharge time constant (RC’, where R = resistance), as shown for metals. The discharge time is promoted by a larger inter-electrode distance. The electret discharges occur upon short-circuiting and charge back upon subsequent opencircuiting. The discharge or charge of the electret amounts to the discharge or charge of C’.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-06
DOI: 10.3390/jlpea13020025
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 26: Innovative Characterization and Comparative
Analysis of Water Level Sensors for Enhanced Early Detection and Warning
of Floods
Authors: Rula Tawalbeh, Feras Alasali, Zahra Ghanem, Mohammad Alghazzawi, Ahmad Abu-Raideh, William Holderbaum
First page: 26
Abstract: In considering projections that flooding will increase in the future years due to factors such as climate change and urbanization, the need for dependable and accurate water sensors systems is greater than ever. In this study, the performance of four different water level sensors, including ultrasonic, infrared (IR), and pressure sensors, is analyzed based on innovative characterization and comparative analysis, to determine whether or not these sensors have the ability to detect rising water levels and flash floods at an earlier stage under different conditions. During our exhaustive tests, we subjected the device to a variety of conditions, including clean and contaminated water, light and darkness, and an analogue connection to a display. When it came to monitoring water levels, the ultrasonic sensors stood out because of their remarkable precision and consistency. To address this issue, this study provides a novel and comparative examination of four water level sensors to determine which is the most effective and cost-effective in detecting floods and water level fluctuations. The IR sensor delivered accurate findings; however, it demonstrated some degree of variability throughout the course of the experiment. In addition, the results of our research show that the pressure sensor is a legitimate alternative to ultrasonic sensors. This presents a possibility that is more advantageous financially when it comes to the development of effective water level monitoring systems. The findings of this study are extremely helpful in improving the dependability and accuracy of flood detection systems and, eventually, in lessening the devastation caused by natural catastrophes.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-11
DOI: 10.3390/jlpea13020026
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 27: Buck-Boost Charge Pump Based DC-DC Converter
Authors: Evi Keramida, George Souliotis, Spyridon Vlassis, Fotis Plessas
First page: 27
Abstract: This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltage, respectively, compared to the input. To achieve each mode, only a switching of the input–output connections is needed without any other modification in the design of the DC-DC converter. The dual-mode configuration aims to merge two different functions into one circuit, minimizing the design time and the area the DC-DC converter occupies on the die. The proposed buck-boost CP has been designed using TSMC 65 nm complementary metal–oxide–semiconductor (CMOS) technology. The functional input voltage range of the CP in boost mode is 1.2 V to 1.8 V and the typical output voltage is 1.8 V. For the buck mode, the input voltage range is 3.2 V to 3.6 V and the output is 1.5 V. For both modes, the output can be easily modified to new values by changing the comparator configuration. Efficiency results are also provided for the two modes.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-21
DOI: 10.3390/jlpea13020027
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 28: Class AB Voltage Follower and Low-Voltage
Current Mirror with Very High Figures of Merit Based on the Flipped
Voltage Follower
Authors: Jaime Ramírez-Angulo, Anindita Paul, Manaswini Gangineni, Jose Maria Hinojo-Montero, Jesús Huerta-Chua
First page: 28
Abstract: The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180nm CMOS (Complementary Metal Oxide Semiconductor) technology.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-24
DOI: 10.3390/jlpea13020028
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 29: Battery Parameter Analysis through
Electrochemical Impedance Spectroscopy at Different State of Charge Levels
Authors: Yuchao Wu, Sneha Sundaresan, Balakumar Balasingam
First page: 29
Abstract: This paper presents a systematic approach to extract electrical equivalent circuit model (ECM) parameters of the Li-ion battery (LIB) based on electrochemical impedance spectroscopy (EIS). Particularly, the proposed approach is suitable to practical applications where the measurement noise can be significant, resulting in a low signal-to-noise ratio. Given the EIS measurements, the proposed approach can be used to obtain the ECM parameters of a battery. Then, a time domain approach is employed to validate the accuracy of estimated ECM parameters. In order to investigate whether the ECM parameters vary as the battery’s state of charge (SOC) changes, the EIS experiment was repeated at nine different SOCs. The experimental results show that the proposed approach is consistent in estimating the ECM parameters. It is found that the battery parameters, such as internal resistance, capacitance and inductance, remain the same for practical SOC ranges starting from 20% until 90%. The ECM parameters saw a significant change at low SOC levels. Furthermore, the experimental data show that the resistive components estimated in the frequency domain are very close to the internal resistance estimated in the time domain. The proposed approach was applied to eight different battery cells consisting of two different manufacturers and produced consistent results.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-26
DOI: 10.3390/jlpea13020029
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 30: Energy-Efficient Audio Processing at the Edge
for Biologging Applications
Authors: Jonathan Miquel, Laurent Latorre, Simon Chamaillé-Jammes
First page: 30
Abstract: Biologging refers to the use of animal-borne recording devices to study wildlife behavior. In the case of audio recording, such devices generate large amounts of data over several months, and thus require some level of processing automation for the raw data collected. Academics have widely adopted offline deep-learning-classification algorithms to extract meaningful information from large datasets, mainly using time-frequency signal representations such as spectrograms. Because of the high deployment costs of animal-borne devices, the autonomy/weight ratio remains by far the fundamental concern. Basically, power consumption is addressed using onboard mass storage (no wireless transmission), yet the energy cost associated with data storage activity is far from negligible. In this paper, we evaluate various strategies to reduce the amount of stored data, making the fair assumption that audio will be categorized using a deep-learning classifier at some point of the process. This assumption opens up several scenarios, from straightforward raw audio storage paired with further offline classification on one side, to a fully embedded AI engine on the other side, with embedded audio compression or feature extraction in between. This paper investigates three approaches focusing on data-dimension reduction: (i) traditional inline audio compression, namely ADPCM and MP3, (ii) full deep-learning classification at the edge, and (iii) embedded pre-processing that only computes and stores spectrograms for later offline classification. We characterized each approach in terms of total (sensor + CPU + mass-storage) edge power consumption (i.e., recorder autonomy) and classification accuracy. Our results demonstrate that ADPCM encoding brings 17.6% energy savings compared to the baseline system (i.e., uncompressed raw audio samples). Using such compressed data, a state-of-the-art spectrogram-based classification model still achieves 91.25% accuracy on open speech datasets. Performing inline data-preparation can significantly reduce the amount of stored data allowing for a 19.8% energy saving compared to the baseline system, while still achieving 89% accuracy during classification. These results show that while massive data reduction can be achieved through the use of inline computation of spectrograms, it translates to little benefit on device autonomy when compared to ADPCM encoding, with the added downside of losing original audio information.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-27
DOI: 10.3390/jlpea13020030
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 31: Batteryless Sensor Devices for Underground
Infrastructure—A Long-Term Experiment on Urban Water Pipes
Authors: Manuel Boebel, Fabian Frei, Frank Blumensaat, Christian Ebi, Marcel Louis Meli, Andreas Rüst
First page: 31
Abstract: Drinking water is becoming increasingly scarce as the world’s population grows and climate change continues. However, there is great potential to improve drinking water pipelines, as 30% of fresh water is lost between the supplier and consumer. While systematic process monitoring could play a crucial role in the early detection and repair of leaks, current practice requires manual inspection, which is both time-consuming and costly. This project envisages maintenance-free measurements at numerous locations within the underground infrastructure, a goal that is to be achieved through the use of a harvesting device mounted on the water pipe. This device extracts energy from the temperature difference between the water pipe and the soil using a TEG (thermoelectric generator), takes sensor measurements, processes the data and transmits it wirelessly via LoRaWAN. We built 16 harvesting devices, installed them in four locations and continuously evaluated their performance throughout the project. In this paper, we focus on two devices of a particular type. The data for a full year show that enough energy was available on 94% of the days, on average, to take measurements and transmit data. This study demonstrates that it is possible to power highly constrained sensing devices with energy harvesting in underground environments.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-04-29
DOI: 10.3390/jlpea13020031
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 32: A Time-Mode PWM 1st Order Low-Pass Filter
Authors: Konstantinos P. Pagkalos, Orfeas Panetas-Felouris, Spyridon Vlassis
First page: 32
Abstract: In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-06
DOI: 10.3390/jlpea13020032
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 33: In-Pipeline Processor Protection against Soft
Errors
Authors: Ján Mach, Lukáš Kohútka, Pavel Čičák
First page: 33
Abstract: The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-10
DOI: 10.3390/jlpea13020033
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 34: Evaluation of Polylactic Acid Polymer as a
Substrate in Rectenna for Ambient Radiofrequency Energy Harvesting
Authors: Pangsui Usifu Linge, Tony Gerges, Pascal Bevilacqua, Jean-Marc Duchamp, Philippe Benech, Jacques Verdier, Philippe Lombard, Michel Cabrera, Pierre Tsafack, Fabien Mieyeville, Bruno Allard
First page: 34
Abstract: This work details the design and experimental characterization of a 2D rectenna for scavenging radio frequency energy at 2.45 GHz (WiFi band), fabricated on polylactic acid polymer (PLA) using a plastronics approach. PLA is the RF substrate of both antenna and rectifier. The two transmission line (TTL) approach is used to characterize the substrate properties to be considered during design. A linearly polarized patch antenna with microstrip transmission feeding is connected to a single series diode rectifier through a T-matching network. The antenna has simulated and measured gain of 7.6 dB and 7.5 dB, respectively. The rectifier has a measured DC output power of 0.96 μW at an optimal load of 2 kΩ under RF input power of −20 dBm at 2.45 GHz. The power conversion efficiency is 9.6% in the latter conditions for a 54 × 36 mm patch antenna of a 1.5 mm thick PLA substrate obtained from additive manufacturing. The power conversion efficiency reaches a value of 28.75% when the input power is −10 dBm at 2.45 GHz. This corresponds to a peak DC power of 28.75 μW when the optimal load is 1.5 kΩ. The results compare significantly with the ones of a similar rectenna circuit manufactured on preferred RF substrate.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-12
DOI: 10.3390/jlpea13020034
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 35: A 0.15-to-0.5 V Body-Driven Dynamic Comparator
with Rail-to-Rail ICMR
Authors: Riccardo Della Sala, Valerio Spinogatti, Cristian Bocciarelli, Francesco Centurelli, Alessandro Trifiletti
First page: 35
Abstract: In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-11
DOI: 10.3390/jlpea13020035
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 36: AMA: An Ageing Task Migration Aware for
High-Performance Computing
Authors: Emmanuel Ofori-Attah, Michael Opoku Agyeman
First page: 36
Abstract: The dark-silicon challenge poses a design problem for future many-core systems. As a result of this, several techniques have been introduced to improve the number of processing elements that can be powered on. One of the techniques employed by many is Task Migration. In this paper, an Ageing Task Migration Aware for High-Performance Computing (AMA) is proposed to improve the lifetime of nodes. The proposed method determines which clusters applications are mapped to and migrates high-demand tasks amongst nodes to improve the lifetime at every epoch. Experimental results show that the proposed method outperforms state-of-the-art techniques by more than 10%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-22
DOI: 10.3390/jlpea13020036
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 37: Ultra-Low Power Programmable Bandwidth
Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply
for Biomedical Applications
Authors: Xuan Thanh Pham, Xuan Thuc Kieu, Manh Kha Hoang
First page: 37
Abstract: This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-24
DOI: 10.3390/jlpea13020037
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 38: Ultra-Low-Power ICs for the Internet of Things
Authors: Orazio Aiello
First page: 38
Abstract: The collection of research works in this Special Issue focuses on Ultra-Low-Power (ULP) Integrated Circuits (ICs) operating under a tight budget of power as a criterion to build electronic devices relying less and less on batteries [...]
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-26
DOI: 10.3390/jlpea13020038
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 39: Nanomaterial-Based Sensor Array Signal
Processing and Tuberculosis Classification Using Machine Learning
Authors: Chenxi Liu, Israel Cohen, Rotem Vishinkin, Hossam Haick
First page: 39
Abstract: Tuberculosis (TB) has long been recognized as a significant health concern worldwide. Recent advancements in noninvasive wearable devices and machine learning (ML) techniques have enabled rapid and cost-effective testing for the real-time detection of TB. However, small datasets are often encountered in biomedical and chemical engineering domains, which can hinder the success of ML models and result in overfitting issues. To address this challenge, we propose various data preprocessing methods and ML approaches, including long short-term memory (LSTM), convolutional neural network (CNN), Gramian angular field-CNN (GAF-CNN), and multivariate time series with MinCutPool (MT-MinCutPool), for classifying a small TB dataset consisting of multivariate time series (MTS) sensor signals. Our proposed methods are compared with state-of-the-art models commonly used in MTS classification (MTSC) tasks. We find that lightweight models are more appropriate for small-dataset problems. Our experimental results demonstrate that the average performance of our proposed models outperformed the baseline methods in all aspects. Specifically, the GAF-CNN model achieved the highest accuracy of 0.639 and the highest specificity of 0.777, indicating its superior effectiveness for MTSC tasks. Furthermore, our proposed MT-MinCutPool model surpassed the baseline MTPool model in all evaluation metrics, demonstrating its viability for MTSC tasks.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-05-29
DOI: 10.3390/jlpea13020039
Issue No: Vol. 13, No. 2 (2023)
- JLPEA, Vol. 13, Pages 4: Simple Technique to Improve Essentially the
Performance of One-Stage Op-Amps in Deep Submicrometer CMOS Technologies
Authors: Jaime Ramirez-Angulo, Alejandra Diaz-Armendariz, Jesus E. Molinar-Solis, Alejandro Diaz-Sanchez, Jesus Huerta-Chua
First page: 4
Abstract: A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-04
DOI: 10.3390/jlpea13010004
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 5: A Bottom-Up Methodology for the Fast Assessment
of CNN Mappings on Energy-Efficient Accelerators
Authors: Guillaume Devic, Gilles Sassatelli, Abdoulaye Gamatié
First page: 5
Abstract: The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads on accelerators, however, is a very challenging task. In this paper, we propose a design methodology by combining different abstraction levels to quickly address the mapping of convolutional neural networks on ML accelerators. Starting from an open-source core adopting the RISC-V instruction set architecture, we define in RTL a more flexible and powerful multiply-and-accumulate (MAC) unit, compared to the native MAC unit. Our proposal contributes to improving the energy efficiency of the RISC-V cores of PULPino. To effectively evaluate its benefits at system level, while considering CNN execution, we build a corresponding analytical model in the Timeloop/Accelergy simulation and evaluation environment. This enables us to quickly explore CNN mappings on a typical RISC-V system-on-chip model, manufactured under the name of GAP8. The modeling flexibility offered by Timeloop makes it possible to easily evaluate our novel MAC unit in further CNN accelerator architectures such as Eyeriss and DianNao. Overall, the resulting bottom-up methodology assists designers in the efficient implementation of CNNs on ML accelerators by leveraging the accuracy and speed of the combined abstraction levels.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-05
DOI: 10.3390/jlpea13010005
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 6: FPGA-Based Decision Support System for ECG
Analysis
Authors: Agostino Giorgio, Cataldo Guaragnella, Maria Rizzi
First page: 6
Abstract: The high mortality rate associated with cardiac abnormalities highlights the need of accurately detecting heart disorders in the early stage so to avoid severe health consequence for patients. Health trackers have become popular in the form of wearable devices. They are aimed to perform cardiac monitoring outside of medical clinics during peoples’ daily lives. Our paper proposes a new diagnostic algorithm and its implementation adopting a FPGA-based design. The conceived system automatically detects the most common arrhythmias and is also able to evaluate QT-segment lengthening and pulmonary embolism risk often caused by myocarditis. Debug and simulations have been carried out firstly in Matlab environment and then in Quartus IDE by Intel. The hardware implementation of the embedded system and the test for the functional accuracy verification have been performed adopting the DE1_SoC development board by Terasic, which is equipped with the Cyclone V 5CSEMA5F31C6 FPGA by Intel. Properly modified real ECG signals corrupted by a mixture of muscle noise, electrode movement artifacts, and baseline wander are used as a test bench. A value of 99.20% accuracy is achieved by taking into account 0.02 mV for the root mean square value of noise voltage. The implemented low-power circuit is suitable as a wearable decision support device.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-07
DOI: 10.3390/jlpea13010006
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 7: Electromigration-Aware Architecture for Modern
Microprocessors
Authors: Freddy Gabbay, Avi Mendelson
First page: 7
Abstract: Reliability is a fundamental requirement in microprocessors that guarantees correct execution over their lifetimes. The reliability-related design rules depend on the process technology and device operating conditions. To meet reliability requirements, advanced process nodes impose challenging design rules, which place a major burden on the VLSI implementation flow because they impose severe physical constraints. This paper focuses on electromigration (EM), one of the critical factors affecting semiconductor reliability. EM is the aging process of on-die wires in integrated circuits (ICs). Traditionally, EM issues have been handled at the physical design level, which enforces reliability rules using worst-case scenario analysis to detect and solve violations. In this paper, we offer solutions that exploit architectural characteristics to reduce EM impact. The use of architectural methods can simplify EM solutions, and such methods can be incorporated with standard physical-design-based solutions to enhance current methods. Our comprehensive physical simulation results show that, with minimal area, power, and performance overhead, the proposed solution can relax EM design efforts and significantly extend a microprocessor’s lifetime.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-11
DOI: 10.3390/jlpea13010007
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 8: Numerical Optimization of a Nonlinear Nonideal
Piezoelectric Energy Harvester Using Deep Learning
Authors: Andreas Hegendörfer, Paul Steinmann, Julia Mergheim
First page: 8
Abstract: This contribution addresses the numerical optimization of the harvested energy of a mechanically and electrically nonlinear and nonideal piezoelectric energy harvester (PEH) under triangular shock-like excitation, taking into account a nonlinear stress constraint. In the optimization problem, a bimorph electromechanical structure equipped with the Greinacher circuit or the standard circuit is considered and different electrical and mechanical design variables are introduced. Using a very accurate coupled finite element-electronic circuit simulator method, deep neural network (DNN) training data are generated, allowing for a computationally efficient evaluation of the objective function. Subsequently, a genetic algorithm using the DNNs is applied to find the electrical and mechanical design variables that optimize the harvested energy. It is found that the maximum harvested energy is obtained at the maximum possible mechanical stresses and that the optimum storage capacitor for the Greinacher circuit is much smaller than that for the standard circuit, while the total harvested energy by both configurations is similar.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-12
DOI: 10.3390/jlpea13010008
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 9: Acknowledgment to the Reviewers of Journal of Low
Power Electronics and Applications in 2022
Authors: JLPEA Editorial Office JLPEA Editorial Office
First page: 9
Abstract: High-quality academic publishing is built on rigorous peer review [...]
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-16
DOI: 10.3390/jlpea13010009
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 10: A Power-Efficient Neuromorphic Digital
Implementation of Neural–Glial Interactions
Authors: Angeliki Bicaku, Maria Sapounaki, Athanasios Kakarountas, Sotiris K. Tasoulis
First page: 10
Abstract: Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate area- and power-efficient circuits. Motivated by studies that outline the indispensable role of astrocytes in the dynamic regulation of synaptic transmission and their active contribution to neural information processing in the CNS, in this work we propose a digital implementation of neuron–astrocyte bidirectional interactions. In order to describe the neuronal dynamics and the astrocytes’ calcium dynamics, a modified version of the original Izhikevich neuron model was combined with a linear approximation of the Postnov functional neural–glial interaction model. For the implementation of the neural–glial computation core, only three pipeline stages and a 10.10 fixed point representation were utilized. Regarding the results obtained from the FPGA implementation and the comparisons to other works, the proposed neural–glial circuit reported significant savings in area requirements (from 22.53% up to 164.20%) along with considerable savings in total power consumption of 28.07% without sacrificing output computation accuracy. Finally, an RMSE analysis was conducted, confirming that this particular implementation produces more accurate results compared to previous studies.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-18
DOI: 10.3390/jlpea13010010
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 11: Study of Nitrogen-Doped Carbon Nanotubes for
Creation of Piezoelectric Nanogenerator
Authors: Marina V. Il’ina, Olga I. Soboleva, Soslan A. Khubezov, Vladimir A. Smirnov, Oleg I. Il’in
First page: 11
Abstract: The creation of sustainable power sources for wearable electronics and self-powered systems is a promising direction of modern electronics. At the moment, a search for functional materials with high values of piezoelectric coefficient and elasticity, as well as non-toxicity, is underway to generate such power sources. In this paper, nitrogen-doped carbon nanotubes (N-CNTs) are considered as a functional material for a piezoelectric nanogenerator capable of converting nanoscale deformations into electrical energy. The effect of defectiveness and of geometric and mechanical parameters of N-CNTs on the current generated during their deformation is studied. It was established that the piezoelectric response of N-CNTs increased nonlinearly with an increase in the Young’s modulus and the aspect ratio of the length to diameter of the nanotube and, on the contrary, decreased with an increase in defectiveness not caused by the incorporation of nitrogen atoms. The advantages of using N-CNT to create energy-efficient piezoelectric nanogenerators are shown.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-01-22
DOI: 10.3390/jlpea13010011
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 12: Energy Autonomous Wireless Sensing Node Working
at 5 Lux from a 4 cm2 Solar Cell
Authors: Marcel Louis Meli, Sebastien Favre, Benjamin Maij, Stefan Stajic, Manuel Boebel, Philip John Poole, Martin Schellenberg, Charalampos S. Kouzinopoulos
First page: 12
Abstract: Harvesting energy for IoT nodes in places that are permanently poorly lit is important, as many such places exist in buildings and other locations. The need for energy-autonomous devices working in such environments has so far received little attention. This work reports the design and test results of an energy-autonomous sensor node powered solely by solar cells. The system can cold-start and run in low light conditions (in this case 20 lux and below, using white LEDs as light sources). Four solar cells of 1 cm2 each are used, yielding a total active surface of 4 cm2. The system includes a capacitive sensor that acts as a touch detector, a crystal-accurate real-time clock (RTC), and a Cortex-M3-compatible microcontroller integrating a Bluetooth Low Energy radio (BLE) and the necessary stack for communication. A capacitor of 100 μF is used as energy storage. A low-power comparator monitors the level of the energy storage and powers up the system. The combination of the RTC and touch sensor enables the MCU load to be powered up periodically or using an asynchronous user touch activity. First tests have shown that the system can perform the basic work of cold-starting, sensing, and transmitting frames at +0 dBm, at illuminances as low as 5 lux. Harvesting starts earlier, meaning that the potential for full function below 5 lux is present. The system has also been tested with other light sources. The comparator is a test chip developed for energy harvesting. Other elements are off-the-shelf components. The use of commercially available devices, the reduced number of parts, and the absence of complex storage elements enable a small node to be built in the future, for use in constantly or intermittently poorly lit places.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-01
DOI: 10.3390/jlpea13010012
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 13: Minimum Active Component Count Design of a
PIλDμ Controller and Its Application in a Cardiac Pacemaker
System
Authors: Julia Nako, Costas Psychalinos, Ahmed S. Elwakil
First page: 13
Abstract: A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as the Foster and Cauer networks. The main offered benefit, with regards to the corresponding convectional implementations, is the reduced active and, also, passive component count. To demonstrate the versatility of the proposed concept, a controller suitable for implementing a cardiac pacemaker control system is designed. The evaluation of the performance of the system is performed through circuit simulation results, using a second-generation voltage conveyor as the active element.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-02
DOI: 10.3390/jlpea13010013
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 14: Wideband Cascaded and Stacked Receiver
Front-Ends Employing an Improved Clock-Strategy Technique
Authors: Arash Abbasi, Frederic Nabki
First page: 14
Abstract: A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-02
DOI: 10.3390/jlpea13010014
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 15: A 1.1 V 25 ppm/°C Relaxation Oscillator with
0.045%/V Line Sensitivity for Low Power Applications
Authors: Yizhuo Liao, Pak Kwong Chan
First page: 15
Abstract: A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-07
DOI: 10.3390/jlpea13010015
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 16: Exploring Topological Semi-Metals for
Interconnects
Authors: Satwik Kundu, Rupshali Roy, M. Saifur Rahman, Suryansh Upadhyay, Rasit Onur Topaloglu, Suzanne E. Mohney, Shengxi Huang, Swaroop Ghosh
First page: 16
Abstract: The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-09
DOI: 10.3390/jlpea13010016
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 17: Decoding Algorithms and HW Strategies to
Mitigate Uncertainties in a PCM-Based Analog Encoder for Compressed
Sensing
Authors: Carmine Paolino, Alessio Antolini, Francesco Zavalloni, Andrea Lico, Eleonora Franchi Scarselli, Mauro Mangia, Alex Marchioni, Fabio Pareschi, Gianluca Setti, Riccardo Rovatti, Mattia Luigi Torres, Marcella Carissimi, Marco Pasotti
First page: 17
Abstract: Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. The same concept can be readily applied to the encoding stage in Compressed Sensing (CS) systems, where an MVM operation maps input signals into compressed measurements. With a focus on an encoder built on top of a Phase-Change Memory (PCM) AIMC platform, the effects of device non-idealities, namely programming spread and drift over time, are observed in terms of the reconstruction quality obtained for synthetic signals, sparse in the Discrete Cosine Transform (DCT) domain. PCM devices are simulated using statistical models summarizing the properties experimentally observed in an AIMC prototype, designed in a 90 nm STMicroelectronics technology. Different families of decoders are tested, and tradeoffs in terms of encoding energy are analyzed. Furthermore, the benefits of a hardware drift compensation strategy are also observed, highlighting its necessity to prevent the need for a complete reprogramming of the entire analog array. The results show >30 dB average reconstruction quality for mid-range conductances and a suitably selected decoder right after programming. Additionally, the hardware drift compensation strategy enables robust performance even when different drift conditions are tested.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-13
DOI: 10.3390/jlpea13010017
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 18: Self-Parameterized Chaotic Map for Low-Cost
Robust Chaos
Authors: Partha Sarathi Paul, Anurag Dhungel, Maisha Sadia, Md Razuan Hossain, Md Sakib Hasan
First page: 18
Abstract: This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-13
DOI: 10.3390/jlpea13010018
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 19: Radio-Frequency Energy Harvesting Using Rapid 3D
Plastronics Protoyping Approach: A Case Study
Authors: Xuan Viet Linh Nguyen, Tony Gerges, Pascal Bevilacqua, Jean-Marc Duchamp, Philippe Benech, Jacques Verdier, Philippe Lombard, Pangsui Usifu Linge, Fabien Mieyeville, Michel Cabrera, Bruno Allard
First page: 19
Abstract: Harvesting of ambient radio-frequency energy is largely covered in the literature. The RF energy harvester is considered most of the time as a standalone board. There is an interest to add the RF harvesting function on an already-designed object. Polymer objects are considered here, manufactured through an additive process and the paper focuses on the rapid prototyping of the harvester using a plastronic approach. An array of four antennas is considered for circular polarization with high self-isolation. The RF circuit is obtained using an electroless copper metallization of the surface of a 3D substrate fabricated using stereolithography printing. The RF properties of the polymer resin are not optimal; thus, the interest of this work is to investigate the potential capabilities of such an implementation, particularly in terms of freedom of 3D design and ease of fabrication. The electromagnetic properties of the substrate are characterized over a band of 0.5–2.5 GHz applying the two-transmission-line method. A circular polarization antenna is experimented as a rapid prototyping vehicle and yields a gain of 1.26 dB. A lab-scale prototype of the rectifier and power management unit are experimented with discrete components. The cold start-up circuit accepts a minimum voltage of 180 mV. The main DC/DC converter operates under 1.4 V but is able to compensate losses for an input DC voltage as low as 100 mV (10 μW). The rectifier alone is capable of 3.5% efficiency at −30 dBm input RF power. The global system of circularly polarized antenna, rectifier, and voltage conversion features a global experimental efficiency of 14.7% at an input power of −13.5 dBm. The possible application of such results is discussed.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-02-17
DOI: 10.3390/jlpea13010019
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 20: Efficient Dual Output Regulating Rectifier and
Adiabatic Charge Pump for Biomedical Applications Employing Wireless Power
Transfer
Authors: Noora Almarri, Peter Langlois, Dai Jiang, Andreas Demosthenous
First page: 20
Abstract: A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-04
DOI: 10.3390/jlpea13010020
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 21: DycSe: A Low-Power, Dynamic Reconfiguration
Column Streaming-Based Convolution Engine for Resource-Aware Edge AI
Accelerators
Authors: Weison Lin, Yajun Zhu, Tughrul Arslan
First page: 21
Abstract: Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator brings a customized design to meet the requirements of the edge environment. The requirements include real-time processing, low-power consumption, and resource-awareness, including resources on field programmable gate array (FPGA) or limited application-specific integrated circuit (ASIC) area. The system’s reliability (e.g., permanent fault tolerance) is essential if the devices target radiation fields such as space and nuclear power stations. This paper proposes a dynamic reconfigurable column streaming-based convolution engine (DycSe) with programmable adder modules for low-power and resource-aware edge AI accelerators to meet the requirements. The proposed DycSe design does not target the FPGA platform only. Instead, it is an intellectual property (IP) core design. The FPGA platform used in this paper is for prototyping the design evaluation. This paper uses the Vivado synthesis tool to evaluate the power consumption and resource usage of DycSe. Since the synthesis tool is limited to giving the final complete system result in the designing stage, we compare DycSe to a commercial edge AI accelerator for cross-reference with other state-of-the-art works. The commercial architecture shares the competitive performance within the low-power ultra-small (LPUS) edge AI scopes. The result shows that DycSe contains 3.56% less power consumption and slight resources (1%) overhead with reconfigurable flexibility.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-16
DOI: 10.3390/jlpea13010021
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 22: Extreme Path Delay Estimation of Critical Paths
in Within-Die Process Fluctuations Using Multi-Parameter Distributions
Authors: Miikka Runolinna, Matthew Turnquist, Jukka Teittinen, Pauliina Ilmonen, Lauri Koskinen
First page: 22
Abstract: Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distributions outperform the normal distribution in goodness-of-fit statistics for simulated path delay data derived from a fabricated microcontroller, with the six-term metalog distribution offering the best fit. Furthermore, 99.7% confidence intervals are calculated for some extreme quantiles on each dataset using the previous distributions. Considering the six-term metalog distribution estimates as the golden standard, the relative errors in single paths vary between 4 and 14% for the normal distribution. Finally, the within-die (WID) variation maximum critical path delay distribution for multiple critical paths is derived under the assumption of independence between the paths. Its density function is then used to compute different maximum delays for varying numbers of critical paths, assuming each path has one of the previous distributions with the metalog estimates as the golden standard. For 100 paths, the relative errors are at most 14% for the normal distribution. With 1000 and 10,000 paths, the corresponding errors extend up to 16 and 19%, respectively.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2023-03-20
DOI: 10.3390/jlpea13010022
Issue No: Vol. 13, No. 1 (2023)
- JLPEA, Vol. 13, Pages 1: CCALK: (When) CVA6 Cache Associativity Leaks the
Key
Authors: Valentin Martinoli, Elouan Tourneur, Yannick Teglia, Régis Leveugle
First page: 1
Abstract: In this work, we study an end-to-end implementation of a Prime + Probe covert channel on the CVA6 RISC-V processor implemented on a FPGA target and running a Linux OS. We develop the building blocks of the covert channel and provide a detailed view of its behavior and effectiveness. We propose a realistic scenario for extracting information of an AES-128 encryption algorithm implementation. Throughout this work, we discuss the challenges brought by the presence of a running OS while carrying out a micro architectural covert channel. This includes the effects of having other running processes, unwanted cache evictions and the OS’ timing behavior. We also propose an analysis of the relationship between the data cache’s characteristics and the developed covert channel’s capacity to extract information. According to the results of our experimentations, we present guidelines on how to build and configure a micro architectural covert channel resilient cache in a mono-core mono-thread scenario.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-12-27
DOI: 10.3390/jlpea13010001
Issue No: Vol. 13, No. 1 (2022)
- JLPEA, Vol. 13, Pages 2: Evaluation of Dynamic Triple Modular Redundancy
in an Interleaved-Multi-Threading RISC-V Core
Authors: Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi, Mauro Olivieri
First page: 2
Abstract: Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-12-28
DOI: 10.3390/jlpea13010002
Issue No: Vol. 13, No. 1 (2022)
- JLPEA, Vol. 13, Pages 3: A Fully-Differential CMOS Instrumentation
Amplifier for Bioimpedance-Based IoT Medical Devices
Authors: Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo
First page: 3
Abstract: The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal and feed back the output signal, a summing stage, used to add both contributions and generate the correcting current feedback signal, and a common-mode feedback network, which controls the DC level at the output nodes of the circuit. The transconductors are formed by a voltage-to-current conversion resistor and two voltage buffers, which are based on a super source follower cell in order to improve the overall response of the circuit. As a result, a compact single-stage structure, suitable for achieving a high bandwidth and a low power consumption, is obtained. The FD ICF IA has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply and provide a nominal gain of 4 V/V. Experimental results show a voltage gain of 3.78 ± 0.06 V/V, a BW of 5.83 MHz, a CMRR at DC around 70 dB, a DC current consumption of 266.4 μA and a silicon area occupation of 0.0304 mm2.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-12-30
DOI: 10.3390/jlpea13010003
Issue No: Vol. 13, No. 1 (2022)
- JLPEA, Vol. 12, Pages 49: Designing Energy-Efficient Approximate
Multipliers
Authors: Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
First page: 49
Abstract: This paper proposes a novel approach suitable to design energy-efficient approximate multipliers using both ASIC and FPGAs. The new strategy harnesses specific encoding logics based on bit significance and computes the approximate product performing accurate sub-multiplications by applying an unconventional approach instead of using approximate computational modules implementing traditional static or dynamic bit-truncation approaches. The proposed platform-independent architecture exhibits an energy saving of up to 80% over the accurate counterparts and significantly better behavior in terms of accuracy loss with respect to competitor approximate architectures. When employed in 2D digital filters and edge detectors, the novel approximate multipliers lead to an energy consumption up to ~82% lower than the accurate counterparts, which is up to ~2 times higher than that obtained by state-of-the-art competitors.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-09-27
DOI: 10.3390/jlpea12040049
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 50: FAC-V: An FPGA-Based AES Coprocessor for RISC-V
Authors: Tiago Gomes, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, Sandro Pinto
First page: 50
Abstract: In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-09-27
DOI: 10.3390/jlpea12040050
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 51: BIoU: An Improved Bounding Box Regression for
Object Detection
Authors: Niranjan Ravi, Sami Naqvi, Mohamed El-Sharkawy
First page: 51
Abstract: Object detection is a predominant challenge in computer vision and image processing to detect instances of objects of various classes within an image or video. Recently, a new domain of vehicular platforms, e-scooters, has been widely used across domestic and urban environments. The driving behavior of e-scooter users significantly differs from other vehicles on the road, and their interactions with pedestrians are also increasing. To ensure pedestrian safety and develop an efficient traffic monitoring system, a reliable object detection system for e-scooters is required. However, existing object detectors based on IoU loss functions suffer various drawbacks when dealing with densely packed objects or inaccurate predictions. To address this problem, a new loss function, balanced-IoU (BIoU), is proposed in this article. This loss function considers the parameterized distance between the centers and the minimum and maximum edges of the bounding boxes to address the localization problem. With the help of synthetic data, a simulation experiment was carried out to analyze the bounding box regression of various losses. Extensive experiments have been carried out on a two-stage object detector, MASK_RCNN, and single-stage object detectors such as YOLOv5n6, YOLOv5x on Microsoft Common Objects in Context, SKU110k, and our custom e-scooter dataset. The proposed loss function demonstrated an increment of 3.70% at APS on the COCO dataset, 6.20% at AP55 on SKU110k, and 9.03% at AP80 of the custom e-scooter dataset.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-09-28
DOI: 10.3390/jlpea12040051
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 52: Advanced Embedded System Modeling and Simulation
in an Open Source RISC-V Virtual Prototype
Authors: Pascal Pieper, Vladimir Herdt, Rolf Drechsler
First page: 52
Abstract: RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been introduced into the RISC-V ecosystem to lay the foundation for advanced industry-proven system-level use-cases. However, VP-driven environment modeling and interaction have mostly been neglected in the RISC-V context. In this paper, we propose such an extension to broaden the application domain for virtual prototyping in the RISC-V context. As a foundation, we built upon the open source RISC-V VP available at GitHub. For a visualization of the environment purposes, we designed a Graphical User Interface (GUI) and designed appropriate libraries to offer hardware communication interfaces such as GPIO and SPI from the VP to an interactive environment model. Our approach is designed to be integrated with SystemC-based VPs that leverage a Transaction-Level Modeling (TLM) communication system to prefer a speed-optimized simulation. To show the practicability of an environment model, we provide a set of building blocks such as buttons, LEDs and an OLED display and configured them in two demonstration environments. Moreover, for rapid prototyping purposes, we provide a modeling layer that leverages the dynamic Lua scripting language to design components and integrate them with the VP-based simulation. Our evaluation with two different case-studies demonstrates the applicability of our approach in building virtual environments effectively and correctly when matching the real physical systems. To advance the RISC-V community and stimulate further research, we provide our extended VP platform with the environment configuration and visualization toolbox, as well as both case-studies as open source on GitHub.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-09-29
DOI: 10.3390/jlpea12040052
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 53: Multi-Objective Resource Scheduling for IoT
Systems Using Reinforcement Learning
Authors: Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
First page: 53
Abstract: IoT embedded systems have multiple objectives that need to be maximized simultaneously. These objectives conflict with each other due to limited resources and tradeoffs that need to be made. This requires multi-objective optimization (MOO) and multiple Pareto-optimal solutions are possible. In such a case, tradeoffs are made w.r.t. a user-defined preference. This work presents a general Multi-objective Reinforcement Learning (MORL) framework for MOO of IoT embedded systems. This framework comprises a general Multi-objective Markov Decision Process (MOMDP) formulation and two novel low-compute MORL algorithms. The algorithms learn policies to tradeoff between multiple objectives using a single preference parameter. We take the energy scheduling problem in general Energy Harvesting Wireless Sensor Nodes (EHWSNs) as a case example in which a sensor node is required to maximize its sensing rate, and transmission performance as well as ensure long-term uninterrupted operation within a very tight energy budget. We simulate single-task and dual-task EHWSN systems to evaluate our framework.. The results demonstrate that our MORL algorithms can learn better policies at lower learning costs and successfully tradeoff between multiple objectives at runtime.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-10-08
DOI: 10.3390/jlpea12040053
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 54: Intelligent Control of Seizure-Like Activity in
Authors: Wallace Moreira Bessa, Gabriel da Silva Lima
First page: 54
Abstract: Memristive neuromorphic systems represent one of the most promising technologies to overcome the current challenges faced by conventional computer systems. They have recently been proposed for a wide variety of applications, such as nonvolatile computer memory, neuroprosthetics, and brain–machine interfaces. However, due to their intrinsically nonlinear characteristics, they present a very complex dynamic behavior, including self-sustained oscillations, seizure-like events, and chaos, which may compromise their use in closed-loop systems. In this work, a novel intelligent controller is proposed to suppress seizure-like events in a memristive circuit based on the Hodgkin–Huxley equations. For this purpose, an adaptive neural network is adopted within a Lyapunov-based nonlinear control scheme to attenuate bursting dynamics in the circuit, while compensating for modeling uncertainties and external disturbances. The boundedness and convergence properties of the proposed control scheme are rigorously proved by means of a Lyapunov-like stability analysis. The obtained results confirm the effectiveness of the proposed intelligent controller, presenting a much improved performance when compared with a conventional nonlinear control scheme.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-10-12
DOI: 10.3390/jlpea12040054
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 55: Direct-Grown Helical-Shaped Tungsten-Oxide-Based
Devices with Reconfigurable Selectivity for Memory Applications
Authors: Ying-Chen Chen, Yi-Fu Huang, Sumant Sarkar, John Gibbs, Jack Lee
First page: 55
Abstract: In this study, a direct-grown helical-shaped tungsten-oxide-based (h-WOx) selection device is presented for emerging memory applications. The selectivity in the selection devices is from 10 to 103 with a low off-current of 0.1 to 0.01 nA. In addition, the selectivity of volatile switching in the h-WOx selection devices is reconfigurable with a pseudo RESET process on the one-time negative voltage operations. The helical-shaped selection devices with the glancing angle deposition (GLAD) method show good compatibility, low power consumption, good selectivity, and good reconfigurability for next-generation memory applications.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-10-15
DOI: 10.3390/jlpea12040055
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 56: Templatized Fused Vector Floating-Point Dot
Product for High-Level Synthesis
Authors: Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
First page: 56
Abstract: Machine-learning accelerators rely on floating-point matrix and vector multiplication kernels. To reduce their cost, customized many-term fused architectures are preferred, which improve the latency, power, and area of the designs. In this work, we design a parameterized fused many-term floating-point dot product architecture that is ready for high-level synthesis. In this way, we can exploit the efficiency offered by a well-structured fused dot-product architecture and the freedom offered by high-level synthesis in tuning the design’s pipeline to the selected floating-point format and architectural constraints. When compared with optimized dot-product units implemented directly in RTL, the proposed design offers lower-latency implementations under the same clock frequency with marginal area savings. This result holds for a variety of floating-point formats, including standard and reduced-precision representations.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-10-17
DOI: 10.3390/jlpea12040056
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 57: Ocelli: Efficient Processing-in-Pixel Array
Enabling Edge Inference of Ternary Neural Networks
Authors: Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi
First page: 57
Abstract: Convolutional Neural Networks (CNNs), due to their recent successes, have gained lots of attention in various vision-based applications. They have proven to produce incredible results, especially on big data, that require high processing demands. However, CNN processing demands have limited their usage in embedded edge devices with constrained energy budgets and hardware. This paper proposes an efficient new architecture, namely Ocelli includes a ternary compute pixel (TCP) consisting of a CMOS-based pixel and a compute add-on. The proposed Ocelli architecture offers several features; (I) Because of the compute add-on, TCPs can produce ternary values (i.e., −1, 0, +1) regarding the light intensity as pixels’ inputs; (II) Ocelli realizes analog convolutions enabling low-precision ternary weight neural networks. Since the first layer’s convolution operations are the performance bottleneck of accelerators, Ocelli mitigates the overhead of analog buffers and analog-to-digital converters. Moreover, our design supports a zero-skipping scheme to further power reduction; (III) Ocelli exploits non-volatile magnetic RAMs to store CNN’s weights, which remarkably reduces the static power consumption; and finally, (IV) Ocelli has two modes, including sensing and processing. Once the object is detected, the architecture switches to the typical sensing mode to capture the image. Compared to the conventional pixels, it achieves an average 10% efficiency on its lane detection power consumption compared with existing edge detection algorithms. Moreover, considering different CNN workloads, our design shows more than 23% power efficiency over conventional designs, while it can achieve better accuracy.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-10-30
DOI: 10.3390/jlpea12040057
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 58: Tunnel Field-Effect Transistor: Iimpact of the
Asymmetric and Symmetric Ambipolarity on Fault and Performance in Digital
Circuits
Authors: Chiara Elfi Spano, Fabrizio Mo, Roberta Antonina Claudino, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, Marco Vacca
First page: 58
Abstract: Tunnel Field-Effect Transistors (TFETs) have been considered one of the most promising technologies to complement or replace CMOS for ultra-low-power applications, thanks to their subthreshold slope below the well-known limit of 60 mV/dec at room temperature holding for the MOSFET technologies. Nevertheless, TFET technology still suffers of ambipolar conduction, limiting its applicability in digital systems. In this work, we analyze through SPICE simulations, the impact of the symmetric and asymmetric ambipolarity in failure and power consumption for TFET-based complementary logic circuits. Our results clarify the circuit-level effects induced by the ambipolarity feature, demonstrating that it affects the correct functioning of logic gates and strongly impacts power consumption. We believe that our outcomes motivate further research towards technological solutions for ambipolarity suppression in TFET technology for near-future ultra-low-power applications.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-10-31
DOI: 10.3390/jlpea12040058
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 59: Towards Low-Power Machine Learning Architectures
Inspired by Brain Neuromodulatory Signalling
Authors: Taylor Barton, Hao Yu, Kyle Rogers, Nancy Fulda, Shiuh-hua Wood Chiang, Jordan Yorgason, Karl F. Warnick
First page: 59
Abstract: We present a transfer learning method inspired by modulatory neurotransmitter mechanisms in biological brains and explore applications for neuromorphic hardware. In this method, the pre-trained weights of an artificial neural network are held constant and a new, similar task is learned by manipulating the firing sensitivity of each neuron via a supplemental bias input. We refer to this as neuromodulatory tuning (NT). We demonstrate empirically that neuromodulatory tuning produces results comparable with traditional fine-tuning (TFT) methods in the domain of image recognition in both feed-forward deep learning and spiking neural network architectures. In our tests, NT reduced the number of parameters to be trained by four orders of magnitude as compared with traditional fine-tuning methods. We further demonstrate that neuromodulatory tuning can be implemented in analog hardware as a current source with a variable supply voltage. Our analog neuron design implements the leaky integrate-and-fire model with three bi-directional binary-scaled current sources comprising the synapse. Signals approximating modulatory neurotransmitter mechanisms are applied via adjustable power domains associated with each synapse. We validate the feasibility of the circuit design using high-fidelity simulation tools and propose an efficient implementation of neuromodulatory tuning using integrated analog circuits that consume significantly less power than digital hardware (GPU/CPU).
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-11-04
DOI: 10.3390/jlpea12040059
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 60: Ultra-Low-Power Circuits for Intermittent
Communication
Authors: Alessandro Torrisi, Kasım Sinan Yıldırım, Davide Brunelli
First page: 60
Abstract: Self-sustainable energy harvesting for Internet of Things devices is challenging since ambient energy may be sporadic and unpredictable. This situation leads to frequent power failures that lead to intermittent operations, which prevent the reliability of data communications. This article presents fundamental hardware circuitry that enables reliable intermittent communications over wireless batteryless node networks. We emphasize two main mechanisms that ensure energy awareness and reliability: energy status-sharing and synchronized operation. We introduce novel low-power and self-sustainable plug-and-play circuits to support these mechanisms.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-11-13
DOI: 10.3390/jlpea12040060
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 61: Hardware Solutions for Low-Power Smart Edge
Computing
Authors: Lucas Martin Wisniewski, Jean-Michel Bec, Guillaume Boguszewski, Abdoulaye Gamatié
First page: 61
Abstract: The edge computing paradigm for Internet-of-Things brings computing closer to data sources, such as environmental sensors and cameras, using connected smart devices. Over the last few years, research in this area has been both interesting and timely. Typical services like analysis, decision, and control, can be realized by edge computing nodes executing full-fledged algorithms. Traditionally, low-power smart edge devices have been realized using resource-constrained systems executing machine learning (ML) algorithms for identifying objects or features, making decisions, etc. Initially, this paper discusses recent advances in embedded systems that are devoted to energy efficient ML algorithm execution. A survey of the mainstream embedded computing devices for low power IoT and edge computing is then presented. Finally, CYSmart is introduced as an innovative smart edge computing system. Two operational use cases are presented to illustrate its power efficiency.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-11-25
DOI: 10.3390/jlpea12040061
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 62: 0.6-V 1.65-μW Second-Order Gm-C Bandpass
Filter for Multi-Frequency Bioimpedance Analysis Based on a Bootstrapped
Bulk-Driven Voltage Buffer
Authors: Juan M. Carrillo, Carlos A. de la Cruz-Blas
First page: 62
Abstract: A bootstrapping technique used to increase the intrinsic voltage gain of a bulk-driven MOS transistor is described in this paper. The proposed circuit incorporates a capacitor and a cutoff transistor to be connected to the gate terminal of a bulk-driven MOS device, thus achieving a quasi-floating-gate structure. As a result, the contribution of the gate transconductance is cancelled out and the voltage gain of the device is correspondingly increased. The technique allows for implementing a voltage follower with a voltage gain much closer to unity as compared to the conventional bulk-driven case. This voltage buffer, along with a pseudo-resistor, is used to design a linearized transconductor. The proposed transconductance cell includes an economic continuous tuning mechanism that permits programming the effective transconductance in a range sufficiently wide to counteract the typical variations that process parameters suffer during fabrication. The transconductor has been used to implement a second-order Gm-C bandpass filter with a relatively high selectivity factor, suited for multi-frequency bioimpedance analysis in a very low-voltage environment. All the circuits have been designed in 180 nm CMOS technology to operate with a 0.6-V single-supply voltage. Simulated results show that the proposed technique allows for increasing the linearity and reducing the input-referred noise of the bootstrapped bulk-driven MOS transistor, which results in an improvement of the overall performance of the transconductor. The center frequency of the bandpass filter designed can be programmed in the frequency range from 6.5 kHz to 37.5 kHz with a power consumption ranging between 1.34 μW and 2.19 μW. The circuit presents an in-band integrated noise of 190.5 μVrms and is able to process signals of 110 mVpp with a THD below −40 dB, thus leading to a dynamic range of 47.4 dB.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-11-30
DOI: 10.3390/jlpea12040062
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 63: A Spintronic 2M/7T Computation-in-Memory Cell
Authors: Atousa Jafari, Christopher Münch, Mehdi Tahoori
First page: 63
Abstract: Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-12-06
DOI: 10.3390/jlpea12040063
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 64: All-Standard-Cell-Based Analog-to-Digital
Architectures Well-Suited for Internet of Things Applications
Authors: Ana Correia, Vítor Grade Tavares, Pedro Barquinha, João Goes
First page: 64
Abstract: In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-12-07
DOI: 10.3390/jlpea12040064
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 65: Energy Sustainability in Wireless Sensor
Networks: An Analytical Survey
Authors: Emmanouil Andreas Evangelakos, Dionisis Kandris, Dimitris Rountos, George Tselikis, Eleftherios Anastasiadis
First page: 65
Abstract: Wireless Sensor Networks (WSNs) are considered to be among the most important scientific domains. Yet, the exploitation of WSNs suffers from the severe energy restrictions of their electronic components. For this reason there are numerous scientific methods that have been proposed aiming to achieve the extension of the lifetime of WSNs, either by energy saving or energy harvesting or through energy transfer. This study aims to analytically examine all of the existing hardware-based and algorithm-based mechanisms of this kind. The operating principles of 48 approaches are studied, their relative advantages and weaknesses are highlighted, open research issues are discussed, and resultant concluding remarks are drawn.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-12-16
DOI: 10.3390/jlpea12040065
Issue No: Vol. 12, No. 4 (2022)
- JLPEA, Vol. 12, Pages 35: ±0.3V Bulk-Driven Fully Differential
Buffer with High Figures of Merit
Authors: Manaswini Gangineni, Jaime Ramirez-Angulo, Héctor Vázquez-Leal, Jesús Huerta-Chua, Antonio J. Lopez-Martin, Ramon Gonzalez Carvajal
First page: 35
Abstract: A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOMSS = 12.69 MHzpFμW−1, a large signal figure of merit FOMLS = 34.89 (V/μs) pFμW−1, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-06-22
DOI: 10.3390/jlpea12030035
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 36: Performance Estimation of High-Level Dataflow
Program on Heterogeneous Platforms by Dynamic Network Execution
Authors: Aurelien Bloch, Simone Casale-Brunet, Marco Mattavelli
First page: 36
Abstract: The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters that define the partitioning, mapping, scheduling, and allocation of data exchanges among the various processing elements of the platform executing the program. The advantage of programs written in languages using the dataflow model of computation (MoC) is that executing the program with different configurations and parameter settings does not require rewriting the application software for each configuration setting, but only requires generating a new synthesis of the execution code corresponding to different parameters. The synthesis stage of dataflow programs is usually supported by automatic code generation tools. Another competitive advantage of dataflow software methodologies is that they are well-suited to support designs on heterogeneous parallel systems as they are inherently free of memory access contention issues and naturally expose the available intrinsic parallelism. So as to fully exploit these advantages and to be able to efficiently search the configuration space to find the design points that better satisfy the desired design constraints, it is necessary to develop tools and associated methodologies capable of evaluating the performance of different configurations and to drive the search for good design configurations, according to the desired performance criteria. The number of possible design assumptions and associated parameter settings is usually so large (i.e., the dimensions and size of the design space) that intuition as well as trial and error are clearly unfeasible, inefficient approaches. This paper describes a method for the clock-accurate profiling of software applications developed using the dataflow programming paradigm such as the formal RVL-CAL language. The profiling can be applied when the application program has been compiled and executed on GPU/CPU heterogeneous hardware platforms utilizing two main methodologies, denoted as static and dynamic. This paper also describes how a method for the qualitative evaluation of the performance of such programs as a function of the supplied configuration parameters can be successfully applied to heterogeneous platforms. The technique was illustrated using two different application software examples and several design points.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-06-23
DOI: 10.3390/jlpea12030036
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 37: Deep Learning Approaches to Source Code Analysis
for Optimization of Heterogeneous Systems: Recent Results, Challenges and
Opportunities
Authors: Francesco Barchi, Emanuele Parisi, Andrea Bartolini, Andrea Acquaviva
First page: 37
Abstract: To cope with the increasing complexity of digital systems programming, deep learning techniques have recently been proposed to enhance software deployment by analysing source code for different purposes, ranging from performance and energy improvement to debugging and security assessment. As embedded platforms for cyber-physical systems are characterised by increasing heterogeneity and parallelism, one of the most challenging and specific problems is efficiently allocating computational kernels to available hardware resources. In this field, deep learning applied to source code can be a key enabler to face this complexity. However, due to the rapid development of such techniques, it is not easy to understand which of those are suitable and most promising for this class of systems. For this purpose, we discuss recent developments in deep learning for source code analysis, and focus on techniques for kernel mapping on heterogeneous platforms, highlighting recent results, challenges and opportunities for their applications to cyber-physical systems.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-07-05
DOI: 10.3390/jlpea12030037
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 38: Analysis and Comparison of Different Approaches
to Implementing a Network-Based Parallel Data Processing Algorithm
Authors: Iouliia Skliarova
First page: 38
Abstract: It is well known that network-based parallel data processing algorithms are well suited to implementation in reconfigurable hardware recurring to either Field-Programmable Gate Arrays (FPGA) or Programmable Systems-on-Chip (PSoC). The intrinsic parallelism of these devices makes it possible to execute several data-independent network operations in parallel. However, the approaches to designing the respective systems vary significantly with the experience and background of the engineer in charge. In this paper, we analyze and compare the pros and cons of using an embedded processor, high-level synthesis methods, and register-transfer low-level design in terms of design effort, performance, and power consumption for implementing a parallel algorithm to find the two smallest values in a dataset. This problem is easy to formulate, has a number of practical applications (for instance, in low-density parity check decoders), and is very well suited to parallel implementation based on comparator networks.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-07-09
DOI: 10.3390/jlpea12030038
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 39: Efficiency of Priority Queue Architectures in
FPGA
Authors: Lukáš Kohútka
First page: 39
Abstract: This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, is optimized for minimum chip area costs, which leads to lower energy consumption too. The MultiQueue architecture has constant time complexity, constant critical path length and constant latency. Therefore, it is highly predictable and very suitable for real-time systems too. The proposed architecture was verified using a simplified version of UVM and applying millions of instructions with randomly generated input values. Achieved FPGA synthesis results are presented and discussed. These results show significant savings in FPGA Look-Up Tables consumption in comparison to existing solutions. More than 63% of Look-Up Tables can be saved using the MultiQueue architecture instead of the existing priority queues.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-07-14
DOI: 10.3390/jlpea12030039
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 40: Dynamic SIMD Parallel Execution on GPU from
High-Level Dataflow Synthesis
Authors: Aurelien Bloch, Simone Casale-Brunet, Marco Mattavelli
First page: 40
Abstract: Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental components and features of both the design and of the platform to maximize the overall performance. The dataflow programming approach has proven to be an appropriate methodology for reaching such a difficult and complex goal for the intrinsic portability and the possibility of easily decomposing a network of actors on different processing units of the heterogeneous hardware. Nonetheless, such a design method might not be enough on its own to achieve the desired performance goals, and supporting tools are useful to be able to efficiently explore the design space so as to optimize the desired performance objectives. This article presents a methodology composed of several stages for enhancing the performance of dataflow software developed in RVC-CAL and generating low-level implementations to be executed on GPU/CPU heterogeneous hardware platforms. The stages are composed of a method for the efficient scheduling of parallel CUDA partitions, an optimization of the performance of the data transmission tasks across computing kernels, and the exploitation of dynamic programming for introducing SIMD-capable graphics processing unit systems. The methodology is validated on both the quantitative and qualitative side by means of dataflow software application examples running on platforms according to various different mapping configurations.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-07-17
DOI: 10.3390/jlpea12030040
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 41: Electrical Impedance Tomography for Hand Gesture
Recognition for HMI Interaction Applications
Authors: Noelia Vaquero-Gallardo, Herminio Martínez-García
First page: 41
Abstract: Electrical impedance tomography (EIT) is based on the physical principle of bioimpedance defined as the opposition that biological tissues exhibit to the flow of a rotating alternating electrical current. Consequently, here, we propose studying the characterization and classification of bioimpedance patterns based on EIT by measuring, on the forearm with eight electrodes in a non-invasive way, the potential drops resulting from the execution of six hand gestures. The starting point was the acquisition of bioimpedance patterns studied by means of principal component analysis (PCA), validated through the cross-validation technique, and classified using the k-nearest neighbor (kNN) classification algorithm. As a result, it is concluded that reduction and classification is feasible, with a sensitivity of 0.89 in the worst case, for each of the reduced bioimpedance patterns, leading to the following direct advantage: a reduction in the numbers of electrodes and electronics required. In this work, bioimpedance patterns were investigated for monitoring subjects’ mobility, where, generally, these solutions are based on a sensor system with moving parts that suffer from significant problems of wear, lack of adaptability to the patient, and lack of resolution. Whereas, the proposal implemented in this prototype, based on the so-called electrical impedance tomography, does not have these problems.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-07-18
DOI: 10.3390/jlpea12030041
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 42: The Benefits and Costs of Netlist Randomization
Based Side-Channel Countermeasures: An In-Depth Evaluation
Authors: Ali Asghar, Andreas Becher, Daniel Ziener
First page: 42
Abstract: Exchanging FPGA-based implementations of cryptographic algorithms during run-time using netlist randomized versions has been introduced recently as a unique countermeasure against side channel attacks. Using partial reconfiguration, it is possible to shuffle between structurally different but functionally similar versions of a cryptographic implementation. The resulting varying power profile enhances the resistance against power-based side channel attacks. While side channel leakage is reduced, costs in terms of additional resources and/or lowered throughput are often increased due to the overheads of the required online partial reconfiguration. In this work, we provide an in-depth evaluation of the leakage-area-throughput trade-off.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-07-23
DOI: 10.3390/jlpea12030042
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 43: A Subthreshold Layout Strategy for Faster and
Lower Energy Complex Digital Circuits
Authors: Jordan Morris, Pranay Prabhat, James Myers, Alex Yakovlev
First page: 43
Abstract: This work presents complex circuitry from subthreshold standard cell libraries created by geometric STI spacer patterning for bulk planar CMOS technology nodes. Performance/leakage granularity enhancement affords safer multi-Vt synthesis in aggressive voltage scaling schemes. Libraries are evaluated in silicon through implementation of 32-bit datapath 128-bit AES cores. Intra-die nominal temperature (20 °C) analysis reveals improvements of up to 8.65×/24% MEP-to-MEP in frequency and energy-per-cycle respectively, compared to a state-of-the-art subthreshold library. A negative temperature correlation with performance enhancement is demonstrated extending beyond the cell level and into more complex designs. MEP-to-MEP performance enhancement and energy-per-cycle reduction are demonstrated over a temperature range of 0 °C to 85 °C.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-08-02
DOI: 10.3390/jlpea12030043
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 44: Review on the Basic Circuit Elements and
Memristor Interpretation: Analysis, Technology and Applications
Authors: Aliyu Isah, Jean-Marie Bilbault
First page: 44
Abstract: Circuit or electronic components are useful elements allowing the realization of different circuit functionalities. The resistor, capacitor and inductor represent the three commonly known basic passive circuit elements owing to their fundamental nature relating them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing the resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. After a brief recall on the first three known basic passive circuit elements, a thorough description of the memristor follows. Memristor sparks interest in the scientific community due to its interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc. These features among many others are currently in high demand on an industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, the paper presents an in-depth overview of the philosophical argumentations of memristor, technologies and applications.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-08-03
DOI: 10.3390/jlpea12030044
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 45: Computer Engineering Education Experiences with
Authors: Peter Jamieson, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret, Michel A. Kinsy
First page: 45
Abstract: With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a microcontroller at a low-level using real tool-flows and implement and test their hardware. In this work, we describe our experiences with undergraduate engineers building RISC-V architectures on an FPGA and then extending their experiences to implement an Arduino-like RISC-V tool-flow and the respective hardware and software to handle input-output ports, interrupts, hardware timers, and communication protocols. The microcontroller is implemented on an FPGA as a Senior Design project to test the viability of such efforts. In this work, we will explain how undergraduates can achieve these experiences including preparation for these projects, the tool-flows they use, the challenges in understanding and extending a RISC-V processor with microcontroller functionality, and a suggestion of how to integrate this learning into an existing curriculum, including a discussion on if we should include these deeper experiences in the Computer Engineering undergraduate curriculum.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-08-09
DOI: 10.3390/jlpea12030045
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 46: High-Speed and Energy-Efficient Carry Look-Ahead
Adder
Authors: Padmanabhan Balasubramanian, Nikos E. Mastorakis
First page: 46
Abstract: The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-08-10
DOI: 10.3390/jlpea12030046
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 47: LoRa-Based Wireless Sensors Network for Rockfall
and Landslide Monitoring: A Case Study in Pantelleria Island with Portable
LoRaWAN Access
Authors: Mattia Ragnoli, Alfiero Leoni, Gianluca Barile, Giuseppe Ferri, Vincenzo Stornelli
First page: 47
Abstract: Rockfalls and landslides are hazards triggered from geomorphological and climatic factors other than human interaction. The economic and social impacts are not negligible, therefore the topic has become an important field in the application of remote monitoring. Wireless sensor networks (WSNs) are particularly suited for the deployment of such systems, thanks to the different technologies and topologies that are evolving nowadays. Among these, LoRa modulation technique represents a fitting technical solution for nodes communication in a WSN. In this paper, a smart autonomous LoRa-based rockfall and landslide monitoring system is presented. The structure has been operating in Pantelleria Island, Sicily, Italy. The sensing elements are disposed in sensor nodes arranged in a star topology. Network access to the LoRaWAN and the Internet is provided through gateways using a portable, solar powered device assembly. A system overview concerning both hardware and functionality of the nodes and gateways devices, then a power analysis is reported, and a monthly recorded result is presented, with related discussion.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-09-07
DOI: 10.3390/jlpea12030047
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 48: Time- and Amplitude-Controlled Power Noise
Generator against SPA Attacks for FPGA-Based IoT Devices
Authors: Luis Parrilla, Antonio García, Encarnación Castillo, Salvador Rodríguez-Bolívar, Juan Antonio López-Villanueva
First page: 48
Abstract: Power noise generation for masking power traces is a powerful countermeasure against Simple Power Analysis (SPA), and it has also been used against Differential Power Analysis (DPA) or Correlation Power Analysis (CPA) in the case of cryptographic circuits. This technique makes use of power consumption generators as basic modules, which are usually based on ring oscillators when implemented on FPGAs. These modules can be used to generate power noise and to also extract digital signatures through the power side channel for Intellectual Property (IP) protection purposes. In this paper, a new power consumption generator, named Xored High Consuming Module (XHCM), is proposed. XHCM improves, when compared to others proposals in the literature, the amount of current consumption per LUT when implemented on FPGAs. Experimental results show that these modules can achieve current increments in the range from 2.4 mA (with only 16 LUTs on Artix-7 devices with a power consumption density of 0.75 mW/LUT when using a single HCM) to 11.1 mA (with 67 LUTs when using 8 XHCMs, with a power consumption density of 0.83 mW/LUT). Moreover, a version controlled by Pulse-Width Modulation (PWM) has been developed, named PWM-XHCM, which is, as XHCM, suitable for power watermarking. In order to build countermeasures against SPA attacks, a multi-level XHCM (ML-XHCM) is also presented, which is capable of generating different power consumption levels with minimal area overhead (27 six-input LUTS for generating 16 different amplitude levels on Artix-7 devices). Finally, a randomized version, named RML-XHCM, has also been developed using two True Random Number Generators (TRNGs) to generate current consumption peaks with random amplitudes at random times. RML-XHCM requires less than 150 LUTs on Artix-7 devices. Taking into account these characteristics, two main contributions have been carried out in this article: first, XHCM and PWM-XHCM provide an efficient power consumption generator for extracting digital signatures through the power side channel, and on the other hand, ML-XHCM and RML-XHCM are powerful tools for the protection of processing units against SPA attacks in IoT devices implemented on FPGAs.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-09-10
DOI: 10.3390/jlpea12030048
Issue No: Vol. 12, No. 3 (2022)
- JLPEA, Vol. 12, Pages 19: A Novel Inductorless Design Technique for Linear
Equalization in Optical Receivers
Authors: Diaaeldin Abdelrahman, Christopher Williams, Odile Liboiron-Ladouceur, Glenn E. R. Cowan
First page: 19
Abstract: To mitigate the trade-off between gain and bandwidth of CMOS multistage amplifiers, a receiver front-end (FE) that employs a high-gain narrowband transimpedance amplifier (TIA) followed by an equalizing main amplifier (EMA) is proposed. The EMA provides a high-frequency peaking to extend the FE’s bandwidth from 25% to 60% of the targeted data rate (fbit). The peaking is realized by adding a pole in the feedback paths of an active feedback-based wideband amplifier. By embedding the peaking in the main amplifier (MA), the front-end meets the sensitivity and gain of conventional equalizer-based receivers with better energy efficiency by eliminating the equalizer stages. Simulated in TSMC 65 nm CMOS technology, the proposed front-end achieves 7.4 dB and 6 dB higher gain at 10 Gb/s and 20 Gb/s, respectively, compared to a conventional front-end that is designed for equal bandwidth and dissipates the same power. The higher gain demonstrates the capability of the proposed technique in breaking the gain-bandwidth trade-off. The higher gain also reduces the power penalty incurred by the decision circuit and improves the sensitivity by 1.5 dB and 2.24 dB at 10 Gb/s and 20 Gb/s, respectively. Simulations also confirm that the proposed FE exhibits a robust performance against process and temperature variations and can support large input currents.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-04-01
DOI: 10.3390/jlpea12020019
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 20: An Experimental Study on Step-Up DC–DC
Converters for Organic Photovoltaic Cells
Authors: P. Mendonça dos Santos, António J. Serralheiro, Beatriz Borges, João Paulo N. Torres, Ana Charas
First page: 20
Abstract: This work studies two circuit topologies to step-up the voltage supplied by an organic photovoltaic (OPV) cell. Comparison and validation of the proposed topologies are accomplished throughout analytical, simulation, and experimental results. Two circuit solutions were found more suitable to boost the harvested OPV cell low voltage, depending on the load condition: the classical hard-switching boost converter and a multilevel boost converter. Both experimental circuits include the drive of the MOSFET switch based on an LC oscillator at 1.2 MHz, allowing the implementation of a conversion system, supplied by voltages as low as 500 mV, with output voltages from 1.2 V up to 7 V, under solar simulator conditions. The circuit area for each converter prototype is 2.35 cm2, with a total area below 3.0 cm2 for the overall energy harvesting system, including the OPV cell, which makes this proposal an extremely compact solution for ultra-low power harvesting applications.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-04-08
DOI: 10.3390/jlpea12020020
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 21: Real-Time Embedded Implementation of Improved
Object Detector for Resource-Constrained Devices
Authors: Niranjan Ravi, Mohamed El-Sharkawy
First page: 21
Abstract: Artificial intelligence (A.I.) has revolutionised a wide range of human activities, including the accelerated development of autonomous vehicles. Self-navigating delivery robots are recent trends in A.I. applications such as multitarget object detection, image classification, and segmentation to tackle sociotechnical challenges, including the development of autonomous driving vehicles, surveillance systems, intelligent transportation, and smart traffic monitoring systems. In recent years, object detection and its deployment on embedded edge devices have seen a rise in interest compared to other perception tasks. Embedded edge devices have limited computing power, which impedes the deployment of efficient detection algorithms in resource-constrained environments. To improve on-board computational latency, edge devices often sacrifice performance, creating the need for highly efficient A.I. models. This research examines existing loss metrics and their weaknesses, and proposes an improved loss metric that can address the bounding box regression problem. Enhanced metrics were implemented in an ultraefficient YOLOv5 network and tested on the targeted datasets. The latest version of the PyTorch framework was incorporated in model development. The model was further deployed using the ROS 2 framework running on NVIDIA Jetson Xavier NX, an embedded development platform, to conduct the experiment in real time.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-04-13
DOI: 10.3390/jlpea12020021
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 22: Graph Coloring via Locally-Active Memristor
Oscillatory Networks
Authors: Alon Ascoli, Martin Weiher, Melanie Herzig, Stefan Slesazeck, Thomas Mikolajick, Ronald Tetzlaff
First page: 22
Abstract: This manuscript provides a comprehensive tutorial on the operating principles of a bio-inspired Cellular Nonlinear Network, leveraging the local activity of NbOx memristors to apply a spike-based computing paradigm, which is expected to deliver such a separation between the steady-state phases of its capacitively-coupled oscillators, relative to a reference cell, as to unveal the classification of the nodes of the associated graphs into the least number of groups, according to the rules of a non-deterministic polynomial-hard combinatorial optimization problem, known as vertex coloring. Besides providing the theoretical foundations of the bio-inspired signal-processing paradigm, implemented by the proposed Memristor Oscillatory Network, and presenting pedagogical examples, illustrating how the phase dynamics of the memristive computing engine enables to solve the graph coloring problem, the paper further presents strategies to compensate for an imbalance in the number of couplings per oscillator, to counteract the intrinsic variability observed in the electrical behaviours of memristor samples from the same batch, and to prevent the impasse appearing when the array attains a steady-state corresponding to a local minimum of the optimization goal. The proposed Memristor Cellular Nonlinear Network, endowed with ad hoc circuitry for the implementation of these control strategies, is found to classify the vertices of a wide set of graphs in a number of color groups lower than the cardinality of the set of colors identified by traditional either software or hardware competitor systems. Given that, under nominal operating conditions, a biological system, such as the brain, is naturally capable to optimise energy consumption in problem-solving activities, the capability of locally-active memristor nanotechnologies to enable the circuit implementation of bio-inspired signal processing paradigms is expected to pave the way toward electronics with higher time and energy efficiency than state-of-the-art purely-CMOS hardware.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-04-18
DOI: 10.3390/jlpea12020022
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 23: A Network Simulator for the Estimation of
Bandwidth Load and Latency Created by Heterogeneous Spiking Neural
Networks on Neuromorphic Computing Communication Networks
Authors: Robert Kleijnen, Markus Robens, Michael Schiek, Stefan van Waasen
First page: 23
Abstract: Accelerated simulations of biological neural networks are in demand to discover the principals of biological learning. Novel many-core simulation platforms, e.g., SpiNNaker, BrainScaleS and Neurogrid, allow one to study neuron behavior in the brain at an accelerated rate, with a high level of detail. However, they do not come anywhere near simulating the human brain. The massive amount of spike communication has turned out to be a bottleneck. We specifically developed a network simulator to analyze in high detail the network loads and latencies caused by different network topologies and communication protocols in neuromorphic computing communication networks. This simulator allows simulating the impacts of heterogeneous neural networks and evaluating neuron mapping algorithms, which is a unique feature among state-of-the-art network models and simulators. The simulator was cross-checked by comparing the results of a homogeneous neural network-based run with corresponding bandwidth load results from comparable works. Additionally, the increased level of detail achieved by the new simulator is presented. Then, we show the impact heterogeneous connectivity can have on the network load, first for a small-scale test case, and later for a large-scale test case, and how different neuron mapping algorithms can influence this effect. Finally, we look at the latency estimations performed by the simulator for different mapping algorithms, and the impact of the node size.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-04-21
DOI: 10.3390/jlpea12020023
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 24: Low-Power Deep Learning Model for Plant Disease
Detection for Smart-Hydroponics Using Knowledge Distillation Techniques
Authors: Aminu Musa, Mohammed Hassan, Mohamed Hamada, Farouq Aliyu
First page: 24
Abstract: Recent advances in computing allows researchers to propose the automation of hydroponic systems to boost efficiency and reduce manpower demands, hence increasing agricultural produce and profit. A completely automated hydroponic system should be equipped with tools capable of detecting plant diseases in real-time. Despite the availability of deep-learning-based plant disease detection models, the existing models are not designed for an embedded system environment, and the models cannot realistically be deployed on resource-constrained IoT devices such as raspberry pi or a smartphone. Some of the drawbacks of the existing models are the following: high computational resource requirements, high power consumption, dissipates energy rapidly, and occupies large storage space due to large complex structure. Therefore, in this paper, we proposed a low-power deep learning model for plant disease detection using knowledge distillation techniques. The proposed low-power model has a simple network structure of a shallow neural network. The parameters of the model were also reduced by more than 90%. This reduces its computational requirements as well as its power consumption. The proposed low-power model has a maximum power consumption of 6.22 w, which is significantly lower compared to the existing models, and achieved a detection accuracy of 99.4%.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-04-26
DOI: 10.3390/jlpea12020024
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 25: Selective Noise Based Power-Efficient and
Effective Countermeasure against Thermal Covert Channel Attacks in
Multi-Core Systems
Authors: Parisa Rahimi, Amit Kumar Singh, Xiaohang Wang
First page: 25
Abstract: With increasing interest in multi-core systems, such as any communication systems, infra-structures can become targets for information leakages via covert channel communication. Covert channel attacks lead to leaking secret information and data. To design countermeasures against these threats, we need to have good knowledge about classes of covert channel attacks along with their properties. Temperature–based covert communication channel, known as Thermal Covert Channel (TCC), can pose a threat to the security of critical information and data. In this paper, we present a novel scheme against such TCC attacks. The scheme adds selective noise to the thermal signal so that any possible TCC attack can be wiped out. The noise addition only happens at instances when there are chances of correct information exchange to increase the bit error rate (BER) and keep the power consumption low. Our experiments have illustrated that the BER of a TCC attack can increase to 94% while having similar power consumption as that of state-of-the-art.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-05-03
DOI: 10.3390/jlpea12020025
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 26: A Generalistic Approach to
Machine-Learning-Supported Task Migration on Real-Time Systems
Authors: Octavio Delgadillo, Bernhard Blieninger, Juri Kuhn, Uwe Baumgarten
First page: 26
Abstract: Consolidating tasks to a smaller number of electronic control units (ECUs) is an important strategy for optimizing costs and resources in the automotive industry. In our research, we aim to enable ECU consolidation by migrating tasks at runtime between different ECUs, which adds redundancy and fail-safety capabilities to the system. In this paper, we present a setup with a generalistic and modular architecture that allows for integrating and testing different ECU architectures and machine learning (ML) models. As part of a holistic testbed, we introduce a collection of reproducible tasks, as well as a toolchain that controls the dynamic migration of tasks depending on ECU status and load. The migration is aided by the machine learning predictions on the schedulability analysis of possible future task distributions. To demonstrate the capabilities of the setup, we show its integration with FreeRTOS-based ECUs and two ML models—a long short-term memory (LSTM) network and a spiking neural network—along with a collection of tasks to distribute among the ECUs. Our approach shows a promising potential for machine-learning-based schedulability analysis and enables a comparison between different ML models.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-05-03
DOI: 10.3390/jlpea12020026
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 27: A Standard-Cell-Based CMFB for Fully
Synthesizable OTAs
Authors: Francesco Centurelli, Riccardo Della Sala, Giuseppe Scotti
First page: 27
Abstract: In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of such stages. A detailed analysis of the CMFB is reported to both provide insight into circuit behavior and to derive useful design guidelines. The proposed CMFB is then exploited to build a fully standard-cell OTA suitable for automatic place and route. Simulation results referring to the standard-cell library of a commercial 130 nm CMOS process illustrated a differential gain of 28.3 dB with a gain-bandwidth product of 15.4 MHz when driving a 1.5 pF load capacitance. The OTA exhibits good robustness under PVT and mismatch variations and achieves state-of-the-art FOMs also thanks to the limited area footprint.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-05-05
DOI: 10.3390/jlpea12020027
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 28: Big–Little Adaptive Neural Networks on
Low-Power Near-Subthreshold Processors
Authors: Zichao Shen, Neil Howard, Jose Nunez-Yanez
First page: 28
Abstract: This paper investigates the energy savings that near-subthreshold processors can obtain in edge AI applications and proposes strategies to improve them while maintaining the accuracy of the application. The selected processors deploy adaptive voltage scaling techniques in which the frequency and voltage levels of the processor core are determined at the run-time. In these systems, embedded RAM and flash memory size is typically limited to less than 1 megabyte to save power. This limited memory imposes restrictions on the complexity of the neural networks model that can be mapped to these devices and the required trade-offs between accuracy and battery life. To address these issues, we propose and evaluate alternative ‘big–little’ neural network strategies to improve battery life while maintaining prediction accuracy. The strategies are applied to a human activity recognition application selected as a demonstrator that shows that compared to the original network, the best configurations obtain an energy reduction measured at 80% while maintaining the original level of inference accuracy.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-05-18
DOI: 10.3390/jlpea12020028
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 29: Low-Overhead Reinforcement Learning-Based Power
Management Using 2QoSM
Authors: Michael Giardino, Daniel Schwyn, Bonnie Ferri, Aldo Ferri
First page: 29
Abstract: With the computational systems of even embedded devices becoming ever more powerful, there is a need for more effective and pro-active methods of dynamic power management. The work presented in this paper demonstrates the effectiveness of a reinforcement-learning based dynamic power manager placed in a software framework. This combination of Q-learning for determining policy and the software abstractions provide many of the benefits of co-design, namely, good performance, responsiveness and application guidance, with the flexibility of easily changing policies or platforms. The Q-learning based Quality of Service Manager (2QoSM) is implemented on an autonomous robot built on a complex, powerful embedded single-board computer (SBC) and a high-resolution path-planning algorithm. We find that the 2QoSM reduces power consumption up to 42% compared to the Linux on-demand governor and 10.2% over a state-of-the-art situation aware governor. Moreover, the performance as measured by path error is improved by up to 6.1%, all while saving power.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-05-19
DOI: 10.3390/jlpea12020029
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 30: Embedded Object Detection with Custom LittleNet,
FINN and Vitis AI DCNN Accelerators
Authors: Michal Machura, Michal Danilowicz, Tomasz Kryjak
First page: 30
Abstract: Object detection is an essential component of many systems used, for example, in advanced driver assistance systems (ADAS) or advanced video surveillance systems (AVSS). Currently, the highest detection accuracy is achieved by solutions using deep convolutional neural networks (DCNN). Unfortunately, these come at the cost of a high computational complexity; hence, the work on the widely understood acceleration of these algorithms is very important and timely. In this work, we compare three different DCNN hardware accelerator implementation methods: coarse-grained (a custom accelerator called LittleNet), fine-grained (FINN) and sequential (Vitis AI). We evaluate the approaches in terms of object detection accuracy, throughput and energy usage on the VOT and VTB datasets. We also present the limitations of each of the methods considered. We describe the whole process of DNNs implementation, including architecture design, training, quantisation and hardware implementation. We used two custom DNN architectures to obtain a higher accuracy, higher throughput and lower energy consumption. The first was implemented in SystemVerilog and the second with the FINN tool from AMD Xilinx. Next, both approaches were compared with the Vitis AI tool from AMD Xilinx. The final implementations were tested on the Avnet Ultra96-V2 development board with the Zynq UltraScale+ MPSoC ZCU3EG device. For two different DNNs architectures, we achieved a throughput of 196 fps for our custom accelerator and 111 fps for FINN. The same networks implemented with Vitis AI achieved 123.3 fps and 53.3 fps, respectively.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-05-20
DOI: 10.3390/jlpea12020030
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 31: A Methodology to Design Static NCL Libraries
Authors: Toi Le Thanh, Lac Truong Tri, Trang Hoang
First page: 31
Abstract: The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-06-06
DOI: 10.3390/jlpea12020031
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 32: Implementing a Timing Error-Resilient and
Energy-Efficient Near-Threshold Hardware Accelerator for Deep Neural
Network Inference
Authors: Noel Daniel Gundi, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty
First page: 32
Abstract: Increasing processing requirements in the Artificial Intelligence (AI) realm has led to the emergence of domain-specific architectures for Deep Neural Network (DNN) applications. Tensor Processing Unit (TPU), a DNN accelerator by Google, has emerged as a front runner outclassing its contemporaries, CPUs and GPUs, in performance by 15×–30×. TPUs have been deployed in Google data centers to cater to the performance demands. However, a TPU’s performance enhancement is accompanied by a mammoth power consumption. In the pursuit of lowering the energy utilization, this paper proposes PREDITOR—a low-power TPU operating in the Near-Threshold Computing (NTC) realm. PREDITOR uses mathematical analysis to mitigate the undetectable timing errors by boosting the voltage of the selective multiplier-and-accumulator units at specific intervals to enhance the performance of the NTC TPU, thereby ensuring a high inference accuracy at low voltage. PREDITOR offers up to 3×–5× improved performance in comparison to the leading-edge error mitigation schemes with a minor loss in accuracy.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-06-06
DOI: 10.3390/jlpea12020032
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 33: The Potential of SoC FPAAs for Emerging
Ultra-Low-Power Machine Learning
Authors: Jennifer Hasler
First page: 33
Abstract: Large-scale field-programmable analog arrays (FPAA) have the potential to handle machine inference and learning applications with significantly low energy requirements, potentially alleviating the high cost of these processes today, even in cloud-based systems. FPAA devices enable embedded machine learning, one form of physical mixed-signal computing, enabling machine learning and inference on low-power embedded platforms, particularly edge platforms. This discussion reviews the current capabilities of large-scale field-programmable analog arrays (FPAA), as well as considering the future potential of these SoC FPAA devices, including questions that enable ubiquitous use of FPAA devices similar to FPGA devices. Today’s FPAA devices include integrated analog and digital fabric, as well as specialized processors and infrastructure, becoming a platform of mixed-signal development and analog-enabled computing. We address and show that next-generation FPAAs can handle the required load of 10,000–10,000,000,000 PMAC, required for present and future large fielded applications, at orders of magnitude of lower energy levels than those expected by current technology, motivating the need to develop these new generations of FPAA devices.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-06-06
DOI: 10.3390/jlpea12020033
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 34: Bridging the Gap between Design and Simulation
of Low-Voltage CMOS Circuits
Authors: Cristina Missel Adornes, Deni Germano Alves Neto, Márcio Cherem Schneider, Carlos Galup-Montoro
First page: 34
Abstract: This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced compact MOSFET (ACM) model and was implemented in Verilog-A to simulate different circuits designed with the ACM model in Verilog-compatible simulators. Being able to simulate MOS circuits through the same model used in a hand design benefits designers in understanding how the main MOSFET parameters affect the design. Herein, the classic CMOS inverter, a ring oscillator, a self-biased current source and a common source amplifier were designed and simulated using either the 4PM or the BSIM model. The four-parameter model was simulated in many sorts of circuits with very satisfactory results in the low-voltage cases. As the ultra-low-voltage (ULV) domain is expanding due to applications, such as the internet of things and wearable circuits, so is the use of a simplified ULV MOSFET model.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-06-16
DOI: 10.3390/jlpea12020034
Issue No: Vol. 12, No. 2 (2022)
- JLPEA, Vol. 12, Pages 5: Design Aspects of a Single-Output Multi-String
WLED Driver Using 40 nm CMOS Technology
Authors: Fadi R. Shahroury, Hani H. Ahmad, Ibrahim Abuishmais
First page: 5
Abstract: This work presents various essential features and design aspects of a single-inductor, common-output, and multi-string White Light Emitting Diode (WLED) driver for low-power portable devices. High efficiency is one of the main features of such a device. Here, the efficiency improvement is achieved by selecting the proper arrangement of WLEDs and a proper sensing-circuit technique to determine the minimum, real-time, needed output voltage. This minimum voltage necessary to activate all WLEDs depends on the number of strings and the forward voltage drops among the WLEDs. Advanced CMOS technology is advantageous in mixed-signal environments such as WLED drivers. However, this process suffers from low on-resistance, which degrades the accuracy of the current sinks. To accommodate the above features and mitigate the low node process issue, a boost-converter that is single output with a load of a three-string arrangement, with 6 WLEDs each, is presented. The designed driver has an input voltage range of 3.2–4.2V. The proposed solution is realized with ultra-low power consumption circuits and verified using ADS tools utilizing 40 nm 1P9M TSMC CMOS technology. An inter-string current accuracy of 0.2% and peak efficiency of 91% are achieved with an output voltage up to 25 V. The integrated WLED driver circuitry enables a high switching frequency of 1MHz and reduces the passive elements’ size in the power stage.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-01-18
DOI: 10.3390/jlpea12010005
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 6: Hardware/Software Solution for Low Power
Evaluation of Tsunami Danger
Authors: Mikhail Lavrentiev, Konstantin Lysakov, Andrey Marchuk, Konstantin Oblaukhov, Mikhail Shadrin
First page: 6
Abstract: Carbon footprint reduction issues have been drawing more and more attention these days. Reducing the energy consumption is among the basic directions along this line. In the paper, a low-energy approach to tsunami danger evaluation is concerned. After several disaster tsunamis of the XXIst century, the question arises whether is it possible to evaluate in a couple of minutes the tsunami wave parameters, expected at the particular geo location. The point is that it takes around 20 min for the wave to approach the nearest coast after a seismic event offshore of Japan. Currently, the main tool for studying tsunamis is computer modeling. In particular, the expected tsunami height near the coastline, when a major underwater earthquake is detected, can be estimated by a series of numerical experiments of various scenarios of generation and the following wave propagation. Reducing the calculation time of such scenarios and the necessary energy consumption for this is the scope of this study. Moreover, in case of the major earthquake, the electric power shutdown is possible (e.g., the accident at the Fukushima nuclear power station in Japan on 11 May 2011), so the solution should be of low energy-consuming, preferably based at regular personal computers (PCs) or laptops. The way to achieve the requested performance of numerical modeling at the PC platform is a combination of efficient algorithms and their hardware acceleration. Following this strategy, a solution for the fast numerical simulation of tsunami wave propagation has been proposed. Most of tsunami researchers use the shallow-water approximation to simulate tsunami wave propagation at deep water areas. For software implementation, the MacCormack finite-difference scheme has been chosen, as it is suitable for pipelining. For hardware code acceleration, a special processor, that is, the calculator, has been designed at a field-programmable gate array (FPGA) platform. This combination was tested in terms of precision by comparison with the reference code and with the exact solutions (known for some special cases of the bottom profile). The achieved performance made it possible to calculate the wave propagation over a 1000 × 500 km water area in 1 min (the mesh size was compared to 250 m). It was nearly 300 times faster compared to that of a regular PC and 10 times faster compared to the use of a central processing unit (CPU). This result, being implemented into tsunami warning systems, will make it possible to reduce human casualties and economy losses for the so-called near-field tsunamis. The presented paper discussed the new aspect of such implementation, namely low energy consumption. The corresponding measurements for three platforms (PC and two types of FPGA) have been performed, and a comparison of the obtained results of energy consumption was given. As the numerical simulation of numerous tsunami propagation scenarios from different sources are needed for the purpose of coastal tsunami zoning, the integrated amount of the saving energy is expected to be really valuable. For the time being, tsunami researchers have not used the FPGA-based acceleration of computer code execution. Perhaps, the energy-saving aspect is able to promote the use of FPGAs in tsunami researches. The approach to designing special FPGA-based processors for the fast solution of various engineering problems using a PC could be extended to other areas, such as bioinformatics (motif search in DNA sequences and other algorithms of genome analysis and molecular dynamics) and seismic data processing (three-dimensional (3D) wave package decomposition, data compression, noise suppression, etc.).
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-01-21
DOI: 10.3390/jlpea12010006
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 7: Acknowledgment to Reviewers of Journal of Low
Power Electronics and Applications in 2021
Authors: Journal of Low Power Electronics; Applications Editorial Office
First page: 7
Abstract: Rigorous peer-reviews are the basis of high-quality academic publishing [...]
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-01-25
DOI: 10.3390/jlpea12010007
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 8: CondenseNeXtV2: Light-Weight Modern Image
Classifier Utilizing Self-Querying Augmentation Policies
Authors: Priyank Kalgaonkar, Mohamed El-Sharkawy
First page: 8
Abstract: Artificial Intelligence (AI) combines computer science and robust datasets to mimic natural intelligence demonstrated by human beings to aid in problem-solving and decision-making involving consciousness up to a certain extent. From Apple’s virtual personal assistant, Siri, to Tesla’s self-driving cars, research and development in the field of AI is progressing rapidly along with privacy concerns surrounding the usage and storage of user data on external servers which has further fueled the need of modern ultra-efficient AI networks and algorithms. The scope of the work presented within this paper focuses on introducing a modern image classifier which is a light-weight and ultra-efficient CNN intended to be deployed on local embedded systems, also known as edge devices, for general-purpose usage. This work is an extension of the award-winning paper entitled ‘CondenseNeXt: An Ultra-Efficient Deep Neural Network for Embedded Systems’ published for the 2021 IEEE 11th Annual Computing and Communication Workshop and Conference (CCWC). The proposed neural network dubbed CondenseNeXtV2 utilizes a new self-querying augmentation policy technique on the target dataset along with adaption to the latest version of PyTorch framework and activation functions resulting in improved efficiency in image classification computation and accuracy. Finally, we deploy the trained weights of CondenseNeXtV2 on NXP BlueBox which is an edge device designed to serve as a development platform for self-driving cars, and conclusions will be extrapolated accordingly.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-02-03
DOI: 10.3390/jlpea12010008
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 9: Fully Differential Miller Op-Amp with Enhanced
Large- and Small-Signal Figures of Merit
Authors: Anindita Paul, Jaime Ramirez-Angulo, Héctor Vázquez-Leal, Jesús Huerta-Chua, Alejandro Diaz-Sanchez
First page: 9
Abstract: A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-02-08
DOI: 10.3390/jlpea12010009
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 10: Mapping Transformation Enabled High-Performance
and Low-Energy Memristor-Based DNNs
Authors: Md. Oli-Uz-Zaman, Saleh Ahmad Khan, Geng Yuan, Zhiheng Liao, Jingyan Fu, Caiwen Ding, Yanzhi Wang, Jinhui Wang
First page: 10
Abstract: When deep neural network (DNN) is extensively utilized for edge AI (Artificial Intelligence), for example, the Internet of things (IoT) and autonomous vehicles, it makes CMOS (Complementary Metal Oxide Semiconductor)-based conventional computers suffer from overly large computing loads. Memristor-based devices are emerging as an option to conduct computing in memory for DNNs to make them faster, much more energy efficient, and accurate. Despite having excellent properties, the memristor-based DNNs are yet to be commercially available because of Stuck-At-Fault (SAF) defects. A Mapping Transformation (MT) method is proposed in this paper to mitigate Stuck-at-Fault (SAF) defects from memristor-based DNNs. First, the weight distribution for the VGG8 model with the CIFAR10 dataset is presented and analyzed. Then, the MT method is used for recovering inference accuracies at 0.1% to 50% SAFs with two typical cases, SA1 (Stuck-At-One): SA0 (Stuck-At-Zero) = 5:1 and 1:5, respectively. The experiment results show that the MT method can recover DNNs to their original inference accuracies (90%) when the ratio of SAFs is smaller than 2.5%. Moreover, even when the SAF is in the extreme condition of 50%, it is still highly efficient to recover the inference accuracy to 80% and 21%. What is more, the MT method acts as a regulator to avoid energy and latency overhead generated by SAFs. Finally, the immunity of the MT Method against non-linearity is investigated, and we conclude that the MT method can benefit accuracy, energy, and latency even with high non-linearity LTP = 4 and LTD = −4.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-02-10
DOI: 10.3390/jlpea12010010
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 11: DSCU: Accelerating CNN Inference in FPGAs with
Dual Sizes of Compute Unit
Authors: Zhenshan Bao, Junnan Guo, Wenbo Zhang, Hongbo Dang
First page: 11
Abstract: FPGA-based accelerators have shown great potential in improving the performance of CNN inference. However, the existing FPGA-based approaches suffer from a low compute unit (CU) efficiency due to their large number of redundant computations, thus leading to high levels of performance degradation. In this paper, we show that no single CU can perform best across all the convolutional layers (CONV-layers). To this end, we propose the use of dual sizes of compute unit (DSCU), an approach that aims to accelerate CNN inference in FPGAs. The key idea of DSCU is to select the best combination of CUs via dynamic programming scheduling for each CONV-layer and then assemble each CONV-layer combination into a computing solution for the given CNN to deploy in FPGAs. The experimental results show that DSCU can achieve a performance density of 3.36 × 10−3 GOPs/slice on a Xilinx Zynq ZU3EG, which is 4.29 times higher than that achieved by other approaches.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-02-13
DOI: 10.3390/jlpea12010011
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 12: A Tree-Based Architecture for High-Performance
Ultra-Low-Voltage Amplifiers
Authors: Francesco Centurelli, Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
First page: 12
Abstract: In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-02-17
DOI: 10.3390/jlpea12010012
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 13: A Model for the Evaluation of Monostable
Molecule Signal Energy in Molecular Field-Coupled Nanocomputing
Authors: Yuri Ardesi, Mariagrazia Graziano, Gianluca Piccinini
First page: 13
Abstract: Molecular Field-Coupled Nanocomputing (FCN) is a computational paradigm promising high-frequency information elaboration at ambient temperature. This work proposes a model to evaluate the signal energy involved in propagating and elaborating the information. It splits the evaluation into several energy contributions calculated with closed-form expressions without computationally expensive calculation. The essential features of the 1,4-diallylbutane cation are evaluated with Density Functional Theory (DFT) and used in the model to evaluate circuit energy. This model enables understanding the information propagation mechanism in the FCN paradigm based on monostable molecules. We use the model to verify the bistable factor theory, describing the information propagation in molecular FCN based on monostable molecules, analyzed so far only from an electrostatic standpoint. Finally, the model is integrated into the SCERPA tool and used to quantify the information encoding stability and possible memory effects. The obtained results are consistent with state-of-the-art considerations and comparable with DFT calculation.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-03-01
DOI: 10.3390/jlpea12010013
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 14: Silicon-Compatible Memristive Devices Tailored
by Laser and Thermal Treatments
Authors: Maria N. Koryazhkina, Dmitry O. Filatov, Stanislav V. Tikhov, Alexey I. Belov, Dmitry S. Korolev, Alexander V. Kruglov, Ruslan N. Kryukov, Sergey Yu. Zubkov, Vladislav A. Vorontsov, Dmitry A. Pavlov, David I. Tetelbaum, Alexey N. Mikhaylov, Sergey A. Shchanikov, Sungjun Kim, Bernardo Spagnolo
First page: 14
Abstract: Nowadays, memristors are of considerable interest to researchers and engineers due to the promise they hold for the creation of power-efficient memristor-based information or computing systems. In particular, this refers to memristive devices based on the resistive switching phenomenon, which in most cases are fabricated in the form of metal–insulator–metal structures. At the same time, the demand for compatibility with the standard fabrication process of complementary metal–oxide semiconductors makes it relevant from a practical point of view to fabricate memristive devices directly on a silicon or SOI (silicon on insulator) substrate. Here we have investigated the electrical characteristics and resistive switching of SiOx- and SiNx-based memristors fabricated on SOI substrates and subjected to additional laser treatment and thermal treatment. The investigated memristors do not require electroforming and demonstrate a synaptic type of resistive switching. It is found that the parameters of resistive switching of SiOx- and SiNx-based memristors on SOI substrates are remarkably improved. In particular, the laser treatment gives rise to a significant increase in the hysteresis loop in I–V curves of SiNx-based memristors. Moreover, for SiOx-based memristors, the thermal treatment used after the laser treatment produces a notable decrease in the resistive switching voltage.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-03-02
DOI: 10.3390/jlpea12010014
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 15: Cooperative Design of Devices and Services to
Balance Low Power and User Experience
Authors: Takayuki Hoshino, Rentaro Yoshioka, Yukihide Kohira, Shingo Tetsuka
First page: 15
Abstract: CPS (Cyber Physical Systems) is an approach often adopted for improving real-world activities by utilizing data. It also can be used to improve customer experiences in service applications by analyzing customer behavior, captured by sensing devices and by supporting utilization of that data by the service providers, to improve the system. In developing such systems, no method has been established to systematically evaluate the impact of individual component design on the user experience. Knowledge Experience Design is a method for distilling and validating information that affects the quality of the user experience by focusing on user activities and underlying knowledge. This methodology has been applied to a system for a museum, in which visitor activities are observed by sensing devices, to aid the Curator’s awareness for improving museum services. As a result, a cooperative process for designing devices and user experience as a service was derived, in which competing interests of lower power consumption and user experience improvement have been attained. The proposed design method can be used for the co-design of systems that are built on the close coordination of hardware devices and software applications, for providing value-oriented services to users, which aids realization of CPS oriented to evaluating and improving such environments.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-03-08
DOI: 10.3390/jlpea12010015
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 16: A 0.5 V Sub-Threshold CMOS Current-Controlled
Ring Oscillator for IoT and Implantable Devices
Authors: Andrea Ballo, Salvatore Pennisi, Giuseppe Scotti, Chiara Venezia
First page: 16
Abstract: A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a standard 28-nm technology and supplied by 0.5 V, were simulated. By exploiting a programmable capacitor array, it allows a very large range of oscillation frequencies to be set, from 1 MHz to about 1 GHz, with a limited current consumption. Considering, for example, the five-stage topology, a nominal oscillation frequency of 516 MHz is obtained with an average power dissipation of about 29 µW. The solution provides a tuneable oscillation frequency, which can be adjusted from 360 to 640 MHz by controlling the bias current with a sensitivity of 0.43 MHz/nA.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-03-09
DOI: 10.3390/jlpea12010016
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 17: Implementation of a Fuel Estimation Algorithm
Using Approximated Computing
Authors: Imed Ben Dhaou
First page: 17
Abstract: The rising concerns about global warming have motivated the international community to take remedial actions to lower greenhouse gas emissions. The transportation sector is believed to be one of the largest air polluters. The quantity of greenhouse gas emissions is directly linked to the fuel consumption of vehicles. Eco-driving is an emergent driving style that aims at improving gas mileage. Real-time fuel estimation is a critical feature of eco-driving and eco-routing. There are numerous approaches to fuel estimation. The first approach uses instantaneous values of speed and acceleration. This can be accomplished using either GPS data or direct reading through the OBDII interface. The second approach uses the average value of the speed and acceleration that can be measured using historical data or through web mapping. The former cannot be used for route planning. The latter can be used for eco-routing. This paper elaborates on a highly pipelined VLSI architecture for the fuel estimation algorithm. Several high-level transformation techniques have been exercised to reduce the complexity of the algorithm. Three competing architectures have been implemented on FPGA and compared. The first one uses a binary search algorithm, the second architecture employs a direct address table, and the last one uses approximation techniques. The complexity of the algorithm is further reduced by combining both approximated computing and precalculation. This approach helped reduce the floating-point operations by 30% compared with the state-of-the-art implementation.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-03-16
DOI: 10.3390/jlpea12010017
Issue No: Vol. 12, No. 1 (2022)
- JLPEA, Vol. 12, Pages 18: Towards Integration of a Dedicated Memory
Controller and Its Instruction Set to Improve Performance of Systems
Containing Computational SRAM
Authors: Kévin Mambu, Henri-Pierre Charles, Maha Kooli, Julie Dumas
First page: 18
Abstract: In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by the memory wall. However, it does not address the energy wall problem caused by data transfer over memory hierarchies. This paper proposes the data-locality management unit (DMU) to efficiently transfer data from a DRAM memory to a computational SRAM (C-SRAM) memory allowing IMC operations. The DMU is tightly coupled within the C-SRAM and allows one to align the data structure in order to perform effective in-memory computation. We propose a dedicated instruction set within the DMU to issue data transfers. The performance evaluation of a system integrating C-SRAM within the DMU compared to a reference scalar system architecture shows an increase from ×5.73 to ×11.01 in speed-up and from ×29.49 to ×46.67 in energy reduction, versus a system integrating C-SRAM without any transfer mechanism compared to a reference scalar system architecture.
Citation: Journal of Low Power Electronics and Applications
PubDate: 2022-03-16
DOI: 10.3390/jlpea12010018
Issue No: Vol. 12, No. 1 (2022)
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