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  Subjects -> ELECTRONICS (Total: 207 journals)
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IEEE Embedded Systems Letters
Journal Prestige (SJR): 0.347
Citation Impact (citeScore): 2
Number of Followers: 61  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1943-0663
Published by IEEE Homepage  [228 journals]
  • IEEE Embedded Systems Letters Publication Information

    • Free pre-print version: Loading...

      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Infeasibility Test for Fixed-Priority Scheduling on Multiprocessor
           Platforms

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      Authors: Hoon Sung Chwa;Jinkyu Lee;
      Pages: 55 - 58
      Abstract: Fixed-priority scheduling (FPS), due to its simplicity to implement, has been one of the most popular scheduling algorithms for real-time embedded systems equipped with multiprocessor platforms. While there have been many studies that find sufficient conditions for a given task set to be feasible (schedulable) by FPS with a proper priority assignment, the other direction (i.e., finding infeasible task sets) has not been studied. In this letter, we address a necessary feasibility condition that judges a given task set to be infeasible under FPS with every priority assignment on multiprocessor platforms. To this end, we derive useful properties for the condition and develop the first infeasibility test for FPS on multiprocessor platforms. Via simulations, we show that the proposed infeasibility test discovers a number of FPS-infeasible task sets which are not proven FPS-infeasible by any existing studies.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Low-Power Compressor-Based Approximate Multipliers With Error Correcting
           Module

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      Authors: U. Anil Kumar;Sumit K. Chatterjee;Syed Ershad Ahmed;
      Pages: 59 - 62
      Abstract: This letter proposes an unsigned approximate multiplier architecture segmented into three portions: the least significant portion that contributes least to the partial product (PP) is replaced with a new constant compensation term to improve hardware savings without sacrificing accuracy. The PPs in the middle portion are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple yet efficient error correction module. The most significant portion of the multiplier is implemented using exact logic as approximating it will results in a large error. Experimental results of 8-bit multiplier show that the power and power-delay products are reduced up to 47.7% and 55.2%, respectively, in comparison with the exact design and 36.9% and 39.5%, respectively, in comparison with the existing designs without significant compromise on accuracy.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on
           FPGAs

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      Authors: Muhammad Irfan;Hasan Erdem Yantır;Zahid Ullah;Ray C. C. Cheung;
      Pages: 63 - 66
      Abstract: Field-programmable gate arrays (FPGAs) having software-like reconfigurability and hardware-like performance are adopted as developing platforms to implement complex systems, i.e., software-defined networks (SDNs). Ternary content-addressable memory (TCAM) is not present in modern FPGA, but rather it is used as a softcore where needed. The hardware structure of an FPGA is flexible but rigid; the elemental structure is fixed and can be used in a limited number of ways. Existing FPGA-based TCAMs exhaust one particular type of memory when a large size is implemented, resulting in a shortage of memory for the rest of the system. Our proposed architecture uses only those memory elements of FPGA that are redundant and not used by other parts. In this letter, the proposed architecture, comp-TCAM, combines both block RAM (BRAM) and lookup table RAM (LUTRAM) to implement the TCAM architecture; that eliminates the dependency on the type of memory and is adaptable to the requirement of the system. Evaluation results show the feasibility, scalability, and effectiveness of the proposed TCAM architecture compared to the existing TCAM architectures. The hardware resource utilization on Xilinx VIrtex-7 FPGA is reduced by 41.6% compared to state-of-the-art FPGA-based TCAM with no harm to the system’s performance providing a throughput of 21.06 Gbits/s.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC

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      Authors: Surajit Das;Chandan Karfa;
      Pages: 67 - 70
      Abstract: Wraparound channels in Torus network-on-chip (NoC) help in reducing overall hop counts traversed by traffic. However, the cyclic paths created by the wraparound channel make Torus NoC deadlock prone. The Turn model and channel dependency graph (CDG) are two classical approaches used for detecting and avoiding deadlock in NoC. In this work, we propose an Arc model for avoiding deadlock in Torus NoC. The Arc model is an extension to the Turn model and is useful for deadlock avoidance in Torus. Directional dependency graph (DDG) is also presented in this work by combining both the Turn model and CDG for detecting deadlock in Torus NoC. DDG is a simpler approach for identifying deadlock scenarios, formulating deadlock avoidance, and showing deadlock freedom while using the Arc model along with a set of Turns.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • HASTE: Software Security Analysis for Timing Attacks on Clear Hardware
           Assumption

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      Authors: Prabuddha Chakraborty;Jonathan Cruz;Christopher Posada;Sandip Ray;Swarup Bhunia;
      Pages: 71 - 74
      Abstract: Information leakage via timing side-channel analysis can compromise embedded systems used in diverse applications that are otherwise secure. Most state-of-the-art timing side-channel detection techniques focus on analyzing the software code while paying little to no attention to the underlying hardware. This limits the ability of such techniques in terms of detection and repair. In this letter, we propose a timing side-channel analysis framework that takes into consideration both the software and the underlying hardware microarchitecture to detect vulnerabilities with high precision. We also propose a set of metrics to quantify the severity of the vulnerabilities. We verify our proposed framework on two different computation subroutines which are widely used in crypto and secure systems.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Machine Learning for Sensor Transducer Conversion Routines

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      Authors: Thomas Newton;James T. Meech;Phillip Stanley-Marbell;
      Pages: 75 - 78
      Abstract: Sensors with digital outputs require software conversion routines to transform the unitless analog-to-digital converter samples to physical quantities with correct units. These conversion routines are computationally complex given the limited computational resources of low-power embedded systems. This letter presents a set of machine learning methods to learn new, less-complex conversion routines that do not sacrifice accuracy for the BME680 environmental sensor. We present a Pareto analysis of the tradeoff between accuracy and computational overhead for the models and models that reduce the computational overhead of the existing industry-standard conversion routines for temperature, pressure, and humidity by 62%, 71%, and 18%, respectively. The corresponding RMS errors are 0.0114 °C, 0.0280 KPa, and 0.0337%. These results show that machine learning methods for learning conversion routines can produce conversion routines with a reduced computational overhead which maintain good accuracy.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Design of Fault-Tolerant Distributed Cyber–Physical Systems for
           Smart Environments

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      Authors: Luca Cassano;Antonio Miele;Francesco Mione;Nicola Tonellotto;Carlo Vallati;
      Pages: 79 - 82
      Abstract: Cyber–physical systems are more and more employed to implement smart environments also in safety-critical scenarios. We here propose a novel system-level design approach capable of considering two relevant aspects of such systems: 1) elaborations together with sensing and actuation need to be placed in the zones where cyber–physical interactions take place and 2) fault-tolerance mechanisms have to be incorporated to tolerate device failures. The proposed design approach identifies the optimal instantiation of the system architecture and deployment of the applications to minimize the monetary cost of the solution while guaranteeing resource requirements and fault tolerance. Experimental results show that the proposed approach reduces up to 20% the solution cost w.r.t. a straightforward hardening baseline with a computationally viable execution time.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Guaranteeing That Multilevel Prioritized DNN Models on an Embedded GPU
           Have Inference Performance Proportional to Respective Priorities

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      Authors: Myungsun Kim;
      Pages: 83 - 86
      Abstract: When multiple deep neural networks (DNNs) are using an embedded GPU as an accelerator, adjusting the CPU occupancy time of the process encompassing each DNN on a priority basis does not always guarantee that higher priority DNNs take priority over the GPU. To address this problem, we propose a methodology that basically uses the model from PyTorch without modification while providing additional advantages. First, the response performance of higher priority DNNs is improved by allowing DNNs to occupy the GPU in preference in proportion to the priority granted to the hosting processes. Second, it reduces the execution time of each DNN by removing the multicontext overhead that occurs under an environment with an independent process per DNN, executing DNNs in a multithreaded manner to overcome the limitation of pure Python and taking advantage of multistream for concurrent running of different DNN operations inside the GPU.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Improved Low Time-Complexity Schedulability Test for Nonpreemptive EDF on
           a Multiprocessor

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      Authors: Seongtae Lee;Sanghyeok Park;Jinkyu Lee;
      Pages: 87 - 90
      Abstract: In real-time embedded systems, nonpreemptive earliest deadline first (NP-EDF) is one of the most popular scheduling algorithms to offer timing guarantees of a set of nonpreemptive real-time jobs (tasks). While most existing schedulability tests for NP-EDF on a multiprocessor platform have paid attention to improving schedulability performance at the expense of increasing time complexity, only a few studies can be used for the situation where low time complexity is critical. In this letter, based on an existing low time-complexity schedulability test for NP-EDF, we develop schedulability tests that improve schedulability performance but maintain low time complexity. Our experiments show that the proposed schedulability tests improve schedulability performance up to 592.4%, compared to the existing low time-complexity one, and they can find some additional task sets schedulable by NP-EDF, which cannot be covered by existing high time-complexity NP-EDF schedulability tests.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Call String Sensitivity for Hardware-Based Hybrid WCET Analysis

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      Authors: Boris Dreyer;Christian Hochberger;Simon Wegener;
      Pages: 91 - 94
      Abstract: Many embedded systems operate under real-time conditions. For them, the worst case execution time (WCET) is a crucial information to check whether the software implementation meets the requirements. In modern microcontrollers, this WCET can often no longer be evaluated statically since these processors include too many unpredictable components (cache, bus arbitration, $ldots$ ,). Here, hybrid WCET estimation comes into play, where measured traces are used to empirically compute bounds for the WCET. For meaningful estimations, it is required to put each measured segment into a corresponding execution context. In this contribution, we present a method that allows to gather such context-sensitive statistics online in hardware. This enables arbitrary long measurement intervals with a precision that compares to state-of-the-art offline tools.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • A Quantitative Analysis and Optimization on the Cache Behavior Influenced
           by Literal Pools

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      Authors: Ming Ling;Hongxi Li;Xiang Yu;
      Pages: 95 - 98
      Abstract: A literal pool is normally used by a RISC processor to store constant values adjacent to the function that accesses them. Therefore, during a cache line filling, the literals in literal pools are possibly filled into the instruction cache, while instructions near literal pools could also be fetched into the data cache because the smallest cache management granularity is the size of a cache line. This useless but cached data deteriorates the performance of caches in a RISC processor. In this letter, we propose a find literal pool (FLP) algorithm to locate and record all literal pools in the text segment. Based on this information, we analyze the distribution of literal pools in SPEC CPU 2006 benchmarks and trace the process of caching literals to quantify the impacts of literal pools on caches. To optimize the cache performance influenced by literal pools, a relocate literal pool (RLP) algorithm is proposed to merge originally scattered literal pools into bigger ones without any hardware overhead. We evaluate the effectiveness of RLP with six SPEC 2006 benchmarks. Experimental results show that RLP reduces cache misses up to 24.4% in I-Cache and 38.72% in D-Cache compared to those of original literal pool layouts.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Gate-Level Design Methodology for Side-Channel Resistant Logic Styles
           Using TFETs

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      Authors: Ignacio M. Delgado-Lozano;Erica Tena-Sánchez;Juan Núñez;Antonio J. Acosta;
      Pages: 99 - 102
      Abstract: The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. This letter deals with the optimized design of differential power analysis (DPA)-resilient hiding-based techniques, using tunnel field-effect transistors (TFETs). Specifically, proposed TFET implementations of dual-precharge-logic primitives optimizing their computation tree in three different ways are applied to the design of the PRIDE 4-bit substitution box, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals has shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction ( $times 25$ ), compared to their CMOS-based counterparts in 65 nm, which is a significant advance in the development of secure circuits with TFETs.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage

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      Authors: Nikhil Rangarajan;Johann Knechtel;Dinesh Rajasekharan;Ozgur Sinanoglu;
      Pages: 103 - 106
      Abstract: Memory security has recently come into the spotlight as attackers have stepped up their efforts to gain illicit access to sensitive data or cause denial-of-memory service via a variety of avenues, such as cold boot attacks, bus snooping, and physical probing or tampering. In this letter, we propose SuperVAULT, a novel secure storage solution for protecting secret data/keys by exploiting the superparamagnetic regime of nanomagnets. Through materials and dimensional engineering of the magnetic tunnel junction (MTJ) free layer, the energy barrier of spin-transfer torque magnetoresistive random-access memory (STT-MRAM) cells can be designed to lie in the range of the thermal energy ( ${k_{textrm {B}}T}$ ). Such superparamagnetic MTJ (s-MTJ) cells, with an ${mathcal {O}}$ (10 ns) retention time, need to be refreshed frequently. In the absence of data refresh (under attack conditions), the data they hold is thermally corrupted to a random state after an arbitrary but short amount of time. We leverage this property to devise a secure memory primitive and showcase its potential against cold boot and Boolean satisfiability (SAT) attacks. Further, the overheads for s-MTJ-based STT-MRAMs are shown to be promising for on-chip implementations.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
  • Reconfigurable Field Effect Transistors Design Solutions for
           Delay-Invariant Logic Gates

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      Authors: Giulio Galderisi;Thomas Mikolajick;Jens Trommer;
      Pages: 107 - 110
      Abstract: Reconfigurable field effect transistors (RFETs) are an emerging technology platform that offers the possibility to merge ${n}$ -type and ${p}$ -type functionalities in a single device. From the circuit perspective, this feature enables layout camouflaged designs by realizing polymorphic logic gates with dynamically reconfigurable functions. In this work, mixed-mode simulations employing a technology computer-aided design (TCAD) model of RFETs with three gates are presented. Three different designs for reconfigurable NAND/NOR logic gates are analyzed in order to optimize the equalization of both operational modes delay traces. Moreover, work function fluctuations arising from process variations are considered to prove that their inevitable presence can be exploited to further increase the level of obfuscation between those modes. Statistical analysis of the results from 100 simulated devices shows effective overlapping of the distribution of the delays extracted at half the value of the drain voltage. Together with a good resilience against supply voltage variations in fault induction attacks schemes, these results suggest how this emerging technology can grow up and evolve to play an interesting role in the field of hardware security.
      PubDate: June 2022
      Issue No: Vol. 14, No. 2 (2022)
       
 
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