 Subjects -> ELECTRONICS (Total: 207 journals)
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- IEEE Embedded Systems Letters Publication Information
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PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- Enhancing Perceptual Experience of Video Quality in Drone Communications
by Using VPN Bonding-
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Authors:
Roberta Avanzato;Francesco Beritelli;Corrado Rametta;
Pages: 1 - 4
Abstract: Recently, drones are increasingly being used as innovative IoT sensors. The application contexts of UAV systems where there is often a need to transmit time-critical data between the drone and the Internet are increasingly numerous and varied. Keeping this in mind and assuming that most professional UAVs are equipped with multiinterface routers and use virtual private networks (VPNs) to ensure reliable, robust, and secure transmission to the operation room, this letter presents a technique to enhance real-time and time-critical communications such as real-time video streaming. An embedded system, Raspberry-based gateway prototype, was used to create a testbed using a professional drone that captured and transmitted real-time video during a 30-min flight over a rural area characterized by poor mobile radio coverage. A perceptual video quality assessment tool, video multimethod assessment fusion (VMAF), has been employed to evaluate the improvement in terms of video quality perceived by the operator.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- Area-Optimized Constant-Time Hardware Implementation for Polynomial
Multiplication-
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Authors:
Safiullah Khan;Wai-Kong Lee;Ayesha Khalid;Abdul Majeed;Seong Oun Hwang;
Pages: 5 - 8
Abstract: This work presents a lightweight, FPGA-based hardware implementation for polynomial multiplication, which is the major bottleneck in the NTRU public-key cryptographic scheme. NTRU is a quantum-resilient, lattice-based key exchange cryptosystem, and is currently a finalist in the ongoing National Institute of Standards and Technology post-quantum cryptography standardization. It is challenging to fit these quantum-resilient schemes into Internet of Things (IoT) sensor nodes due to the strict resource constraints (smaller area, less memory, and lower energy budgets) and the limited computational capabilities in embedded devices. We undertake this compact implementation for polynomial multiplication with two motivations: 1) constant-time implementation ensuring inherent security against timing side-channel attacks and 2) optimized hardware consumption to make it suitable for IoT applications. A single-step multiplexer-based iterative architecture is proposed to achieve both goals simultaneously. Compared to the architectures presented in the literature, our proposed work eliminates the utilization of a modular arithmetic unit and replaces it with the correct selection of input followed by an accumulator, which can help to save substantial device resources. Experimental results with an FPGA show that our proposed architecture achieves an area reduction of up to $2.86 times $ and the throughput increase up to $1.23 times $ compared to the state-of-the-art implementation strategies, providing comparable latency along with an inherent-timing attack resilience that is absent in several NTRU hardware implementation schemes.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence
and Prefetch-Control Mechanism-
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Authors:
Soma Niloy Ghosh;Vineet Sahula;Lava Bhargava;
Pages: 9 - 12
Abstract: We propose a hardware technique for cache coherence over the existing approaches that ensure that shared and less frequently used cache blocks bypass private caches of multiple cores. Furthermore, this manuscript proposes a mechanism to tune the aggressiveness of a data prefetcher. Increased cache hit rate and improved performance have been observed since coherence management and prefetching delays are avoided using the proposed bypassing and thread progress-aware prefetch controlling mechanism. Our approach shows around 19% improvement in cache hit rate and 29% average performance improvement over existing state-of-the-art techniques for Parsec & Splash-2 multithreaded benchmarks.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- A Traceability Localization Method of Acoustic Attack Source for MEMS
Gyroscope-
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Authors:
Tao Liu;Zhen Hong;Huan Chen;
Pages: 13 - 16
Abstract: The malicious acoustic attack can easily cause the failure of micro-electro mechanical systems (MEMS) sensors. It can use ultrasonic waves to attack the MEMS gyroscope over long distances. This type of attack is highly hidden and harmful. Therefore, the purpose of this letter is to locate malicious sources and facilitate the eradication of the threat. We designed a prototype system to simulate an ultrasonic attack on an MEMS gyroscope, which can collect and analyze the state of the gyroscope after being attacked. Furthermore, we proposed $sigma $ -standard deviation-based feature extraction, and then designed a neural-network-based traceability location method to seek for attacker’s location. The experimental results indicate that our approach can effectively and accurately locate the malicious acoustic source location.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- FPGA Implementation of Batch-Mode Depth-Pipelined Two Means Decision Tree
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Authors:
Rituparna Choudhury;Shaik Rafi Ahamed;Prithwijit Guha;
Pages: 17 - 20
Abstract: Decision tree for classification tasks are learned from the input dataset and consist of split nodes and leaf nodes. This letter presents the hardware implementation of learning of two means decision tree (TMDT). To accommodate large-size datasets and hence, to increase accuracy, the training data is divided into small batches and one batch at a time is loaded into chip memory. The hardware is divided into two pipelines to optimize timing and resource consumption. The critical path of the architecture enables the field-programmable gate array (FPGA) to operate with maximum frequency of 62 MHz. Simulation results show that the proposed FPGA runs at least $27times $ and $26times $ faster than the C implementation and existing hardware, respectively.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- Novel Low Memory Footprint DNN Models for Edge Classification of
Surgeons’ Postures-
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Authors:
Alex Hanneman;Terry Fawden;Marco Branciforte;Maria Celvisia Virzì;Esther L. Moss;Luciano Ost;Massimiliano Zecca;
Pages: 21 - 24
Abstract: Skill assessment is fundamental to enhance current laparoscopic surgical training and reduce the incidence of musculoskeletal injuries from performing these procedures. Recently, deep neural networks (DNNs) have been used to improve human posture and surgeons’ skills training. While they work well in the lab, they normally require significant computational power which makes it impossible to use them on edge devices. This letter presents two low memory footprint DNN models used for classifying laparoscopic surgical skill levels at the edge. Trained models were deployed on three Arm Cortex-M processors using the X-Cube-AI and Tensorflow Lite Micro (TFLM) libraries. Results show that the CUBE-AI-based models give the best relative performance, memory footprint, and accuracy tradeoffs when executed on the Cortex-M7.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- Communication-Efficient Federated Learning With Gradual Layer Freezing
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Authors:
Erich Malan;Valentino Peluso;Andrea Calimera;Enrico Macii;
Pages: 25 - 28
Abstract: Federated learning (FL) is a collaborative, privacy-preserving method for training deep neural networks at the edge of the Internet of Things (IoT). Despite the many advantages, existing FL implementations suffer high communication costs that prevent adoption at scale. Specifically, the frequent model updates between the central server and the many end nodes are a source of channel congestion and high energy consumption. This letter tackles this aspect by introducing federated learning with gradual layer freezing (FedGLF), a novel FL scheme that gradually reduces the portion of the model sent back and forth, relieving the communication bundle yet preserving the quality of the training service. The results collected on two image classification tasks learned with different data distributions prove that FedGLF outperforms conventional FL schemes, with data volume savings ranging from 14% to 59% or up to 2.5% higher accuracy.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge
Computing'-
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Authors:
Paul R. Genssler;Austin Vas;Hussam Amrouch;
Pages: 29 - 32
Abstract: Brain-inspired hyperdimensional computing (HDC) is an emerging machine learning (ML) method. It is based on large vectors of binary or bipolar symbols and a few simple mathematical operations. The promise of HDC is a highly efficient implementation for embedded systems, such as wearables. While fast implementations have been presented, other constraints have not been considered for edge computing. In this work, we aim at answering how thermal-friendly HDC for edge computing is. Devices, such as smartwatches, smart glasses, or even mobile systems have a restrictive cooling budget due to their limited volume. Although HDC operations are simple, the vectors are large, resulting in a high number of CPU operations and, thus, a heavy load on the entire system potentially causing temperature violations. In this work, the impact of HDC on the chip’s temperature is investigated for the first time. We measure the temperature and power consumption of a commercial embedded system and compare HDC with the conventional convolutional neural network (CNN). We reveal that HDC causes up to 6.8°C higher temperatures and leads to up to 47% more CPU throttling. Even when both HDC and CNN aim for the same throughput (i.e., perform a similar number of classifications per second), HDC still causes higher on-chip temperatures due to the larger power consumption.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation
of Computer Architectures-
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Authors:
Ayoub Sadeghi;Razieh Ghasemi;Hossein Ghasemian;Nabiollah Shiri;
Pages: 33 - 36
Abstract: Approximate computing (AC) is an emerging technique in arithmetic circuits. In this letter, a new AC-based full adder (FA) circuit is presented with 12 transistors, 150mm]Please confirm or add details for any funding or financial support for the research of this article. -160mm]If you haven’t done so already, please make sure you have submitted a video graphical abstract (GA) for your paper, along with a caption and overlay image. The GA will be displayed on your articles abstract page on IEEE Xplore. Note that captions cannot exceed 1800 characters (including spaces). Overlay images are usually a screenshot of your video that best represents the video. This is for readers who may not have access to video-viewing software. 0.239 $mu text{m}^{2}$ of area, and two errors in the outputs. In the proposed FA, the gate diffusion input (GDI) and dynamic-threshold (DT) techniques are applied using the carbon nanotube field-effect transistor (CNTFET) technology. Accuracy metrics, such as normalized mean error distance (NMED) and mean relative error distance (MRED) along with circuitry parameters of power-delay-product (PDP), energy-delay-product (EDP), and power-delay-area-product (PDAP), confirm the efficiency of the proposed FA for complex structures. The proposed FA is embedded in a ripple carry adder (RCA) by various numbers of approximate bits (NABs), and then the accuracy and circuitry parameters are extracted. Compared to the state-of-the-art designs, the high-efficient behavior of the proposed FA is proved when it is used in image processing applications.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- EnHDC: Ensemble Learning for Brain-Inspired Hyperdimensional Computing
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Authors:
Ruixuan Wang;Dongning Ma;Xun Jiao;
Pages: 37 - 40
Abstract: Recently, brain-inspired hyperdimensional computing (HDC) becomes an emerging computational scheme that has achieved success in various domains, such as human activity recognition, voice recognition, and bio-medical signal classification. HDC mimics the brain cognition and leverages high-dimensional vectors (e.g., 10 000 dimensions) with fully distributed holographic representation and (pseudo-)randomness. Ensemble learning is a classical learning method utilizing a group of weak learners to form a strong learner, which aims to increase the accuracy of the model. This letter presents a systematic effort in exploring ensemble learning in the context of HDC and proposes an ensemble HDC model referred to as EnHDC. EnHDC uses a majority voting-based mechanism to synergistically integrate the prediction outcomes of multiple base HDC classifiers. To enhance the diversity of base classifiers, we vary the encoding mechanisms, dimensions, and data width settings among base classifiers. By applying EnHDC on a wide range of applications, results show that EnHDC can achieve on average 3.2% accuracy improvement over a single HDC classifier. Further, we show that EnHDC with reduced dimensionality can achieve similar or even surpass the accuracy of baseline HDC with higher dimensionality. This leads to a 20% reduction of storage requirement of the HDC model, which can enhance the efficiency of HDC enabled on low-power computing platforms.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- An Efficient Self-Healing Architecture for Improving the RAS
Characteristics of RISC-V Server and Its Quantitative Evaluation Method-
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Authors:
Chengbo Zhang;Peiyong Zhang;Shengrui Zheng;Zhao Yang;Rui Liu;Kaitian Huang;
Pages: 41 - 44
Abstract: This letter proposes a self-healing called automatic monitoring architecture (AMA), which can help RISC-V server self-heal from hardware errors. AMA reduces redundant error classification, and only monitors hardware devices that have a relatively large proportion of errors in RISC-V server, thereby reducing the resource consumption of AMA on the basis of ensuring performance. In addition, AMA uses the Correctable-error Dynamic Threshold technology to further reduce the probability of serious uncorrectable hardware errors. Compared with an RISC-V server without a self-healing system, this architecture consumes very few hardware resources, reducing server downtime by about 80% each year. Compared with other self-healing architectures, such as Intel’s machine check architecture, AMA can reduce server downtime by an additional 5% per year. Therefore, AMA is highly efficient with little resource consumption.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of
Encrypted Nonvolatile Main Memories-
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Authors:
Arijit Nath;Hemangee K. Kapoor;
Pages: 45 - 48
Abstract: Nonvolatile memories are widely considered as a potential replacement of DRAM in main memory due to their high density and low-leakage power consumption. The data in these memories are stored in encrypted form to protect them from data stealing. However, the encryption techniques, on account of their diffusion property impose high randomization in the generated encrypted data. It leads to enormous bit-flips in the memory cells, leading to their early wear out. In this letter, we propose a technique called CADEN that combines our compression technique COMF with an adaptive encoding scheme. The compressed data generated by COMF is encoded in finer granularity using an adaptive encoding approach at low storage overhead. Experimental evaluation shows that CADEN reduces bit-flips and improves lifetime in PCM main memory compared to baseline and existing techniques. In particular, CADEN shows 52% and 57% reduction in bit-flips and energy consumption and $2.31times $ improvement in lifetime over baseline.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
- A Novel Mapping of ECG and PPG to Ensure the Safety of Health Monitoring
Applications-
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Authors:
Abhinandan Panda;Srinivas Pinisetty;Partha Roop;
Pages: 49 - 52
Abstract: Biophysical signals, such as electrocardiogram (ECG) and photoplethysmogram (PPG) are key to the sensing of vital parameters for wellbeing. Coincidentally, both ECG and PPG provide a different window into the same phenomena, namely, the cardiac cycle. However, they are used separately for various health monitoring tasks, which often have safety implications. As these sensors are subject to errors and failures, there is a need to develop methods that consider both sensors so as to enhance the safety of the health monitoring application. Considering this, we present the first approach to establish the key relationships between ECG and PPG signals formally. We combine formal runtime monitoring with statistical analysis and regression analysis for our results.
PubDate:
March 2023
Issue No: Vol. 15, No. 1 (2023)
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