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IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Prestige (SJR): 0.869
Citation Impact (citeScore): 4
Number of Followers: 45  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1057-7122 - ISSN (Online) 1549-8328
Published by IEEE Homepage  [228 journals]
  • IEEE Transactions on Circuits and Systems--I: Regular Papers Publication
           Information

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • IEEE Circuits and Systems Society Information

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Proximity Wireless Communication Technologies: An Overview and Design
           Guidelines

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      Authors: Atsutake Kosuge;Tadahiro Kuroda;
      Pages: 4317 - 4330
      Abstract: This paper presents an overview of proximity wireless communication (PWC) technologies, their principles, design guidelines and practical applications. In particular, two different applications of PWC are reviewed. One is PWC between stacked chips. Both communication distance and coupler size are several tens of microns. Area and energy efficient design techniques are introduced. Another is PWC between module boards. Both communication distance and coupler size are several millimeters. Energy and area efficient practical designs are introduced for mobile and industrial machinery applications.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • APCCAS 2021 Guest Editorial

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      Authors: Yong Chen;Harikrishnan Ramiah;
      Pages: 4331 - 4331
      Abstract: Welcome to the Special Issue Based on the 17th Edition of the Asia Pacific Conference on Circuits and Systems.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Digraph Filter Design Based on Directed Laplacian Matrix and Least Squares
           Method

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      Authors: Chien-Cheng Tseng;Su-Ling Lee;
      Pages: 4332 - 4344
      Abstract: In this paper, the digraph filter design based on directed Laplacian matrix (DLM) and least squares method is presented. First, the eigen-decomposition of DLM is used to define the digraph Fourier transform (DGFT). Then, the spectral properties of DGFT are studied and applied to specify the ideal spectral response of the digraph filter. Next, the coefficients of polynomial and rational digraph filters are determined by the least squares method which minimizes the integral absolute squared errors between ideal response and actual spectral response of filter. The matrix inversion can be used to compute the optimal solution. Finally, the proposed method is compared with conventional design methods to evaluate performance and the signal denoising application examples are demonstrated to show the effectiveness of the designed digraph filters.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G
           Short-Reach Optical Interconnects

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      Authors: Jian He;Donglai Lu;Haiyun Xue;Sikai Chen;Han Liu;Leliang Li;Guike Li;Zhao Zhang;Jian Liu;Liyuan Liu;Nanjian Wu;Ningmei Yu;Fengman Liu;Xi Xiao;Yong Chen;Nan Qi;
      Pages: 4345 - 4357
      Abstract: This paper presents a hybrid-integrated optical transceiver front-end for beyond-400G short-reach optical links. A pair of the monolithic 8-channel laser drivers and the trans-impedance amplifier (TIA) is developed in 180nm SiGe BiCMOS, incorporating arrayed Vertical-Cavity-Surface- Emitting Lasers and photo-detectors. The driver uses a $2^{mathrm {nd}}$ -order continuous-time linear equalizer (CTLE) to compensate for the channel loss with a nonlinear frequency response. Both the inductive peaking and RC-degeneration are embedded at the output stage to extend the optical modulation bandwidth (BW). The series-peaking and multi-stage distributed CTLE are combined in a resistive feedback TIA topology for improved BW and linearity. Measurement results show up to 100-Gb/s PAM-4 electrical eyes of the driver and TIA. The optical transmitter front-end operates 56 Gb/s, 4.1-dB extinction ratio, and 6.6-pJ/bit power efficiency, while the optical receiver front-end achieves 56-Gb/s, $10^{-6}$ bit error rate, and 5.9-pJ/bit power efficiency.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Area-Efficient Finite Field Multiplication Using Hybrid SET-MOS Technology

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      Authors: Chen Zhang;Huapeng Wu;Chunhong Chen;
      Pages: 4358 - 4366
      Abstract: Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores Karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM
           Matrix Computing Circuits

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      Authors: Yubiao Luo;Shiqing Wang;Pushen Zuo;Zhong Sun;Ru Huang;
      Pages: 4367 - 4380
      Abstract: Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for
           Efficient GaN HEMT Power Converters

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      Authors: Mousa Karimi;Mohamed Ali;Amir Aghajani;Ahmad Hassan;Mohamad Sawan;Benoit Gosselin;
      Pages: 4381 - 4394
      Abstract: This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ( $text{C}_{mathrm {L}}$ ) and operating frequencies ( ${f}_{mathrm {s}}$ ). The circuit consumed a power between 610 $mu text{W}$ and $850~mu text{W}$ across the measured deadtime ranges while $text{C}_{mathrm {L}} =12$ pF, $text{V}_{mathrm {dd}} =3.3$ V, and $text{f}_{mathrm {s}}=200$ kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of $150mu $ m $times 260mu text{m}$ . The fabricated chip is connected to a buck converter to validate the operation of the proposed circu-t. The efficiency of a typical buck converter with minimum $text{T}_{mathrm {DLH}}$ and optimal $text{T}_{mathrm {DHL}}$ at $text{I}_{mathrm {Load}} =25$ mA is improved by 12% compared to a converter with a fixed deadtime of $text{T}_{mathrm {DLH}} =,,text{T}_{mathrm {DHL}} =12$ ns.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Reconfigurable Filtering Power Divider With Arbitrary Operating Channels
           Based on External Quality Factor Control

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      Authors: Jin-Xu Xu;Mo Huang;Wan-Li Zhan;Xiu Yin Zhang;
      Pages: 4395 - 4403
      Abstract: In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ( $Q_{mathbf {e}}$ ) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{mathbf {e}}$ values. Design theories for obtaining the desired $Q_{mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With

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      Authors: Athanasios T. Ramkaj;Marcel J. M. Pelgrom;Michiel S. J. Steyaert;Filip Tavernier;
      Pages: 4404 - 4414
      Abstract: This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5 $text{m}text {V}_{text {pp}}$ differential input ( $Delta V_{textrm {I}}$ ) at 0.5 V common-mode ( $V_{textrm {CM}}$ ) and 1V supply ( $V_{textrm {DD}}$ ). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a < 70ps delay down to 0.6 V $V_{textrm {DD}}$ . The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Phase Noise Analysis of Separately Driven Ring Oscillators

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      Authors: Neeraj Mishra;Anchit Proch;Lomash Chandra Acharya;Jeffrey Prinzie;Sudipto Chakraborty;Rajiv Joshi;Sudeb Dasgupta;Anand Bulusu;
      Pages: 4415 - 4428
      Abstract: In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering
           DACs

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      Authors: Daniel Beauchamp;Keith M. Chugg;
      Pages: 4429 - 4442
      Abstract: This work presents analysis and calibration of interleaving and data timing errors that are encountered in modern times-2 interleaved digital-to-analog converters (DACs) with a current-steering (CS) architecture. Such errors corrupt the DAC output spectrum with spectral images that require calibration. We develop an analytical model for the interleaving and data timing errors that we understand are most significant and propose a calibration algorithm that treats all of them. Extensive simulations of the algorithm are made possible by leveraging the speed and accuracy of the analytical model. The algorithm is demonstrated on a commercially-developed 10-bit times-2 interleaved CS-DAC, operating at 40GS/s in 14nm CMOS.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and
           Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS

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      Authors: Xiangyu Mao;Yan Lu;Rui P. Martins;
      Pages: 4443 - 4452
      Abstract: This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the $text{V}_{mathrm {OUT}}$ error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- $mu text{V}$ /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Highly Linear Ka-Band GaN-on-Si Active Balanced Mixer for Radar
           Applications

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      Authors: Alessandro Cidronali;Lorenzo Pagnini;Giovanni Collodi;Marco Passafiume;
      Pages: 4453 - 4464
      Abstract: A highly linear active mixer in Gallium Nitride on Silicon (GaN-on-Si) monolithic microwave integrated circuit (MMIC) technology, operating in Ka-band for radar applications is introduced. It exhibits a local oscillator (LO) balanced topology of gate-pumped mixers based on high-electron mobility transistors (HEMT) and operates in down-conversion mode. Its design principles and the theoretical foundation of its linearity features resulting from both the high power handling capability of GaN-on-Si HEMTs and the corresponding high applied LO level are presented. An extensive characterization based on excitation of a prototype by broadband continuous wave signals and frequency modulated continuous wave signals validates both the analytical treatment of its linearity and the design of the prototype of the mixer. In the 35–40 GHz operating band, this prototype exhibits a state-of-the-art input referred third order intercept point that reaches 39.1 dBm, and a maximum input referred second order intercept point of 39.4 dBm, with a corresponding conversion gain of −5.2 dB, and LO level of 24 dBm.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM
           to Reduce Weight Loading Energy of Neural Networks

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      Authors: He Zhang;Junzhan Liu;Jinyu Bai;Sai Li;Lichuan Luo;Shaoqian Wei;Jianxin Wu;Wang Kang;
      Pages: 4465 - 4474
      Abstract: SRAM based computing-in-memory (SRAM-CIM) techniques have been widely studied for neural networks (NNs) to solve the “Von Neumann bottleneck”. However, as the scale of the NN model increasingly expands, the weight cannot be fully stored on-chip owing to the big device size (limited capacity) of SRAM. In this case, the NN weight data have to be frequently loaded from external memories, such as DRAM and Flash memory, which results in high energy consumption and low efficiency. In this paper, we propose a hybrid-device computing-in-memory (HD-CIM) architecture based on SRAM and MRAM (magnetic random-access memory). In our HD-CIM, the NN weight data are stored in on-chip MRAM and are loaded into SRAM-CIM core, significantly reducing energy and latency. Besides, in order to improve the data transfer efficiency between MRAM and SRAM, a high-speed pipelined MRAM readout structure is proposed to reduce the BL charging time. Our results show that the NN weight data loading energy in our design is only 0.242 pJ/bit, which is 289 $times $ less in comparison with that from off-chip DRAM. Moreover, the energy breakdown and efficiency are analyzed based on different NN models, such as VGG19, ResNet18 and MobileNetV1. Our design can improve $mathbf {58times ,,to,,124times }$ energy efficiency.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Memristor-Based Neural Network Circuit of Operant Conditioning Accorded
           With Biological Feature

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      Authors: Junwei Sun;Juntao Han;Yanfeng Wang;Peng Liu;
      Pages: 4475 - 4486
      Abstract: Most memristor-based associative memory neural networks are focused on classical conditioning and ignored operant conditioning. In this paper, a memristor-based neural network of operant conditioning accorded with biological feature is designed. The designed circuit includes a voltage control module, an operant module and synapse modules. It realizes learning, forgetting, long-term memory, reinforcement and punishment functions based on variable synapse structure and double self-protection measure. Meanwhile, the four factors that affect operant conditioning such as contingency, immediacy, magnitude and deprivation are discussed and implemented. The simulation results in PSPICE show that the circuit can be used to simulate actual conditioned reflex and complicated applications. The memristor-based neural network circuit of operant conditioning provides more references for further development of neural networks.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro
           for Deep Neural Network Based on Nonvolatile Memory

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      Authors: Lixia Han;Peng Huang;Yijiao Wang;Zheng Zhou;Yizhou Zhang;Xiaoyan Liu;Jinfeng Kang;
      Pages: 4487 - 4498
      Abstract: Nonvolatile memory (NVM) based neural network can directly perform in situ computation in memory to significantly reduce energy consumption resulting from the data movement. However, the energy consumption by the analog-to-digital converter (ADC) restricts the efficiency of the mixed-signal in-memory computing macro. The rate coding spike-driven in-memory computing macro can increase the energy efficiency via eliminating the ADC, but the improvement is limited because substantial energy is consumed for the coding of multiple spikes. In this work, we propose a discrete temporal coding spike-driven in-memory computing macro, including input coding scheme, weight mapping method, and improved leaky integrate-and-fire (LIF) neuron circuit, to perform the efficient forward inference of deep neural networks based on NVM array. We then optimize the designment of the proposed in-memory computing macro to mitigate the neural network accuracy loss due to the nonlinearity of the LIF neuron and voltage drop caused by interconnect resistance. Because the temporal coding scheme reduces spike numbers and the improved-LIF circuit simultaneously integrates two bit-lines current corresponding to positive and negative weight, the proposed macro achieves 46.63TOPS/W energy efficiency and 1.92TOPS throughput for 3bit temporal coding precision.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Family of ΔΣ Modulators With High Spur Immunity and Low Folded
           Nonlinearity Noise When Used in Fractional- Frequency Synthesizers

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      Authors: Valerio Mazzaro;Michael Peter Kennedy;
      Pages: 4499 - 4509
      Abstract: Phase locked loops for fractional frequency synthesis typically use Digital $Delta Sigma $ Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional- ${N}$ frequency synthesizers with polynomial nonlinearities.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Accurate Design Method for Millimeter Wave Distributed Amplifier Based on
           Four-Port Chain (ABCD) Matrix Model

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      Authors: Mohamad El-Chaar;Loic Vincent;Jean-Daniel Arnould;Antonio A. L. de Souza;Sylvain Bourdel;Florence Podevin;
      Pages: 4510 - 4523
      Abstract: This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ( $mathrm {P}_{mathrm {DC}}$ ), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs $ge80$ GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ( $mathrm {P}_{mathrm {DC}}$ ) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per $mathrm {P}_{mathrm {DC}}$ ( ${mathrm {GBP}} mathord {left /{ {vphantom {{mathrm {GBP}} mathrm {P}_{mathrm {DC}}}} }right. } mathrm {P}_{mathrm {DC}}$ ) of 6.01 GHz/mW while being power-efficient.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Energy-Quality Scalable Design Space Exploration of Approximate FFT
           Hardware Architectures

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      Authors: Pedro Tauã Lopes Pereira;Patrícia Ücker Leleu da Costa;Guilherme da Costa Ferreira;Brunno Alves de Abreu;Guilherme Paim;Eduardo Antônio Ceśar da Costa;Sergio Bampi;
      Pages: 4524 - 4534
      Abstract: This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (AxM) combined with approximate adder (AxA) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of AxMs – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), leading one Bit-based Approximate (LoBA), and Truncated approach – jointly with the LOA, ETA-I, CopyA, CopyB, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the ${L}$ and ${K}$ least-significant bits, respectively, for the AxM and AxA), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining ${L}$ and ${K}$ variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the LoBA multiplier with $L$ =8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for
           High-Performance Computing in Memory Architecture

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      Authors: Jinkai Wang;Yining Bai;Hongyu Wang;Zuolei Hao;Guanda Wang;Kun Zhang;Youguang Zhang;Weifeng Lv;Yue Zhang;
      Pages: 4535 - 4545
      Abstract: Computing in memory (CIM) is a promising candidate for high throughput and energy-efficient data-driven applications, which mitigates the well-known memory bottleneck in Von Neumann architecture. In this paper, we present a reconfigurable bit-serial operation using toggle spin-orbit torque magnetic random access memory (TSOT-MRAM) to perform the computation completely in the bit-cell array instead of in a peripheral circuit. This bit-serial CIM (BSCIM) scheme achieves higher throughput and energy efficiency in CIM. First, basic Boolean logic operations are realized by utilizing the feature of TSOT device. A bit-cell array that implements the bit-serial operation is then built to provide the communication between column and row necessary for arithmetic operations, such as the carry propagation of addition and multiplication. Finally, we analyze the reliability of BSCIM scheme and demonstrate the performance advantage by performing convolution operations for $28times 28$ handwritten digit images in a BSCIM architecture. The results show that the delay and energy of BSCIM architecture are respectively reduced by 1.16-5.49 times and 1.12-1.43 times compared with the existing digital CIM architectures. Besides, its throughput and energy efficiency are also enhanced to 51.2 GOPS and 9.9 TOPS/W respectively.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Inner Product Computation In-Memory Using Distributed Arithmetic

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      Authors: Vijaya Lakshmi;Vikramkumar Pudi;John Reuben;
      Pages: 4546 - 4557
      Abstract: In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves $approx 60$ % energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Characterizing Approximate Adders and Multipliers for Mitigating Aging and
           Temperature Degradations

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      Authors: Francisco Javier Hernandez Santiago;Honglan Jiang;Hussam Amrouch;Andreas Gerstlauer;Leibo Liu;Jie Han;
      Pages: 4558 - 4571
      Abstract: The performance of nanoscale semiconductor technologies has become susceptible to high temperatures and aging phenomena. While guard-bands have conventionally been used to combat degradation-induced timing violations, approximations have recently been leveraged to compensate for degradations in lieu of adding timing guard-bands, without a loss in performance. However, only simple approximation techniques such as truncation have been considered in prior work. In this paper, a wide range of approximate arithmetic circuits including adders and multipliers using various sophisticated approximation techniques are investigated to cope with aging- and temperature-induced degradations. To this end, approximate circuits are first characterized for their delay increase under degradations. With this, we then determine the approximation level required to compensate for guard-bands under different degradations. Degradation-aware logic synthesis results show that the simple use of truncated arithmetic circuits leads to a higher quality loss compared to using other approximate circuits. However, a truncated multiplier has the lowest error distance towards a reliable operation in 10 years. The approximate multipliers with configurable error recovery are most suitable when the level of degradation is higher, e.g., at a temperature of 70 °C. The characterization of degradation at the circuit level is then used for design exploration at the architecture level without the need for further gate-level simulations. For three different image processing applications, experimental results show that guard-bands can be mitigated while maintaining an output result with a high visual quality.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • An Efficient Unstructured Sparse Convolutional Neural Network Accelerator
           for Wearable ECG Classification Device

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      Authors: Jiahao Lu;Dongsheng Liu;Xuan Cheng;Lai Wei;Ang Hu;Xuecheng Zou;
      Pages: 4572 - 4582
      Abstract: Convolution neural network (CNN) with pruning techniques has shown remarkable prospects in electrocardiogram (ECG) classification. However, efficiently deploying the existing pruned neural network to wearable devices for ECG classification is a great challenge due to the limited hardware resource and randomly distributed sparse weights. To address this issue, an efficient unstructured sparse CNN accelerator is proposed in this paper. A tile-first dataflow with compressed data storage format is presented to skip zero weight multiplications and increase the computing efficiency during inference of small-scale model with large sparsity. The two-level weight index matching structure in the dataflow exploits shifting operation to select valid data pairs and maintain the fully-pipelined calculation process. A configurable processing element (PE) array with 32-bit instruction control is proposed to increase the flexibility of the accelerator. Verified in FPGA and post-synthesis simulations in SMIC 40nm process, the proposed sparse CNN accelerator consumes $3.93~mu $ J/classification at 2MHz clock frequency and it achieves an averaged ECG classification accuracy of 98.99%. A computing efficiency of 118.75% is realized which is improved by 48% compared to the dense baseline. In brief, the proposed efficient CNN accelerator is especially suitable for wearable ECG classification device.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Model-Based Approach Digital Pre-Distortion Method for Current-Steering
           Digital-to-Analog Converters

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      Authors: Patrick Valet;David Schwingshackl;Ulrich Gaier;Andrea M. Tonello;
      Pages: 4583 - 4595
      Abstract: This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Edge of Chaos Is Sine Qua Non for Turing Instability

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      Authors: Alon Ascoli;Ahmet Samil Demirkol;Ronald Tetzlaff;Leon Chua;
      Pages: 4596 - 4609
      Abstract: Diffusion-driven instabilities with pattern formation may occur in a network of identical, regularly-spaced, and resistively-coupled cells if and only if the uncoupled cell is poised on a locally-active and stable operating point in the Edge of Chaos domain. This manuscript presents the simplest ever-reported two-cell neural network, combining together only 7 two-terminal components, namely 2 batteries, 3 resistors, and 2 volatile NbOx memristive threshold switches from NaMLab, and subject to diffusion-driven instabilities with the concurrent emergence of Turing patterns. Very remarkably, this is the first time an homogeneous cellular medium, with no other dynamic element than 2 locally-active memristors, hence the attribute all-memristor coined to address it in this paper, is found to support complex phenomena. The destabilization of the homogeneous solution occurs in this second-order two-cell array if and only if the uncoupled cell circuit parameters are chosen from the Edge of Chaos domain. A deep circuit- and system-theoretic investigation, including linearization analysis and phase portrait investigation, provides a comprehensive picture for the local and global dynamics of the bio-inspired network, revealing how a theory-assisted approach may guide circuit design with inherently non-linear memristive devices.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Design Space Exploration of Interconnect Materials for Cryogenic
           Operation: Electrical and Thermal Analyses

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      Authors: Rakshith Saligram;Suman Datta;Arijit Raychowdhury;
      Pages: 4610 - 4618
      Abstract: With Copper (Cu) Interconnects causing performance bottleneck at single nanometer nodes due to increase in resistivity size effects viz., grain boundary scattering and surface scattering, there has always been scavenging for alternate interconnect materials. Although the Cu resistivity value decreases at cryogenic temperature, the problems continue to persist. In this work, we study three alternate interconnect materials specifically for 77K High Performance Compute applications. We select the materials based on their resistivity value at 77K for 7nm node computed using Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models. We analyze the delay of the interconnects, understand repeater insertion as a function of wire length, evaluate repeater count and energy at system level and perform IR drop analysis by showing through detailed analytical models that Ru, Rh and Al can provide appreciable improvements over Cu at 77K. The delay of interconnects reduces by 1-3.75% for Ru, 1.5-7.25% for Rh and 4.4-17.8% for Al across the BEOL stack while repeater counts decrease by 10%, 15% and 37% for Ru, Rh and Al respectively at 77K. We investigate thermal and reliability aspects of interconnect design including electromigration, Joule Heating and maximum allowed current densities again proving that Ru (9%), Rh (18%) and Al (63%) outperform Cu at 77K. Finally, we study the effects of various Low-k dielectric materials on the interconnect capacitance and thermal behavior for Cu as well as three alternate materials noting that, even though thermal conductivity of dielectrics decrease at 77K, the Joule Heating will not be as worse as one might expect.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Field-Coupled Nanocomputing Placement and Routing With Genetic and
           A* Algorithms

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      Authors: Yangshuai Li;Guangjun Xie;Qian Han;Xiaoshuai Li;Gaisheng Li;Bing Zhang;Fei Peng;
      Pages: 4619 - 4631
      Abstract: Field-Coupled Nanocomputing technologies have great potential to surpass CMOS technology because of their lower power consumption and higher device concentration. To ease the burden of placement and routing (P&R) problems for FCN circuits, many delicate two-dimensional clocking schemes have been proposed, upon which algorithms can solve the P&R problems more strategically. In this paper, we propose a two-level optimization strategy by using a genetic algorithm (GA) combined with an enhanced A* algorithm. Some circuit design requirements, such as clock synchronization, layout area, etc., are cleverly designed in the fitness value function of the GA. Numerical results demonstrate the effectiveness of the hybrid algorithm. In particular, compared to current tools, such as fiction and Ropper, the proposed algorithm can achieve an optimal solution with a higher success rate and a sizeable applicable circuit scale. In addition, the concept of design rule checking (DRC) was proposed in FCN and integrated into the algorithm, making the P&R results mapping from gate-level to cell-level more smoothly. Besides, the number of cross wires is significantly reduced, and the distribution of IO ports can be more effectively controlled.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Fixed-Time Disturbance Observer-Based Control for Quadcopter Suspension
           Transportation System

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      Authors: Wei Liu;Mou Chen;Peng Shi;
      Pages: 4632 - 4642
      Abstract: By considering the under-actuated characteristics of the quadcopter suspension transportation system and the external disturbance, the effective tracking control of the quadrotor transportation system faces great difficulties and challenges. An adaptive hierarchical sliding mode control (HSMC) scheme based on fixed-time sliding mode disturbance observer (FTSMDO) is developed for the anti-disturbance tracking control of under-actuated quadcopter suspension transportation system (UQSTS). The HSMC is used to deal with the under-actuated characteristics of the UQSTS, and the external disturbance is estimated by designing the FTSMDO. Synchronously, the disturbance estimation error is processed by designing the adaptive law. The stability analysis based on Lyapunov is applied to verify the uniform ultimate boundedness of the closed-loop system. Finally, the comparison of physical experiment upshots shows the effectiveness and potential of the proposed new control techniques.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Stabilization for a General Class of Fractional-Order Systems: A
           Sampled-Data Control Method

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      Authors: Xinyao Li;Changyun Wen;Xiaolei Li;Chao Deng;
      Pages: 4643 - 4653
      Abstract: In this paper, based on sampled-data control method, we address the stabilization problem for a general class of linear continuous-time fractional systems whose solution contains the Mittag-Leffler function that does not obey the basic exponentiation identity. By considering the infinite memory and hereditary characteristics of fractional-order calculus, we propose a sampled-data controller that guarantees the resulting closed-loop system to be asymptotically stable. Simulation examples are presented to demonstrate the effectiveness of the proposed controller and verify the established results.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Identification of Nonlinear State-Space Systems With Skewed Measurement
           Noises

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      Authors: Xinpeng Liu;Xianqiang Yang;
      Pages: 4654 - 4662
      Abstract: In this paper, we consider the identification problem for nonlinear state-space models with skewed measurement noises. The generalized hyperbolic skew Student’s t (GHSkewt) distribution is employed to describe the skewed noises and formulate the hierarchical model of the considered system. A unified framework for estimating unknown states and model parameters is presented based on expectation-maximization (EM) algorithm, in which the forward filtering backward simulation with rejection sampling (RS-FFBSi) is employed to efficiently estimate the smoothing densities of the hidden states, and optimization method is adopted to update model parameters. One numerical study and the electro-mechanical positioning system (EMPS) are employed to verify the effectiveness of the developed approach.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Dynamic Deadband Event-Triggered Strategy for Distributed Adaptive
           Consensus Control With Applications to Circuit Systems

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      Authors: Yong Xu;Jian Sun;Ya-Jun Pan;Zheng-Guang Wu;
      Pages: 4663 - 4673
      Abstract: This paper focuses on the distributed consensus seeking of multi-agent systems (MASs) with discrete-time control updating and intermittent communications among agents. Compared with existing linearly coupled protocols, a nonlinear coupled Zeno-free event-triggered controller is first proposed, which is further to project the static and dynamic triggering mechanisms exploited by using the deadband control method. Then, the node-based nonlinear coupled adaptive event-triggered controller with online self-tuning of time-varying coupling weight and its corresponding to static and dynamic deadband-based event-triggered mechanisms are designed, respectively. The exploited adaptive event-triggered controller does not rely on any global information of interaction structure and is implemented in a fully distributed fashion. In addition, two dynamic proposals not only cover existing static strategies as special cases, but also show that the minimal inter-execution time of dynamic one is not smaller than that of static one. Theoretical analysis shows that the proposed static and dynamic deadband-based event-triggered mechanisms can not only ensure the average consensus with Zeno-freeness, but also achieve the data reduction of communication and control. Finally, the proposed algorithms applied to circuit implementation are corroborated to prove its practical merits and validity.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Transmitter and Receiver for High Speed Polymer Microwave Fiber
           Communication at D-Band

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      Authors: Frida Strömbeck;Zhongxia Simon He;Herbert Zirath;
      Pages: 4674 - 4681
      Abstract: A chipset for high datarate polymer microwave fiber (PMF) communication is described. It consist of a PAM-4 RF-DAC and power detector (PD) and is fabricated using a commercial 130 nm SiGe BiCMOS process. A link measurement is performed over a one meter long PMF verifying that the link can support data rates up to 20 Gbps using PAM-4, with a bit error rate (BER) of
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Cycle by Cycle FSK Demodulator With High Sensitivity of 1% Frequency
           Modulation Index for Implantable Medical Devices

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      Authors: Ali Asghar Razavi Haeri;Aminghasem Safarian;
      Pages: 4682 - 4690
      Abstract: This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with $0.18mu m$ CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the demodulator is able to demodulate the cycle-by-cycle modulated FSK signals with low modulation index of 2.5%, with a BER of $1.24times 10^{-5}$ .
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Design and Analysis of Flexible Capacitive Power Transfer With Stable
           Output Capability

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      Authors: Li Fang;Hong Zhou;Wenshan Hu;Xingran Gao;Haitang Liu;Qijun Deng;
      Pages: 4691 - 4701
      Abstract: This paper presents a novel flexible capacitive power transfer (CPT) system, which has stable output capability when the coupler is deformed. To obtain the flexible coupler structure, the copper foil with the features of light, thin, and cost-efficiency is employed to form the flexible capacitive coupling. To achieve stable output capability, the frequency band selection method and the frequency splitting characteristic are deduced, which indicates that if the system works on optimized natural resonant frequency, moderate deformation of the copper foil coupler could have negligible effects on output power and efficiency. Furthermore, the finite-element analysis (FEA) is employed to simulate the variation of electric field distribution in the flexible coupler. Finally, a prototype is constructed in the laboratory. The copper foil coupler with 60 $mu text{m}$ thickness and the dimension of $30times 16$ cm is adopted, which can achieve more than 147 W power transfer for a 100 mm air gap with the efficiency over 86%. When the bending displacement is within 40 mm, the fluctuations of received power and efficiency are less than 3.6% and 3.1%, respectively. The measured results validate the feasibility of the proposed CPT system for being applied in flexible scenarios.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • Low Frequency Current-Mode Control for DC-DC Boost Converters With
           Overshoot Suppression

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      Authors: Peng Li;Yijing Wang;Lei Liu;Xialin Li;Zhiqiang Zuo;
      Pages: 4702 - 4713
      Abstract: The DC-DC converter severs as one of the crucial components in DC microgrid applications. In this paper, a novel low frequency current-mode control strategy is proposed to improve overshoot suppression performance for the boost converter against load current and source voltage disturbances. The control strategy is presented as a cascade dual-loop structure composed of a dynamic current-loop controller with asymmetric saturation and a PI form voltage-loop controller. With the low frequency information of disturbances, the designed dynamic current-loop controller delivers not only promising disturbance suppression but also superior reference current tracking. Simulation and experiment results are provided to illustrate the superiority of the proposed strategy on overshoot suppression.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • A Wireless DC Motor Drive Using LCCC-CCL Compensated Network With
           Bidirectional Motion Capability

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      Authors: Haitang Liu;Hong Zhou;Qijun Deng;Wenshan Hu;Xingran Gao;Li Fang;
      Pages: 4714 - 4725
      Abstract: This paper proposes an LCCC and CCL compensated wireless servo motor control circuitry utilizing the merits of fundamental and third harmonic. With this circuitry, the motor side needs no additional power supply and controller, which significantly reduces the difficulty of maintenance. Besides, benefiting from the proposing of CCL compensating topology and utilizing of the self-driven circuitry, the secondary operates in fully resonant state and the motor direction control H-bridge is self-driven by the LC frequency selecting circuitry (FSC). Moreover, compared with the conventional motor control circuitry, because of the use of fundamental and third harmonic, the power equalization becomes significantly easier, and zero voltage switch (ZVS) can be realized at the same time; Besides, motion direction control of the motor is simpler with only a single pole double throw (SPDT) at the transmitter side. In addition, system resource consumption is reduced compared with conventional motor drive topologies. In this paper, an 180W prototype is built for experimental verification, and the result shows a good power equalization capability and a transfer efficiency reaching up to 90% at the distance of 10cm.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • TechRxiv: Share Your Preprint Research with the World!

    • Free pre-print version: Loading...

      Pages: 4726 - 4726
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • IEEE Open Access Publishing

    • Free pre-print version: Loading...

      Pages: 4727 - 4727
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
  • IEEE Transactions on Circuits and Systems--I: Regular Papers Information
           for Authors

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      Pages: 4728 - 4728
      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Nov. 2022
      Issue No: Vol. 69, No. 11 (2022)
       
 
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