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IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Prestige (SJR): 0.869
Citation Impact (citeScore): 4
Number of Followers: 45  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1057-7122 - ISSN (Online) 1549-8328
Published by IEEE Homepage  [228 journals]
  • IEEE Transactions on Circuits and Systems--I: Regular Papers Publication
           Information

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      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • IEEE Circuits and Systems Society Information

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      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta
           ADC

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      Authors: Sudhanva Vasishta;K. R. Raghunandan;Ananth Dodabalapur;T. R. Viswanathan;
      Pages: 993 - 1005
      Abstract: This paper presents a novel subranging Sigma-Delta ADC using a relaxation Current-Controlled Oscillator (ICO). The instantaneous frequency of the ICO at the sampling instant determines its time resolution and hence its quantization error, while its average frequency determines its power dissipation. Therefore, running the ICO at nominally lower frequency for most of the sampling period while increasing its frequency close to the sampling instant achieves high resolution and low power consumption. This idea is similar to the strategy employed by athletes in a race where they speed-up close to the finish line to gain a clear lead from others. A prototype ADC is designed and fabricated in TSMC 180nm CMOS technology. It achieves an ENOB of 11.9 bits consuming $10~mu text{W}$ of power from a 1.8V supply and occupies an active area of 0.06 mm 2, which corresponds to a Schreier FoM of 156.8 dB and a Walden FoM of 625 fJ/conversion cycle.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise
           Amplifier

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      Authors: Neha Bajpai;Paramita Maity;Manish Shah;Amitava Das;Yogesh Singh Chauhan;
      Pages: 1006 - 1016
      Abstract: In this article, we design and fabricate an ultra-low noise figure, multi-band low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) using ${0.25~mu text {m}}$ GaAs pHEMT process. The proposed LNA’s performance results from a simultaneous match of optimal impedance for minimum noise figure and maximum power gain at the input. It also includes theoretical analysis of key factors in which simultaneous match of noise figure and input power gain depend. The presented LNA design can be re-configured anywhere in the frequency range from 1.8 to 5.0 GHz with the bandwidth of 200 MHz to 600 MHz. The experimentally reported performance of the proposed LNA includes a maximum 22 dB small signal gain, 18.6 dBm output power at 1-dB gain compression (OP1dB), 39.4 dBm output power at 3 $^{mathrm{ rd}}$ -order intercept point (OIP3), and 0.35 dB minimum noise figure in the band 1.8 – 2.1 GHz while consuming only 0.165 W of dc power. Moreover, our LNA MMIC has an inbuilt input and output Electro-Static-Discharge (ESD) limiter, which can handle a 250 V charged device model (CDM) and 650 V human body model (HBM) according to JEDEC standards while occupying only ${0.32~text {mm}^{2}}$ of area.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A Low-Offset VCO-Based Time-Domain Comparator Using a Phase Frequency
           Detector With Reduced Dead and Blind Zones

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      Authors: Mahin Esmaeilzadeh;Yves Audet;Mohamed Ali;Mohamad Sawan;
      Pages: 1017 - 1029
      Abstract: We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148 $boldsymbol {mu }mathbf {V_{rms}}$ input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14 ${mu }text{V}$ . Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost ${pm 2pi }$ input phase range, the maximum operating frequency of the PFD is 1.32 GHz.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Ultra-Low-Power Sub-1 V 29 ppm/°C Voltage Reference and
           Shared-Resistive Current Reference

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      Authors: Darshan Shetty;Christoph Steffan;Gerald Holweg;Wolfgang Bösch;Jasmin Grosinger;
      Pages: 1030 - 1042
      Abstract: This paper presents a curvature-compensated sub-1V voltage reference (VR) and a shared-resistive nanoampere current reference (CR) in a 130nm CMOS process. The CR is used to generate a bipolar junction transistor complementary-to-absolute-temperature voltage, which is summed up with a proportional-to-absolute-temperature voltage generated using a summing network of PMOS gate-coupled pairs. The measured output voltage and current references from 10 chips ( $V_{mathrm {REF}}$ and $I_{mathrm {REF}}$ ) at room temperature are 469mV and 1.86nA, respectively. The measured average temperature coefficient of $V_{mathrm {REF}}$ and $I_{mathrm {REF}}$ are 29ppm $/^{circ} text{C}$ and 822ppm $/^{circ} text{C}$ over a temperature range from $- 40^{circ} text{C}$ to $120^{circ} text{C}$ . The minimum supply voltage of the voltage-current reference is 0.95V, and the total power consumption is 30nW.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Exploring Speed Maximization of Frequency-to-Digital Conversion for
           Ultra-Low-Voltage VCO-Based ADCs

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      Authors: Viet Nguyen;Filippo Schembari;Robert Bogdan Staszewski;
      Pages: 1043 - 1056
      Abstract: A frequency-to-digital converter (FDC) performs the role of precise frequency digitization within a voltage-controlled oscillator (VCO)-based ADC. To be compatible with energy-harvesting (EH) Internet-of-Things (IoT) devices, the development of ultra-low-voltage (ULV) FDCs is crucial, where the primary focus must be directed towards the maximization of data throughput under dramatic constraints of reliability and timing variability associated with deep-subthreshold operation. This article investigates the speed maximization of a 0.2V full-custom ULV FDC design, consisting of an array of several parallel XOR-based FDC units, and the multi-rate decimation-filtering digital back-end. At the core of this broad exploration is a high-speed sense-amplify phase sampler (PS) featuring hardware redundancy, capable of sampling the phase of low-voltage-swing inputs. Particular focus is placed on the yield-based reliability-driven design methodology for the sense-amplify phase-sampling circuits running up to 40MS/s and practical variability-mitigation strategies. To overcome the speed bottleneck in the digital back-end, a fully parallel bitstream-processing architectural composition of the computations for summation and decimation are proposed. Experimental verification through measurements of the FDC integrated within a 10-bit 160kHz bandwidth (BW) open-loop VCO-based ADC across clock frequency with supply variations demonstrate robust operation of the first 0.2V multi-phase FDC in the advanced 28nm CMOS process.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Optimized MASH-SR Divider Controller for Fractional-N
           Frequency Synthesizers

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      Authors: Dawei Mai;Michael Peter Kennedy;
      Pages: 1057 - 1070
      Abstract: The divider controller in a conventional phase-locked loop fractional- $N$ frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • 24–35 GHz Filtering LNA and Filtering Switch Using Compact Mixed
           Magnetic-Electric Coupling Circuit in 28-nm Bulk CMOS

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      Authors: Hui-Yang Li;Jin-Xu Xu;Li Gao;Quan Xue;Xiu Yin Zhang;
      Pages: 1071 - 1082
      Abstract: This paper presents compact 24–35 GHz filtering low noise amplifier (LNA) and filtering switch in 28-nm CMOS technology. A compact mixed magnetic-electric coupling circuit is designed, where a transmission zero is introduced out of the passband due to the cancellation of the magnetic and electric couplings. By analyzing the impedance characteristics, this structure can be designed with the impedance conversion function to replace the widely used transformers in integrated circuit designs. It shows the advantages of easy control of coupling coefficient and out-of-band rejection. Then, an LNA employing the magnetic-electric coupling circuits as impedance matching networks is designed. Image rejection can be achieved without increasing the circuit area. Moreover, by loading transistors to this mixed magnetic-electric coupling circuit, the input impedance can be controlled by the parasitic components of the transistor. Subsequently, a filter passband can be switched on and off, realizing a very compact filtering single-pole single-throw (SPST) switch. The fabricated filtering LNA is measured with a 3-dB bandwidth of 24–35 GHz, a noise figure (NF) of 2.4-3.6 dB, a maximum gain of 22 dB, and suppression of better than 25 dBc below 18 GHz. The filtering switch shows a minimum on-state loss of 2.1 dB at 28.6 GHz with better than 12.9 dB rejection below 16 GHz and off-state isolation of higher than 19 dB.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Hardware Implementations for Voice Activity Detection: Trends, Challenges
           and Outlook

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      Authors: Shubham Yadav;Patrice Abbie D. Legaspi;Mark S. Oude Alink;André B. J. Kokkeler;Bram Nauta;
      Pages: 1083 - 1096
      Abstract: Voice Activity Detection (VAD) is a technique used to identify the presence of human voice in an audio signal. It is implemented as an always-on component in most speech processing applications. As speech is absent most of the time, this component typically dominates the overall average power consumption of the system (excluding microphone). The widespread usage in speech applications and the need for ultra low power VAD have led to a plethora of algorithms and implementations in the hardware domain, necessitating a comprehensive study and analysis to understand (real-time) requirements, different design parameters, testing strategies, but also to identify design trends, challenges and guidelines for future implementations and testing of VAD devices. A scoping review was conducted to identify the articles for hardware implementations of VAD from January 2010 - December 2021, the results of which are presented in this article. The results highlight a big design space being used for VAD along with a lack of standard testing methodology and usage of application-dependent performance metrics. An increased usage of filter-based feature extractors along with neural-network-based classifiers is observed. Due to lack of standardisation, no other trends can be established from the results. A set of rules and guidelines are therefore provided to facilitate the future development and benchmarking of VADs.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A 95.2% Efficiency DC–DC Boost Converter Using Peak Current Fast
           Feedback Control (PFFC) for Improved Load Transient Response

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      Authors: Shashank Alevoor;Rakshit Dambe Nayak;Bhushan Talele;Abhishek Ray;Joseph D. Rutkowski;Troy Stockstad;Bertan Bakkaloglu;
      Pages: 1097 - 1109
      Abstract: The load transient response and unity gain bandwidth of DC-DC boost converters are primarily restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. In the proposed PFFC method, the closed loop output impedance ( $Z_{OCL}$ ) is improved by reducing the DC value and by increasing the bandwidth of $Z_{OCL}$ as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for $V_{OUT} =5text{V}$ , $V_{IN} =2.5text{V}$ -4.4V and $I_{LOAD} =10$ mA-1A operating at a fixed frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by $sim 2.6times $ and the undershoot reduces by 62% to $12~mu text{s}$ and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/ $mu text{s}$ . The converter achieves a peak efficiency of 95.2% at 0.5W output power with $V_{IN} =4.4text{V}$ and load regulatio- of 9mV/A at $V_{IN} =2.5text{V}$ .
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm
           for TIADC

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      Authors: Haoyang Shen;Adam Blaq;Deepu John;Barry Cardiff;
      Pages: 1110 - 1120
      Abstract: This paper proposes a foreground digital calibration algorithm that estimates and corrects the offset, gain, and time-skew mismatches for time-interleaved analog-to-digital converters (TIADCs) furthermore our algorithm is designed to correct for harmonic distortion introduced by the presence of a nonlinear front-end. We propose a novel simplified non-linear model in place of the more complex conventional Volterra series based structure. The mismatch estimation technique based on the Fast Fourier Transform (FFT) is proposed to estimate the various time-interleaving mismatches simultaneously. A Taylor-based technique is applied to compensate for these mismatches. We also consider the choice of an appropriate time reference for the time-skew correction algorithm by theoretical analysis. The nonlinear distortion correction technique is based on estimating and inverting an assumed $3^{text {rd}}$ order nonlinearity with a fractional delay. To do this, we design a customized filter in an offline process. Our algorithms are designed to operate in any Nyquist zone. The proposed techniques are verified by a Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit containing a 12-bit, 4.096 GHz TI-ADC with 8 sub-ADCs operating in the $2^{text {nd}}$ Nyquist zone. Accordingly, we observed an improvement in SFDR of 14 dB for mismatch calibration alone and up to another 12 dB with nonlinear correction enabled.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Real-Time External Compensation System With Error Correction Algorithm for
           High-Resolution Mobile Displays

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      Authors: Kyeongmin Park;Seunghun Oh;Dongjin Choi;Kyeonghan Shin;Haewan Cho;Franklin Bien;
      Pages: 1121 - 1132
      Abstract: This paper presents an external compensation system for QHD+ ( $3040times1224$ ) mobile active-matrix organic light emitting diode (AMOLED) displays at a frame rate of 60 Hz. During vertical blank periods, current sensing AFE (CS-AFE) measures OLED currents to calculate threshold voltage ( $V_{TH}$ ) of driving thin-film transistors (TFTs). For precise $V_{TH}$ calculation against panel ground noise, a differential sensing scheme with 5-bit programmable capacitor array (PCA) is employed. In addition, digital correlated double sampling (CDS) removes an offset of the CS-AFE. However, recent advances in high efficiency OLED technology have led to increase in pixel density as well as the driving TFTs to operate close to subthreshold region. Therefore, the $V_{TH}$ calculation based on the quadratic model yields inaccurate results. To compensate for the modeling error, we propose an error correction algorithm, which establishes an error function using a relationship between the modeling error and calculated threshold voltage during the manufacturing process. The proposed external compensation system was verified using CMOS-modeled three transistors and one capacitor (3T1C) pixel circuit. The test chip, fabricated in a $0.18~mu text{m}$ BCD process, comprises 26 channels. Each channel consumes 78 $mu text{W}$ and occupies 1350 $times 50,,mu text{m}^{2}$ . Measurement results show that current error at $-4^{mathrm {th}}$ gray level is reduced from 35.56 LSB to 6.03 LSB after error correction and four frames average.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A SiPM-Based Gamma Spectrometer With Field-Programmable Energy Binning for
           Data-Efficient Isotope Analysis

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      Authors: Shaan Sengupta;Matthew L. Johnston;
      Pages: 1133 - 1146
      Abstract: A highly reconfigurable gamma spectrometer with a silicon photomultiplier detector and a custom integrated circuit (IC)-based multi-channel analyzer (MCA) is presented. The core of the MCA comprises a custom analog front-end IC and a piecewise-linear analog-to-digital converter (ADC) IC, both fabricated in a 180nm complementary metal-oxide-semiconductor (CMOS) process. Along with a field-programmable gate array (FPGA)-based digital back-end, the proposed architecture allows pulse-height analysis with reconfigurable analog gain and ADC resolution across the full dynamic range. Specifically, the piecewise-linear ADC can increase resolution in selected regions of interest while utilizing a fixed 7-bit digital word, thus enabling data reduction and spectrum feature enhancement. Reconfigurability also allows the MCA to be tuned for different scintillator materials used in the detector. The system architecture is introduced at a conceptual level, followed by detector and circuit-level MCA implementation details and design trade-offs. Several isotope spectra were recorded with two common scintillators, LYSO and CsI(Tl), spanning energy peaks from 32keV to 1.33MeV. Variable energy bin-widths were measured across different AFE gains, ranging from 3keV to 58keV for LYSO, and 1.4keV to 51keV for CsI(Tl), demonstrating the versatility of the proposed system and its ability to provide reconfigurable peak enhancement for radiation spectroscopy.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Double-Ended Superposition Anti-Noise Resistance Monitoring Write
           Termination Scheme for Reliable Write Operation in STT-MRAM

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      Authors: An Yang;Zhilin Jiang;Zheng Huang;Zitong Zhang;Yanfeng Jiang;
      Pages: 1147 - 1160
      Abstract: Although resistance monitoring write termination (RM-WT) scheme for STT-MRAM can reduce the write energy, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) and intrusion of noise with process variation still seriously deteriorates the stability of the WT operation. In this paper, a double-ended superposition anti-noise write termination (DSA-WT) scheme is proposed and implemented, in which the voltage changes on both BL and SL can be superimposed to boost sensing margin (SM). Schmitt trigger (ST) is adopted to take the place of the inverter (INV) in the traditional WT scheme, which is demonstrated to be helpful for stability improvement. Based on 65-nm CMOS technology, the proposed DSA-WT scheme shows 15% ~33% sensing margin boosting under various PVT conditions and 1000 times lower read bit-error-rate (BER) compared with the other WT schemes. The write done (WD) delay and the energy-delay-product (EDP) achieve 49.6% and 47.2% improvements compared to the state-of-art self-referenced single-ended RM-WT scheme (SS-RM-WT), respectively.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Modular Modeling of Analog Organic Neuromorphic Circuits: Toward
           Prototyping of Hardware-Level Spiking Neural Networks

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      Authors: Yi Yang;Mohammad Javad Mirshojaeian Hosseini;Walter Kruger;Robert A. Nawrocki;
      Pages: 1161 - 1174
      Abstract: This work proposes a novel modeling approach for analog organic circuits using very simple to customize circuit topology and parameters of individual p- and n-type organic field effect transistors (OFETs). Aided with the combination of primitive elements (OFETs, capacitors, resistors), the convoluted behavior of analog organic neuromorphic circuits (ONCs) and even other general analog organic circuits, can be predicted. The organic log-domain integrator (oLDI) synaptic circuit, the organic differential-pair integrator (oDPI) synaptic circuit, and the organic Axon-Hillock (oAH) somatic circuit are designed and serve as the modular circuit primitives of more complicated ONCs. We first validate our modeling approach by comparing the simulated oDPI and oAH circuit responses to their experimental measurements. Thereafter, the summation effects of the excitatory and inhibitory oDPI circuits in prototyped ONCs are investigated. We also predict the dynamic power dissipation of modular ONCs and show an average power consumption of $2.1 mu text {J}$ per spike for the oAH soma at a ~1 Hz spiking frequency. Furthermore, we compare our modeling approach with other two representative organic circuit models and prove that our approach outperforms the other two in terms of accuracy and convergence speed.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Compact, High Power Capacity, and Low Insertion Loss Millimeter-Wave
           On-Chip Limiting Filter With GaAs PIN Technology

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      Authors: Hao-Ran Zhu;Jun Wang;Min Tang;
      Pages: 1175 - 1188
      Abstract: In this paper, a collaborative design of compact, high-power capacity, and low insertion loss millimeter-wave limiting filter using gallium arsenide (GaAs) PIN technology is presented. Parallel topology is employed to distribute the PIN diodes of the first stage of limiting circuit for high power handling capacity. In order to reduce the circuit size, the filtering function structure is incorporated into the limiter. Four transmission zeros (TZs) are introduced to improve the out-of-band suppression performances of the limiting filter. By utilizing the inductive short-circuited stub, a parallel resonator is introduced to exhibit the passband characteristic. Semi-lumped and $pi $ -type topologies are employed to reduce the size of the conventional quarter-wavelength transmission line and introduce several TZs within the stopband. An on-chip limiting filter sample is fabricated by the GaAs PIN process and occupies an area of only $1.1times 0.9$ mm2. It is measured with the insertion loss of 1.67 dB at the center frequency of 35 GHz, the stopband suppression of better than 20 dB, and the tolerable input power of greater than 40 dBm. Compared with the traditional designs, good features of high-power capacity, low insertion loss, and miniaturization are obtained with the presented on-chip limiting filter.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A 216 × 216 Global-Shutter CMOS Image Sensor With Embedded Analog Memory
           and Automatic Exposure Control for Under-Display Optical Fingerprint
           Sensing Applications

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      Authors: Ping-Hung Yin;Chih-Wen Lu;Jia-Shyang Wang;Yuan-Chang Chien;Cheng-Te Chou;Guo-Dung John Su;Poki Chen;
      Pages: 1189 - 1201
      Abstract: A $216times216$ under-display optical fingerprint CMOS image sensor (CIS) is proposed and was prototyped using 0.11- $mu text{m}$ CIS technology. Two analog storage nodes that act as a ping-pong buffer are embedded in each pixel of the global-shutter CIS, rendering a digital buffer unnecessary and increasing the operating frame rate. A processor with automatic exposure (AE) and black-level correction is embedded in the CIS to shorten the data transmission time. The AE and dynamic range enhancement functions are initiated to increase the success rate of fingerprint recognition. The full well capacity and sensitivity of the global-shutter CIS are 9 ke− and 21 V/(lux $cdot $ s), respectively. A prototype of the fingerprint sensor consumed only 26 mW with a 3.3-V supply voltage. An imaging lens and the CIS were combined to form the prototype of a compact camera module (CCM). Each pixel size is $6.8times 6.8,,mu text{m}^{2}$ , equivalent to a panel resolution of 747 dots per inch with an optical ratio of 5. The sensor chip size is $2.23times2.39$ mm2, and the sensing area is $1.469times1.469$ mm2, occupying 40.5% of the chip. The prototype CCM was successfully embedded in a mobile phone, and the performance of the CIS was validated in the temperature range of −20°C to 50°C. Even when the interrupt interval for the serial peripheral interface communication was 300 ms, the CIS as a slave device could capture the fingerprint images clearly.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A 53–78 GHz Complementary Push–Push Frequency Doubler With Implicit
           Dual Resonance for Output Power Combining

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      Authors: Xiaoping Wu;Zehui Kang;Yihui Wang;Liang Wu;
      Pages: 1202 - 1213
      Abstract: This paper presents a millimeter-wave (mmW) frequency doubler based on complementary push-push (CPP) configuration achieving wideband, low-power and high-efficiency operation. Conventional push-push (PP) frequency doublers typically rely on half-wave rectification and suffer from performance compromise between the desired output and the DC current consumed. To mitigate this issue, a simple but effective CPP frequency doubling scheme is proposed to realize full-wave rectification, attaining enhanced output harmonic current and improved fundamental rejection without extra power consumption. At the output, an implicit dual-resonance (IDR) network featuring inherent resonant frequency alignment is employed to efficiently combine the harmonic power generated by the CPP transistors. Implemented in a 65-nm CMOS process and occupying a core area of 0.04 mm2, the proposed frequency doubler prototype measures conversion loss of < 10 dB from 53 to 78.5 GHz at 0-dBm input, while consuming 21.5 mW from a 1-V supply.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Analysis and Design of VCO-Based Neural Front-End With Mixed Domain
           Level-Crossing for Fast Artifact Recovery

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      Authors: Huaiyu Liu;Yang Lin;Liang Qi;Yongwei Lou;Guoxing Wang;Yan Liu;
      Pages: 1214 - 1227
      Abstract: Concurrent neural signal instrumentation withstanding neural stimulation artifacts is essential for bi-directional neural interfaces to guarantee signal integrity. In this work, different front-end structures and stimulation artifact mitigation techniques are firstly reviewed to benchmark their step response speed. Then, a mixed domain level-crossing scheme is proposed to achieve fast dynamic response with minimized hardware overhead. The benefit of extending the phase detection range of the phase detectors in VCO-based continuous time $rm Delta Sigma $ modulators is investigated with stability and noise consideration. Then a shift-register-based phase counter is proposed to extend the phase detectors’s detection range, thereby increase quantization resolution and stability margin for in-band noise optimization. The proposed VCO-based neural front-end was fabricated in a 180 nm CMOS process. The prototype achieves $6.38~mu $ Vrms input-referred noise over 0.5 Hz-10 kHz bandwidth. With a linear input range of 120 mVpp, it exhibits a SNDR of 71.6 dB and a DR of 77.0 dB, which could be further extended up to 100 dB in the artifact adaption mode. Measurements verify that the proposed neural front-end can recover from rail-to-rail differential mode or common mode artifacts within 10 $mu text{s}$ (minimum $6.25~mu text{s}$ ) while the superposed small signal can be recorded uninterruptedly.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of
           Reconfigurable AI Chips

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      Authors: Shaojun Wei;Xinhan Lin;Fengbin Tu;Yang Wang;Leibo Liu;Shouyi Yin;
      Pages: 1228 - 1241
      Abstract: Nowadays, artificial intelligence (AI) technologies, especially deep neural networks (DNNs), play an vital role in solving many problems in both academia and industry. In order to simultaneously meet the demand of performance, energy efficiency and flexibility in DNN processing, various reconfigurable AI chips have been proposed in the past several years. They are based on FPGA or CGRA platforms and have domain-specific reconfigurability to customize the computing units and data paths for different DNN tasks without re-produce the chips. This paper surveys typical reconfigurable AI chips from three reconfiguration hierarchies: processing element level, processing element array level, and chip level. Each reconfiguration hierarchy covers a set of important optimization techniques for DNN computation which are frequently adopted in real life. This paper lists the reconfigurable AI chip works in chronological order, discusses the hardware development process for each optimization techniques, and analyzes the necessity of reconfigurability in AI tasks processing. The trends of each reconfiguration hierarchy and insights about the cooperation of techniques from different hierarchies are also proposed.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • An Energy-and-Area-Efficient CNN Accelerator for Universal Powers-of-Two
           Quantization

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      Authors: Tian Xia;Boran Zhao;Jian Ma;Gelin Fu;Wenzhe Zhao;Nanning Zheng;Pengju Ren;
      Pages: 1242 - 1255
      Abstract: CNN model computation on edge devices is tightly restricted to the limited resource and power budgets, which motivates the low-bit quantization technology to compress CNN models into 4-bit or lower format to reduce the model size and increase hardware efficiency. Most current low-bit quantization methods use uniform quantization that maps weight and activation values onto evenly-distributed levels, which usually results in accuracy loss due to distribution mismatch. Meanwhile, some non-uniform quantization methods propose specialized representation that can better match various distribution shapes but are usually difficult to be efficiently accelerated on hardware. In order to achieve low-bit quantization with high accuracy and hardware efficiency, this paper proposes Universal Power-of-Two (UPoT), a novel low-bit quantization method that represents values as the addition of multiple power-of-two values selected from a series of subsets. By updating the subset contents, UPoT can provide adaptive quantization levels for various distributions. For each CNN model layer, UPoT automatically searches for the optimized distribution that minimizes the quantization error. Moreover, we design an efficient accelerator system with specifically optimized power-of-two multipliers and requantization units. Evaluations show that the proposed architecture can provide high-performance CNN inference with reduced circuit area and energy, and outperforms several mainstream CNN accelerators with higher ( $8times $ – $65times $ ) area efficiency and ( $2times $ – $19times $ ) energy efficiency. Further experiments of 4/3/2-bit quantization on ResNet18/50, MobileNet&#x-05F;V2 and EfficientNet models show that our UPoT can achieve high model accuracy which greatly outperform other state-of-the-art low-bit quantization methods by 0.3%–6%. The results indicate that our approach provides a highly-efficient accelerator for low-bit CNN model quantization with low hardware overheads and good model accuracy.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in
           Compact Form Factors

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      Authors: Reid Pinkham;Jack Erhardt;Barbara De Salvo;Andrew Berkovich;Zhengya Zhang;
      Pages: 1256 - 1269
      Abstract: Advanced edge sensing/computing devices, such as AR/VR devices, have a uniquely challenging adaptive baseline workload and camera sensor structure. These devices must process images in real-time from multiple sensors, placing a large burden on a typical centralized mobile SoC processor. Augmenting the sensors with a package-integrated near-sensor processor can improve the device’s processing performance as well as reduce energy consumption. This near-sensor processor must adapt to the dynamic workloads, fit within a limited silicon footprint and energy envelope, and satisfy the real-time requirement. In this work, we present ANSA, a near-sensor processor architecture supporting flexible processing schemes and dataflows to maintain high efficiency for dynamic CNN workloads. ANSA is scalable to sub-mm2 sizes to match the footprint of advanced image sensors. ANSA supports module-level power gating to adapt the compute capacity to dynamic workloads. Finally, ANSA leverages recent advancements in high-density non-volatile memory and 3D packaging to support weight storage within the area constraints of an image sensor. Overall, ANSA achieves inference energy consumption up to $30times $ lower than a standard SIMD baseline. Additionally, our design’s scalability allows it to achieve up to $2.76times $ lower average inference energy at $4.5times $ lower silicon area compared to competing edge accelerator designs.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Area-Efficient Number Theoretic Transform Architecture for Homomorphic
           Encryption

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      Authors: Phap Duong-Ngoc;Sunmin Kwon;Donghoon Yoo;Hanho Lee;
      Pages: 1270 - 1283
      Abstract: Homomorphic encryption (HE) has emerged as an ideal cryptographic technology for meaningful computations on encrypted data. Not only does HE secure private information even if the ciphertext is leaked, but it also maintains data integrity when inferring cloud-side services. However, homomorphic computations include expensive polynomial arithmetic, especially polynomial multiplication. Prior studies proposed number theoretic transform (NTT) hardware designs to accelerate polynomial multiplication. However, the trade-off between hardware complexity and throughput of NTT designs was not considered carefully. This paper proposes an area-efficient NTT architecture suitable for HE schemes. Center of the proposed NTT architecture is a high-throughput butterfly unit array, which communicates with a single data memory unit through a conflict-free memory access pattern. Additionally, we developed a twiddle factor generator to reduce memory consumption. The proposed NTT architecture was successfully accelerated on the Xilinx FPGA devices. Performing with a large number of moduli, the proposed NTT design achieves higher hardware efficiency than the prior arts. Especially, our NTT design consumes less on-chip memory with efficiency improvement of $8.8times $ over the most related work. The implementation results confirm that our design methodology has advantages to deploy many NTT accelerators on an FPGA device for practical HE-based applications.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • An Efficient Fault-Tolerant Protection Method for L0 BTB

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      Authors: Jiawei Nian;Zongnan Liang;Hongjin Liu;Mengfei Yang;
      Pages: 1284 - 1297
      Abstract: Branch prediction structures are increasingly used in space processors due to their crucial role in improving processor performance. Due to radiation effects such as Single Event Upset (SEU) causing system failures, it is necessary to provide protection techniques for branch prediction modules against complex spatial environments. In this paper, we proposed a simple, efficient, low-power, and fault-tolerant design scheme for L0 BTB consisting of a master-slave and a check-decision module. The strategy sets up the L0 BTB structure as a master-slave structure and adds an error check to detect single-bit errors. Experimental results show that we achieve 100% fault tolerance without a loss hit rate. The increase in resource usage is 1.1x, and the path delay increases by 8.1%, superior to other methods. The L0 BTB is a fully-associative structure and multiple entries are accessed simultaneously, which introduces significant power consumption. We added a low-power design for the master-slave module to reduce the query power consumption by 65.9%. In addition, we also applied the scheme to the RAS module. The experimental results demonstrate that our approach is an efficient, generic, fault-tolerant design scheme that can be deployed to different register files.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based
           Wideband Spectrum Sensor for Cognitive Radio Network

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      Authors: Rahul Sharma;Rahul Shrestha;Satinder K. Sharma;
      Pages: 1298 - 1310
      Abstract: This work proposes implementation friendly algorithm for multicoset sampling based wideband spectrum sensing that alleviates computational space and enables parallel execution, incurring lower latency. Based on this proposed algorithm, we provide a new hardware-efficient VLSI architecture of wideband spectrum sensor (WSSR), which offers short sensing time while sensing the wideband spectrum. Additionally, this paper presents a comprehensive discussion of all the submodule micro-architectures of the proposed WSSR. Subsequently, extensive performance analyses performed in the AWGN channel environment have demonstrated that our WSSR delivers adequate detection probability of 0.9 at -5 dB of SNR. Furthermore, the proposed WSSR design also uses a Zynq UltraScale+ FPGA board with a $14.16~mu text{s}$ sensing time and a 2.63 GHz maximum sensing bandwidth. Comparison of our hardware implementation results has shown that the proposed WSSR achieves 38.5% higher sensing bandwidth and 90% shorter sensing time, in comparison to the state-of-the-art work. Eventually, this paper concludes by showing the ASIC synthesis and post-layout simulation results of the proposed WSSR in 90 nm-CMOS technology, which senses $5.4times $ wider bandwidth than the state-of-the-art implementation.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB
           Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias

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      Authors: Adrian Kneip;David Bol;
      Pages: 1311 - 1323
      Abstract: This work presents a 16kB ultra-low power (ULP) SRAM macro in 28nm FD-SOI with high energy efficiency in active mode and ultra-low leakage (ULL) in sleep mode, embedded in the SleepRider micro-controller unit (MCU) intended for IoT edge applications. The proposed SRAM integrates custom 7T ULL bitcells based on negative differential resistance (NDR) structures and a pMOS-only write port, achieving $2.1times $ lower area than previous NDR-based bitcells. A dual-supply strategy combined with negative-wordline write-assist concurrently provides worst-case data retention and correct write operations, up to the 64-MHz MCU target frequency. The SRAM macro periphery combines several low-power techniques to extract the full potential of the novel 7T bitcells, reaching an unprecedented speed-energy-leakage optimum with only 2.5% area overhead. Adaptive forward body biasing (FBB) further improves active mode performance while ensuring robustness against PVT variations. Measurement results showcase a minimum energy point of 0.78pJ per 32b access (assuming 50% read/write) at 0.5V and 64MHz. Moreover, leakage power drops from 296nW/kB at 0.5V in idle conditions to 0.23nW/kB in sleep at the 0.46V data retention voltage (DRV), yielding more than $1000times $ leakage reduction. As such, the proposed SRAM achieves an excellent trade-off between area, leakage and energy in the 10-to-100MHz frequency range.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Generating Grid Multi-Scroll Attractors in Memristive Neural Networks

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      Authors: Qiang Lai;Zhiqiang Wan;Paul Didier Kamdem Kuate;
      Pages: 1324 - 1336
      Abstract: Memristors are well suited as artificial nerve synapses owing to its unique memory function. This paper establishes a novel flux-controlled memristor model using hyperbolic function series. By taking the memristor as synapses in a Hopfield neural network (HNN), three memristive HNNs are constructed. These memristive HNNs can generate multi-double-scroll chaotic attractors or grid multi-double-scroll chaotic attractors. The number of double scrolls in the attractors is controlled by the memristor. Equilibrium points analysis further reveals the generation mechanism of grid multi-double-scroll chaotic attractors. Moreover, numerical simulations indicate the existence of complex dynamics in the memristive HNNs, including extreme multistability and amplitude control. An approach to physically realize grid multi-double-scroll chaotic attractors is also given. Finally, an encryption scheme based on the proposed memristive HNN is designed to demonstrate application potential of the attractors.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Disturbance Utilization-Based Tracking Control for the Fixed-Wing UAV With
           Disturbance Estimation

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      Authors: Zhengguo Huang;Mou Chen;Peng Shi;
      Pages: 1337 - 1349
      Abstract: This paper investigates the disturbance utilization-based attitude control for the fixed-wing unmanned aerial vehicle (UAV). The disturbance utilization condition (DUC) is formed based on the Lyapunov function analysis to retain the disturbance that benefits the stability of closed-loop systems. To reduce the sign-misjudgment of disturbance coupling terms induced by the DUC, the disturbance estimation error analysis auxiliary system (DEEAAS) is designed based on the disturbance observer (DO). Combined with the DEEAAS and the DO, the boundaries of the disturbance estimation error (DEE) are derived. Subsequently, the composite DUC is proposed based on the above boundaries and the given thresholds to replace the basic DUC. Then, the boundedness of the attitude tracking errors of the fixed-wing UAV can be ensured by the controller designed with the composite DUC. And combined with the derived boundaries of the DEE and the given thresholds, the adaptive DO and the adaptive DEEAAS are also designed to avoid the use of big parameters. In addition, sufficient conditions that stabilize the attitude closed-loop system of fixed-wing UAVs equipped with the disturbance utilization-based controller (DUBC) are given. Finally, the numerical simulation for the fixed-wing UAV illustrates the effectiveness of the proposed DUBC.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Privacy-Preserved Distributed Optimization for Multi-Agent Systems With
           Antagonistic Interactions

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      Authors: Qi Luo;Shuai Liu;Licheng Wang;Engang Tian;
      Pages: 1350 - 1360
      Abstract: This paper is concerned with the privacy-preserving distributed optimization problem for a class of cooperative-competitive multi-agent systems. Each agent only knows its own local objective function and interacts the state information with neighbors through a communication network. By means of the signed graph theory, the antagonistic interactions among agents are considered to characterize both the cooperative and the competitive relationships. With the help of the gauge transformation technique, a structurally balanced undirected signed graph is firstly transformed into a standard undirected graph. Then, the distributed optimization problem subject to signed network is converted into the traditional distributed optimization problem. Subsequently, a novel privacy-preserving distributed optimization algorithm is put forward to 1) minimize the sum of local objective functions; 2) achieve the bipartite consensus for all agents; and 3) avoid the information leakage caused by message exchange among agents, simultaneously. Finally, a simulation example is given to verify the effectiveness of the proposed optimization algorithm.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Fast Finite-Time Event-Triggered Consensus Control for Uncertain Nonlinear
           Multiagent Systems With Full-State Constraints

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      Authors: Jianhui Wang;Chen Wang;C. L. Philip Chen;Zhi Liu;Chunliang Zhang;
      Pages: 1361 - 1370
      Abstract: The fast finite-time event-triggered consensus control is investigated for a category of uncertain nonlinear multiagent systems (MASs) with full-state constraints. The uncertainty of the system is estimated by the radial basis function neural networks (RBFNNs). Furthermore, to achieve the fast finite-time stability and not violate the full-state constraints, a fast finite-time event-triggered consensus control method is proposed. The proposed control method can achieve the fast finite-time stability of the system, and all the followers can track the output signal of the leader. Meanwhile, the system states do not exceed the boundaries of the full-state constraints, and the communication resources of the system can be saved. Finally, some simulation examples are provided to verify the feasibility of the proposed approach.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Distributed Bipartite Containment Control of High-Order Nonlinear
           Multi-Agent Systems With Time-Varying Powers

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      Authors: Liuliu Zhang;Songsong Liu;Changchun Hua;
      Pages: 1371 - 1380
      Abstract: In this paper, the distributed bipartite containment control problem for high-order nonlinear multi-agent systems (MASs) with time-varying powers is investigated under signed communication topology. Unlike existing bipartite containment control problems, the powers of the systems are considered to be unknown and time-varying, and the novel bipartite containment controller is proposed. First, the dynamic gain compensator and bipartite containment observer, which could estimate the corresponding virtual leader trajectory belonging to the convex hull spanned by multiple leaders and their symmetric ones, are developed for each follower. Subsequently, with the help of observer, a novel distributed bipartite containment controller is designed by using the power integrator technique and the backstepping method to ensure that the followers converge in the convex hull spanned by multiple leaders and their symmetric ones. Finally, the effectiveness of the bipartite containment scheme is verified by a simulation example.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Event-Triggered Quantized Input-Output Finite-Time Synchronization of
           Markovian Neural Networks

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      Authors: Peng Shi;Xiao Li;Yingqi Zhang;Jingjing Yan;
      Pages: 1381 - 1391
      Abstract: This paper addresses the event-triggered input-output finite-time mean square synchronization for uncertain Markovian jump neural networks with partly unknown transition rates and quantization. Considering the limited network resources, an event-triggered technique and a logarithmic quantizer are both provided. The error system model with uncertainty is established in the unified framework. Then, based on Lyapunov functional approach, interesting results are presented to guarantee the properties of the input-output finite-time mean square synchronization for the error systems. Furthermore, some solvability conditions are induced for the desired input-output finite-time mean square synchronization controller under linear matrix inequality techniques. Eventually, the theoretical finding’s efficiency is shown by an example.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Secure Aperiodic Sampling Control for Micro-Grids Under Abnormal Deception
           Cyber Attacks

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      Authors: Xiao Cai;Kaibo Shi;Kun She;Shouming Zhong;Poogyeon Park;Oh-Min Kwon;Sheng Han;
      Pages: 1392 - 1402
      Abstract: This paper studies the secure aperiodic sampling control issue for Micro-Grids(MGs) under abnormal deception cyber attacks (ADCAs). Firstly, a novel relaxed condition that depends on the time delay (TD) is constructed, further reducing the existing constraint condition. Secondly, a new bilateral delay-dependent looped-functional (BDDLF) $V_{c}(x_{t})$ is developed. Thirdly, based on the characteristics of the aperiodic sampling control, another improved BDDLF $V_{d}(x_{t})$ is developed for acquiring more state information. Furthermore, an optimized control algorithm is designed using proper integral inequalities and the convex combination method. Then, a new secure aperiodic sampled data (SASD) controller under ADCAs is achieved to guarantee real power-sharing between distributed generators (DGs) and energy storage systems (ESSs) in MG. Finally, simulation experiments are carried out on MG to verify the effectiveness and feasibility of the designed control algorithm.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • An Efficient Approximate Expectation Propagation Detector With
           Block-Diagonal Neumann-Series

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      Authors: Huizheng Wang;Bingyang Cheng;Xiaosi Tan;Xiaohu You;Chuan Zhang;
      Pages: 1403 - 1416
      Abstract: Expectation propagation (EP) achieves near-optimal performance for large-scale multiple-input multiple-output (L-MIMO) detection, however, at the expense of unaffordable matrix inversions. To tackle the issue, several low-complexity EP detectors have been proposed. However, they all fail to exploit the properties of channel matrices, thus resulting in unsatisfactory performance in non-ideal scenarios. To this end, in this paper, a block-diagonal Neumann-series-based expectation propagation approximation (BD-NS-EPA) algorithm is proposed, which is applicable for both ideal uncorrelated channels and the correlated channels with multiple-antenna user equipment system. First, a block-diagonal-based Neumann iteration is employed, which skillfully exerts the main information of the channels while reducing computational cost. An adjustable sorting message updating scheme then is introduced to reduce the update of redundant nodes during iterations. Numerical results show that, for $128times 32$ MIMO with the non-ideal channel, the proposed algorithm exhibits 0.3 dB away from the original EP when bit error-rate (BER) $=10^{-3}$ , at the cost of mere 3% normalized complexity. The implementation results on SMIC 65-nm CMOS technology suggest that the proposed detector can achieve 1.252 Gbps/W and 0.275 Mbps/kGE hardware efficiency, further demonstrating that the proposed detectors can achieve a good trade-off between error-rate performance and hardware efficiency.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning
           Operations

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      Authors: Dongyun Kam;Byeong Yong Kong;Youngjoo Lee;
      Pages: 1417 - 1427
      Abstract: Allowing the superior error-correction performance even for short-length codewords, the successive-cancellation list (SCL) decoding algorithm has allowed the polar code to be adopted in 5G New Radio standard for control channel. However, existing SCL polar decoders still suffer from long processing latency caused by a number of serialized internal operations. In this work, to solve the latency problem, we present several parallel computing solutions for the serialized operations, i.e., simplified data dependencies and two overlapped pruning operations. To realize the proposed parallel computing, we also introduce internal circuit blocks including dual read-port buffers, an on-the-fly parity checker, and overlapped processing units. The proposed SCL polar decoders are precisely designed with optimal design parameters by analyzing trade-offs between the latency reduction and area overheads. Implemented in a 65-nm CMOS technology, the proposed list-8 SCL polar decoder requires only 374 ns to handle a (1024, 512) 5G codeword, improving the decoding efficiency by 34.7% compared to the previous designs.
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
  • IEEE Transactions on Circuits and Systems--I: Regular Papers Information
           for Authors

    • Free pre-print version: Loading...

      Pages: 1428 - 1428
      PubDate: March 2023
      Issue No: Vol. 70, No. 3 (2023)
       
 
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