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IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Prestige (SJR): 0.869
Citation Impact (citeScore): 4
Number of Followers: 45  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1057-7122 - ISSN (Online) 1549-8328
Published by IEEE Homepage  [228 journals]
  • IEEE Transactions on Circuits and Systems--I: Regular Papers Publication
           Information

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • IEEE Circuits and Systems Society Information

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      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • 2022 Index IEEE Transactions on Circuits and Systems I: Regular Papers
           Vol. 69

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      Pages: 1 - 87
      Abstract: Presents the 2022 author/subject index for this issue of the publication.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Guest Editorial Special Issue on the International Symposium on Integrated
           Circuits and Systems—ISICAS 2022

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      Authors: Hai Helen Li;
      Pages: 4730 - 4730
      Abstract: This Special Issue of the IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS) 2022, held on October 20–21, 2022, at Bordeaux, France. This is the fifth edition of this journal track symposium as part of the initiative of the IEEE Circuits and Systems Society (CASS), started in 2018. The Symposium welcomes high-quality original research papers in the areas of integrated circuits and systems, including but not limited to analog, digital, power, energy, biomedical, sensor interfaces, and communication systems. A reader will notice that all the papers presented in this Special Issue and at the conference describe integrated circuit and implementations in CMOS, hybrid, SiP or SoC forms with experimental results—this is a mandatory requirement of the Symposium.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined
           ADCs

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      Authors: M. Wagih Ismail;Hajime Shibata;Zhao Li;Sharvil Patil;Tony Chan Carusone;
      Pages: 4731 - 4740
      Abstract: Continuous-time pipelined (CTP) ADCs have shown the potential to alleviate the challenges of discrete-time (DT) pipelined converters with Multi-GHz bandwidth, but have so far required an oversampling ratio (OSR) of at least 4. After elucidating the factors that limit CTP bandwidth, this paper presents a design methodology for near-Nyquist CTP ADCs. The delay circuit is optimized to match the ADC/DAC path in both its broadband magnitude response and phase. The residue filter response is optimized to prevent image signals from overloading the subsequent stage. We show that practical circuits can realize these optimized responses and extend the bandwidth of the CTP architecture to OSRs of 1.5-2.0, essentially equivalent to the OSR of DT converters when allowing for practical anti-aliasing. The direct path (i.e. delay) and the residue-amplifying filter circuits required for 3 GHz bandwidth are incorporated into a complete 4-bit 10 GS/s CTP ADC stage in a 28nm CMOS prototype. Simulation and measurement results confirm that CTP ADCs can operate at a near-Nyquist sampling rate with an OSR of 1.7.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Dual-Branch Series-Parallel Hybrid Buck DC-DC Converter With Flying
           Capacitor Voltage Auto-Balancing

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      Authors: Chuang Wang;Yan Lu;Xiuping Li;Rui P. Martins;
      Pages: 4741 - 4750
      Abstract: This paper presents a dual-branch series-parallel hybrid buck converter with flying capacitor voltage auto-balancing and reduced output impedance. The proposed converter automatically and inherently balances the flying capacitor voltages as one-third of the input voltage. Besides, the proposed converter operates in four states per cycle rather than the conventional six states, leading to a feasible Type-III compensation of the analog pulse-width modulation (PWM) controller. Moreover, due to the multiple parallel current paths in the switched-capacitor network, the proposed converter reduces the output impedance, thus decreasing the conduction loss. Finally, validated in 65-nm CMOS, the proposed converter regulates a 0.55 V–1 V output voltage from a 3.6 V input voltage over a large output power of 0.45 W with 82% peak efficiency, and switching frequency up to 5 MHz. It also automatically sets the flying capacitor voltages at 1.2 V.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An Ultra-Low-Power Octave-Tuning VCO IC With a Single Analog
           Voltage-Controlled Novel Varactor

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      Authors: Mengchu Fang;Toshihiko Yoshimasu;
      Pages: 4751 - 4760
      Abstract: In this paper, an ultra-low-power octave-tuning voltage-controlled oscillator (VCO) integrated circuit (IC) is proposed, using a novel varactor with a single control voltage. The novel varactor including VCO-gain ( ${K} _{mathrm{ VCO}}$ ) improving structure consists of two parallel-connected inversion-mode MOS (I-MOS) -based varactors with shifted bias and an NMOSFET operating as a variable resistor. This novel varactor is able to give a large capacitance variation with a single analog control voltage. The proposed wideband VCO IC implementing this novel varactor is designed, fabricated, and evaluated fully on-wafer in 40-nm CMOS SOI technology. The proposed wideband VCO IC has exhibited a completely continuous measured tuning range (TR) of 67.9% from 3.2 to 6.49 GHz. The measured dc power consumption is from 0.35 to 1.36 mW throughout the whole TR under a supply voltage of 0.36 V. This is an extremely low dc power consumption among the reported sub-10-GHz octave-tuning VCO ICs so far. The measured peak figure-of-merit including TR (FoMT) of the proposed VCO IC is 210.4 dBc/Hz with a carrier frequency of 6.49 GHz.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Symmetrical Double Step-Down Converter With Extended Voltage Conversion
           Ratio

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      Authors: Junwei Huang;Chi-Seng Lam;Yan Lu;Rui Paulo Martins;
      Pages: 4761 - 4773
      Abstract: The Hybrid DC-DC converter, especially with multiple inductors targeting high current delivery, has the advantages of high efficiency and power density with a large voltage conversion ratio (VCR), due to the combination of the benefits of both switched-capacitor-based and inductor-based buck converters. However, a higher number of inductors means that the energizing time for each inductor has more limitations, resulting in a relatively narrower VCR range. To reduce the conduction loss and extend the voltage conversion ratio scope, this paper presents a symmetrical double step-down (SDSD) converter with a VCR range up to 1/3, regulating an output voltage interval of 0.5 V-0.8 V from a 2.7 V-4.2 V Lithium-ion battery. This converter, implemented in 65 nm CMOS, occupies a core active area of 1.53 mm2. This work obtains 86.5% peak efficiency and 326 mA/mm2 maximum current density, with an effective switching frequency of 3 MHz.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a
           Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction

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      Authors: Tailong Xu;Shenke Zhong;Jun Yin;Pui-In Mak;Rui P. Martins;
      Pages: 4774 - 4786
      Abstract: This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band phase noise and RMS jitter. The proposed gain-boosting RSPD converts the phase error to the voltage error and utilizes a passive switched-capacitor voltage multiplier to amplify the sampled voltage error, which effectively increases the gain of the RSPD. The boosted RSPD gain helps suppress the phase noise contributed from the gm cell. To prevent the transistors in the gain-boosting RSPD and gm cell from breakdown, the gain-boosting function is only activated during the locked state when the phase and voltage errors are small. The switching between the gain-boosting and normal modes is realized automatically by monitoring the sampled voltage and comparing it with a pre-defined threshold window. Fabricated in 65-nm CMOS, the type-II RS-PLL measures an RMS jitter of 54 fs at 6.75 GHz and consumes 7.1 mW, corresponding to a jitter figure-of-merit (FoMjitter) of −256.8 dB. The measured reference spur is −62.6 dBc, and the active area is 0.25 mm2.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and
           Latency-Free Background-Calibrated DAC

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      Authors: Yuekang Guo;Jing Jin;Xiaoming Liu;Jianjun Zhou;
      Pages: 4787 - 4798
      Abstract: This paper presents a continuous-time sigma-delta modulator (CTSDM) with a voltage-controlled-oscillator-based (VCO-based) integrating quantizer. A background replica-based calibration technique is proposed to alleviate the impact of the process, voltage supply, and temperature (PVT) variations on the tuning characteristic and current consumption of the VCO-based quantizer. Matching between the replica VCO and the main VCO in the proposed calibration is not needed. A latency-free background calibration technique is also proposed to eliminate the distortions caused by the DAC mismatch. The prototype VCO-based CTSDM is fabricated in a 40 nm CMOS and achieves SNDR/SFDR/DR of 76.4 dB/91.7 dBc/79.6 dB, respectively, within a 50 MHz bandwidth (BW) at 1.6 GHz sampling frequency. The measured SNDR varies within ±1 dB over a temperature range of $0sim 80~^{circ }text{C}$ and a voltage supply variation of ±10%, across different tested samples. The power consumption is 18.1 mW, achieving a Schreier Figure of Merit (FoMS) of 170.8 dB.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving
           ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference

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      Authors: Yu Duan;Chi-Hang Chan;Yan Zhu;Rui Paulo Martins;
      Pages: 4799 - 4809
      Abstract: This paper presents a supply-noise-robust PLL that achieves low-jitter performance within full-spectrum supply interference. A digital-regulated supply noise cancellation (DSNC) scheme suppresses the large amplitude supply noise within an adequate range for a supply-noise-insensitive (SNI) VCO. It ensures that the low pushing factor SNI-VCO only induces a decent amount of phase noise falling within the effective correction range of the phase noise cancellation (PNC). A sample-and-isolate-based (S/I)-PNC cascaded at the VCO output enables a wider correction range for a fine supply noise and phase noise suppression. Fabricated in 28-nm CMOS with an area of 0.088 mm2, the proposed PLL consumes 6.65 mW from a 1 V supply at 4 GHz output. With 20 mVpp supply interference, the prototype obtains a maximum >37 dB output spur reduction at 5 MHz and maintains ≤1.6 ps RMS jitter in the worst case. The suppression performance degrades less than 10% within −20 °C to 80 °C operation temperature.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration
           for Quantum Computing Applications

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      Authors: Jiang Gong;Yue Chen;Edoardo Charbon;Fabio Sebastiano;Masoud Babaie;
      Pages: 4810 - 4822
      Abstract: This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a new PN expression for an oscillator is derived by considering the shot-noise effect. To reach the optimum performance of an LC oscillator, a common-mode (CM) resonance technique is implemented. Additionally, this work presents a digital calibration loop to adjust the CM frequency automatically at 4.2K, reducing the oscillator’s PN and thus improving the control fidelity. The calibration technique reduces the flicker corner of the oscillator over a wide temperature range (10 $times $ and 8 $times $ reduction at 300K and 4.2K, respectively). At 4.2K, our 0.15-mm2 oscillator consumes a 5-mW power and achieves a PN of −153.8dBc/Hz at a 10MHz offset, corresponding to a 200-dB FOM. The calibration circuits consume only a 0.4-mW power and 0.01-mm2 area.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An Inductor-First Single-Inductor Multiple-Output Hybrid DC–DC Converter
           With Integrated Flying Capacitor for SoC Applications

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      Authors: Zhiyuan Zhou;Nghia Tang;Bai Nguyen;Wookpyo Hong;Partha Pratim Pande;Ram K. Krishnamurthy;Deukhyoun Heo;
      Pages: 4823 - 4836
      Abstract: With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple-output (SIMO) inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual-switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with the maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with 500MHz system clock to achieve a less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Analog Spiking Neural Network Based Phase Detector

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      Authors: Hendrik M. Lehmann;Julian Hille;Cyprian Grassmann;Alois Knoll;Vadim Issakov;
      Pages: 4837 - 4846
      Abstract: Spiking Neural Networks represent the third generation of biologically inspired systems for signal processing. They are associated with a particularly efficient and thus low-energy possibility of computing. However, this advantage can only be fully achieved if these networks utilize special neuromorphic circuits. In this work, an analog Spiking Neural Network Phase Detector is presented, from conceptual formulation to implementation in a ${130}~{text {nm}}$ BiCMOS process. The phase detector is capable of directly processing various continuous-time signals up to a frequency of ${200}~{text {MHz}}$ , while consuming just ${840}~{mu text {W}}$ . The phase difference between the signal under test and the reference signal that shall be detected is adaptable. Experimental findings confirm the simulative investigations. The proposed method presented in the paper provides an entry-level approach to designing more complex analog spiking neural networks.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN
           Accelerator on FPGAs

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      Authors: Ching-Te Chiu;Yu-Chun Ding;Wei-Chen Lin;Wei-Jyun Chen;Shu-Yun Wu;Chao-Tsung Huang;Chun-Yeh Lin;Chia-Yu Chang;Meng-Jui Lee;Shimazu Tatsunori;Tsung Chen;Fan-Yi Lin;Yuan-Hao Huang;
      Pages: 4847 - 4859
      Abstract: Face classification is important in many applications such as surveillance, border control, and security systems. However, wide variations in environments such as insufficient light, large distances or pose angles make the task challenging. Depth sensors are added with RGB cameras for improving classification accuracy but commercial RGB-D sensors are most targeted for indoors applications. In this paper, we present and design a Chaos LiDAR depth sesnor that provides high-precision depth images through intelligent correlation processing for both indoors and outdoors applications. Our Chaos LiDAR depth sensor detects range from 2 to 40 meters with precision around 8mm at 20-meter. With the Chaos LiDAR depth as input, we design a RGB-D based face classification embedded CNN (eCNN) model for wide range applications such as dim illumination, various distances and large poses. Our Chaos LiDAR increases around 14.27% classification accuracy compared to RealSense D435i for distance from 3 to 5 meter. The eCNN face classification subsystem is implemented in Xilinx ZCU 102 and achieves 11.11 ms inference time. The eCNN engine achieves a peak throughput at 614.4 GOPS. The overall system including Chaos LiDAR, correlation and eCNN FPGA achieves face classification inference rate of 10fps.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater
           Object Recognition

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      Authors: Chua-Chin Wang;Ralph Gerard B. Sangalang;Chien-Ping Kuo;Hsin-Che Wu;Yi Hsu;Shen-Fu Hsiao;Chia-Hung Yeh;
      Pages: 4860 - 4871
      Abstract: This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An Energy-Efficient Domain-Specific Reconfigurable Array Processor With
           Heterogeneous PEs for Wearable Brain–Computer Interface SoCs

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      Authors: Wooseok Byun;Minkyu Je;Ji-Hoon Kim;
      Pages: 4872 - 4885
      Abstract: Recently, there is increasing demand for energy-efficient signal processing in wearable visual-stimuli-based brain-computer interface (V-BCI) devices. For the better accuracy and the reduced latency of the V-BCI system, the target identification (TI) algorithm that analyzes brain signals is being advanced, and the importance of an energy-efficient accelerating chip that processes various linear algebra operations constituting the TI algorithms is growing. In this paper, we propose a domain-specific reconfigurable array processor (RAP) with a dynamically reconfigurable and scalable array including 5-heterogeneous processing elements (PEs) for the energy-efficient acceleration of basic linear algebra subprograms (BLAS) and matrix decompositions. The system-on-chip (SoC), including the proposed RAP, was fabricated in 130-nm CMOS technology with an area of 16.87-mm2 and measured at 1.0 V 90 MHz. The RAP achieved an information transfer rate (ITR) of 139.9-bits/min and a TI accuracy of 95.4% on a fabricated chip through an optimized TI algorithm and scalable array processing. In addition, the RAP has $16.8times $ higher TI energy efficiency than prior work and achieved an energy efficiency of 2144.2-bits/min/mW for information transfer processing rate with the proposed TI algorithm. The RAP supports a greater variety of linear algebra operations and data sizes with hardware reconfiguration than the prior accelerators.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli
           Metastable Cells

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      Authors: Riccardo Della Sala;Davide Bellizia;Giuseppe Scotti;
      Pages: 4886 - 4897
      Abstract: This paper presents a True Random Number Generator (TRNG) exploiting latched-XOR (LX) gates and its implementation on a Xilinx Spartan 6 FPGA device. The proposed LX-TRNG aims at improving the Throughput (TP) of conventional ring oscillators (ROs) based TRNGs by combining the effect of latches metastability and ROs jitter. Measurements results have demonstrated that the generated bitstreams show very good randomness exhibiting a byte (bit) entropy of 7.9979 (0.9997), according to T8-test of AIS-31. The proposed TRNG has also been extensively tested under voltage and temperature variations showing very good robustness. In particular both NIST’s and AIS-31 tests are passed for all the considered supply voltage and temperature ranges. The FPGA implementation occupies only 9 Slices and, despite its compactness, it exhibits a throughput as high as 12.5 Mbit/s with a 50 MHz operating frequency. The computation of the figure of merit $FOM_{E}$ has shown the capability of the proposed TRNG to optimize the trade-off between hardware resources, bitstreams entropy and throughput, outperforming previous works.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks
           and Ultra-Low BER

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      Authors: Jiahao Liu;Yuanzhe Zhao;Yan Zhu;Chi-Hang Chan;Rui Paulo Martins;
      Pages: 4898 - 4907
      Abstract: This paper presents a weak PUF-assisted strong PUF that combines the metrics between weak and strong PUFs. Unlike the conventional strong PUFs that rely on the nonlinear combination of a large number of entropy cells for high modeling attacks resilience, the presented strong PUF utilizes unique key streams to bitwise encrypt the raw responses from the conventional strong PUF to facilitate an inherent immunity to modeling attacks thus fulfilling high-level security. A device-specific pseudo-random number generator (P-RNG) configured by a dedicated weak PUF array generates a unique key stream (K). Since the weak PUFs are inherently immune to machine learning or deep learning-based modeling attacks, the final encrypted responses of the proposed strong PUF are also inherently immune to modeling attacks. Moreover, we propose a two-to-one (2-to-1) selection scheme and the digitally-controlled-delay-line (DCDL)-based stability checker to suppress the bit-error-rate (BER) of the weak PUF array and improve the efficiency of the spatial majority voting (SMV)-based error correction scheme, thus achieving high stability for our proposed strong PUF. Fabricated in 65nm CMOS GP technology, the proposed weak PUF-assisted strong PUF shows a high energy efficiency of 3.05 pJ/bit at a 2M bit rate. Meanwhile, it demonstrates an ultra-low average worst-case BER of $8.9 times 10^{-11}$ for the temperature range of −20°C to 120°C and a supply voltage variation of ±10% with the proposed stabilization schemes. The proposed strong PUF occupies a core area of 0.075mm2.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Area, Time and Energy Efficient Multicore Hardware Accelerators for
           Extended Merkle Signature Scheme

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      Authors: Yuan Cao;Yanze Wu;Lan Qin;Shuai Chen;Chip-Hong Chang;
      Pages: 4908 - 4918
      Abstract: This paper addresses a barrier that prevents the timely adoption of post-quantum signature algorithms, such as the eXtended Merkle Signature Scheme (XMSS), due to its lack of fast, cost-effective and energy-efficient hardware accelerators. Two new architectures that use more than one hash core are proposed for the first time to significantly reduce the latency of two bottleneck XMSS operations, namely key generation and signature generation, for which the speed of existing hardware accelerators is still apparently inadequate. The first proposed multi-core design uses block RAM and a simplified data flow to maximize the use of $p$ hash cores concurrently in three major sequential stages of computation, i. e., Winternitz One-time Signature (WOTS), L-tree and Merkle tree. The second proposed multi-core design adds a dedicated hash core for tree hashing in the L-tree and Merkle tree while keeping the $p$ hash cores solely for chain hashing in WOTS. The dedicated hash core leapfrogs between the L-tree and Merkle tree and computes concurrently with the $p$ hash cores to keep the $p+1$ hash cores active most of the time while minimizing the storage requirement and energy consumption. Both designs are implemented on a 28 nm ATRIX-7 FPGA chip. Experimental results show that both proposed accelerators with $p=8$ operate at a much faster speed and consume significantly less hardware resources and energy than all existing XMSS accelerators. Specifically, they are $sim 8times $ and $sim 6times $ faster than the fastest reported design in key generation and signature generation operations, respectively.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator
           for Mobile VSLAM

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      Authors: Ye Liu;Jingyuan Li;Kun Huang;Xiangting Li;Xiuyuan Qi;Liang Chang;Yu Long;Jun Zhou;
      Pages: 4919 - 4929
      Abstract: Keypoint extraction is a key technique for Visual Simultaneous Localization and Mapping (VSLAM). Recently, Convolutional Neural Network (CNN) has been used in the keypoint extraction for improving the accuracy. As one of the state-of-the-art CNN based keypoint extraction techniques, the SuperPoint ranked top in the CVPR2020 image matching challenge. However, the use of complex CNN makes it difficult to meet the real-time performance on a mobile platform with limited resource such as mobile robots and wearable Augmented Reality (AR) devices. In this work, based on the SuperPoint, we proposed an FPGA-based real-time keypoint extraction hardware accelerator through algorithm-hardware co-design for mobile VSLAM applications, which is named as MobileSP. Several algorithm and hardware level design techniques have been proposed to reduce the computation and improve the processing speed while maintaining high accuracy, including a partially shared detection & description encoding architecture, a pre-sorting based Non-Maximum Suppression (NMS) engine and a software-hardware hybrid pipeline computing technique. The design has been implemented and evaluated on a ZCU104 FPGA board. It achieves real-time performance of 42 fps with low Absolute Trajectory Error (ATE) of 1.82 cm simultaneously, outperforming several state-of-the-art designs.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An Energy-Efficient SIFT Based Feature Extraction Accelerator for High
           Frame-Rate Video Applications

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      Authors: Bingqiang Liu;Zehua Yin;Xvpeng Zhang;Yi Zhan;Xiaofeng Hu;Guoyi Yu;Yuanjin Zheng;Chao Wang;Xuecheng Zou;
      Pages: 4930 - 4943
      Abstract: Visual feature extraction is a key technology of computer vision for intelligent video processing. Efficient feature extraction is a fundamental problem in computer vision applications. Scale-Invariant Feature Transform (SIFT) is one of the most popular feature extraction algorithms because SIFT features are invariant to image scale and rotation and robust to changes in illumination and noise. However, SIFT is a computationally-intensive and power-hungry algorithm, which needs to be accelerated by efficient hardware design to achieve both high-speed feature extraction and high energy efficiency for many high frame-rate video applications at Artificial-intelligent Internet of Things edges. In this work, an energy-efficient SIFT based feature extraction accelerator is proposed. In the Gaussian pyramid and Differences of Gaussian (DoG) pyramid construction process, three design methods are proposed to reduce power consumption and improve information fidelity: a fast and slow dual clock domain design method with a reconfigurable design strategy is proposed to reduce the computation resources; a partial sum reuse design method is proposed to further reduce the computation resources and the amount of computation; a dynamic padding design method is proposed to solve the problem of information loss at image edges and corners after convolution operation. In the keypoint descriptor generation process, an optimized algorithm using circular region and polar coordinates is proposed to parallelize the main orientation assignment and descriptor generation to achieve high-speed processing, while maintaining a comparable matching accuracy with the state-of-the-art designs. The experiment results show that the proposed SIFT hardware accelerator is able to extract features by up to 162 frames per second ( $640times 480$ pixels) under 100 MHz, with the power consumption of 364.26 mW and en-rgy efficiency of 2.25 mJ/frame based on 180 nm technology, which is suitable for many high frame-rate AIoT applications including autonomous driving cars and unmanned aerial vehicles.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based
           Calibration for Nonlinear Amplitude and Phase Distortion

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      Authors: Danfeng Zhai;Wenning Jiang;Xinru Jia;Jingchao Lan;Mingqiang Guo;Sai-Weng Sin;Fan Ye;Qi Liu;Junyan Ren;Chixiao Chen;
      Pages: 4944 - 4957
      Abstract: This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Programmable On-Chip Hopf Bifurcation Circuit

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      Authors: Jennifer Hasler;
      Pages: 4958 - 4968
      Abstract: This effort discusses a programmable Hopf bifurcation element based on Transconductance Amplifiers (TA) that can be directly implemented in configurable hardware (e.g. an SoC FPAA). The TA Hopf bifurcation circuit shows the complete dynamics of a Van der Pol circuit, a Hopf bifurcation prototype. This Low-Pass Filter (LPF) TA-implemented ODE shows the necessary linear dynamics, as well as stable and oscillatory nonlinear dynamics expected near a Hopf bifurcation. This component directly uses the dynamics of the TA devices not translating equations, reducing the implementation complexity.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Capacitive Feedbacked Cold-Phase Compensator Analog Pre-Distorter and PAE
           Enhancer for K-Band CMOS PAs

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      Authors: Omar Z. Alngar;Adel Barakat;Ramesh K. Pokharel;
      Pages: 4969 - 4980
      Abstract: A K-band two-stage power amplifier (PA) with capacitive-feedbacked cold-phase compensator (cold-PC) linearizer and power-added-efficiency (PAE) enhancer is introduced in 180-nm CMOS technology. This cold-PC consists of two parts. First, a cold-FET analog pre-distorter (APD) with a new capacitive-feedbacked technique is proposed to improve the linear behavior of the PA by enhancing the corresponding APD’s compensation slope. The proposed implementation has a reduced insertion loss and a minimal chip area overhead. Second, a low-pass two-tunable inductive and capacitive PC is proposed to solve the phase shift problem at intermediate nodes that would enhance the PAE of the stacked-transistors configuration. The implemented PA achieves, at 23.5-GHz, a maximum measured PAE of 21.2%, output power at the 1-dB compression point (OP1dB) of 13.4-dBm, and saturated output power of 15-dBm using a total chip area of 0.58 mm2. Employing the proposed cold-PC results in a decrease of the measured error vector magnitude (EVM) of the 400-MHz 5G-NR of 64-QAM modulated signal and an increase of the OP1dB and its PAE by 2.5-dB and 7%, respectively (enhancement by 78% and 72% from the original case, respectively), which, to the best of authors’ knowledge, is the highest reported enhancement of the linearizers of k-band PAs.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Crystal-Less Clock Generation Technique for Battery-Free Wireless
           Systems

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      Authors: Ziyi Chang;Yunshan Zhang;Changgui Yang;Yuxuan Luo;Sijun Du;Yong Chen;Bo Zhao;
      Pages: 4981 - 4992
      Abstract: The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the $2^{mathrm{nd}}$ -order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8 $mu text{W}$ power.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • DTC Linearization via Mismatch-Noise Cancellation for Digital
           Fractional-N PLLs

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      Authors: Eslam Helal;Amr I. Eissa;Ian Galton;
      Pages: 4993 - 5006
      Abstract: Digital-to-time converter (DTC) based quantization noise cancellation (QNC) has recently been shown to enable excellent fractional- $N$ PLL performance, but it requires a highly-linear DTC. Known DTC linearization strategies include analog-domain techniques which involve performance tradeoffs and digital predistortion techniques which converge slowly relative to typical required PLL settling times. Alternatively, a DTC implemented as a cascade of 1-bit DTC stages can be made highly linear without special techniques, but such DTCs typically introduce excessive error from component mismatches which has so far hindered their use in low-jitter PLLs. This paper presents a background calibration technique that addresses this issue by adaptively canceling error from DTC component mismatches. The technique is entirely digital, is compatible with a large class of digital fractional- $N$ PLLs, and has at least an order of magnitude lower convergence time than the above-mentioned predistortion techniques. The paper presents a rigorous theoretical analysis closely supported by simulation results which quantifies the calibration technique’s convergence time and noise performance.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Gm -Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm
           Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing

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      Authors: Enis Kobal;Teerachot Siriburanon;Xi Chen;Hieu Minh Nguyen;Robert Bogdan Staszewski;Anding Zhu;
      Pages: 5007 - 5017
      Abstract: This paper presents a simple yet effective $G_{m}$ -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A 2 nJ/bit, 2.3% FSK Error Fully Integrated Sub-2.4 GHz Transmitter With
           Duty-Cycle Controlled PA for Medical Band

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      Authors: Heng Huang;Xiliang Liu;Zijian Tang;Wei Song;Yuwei Zhang;Xiaoyan Ma;Milin Zhang;Jintao Wang;Zhihua Wang;Guolin Li;
      Pages: 5018 - 5029
      Abstract: This paper proposed a fully integrated MBAN (2360–2400 MHz) continuous phase modulated transmitter (TX) with tunable less than 0dBm output power for medical band. A duty-cycle tuning strategy was proposed for the power amplifier (PA) featuring adaptive optimized efficiency for different output powers. A fully on-chip transformer-based match network was proposed to suppress the 2nd harmonic using a series $LC$ resonator and to suppress the 3rd harmonic by introducing a transformer inter-winding capacitor feedback path. A fractional-N all-digital phase locked loop (ADPLL) with a transformer-based digitally controlled oscillator (DCO) is employed to reduce power consumption as well as improve modulation quality. The transmitter was fabricated in 40-nm CMOS technology, occupying an active area of 0.48mm2. Experimental results show a 26% drain efficiency with −10dBm PA output and 4dB tunable range. A 2mW total power consumption was measured with a TX efficiency of 5% and an energy efficiency of 2nJ/bit. The measured 2nd and 3rd harmonic distortion of the output were −44.3dBm and −57.2dBm, respectively, with on-chip matching network. The measured FSK error of CPM was 2.3% with an M of 2 and 1.57% with an M of 4.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Balanced-to-Unbalanced Quadrature Couplers With Wide-Band Common-Mode
           Suppression

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      Authors: Wenjie Feng;Bosang Pan;Wenquan Che;Yongrong Shi;Xinyu Zhou;Quan Xue;
      Pages: 5030 - 5038
      Abstract: In this paper, two types of balanced-to-unbalanced quadrature couplers with six hybrid ports and arbitrary power division ratio are proposed. For Type 1, the quadrature coupler can realize two power division functions, including balanced/unbalanced to balanced-unbalanced-hybrid, and for Type 2, the quadrature coupler contains balanced -to-unbalanced and unbalanced-to-balanced power division functions. To reduce the circuit size, double-sided parallel-strip line (DSPSL) swap structure is used to replace the half-wavelength transmission line, and compact circuit size can be easily achieved. To validate the performance of the quadrature couplers, two types of the balanced-to-unbalanced quadrature couplers centered at 1 GHz with power division ratios 1:1 and 3:1 are fabricated and measured, respectively. The common mode suppression higher than 10 dB (bandwidths over than 176%) can be realized, the isolation and in-band matching level can be also improved.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Analysis of Conditional Stability and Unconditional Stability and
           Instability for Microwave 3-Ports

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      Authors: Giancarlo Lombardi;Bruno Neri;
      Pages: 5039 - 5049
      Abstract: A full and rigorous treatment of conditional and unconditional stability and instability for an active 3-port microwave circuit, represented at a given frequency by $S$ -parameters, is carried out. By terminating a given port with a variable termination one may study at the input and the output of the resulting 2-port circuit the occurrence of unconditional stability and instability, as well as of special cases of conditional stability, defined as reactive unconditional stability or instability. Such conditions are especially relevant in microwave oscillator design and were exhaustively identified for the first time and treated in previous analysis by the authors. Drawing from its conclusions, one obtains in the plane of the variable termination and with a simple algorithm, a single parametric representation, providing at once, in a closed and direct form, the entire collection of boundaries of the regions, wherein the listed conditions occur at ports of the resulting 2-port circuit. Guidelines for the design of microwave amplifiers and oscillators, both in series and shunt configuration, are sketched. Numerical examples, validated by simulations, are also presented.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct
           ToF Imaging LiDAR Applications

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      Authors: Hao Zheng;Rui Ma;Xiayu Wang;Dong Li;Jin Hu;Yang Liu;Zhangming Zhu;
      Pages: 5050 - 5058
      Abstract: To increase the light detection and ranging (LiDAR) system spatial resolution, the multiple photodetectors are typically deployed in the receiver. An equivalent linear-array receiver with multiplexing operation scheme is presented for the direct time of flight (dToF) LiDAR applications. In particular, the analog front-end (AFE) circuit of the proposed receiver mainly consists of eight transimpedance preamplifiers (preTIAs), a dummy preTIA, a post amplifier (PA) with an 8-to-1 multiplexer, an analog output buffer and a timing discriminator. The proposed AFE circuit, which achieves a transimpedance gain of ~106 dB $Omega $ , a bandwidth of ~220 MHz, an equivalent input-referred noise current of ~5.1 pA/Hz0.5 and a channel switchover time of 6 ns, was fabricated in a 65 nm standard CMOS technology. The associated DC power consumption is 137 mW with a power supply of 2.5 V. The total area of the proposed AFE circuit, which includes the circuit core, bias circuits and I/O PADs, is approximately equal to $1.2times 1.2$ mm2.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • −11 to 7 dBm Power Range, Triple Band RF Energy Harvesting System With
           99.9% Peak Tracking Efficiency and Improved PCE

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      Authors: Eunho Choi;Gyeongho Namgoong;Woojin Park;Suhwan Kim;Jiwon Kim;Bonyoung Lee;Franklin Bien;
      Pages: 5059 - 5071
      Abstract: This paper presents a triple-band radio frequency (RF) energy harvesting system with 99.99% peak tracking efficiency and the triple band rectifier achieves the 4.6% improvement in the power conversion efficiency (PCE). The proposed system has a power range of −11 to 7 dBm with the three bands targeted on 900, 1900, and 2400 MHz. In this paper, the voltage and power characteristics of the triple-band rectifier at each band are extracted as raw data by measurement. The DC-DC boost converter is applied to achieve the maximum power point tracking (MPPT), which exploits the hill-climbing MPPT method. The method is implemented with register logics and power calculator. The converter’s voltage range of 0.1V to 2V is achieved, and the converter facilitates to achieve the highest tracking efficiency of 99.99%, 98.57%, 99.85% at each bands. The performance is verified through experimental results showing PCE improvement and over 87% tracking efficiency in a wide power range at triple bands. The triple-band rectifier with transmission line is fabricated on FR-4 substrate with active area 35.7 cm2, and the DC-DC boost converter with MPPT is implemented in a $0.18~mu text{m}$ CMOS process with an active area of 0.94 mm2.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Analysis of Offset Spurs in Phase-Locked-Loops Employing
           Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation

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      Authors: Masaru Osada;Zule Xu;Ryoya Shibata;Tetsuya Iizuka;
      Pages: 5072 - 5084
      Abstract: Fractional-N phase-locked loops using Harmonic-Mixer (HM) based feedback offer good phase noise and spur performance without relying on complex calibration schemes. The HMs in prior art are often realized using the Sample-and-Hold (S/H) operation. This, however, can result in unwanted tones due to intermodulation, which must be suppressed using properly-designed filters. This paper proposes a simple and accurate analysis of the location and magnitude of these tones. We also provide a design guideline for the HM based on this analysis to properly suppress these tones. The results are supported through behavioral and transistor-level simulations.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Voltage Control Ratiometric Readout Technique With Improved Dynamic Range
           and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer

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      Authors: Longjie Zhong;Shubin Liu;Donglai Xu;Zhangming Zhu;
      Pages: 5085 - 5095
      Abstract: MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, the voltage control readout technique suffers from low dynamic range and low power efficiency (in terms of $mathbf {FoM}$ ). In this paper, the voltage control ratiometric (VCR) readout technique is proposed to improve both dynamic range and power efficiency. The VCR readout technique is demonstrated in a readout circuit fabricated in a commercial 0.18 $mu {mathrm{ m}}$ 1.8V/5.0V CMOS process. Compared to the traditional voltage readout circuit fabricated with the same CMOS process and tested with the same sensing element, the VCR readout circuit improves full input signal range by $mathbf {3.5dB}$ (from $boldsymbol {pm 8g}$ to $boldsymbol {pm 12g}$ ) and the noise floor by $mathbf {9.5dB}$ (from $mathrm {mathbf {804~mu g/}}sqrt {mathbf {Hz}} $ to $mathbf {270~mu g/}sqrt {mathbf {Hz}} $ ). As a result, the dynamic range is improved by $mathbf {13.0dB}$ (from $mathbf {44.0dB}$ to $mathbf {57.0dB}$ ), the $mathbf {Fo}mathbf {M}_{mathbf {1}}$ is improved from $mathbf {310pJ}$ to $mathrm {mathbf {83pJ }}$ and the $mathbf {Fo}mathbf {M}_{mathbf {2}}$ is improved from $mathbf {1977~mu Wcdot mu g/Hz}$ to $mathbf {796~mu Wcdot mu g/Hz}$ .
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash
           LiDAR

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      Authors: Jin Hu;Xiayu Wang;Dong Li;Yang Liu;Rui Ma;Zhangming Zhu;
      Pages: 5096 - 5107
      Abstract: This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18- $mu text{m}$ HV-CMOS technology in a 32 $times32$ array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to
           Machine Learning Attacks and High Energy Efficiency

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      Authors: Jiahao Liu;Yan Zhu;Chi-Hang Chan;Rui Paulo Martins;
      Pages: 5108 - 5120
      Abstract: This paper presents an entropy-source-preselection-based strong PUF (ESP-PUF). Through the presented entropy-source-preselection scheme, we will convert first the input challenge bits of the ESP-PUF into the entropy selection signals through the front-end selection network, realized based on an XOR tree. Then the entropy selection signals serve as the power-on indicator to randomly select the back-end entropy sources to generate the raw responses. Utilizing this preselection scheme, we can fulfill both ultra-low power and strong resilience to machine learning (ML) attacks. An effective randomness-enhancement block amplifies the randomness of the raw responses thus alleviating their bias. Moreover, we propose an obfuscation-based protection mechanism to further protect the root challenge-response pairs (CRPs) of the entropy sources and enhance the resilience to ML attacks. Fabricated in 65nm CMOS LP technology, the proposed ESP-PUF shows a high energy efficiency of 0.46pJ/bit. Meanwhile, it demonstrates an average bit-error rate (BER) of 5.83% in the worst-case for the temperature range of −20°C to 120°C and a supply voltage variation of ±10%. The proposed CRPs filtering method can suppress the worst-case BER to a value $< 6.7times 10 ^{-6}$ , presenting high stability. The proposed ESP-PUF occupies an active area of 0.0122 mm2. After training for 1M CRPs samples, the prediction accuracy of the adopted ML algorithms is still ~50%, confirming a strong resilience of the proposed ESP-PUF.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Interleaved Challenge Loop PUF: A Highly Side-Channel Protected
           Oscillator-Based PUF

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      Authors: Lars Tebelmann;Jean-Luc Danger;Michael Pehl;
      Pages: 5121 - 5134
      Abstract: Physical Unclonable Functions (PUFs) leverage manufacturing variations to generate device-specific keys during runtime only, overcoming the need for protection after power-off as for Non-Volatile Memory. The main challenges of PUF-based key storage are reliability of the response and sensitivity to Side-Channel Analysis (SCA). Oscillator-based PUFs are particularly sensitive to frequency spectrum SCA. Existing countermeasures can protect sign-based bit derivation that requires error correction or discarding unreliable bits to achieve reliable key generation. Amplitude-based bit derivation enhances the reliability of oscillator-based PUFs without discarding unsteady response bits, keeping a high entropy. However, existing lightweight countermeasures against SCA are not applicable for this case. This raises the demand for an alternative solution. This work targets the protection of amplitude-based bit derivation combined with the Loop PUF, an oscillator-based PUF primitive well suited for key generation. It presents the Interleaved Challenge Loop PUF (ICLooPUF), a side-channel-hardened offspring of the Loop PUF that uses dynamic challenge interleaving. The SCA-protected PUF primitive is applicable to amplitude-based and sign-based bit derivation methods, and requires a low hardware overhead. Theoretical and experimental results show the efficiency of the protection mechanism.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • APTPU: Approximate Computing Based Tensor Processing Unit

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      Authors: Mohammed E. Elbtity;Peyton S. Chandarana;Brendan Reidy;Jason K. Eshraghian;Ramtin Zand;
      Pages: 5135 - 5146
      Abstract: We propose an approximate tensor processing unit (APTPU), which includes two main components: (1) approximate processing elements (APEs) consisting of a low-precision multiplier and an approximate adder, and (2) pre-approximate units (PAUs) which are shared among the APEs in the APTPU’s systolic array, functioning as the steering logic to pre-process the operands and feed them to the APEs. We conduct extensive experiments to evaluate the performance of the APTPU across various configurations and various workloads. The results show that the APTPU’s systolic array achieves up to $5.2times textit {TOPS}/mm^{2}$ and $4.4times textit {TOPS}/W$ improvements compared to that of a conventional systolic array design. The comparison between the proposed APTPU and in-house TPU designs shows that we can achieve approximately $2.5times $ and $1.2times $ area and power reduction, respectively, while realizing comparable accuracy. Finally, a comparison with the state-of-the-art approximate systolic arrays shows that the APTPU can realize up to $1.58times $ , $2times $ , and $1.78times $ , reduction in delay, power, and area, respectively, while using similar design specifications and synthesis constraints.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning

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      Authors: Congyi Sun;Haohan Sun;Jin Xu;Jianing Han;Xinyuan Wang;Xinyu Wang;Qinyu Chen;Yuxiang Fu;Li Li;
      Pages: 5147 - 5158
      Abstract: In this paper, we propose a spike-time based unsupervised learning method using spiking-timing dependent plasticity (STDP). A simplified linear STDP learning rule is proposed for the energy efficient weight updates. To reduce unnecessary computations for the input spike values, a stop mechanism of the forward pass is introduced in the forward pass. In addition, a hardware-friendly input quantization scheme is used to reduce the computational complexities in both the encoding phase and the forward pass. We construct a two-layer fully-connected spiking neuron network (SNN) based on the proposed method. Compared to general rate-based SNNs trained by STDP, the proposed method reduces the complexity of network architecture (an extra inhibitory layer is not needed) and the computations of synaptic weight updates. According to the fixed-point simulation with 9-bit synaptic weights, the proposed SNN with 6144 excitatory neurons achieves 96% of recognition accuracy on MNIST dataset without any supervision. An SNN processor that contains 384 excitatory neurons with on-chip learning capability is designed and implemented with 28 nm CMOS technology based on the proposed low complexity methods. The SNN processor achieves an accuracy of 93% on MNIST dataset. The implementation results show that the SNN processor achieves a throughput of 277.78k FPS with $0.50~mu text{J}$ /inference energy consuming in inference mode, and a throughput of 211.77k FPS with $0.66~mu text{J}$ /learning energy consuming in learning mode.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Signal Flow Graph Approach to the Resolution of Spherical Triangles
           Using CORDIC

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      Authors: Jean-Marc Delosme;
      Pages: 5159 - 5170
      Abstract: Jack Volder’s original motivation for the COordinate DIgital Computer (CORDIC) was the real-time digital solution of spherical triangle equations employed in airborne navigation, for which he presented a solution flow diagram without detailing its construction. In fact, without a strong guidance, it is not easy to express the solutions of linear algebraic problems such as those involved when solving spherical triangles as cascades of CORDIC operations—called by Volder CORDIC solution-flow diagrams—and thus to devise a system solution on CORDIC processing units. As it gives a bird’s eye view of the system design problem, a signal flow graph representation of the underlying system of linear equations provides such guidance; the operations leading to the problem solution are uncovered by performing a sequence of partial flow reversals on the graph. The approach is illustrated by the problem where two sides and the included angle of a spherical triangle are given, called SAS problem, that is encountered in applications as diverse as air navigation, lattice filters for adaptive processing, and dexterous robotic hands. The solutions thus obtained are at least as efficient as existing ones, whenever available.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional
           Hardware Accelerators

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      Authors: Leonardo Rezende Juracy;Alexandre de Morais Amory;Fernando Gehm Moraes;
      Pages: 5171 - 5184
      Abstract: Convolutional Neural Networks (CNN) are widely adopted for Machine Learning (ML) tasks, such as classification and computer vision. GPUs became the reference platforms for both training and inference phases of CNNs due to their tailored architecture to the CNN operators. However, GPUs are power-hungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. However, the literature presents gaps regarding analyses and comparisons of these accelerators to evaluate Power-Performance-Area (PPA) trade-offs. Typically, the literature estimates PPA from the number of executed operations during the inference phase, such as the number of MACs, which may not be a good proxy for PPA. Thus, it is necessary to deliver accurate hardware estimations, enabling design space exploration (DSE) to deploy CNNs according to the design constraints. This work proposes a fast and accurate DSE approach for CNNs using an analytical model fitted from the physical synthesis of hardware accelerators. The model is integrated with CNN frameworks, like TensorFlow, to generate accurate results. The analytic model estimates area, performance, power, energy, and memory accesses. The observed average error comparing the analytical model to the data obtained from the physical synthesis is smaller than 7%.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG
           by On-Chip Monitor With Less Recovery Impact

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      Authors: Yarong Fu;Wang Wang;Xin Zhong;Manni Li;Zixu Li;Qing Dong;Yu Jiang;Yinyin Lin;
      Pages: 5185 - 5194
      Abstract: An on-chip digital sensor has been demonstrated in 28nm High-k Metal Gate (HKMG) for bias temperature instability (BTI) statistical characterization with the benefits: fast statistical measurement, less recovery impact (Toff-stress@around 15ns, Fast Period Sampling (FPS) @around 300ns), and high resolution (0.1mV of $Delta $ Vth). As far as we know, it is the first time to statistically observe the very early stage of trap recovery of individual device in practical scenario, e.g., static random-access memory (SRAM). We find that three Negative BTI (NBTI) recovery behaviors, 2/3/4-step with clear transition slope, co-exist in HKMG devices. Our further analysis ascribes the phenomena to co-existing of four types of defects in 28nm HKMG Devices Under Test (DUTs). Three types are recoverable and one unrecoverable. The transition slope instead of steep drop between steps is the aggregative effects of one certain type of recoverable defect contained across DUTs. More types of defects lead to more Vth shift. But the contribution percentage of unrecoverable defect remains quite close, while recoverable defects dominate the Vth degradation. Only when the Toff-stress is less than the starting point of 1st recover step (within 1 $mu text{s}$ in our case), accurate and consistent Vth degradation data can be achieved.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation

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      Authors: Erfan Abbasian;
      Pages: 5195 - 5205
      Abstract: This paper aims to explore the design of a novel highly stable low-energy 10T (SLE10T) SRAM cell for near-threshold operation. The latch core of the proposed design consists of a cross-coupled structure of a tri-state inverter and a standard inverter. The tri-state inverter is switched to the high-impedance mode during a write operation to temporarily float the data node, improving writability. In addition, read stability is equivalent to hold stability due to considering a separate path for read current flow, as well as a built-in read-assist scheme to force the ‘0’ storing node to ground. Leakage and dynamic power consumptions in the designed cell are reduced with the help of single-bitline structure and stacking of transistors. The simulation results in a 7-nm FinFET at a 0.5 V show that the SLE10T improves read stability by at least $1.31times $ compared to read-disturbance SRAMs and offers the second-highest writability, improvement of at least $1.10times $ . Leakage power dissipation is reduced in the SLE10T by at least $1.10times $ . Moreover, it improves read/write energy by at least $1.01times /1.03times $ . However, the area of the SLE10T bitcell is $0.02~mu text{m}^{2}$ , which is $1.657times /1.318times $ larger than the conventional 6T/8T bitcell.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Quantum Protocol for Secure Multiparty Logical AND With Application to
           Multiparty Private Set Intersection Cardinality

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      Authors: Run-Hua Shi;Yi-Fei Li;
      Pages: 5206 - 5218
      Abstract: Like addition, subtraction, multiplication and division, logical AND is a fundamental arithmetic operation in scientific computing. In this paper, we first consider and define a new privacy-preserving problem, i.e., Secure Multiparty Logical AND (SMLA), in which multiple participants can jointly compute the logical AND of their respective private bits. Furthermore, we present a novel quantum SMLA protocol by employing phase-matching quantum conference key agreement and perfect quantum encryption, and design the corresponding quantum circuits. The proposed quantum SMLA protocol can ensure information-theoretical security. What’s more, we design a private grouping strategy to reduce the communicational complexity and accordingly present an improved quantum SMLA protocol with the linear communicational rounds. In addition, we investigate its applications and design a feasible quantum Multiparty Private Set Intersection Cardinality (MPSI-CA) protocol based on the improved quantum SMLA protocol, in which multiple participants jointly compute the intersection cardinality without revealing their respective private sets. Finally, we verify the correctness and the feasibility of the proposed quantum protocols by circuit simulations in IBM Qiskit.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Fracmemristor Oscillator: Fractional-Order Memristive Chaotic Circuit

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      Authors: Yi-Fei Pu;Bo Yu;Qiu-Yan He;Xiao Yuan;
      Pages: 5219 - 5232
      Abstract: In this paper, the Fractional-Order Memristive Chaotic Circuit (FMCC) is proposed to be achieved by the fracmemristor, which is a portmanteau of “fractional-order” and “memristor”. Considering the unique fingerprints and nonlinearities of fracmemristors, it is natural to ponder a challenging theoretical problem to generalize the Integer-Order Memristive Chaotic Circuit (IMCC) to the FMCC. Motivated by this inspiration, the paper proposes an FMCC by replacing the diode in Chua’s chaotic circuit with a fracmemristor and a negative resistor in parallel. To simplify analysis, a new Cubic Nonlinear Voltage-Controlled Capacitive Ladder Scaling Fracmemristor (CVCLF) is proposed to implement the FMCC. New fingerprints are found in the CVCLF. Compared with the IMCC, dynamical behaviors of the FMCC are not only related to circuit parameters and initial conditions, but also related to the circuit stage and the operational order. The FMCC provides two extra degrees of freedom. Numerical simulations and hardware experiments demonstrate that the FMCC has multistability, transient chaos, state transition phenomena, etc. A significant advantage of the FMCC is that it possesses the fractional-order-sensitivity characteristic, which represents its dynamical behaviors change with the operational order. The proposed FMCC is the first application of fracmemristors in chaos.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Efficient Learning Strategies for Machine Learning-Based Characterization
           of Aging-Aware Cell Libraries

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      Authors: Florian Klemme;Hussam Amrouch;
      Pages: 5233 - 5246
      Abstract: Machine learning (ML)-driven standard cell library characterization enables rapid, on-the-fly generation of cell libraries, opening the door for extensive design-space exploration and other, previously infeasible approaches. However, the benefits of ML-based cell library characterization are strongly limited by its high demand in training data and the costly SPICE simulation required to generate the training samples. Therefore, efficient learning strategies are needed to minimize the required training data for ML models while still sustaining high prediction accuracy. In this work, we explore multiple active and passive learning strategies for ML-based cell library characterization with focus on aging-induced degradation. While random sampling and greedy sampling strategies operate with low computational overhead, active learning considers the performance of ML models to find the most valuable samples for training. We also introduce a hybrid approach of active learning and greedy sampling to optimize the trade-off between reduction in training samples and computational overhead. Our experiments demonstrate an achievable training data reduction of up to 77% compared to the state of the art, depending on the targeted accuracy of the ML models.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D
           Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination

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      Authors: Changle Zhi;Gang Dong;Yang Wang;Zhangming Zhu;Yintang Yang;
      Pages: 5247 - 5258
      Abstract: Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Prescribed-Time Asymptotic Tracking Control of Strict Feedback Systems
           With Time-Varying Parameters and Unknown Control Direction

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      Authors: Wenrui Shi;Mingzhe Hou;Guangren Duan;
      Pages: 5259 - 5272
      Abstract: This paper considers the global prescribed-time asymptotic tracking control problem for uncertain strict feedback nonlinear systems with time-varying parameters and an unknown control direction. A novel prescribed-time scaling function is constructed, and the frequently used basic lemma on the Nussbaum function is modified to adapt to the situation where the initial value of the control coefficient is zero. With the help of the nonlinear mapping technique, the congelation of variables method and the backstepping method, an adaptive tracking control method is presented, which exhibits several attractive features: (1) all the closed-loop signals are bounded; (2) for any initial condition, the tracking error can be confined within a prescribed zone in a prescribed time; and (3) the asymptotic convergence of the tracking error is ensured. The effectiveness of the proposed control method is demonstrated by using two simulation examples.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Robust Hierarchical Pinning Control for Nonlinear Heterogeneous Multiagent
           System With Uncertainties and Disturbances

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      Authors: Deyuan Liu;Hao Liu;Kexin Liu;Haibo Gu;Jinhu Lü;
      Pages: 5273 - 5285
      Abstract: This paper investigates the coordination control problem for a special nonlinear heterogeneous multi-agent system consisting of tail-sitter unmanned aerial vehicles and unmanned ground vehicles with uncertainties and disturbances. A robust hierarchical pinning control scheme is proposed for the heterogeneous multi-agent system to restrain the uncertainties and disturbances and achieve coordination scenarios. The heterogeneous multi-agent system can realize coordination tasks by selecting proper pinning nodes and estimating coupling strength. The robustness of the whole system is proven utilizing the Lyapunov stability theorem. The effectiveness of the robust hierarchical pining control method is validated by simulation scenarios.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Fixed-Time Consensus Tracking of Multiagent System Under DOS Attack With
           Event-Triggered Mechanism

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      Authors: Junkang Ni;Feiyu Duan;Peng Shi;
      Pages: 5286 - 5299
      Abstract: This paper focuses on fixed-time event-triggered consensus tracking of high-order MAS over digraph and under DOS attack. The considered DOS attack is divided into connectivity-maintained attack and connectivity-broken attack. To detect connectivity-broken attack under event-triggered environment, a new cyberattack detection algorithm is presented. Next, using cyberattack detection results, a fixed-time event-triggered distributed observer is developed to estimate the leader’s states in the presence of DOS attack, which conducts event-triggered update in the normal condition and under connectivity-maintained attack and stops updating in the presence of connectivity-broken attack. Then, an adaptive event-triggered prescribed-time dynamic surface consensus tracking control protocol is proposed to eliminate mismatched disturbances caused by estimation error and achieve prescribed-time convergence of the tracking error. Stability analysis proves fixed-time convergence of the developed consensus tracking strategy and non-zeno analysis shows the developed distributed observer and consensus tracking control strategy exclude zeno behavior. This paper contributes to proposing a fixed-time leader-follower consensus control strategy for MAS under DOS attack via event-triggered approach, which eliminates the effect of DOS attack, achieves consensus tracking within a fixed time and reduces resources consumption. Finally, simulation results show the effectiveness and superiority of the developed consensus tracking approach.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Distributed Containment Control for Human-in-the-Loop MASs With Unknown
           Time-Varying Parameters

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      Authors: Guohuai Lin;Hongyi Li;Hui Ma;Qi Zhou;
      Pages: 5300 - 5311
      Abstract: This paper considers the distributed containment control problem for human-in-the-loop (HiTL) multiagent systems (MASs) subject to unknown time-varying parameters and input saturation. A smooth function containing positive integrable time-varying function is embedded in the controller to compensate for the negative effects of unknown time-varying parameters and uncertain disturbances. Meanwhile, an auxiliary system with the same order as the considered system is skillfully introduced into the backstepping control method to overcome the problem of input saturation. By constructing an adaptive command filter with error compensation mechanism, the problems of the computation burden and filtering errors are solved simultaneously. Moreover, the output signals of followers can converge into the convex hull spanned by multiple dynamic leaders which are controlled by a human operator. Based on the Lyapunov stability theory, it is shown that the containment errors can asymptotically converge into the prescribed bounds. Finally, two simulation examples evaluate the effectiveness of the presented control scheme.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Neural-Network-Based Control With Dynamic Event-Triggered Mechanisms Under
           DoS Attacks and Applications in Load Frequency Control

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      Authors: Xueli Wang;Derui Ding;Xiaohua Ge;Hongli Dong;
      Pages: 5312 - 5324
      Abstract: The paper is concerned with the supplementary control based on adaptive dynamic programming (ADP) for a class of discrete-time networked system with the simultaneous presence of dynamic event-triggered mechanisms and Denial-of-Service (DoS) attacks. The dynamic behavior of DoSs is described by a model with the appropriate frequency and durations. A neural network (NN)-based observer is first designed to estimate system states in order to resolve the limitation in ADP-based control due mainly to data sparsity. The performance analysis and gain design of the NN-based observer are systematically discussed in light of the switched system theory combined with the average dwell-time method. Subsequently, the policy iteration algorithm with an actor-critic structure is developed to implement the designed supplementary ADP controller, and the corresponding condition on learning rates in weight updating rules is derived by virtue of the well-known Lyapunov stability. Finally, the effectiveness of the developed approach is demonstrated by an application in load frequency control of power systems.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

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      Authors: Peng-Wei Zhang;Sheng Jiang;Francis C. M. Lau;Chiu-Wing Sham;
      Pages: 5325 - 5338
      Abstract: Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of $10^{-5}$ at around $E_{b}/N_{0}=-0.40$ dB. The decoder can also achieve the same BER at $E_{b}/N_{0}=-1.14$ dB with a reduced throughput of 0.20 Gbps.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Analysis and Design of Class-E M Power Amplifier at Subnominal Operation

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      Authors: Tian Li;Mingyu Li;Zhijiang Dai;Li Li;Yi Jin;Changzhi Xu;Weimin Shi;Jingzhou Pang;Hailin Cao;
      Pages: 5339 - 5352
      Abstract: In this paper, an analytical design procedure for subnominal class $E_{M}$ power amplifier (PA) is proposed. The main circuit only satisfies zero voltage switching (ZVS) and zero current switching (ZCS) conditions, which provide two extra design freedoms compared to the traditional class $E_{M}$ PA. All the parameters in the circuit can be expressed as a function of the two design freedoms, and more selectable circuits with higher efficiency can be provided. Meanwhile, the design freedoms can also be applied to improve circuit performance by selecting suitable values. To validate the analytical process, two subnominal class $E_{M}$ circuits are fabricated and measured with specific design freedoms at the operating frequency 2 MHz. The obtained output power for the two designs are 5.92 W and 13.45 W, and the efficiency can reach 96.1% and 97.3%, respectively. Compared to the traditional class $E_{M}$ PA, the transistor peak voltages of the main and auxiliary circuits in the first design can be reduced by 10% and 27%, and the transistor peak voltage of the auxiliary circuit in the second design is reduced by 25%, which demonstrates that the subnominal operation can be well applied for decreasing the transistor voltage stress. The experimental results show the validity of the presented theoretical analysis.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Introducing IEEE Collabratec

    • Free pre-print version: Loading...

      Pages: 5353 - 5353
      Abstract: Advertisement.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • Call for Papers: Special Issue Dedicated to the 70th Anniversary of IEEE
           Transactions on Circuits and Systems I Regular Papers

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      Pages: 5354 - 5355
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
  • IEEE Transactions on Circuits and Systems--I: Regular Papers Information
           for Authors

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      Pages: 5356 - 5356
      Abstract: Provides instructions and guidelines to prospective authors who wish to submit manuscripts.
      PubDate: Dec. 2022
      Issue No: Vol. 69, No. 12 (2022)
       
 
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