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  Subjects -> AERONAUTICS AND SPACE FLIGHT (Total: 120 journals)
Showing 1 - 30 of 30 Journals sorted by number of followers
AIAA Journal     Hybrid Journal   (Followers: 1191)
SpaceNews     Free   (Followers: 825)
Journal of Spacecraft and Rockets     Hybrid Journal   (Followers: 771)
Journal of Propulsion and Power     Hybrid Journal   (Followers: 610)
Acta Astronautica     Hybrid Journal   (Followers: 495)
Advances in Space Research     Full-text available via subscription   (Followers: 457)
Aviation Week     Full-text available via subscription   (Followers: 437)
Aerospace Science and Technology     Hybrid Journal   (Followers: 427)
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 384)
Journal of Aircraft     Hybrid Journal   (Followers: 335)
Control Systems     Hybrid Journal   (Followers: 314)
IEEE Aerospace and Electronic Systems Magazine     Full-text available via subscription   (Followers: 282)
Journal of Navigation     Hybrid Journal   (Followers: 278)
Aircraft Engineering and Aerospace Technology     Hybrid Journal   (Followers: 261)
Gyroscopy and Navigation     Hybrid Journal   (Followers: 258)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 204)
Space Science International     Open Access   (Followers: 200)
Space Science Reviews     Hybrid Journal   (Followers: 97)
International Journal of Aerospace Engineering     Open Access   (Followers: 82)
Progress in Aerospace Sciences     Full-text available via subscription   (Followers: 80)
Advances in Aerospace Engineering     Open Access   (Followers: 69)
Journal of Aerospace Engineering     Full-text available via subscription   (Followers: 69)
Propulsion and Power Research     Open Access   (Followers: 68)
Aerospace     Open Access   (Followers: 60)
Space Safety Magazine     Free   (Followers: 51)
Space Research Today     Full-text available via subscription   (Followers: 48)
Proceedings of the Institution of Mechanical Engineers Part G: Journal of Aerospace Engineering     Hybrid Journal   (Followers: 46)
International Journal of Aeroacoustics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Circuits and Systems I: Regular Papers     Hybrid Journal   (Followers: 39)
International Journal of Aerodynamics     Hybrid Journal   (Followers: 37)
Canadian Aeronautics and Space Journal     Full-text available via subscription   (Followers: 34)
Journal of Aerospace Information Systems     Hybrid Journal   (Followers: 34)
International Journal of Aerospace Sciences     Open Access   (Followers: 32)
Journal of Aeronautics & Aerospace Engineering     Open Access   (Followers: 31)
Space Policy     Hybrid Journal   (Followers: 30)
CEAS Aeronautical Journal     Hybrid Journal   (Followers: 29)
Journal of Space Weather and Space Climate     Open Access   (Followers: 27)
Aviation Psychology and Applied Human Factors     Hybrid Journal   (Followers: 27)
Russian Aeronautics (Iz VUZ)     Hybrid Journal   (Followers: 24)
Egyptian Journal of Remote Sensing and Space Science     Open Access   (Followers: 24)
Artificial Satellites     Open Access   (Followers: 23)
International Journal of Aerospace Psychology     Hybrid Journal   (Followers: 23)
Journal of Aerospace Information Systems     Hybrid Journal   (Followers: 22)
Annual of Navigation     Open Access   (Followers: 22)
Chinese Journal of Aeronautics     Open Access   (Followers: 21)
Nonlinear Dynamics     Hybrid Journal   (Followers: 20)
Aerospace Medicine and Human Performance     Full-text available via subscription   (Followers: 19)
Journal of Aerospace Engineering & Technology     Full-text available via subscription   (Followers: 18)
Journal of Aerodynamics     Open Access   (Followers: 18)
Aerospace Scientific Journal     Open Access   (Followers: 18)
Journal of Wind Engineering and Industrial Aerodynamics     Hybrid Journal   (Followers: 17)
Aviation     Open Access   (Followers: 17)
International Journal of Space Structures     Full-text available via subscription   (Followers: 17)
Research & Reviews : Journal of Space Science & Technology     Full-text available via subscription   (Followers: 17)
Proceedings of the Human Factors and Ergonomics Society Annual Meeting     Hybrid Journal   (Followers: 16)
Fatigue of Aircraft Structures     Open Access   (Followers: 15)
International Journal of Satellite Communications Policy and Management     Hybrid Journal   (Followers: 13)
Frontiers in Astronomy and Space Sciences     Open Access   (Followers: 12)
Elsevier Astrodynamics Series     Full-text available via subscription   (Followers: 12)
Aeronautical Journal, The     Hybrid Journal   (Followers: 12)
International Journal of Crashworthiness     Hybrid Journal   (Followers: 12)
Journal of Airline and Airport Management     Open Access   (Followers: 12)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 11)
Journal of Aviation Technology and Engineering     Open Access   (Followers: 11)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 11)
Air Force Magazine     Full-text available via subscription   (Followers: 11)
COSPAR Colloquia Series     Full-text available via subscription   (Followers: 11)
International Journal of Space Technology Management and Innovation     Full-text available via subscription   (Followers: 10)
Aviation in Focus - Journal of Aeronautical Sciences     Open Access   (Followers: 10)
Journal of Aircraft and Spacecraft Technology     Open Access   (Followers: 9)
Population Space and Place     Hybrid Journal   (Followers: 9)
Journal of Aeronautical Materials     Open Access   (Followers: 9)
International Journal of Aviation Management     Hybrid Journal   (Followers: 9)
Transportmetrica A : Transport Science     Hybrid Journal   (Followers: 9)
Journal of the Astronautical Sciences     Hybrid Journal   (Followers: 9)
Advances in Aerospace Science and Technology     Open Access   (Followers: 8)
Air Medical Journal     Hybrid Journal   (Followers: 8)
Journal of Space Safety Engineering     Hybrid Journal   (Followers: 8)
International Journal of Aviation Technology, Engineering and Management     Full-text available via subscription   (Followers: 7)
Journal of the American Helicopter Society     Full-text available via subscription   (Followers: 7)
Journal of Aerospace Technology and Management     Open Access   (Followers: 7)
International Journal of Applied Geospatial Research     Hybrid Journal   (Followers: 7)
New Space     Hybrid Journal   (Followers: 6)
Aerospace Systems     Hybrid Journal   (Followers: 6)
International Journal of Turbo and Jet-Engines     Hybrid Journal   (Followers: 6)
RocketSTEM     Free   (Followers: 6)
Civil Aviation High Technologies     Open Access   (Followers: 5)
International Journal of Aviation, Aeronautics, and Aerospace     Open Access   (Followers: 5)
REACH - Reviews in Human Space Exploration     Full-text available via subscription   (Followers: 5)
International Journal of Sustainable Aviation     Hybrid Journal   (Followers: 5)
Aviation Advances & Maintenance     Open Access   (Followers: 5)
Cosmic Research     Hybrid Journal   (Followers: 5)
Unmanned Systems     Hybrid Journal   (Followers: 5)
Space and Polity     Hybrid Journal   (Followers: 4)
Life Sciences in Space Research     Hybrid Journal   (Followers: 4)
Aerotecnica Missili & Spazio : Journal of Aerospace Science, Technologies & Systems     Hybrid Journal   (Followers: 4)
Astrodynamics     Hybrid Journal   (Followers: 4)
Investigación Pecuaria     Open Access   (Followers: 3)
Aerospace technic and technology     Open Access   (Followers: 3)
Journal of Spatial Science     Hybrid Journal   (Followers: 3)
ASTRA Proceedings     Open Access   (Followers: 3)
Journal of KONBiN     Open Access   (Followers: 3)
Problemy Mechatroniki. Uzbrojenie, lotnictwo, inżynieria bezpieczeństwa / Problems of Mechatronics. Armament, Aviation, Safety Engineering     Open Access   (Followers: 3)
npj Microgravity     Open Access   (Followers: 3)
Journal of Astrobiology & Outreach     Open Access   (Followers: 3)
Journal of Aviation/Aerospace Education & Research     Open Access   (Followers: 2)
IEEE Journal on Miniaturization for Air and Space Systems     Hybrid Journal   (Followers: 2)
Microgravity Science and Technology     Hybrid Journal   (Followers: 2)
Вісник Національного Авіаційного Університету     Open Access   (Followers: 2)
International Journal of Aeronautical and Space Sciences     Hybrid Journal   (Followers: 2)
Ciencia y Poder Aéreo     Open Access   (Followers: 2)
MAD - Magazine of Aviation Development     Open Access   (Followers: 2)
Journal of the Australasian Society of Aerospace Medicine     Open Access   (Followers: 1)
Open Aerospace Engineering Journal     Open Access   (Followers: 1)
Advances in Astronautics Science and Technology     Hybrid Journal   (Followers: 1)
Journal of Engineering and Technological Sciences     Open Access   (Followers: 1)
Technical Soaring     Full-text available via subscription   (Followers: 1)
Spatial Information Research     Hybrid Journal   (Followers: 1)
Mekanika : Jurnal Teknik Mesin i     Open Access   (Followers: 1)
Perspectives of Earth and Space Scientists i     Open Access  

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Similar Journals
Journal Cover
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Prestige (SJR): 0.869
Citation Impact (citeScore): 4
Number of Followers: 39  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1057-7122 - ISSN (Online) 1549-8328
Published by IEEE Homepage  [229 journals]
  • IEEE Transactions on Circuits and Systems—I:Regular Papers
           publication information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • IEEE Circuits and Systems Society Information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Jitter-Power Trade-Offs in PLLs
    • Authors: Behzad Razavi;
      Pages: 1381 - 1387
      Abstract: As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A Galvanic Isolated Amplifier Based on CMOS Integrated Hall-Effect Sensors
    • Authors: Seyed Sepehr Mirfakhraei;Yves Audet;Ahmad Hassan;Mohamad Sawan;
      Pages: 1388 - 1397
      Abstract: A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain amplifier, and anti-aliasing filter. Because of the miniaturized size of isolation components, this approach can be packaged in chip for industrial applications. This solution replaces the need of bulky/frequency dependent current transformers, complex isolation amplifiers with embedded analog to digital converters, and allows proposed sensors to be used in voltage and current sensing applications. The introduced prototype achieves an input referred offset of 1 mV, 50 dB full-scale signal-to-noise ratio in a 10 kHz bandwidth, and spurious-free dynamic range of 53 dB, while satisfying continuous isolation working voltage of 550 V.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Analysis and Design of a CMOS Bidirectional Passive Vector-Modulated Phase
           Shifter
    • Authors: Peng Gu;Dixian Zhao;Xiaohu You;
      Pages: 1398 - 1408
      Abstract: This paper presents a passive vector-modulated phase shifter (VMPS). The passive X-type attenuator consisting of digitally controlled transistor-array units is employed to perform the phase-invertible gain tuning, and thus enables phase shift in all four quadrants. The Wilkinson-like power combiner is utilized to sum up the quadrature signals and avoid impedance mismatches. Analysis proves that the proposed passive VMPS can provide consistent phase-shift performance for bidirectional operation. The proof-of-concept VMPS is implemented in 40-nm CMOS technology and occupies a core chip area of 0.15 mm2. Measured results prove that it can provide consistent bidirectional 6-bit phase-shift operation, with accurate phase tuning (i.e., RMS phase error
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A 1.25 μJ per Measurement Ultrasound Rangefinder System in 65 nm CMOS for
           Explorations With a Swarm of Sensor Nodes
    • Authors: Gönenç Berkol;Peter G. M. Baltus;Pieter J. A. Harpe;Eugenio Cantatore;
      Pages: 1409 - 1420
      Abstract: This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~mu text{J}$ and ${0.82~mu text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~mu text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~mu text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Dual Input Digitally Controlled Broadband Three-Stage Doherty Power
           Amplifier With Back-Off Reconfigurability
    • Authors: Ayushi Barthwal;Karun Rawat;Shiban K. Koul;
      Pages: 1421 - 1431
      Abstract: This article presents a design strategy to improve the bandwidth of the three-stage Doherty Power Amplifier (DPA) by controlling the phase difference between the dual RF inputs digitally. The theory also proposes multiple back-off reconfigurability without using tuning elements and extra circuitry. The proposed theory is validated by demonstration of a dual-input three-stage DPA which is designed and implemented using Wolfspeed’s GaN HEMT transistors. The measured results show a drain efficiency of 50.4 – 58% and 46.1 – 65.4% at 12 dB and 6 dB back-off respectively, over the frequency range of 550-900 MHz. Over this 350 MHz band, the drain efficiency is between 53.97% and 71.5% at saturation, corresponding to 48.3% fractional bandwidth. The measurement results also show that both the back-offs are reconfigurable by changing the drain bias of main and first auxiliary power amplifier. The modulated measurements are carried with a 10 MHz LTE signal with a PAPR of 11.75 dB. The high average efficiency of 51.6%, 54.9%, and 52.6% is reported at 600, 700, and 800 MHz, respectively, at an average power of around 30 dBm. The measurement results validate the theory proposed making the presented DPA as a potential candidate for future wireless transmitters.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A 660 MHz–5 GHz 6-Phase/3-Phase Transmitter With Cancellation of
           Counter-Intermodulation Distortion and Improved Image Rejection
    • Authors: Hong Jiang;Wael Al-Qaq;Mark Forrester;Zhihang Zhang;Timothy McHugh;Brian Iehl;Lawrence Connell;Eric Sung;Ramesh Chadalawada;Robert Irvine;
      Pages: 1432 - 1443
      Abstract: In the transmit signal path of a cellular terminal that supports the Long-Term Evolution (LTE) standard, the third-order counter-intermodulation (CIM3) product can be a significant contributor to spurious emissions in protected bands, primarily in cases where all the transmit power is concentrated in one resource block at the edge of the allocated bandwidth. This problem can be addressed with a harmonic rejection architecture for the up-conversion mixer in the transceiver. Prior work in this area retains the four-phase baseband inputs of a conventional quadrature mixer, utilizes various techniques in the local oscillator (LO) path involving overlapping LO waveforms to suppress harmonics and requires the digitally-controlled oscillator (DCO) to be operated at two or more times the LO frequency. The harmonic rejection architecture presented in this paper has six baseband phases and six non-overlapping LO phases and, for higher-frequency bands, allows the DCO to run at 1.5 times the LO frequency. It also provides an inherently higher uncalibrated image rejection than architectures with quadrature baseband inputs, which is advantageous for any wireless communication standard that supports higher-order quadrature amplitude modulation (QAM) schemes such as 1024-QAM and 4096-QAM.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A Foreground Calibration for M-Channel Time-Interleaved Analog-to-Digital
           Converters Based on Genetic Algorithm
    • Authors: Yang Azevedo Tavares;Minjae Lee;
      Pages: 1444 - 1457
      Abstract: The time-interleaved analog-to-digital converter has shown to be a key component of the latest ultra-wide band systems. Unfortunately, the sub-analog-to-digital converters are prone to parameter deviations caused by process-voltage-temperature, which can affect the output linearity. This article presents a foreground time-interleaved analog-to-digital converter mismatch calibration, which is one of the few available in the literature that can be adapted to any interleaving factor and calibrate overall frequency-dependent mismatches. Moreover, the proposed scheme is highly suited to state-of-the-art transceivers without the need for extra analog expensive circuitry or input signal purity. The foreground signal and correction structure complexity are greatly alleviated due to the developed mismatch detection and genetic algorithm logic. Numerical simulations and measurement results are presented. A commercial 3.6-GS/s time-interleaved analog-to-digital converter was utilized to verify the algorithm performance and experimental issues regarding mixed mismatches are addressed.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A Low-Profile Autonomous Interface Circuit for Piezoelectric Micro-Power
           Generators
    • Authors: Berkay Çiftci;Salar Chamanian;Aziz Koyuncuoğlu;Ali Muhtaroğlu;Haluk Külah;
      Pages: 1458 - 1471
      Abstract: This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Mode Composite Waveguide Based on Hybrid Substrate Integrated Waveguide
           and Spoof Surface Plasmon Polariton Structure
    • Authors: Zhang-Biao Yang;Dongfang Guan;Qingfeng Zhang;Hantao Xu;Mingtuan Lin;Ximeng Zhang;Rentang Hong;Shao-Wei Yong;
      Pages: 1472 - 1480
      Abstract: In this paper, a novel mode composite waveguide based on hybrid substrate integrated waveguide and spoof surface plasmon polariton (SIW-SSPP) is proposed. Through different feeding methods, the odd mode and even mode of SSPP are excited simultaneously and operate at the same frequency band. Thus, co-frequency mode multiplexing is achieved for the proposed odd-even mode composite waveguide (OEMCW). The design principle and characteristics of the OEMCW are analyzed in this work. A prototype is fabricated and measured to demonstrate its transmission performance. The measured results indicate that the proposed waveguide can operate from 10.3 GHz to 18 GHz in two modes with the isolation larger than 18 dB.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • On the Resiliency of NCFET Circuits Against Voltage Over-Scaling
    • Authors: Guilherme Paim;Georgios Zervakis;Girish Pahwa;Yogesh Singh Chauhan;Eduardo Antônio Ceśar da Costa;Sergio Bampi;Jörg Henkel;Hussam Amrouch;
      Pages: 1481 - 1492
      Abstract: Approximate computing is established as a design alternative to improve the energy requirements of a vast number of applications, leveraging their intrinsic error tolerance. Voltage over-scaling (VOS) is one of the most energy-efficient approximation techniques, but its exploitation is still limited due to the large errors it induces. In this work, we investigate, for the first time, the resiliency of negative capacitance transistor (NCFET) technology to VOS in comparison to conventional CMOS technology. Our work reveals that circuits implemented using the NCFET technology exhibit much less timing errors under VOS due to the inherent voltage amplification provided by the ferroelectric layer. NCFET is one of the very promising emerging technologies that is rapidly evolving for low-power circuit as it enables the transistors to switch faster without the need to increase the voltage. We demonstrate how NCFET technology allows circuit designers to effectively employ VOS to boost the efficiency of their approximate circuits, while still keeping the induced errors marginal. Our analysis shows that the VOS-resilience of NCFET circuits enables maximizing the voltage decrease and thus, NCFET based VOS approximate circuits achieve from $1.83times$ up to $2.78times$ higher energy reduction compared to the corresponding FinFET circuits for the same error bounds.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A High-Performance Bidirectional Architecture for the
           Quasi-Comparison-Free Sorting Algorithm
    • Authors: Wei-Ting Chen;Ren-Der Chen;Pei-Yin Chen;Yu-Che Hsiao;
      Pages: 1493 - 1506
      Abstract: This paper proposes a high-performance bidirectional architecture for the quasi-comparison-free sorting algorithm. Our architecture improves the performance of the conventional unidirectional architecture by reducing the total number of sorting cycles via bidirectional sorting along with two auxiliary methods. Bidirectional sorting allows the sorting tasks to be conducted concurrently in the high- and low-index parts of our architecture. The first auxiliary method is boundary finding, which shortens the range for index searching by finding the boundaries of the range. The second auxiliary method is queue storing, which stores each useful index in a queue in advance to reduce the number of miss cycles during index searching. The performance of our architecture highly depends on the distribution of input data. For each set of input data to be sorted, five Gaussian distributions of the input data and four standard derivations for each distribution were adopted in our experiments. The results show that at the expense of some additional area cost, the number of sorting cycles and the energy consumption are significantly reduced by our method.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Memory Access Optimization for On-Chip Transfer Learning
    • Authors: Muhammad Awais Hussain;Tsung-Han Tsai;
      Pages: 1507 - 1519
      Abstract: Training of Deep Neural Network (DNN) at the edge faces the challenge of high energy consumption due to the requirements of a large number of memory accesses for gradient calculations. Therefore, it is necessary to minimize data fetches to perform training of a DNN model on the edge. In this paper, a novel technique has been proposed to reduce the memory access for the training of fully connected layers in transfer learning. By analyzing the memory access patterns in the backpropagation phase in fully connected layers, the memory access can be optimized. We introduce a new method to update the weights by introducing the delta term for every node of output and fully connected layer. Delta term aims to reduce memory access for the parameters which are required to access repeatedly during the training process of fully connected layers. The proposed technique shows 0.13x-13.93x energy savings for the training of fully connected layers for famous DNN architectures on multiple processor architectures. The proposed technique can be used to perform transfer learning on-chip to reduce energy consumption as well as memory access.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Analysis and Optimization Strategies Toward Reliable and High-Speed 6T
           Compute SRAM
    • Authors: Jian Chen;Wenfeng Zhao;Yuqi Wang;Yajun Ha;
      Pages: 1520 - 1531
      Abstract: In-SRAM Computation improves the throughput and energy-efficiency of data-intensive applications by utilizing parallelism and reducing the data transfers. However, when multiple wordlines are accessed simultaneously, a short-circuit path will likely incur dynamic read disturbance and generate extra direct current in 6T Compute SRAM (CSRAM). In order to mitigate this issue, existing works either degrade the access speed, use area-hungry bitcells, or incur architecture-level overheads. In this paper, we first perform a comprehensive circuit-level analysis of the dynamic read disturbance issues of 6T SRAM for the first time and find that such disturbance can be efficiently avoided by maintaining the bitline voltage at a high level. Second, we propose a novel energy-efficient, reconfigurable sense amplifier design that is able to achieve fast and reliable sensing when the bitline voltage level is high for the compute access. Third, we propose an adaptive wordline control scheme that keeps the bitline voltage at a high level to eliminate the dynamic read disturbance and the sneaky direct current pathway. Both the new sense amplifier and adaptive wordline control are also optimized to support the normal read access efficiently. We have validated our design in a 55nm CMOS technology. Experimental results show that our design not only reliably addresses the read disturbance and the extra direct current, but also operates 19% faster than the state-of-the-art design using an advanced 28nm FDSOI technology.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Neural Network Training With Stochastic Hardware Models and Software
           Abstractions
    • Authors: Bonan Zhang;Lung-Yen Chen;Naveen Verma;
      Pages: 1532 - 1542
      Abstract: Machine learning inference is of broad interest, increasingly in energy-constrained applications. However, platforms are often pushed to their energy limits, especially with deep learning models, which provide state-of-the-art inference performance but are also computationally intensive. This has motivated algorithmic co-design, where flexibility in the model and model parameters, derived from training, is exploited for hardware energy efficiency. This work extends a model-training algorithm referred to as Stochastic Data-Driven Hardware Resilience (S-DDHR) to enable statistical models of computations, amenable for energy/throughput aggressive hardware operating points as well as emerging variation-prone device technologies. S-DDHR itself extends the previous approach of DDHR by incorporating the statistical distribution of hardware variations for model-parameter learning, rather than a sample of the distributions. This is critical to developing accurate and composable abstractions of computations, to enable scalable hardware-generalized training, rather than hardware instance-by-instance training. S-DDHR is demonstrated and evaluated for a bit-scalable MRAM-based in-memory computing architecture, whose energy/throughput trade-offs explicitly motivate statistical computations. Using foundry data to model MRAM device variations, S-DDHR is shown to preserve high inference performance for benchmark datasets (MNIST, CIFAR-10, SVHN) as variation parameters are scaled to high levels, exhibiting less than 3.5% accuracy drop at $10 times $ the nominal variation level.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven
           Computation Scheme and Online Learning
    • Authors: Sixu Li;Zhaomin Zhang;Ruixin Mao;Jianbiao Xiao;Liang Chang;Jun Zhou;
      Pages: 1543 - 1552
      Abstract: In the recent years, the spiking neural network (SNN) has attracted increasing attention due to its low energy consumption and online learning potential. However, the design of SNN processor has not been thoroughly investigated in the past, resulting in limited performance and energy consumption. In this work, a fast and energy-efficient SNN processor with adaptive clock/event-driven computation scheme and online learning capability has been proposed. Several techniques have been proposed to reduce the computation time and energy consumption, including Adaptive Clock- and Event-Driven Computing Scheme, Neighboring PE Borrowing Technique, Compressed Spike Routing Technique and Reconfigurable PE for Inference and Learning. Implemented on a Virtex-7 FPGA, the proposed design achieves computation time of 3.15 ms/image, inference energy consumption of $0.028~mu $ J/synapse/image and online learning energy consumption of $0.297~mu $ J/synapse/image for the MNIST 10-class dataset, which outperform several state-of-the-art SNN processors. The proposed SNN processor is suitable for real-time and energy-constrained applications.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A New Message Expansion Structure for Full Pipeline SHA-2
    • Authors: Yin Zhang;Zhangqing He;Meilin Wan;Muwen Zhan;Ming Zhang;Kuang Peng;Min Song;Haoshuang Gu;
      Pages: 1553 - 1566
      Abstract: Once there are constant or infrequently changed bits (COIBs) in two adjacent input messages of SHA-2, the switching power of input messages data registers (IMD-REGs) used for COIBs will disappear. Meanwhile, when full pipeline SHA-2 is applied in a certain application scenario where the IMD-REGs used for COIBs can be removed, more area of full pipeline SHA-2 can be saved as the proportion of IMD-REGs in message word registers increases. This paper proposes a new message expansion structure for full pipeline SHA-2 to increase the proportion of IMD-REGs. By inserting two expanders in last part of expansion structure pipeline stages and rescheduling the expander, the consumption rate of input messages will be decreased and the proportion of IMD-REGs will be increased. Compared with normal message expansion structure, the ratio of IMD-REGs to total message word registers in the proposed structure is increased from 15.1% to 41.6% for full pipeline SHA256, and 11.2% to 32.4% for full pipeline SHA512. When COIBs exists in adjacent input messages, the power and area advantages of proposed new message expansion structure have been demonstrated by FPGA and ASIC implementations.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based
           Sensitivity Analysis
    • Authors: Hyunjeong Kwon;Daeyeon Kim;Young Hwan Kim;Seokhyeong Kang;
      Pages: 1567 - 1577
      Abstract: Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters. This paper proposes a novel SRAM optimization method that uses a deep neural network (DNN). Multiple DNNs from ensemble techniques represent the mean and variance of SRAM cell stability for the nominal design parameters. Subsequent sensitivity analysis of DNN extracts the ${K}$ design parameters that have the most dominant effects on the mean and variance of SRAM cell stability. Then multidimensional optimization is used to find the optimal values of these ${K}$ parameters to maximize the mean stability while minimizing its variance. The proposed method achieved an average of 2% error compared to MC simulation. The proposed optimization method takes only 561 s to provide the most optimal design parameter values of an SRAM cell.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • An 800 nW Switched-Capacitor Feature Extraction Filterbank for Sound
           Classification
    • Authors: Daniel Augusto Villamizar;Dante Gabriel Muratore;James B. Wieser;Boris Murmann;
      Pages: 1578 - 1588
      Abstract: This paper presents a 32-channel analog filterbank for front-end signal processing in sound classification systems. It employs a passive N-path switched capacitor topology to achieve high power efficiency and reconfigurability. The circuit’s unwanted harmonic mixing products are absorbed by the machine learning model during training. To enable a systematic pre-silicon study of this effect, we develop a computationally efficient circuit model that can process large machine learning datasets on practical time scales. Measured results using a 130 nm CMOS prototype IC indicate competitive classification accuracy on datasets for baby cry detection (93.7% AUC) and voice commands (92.4% average precision), while lowering the feature extraction energy compared to digital realizations by approximately $2times $ and $10times $ , respectively. The 1.44 mm2 chip consumes 800 nW, which corresponds to the lowest normalized power per simultaneously sampled channel in recent literature.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Finite-Time Intra-Layer and Inter-Layer Quasi-Synchronization of Two-Layer
           Multi-Weighted Networks
    • Authors: Yuhua Xu;Xiaoqun Wu;Bing Mao;Jinhu Lü;Chengrong Xie;
      Pages: 1589 - 1598
      Abstract: The article pays attention to a two-layer multi-weighted network, and studies finite-time (FT) intra-/inter-layer quasi-synchronization of two-layer multi-weighted networks. Firstly, FT stability and quasi-stability theorems of dynamical system are discussed, and the results show that the maximum convergence time of FT quasi-stability is smaller than that of FT stability for the dynamic system. Secondly, novel sufficient criteria are gained for FT intra-/inter-layer quasi-synchronization of two-layer multi-weighted networks. Thirdly, the relationship among multiple weights number, the topological structure, inner coupling modes, coupling strengthes and across layers are established. In particular, the results show that the smaller multiple weights number do not necessarily lead to faster quasi-synchronization, and the multiple weights number may have a positive feedback effect on FT intra-/inter-layer quasi-synchronization. When the multiple weights number is greater than a certain value, FT intra-layer quasi-synchronization and FT inter-layer quasi-synchronization of networks can be realized simultaneously, and the conditions of taking the minimum convergence time are also given. Finally, numerical examples verify the effectiveness of the proposed method.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Novel Finite-Time Reliable Control Design for Memristor-Based Inertial
           Neural Networks With Mixed Time-Varying Delays
    • Authors: Lanfeng Hua;Hong Zhu;Kaibo Shi;Shouming Zhong;Yiqian Tang;Yajuan Liu;
      Pages: 1599 - 1609
      Abstract: The issue of finite-time stabilization (FTS) for the memristor-based inertial neural networks (MINNs) with mixed time-varying delays (MTVDs) is researched by virtue of a new analytical method in this brief. First, an appropriate reliable control strategy is proposed for MINNs, which takes the influence of actuator failures into account. Second, by combining Lyapunov functional theory with new analysis techniques, novel theoretical results to guarantee the FTS for the concerned MINNs are acquired, and the desired reliable controller gains are obtained simultaneously. In additions, compared with the previous research works, the FTS results obtained in this paper are established directly from the MINNs themselves without using variable transformation method. In the end, two simulations are exploited to show the correctness and practicability of the acquired theoretical results.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Vibration Control of Conveying Fluid Pipe Based on Inerter Enhanced
           Nonlinear Energy Sink
    • Authors: Nan Duan;Yuhu Wu;Xi-Ming Sun;Chongquan Zhong;
      Pages: 1610 - 1623
      Abstract: Many fundamental studies have indicated that the vibration of conveying fluid pipe is more severe and complex at high subcritical fluid velocity. The control of vibration in this case, however, still remains a challenge for the general vibration absorbers. In this work, the inerter enhanced nonlinear energy sink (NES) is used to solve the severe vibration problem. The partial differential equation form model of the conveying fluid pipe-inerter enhanced NES system is derived and converted to an ordinary differential equation with an easy solution. Global stability of the conveying fluid pipe-inerter enhanced NES system is proved under the Lyapunov stability theory framework and functional analysis technique, to explain the effectiveness of the inerter enhanced NES. The influence of parameters on the conveying fluid pipe is discussed through a sensitivity analysis. The parameters of the proposed controller are optimized based on the energy functional. Finally, numerical examples are provided to verify the control effectiveness and the theoretical results, and also to show the advantages of inerter enhanced NES by comparing with the general NES.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Re-Assessment of Steep-Slope Device Design From a Circuit-Level
           Perspective Using Novel Evaluation Criteria and Model-Less Method
    • Authors: Zhixuan Wang;Le Ye;Qianqian Huang;Yangyuan Wang;Ru Huang;
      Pages: 1624 - 1635
      Abstract: Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ( $SS_{avg}$ ), off current ( ${I} _{OFF}$ ), and on current ( ${I} _{ON}$ ) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Resonant Clock Synchronization With Active Silicon Interposer for
           Multi-Die Systems
    • Authors: Ragh Kuttappa;Baris Taskin;Scott Lerner;Vasil Pano;
      Pages: 1636 - 1645
      Abstract: This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Distributed Fault-Tolerant Consensus Tracking Control of Multi-Agent
           Systems Under Fixed and Switching Topologies
    • Authors: Chun Liu;Bin Jiang;Ke Zhang;Ron J. Patton;
      Pages: 1646 - 1658
      Abstract: This paper proposes a novel distributed fault-tolerant consensus tracking control design for multi-agent systems with abrupt and incipient actuator faults under fixed and switching topologies. The fault and state information of each individual agent is estimated by merging unknown input observer in the decentralized fault estimation hierarchy. Then, two kinds of distributed fault-tolerant consensus tracking control schemes with average dwelling time technique are developed to guarantee the mean-square exponential consensus convergence of multi-agent systems, respectively, on the basis of the relative neighboring output information as well as the estimated information in fault estimation. Simulation results demonstrate the effectiveness of the proposed fault-tolerant consensus tracking control algorithm.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Distributed Observer-Based H ∞ Fault-Tolerant Control for DC Microgrids
           With Sensor Fault
    • Authors: Mingyu Huang;Li Ding;Wenqu Li;Chao-Yang Chen;Zhiwei Liu;
      Pages: 1659 - 1670
      Abstract: Disturbances, uncertainties, noises and device faults commonly exist in microgrids and often undermine the system stability. To meet these challenges, robust control methods have been recently employed in microgrids systems. In this paper, an active fault-tolerant control scheme is proposed for DC islanded microgrids subjected to sensor fault and external disturbance. Firstly, a distributed ${H_infty }$ observer is designed to estimate the uncorrupted voltage and current with high accuracy. Then, an observer based state feedback controller is proposed to ensure stability of voltage regulation for the system. A consensus based control layer in the secondary level is provided to realize current sharing. For the plug-and-play operation of DC microgrids, decentralized parameters design approaches for the observer and controller are both discussed. Finally, simulation studies and experiments are carried out on a DC microgrid system to evaluate the effectiveness of the proposed fault-tolerant control scheme. The simulation and experiment results show that compared with previous works, the proposed observer based control strategy can significantly improve the reliability and resilience of DC microgrid systems.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • LMI-Based Robust Stability Analysis of Discrete-Time Fractional-Order
           Systems With Interval Uncertainties
    • Authors: Zhen Zhu;Jun-Guo Lu;
      Pages: 1671 - 1680
      Abstract: Robust stability problem of discrete-time fractional-order systems (DTFOSs) with interval uncertainties is investigated in this paper. Firstly, a new theorem for matrix root-clustering in union-region is established. Based on this theorem, the stability regions of DTFOSs are described as the union-region of closed sub-regions, and sufficient conditions for stability of DTFOSs are presented. Then, new sufficient conditions for robust stability of DTFOSs with interval uncertainties are derived. All the results are obtained in terms of linear matrix inequalities (LMIs) which are more tractable than the existing ones. Finally, numerical examples are given to show that our results are valid and less conservative than the existing ones.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Asymptotic Waveform Evaluation With Higher Order Poles
    • Authors: Yao-Lin Jiang;Jun-Man Yang;
      Pages: 1681 - 1692
      Abstract: The research generalizes the traditional asymptotic waveform evaluation method only with first order poles to the method with higher order poles case. We discuss the invertibility of the induced generalized Vandermonde matrix with the determinant formula of the matrix. Via establishing the equivalence of the multiplicity of the poles and the coefficients of the introduced matrix, the generalized asymptotic waveform evaluation algorithm is built. Then the real system realization of the lower order poles-residues form is asserted. At last two experiments are provided to check the validity of our algorithm.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Delay-Dependent Stability Analysis of Modern Shipboard Microgrids
    • Authors: Burak Yildirim;Meysam Gheisarnejad;Mohammad Hassan Khooban;
      Pages: 1693 - 1705
      Abstract: This study proposes a new application for delay-dependent stability analysis of a shipboard microgrid system. Gain and phase margin values are taken into consideration in delay dependent stability analysis. Since such systems are prone to unwanted frequency oscillations against load disturbances and randomness of renewable resources, a virtual gain and phase margin tester has been incorporated into the system to achieve the desired stabilization specification. In this way, it is considered that the system provides the desired dynamic characteristics (e.g. less oscillation, early damping, etc.) in determining the time delay margin. Firstly, the time delay margin values are obtained and their accuracy in the terms of desired gain and phase margin values are investigated. Then, the accuracy of the time delay margin values obtained by using the real data of renewable energy sources and loads in the shipboard microgrid system is shown in the study. Finally, a real-time hardware-in-the-loop (HIL) simulation based on OPAL-RT is accomplished to affirm the applicability of the suggested method, from a systemic perspective, for the load frequency control problem in the shipboard microgrid.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • A Mixed-Pruning Based Framework for Embedded Convolutional Neural Network
           Acceleration
    • Authors: Xuepeng Chang;Huihui Pan;Weiyang Lin;Huijun Gao;
      Pages: 1706 - 1715
      Abstract: Convolutional neural networks (CNN) have been proved to be an effective method in the field of artificial intelligence (AI), and large-scale deploying CNN to embedded devices, no doubt, will greatly promote the development and application of AI into the practical industry. However, mainly due to the space-time complexity of CNN, computing power, memory bandwidth and flexibility are performance bottlenecks. In this paper, a framework containing model compression and hardware acceleration is proposed to solve the above problems. This framework consists of a mixed pruning method, data storage optimization for efficient memory utilization and an accelerator for mapping CNN on field programmable gate array (FPGA). The mixed pruning method is used to compress the model, and data bit-width is reduced to 8-bit by data quantization. Accelerator based on FPGA makes it flexible, configurable and efficient for CNN implementation. The model compression is evaluated on NVIDIA RTX2080Ti, and the results illustrate that the VGG16 is compressed by $30times $ and the fully convolutional network (FCN) is compressed by $11times $ within 1% accuracy loss. The compressed model is deployed and accelerated on ZCU102, which is up to $1.7times $ and $24.5times $ better in energy efficiency compared with RTX2080Ti and Intel i7 7700.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Adaptive Practical Fixed-Time Tracking Control With Prescribed Boundary
           Constraints
    • Authors: Ming Chen;Huanqing Wang;Xiaoping Liu;
      Pages: 1716 - 1726
      Abstract: The article investigates an adaptive practical fixed-time tracking control of nonlinear systems with prescribed boundary constraints. The main control objective is that the system output variable tracks the desired signal at fixed time, and the tracking error can also converge to the prescribed boundary constraints. Primarily, a new coordinate transformation is introduced, which will be utilized in the proposed controller. Next, based on the backstepping scheme, the sufficient conditions for the existence of the adaptive practical fixed-time tracking controller are presented. Meanwhile, the fuzzy logic systems are employed to approximate to unknown parts in the controlled system. Theoretical analysis shows that the tracking error converges to the prescribed boundary constraints at fixed time. At the same time, all the signals in the closed-loop controlled system are bounded and the controlled system is practically fixed-time stable. At last, simulation results verify the effectiveness of the proposed scheme by comparing the cases with/wihtout prescribed boundary constraints.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Fast Beam Training With True-Time-Delay Arrays in Wideband Millimeter-Wave
           Systems
    • Authors: Veljko Boljanovic;Han Yan;Chung-Ching Lin;Soumen Mohapatra;Deukhyoun Heo;Subhanshu Gupta;Danijela Cabric;
      Pages: 1727 - 1739
      Abstract: The best beam steering directions are estimated through beam training, which is one of the most important and challenging tasks in millimeter-wave and sub-terahertz communications. Novel array architectures and signal processing techniques are required to avoid prohibitive beam training overhead associated with large antenna arrays and narrow beams. In this work, we leverage recent developments in true-time-delay (TTD) arrays with large delay-bandwidth products to accelerate beam training using frequency-dependent probing beams. We propose and study two TTD architecture candidates, including analog and hybrid analog-digital arrays, that can facilitate beam training with only one wideband pilot. We also propose a suitable algorithm that requires a single pilot to achieve high-accuracy estimation of angle of arrival. The proposed array architectures are compared in terms of beam training requirements and performance, robustness to practical hardware impairments, and power consumption. The findings suggest that the analog and hybrid TTD arrays achieve a sub-degree beam alignment precision with 66% and 25% lower power consumption than a fully digital array, respectively. Our results yield important design trade-offs among the basic system parameters, power consumption, and accuracy of angle of arrival estimation in fast TTD beam training.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Walsh-Hadamard-Based Orthogonal Sampling Technique for Parallel Neural
           Recording Systems
    • Authors: Reza Ranjandish;Alexandre Schmid;
      Pages: 1740 - 1749
      Abstract: Walsh-Hadamard based orthogonal sampling of signals is studied in this paper, and an application of this technique is presented. Using orthogonal sampling, a single analog-to-digital converter (ADC) only is sufficient to perform parallel (simultaneous) recording from the sensors. Furthermore, employing Walsh functions as modulation signals, the required bandwidth of the ADC in the proposed system is equal to the bandwidth of a time-multiplexed ADC in a system with identical number of recording channels. Therefore, the bandwidth of the ADC in the proposed system is effectively employed and shared among all the channels. The efficient usage of the ADC bandwidth leads to saving power at the ADC stage and reducing the data-rate of the output signal compared to state-of-the-art recording systems based on frequency-division multiplexing. This paper presents the orthogonal sampling technique for neural recording in multi-channel recording systems which is implemented with four recording channels using a $0.18~mu text{m}$ technology which results in a power consumption of $1.26~mu text{W}$ /channel at a 0.8 V supply.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Output Series-Parallel Connection of Passivity-Based Controlled DC–DC
           Converters: Generalization of Asymptotic Stability
    • Authors: Yuma Murakawa;Takashi Hikihara;
      Pages: 1750 - 1759
      Abstract: The series-paralleling technique of dc-dc converters is utilized in various domains of electrical engineering for improved power conversion. Previous studies have proposed and classified the control schemes for the series-paralleled converters. However, they have several restrictions and lack diversity. The purpose of this paper is to propose passivity-based control (PBC) for the diverse output series-parallel connection of dc-dc converters. It is proved that the output series-paralleled converters regulated by PBC are asymptotically stable. The output series-paralleled converters are numerically simulated to confirm the asymptotic stability. PBC is shown to maintain the stability of the output series-paralleled converters with diverse circuit topologies, parameters, and steady-states. The result of this paper theoretically supports the numerical and experimental considerations in the previous studies and justifies the further extension of the series-parallel connection.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Control of a Buck DC/DC Converter Using Approximate Dynamic Programming
           and Artificial Neural Networks
    • Authors: Weizhen Dong;Shuhui Li;Xingang Fu;Zhongwen Li;Michael Fairbank;Yixiang Gao;
      Pages: 1760 - 1768
      Abstract: This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Special Issue for 50 th B irthday of Memristor:
    • Pages: 1769 - 1769
      Abstract: Advertisement.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • Enhanced Systems and Circuits for Network 2030 Beyond 5G
    • Pages: 1770 - 1770
      Abstract: Advertisement.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • TechRxiv: Share Your Preprint Research with the World!
    • Pages: 1771 - 1771
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
  • IEEE Transactions on Circuits and Systems—I:Regular Papers
           information for authors
    • Pages: 1772 - 1772
      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: April 2021
      Issue No: Vol. 68, No. 4 (2021)
       
 
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