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  Subjects -> AERONAUTICS AND SPACE FLIGHT (Total: 123 journals)
Showing 1 - 30 of 30 Journals sorted alphabetically
Acta Astronautica     Hybrid Journal   (Followers: 496)
Advances in Aerospace Engineering     Open Access   (Followers: 70)
Advances in Aerospace Science and Technology     Open Access   (Followers: 8)
Advances in Astronautics Science and Technology     Hybrid Journal   (Followers: 1)
Advances in Space Research     Full-text available via subscription   (Followers: 458)
Aeronautical Journal, The     Hybrid Journal   (Followers: 13)
Aerospace     Open Access   (Followers: 60)
Aerospace Medicine and Human Performance     Full-text available via subscription   (Followers: 19)
Aerospace Science and Technology     Hybrid Journal   (Followers: 430)
Aerospace Scientific Journal     Open Access   (Followers: 18)
Aerospace Systems     Hybrid Journal   (Followers: 6)
Aerospace technic and technology     Open Access   (Followers: 3)
Aerotecnica Missili & Spazio : Journal of Aerospace Science, Technologies & Systems     Hybrid Journal   (Followers: 4)
AIAA Journal     Hybrid Journal   (Followers: 1196)
Air Force Magazine     Full-text available via subscription   (Followers: 10)
Air Medical Journal     Hybrid Journal   (Followers: 8)
Aircraft Engineering and Aerospace Technology     Hybrid Journal   (Followers: 264)
Annual of Navigation     Open Access   (Followers: 22)
Artificial Satellites     Open Access   (Followers: 23)
ASTRA Proceedings     Open Access   (Followers: 3)
Astrodynamics     Hybrid Journal   (Followers: 4)
Aviation     Open Access   (Followers: 17)
Aviation Advances & Maintenance     Open Access   (Followers: 5)
Aviation in Focus - Journal of Aeronautical Sciences     Open Access   (Followers: 10)
Aviation Psychology and Applied Human Factors     Hybrid Journal   (Followers: 27)
Aviation Week     Full-text available via subscription   (Followers: 438)
Canadian Aeronautics and Space Journal     Full-text available via subscription   (Followers: 34)
CEAS Aeronautical Journal     Hybrid Journal   (Followers: 30)
Chinese Journal of Aeronautics     Open Access   (Followers: 21)
Ciencia y Poder Aéreo     Open Access   (Followers: 2)
Civil Aviation High Technologies     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 315)
Cosmic Research     Hybrid Journal   (Followers: 5)
COSPAR Colloquia Series     Full-text available via subscription   (Followers: 11)
Egyptian Journal of Remote Sensing and Space Science     Open Access   (Followers: 24)
Elsevier Astrodynamics Series     Full-text available via subscription   (Followers: 12)
Fatigue of Aircraft Structures     Open Access   (Followers: 15)
Frontiers in Astronomy and Space Sciences     Open Access   (Followers: 12)
Gravitational and Space Research     Open Access  
Gyroscopy and Navigation     Hybrid Journal   (Followers: 260)
IEEE Aerospace and Electronic Systems Magazine     Full-text available via subscription   (Followers: 279)
IEEE Journal on Miniaturization for Air and Space Systems     Hybrid Journal   (Followers: 2)
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 385)
IEEE Transactions on Circuits and Systems I: Regular Papers     Hybrid Journal   (Followers: 39)
International Journal of Aeroacoustics     Hybrid Journal   (Followers: 41)
International Journal of Aerodynamics     Hybrid Journal   (Followers: 37)
International Journal of Aeronautical and Space Sciences     Hybrid Journal   (Followers: 2)
International Journal of Aerospace Engineering     Open Access   (Followers: 82)
International Journal of Aerospace Psychology     Hybrid Journal   (Followers: 23)
International Journal of Aerospace Sciences     Open Access   (Followers: 32)
International Journal of Applied Geospatial Research     Hybrid Journal   (Followers: 7)
International Journal of Aviation Management     Hybrid Journal   (Followers: 9)
International Journal of Aviation Technology, Engineering and Management     Full-text available via subscription   (Followers: 7)
International Journal of Aviation, Aeronautics, and Aerospace     Open Access   (Followers: 5)
International Journal of Crashworthiness     Hybrid Journal   (Followers: 12)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 11)
International Journal of Satellite Communications Policy and Management     Hybrid Journal   (Followers: 13)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 11)
International Journal of Space Structures     Full-text available via subscription   (Followers: 17)
International Journal of Space Technology Management and Innovation     Full-text available via subscription   (Followers: 10)
International Journal of Sustainable Aviation     Hybrid Journal   (Followers: 5)
International Journal of Turbo and Jet-Engines     Hybrid Journal   (Followers: 6)
Investigación Pecuaria     Open Access   (Followers: 3)
Journal of Aerodynamics     Open Access   (Followers: 18)
Journal of Aeronautical Materials     Open Access   (Followers: 9)
Journal of Aeronautics & Aerospace Engineering     Open Access   (Followers: 31)
Journal of Aerospace Engineering     Full-text available via subscription   (Followers: 69)
Journal of Aerospace Engineering & Technology     Full-text available via subscription   (Followers: 18)
Journal of Aerospace Information Systems     Hybrid Journal   (Followers: 22)
Journal of Aerospace Information Systems     Hybrid Journal   (Followers: 34)
Journal of Aerospace Technology and Management     Open Access   (Followers: 7)
Journal of Aircraft     Hybrid Journal   (Followers: 337)
Journal of Aircraft and Spacecraft Technology     Open Access   (Followers: 9)
Journal of Airline and Airport Management     Open Access   (Followers: 12)
Journal of Astrobiology & Outreach     Open Access   (Followers: 3)
Journal of Aviation Technology and Engineering     Open Access   (Followers: 11)
Journal of Aviation/Aerospace Education & Research     Open Access   (Followers: 2)
Journal of Engineering and Technological Sciences     Open Access   (Followers: 1)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 205)
Journal of KONBiN     Open Access   (Followers: 3)
Journal of Navigation     Hybrid Journal   (Followers: 280)
Journal of Propulsion and Power     Hybrid Journal   (Followers: 615)
Journal of Space Safety Engineering     Hybrid Journal   (Followers: 8)
Journal of Space Weather and Space Climate     Open Access   (Followers: 27)
Journal of Spacecraft and Rockets     Hybrid Journal   (Followers: 773)
Journal of Spatial Science     Hybrid Journal   (Followers: 3)
Journal of the American Helicopter Society     Full-text available via subscription   (Followers: 8)
Journal of the Astronautical Sciences     Hybrid Journal   (Followers: 9)
Journal of the Australasian Society of Aerospace Medicine     Open Access   (Followers: 1)
Journal of Wind Engineering and Industrial Aerodynamics     Hybrid Journal   (Followers: 17)
Life Sciences in Space Research     Hybrid Journal   (Followers: 4)
MAD - Magazine of Aviation Development     Open Access   (Followers: 2)
Mekanika : Jurnal Teknik Mesin i     Open Access   (Followers: 1)
Microgravity Science and Technology     Hybrid Journal   (Followers: 2)
New Space     Hybrid Journal   (Followers: 6)
Nonlinear Dynamics     Hybrid Journal   (Followers: 20)
npj Microgravity     Open Access   (Followers: 3)
Open Aerospace Engineering Journal     Open Access   (Followers: 1)
Perspectives of Earth and Space Scientists i     Open Access  
Population Space and Place     Hybrid Journal   (Followers: 9)
Problemy Mechatroniki. Uzbrojenie, lotnictwo, inżynieria bezpieczeństwa / Problems of Mechatronics. Armament, Aviation, Safety Engineering     Open Access   (Followers: 3)
Proceedings of the Human Factors and Ergonomics Society Annual Meeting     Hybrid Journal   (Followers: 16)
Proceedings of the Institution of Mechanical Engineers Part G: Journal of Aerospace Engineering     Hybrid Journal   (Followers: 46)
Progress in Aerospace Sciences     Full-text available via subscription   (Followers: 81)
Propulsion and Power Research     Open Access   (Followers: 68)
REACH - Reviews in Human Space Exploration     Full-text available via subscription   (Followers: 5)
Research & Reviews : Journal of Space Science & Technology     Full-text available via subscription   (Followers: 17)
RocketSTEM     Free   (Followers: 6)
Russian Aeronautics (Iz VUZ)     Hybrid Journal   (Followers: 24)
Science and Education : Scientific Publication of BMSTU     Open Access   (Followers: 1)
Space and Polity     Hybrid Journal   (Followers: 4)
Space Policy     Hybrid Journal   (Followers: 29)
Space Research Today     Full-text available via subscription   (Followers: 48)
Space Safety Magazine     Free   (Followers: 51)
Space Science International     Open Access   (Followers: 202)
Space Science Reviews     Hybrid Journal   (Followers: 97)
SpaceNews     Free   (Followers: 825)
Spatial Information Research     Hybrid Journal   (Followers: 1)
Technical Soaring     Full-text available via subscription   (Followers: 1)
Transport and Aerospace Engineering     Open Access   (Followers: 1)
Transportmetrica A : Transport Science     Hybrid Journal   (Followers: 9)
Unmanned Systems     Hybrid Journal   (Followers: 5)
Вісник Національного Авіаційного Університету     Open Access   (Followers: 2)

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Similar Journals
Journal Cover
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Prestige (SJR): 0.869
Citation Impact (citeScore): 4
Number of Followers: 39  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1057-7122 - ISSN (Online) 1549-8328
Published by IEEE Homepage  [229 journals]
  • IEEE Transactions on Circuits and Systems—I:Regular Papers
           publication information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • IEEE Circuits and Systems Society Information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge
           Devices
    • Authors: Chuan-Jia Jhang;Cheng-Xin Xue;Je-Min Hung;Fu-Chun Chang;Meng-Fan Chang;
      Pages: 1773 - 1786
      Abstract: When applied to artificial intelligence edge devices, the conventionally von Neumann computing architecture imposes numerous challenges (e.g., improving the energy efficiency), due to the memory-wall bottleneck involving the frequent movement of data between the memory and the processing elements (PE). Computing-in-memory (CIM) is a promising candidate approach to breaking through this so-called memory wall bottleneck. SRAM cells provide unlimited endurance and compatibility with state-of-the-art logic processes. This paper outlines the background, trends, and challenges involved in the further development of SRAM-CIM macros. This paper also reviews recent silicon-verified SRAM-CIM macros designed for logic and multiplication-accumulation (MAC) operations.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Guest Editorial Special Issue on the IEEE Latin American Symposium on
           Circuits and Systems 2020
    • Authors: Elena Blokhina;
      Pages: 1787 - 1788
      Abstract: This Special Issue is a collection of selected papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2020 that was held in San José, Costa Rica, on February 25–28, 2020. As the flagship conference of the IEEE Circuits and Systems Society (CASS) in IEEE Region 9, this conference welcomes contributions across the themes within the scope of the society, including analog, digital, and mixed-signal electronics, signal processing, power electronics, communication theory, sensors, circuit theory, and nonlinear circuits and systems.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • An Optimized Radiation Tolerant Baseline Correction Filter for HEP Using
           AI Methodologies
    • Authors: Bruno Sanches;Wilhelmus Van Noije;
      Pages: 1789 - 1799
      Abstract: This paper presents an improved baseline correction filter to be used in the readout front-end ASICs of gaseous detector systems in high energy physics experiments. The digital filter is based on an FIR section and used in the data pipeline running in real-time thought the input signals, allowing adequate data compression by the subsequent blocks in the processing chain. The proposed design was optimized to cope with the power and area trade-offs while hardening the block using redundancy and a novel automated design system based on artificial intelligence. This optimizer is also discussed including its logic and improvements using genetic algorithms with dynamic mutation and cross-over probabilities connected to run-time EDA tools. The designed filter was fabricated in 130 nm process, packaged and tested in the Peletron particle accelerator at the University of Sao Paulo. The device was irradiated and received a total dose of 70 krad during about one week of exposition to alpha particles without any measured failure, validating the design and solving the vulnerability with a small increase in the channel area of just 0.07%.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Analysis and Design of a Broadband Output Stage With Current-Reuse and a
           Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs
    • Authors: Daniel Schrögendorfer;Thomas Leitner;
      Pages: 1800 - 1813
      Abstract: This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant $beta $ to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm2 and 0.11mm2, respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI
           Hardware for Energy-Efficient ECG Signal Processing
    • Authors: Henrique Bestani Seidel;Morgana Macedo Azevedo da Rosa;Guilherme Paim;Eduardo Antônio César da Costa;Sérgio J. M. Almeida;Sergio Bampi;
      Pages: 1814 - 1826
      Abstract: The approximate computing paradigm emerged as a key alternative for trading off accuracy and energy efficiency. Error-tolerant applications, such as multimedia and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level. The automatic detection of R-peaks in an electrocardiogram (ECG) signal is the essential step preceding ECG processing and analysis. The Haar discrete wavelet transform (HDWT) is a low-complexity pre-processing filter suitable to detect ECG R-peaks in embedded systems like wearable devices, which are incredibly energy-constrained. This work presents an approximate HDWT hardware architecture for ECG processing at very high energy efficiency. Our best-proposal employing pruning within the approximate HDWT hardware architecture requires just seven additions. The use of a truncation technique to improve energy efficiency is also investigated herein by observing the evolution of the signal-to-noise ratio and the ultimate impact in the ECG peak-detection application. This research finds that our HDWT approximate hardware architecture proposal accepts higher truncation levels than the original HDWT. In summary: Our results show about 9 times energy reduction when combining our HDWT matrix approximation proposal with the pruning and the highest acceptable level of truncation while still maintaining the R-peak detection performance accuracy of 99.68% on average.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Signal and Noise Analysis of an Open-Circuit Voltage Pixel for Uncooled
           Infrared Image Sensors
    • Authors: Roman Fragasse;Ramy Tantawy;Dale Smith;Teressa Specht;Zahra Taghipour;Phillip V. Hooser;Chris Taylor;Theodore J. Ronningen;Earl Fuller;Charles Reyner;Josh Duran;Gamini Ariyawansa;Sanjay Krishna;Waleed Khalil;
      Pages: 1827 - 1840
      Abstract: An imaging pixel unit-cell topology leveraging a photodetector in the forward-bias region is proposed. Connecting the anode of the photodiode to the gate of a NMOS device operating in the subthreshold region provides the basis for a new open-circuit voltage pixel (VocP) architecture. Theoretical analysis is presented to show the response and performance benefits of the VocP in comparison to a conventional pixel. Based on this analysis, the signal and noise relationships for both pixels are derived and leveraged to construct an end-to-end readout system model. The model results highlight potential performance benefits of the VocP over a conventional direct-injection pixel topology. To verify the analysis, the proposed VocP readout architecture is fabricated along with a conventional direct-injection pixel readout in a $0.18~mathrm {mu }text{m}$ CMOS technology. The VocP performance is compared to a traditional reverse-bias current-mode photodetector configuration. Simulation, modeling, and measurements align with the proposed analytical model. Benefits in system sensitivity and dynamic range are demonstrated showing more than a $2times $ improvement in noise-equivalent temperature difference and a 4 dB improvement in dynamic range.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Synthesis of High-Order Continuously Tunable Low-Pass Active-R Filters
    • Authors: Adriana C. Sanabria-Borbón;Edgar Sánchez-Sinencio;
      Pages: 1841 - 1854
      Abstract: This work discusses the synthesis and design methodology of high-order and frequency-tunable low-pass active-R filter architectures for multi-standard wireless applications. Active-R filters use the inherent integrator-like behavior of amplifiers to realize their frequency response. The main advantages of this type of filter are high-frequency performance and a low integrated area. Active-R filters only need the Miller capacitor used in internally compensated amplifiers. In this work, amplifiers with configurable unity-gain frequencies enable the continuous tuning of active-R filters. Three different filter architectures realize a fifth-order Butterworth prototype tunable in the 1–50 MHz frequency range. These filters are designed, fabricated, and tested using the TSMC 0.18 ${mu }text{m}$ process. Each fifth-order filter consumes power in the range 7.45 mW to 9.38 mW from a 1.8 V supply and has an integrated area ${leq }~0.33$ mm2. Compared with state-of-the-art active filters, the filters presented in this work have the largest tuning range without linearity degradation and the smallest area per tuning range ratio. Also, the measured filters show a competitive FoM 153.3 dB/J when operating at high frequencies.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS
    • Authors: Feifei Zhang;Peng Chen;Jeffrey S. Walling;Anding Zhu;Robert Bogdan Staszewski;
      Pages: 1855 - 1868
      Abstract: This paper demonstrates a wideband 2.4 GHz $2times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An $8times $ analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • A Ku-Band CMOS Power Amplifier With Series-Shunt LC Notch Filter for
           Satellite Communications
    • Authors: Jiecheng Zhong;Dixian Zhao;Xiaohu You;
      Pages: 1869 - 1880
      Abstract: This article presents a $Ku$ -band power amplifier with a series-shunt $LC$ notch filter in 65-nm CMOS. The notch filter is integrated into the inter-stage matching network to attenuate the receiver-band noise, thereby reducing transmitter-to-receiver interference. A comprehensive analysis of the series and the shunt notch filters, as well as the position to apply the notch filter is discussed. Besides, a systematic method of optimizing passive devices in the notch filter is proposed to further improve network $Q$ and minimize the influence on the power amplifier. Fabricated in 65-nm CMOS technology, the power amplifier prototype delivers a measured gain of 21.9 dB with 3-dB bandwidth from 13.7 GHz to 16.7 GHz at the nominal state. At 14.2 GHz, it can offer a saturated output power of 14.5 dBm with peak power added efficiency of 24.1%. The notch frequency is adjustable from 10.3 to 11.9 GHz to offer the best attenuation at the receiver band. From 10 to 12 GHz, a maximal attenuation of 30 dB is achieved. The design occupies a core area of $0.35times 0.85$ mm2.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS
    • Authors: Chao-Chieh Li;Min-Shueh Yuan;Chia-Chun Liao;Chih-Hsien Chang;Yu-Tso Lin;Tsung-Hsien Tsai;Tien-Chien Huang;Hsien-Yuan Liao;Chung-Ting Lu;Hung-Yi Kuo;Augusto Ronchini Ximenes;Robert Bogdan Staszewski;
      Pages: 1881 - 1891
      Abstract: In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL’s phase detector (2.7–4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of −232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of −247dB, and normalized TR and area (FOMTA) of −262dB.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • NS-FDN: Near-Sensor Processing Architecture of Feature-Configurable
           Distributed Network for Beyond-Real-Time Always-on Keyword Spotting
    • Authors: Qin Li;Changlu Liu;Peiyan Dong;Yanming Zhang;Tong Li;Sheng Lin;Minda Yang;Fei Qiao;Yanzhi Wang;Li Luo;Huazhong Yang;
      Pages: 1892 - 1905
      Abstract: Always-on keyword spotting (KWS) that detects wake-up words has been the indispensable module in the voice interaction system. However, the ultra-low-power embedded devices put forward strict requirements on energy consumption, latency, and recognition accuracy of KWS. In this work, we propose a near-sensor processing architecture of feature-configurable distributed network (NS-FDN) for always-on KWS applications. The proposed distributed network adapts to the flexible keywords demands in the actual scene by splitting the conventional single network into distributed sub-networks. We design a channel-independent training framework to improve the recognition accuracy of distributed networks. The speech features are evaluated and the redundancy is reduced in NS-FDN, which can also configure the speech features to further reduce the computing complexity and improve processing speed. For deeper optimization, we implement a 65nm-process prototype chip with near-sensor mixed-signal processing architecture avoiding energy-consuming analog-to-digital converter. By improving the system, algorithm, and hardware designs of the KWS, our co-optimized architecture eliminates the energy consumption bottleneck long-standing in conventional KWS systems and achieves state-of-the-art system performance. The experiment results show that NS-FDN achieves 31.6% energy consumption savings, 1.6 times memory savings, 57 times speedup, and 3.4% higher recognition accuracy compared with the state of the art.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Circuit Modeling for RRAM-Based Neuromorphic Chip Crossbar Array With and
           Without Write-Verify Scheme
    • Authors: Tuomin Tao;Hanzhi Ma;Quankun Chen;Zhe-Ming Gu;Hang Jin;Manareldeen Ahmed;Shurun Tan;Aili Wang;En-Xiao Liu;Er-Ping Li;
      Pages: 1906 - 1916
      Abstract: This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying MNIST handwritten digits and both achieve a good recognition accuracy of more than 96%. The parasitic model of the unit cell of interconnects is constructed by the domain decomposition method (DDM) and the partial equivalent element circuit (PEEC) method, which is suitable to build up a crossbar array of any size. The impact of parasitic effects of interconnects on the recognition accuracy with and without write-verify scheme is analyzed and compared. The weights trained with write-verify scheme show better robustness to parasitic noises but training with write-verify scheme spends a longer time processing the same amount of data.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for
           Memristor-Based CIM Architectures
    • Authors: Abhairaj Singh;Muath Abu Lebdeh;Anteneh Gebregiorgis;Rajendra Bishnoi;Rajiv V. Joshi;Said Hamdioui;
      Pages: 1917 - 1930
      Abstract: Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Impact of Analog Non-Idealities on the Design Space of 6T-SRAM
           Current-Domain Dot-Product Operators for In-Memory Computing
    • Authors: Adrian Kneip;David Bol;
      Pages: 1931 - 1944
      Abstract: In-memory computing provides unprecedented power and area efficiency for the execution of convolutional neural networks by using memory bitcells to perform dot-product (DP) operations in the analog domain. Yet, these operators suffer from analog non-idealities (ANIs) that degrade the inference accuracy. This paper proposes design guidelines inferred from a holistic simulation-based analysis of the impact of ANIs on the accuracy-efficiency trade-off that affects current-domain DP operators based on conventional 6T-SRAM bitcell arrays. We define a custom SNR metric aware of the DP operand distribution to quantify decision errors associated with various ANIs, over ranges of input/output resolution and hardware design parameters. We find out that non-linearity and local mismatch are the dominant ANIs limiting the design space, while IR drops turn out to be critical only when targeting high parallelism. We then quantify the accuracy-efficiency trade-off related to these dominant ANIs across the design space and propose optimal design choices. We notably identify that using larger operators can either improve or worsen the SNR depending on the target output resolution. Furthermore, we show that hardware calibration techniques which mitigate mismatch help to recover a fraction of the lost SNR, with greater effectiveness when scaling down the supply voltage.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Analysis and Design of Lossy Capacitive Over-Neutralization Technique for
           Amplifiers Operating Near f MAX
    • Authors: Dragan Simic;Patrick Reynaert;
      Pages: 1945 - 1955
      Abstract: This paper proposes a technique to enhance the maximum achievable power gain ( $G_{MAX}$ ) of the two-port active network (2PAN) in the near- $f_{MAX}$ region. This technique is based on using the optimized passive-linear-lossy-reciprocal (PLLR) embedding to increase the unilateral power gain ( $U$ ) of the 2PAN and accordingly the $G_{MAX}$ . Due to the possibility to increase $U$ , it shows the potential to improve the conventional gain-boosting approach which relies on the passive-linear-lossless-reciprocal (PLLLR) embedding and keeps the $U$ constant. The concept itself is demonstrated on pseudo-differential NMOS pair using lossy capacitive feedback as the PLLR. This structure can serve as a basis for further gain optimization by implementing additional PLLLR embedding on top of it. Finally, by using the mentioned technique, a 190GHz amplifier is implemented in 28nm bulk CMOS technology, achieving 14.3dB of gain with 1.5dBm of $P_{SAT}$ and 2.6% of maximum PAE.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • A 7.8–13.6 pJ/b Ultra-Low Latency and Reconfigurable Neural
           Network-Assisted Polar Decoder With Multi-Code Length Support
    • Authors: Chieh-Fang Teng;An-Yeu Wu;
      Pages: 1956 - 1965
      Abstract: Polar codes have been officially selected as the channel coding in 5G standard. To meet the requirements of enhanced mobile broadband (eMBB), most published polar decoder chips aim to improve throughput rate and error-correction performance. However, to meet with the requirements of another two 5G new radio (NR) application scenarios, ultra-reliable low-latency communications (URLLC), and massive machine-type communications (mMTC), the design features of low latency and energy efficiency are also desirable. In this article, we present a 7.8-13.6 pJ/b ultra-low latency and energy-efficient polar decoder fabricated in 40nm CMOS technology. By adopting the decoding algorithm of recurrent neural network-assisted belief propagation (RNN-BP), the learned scaling parameters can improve the convergence rate by 8 times with reasonable hardware and memory overhead. Then, by taking advantage of BP’s regular structure, we propose a fully-reconfigurable RNN-BP decoder architecture to support multiple code lengths with negligible hardware complexity. It contributes to 2- $8times $ improved hardware utilization rate while providing a flexible adjustment between throughput and error-correction performance. At the architectural level, two optimization techniques for the design of the processing element (PE) are proposed to jointly reduce the chip’s area and power by 73% and 67%, respectively. From the measurement results, our reconfigurable RNN-BP polar decoder chip has $2.3times $ , $2.3times $ , and $10.0times $ enhancement over prior designs in terms of latency, throughput rate, and energy efficiency. Consequently, o-r reconfigurable design has great potential to meet various 5G NR applications.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference Using
           Memory-Immersed Data Conversion and Multiplication-Free Operators
    • Authors: Shamma Nasrin;Diaa Badawi;Ahmet Enis Cetin;Wilfred Gomes;Amit Ranjan Trivedi;
      Pages: 1966 - 1978
      Abstract: We propose a co-design approach for compute-in-memory inference for deep neural networks (DNN). We use multiplication-free function approximators based on $ell _{1}$ norm along with a co-adapted processing array and compute flow. Using the approach, we overcame many deficiencies in the current art of in-SRAM DNN processing such as the need for digital-to-analog converters (DACs) at each operating SRAM row/column, the need for high precision analog-to-digital converters (ADCs), limited support for multi-bit precision weights, and limited vector-scale parallelism. Our co-adapted implementation seamlessly extends to multi-bit precision weights, it doesn’t require DACs, and it easily extends to higher vector-scale parallelism. We also propose an SRAM-immersed successive approximation ADC (SA-ADC), where we exploit the parasitic capacitance of bit lines of SRAM array as a capacitive DAC. Since the dominant area overhead in SA-ADC comes due to its capacitive DAC, by exploiting the intrinsic parasitic of SRAM array, our approach allows low area implementation of within-SRAM SA-ADC. Our $8times 62$ SRAM macro, which requires a 5-bit ADC, achieves ~105 tera operations per second per Watt (TOPS/W) with 8-bit input/weight processing at 45 nm CMOS. Our $8times 30$ SRAM macro, which requires a 4-bit ADC, achieves ~84 TOPS/W. SRAM macros that require lower ADC precision are more tolerant of process variability, however, have lower TOPS/W as well. We evaluated the accuracy and performance of our proposed network for MNIST, CIFAR10, and CIFAR100 datasets. We chose a network configuration which adaptively mixes multiplication-free and regular operators. The network configura-ions utilize the multiplication-free operator for more than 85% operations from the total. The selected configurations are 98.6% accurate for MNIST, 90.2% for CIFAR10, and 66.9% for CIFAR100. Since most of the operations in the considered configurations are based on proposed SRAM macros, our compute-in-memory’s efficiency benefits broadly translate to the system-level.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Radix-2 w Arithmetic for Scalar Multiplication in Elliptic Curve
           Cryptography
    • Authors: Abdelkrim Kamel Oudjida;Ahmed Liacha;
      Pages: 1979 - 1989
      Abstract: Elliptic curve scalar multiplication $k$ . $P$ , where $k$ is a nonnegative constant and $P$ is a point on the elliptic curve, requires two distinct operations: addition (ADD) and doubling (DBL). To reduce the number of ADDs without increasing the number of DBLs, a recoding of $k$ with fewer nonzero digits is necessary. Based on Radix- $2^{w}$ arithmetic, we introduce a principled $w$ -bit windowing method where the properties of speed, memory, and security are described by exact analytic formulas as proof of superiority. Contrary to existing windowing algorithms, to minimize the number of ADDs the window size ( $w$ ) is guided by an optimum depending on the bit-length ( $l$ ) of the scalar k. The number of required precomputations is minimal regarding the value of $w$ . The proposed method recodes the binary string $k$ and evaluates the multiplication on-the-fly from right-to-left and left-to-right, likewise. Radix- $2^{w}$ method is very easy to be used and highly reconfigurable, allowing speed-memory and speed-security trade-offs to satisfy different crypto-system constraints. Furthermore, the met-od shows a high resilience to side-channel attacks based on power, timing, and statistical analysis. All Radix- $2^{w}$ properties are confronted to standard windowing methods’ through an in-depth analysis of the complexities. An overall comparison is made via NIST-recommended GF( $2^{l}$ ) finite fields.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Metastability in Superconducting Single Flux Quantum (SFQ) Logic
    • Authors: Gourav Datta;Yunkun Lin;Bo Zhang;Peter A. Beerel;
      Pages: 1990 - 2002
      Abstract: Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106 years.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • A Novel Flow for Reducing Dynamic Power and Conditional Performance
           Improvement
    • Authors: Moaz Mostafa;M. Watheq El-Kharashi;Mohamed Dessouky;Ahmed M. Zaki;
      Pages: 2003 - 2016
      Abstract: Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for its identified issues, which enables using the toggling control with pipelined systems in a more efficient way. A novel flow named “Power Reduction Flow” is proposed for reducing dynamic power of digital circuits. Our flow uses novel design analytical methods, novel “Dynamic Logic Modifier Flow”, and novel “Dynmic Logic Area Validation Flow” for reducing dynamic power with conditionally improving performance. The new design analytical methods are based on probability theory, SystemVerilog covergroups, and digital circuit modeling. A new event type perspective is also proposed to analyze designs to reduce dynamic power in them. Experimental results using TSMC 65 nm and low supply voltages show up to 59% power reduction compared to the original traditional techniques with improving circuit’s performance by $3times $ of its original maximum operating frequency at the cost of an extra 12.3% increase in area.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network
           Processing
    • Authors: Suchang Kim;Jihyuck Jo;In-Cheol Park;
      Pages: 2017 - 2029
      Abstract: This paper presents a convolution process and its hardware architecture for energy-efficient deep neural network (DNN) processing. A DNN in general consists of a number of convolutional layers, and the number of input features involved in the convolution of a shallow layer is larger than that of kernels. As the layer deepens, however, the number of input features decreases, while that of kernels increases. The previous convolution architectures developed for enhancing energy efficiency have tried to reduce the memory accesses by increasing the reuse of the data once accessed from the memory. However, redundant memory accesses are still required as the change in the numbers of data has not been considered. We propose a hybrid convolution process that selects either a kernel-stay or feature-stay process by taking into account the numbers of data, and a forwarding technique to further reduce the memory accesses needed to store and load partial sums. The proposed convolution process is effective in maximizing data reuse, leading to an energy-efficient hybrid convolution architecture. Compared to the state-of-the- art architectures, the proposed architecture enhances the energy efficiency by up to 2.38 times in a 65nm CMOS process.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • A Real-Time Architecture for Pruning the Effectual Computations in Deep
           Neural Networks
    • Authors: Mohammadreza Asadikouhanjani;Hao Zhang;Lakshminarayanan Gopalakrishnan;Hyuk-Jae Lee;Seok-Bum Ko;
      Pages: 2030 - 2041
      Abstract: Integrating Deep Neural Networks (DNNs) into the Internet of Thing (IoT) devices could result in the emergence of complex sensing and recognition tasks that support a new era of human interactions with surrounding environments. However, DNNs are power-hungry, performing billions of computations in terms of one inference. Spatial DNN accelerators in principle can support computation-pruning techniques compared to other common architectures such as systolic arrays. Energy-efficient DNN accelerators skip bit-wise or word-wise sparsity in the input feature maps (ifmaps) and filter weights which means ineffectual computations are skipped. However, there is still room for pruning the effectual computations without reducing the accuracy of DNNs. In this paper, we propose a novel real-time architecture and dataflow by decomposing multiplications down to the bit level and pruning identical computations in spatial designs while running benchmark networks. The proposed architecture prunes identical computations by identifying identical bit values available in both ifmaps and filter weights without changing the accuracy of benchmark networks. When compared to the reference design, our proposed design achieves an average per layer speedup of $times 1.4$ and an energy efficiency of $times 1.21$ per inference while maintaining the accuracy of benchmark networks.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key
           Encapsulation Using a Fast Montgomery Multiplier
    • Authors: Mohammad-Hossein Farzam;Siavash Bayat-Sarmadi;Hatameh Mosanaei-Boorani;Armin Alivand;
      Pages: 2042 - 2050
      Abstract: Public key cryptography lies among the most important bases of security protocols. The classic instances of these cryptosystems are no longer secure when a large-scale quantum computer emerges. These cryptosystems must be replaced by post-quantum ones, such as isogeny-based cryptographic schemes. Supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE) are two of the most important such schemes. To improve the performance of these protocols, we have designed several modular multipliers. These multipliers have been implemented for all the prime fields used in SIKE round 3, on a Virtex-7 FPGA, showing a time and area-time product improvement of up to 60.1% and 64.5%, respectively. These multipliers are also suitable for applications such as RSA, as shown by implementations for 512-bit, 1024-bit, and 2048-bit generic moduli on a Virtex-7 FPGA. Our fastest multiplier has been used in the implementation of SIDH and SIKE round 3. Employing six instances of this multiplier, SIDH completes after 7.33, 8.93, 13.39, and 18.67 milliseconds and the encapsulation and the decapsulation of SIKE is performed in 7.13, 8.68, 13.08, and 18.16 milliseconds over $p_{434}$ , $p_{503}$ , $p_{610}$ , $p_{751}$ , respectively, which yields a least improvement factor of 1.23.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Reduced Complexity Optimal Convolution Based on the Discrete Hirschman
           Transform
    • Authors: Dingli Xue;Linda S. DeBrunner;Victor DeBrunner;
      Pages: 2051 - 2059
      Abstract: The Discrete Hirschman Transform (DHT) is more computationally attractive than the Discrete Fourier Transform (DFT). Based on its derived linear convolution, we have confirmed that the DHT-based convolution filter shows its superiority in reducing computations conditionally, while compared with the conventional DFT-based convolution filter in our previous work. Since the DHT-based convolution has many configurations depending on parameter choices, we conjecture that there should be an optimal case for the largest reduction in computations. In this paper, for the DHT-based convolution, we express the requirement in real computations and propose an approach of how to determine the optimal parameters to reduce computations. We further compare the computational load of the optimal DHT-based convolution with that of other popular convolutions. Moreover, its reduction in clock cycles has also been estimated using a Digital Signal Processor (DSP) TMS320C5545. Results indicate that the optimal DHT-based convolution can reduce real computations (multiplications by $9.09%-50%$ and additions by $1.12%-51.09%$ ) and clock cycles, according to the input length and filter size, except for some cases with identical performance to the radix-2 FFT-based competitor.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Evaluating Performances and Importance of Venture Capitals: A Complex
           Network Approach
    • Authors: Jiaqi Liu;Xuerong Li;Linyuan Lü;Jichang Dong;Jinhu Lü;
      Pages: 2060 - 2068
      Abstract: Venture capital market is one of the most important financial markets, which plays an important role in promoting industrial innovation and economic development. In this study, the complete data set of all venture capital events occurred in China from 2009 to 2020 was used to construct two kinds of complex networks, whose topological property and dynamic evolution trend of the network are studied. Specifically, we construct the co-investment network among investor, as well as the binary complex network of investor-entrepreneur, and propose the evaluation method of the importance and performance of venture capital institutions. Based on the proposed method, we identify some leading venture capital institutions with high performance and importance. Furthermore, this paper enlightens venture capital practitioners by discovering the investment behavior and preference of these leading institutions.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Lattice Trajectory Piecewise Linear Method for the Simulation of Diode
           Circuits
    • Authors: Jiade Wang;Jun Xu;Shuning Wang;
      Pages: 2069 - 2081
      Abstract: In this paper, we present an approach to nonlinear system approximation, called the lattice trajectory piecewise linear (LTPWL) model. The approach involves determining a lattice piecewise linear (PWL) approximation to the state trajectory of a nonlinear system. It has been shown in the literature that the lattice PWL expression can represent any PWL function in any dimension. After the LTPWL approximation has been obtained, the order of each model piece is reduced using a Krylov projection technique. Compared to existing trajectory piecewise linear (TPWL) models, which are quasi-PWL in the whole region, LTPWL models are virtually linear in each subregion. Besides, the single output LTPWL model can be seen as a special kind of TPWL model, in which only one weight is 1, and the other weights are 0. In general, for multiple output LTPWL model, the weights set to be 1 for each component are different, which makes the LTPWL model more flexible in approximation of nonlinear function. The proposed strategy is applied to simulate diode circuits, and the experimental results show that the performance of the LTPWL model is better than that of the traditional TPWL model in terms of approximation accuracy and generalization ability.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Improved Vertex Coloring With NbO Memristor-Based
           Oscillatory Networks
    • Authors: Martin Weiher;Melanie Herzig;Ronald Tetzlaff;Alon Ascoli;Thomas Mikolajick;Stefan Slesazeck;
      Pages: 2082 - 2095
      Abstract: The main focus of this paper is the presentation of reliable methods for the determination of the optimum coloring of a graph, commonly known in the literature as vertex coloring problem. It has been shown that networks of capacitively coupled oscillators can be used to solve vertex coloring problems. In this paper we address the negative impact of an unbalanced number of couplings for the oscillators on the performance of the network and compensate for this non-uniform coupling structure by an adjustment in the network itself. The negative effect of the memristor device-to-device variability of the $text {NbO}_{text {x}}$ memristor on the array functionality will be investigated and reduced via an adaptation of the memristor operating point. The main improvement in network performance is achieved by setting up a control procedure allowing the network to bypass the local solutions and converge to the global one. Two strategies inspired by global optimization algorithms will be proposed to allow the network to overcome sub-optimal solutions, and find the solution corresponding to the absolute minimum of a performance measure function of the vertex coloring problem.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and
           Matching Networks
    • Authors: Rakesh Sinha;
      Pages: 2096 - 2106
      Abstract: Two synthesis algorithms of multiport network with desired unequal complex port-impedances are developed considering the multiport network as an interconnection of two-port networks (TPNs). The first one is direct-synthesis using Y-matrix, and the second one is port-impedance transformation method. The techniques are single-frequency methods, as the scattering parameters of known multiport networks are defined at the design frequency. In direct-synthesis, the desired S- matrix of the multiport network is converted into the desired Y-matrix, considering the reference port-impedance matrix. Then the multiport network structure or topology can be predicted using the non-zero off-diagonal entries of Y-matrix. The Y-matrix of the predicted multiport is calculated in terms of unknown design parameters or sub-network parameters. Finally, by equating the predicted Y-matrix with the desired Y- matrix, the design equations are obtained. In the port impedance transformation method, a core network with intermediate port-impedances is designed using the direct-synthesis method. Then the intermediate port-impedances are converted into desired port impedances using external matching networks. The impedance matching networks are designed using the desired phased impedance matching theory. Two different designs of a four-port network are provided to validate the proposed concepts. Two pseudocodes or algorithms are developed considering lumped $Pi $ networks as building blocks.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Accurate Modeling of the Effective Parasitic Parameters for the Laminated
           Busbar Connected With Paralleled SiC MOSFETs
    • Authors: Jianing Wang;Shaolin Yu;Xing Zhang;Zhaoyang Wei;Nan Jiang;Wenjie Chen;Enli Du;
      Pages: 2107 - 2120
      Abstract: Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered and effectively modeled for the parasitics of the busbar, which is not accurate enough to evaluate the current imbalance for the busbar connected with SiC devices. This paper proposes accurate modeling of the effective parasitic parameter of laminated busbars with paralleled SiC MOSFETs. The model incorporates not only the self-inductance and resistance but also the complex mutual coupling effect of all the current paths. Moreover, a switching period is divided into two durations for accurate effective parasitic models, in which the busbar can have different effective models regarding one physical structure. Furthermore, for easy evaluation of the current balance, a single effective model, namely equivalent model, is derived for a physical structure by replacing the complex mutual network. A specific laminated busbar for EV inverter is analyzed to prove the above theory, which is validated by simulation and experiment separately.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Fixed-Time Fault-Tolerant Formation Control for Heterogeneous Multi-Agent
           Systems With Parameter Uncertainties and Disturbances
    • Authors: Wanglei Cheng;Ke Zhang;Bin Jiang;Steven X. Ding;
      Pages: 2121 - 2133
      Abstract: This paper investigates the fixed-time time-varying formation control problems for heterogeneous multi-agent systems (MASs) composed of multiple Unmanned Ground Vehicles (UGVs) and multiple Unmanned Aerial Vehicles (UAVs) in the presence of actuator faults, parameter uncertainties, matched and mismatched disturbances. Besides achieving the desired formation configurations, each follower can also track the position trajectory produced by the virtual leader within fixed time simultaneously. The difference dynamic characteristics between the heterogeneous agents leads to unbalanced interaction of lumped uncertainties in the communication network, which increases the difficulty of collaborative control. To estimate the mismatched disturbances and lumped uncertainties, a fixed-time observer for each follower is designed, which can guarantee the estimation errors converge to the origin in fixed settling time. Subsequently, by utilizing the backstepping technique and the fixed-time stability theory, an observer-based distributed fixed-time formation controller for each follower in the $X$ - $Y$ axes and the observer-based decentralized fixed-time tracking controllers for follower-UAVs in the $Z$ axes are presented, which are shown to be fixed-time stable even under the influence of actuator faults and mismatched disturbances. Moreover, the fixed-time results can ensure the convergence time is independent of initial conditions. Finally, numerical simulations demonstrate the effectiveness of the proposed algorithms.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Bounded-Input Bounded-Output Stability Tests for Two-Dimensional
           Continuous-Time Systems
    • Authors: Yuval Bistritz;
      Pages: 2134 - 2147
      Abstract: This paper presents two efficient algorithms to determine whether a bivariate polynomial, possibly with complex coefficients, does not vanish in the cross product of two closed right-half planes (is “2-C stable”). A 2-C stable polynomial in the denominator of a two-dimensional analog filter has been proved (not long ago) to imply bounded-input bounded-output (BIBO) stability. The two algorithms are entirely different but both rely on a recently proposed fraction-free (FF) Routh test for complex polynomials in this transaction. The first algorithm tests the 2-C stability of a bivariate polynomial of degree $(n_{1},n_{2})$ in order $n^{6}$ of elementary operations (when $n_{1}=n_{2}=n$ ). It is a “tabular type” two-dimensional stability test that can be regarded as a “Routh table” whose scalar entries were replaced by univariate polynomials. The second 2-C stability test is obtained from the first by its telepolation. It carries out the 2-C stability test by a finite collection of FF Routh tests and requires only order $n^{4}$ elementary operations. Both algorithms possess an integer-preserving property that enhances them with additional merits including numerical error-free decision on 2-C stability.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Quasi-Synchronization of Heterogeneous LC Circuits in Grid-Connected
           Systems With Intentionally Time-Varying Lumped Delays
    • Authors: Yanping Yang;Wangli He;Qing-Long Han;
      Pages: 2148 - 2157
      Abstract: This article is concerned with quasi-synchronization of grid-connected systems in electrical networks, where heterogeneous Inductance-Capacitance (LC) oscillators are coupled via electrical inductance subject to time-varying delays. Note that complete synchronization fails to be accomplished due to the existence of nonidentical parameters and quasi-synchronization cannot be achieved via non-delayed inductive coupling. A configuration of multiple heterogeneous LC oscillators with inductive coupling subject to time-varying lumped delay is first constructed by introducing an active delay intentionally. Then the complete-type Lyapunov-Krasovskii functionals (LKF) are constructed to investigate the exponential convergence of quasi-synchronization of LC oscillators in the presence of parameter mismatches utilizing the positive effects of interval time-varying delays. Some feasible synchronization criteria are derived. The gain matrix can be designed by solving a set of linear matrix inequalities combining an optimization algorithm. Finally, a numerical example of five LC oscillators in photovoltaic grid-connected system is given to demonstrate the effectiveness of the proposed method.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Co-Design of Fault Detection and Consensus Control Protocol for
           Multi-Agent Systems Under Hidden DoS Attack
    • Authors: Dan Zhang;Zehua Ye;Xiwang Dong;
      Pages: 2158 - 2170
      Abstract: This article is concerned with the co-design of fault detection and consensus control protocol for a class of multi-agent systems (MASs) subject to Denial-of-Service attack, where the attack behavior is hidden to the defender as the adversary may launch the attack with different durations but the defender may not know the real situation at each time instant. Due to the complicated attack behavior, a hidden semi-Markov process is introduced where only the observed attack modes emitted by the inaccessible ones are available. The probability density functions of sojourn time and the semi-Markov kernel are adopted to help analyze the combined fault detection and consensus control system. Sufficient conditions on the $sigma $ -error mean square stability of MASs with mixed ${H_infty }/{H_ {-} }$ performance are established by using a set of Lyapunov functions that depend on the hidden and the observed attack modes. Moreover, the gain matrices of controller and detector are obtained by solving an optimization problem with some matrix inequality constraints. Finally, the simulation of autonomous unmanned underwater vehicles is used to show the effectiveness of the proposed results.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Bumpless Transfer Control for Switched Linear Systems and its Application
           to Aero-Engines
    • Authors: Yan Shi;Xi-Ming Sun;
      Pages: 2171 - 2182
      Abstract: To avoid the bumps of the control signal in the switching instants, this paper proposes a bumpless transfer control method which guarantees the continuous of control signal while keeping the asymptotic stability of the closed-loop system. Firstly, the presented bumpless transfer control method possesses a simple structure and meanwhile not have to redesign sub-controllers, which is easy to implement. Furthermore, the method is appropriate for either stable subsystems or unstable subsystems, and be suitable for either state feedback control or dynamic output feedback control. Moreover, we give the sufficient conditions of asymptotic stability for switched linear systems under bumpless transfer control for four cases. For the original switched system with stable subsystems under state or dynamic output feedback control, the stability conditions under mode-dependent average dwell time switching are derived. For the original switched system with unstable subsystems under state or dynamic output feedback control, which is stabilized by some certain switching laws, the stability conditions under the original switching law are given. Finally, a hardware-in-the-loop simulation of an aero-engine control system is employed to verify the effectiveness and superiority of the proposed method.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Power Scaling Laws for Radio Receiver Front Ends
    • Authors: Muris Sarajlić;Ashkan Sheikhi;Liang Liu;Henrik Sjöland;Ove Edfors;
      Pages: 2183 - 2195
      Abstract: In this paper, we combine practically verified results from circuit theory with communication-theoretic laws. As a result, we obtain closed-form theoretical expressions linking fundamental system design and environment parameters with the power consumption of analog front ends (AFEs) for communication receivers. This collection of scaling laws and bounds is meant to serve as a theoretical reference for practical low power AFE design. We show how AFE power consumption scales with bandwidth, $mathit {SNDR}$ , and $mathit {SIR}$ . We build our analysis based on two well established power consumption studies and show that although they have different design approaches, they lead to the same scaling laws. The obtained scaling laws are subsequently used to derive relations between AFE power consumption and several other important communication system parameters, namely, digital modulation constellation size, symbol error probability, error control coding gain, and coding rate. Such relations, in turn, can be used when deciding which system design strategies to adopt for low-power applications. For instance, we show how AFE power scales with environment parameters if the performance is kept constant and we use these results to illustrate that adapting to fading fluctuations can theoretically reduce AFE power consumption by at least 20x.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Adaptive Multi-Band Negative-Group-Delay RF Circuits With Low Reflection
    • Authors: Roberto Gómez-García;José-María Muñoz-Ferreras;Dimitra Psychogiou;
      Pages: 2196 - 2209
      Abstract: Two classes of frequency-reconfigurable multi-band negative-group-delay (NGD) circuit networks that feature low-input-power-reflection capabilities are reported. They consist of lossy-complementary-diplexer architectures, in which the NGD properties are obtained within the stopband regions of their lossy multi-band bandstop-filter (BSF) channel. Their complementary lossy multi-band bandpass-filter (BPF) branch absorbs in its terminating resistor the RF-input-signal energy that is not transmitted by the lossy multi-band BSF channel within its stopbands. In this manner, the input-reflectionless/absorptive behavior is realized. The theoretical foundations of the devised lossy-multi-band-BSF-based NGD structures using a coupling-routing-diagram formalism and single-to-multi-band admittance transformations are described. For the first-order case as illustration, guidelines for the synthesis in the bandpass frequency domain are provided. Furthermore, the extension of these multi-band NGD approaches to higher-order and in-series-cascade multi-stage realizations for more-general and wider-band NGD patterning, as well as to two-port/symmetrical designs, is shown. In addition, the conception of multi-functional passive components with NGD characteristics, such as wide-band BPFs and power directional couplers with embedded NGD regions, is also addressed. For experimental-demonstration purposes, an electronically-reconfigurable microstrip prototype of a two-stage-in-series-cascade dual-band NGD circuit is manufactured and measured.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Impedance Transparency and Performance Metrics of HBT-Based N-Path Mixers
           for mmWave Applications
    • Authors: Robin Ying;Alyosha Molnar;
      Pages: 2210 - 2223
      Abstract: MOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this paper presents the theory and design considerations for a new topology of N-path mixer which makes use of high fT HBTs and breaks this trade-off between performance and tuning range. Here, we borrow from a previously derived LTI model for MOS-based N-path mixers to derive an analogous model for the HBT-based counterpart which provides a meaningful comparison between the performance of the two topologies. We show that the HBT-based implementation is capable of operation beyond the frequency limits of MOS-based implementations while maintaining comparable NF and linearity without consuming exorbitant power. Measurements done on a proof-of-concept chip in GlobalFoundries BiCMOS8HP are consistent with our models and simulations. By organizing process parameters and user-selected design variables into dimensionless ratios, we provide expressions for key performance metrics which enable the designer to make informed decisions about trade-offs and optimizations for both LO generation and the mixer core.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • High-Speed LDPC Decoders Towards 1 Tb/s
    • Authors: Meng Li;Veerle Derudder;Kaoutar Bertrand;Claude Desset;André Bourdoux;
      Pages: 2224 - 2233
      Abstract: Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into the pipeline architecture and by using multi-core architectures. Two high rate medium size QC LDPC codes are designed with fast decoding convergence speed for this architecture. Both codes are implemented with single core and multi-core architectures to explore different trade-offs between code design, communication performance and implementation. The four decoders are implemented in 16 nm CMOS FinFET technology with a clock rate of 1 GHz. The placement and routing implementation results show that the single core decoder for the LDPC (1027, 856) code is able to provide 114 Gb/s throughput at maximum 3 iterations with an area of 0.173 mm2 and energy efficiency of 1.56 pJ/bit; the multi-core decoder for the (1032, 860) code is able to provide 860 Gb/s throughput at maximum 2 iterations with an area of 1.48 mm2 and energy efficiency of 3.24 pJ/bit. The multi-core decoder achieves the highest throughput in the literature for medium size (1–2k) LDPC codes. When compared with other state-of-the-art fully parallel high speed architectures, the proposed architectures bring a significant gain both in area efficiency and energy efficiency while keeping the ability to offer flexibility in code rate, number of iterations and early stop.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency
           Synthesizers
    • Authors: Christoph Preissl;Peter Preyler;Andreas Springer;Mario Huemer;
      Pages: 2234 - 2245
      Abstract: Digital-to-time converters (DTCs) are a promising technology for radio frequency (RF) transceivers but are prone to spur generation. A common approach to change the spurious emissions to a spur-free shape is a method called dithering. The power added due to dithering is an important aspect of this approach and gives raise to investigations on additive dither as well as methods for subtractive dithering. This work presents a mathematical model for dithering DTC-based local oscillator (LO) generators. It proposes concepts for the application of subtractive dither and it introduces a novel generalization of quantization-dither to allow for optimal dithering of nonlinear quantizers.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Dynamic Triggering Mechanisms for Distributed Adaptive Synchronization
           Control and Its Application to Circuit Systems
    • Authors: Yong Xu;Jian Sun;Gang Wang;Zheng-Guang Wu;
      Pages: 2246 - 2256
      Abstract: Nonlinear couplings among units (nodes) are ubiquitous in engineering systems including, e.g., radar and sonar systems, which have been ignored in most works. In this article, the problem of distributed synchronization of nonlinear networked systems with nonlinear couplings is studied. Specifically, two kinds of nodes’ communication couplings including nonlinear relative and nonlinear absolute state couplings are considered. To reduce the requirements of control and communication among nodes and avoid any global network information, two edge-based fully adaptive event-triggered control protocols based on nonlinear relative and absolute state couplings are proposed by using the projection operator technique, which is followed by design of corresponding dynamic event-triggered mechanisms. The advantages of our proposed dynamic event-triggered strategies show that it can boil down to existing static ones as special examples, and the minimal inter-execution time of the proposed dynamic triggering laws is larger than that of static ones. Theoretical analysis shows that the proposed algorithm not only guarantees fully adaptive Zeno-free synchronization of networked systems without requiring any global information, but also avoids continuous communications among nodes, and considerably reduce the frequency of controller updates. Finally, the practical merits of the proposed algorithms are corroborated using a Chua’s circuit network.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • A T-Type Switched-Capacitor Multilevel Inverter With Low Voltage Stress
           and Self-Balancing
    • Authors: Yaoqiang Wang;Yisen Yuan;Gen Li;Yuanmao Ye;Kewen Wang;Jun Liang;
      Pages: 2257 - 2270
      Abstract: This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • Multi-Frequency Multi-Amplitude Superposition Modulation Method With Phase
           Shift Optimization for Single Inverter of Wireless Power Transfer System
    • Authors: Jie Wu;Lizhong Bie;Weihao Kong;Pengfei Gao;Yanfeng Wang;
      Pages: 2271 - 2279
      Abstract: In wireless charging devices, different wireless charging standards have caused charging incompatibility, and the utilization rate of the DC voltage at the transmitter is not high, which brings challenges to the application of wireless charging. To solve these two problems, this paper proposes a multi-frequency multi-amplitude (MFMA) superimposition modulation method. This method superimposes multiple frequency signals, and then compares the synthesized signal with a high-frequency triangular carrier to output a square wave voltage signal containing information such as the frequency and amplitude of the pre-output signal. Furthermore, a phase-shifting optimization algorithm is proposed, i.e., based on the proposed MFMA superimposition modulation method, the utilization rate of the DC voltage of the system is improved by reasonably adjusting the initial phase of each frequency. Simulation and experimental results show that the proposed method can output at least four frequencies simultaneously by using a single inverter, effectively reducing the volume of the transmitter, and being compatible with the frequency range of several charging standards. The proposed phase-shifting optimization has a significant effect on improving the utilization of DC voltage with an increase of 44.88%.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
  • IEEE Transactions on Circuits and Systems—I:Regular Papers
           information for authors
    • Pages: 2280 - 2280
      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: May 2021
      Issue No: Vol. 68, No. 5 (2021)
       
 
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