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Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Xiaoxuan Yang;Brady Taylor;Ailong Wu;Yiran Chen;Leon O. Chua;
Pages: 1845 - 1857 Abstract: As the limits of transistor technology are approached, feature size in integrated circuit transistors has been reduced very near to the minimum physically-realizable channel length, and it has become increasingly difficult to meet expectations outlined by Moore’s law. As one of the most promising devices to replace transistors, memristors have many excellent properties that can be leveraged to develop new types of neural and non-von Neumann computing systems, which are expected to revolutionize information-processing technology. This survey provides a comparative overview of research progress on memristors. Different memristor synaptic devices are classified according to stimulation patterns and the working mechanisms of these various synaptic devices are analyzed in detail. Crossbar-based memristors have demonstrated advantages in physically executing vector-matrix multiplication and enabling highly power-efficient and area-efficient neuromorphic system designs. The extensive uses of crossbar-based memristors cover in-memory logic, vector-matrix multiplication, and many other fundamental computing operations. Furthermore, memristor-based architectures for efficient neural network training and inference have been studied. However, memristors have non-ideal properties due to programming inaccuracies and device imperfections from fabrication, which lead to error or mismatch in computed results. To build reliable memristor-based designs, circuit-level, algorithm-level, and system-level solutions to memristor reliability issues are being studied. To this end, state-of-the-art realizations of memristor crossbars, crossbar-based designs, and peripheral circuitry are presented, which show both promising full-system inference accuracy and excellent power efficiency in multiple tasks. Memristor in-situ learning benefits from high energy efficiency and biologically-imitative characteristics, which are conducive to further realizing hardware acceleration of-cognitive learning. At present, the learning and training processes of brain-like networks are complex, presenting great challenges for network design and implementation. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Luca Bertulessi;Dmytro Cherniak;Mario Mercandelli;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino;
Pages: 1858 - 1870 Abstract: This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 $mu text{s}$ , overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Feng Qiu;Haoshen Zhu;Wenquan Che;Quan Xue;
Pages: 1871 - 1882 Abstract: An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ( $f_{0}$ ) to extract the 2N-order harmonic (2N $f_{0}$ ) while canceling the fundamental ( $f_{0}$ ) and the 2nd to (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential $times 6$ frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented $times 6$ frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2nd to 5th harmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Maxime Schramme;Léopold Van Brandt;Denis Flandre;David Bol;
Pages: 1883 - 1895 Abstract: Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to $4.63times $ lower minimum power consumption and slightly better FoM values than CSROs. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yuyi Shen;Jiachen Xu;Jinho Yi;Ethan Chen;Vanessa Chen;
Pages: 1896 - 1909 Abstract: One means by which the security of Internet-of-Things (IoT)-enabled devices may be augmented is through radio-frequency fingerprinting-based authentication methods. As variability in CMOS processes increases with technology scaling, the hardware imperfections that form RF fingerprints can be controlled with small reconfigurable elements, enabling the feasibility of RF fingerprinting as a low overhead security measure for device authentication. To achieve rapid RF identification, we present an inherently secure RF power amplifier and a convolutional neural network-based machine learning classifier through an exploration of combinatorial randomness and self-aware detection mechanisms. By selecting different subsets of thinly sliced power amplifier elements, combinations of random process variations are exploited and updated to form a large search space of distinct RF fingerprints and improve fingerprint prominence. The rich features enabled by augmented device primitives are updated in a time-varying manner to strengthen built-in hardware security. Measurement results demonstrate the effectiveness of this approach at generating distinguishable RF fingerprints across a significant number of configurations. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Farshad Yazdi;Alireza Nikzamir;Tarek Mealy;Mohamed Y. Nada;Filippo Capolino;
Pages: 1910 - 1918 Abstract: We introduce a circuit topology based on a simple triple-ladder circuit realized with lumped reactive components that provides a sixth order degenerate band-edge (6DBE). The 6DBE is a special kind of sixth-order exceptional point of degeneracy in a lossless and gainless periodic ladder. This degeneracy provides a very flat band edge in the phase-frequency dispersion diagram. The proposed topology exhibits unique structured resonance features associated with a high loaded Q-factor. We investigate the Floquet-Bloch modes in an infinite-length periodic triple-ladder and their dispersion relation using the S parameter formalism. We also provide the approximate analytic expressions of the eigenmodes and dispersion relation around the degenerate point based on the Puiseux series expansion. We investigate the filtering characteristics of a finite-length structure terminated with loads to highlight the special properties of the 6DBE compared to ladders with regular band edge (RBE) and fourth order degenerate band edge (DBE). The circuit framework introduced here with a 6DBE can be exploited in designing novel high Q-factor oscillators, filters, sensors, and pulse shaping networks. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Mahmoud A. A. Ibrahim;Marvin Onabajo;
Pages: 1919 - 1931 Abstract: This paper describes a hybrid binary frequency-phase shift keying (BF-PSK) receiver architecture designed with a technique involving both the received signal frequency and phase for low-power operation with relatively high data rate. The method enables the demodulation of the incoming signal without synchronization requirements, which reduces the design complexity and power consumption. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. A novel low-noise amplifier architecture is introduced in this paper as well. The Medical Implant Communication System (MICS) band receiver was designed and fabricated in a standard 65nm CMOS technology, and the measurement results demonstrate the feasibility of this architecture. As a proof-of-concept, it operates with a 416 MHz carrier frequency at a state-of-the-art data rate for sub-milliwatt receivers of 10 Mbps, while consuming $610~mu text{W}$ from a 1 V supply. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Rui-Jia Liu;Xiao-Wei Zhu;Jing Xia;Peng Chen;Chao Yu;Xiao-Liang Wu;Xiang Chen;
Pages: 1932 - 1942 Abstract: In this paper, a highly efficient gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) from 4.6 to 5.5 GHz with the consideration of the influence of the peaking transistor’s output capacitor $(C_{mathrm {out}}$ ) operated in Class-C state is presented. Based on the load-modulation behavior analysis, the effect of the $C_{mathrm {out}}$ of the peaking transistor on the performance of the wideband DPA has been theoretically analyzed for the first time by directly evaluating the value of the peaking transistor’s $C_{mathrm {out}}$ . A hybrid matching technique has been proposed to ensure that the DPA can realize a proper load-modulation with high back-off efficiency in a wide bandwidth. In this method, the peaking transistor is matched using a simple T-shape band-pass type network with the $C_{mathrm {out}}$ of the peaking transistor in Class-C operation state compensated properly, while the carrier transistor is matched using a 2-point matching method. For verification, a wideband GaN MMIC DPA with the frequency range of 4.6 to 5.5 GHz was designed using a 0.25- $mu {mathrm{ m}}$ GaN on silicon-carbon high-electron-mobility transistor process. Experimental results show that the fabricated DPA can realize the output power of 41.1-41.6 dBm and the drain efficiency (DE) of 57.6%-63.3% at saturation in the whole frequency band. The measured DE at 6-dB power back-off is 51%-56.4%. Good linearity with high average efficiency performance was obtained whe- excited by a 160-MHz modulated signal after linearization. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Po-Wei Chiu;Chris H. Kim;
Pages: 1943 - 1951 Abstract: A digital-intensive four-level pulse amplitude (PAM-4) transceiver featuring a 2-tap time-based decision feedback equalization (TB-DFE) circuit was demonstrated in a 65 nm GP CMOS process. A novel inverter-based differential voltage-to-time converter (DVTC) increases the linearity and dynamic range compared to a prior time-based DFE approach enabling reliable PAM-4 operation. The four-level signal comparison and DFE operation were performed entirely in the time domain using programmable delays and a phase detector (PD). Using an on-chip bit error rate (BER) monitor, we verified a BER less than 10−12 while achieving an energy-efficiency of 0.97pJ/b at a 32Gb/s data rate. The transmitter (TX) and receiver (RX) circuits occupy an area of 0.009 mm2. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Foroozan Karimzadeh;Jong-Hyeok Yoon;Arijit Raychowdhury;
Pages: 1952 - 1961 Abstract: The rising popularity of intelligent mobile devices and the computational cost of deep learning-based models call for efficient and accurate on-device inference schemes. We propose a novel model compression scheme that allows inference to be carried out using bit-level sparsity, which can be efficiently implemented using in-memory computing macros. In this paper, we introduce a method called BitS-Net to leverage the benefits of bit-sparsity (where the number of zeros are more than number of ones in binary representation of weight/activation values) when applied to compute-in-memory (CIM) with resistive RAM (RRAM) to develop energy efficient DNN accelerators operating in the inference mode. We demonstrate that BitS-Net improves the energy efficiency by up to 5x for ResNet models on the ImageNet dataset. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Mojtaba Mahdavi;Stefan Weithoffer;Matthias Herrmann;Liang Liu;Ove Edfors;Norbert Wehn;Michael Lentmaier;
Pages: 1962 - 1975 Abstract: Spatially coupled serially concatenated codes (SC-SCCs) are constructed by coupling several classical turbo-like component codes. The resulting spatially coupled codes provide a close-to-capacity performance and low error floor, which have attracted a lot of interest in the past few years. The aim of this paper is to perform a comprehensive design space exploration to reveal different aspects of SC-SCCs, which is missing in the literature. More specifically, we investigate the effect of block length, coupling memory, decoding window size, and number of iterations on the decoding performance, complexity, latency, and throughput of SC-SCCs. To this end, we propose two decoding algorithms for the SC-SCCs: block-wise and window-wise decoders. For these, we present VLSI architectural templates and explore them based on building blocks implemented in 12nm FinFET technology. Linking architectural templates with the new algorithms, we demonstrate various tradeoffs between throughput, silicon area, latency, and decoding performance. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Lei Wang;Zhijie Yang;Shasha Guo;Lianhua Qu;Xiangyu Zhang;Ziyang Kang;Weixia Xu;
Pages: 1976 - 1989 Abstract: Neuromorphic processors have gained momentum recently due to their high energy efficiency in artificial intelligence applications compared to DNN accelerators. Most neuromorphic processors are executing SNNs (Spiking Neural Networks). Liquid State Machine (LSM), as the spiking version of reservoir computing, shows advantages and great potential in image classification, speech recognition, language translation, etc.. Comparing with other SNN models, LSM has the characteristics of easy to train and low resource utilization, which is suitable for low-power and resource-constrained edge computing scenarios. In this paper, we propose a novel design of a neuromorphic processor, LSMCore, aiming at LSM acceleration. LSMCore supports both training and inference of LSM. It consists of 256 input neurons, 1024 liquid neurons, and 1.31M synapses. Besides, multiple optimization techniques, including weight quantization for reducing storage, zero-skipping for decreasing dynamic sparsity, and mini-batch training are adopted in this processor. The experimental results show that the frequency of LSMCore achieves 400 MHz, the power is 4.9W and the area is 18.49 mm2 with a 40nm library. Comparing with the baseline, LSMCore achieves up to $80.7times $ ( $49.6times $ ), $91.3times $ ( $56.3times $ ), and $83.1times $ ( $56.8times $ ) speedup on MNIST, N-MNIST, and Free Spoken Digital Dataset (FSDD) respectively for training (inference), while the accuracy of LSMCore on these three datasets are 96.8%, 97.6%, and -0% respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Chen Ding;Yuxiang Huan;Hao Jia;Yulong Yan;Fanxi Yang;Lizheng Liu;Meigen Shen;Zhuo Zou;Lirong Zheng;
Pages: 1990 - 2001 Abstract: Large-scale neuromorphic computing requires the multi-chip network to provide high computing power. Efficient routing schemes and on-chip router design are necessary for handling various inter-chip transmission patterns. In this paper, we propose a hybrid-mode on-chip router that supports both multicast and unicast routing for the large-scale neuromorphic simulation. Two routing schemes, namely Cache-like Spike Weight Indexing and General Unicast Flow Control, are proposed to accommodate the chip-to-chip transmission of spike and non-spike data. This work is evaluated on a neuromorphic platform built with an $8times 8$ FPGA chips array. Running a simulation of 1M neurons at 200MHz, the proposed router achieves a processing latency of 25ns and a chip-to-chip latency of 287ns. Working in the unicast mode, the router can synchronize status flags of all chips within $5 ~mu text{s}$ . Moreover, it reduces the peak spike traffic by 25.65% with the help of Load-aware Multicast Routing, compared with other multicast routing strategies. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Gianmarco Cerutti;Lukas Cavigelli;Renzo Andri;Michele Magno;Elisabetta Farella;Luca Benini;
Pages: 2002 - 2012 Abstract: Keyword spotting (KWS) is a crucial function enabling the interaction with the many ubiquitous smart devices in our surroundings, either activating them through wake-word or directly as a human-computer interface. For many applications, KWS is the entry point for our interactions with the device and, thus, an always-on workload. Many smart devices are mobile and their battery lifetime is heavily impacted by continuously running services. KWS and similar always-on services are thus the focus when optimizing the overall power consumption. This work addresses KWS energy-efficiency on low-cost microcontroller units (MCUs). We combine analog binary feature extraction with binary neural networks. By replacing the digital preprocessing with the proposed analog front-end, we show that the energy required for data acquisition and preprocessing can be reduced by $29times $ , cutting its share from a dominating 85% to a mere 16% of the overall energy consumption for our reference KWS application. Experimental evaluations on the Speech Commands Dataset show that the proposed system outperforms state-of-the-art accuracy and energy efficiency, respectively, by 1% and $4.3times $ on a 10-class dataset while providing a compelling accuracy-energy trade-off including a 2% accuracy drop for a $71times $ energy reduction. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ehab M. Ibrahim;Linyan Mei;Marian Verhelst;
Pages: 2013 - 2024 Abstract: Reduced-precision and variable-precision multiply-accumulate (MAC) operations provide opportunities to significantly improve energy efficiency and throughput of DNN accelerators with no/limited algorithmic performance loss, paving a way towards deploying AI applications on resource-constraint edge devices. Accordingly, various precision-scalable MAC array (PSMA) architectures were proposed recently. However, it is difficult to make a fair comparison between those alternatives, as each proposed PSMA is demonstrated in different systems and technologies. This work aims to provide a clear view of the design space of PSMA and offer insights for selecting the optimal architectures based on designers’ needs. First, we introduce a precision-enhanced for-loop representation for DNN dataflows. Next, we use this new representation towards a comprehensive PSMA taxonomy, capable of systematically covering most prominent state-of-the-art PSMAs, as well as uncovering new PSMA architectures. Following that, we build a highly parameterized PSMA template that can be design-time configured into a huge subset of the design space spanned by the taxonomy. This allows to fairly and thoroughly benchmark 72 different PSMA architectures. We perform such studies in 28nm technology targeting run-time precision scalability from 8 to 2 bits, operating at 200 MHz and 1 GHz. Analyzing resulting energy and area breakdowns reveals key design guidelines for PSMA architectures. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Sahra Afshari;Mirembe Musisi-Nkambwe;Ivan Sanchez Esqueda;
Pages: 2025 - 2034 Abstract: This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a smart pulsing strategy is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Seongjin Lee;Sangsoo Park;Boseon Jang;In-Cheol Park;
Pages: 2035 - 2048 Abstract: As the low-density parity-check (LDPC) code has a powerful error-correcting performance and can achieve high throughput, it is being used in many application areas and recently adopted as a channel coding method in the 5G New-Radio communication standard. Unlike other LDPC codes, the 5G LDPC code has various irregular lifting sizes to support diverse message lengths. To meet the demanding requirements of the 5G standard, many solutions have been presented, but all of them are either impractical or fail to satisfy all the requirements. This paper, for the first time, proposes an area-efficient QC-LDPC decoder that satisfies the peak throughput requirements of the 5G standard and supports all the lifting sizes specified in the 5G standard. Instead of relying on full parallelism like in the previous works, this work tries partial parallelism to mitigate the hardware complexity, which leads to high efficiency in hardware complexity. In addition, a novel memory access scheduling method is proposed to solve the data access and alignment problems caused by the partially parallel structure, which is effective in supporting all the lifting sizes. A LDPC decoder realized in 65-nm CMOS technology demonstrates that its decoding throughput is greater than 20Gbps and its area is smaller than the existing decoders. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Jooyoon Kim;Yunho Jang;Taehwan Kim;Jongsun Park;
Pages: 2049 - 2059 Abstract: Although spin orbit torque magnetic random access memory (SOT-MRAM) is one of the strong candidates for next-generation embedded memories, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) with process variations has been a large concern. In this paper, we present the dual-domain dynamic reference (DDDR) sensing scheme, where the reference voltage can be dynamically changed based on the combined voltage and time domain sensing to increase the sensing margin. The Half Schmitt trigger and sample & hold circuits are efficiently employed to generate data-dependent reference voltages and to store the sampled voltage levels at different times, respectively. According to the simulations using 28nm CMOS technology with 128 by 128 SOT-MRAM array, the proposed DDDR approach achieves a 243mV of sensing margin under 6.08E-8 bit-error-rate (BER) at 1.76ns, which is 2X larger margin with more than 100 times lower BER compared to the conventional read scheme. When scaling down the pre-charge voltage, the proposed scheme achieves more than 50% of the read energy savings under 1E-5 target BER condition. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Hong-Han Lien;Tian-Sheuan Chang;
Pages: 2060 - 2069 Abstract: Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps. However, because SNNs contain extra time dimension information, the SNN accelerator will require more buffers and take longer to infer, especially for the more difficult high-resolution object detection task. As a result, this paper proposes a sparse compressed spiking neural network accelerator that takes advantage of the high sparsity of activation maps and weights by utilizing the proposed gated one-to-all product for low power and highly parallel model execution. The experimental result of the neural network shows 71.5% mAP with mixed (1,3) time steps on the IVS 3cls dataset. The accelerator with the TSMC 28nm CMOS process can achieve $1024times 576.29$ frames per second processing when running at 500MHz with 35.88TOPS/W energy efficiency and 1.05mJ energy consumption per frame. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Wenhua Chen;Xin Liu;Jiaming Chu;Huibo Wu;Zhenghe Feng;Fadhel M. Ghannouchi;
Pages: 2070 - 2083 Abstract: In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Tommaso Addabbo;Ada Fort;Riccardo Moretti;Marco Mugnaini;Duccio Papini;Valerio Vignoli;
Pages: 2084 - 2094 Abstract: We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Huiyuan Li;Jian-An Fang;Xiaofan Li;Leszek Rutkowski;Tingwen Huang;
Pages: 2095 - 2107 Abstract: This paper deals with global synchronization problem of multiple discrete-time Markovian jump memristor-based neural networks (DTMJMNNs) with mixed mode-dependent delays via a novel event-triggered impulsive coupling control (ETICC). The parameters of the multiple DTMJMNNs and the mixed time delays (both discrete and distributed delays) switch randomly according to a Markov chain. In the ETICC strategy, the controller does not work all the time, but only works at impulse instants determined by specific events. In particular, the coupling matrix can be non-Laplacian. By using the Lyapunov stability theory, linear matrix inequalities (LMIs), and the Kronecker product, some sufficient conditions for global synchronization of multiple DTMJMNNs under the event-triggered strategy are derived. Two examples are presented to test the validity of the theoretical analysis results. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Hui Li;Yonggui Kao;Yangquan Chen;
Pages: 2108 - 2116 Abstract: The stability of fractional-order (FO) nonlinear system with state-dependent delays (SDDs) is investigated. Unlike the usual time-dependent delays, the state-dependent (SD) delays make the size of the delays relative to the states, which makes the system uncertain when historical state information would be used. A Lemma on Riemann-Liouville derivative is first given to ensure the monotonicity of the considered function. Then, based on the Lyapunov method, several sufficient criteria are presented to guarantee the Mittag-Leffler stability of the discussed systems. In the end, three examples are applied to illustrate the correctness and applicability of our theoretical conclusions, including practical applications in submarine positioning models. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Salwa Echalih;Abdelmajid Abouloifa;Ibtissam Lachkar;Zineb Hekss;Abdelali El Aroudi;Fouad Giri;Mohammed S. Al-Numay;
Pages: 2117 - 2128 Abstract: This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Diego Luis González;Lorenzo Grassi;Alberto U. G. Maurizi;
Pages: 2129 - 2141 Abstract: A new nonlinear circuit with frequency locking capability in the case of a generic quasi-periodic input, is presented. Due to this capability the circuit is called a Quasi-Periodic Locked Loop (Q-PLL). The locked frequency is parametrically selected from among those prescribed by the theory of resonances in dynamical systems. In particular, the locked frequency forms a three-frequency resonance with the frequencies of the quasi-periodic input. The circuit is able to lock also in case of deterministic perturbation (additional frequency components) and stochastic perturbation (wide-band noise). The circuit is closely related to the pitch perception of complex sound in humans and, as such, can be considered a bio-inspired device. From the point of view of applications, it may be considered as an extension of the Phase Locked Loop (PLL) with the additional ability of locking simultaneously to more than one frequency. Due to the dynamical and structural robustness of the locked states, the Q-PLL represents a tangible advance for the development of specific applications, for example, in medicine (hearing aids, and cochlear implants), in robotics (artificial senses), and in industrial and consumer electronics (improvement of speech intelligibility, pitch-based processing, etc.). PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Florian Klemme;Hussam Amrouch;
Pages: 2142 - 2155 Abstract: To ensure the correct functionality of a chip throughout its entire lifetime, preliminary circuit analysis with respect to aging-induced degradation is indispensable. However, state-of-the-art techniques only allow for the consideration of uniformly applied degradations, despite the fact that different workloads will lead to different degradations due to their distinct induced activities. This imposes over-pessimism when estimating the required timing guardbands, resulting in an unnecessary loss of performance and efficiency. In this work, we propose an approach that takes real-world workload dependencies into account and generates workload-specific aging-aware standard cell libraries, allowing for accurate analysis of aging-induced degradations. We employ machine learning techniques to overcome infeasible simulation times for individual transistor aging while sustaining high prediction accuracy. We also demonstrate scalability to previously unknown workloads and discuss multiple approaches to estimate the machine learning accuracy by employing coverage metrics. In our evaluation, we achieve predictions of workload-dependent aging-aware standard cells with an average accuracy (R2 score) of 95.28%. Using predicted cell libraries in static timing analysis, timing guardbands for multiple circuits are reported with an error of less than 0.1% on average. We demonstrate that timing guardband requirements can be reduced by up to 30% when considering specific workloads over worst-case estimations as performed in state-of-the-art tool flows. Even for unknown workloads of different circuits, accurate prediction with relative errors below 1% can be achieved. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Ilya Kiselev;Chang Gao;Shih-Chii Liu;
Pages: 2156 - 2166 Abstract: Including local automatic gain control (AGC) circuitry into a silicon cochlea design has been challenging because of transistor mismatch and model complexity. To address this, we present an alternative system-level algorithm that implements channel-specific AGC in a silicon spiking cochlea by measuring the output spike activity of individual channels. The bandpass filter gain of a channel is adapted dynamically to the input amplitude so that the average output spike rate stays within a defined range. Because this AGC mechanism only needs counting and adding operations, it can be implemented at low hardware cost in a future design. We evaluate the impact of the local AGC algorithm on a classification task where the input signal varies over 32dB input range. Two classifier types receiving cochlea spike features were tested on a speech versus noise classification task. The logistic regression classifier achieves an average of 6% improvement and 40.8% relative improvement in accuracy when the AGC is enabled. The deep neural network classifier shows a similar improvement for the AGC case and achieves a higher mean accuracy of 96% compared to the best accuracy of 91% from the logistic regression classifier. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Haihua Guo;Jian Liu;Choon Ki Ahn;Yongbao Wu;Wenxue Li;
Pages: 2167 - 2178 Abstract: This study proposes a novel dynamic event-triggered impulsive control (ETIC) scheme to study the exponential stabilization of general stochastic nonlinear systems, where the impulsive sequence is determined by a dynamic event-triggered mechanism. The dynamic ETIC can effectively reduce controller updates and significantly save energy under the same decay rate compared to traditional static event-triggered impulsive generators. Additionally, there is a guaranteed positive minimum inter-event time for each sample path solution of systems. Furthermore, the proposed dynamic ETIC scheme is employed to stabilize stochastic complex networks based on the graph theory and the Lyapunov method. Finally, we provide two illustrative examples to verify the effectiveness and correctness of the proposed dynamic ETIC scheme. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Hui Li;Yungang Liu;Fengzhong Li;
Pages: 2179 - 2192 Abstract: This paper investigates global stabilization via adaptive event-triggered output feedback for a class of uncertain nonlinear systems. Typically, unknown polynomial-function rate is admitted in the unmeasurable-state dependent growth of the systems. This calls for an advanced compensation strategy based on dynamic high gain, which in turn requires more intelligent execution in the event-triggered control architecture. To this end, a novel event-triggering mechanism is designed with two events separately evaluating the behaviors of dynamic gain and the controller signal. Particularly, the event on controller signal is enforced to suspend for a certain time after each execution to guarantee a positive lower bound for the inter-execution intervals. More importantly, the suspension time and the threshold therein are both online adjusted according to dynamic gain (rather than pre-specified), which could become small enough as the dynamic gain increases. This ensures timely execution for the effectiveness of adaptive compensation. Then, with the dynamic gain delicately designed to counteract the influence of the execution error, an event-triggered controller via adaptive output feedback is proposed to make the original system states and observer states converge to zero. Further attempt is performed for more efficient resource saving and disturbance tolerance. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Li Tang;Xin-Yu Zhang;Yan-Jun Liu;Shaocheng Tong;
Pages: 2193 - 2202 Abstract: In this paper, a class of flexible riser systems modeled by partial differential equations (PDEs) with the backlash is considered. The backlash is formulated as the addition of a linear input and a interference-like term, then an new auxiliary item is introduced to compensate for the impact of this backlash. In addition, the constraint problem for the position and the velocity is also taken into consideration. To solve this constrain problem, the logarithmic barrier Lyapunov function is employed. For the flexible riser system, two kinds of adaptive controllers are proposed under the following two cases. One controller is designed when only the parameter of backlash is unknown. On the basis of this result, the other controller is presented when some system parameters cannot be measured through actual measurement. Then, combing the theory of Lyapunov stability, the two controllers can guarantee the boundedness of all signals in the closed-loop flexible riser system. Further, both the position and the velocity satisfy their corresponding constraint condition. Finally, the simulation example verifies that the proposed control method is effective. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Carlo Condo;
Pages: 2203 - 2211 Abstract: Guessing Random Additive Noise Decoding (GRAND) is a universal decoding algorithm that has been recently proposed as a practical way to perform maximum likelihood decoding. It generates a sequence of possible error patterns and applies them to the received vector, checking if the result is a valid codeword. Ordered reliability bits GRAND (ORBGRAND) improves on GRAND by considering soft information received from the channel. Both GRAND and ORBGRAND have been implemented in hardware, focusing on average performance, sacrificing worst case throughput and latency. In this work, an improved pattern schedule for ORBGRAND is proposed. It provides $> 0.5$ dB gain over the standard schedule at a block error rate $le 10^{-5}$ , and outperforms more complex GRAND flavors with a fraction of the complexity. The proposed schedule is used within a novel code-agnositic decoder architecture: the decoder guarantees fixed high throughput and low latency, making it attractive for latency-constrained applications. It outperforms the worst-case performance of decoders by orders of magnitude, and outperforms many best-case figures. Decoding a code of length 128, it achieves a throughput of 79.21 Gb/s with 58.49 ns latency, yielding better energy efficiency and comparable area efficiency with respect to the state of the art. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Di Luo;Yuan Gao;Philip K. T. Mok;
Pages: 2212 - 2224 Abstract: This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $mu text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Taejoo Oh;Taejun Lim;Yongshik Lee;
Pages: 2225 - 2234 Abstract: In this paper, self-matching rectifiers for enhanced input dynamic range are demonstrated. The method is based on an artificial transmission line, which consists of a stepped-impedance transmission line loaded with shunt varactors. The output DC voltage of the rectifier is fed back to the varactors to control the effective electrical length and characteristic impedance of the line. Because this bias voltage changes as the power input to the rectifier changes, a matching network that maintains impedance matching regardless of the input power can be developed without additional circuits, thus substantially improving the input dynamic range. The experimental results for prototype rectifiers show a dynamic range as wide as 25 dB with only a single Schottky diode, an improvement of 11 dB over the rectifier with a conventional matching scheme, in which the conversion efficiency remains above 50%. The effectiveness of the proposed method is also verified with the experimental results for rectennas based on the demonstrated rectifiers. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Fabio Corti;Antonino Laudani;Gabriele Maria Lozito;Alberto Reatti;Alessandro Bartolini;Lorenzo Ciani;
Pages: 2235 - 2245 Abstract: A model-based strategy for an efficient power supply control used in a wireless sensor network is presented. The strategy, based on Pulse-Skipping Modulation, regulates the current charging a battery, delivered by a photovoltaic source, resulting in an accurate current regulation and highly efficient power management. The strategy is implemented on a microcontroller unit and compensates for the microcontroller self-absorbed current. The modulation signal is generated through a full software interface, reducing the requirement for external components. Experimental validations, performed on a charger prototype by using a laboratory photovoltaic device simulator, proved that both regulation accuracy, regulation resolution and converter efficiency achieved are superior to the classic Pulse-Width Modulation. The approach results in a simple practical implementation, carries over the advantages of an up-to-date model for the photovoltaic device, and serves the auxiliary purpose of using the photovoltaic source as an instantaneous solar irradiance sensor. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Pages: 2246 - 2246 Abstract: Advertisement: This publication offers open access options for authors. IEEE open access publishing. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Pages: 2247 - 2247 Abstract: Advertisement: TechRxiv is a free preprint server for unpublished research in electrical engineering, computer science, and related technology. TechRxiv provides researchers the opportunity to share early results of their work ahead of formal peer review and publication. Benefits: Rapidly disseminate your research findings; Gather feedback from fellow researchers; Find potential collaborators in the scientific community; Establish the precedence of a discovery; and Document research results in advance of publication. Upload your unpublished research today! PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Pages: 2248 - 2248 Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Hybrid journal (It can contain Open Access articles)
