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- IEEE Transactions on Circuits and Systems--I: Regular Papers Publication
Information-
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Pages: C2 - C2
Abstract: null
PubDate:
WED, 31 JUL 2024 09:18:16 -04
Issue No: Vol. 71, No. 8 (2024)
- IEEE Circuits and Systems Society Information
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Pages: C3 - C3
Abstract: null
PubDate:
WED, 31 JUL 2024 09:18:16 -04
Issue No: Vol. 71, No. 8 (2024)
- A Fully Integrated Dual-Output Continuously Scalable-Conversion-Ratio SC
Converter for Battery-Powered IoT Applications-
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Authors:
Taehyeong Park;Hyunjin Kim;Mingi Jeong;Inho Park;Chulwoo Kim;
Pages: 3463 - 3475
Abstract: This paper proposes a fully integrated dual-output continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) converter that increases the overall power conversion efficiency (PCE) beyond that of the conventional dual-output SC converters. The structure employs proposed dual-output CSCR SC stage and channel SC stage to transfer charges to two output load voltages ( $V_{\mathrm {OUT}}$ s) with high PCE. Also, the converter is controlled by analog switching frequency modulation (ASFM) and digital flying capacitance modulation (DFCM) loops to regulate both $V_{\mathrm {OUT}}$ s simultaneously. The proposed converter is fabricated using a 180 nm CMOS process, and regulates $V_{\mathrm {OUT}}$ of 1.1–1.6 V and 0.55–0.95 V with an input voltage of 1.5–1.9 V. In measurement, the proposed converter achieves a maximum PCE of 85%, and an average PCE of 78.6% for the available $V_{\mathrm {OUT}}$ ranges. Moreover, the converter exhibits the maximum $I_{\mathrm {OUT}}$ s of 21 mA and 4 mA, respectively.
PubDate:
WED, 22 MAY 2024 09:16:53 -04
Issue No: Vol. 71, No. 8 (2024)
- A Power-Efficient Autonomous Current Adaptation ADC Input Driver
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Authors:
Zu-Jia Lo;Tzu-Heng Hsu;Hsiu-Min Yang;Xiu-Zhu Li;Wei-Zhi Lai;Ren-Yong Hung;Yun-Jie Huang;Sheng-Yu Peng;
Pages: 3476 - 3488
Abstract: This paper presents a power-efficient autonomous current adaptation input driver (ACAID) for analog-to-digital converters (ADCs), which employs floating-gate transistors to provide reconfigurability. The proposed ACAID autonomously increases the supply current at the onset of the tracking phase, achieving a high slew rate. As the driver output voltage gradually follows the input signal in the RC-settling or hold phase, the supply current successively diminishes back to the original low quiescent level. The required sensing and actuating circuits for current adaptation are inherent components in the adopted capacitive feedback topology. A prototype version of the proposed ACAID has been designed and fabricated in a $0.35\thinspace \mu {\mathrm { m}}$ CMOS process, along with integrated charge programming circuits and a 10-bit successive approximation register ADC. With $0.5\thinspace {\mathrm { pF}}$ sampling capacitors loading the driver, the proposed ACAID achieves $-70.1\thinspace {\mathrm { dB}}$ total harmonic distortion (THD) with a $100\thinspace {\mathrm { kHz}}$ input signal with $2.8V_{\mathrm { pp}}$ amplitude. When connected to an on-chip ADC with a $200\thinspace {\mathrm { kHz}}$ sampling rate, the measured effective number of bits (ENoB) near the Nyquist rate is 9.1. The proposed ACAID saves more power as the input frequency increases or when the portion of the tracking period reduces. The prototyped driver circuit can save 49.5% power consumption when the input frequency is $100\thinspace {\mathrm { kHz}}$ with a 10% duty cycle for tracking. The power-saving ratio can be up to 76.2% when the sampling rate increases to $1\thinspace {\mathrm { MHz}}$ .
PubDate:
TUE, 04 JUN 2024 09:18:38 -04
Issue No: Vol. 71, No. 8 (2024)
- An 11uW, 0.08 mm2, 125dB-Dynamic-Range Current-Sensing Dynamic CT Zoom ADC
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Authors:
Yizhak Shifman;Joseph Shor;
Pages: 3489 - 3501
Abstract: A Dynamic Continuous-Time Zoom-ADC current to digital converter for bio-sensing applications is presented, comprising a current DAC (IDAC), a loop filter, a comparator, and loop logic. Within the IDAC, a reference voltage is driven to resistor legs, obtaining an accurate current with high Rout. A $1^{\mathrm {st}}$ order loop filter utilizes an inherently linear, zero-static-power, passive integrator. An isolation of the integrator from external sensor capacitance is obtained by a cascode transistor, enabling the use of the passive integrator. During the Zoom’s SAR phase, a binary search detects the approximate signal level and provides zoomed references for the Sigma-Delta phase, where fine conversion is performed. The dynamic mode tracks the comparator output data to determine when the input signal is close to the references and updates them accordingly. This paper is the first to propose a dynamic zoom ADC which utilizes a single DAC. An over-voltage detector detects integrator voltages exceeding the supply level, a result of high input currents, and prevents damage to the circuit. A 65nm implementation achieved a competitive dynamic range of 125dB, an SNR of 91dB and an FoM of 192dB. The design occupies 0.08 mm2, and a state-of-the-art power consumption of 11.4uW was measured. The dynamic mode supports up to 78Hz inputs, and an SFDR of 90.4dB was measured.
PubDate:
WED, 05 JUN 2024 09:18:59 -04
Issue No: Vol. 71, No. 8 (2024)
- Lumped-Distributed Resonators Providing Multiple Transmission Zeros in
Bandpass Filters With Simple and Mixed Couplings-
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Authors:
Alexander V. Zakharov;Sergii M. Litvintsev;
Pages: 3502 - 3513
Abstract: The article proposes three lumped-distributed resonators, each of which introduces two transmission zeros (TZ) at real frequencies into the transfer function of inline bandpass filter (BPF). The use of such resonators in mixed-coupled BPFs without cross-coupling increases the number of TZs from ( $N + 1$ ) to ( $3N + 1$ ). It improves the filter performance. Lumped-distributed resonators represent a stepped-impedance or uniform transmission line segment to which one capacitance or inductance is connected in cascade. These resonators have two antiresonant frequencies $\omega _{p1}$ , $\omega _{p2}$ , which are placed next to the main resonant frequency $\omega _{0}$ , which leads to two TZs. Antiresonant frequencies $\omega _{p1}$ , $\omega _{p2}$ are the poles of the input admittance $Y(j\omega)$ , their position is controlled by the parameters of the resonators. Lumped-distributed resonators can form equidistant TZ pairs, including those of higher degree, allowing the implementation of BPFs with quasielliptic frequency responses and improved selectivity. It has been established that reducing Q-factors of inductor $Q_{L}$ and capacitor $Q_{C}$ do not increase the insertion loss in the passband of BPF. A design method for BPF with mixed couplings between adjacent resonators is established. It is also suitable for filters that use the proposed resonators. As result, the TZ number of such BPFs is increased from ( $N$ + 1) to ( $3N + 1$ ).
PubDate:
MON, 25 MAR 2024 09:20:41 -04
Issue No: Vol. 71, No. 8 (2024)
- Memristor-Based Neural Network Circuit of Operant Conditioning With
Bridging and Conditional Reinforcement-
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Authors:
Junwei Sun;Yu Zhai;Peng Liu;Yanfeng Wang;
Pages: 3514 - 3525
Abstract: Most memristor-based neural network circuits consider only a single pattern of classical conditioning (CC) or operant conditioning (OC), but the simultaneous occurrence of CC and OC during actual animal training is ignored. In this paper, a memristor-based neural network circuit of operant conditioning with bridging and conditional reinforcement is designed. CC and OC can occur simultaneously and multiple CC and OC functions are considered. The designed circuit mainly consists of memory module, delay module, prefrontal cortex module, experience module and generalization module. Bridging in OC is implemented by the delay module and the prefrontal cortex module. Conditional reinforcement in OC is realized by the memory module and the prefrontal cortex module. Finally, the generalization of OC is achieved through the generalization module and the experience module. The proposed circuit may inform the study of smarter brain-like systems.
PubDate:
MON, 13 MAY 2024 09:16:37 -04
Issue No: Vol. 71, No. 8 (2024)
- Multi-Memristor Based Distributed Decision Tree Circuit for Cybersecurity
Applications-
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Authors:
Lei Zhang;Joseph Riem;Jingdi Chen;Henry Mackay;Tian Lan;Nathaniel D. Bastian;Gina C. Adam;
Pages: 3526 - 3537
Abstract: Cybersecurity at the edge requires fast computing in energy-constrained environments. Decision trees can provide an explainable solution for network intrusion detection with high detection accuracy at the packet level. However, their hardware implementation needs to support efficient real-time operation. In this paper, we propose a spatially distributed decision tree for network intrusion detection, using memristor-based chiplet leaves. Each chiplet processes an input by comparing it to a predefined boundary stored in the memristor cell and provides a binary output to select one of the interconnected leaves on the lower level, with an estimated power consumption in a 130nm node design of $389~\mu $ W. The delay is $2.5~\mu $ s for one inference decision. This chiplet approach is reconfigurable and in line with the natural architecture of decision trees. It also supports the prototyping with known good dies, overcoming the non-idealities challenge prevalent in memristor technologies. Our memristor-based decision trees show high intrusion detection accuracy of 82%, 84%, and 73% on the benchmark UNSW, CIC-IDS, and ACI-IoT datasets respectively, considering 6-bit device precision in one memristor vs. three memristor per boundary configurations. This distributed approach opens the way to utilizing memristor technology despite device defects for applications in need of local real-time computing.
PubDate:
THU, 23 MAY 2024 09:17:13 -04
Issue No: Vol. 71, No. 8 (2024)
- Toward Efficient System-on-Module for Design-Space Exploration of Analog
Spiking Neural Networks-
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Authors:
Moamen El-Masry;Thilo Werner;Amir Zjajo;Robert Weigel;
Pages: 3538 - 3549
Abstract: In this paper, we present an integrated system-on-module for design-space exploration of neurosynaptic behavior in non-volatile memory enhanced spiking neural networks. The system operates in locally-analog, globally-digital modus, facilitating the exploration and validation of both, individual computational components, and the characteristic spike-based features of neurosynaptic arrays. The key advantage of the system lies in its reconfigurable, adaptable, and interchangeable components, which enable precise and reproducible firing patterns. By leveraging these capabilities, various aspects of neurosynaptic behavior can be examined and manipulated. To enhance the weight retention mechanism, the platform incorporates embedded resistive-RAM, ensuring the preservation of synaptic weights. This integration further supports the accurate representation and processing of synaptic information. Experimental results in 28 nm CMOS technology demonstrate the feasibility and effectiveness of the proposed methodology in characterizing spiking neural network components.
PubDate:
THU, 06 JUN 2024 09:17:27 -04
Issue No: Vol. 71, No. 8 (2024)
- A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS
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Authors:
Minkyo Shim;Seungha Roh;Yunhee Lee;Jung-Woo Sull;Deog-Kyoon Jeong;Kwanseo Park;
Pages: 3550 - 3560
Abstract: This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts a $\beta $ detector to achieve a unique locking point that resolves the dead-zone problem caused by the combination of the conventional baud-rate PD and adaptive decision feedback equalizer (DFE). The APS CDR is configured with a sign-sign minimum mean squared error (SS-MMSE) PD and an addition of a digital coefficient which is adaptively controlled through the $\beta $ detector by detecting pre-cursor inter-symbol interference (ISI) dependency of 1-level transitions. Therefore, the proposed CDR does not rely on external coefficients. Furthermore, adaptive programmable gain amplifiers (PGAs) and DFE are implemented with the APS CDR to compensate the pre and post-cursor ISIs, and main-cursor level. Since the adaptive equalizers and the APS CDR share the error samplers, no additional analog hardware is required. Fabricated in 28-nm CMOS technology, a prototype PAM-4 RX operates at 50 Gb/s and occupies an active area of 0.16 mm2. The RX tested over a 25.3-dB loss channel achieves a bit error rate (BER) of less than $10^{-12}$ and energy efficiency of 2.52 pJ/b.
PubDate:
WED, 01 MAY 2024 09:16:27 -04
Issue No: Vol. 71, No. 8 (2024)
- A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS
Exploiting Noise Cancellation and Current Reuse-
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Authors:
Zhe Liu;Chirn Chye Boon;Yangtao Dong;
Pages: 3561 - 3572
Abstract: This paper proposes an inductorless wideband common-gate (CG)-common-source (CS) noise-cancelling (NC) low-noise amplifier (LNA) with current reuse (CR) for ultra-low voltage (ULV) application. In the conventional NC LNA with CR, to reuse the DC current of the auxiliary amplifier, three transistors are stacked in a single branch, leading to a reduced voltage headroom. Moreover, additional inductor and capacitors are required, resulting in a large silicon area. In the proposed work, the DC current of the auxiliary amplifier can be reused without using any inductor. Meanwhile, only two transistors are stacked in a single branch, making it suitable for ULV application. Fabricated in 28 nm CMOS, this work exhibits a voltage gain of 20 dB with a 3-dB bandwidth of 0.2 to 2.85 GHz, a minimum NF of 2.9 dB at 1.7 GHz and an IIP3 of -12.3 dBm at 1 GHz. It consumes 1.74 mW from a 0.6 V supply and occupies a very compact die area of 0.0048 mm2.
PubDate:
FRI, 14 JUN 2024 09:16:53 -04
Issue No: Vol. 71, No. 8 (2024)
- 28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil
Transformer and Dual-Feedforward Techniques for Phased Array Systems-
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Authors:
Xiangrong Huang;Haikun Jia;Wei Deng;Zhihua Wang;Baoyong Chi;Ziqiang Wang;
Pages: 3573 - 3583
Abstract: This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and electrical-magnetic (EM) dual-feedforward techniques are proposed to improve the LNA’s noise performance and reduce the chip area. Design procedures targeting compact chip area, low noise, and high gain are provided. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3 dB bandwidth (BW) from 25.6 to 29.9 GHz, and −12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW power consumption. The second LNA employs the current-reuse topology based on the first LNA, which reduces the power consumption to 3.6 mW at the cost of 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65 nm CMOS process. The two LNAs have the same $200~\mu $ m $\times 300~\mu $ m core chip area. To the best of our knowledge, the first LNA shows the lowest NF and smallest core area at 28 GHz compared with the published CMOS works in a similar frequency range.
PubDate:
THU, 23 MAY 2024 09:17:13 -04
Issue No: Vol. 71, No. 8 (2024)
- Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the
Analytic Role-Exchange Doherty-Chireix Continuum Theory-
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Authors:
Yuhan Zheng;Patrick Roblin;
Pages: 3584 - 3596
Abstract: A novel theory and design methodology for continuous-mode dual-input outphasing amplifiers (CM-OPA) is proposed to enhance the bandwidth of mixed-mode Chirex PAs. The design procedure relies on a modified analytical role-exchange Doherty-Chireix continuum theory which doubles the design space for the realization of high-efficiency PAs with a mode of operation continuously changing between the Chireix mode and two role-exchange hybrid Doherty-Chireix outphasing modes as the frequency varies up and down, respectively. Using this theory, a mixed-mode CM-OPA with constant output power back-off level and constant saturated power is developed. The CM-OPA theory is first verified at the current-source reference planes for a frequency range from 1.3 GHz to 2.0 GHz for a GaN HEMT. The proposed CM-OPA is then implemented at the package reference planes using the embedding model to synthesize the combiner circuit across the entire frequency bandwidth. The 1.3 to 2.0 GHz bandwidth-enhanced CM-OPA was fabricated and characterized using both continuous-wave and modulated signals. When driven by a 20-MHz LTE signal with 7.1 dB peak-to-average-power ratio (PAPR), the proposed CM-OPA achieves better than -45 dBc adjacent channel leakage ratio (ACLR) and higher than 44% power-added efficiency (PAE) after digital predistortion linearization at 1.3/1.6/1.8 GHz.
PubDate:
WED, 05 JUN 2024 09:18:59 -04
Issue No: Vol. 71, No. 8 (2024)
- Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low
Reference Spur-
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Authors:
Hao Xu;Shujiang Ji;Yizhuo Wang;Xinyi Lin;Hao Min;Na Yan;
Pages: 3597 - 3607
Abstract: This paper presents an analog low-power sub-sampling phase locked loop (PLL) that tackles the reference spur caused by VCO load modulation from the sub-sampling operation. A complete analysis on the binary frequency shift keying (BFSK) effect including the impact of the VCO buffer is provided, followed by practical design guide that achieves the optimum spur/jitter trade-off. The proposed sub-sampling phase detector incorporates an active primary-secondary architecture for improved isolation to suppress the load modulation. The adaptive frequency locked loop (FLL) consumes zero power in the locked state and activates itself once unlocking is detected. The sub-sampling PLL is fabricated in a 40nm CMOS process. It achieves -121.5dBc/Hz phase noise at 1MHz offset frequency and an RMS jitter of 185fs integrated from 10k to 10MHz. The power dissipation is 1.14mW at 0.95V supply with a -254.1dB figure-of-merit. The proposed phase detector results in -73dBc reference spur that is among the lowest in state-of-art works.
PubDate:
WED, 03 APR 2024 09:16:34 -04
Issue No: Vol. 71, No. 8 (2024)
- Frequency-Transformation-Based Co-Designed
Lowpass-Single/Multi-Passband-Highpass RF Filters-
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Authors:
Roberto Gómez-García;Li Yang;Mohamed Malki;José-María Muñoz-Ferreras;
Pages: 3608 - 3621
Abstract: The theoretical design and practical development of RF analog filtering devices with co-integrated lowpass, single $\boldsymbol {/}$ multi-band bandpass, and highpass transfer functions is reported. For this purpose, two different classes of generalized frequency transformation that convert the equivalent normalized lowpass filter prototype into the desired RF filter with several co-designed filtering actions are proposed. They realize a frequency mapping of the reactance of a normalized unitary capacitor into that of a one-port single $/$ multi-resonance cell with added lowpass and highpass filtering capabilities. For these devised frequency transformations, the theoretical foundations and various illustrative filter examples designed at the ideal-circuit-model level are presented. In addition, higher-selectivity filter architectures based on the generation of additional out-of-band transmission zeros (TZs) by means of cross-coupling techniques are shown. Afterwards, the extension of this design methodology to RF multi-functional filtering components, such as input-reflectionless $\boldsymbol {/}$ absorptive filters based on complementary-diplexer circuit networks and two-way filtering power-distribution circuits, is also demonstrated. Furthermore, two design examples of distributed-element and inverterless lumped-element RF filters are provided. Besides, for the distributed-element circuit, a proof-of-concept microstrip prototype is manufactured and measured as experimental validation.
PubDate:
MON, 08 APR 2024 09:18:49 -04
Issue No: Vol. 71, No. 8 (2024)
- Analysis and Design of Integrated Quadrature Balanced N-Path Transceivers
for Frequency Division Duplex Systems-
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Authors:
Erez Zolkov;Nimrod Ginzberg;Avi Lax;Emanuel Cohen;
Pages: 3622 - 3635
Abstract: We present a fully integrated and tunable transceiver for frequency-division duplex (FDD) and half duplex (HD) operation based on a quadrature balanced N-path mixer-first receiver (MFRX) architecture. The quadrature balanced N-path transceiver (QBNT) comprises a quadrature hybrid (QH) and two identical MFRXs, presenting a short circuit and a matched impedance at the transmitter (TX) and receiver (RX) bands, respectively. The proposed transceiver achieves low TX to antenna loss while maintaining high RX linearity, and is capable of cancelling both TX noise and reciprocal mixing (RM) at the RX under antenna voltage standing wave ratio (VSWR) variations. Analysis and design equations of the QBNT are shown, and the design considerations of each block are presented. A channel estimation algorithm is proposed to cope with the frequency-dependant antenna reflection QH response. An integrated QBNT prototype was fabricated in TSMC 65nm CMOS process as a proof of concept, occupying an active area of $2.96 mm^{2}$ . The QBNT operates at the frequency range between 0.75-2 GHz with a TX-RX offsets above 200 MHz. It achieves RX noise figure (NF) of 2.8-5.8 dB, RXB1dB of 18 dBm, TX-ANT OIP3 of 27.3 dBm and 29.5 dBm in FDD and HD modes, respectively. The demonstrated FDD operation of the QBNT shows that in our implementation we achieve a simultaneous 6.5 dBm TX output power and an RX EVM of −40.8 dB after digital cancellation. The RX and TX (at OP1dB) consume DC power of 82–130 mW and 254 mW, respectively.
PubDate:
WED, 08 MAY 2024 09:16:44 -04
Issue No: Vol. 71, No. 8 (2024)
- A Subthreshold Adaptive-Reference Leakage- Compensation Sensing Scheme for
3D PCM With Enhanced Sensing Margin and Endurance-
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Authors:
Qiuyao Yu;Yu Lei;Qian Wang;Houpeng Chen;Zhitang Song;
Pages: 3636 - 3646
Abstract: 3D phase-change memory (3D PCM) is one of the primary candidates for next-generation memory technologies. To enhance its endurance, a subthreshold read operation has been proposed. However, this operation exhibits extremely low read currents, which are further compromised by a considerable amount of leakage currents, thereby deteriorating the sensing margin. To address this challenge, this paper proposes a subthreshold adaptive-reference leakage-compensation sensing scheme for 3D PCM. The reference current is address-adaptive, and the leakage current is sampled and compensated accurately. Evaluation results demonstrate significant improvements in the proposed circuit. The sensing margin is increased by up to 46.7% and 34.7% across different half-selected cell statuses and addresses, respectively, compared to the conventional leakage-compensation sensing scheme. Moreover, the read endurance is increased by $51\times $ , compared to the conventional read operation.
PubDate:
MON, 24 JUN 2024 09:16:22 -04
Issue No: Vol. 71, No. 8 (2024)
- Optimization of Quantum Circuits for Stabilizer Codes
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Authors:
Arijit Mondal;Keshab K. Parhi;
Pages: 3647 - 3657
Abstract: Quantum computing is an emerging technology that has the potential to achieve exponential speedups over their classical counterparts. To achieve quantum advantage, quantum principles are being applied to fields such as communications, information processing, and artificial intelligence. However, quantum computers face a fundamental issue since quantum bits are extremely noisy and prone to decoherence. Keeping qubits error free is one of the most important steps towards reliable quantum computing. Different stabilizer codes for quantum error correction have been proposed in past decades and several methods have been proposed to import classical error correcting codes to the quantum domain. Design of encoding and decoding circuits for the stabilizer codes have also been proposed. Optimization of these circuits in terms of the number of gates is critical for reliability of these circuits. In this paper, we propose a procedure for optimization of encoder circuits for stabilizer codes. Using the proposed method, we optimize the encoder circuit in terms of the number of 2-qubit gates used. The proposed optimized eight-qubit encoder uses 18 CNOT gates and 4 Hadamard gates, as compared to 14 single qubit gates, 33 2-qubit gates, and 6 CCNOT gates in a prior work. The encoder and decoder circuits are verified using IBM Qiskit. We also present encoder circuits for the Steane code and a 13-qubit code, that are optimized with respect to the number of gates used, leading to a reduction in number of CNOT gates by 1 and 8, respectively.
PubDate:
WED, 17 APR 2024 09:16:47 -04
Issue No: Vol. 71, No. 8 (2024)
- A Computing In-Memory Multibit Multiplication Based on Decoupling and
In-Array Storing-
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Authors:
Jin Zhang;Zhongzhen Tong;Hao Wang;Xin Wang;Qiang Zhao;Jian Zhou;Jiaqun Wang;Zhiting Lin;Xiulong Wu;
Pages: 3658 - 3671
Abstract: Multiplications are basic operations of neural networks. Therefore, multiplication results are crucial in analyzing the operating process of neural networks. However, the multiplication strategies are generally based on analog-domain circuits, and the results are in a multiply-and-accumulate (MAC) form. The result of each multiplication in MAC cannot be distinguished accurately using these strategies. Therefore, we proposed an in-memory multibit multiplication based on the decoupling and in-array storage strategy to overcome this problem, and the core module is the 10T1C SRAM cell. Multibit multiplications are decoupled by a series of logical operations. Therefore, in the analysis mode, multiplication results can be saved and outputted in the normal read mode without requiring additional storage. When executing the neural network, the operation results are stored in the cells. Hence, the operands stored in the array are retained. Accumulation operations are completed based on the charge-sharing technology; thus, the linearity of accumulation is high. We simulated and analyzed the performance of the proposed circuit in a 28 nm CMOS process. The absolute value of integral nonlinearity is at most 0.29. Further, due to high data operation parallelism, the throughputs of the logical operation and MAC are up to 6307.8 and 802.8 GOPS, respectively.
PubDate:
THU, 22 FEB 2024 09:19:14 -04
Issue No: Vol. 71, No. 8 (2024)
- A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b
Binary Searching ADCs for Processing Quantized Neural Networks-
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Authors:
Chengshuo Yu;Haoge Jiang;Junjie Mu;Kevin Tshun Chuan Chai;Tony Tae-Hyoung Kim;Bongjin Kim;
Pages: 3672 - 3682
Abstract: This article presents a novel dual 7T static random-access memory (SRAM)-based compute-in-memory (CIM) macro for processing quantized neural networks. The proposed SRAM-based CIM macro decouples read/write operations and employs a zero-input/weight skipping scheme. A 65nm test chip with $528\times 128$ integrated dual 7T bitcells demonstrated reconfigurable precision multiply and accumulate operations with $384\times $ binary inputs (0/1) and $384\times 128$ programmable multi-bit weights (3/7/15-levels). Each column comprises $384\times $ bitcells for a dot product, $48\times $ bitcells for offset calibration, and $96\times $ bitcells for binary-searching analog-to-digital conversion. The analog-to-digital converter (ADC) converts a voltage difference between two read bitlines (i.e., an analog dot-product result) to a 1-6b digital output code using binary searching in 1-6 conversion cycles using replica bitcells. The test chip with 66Kb embedded dual SRAM bitcells was evaluated for processing neural networks, including the MNIST image classifications using a multi-layer perceptron (MLP) model with its layer configuration of 784-256-256-256-10. The measured classification accuracies are 97.62%, 97.65%, and 97.72% for the 3, 7, and 15 level weights, respectively. The accuracy degradations are only 0.58 to 0.74% off the baseline with software simulations. For the VGG6 model using the CIFAR-10 image dataset, the accuracies are 88.59%, 88.21%, and 89.07% for the 3, 7, and 15 level weights, with degradations of only 0.6 to 1.32% off the software baseline. The measured energy efficiencies are 258.5, 67.9, and 23.9 TOPS/W for the 3, 7, and 15 level weights, respectively, measured at 0.45/0.8V supplies.
PubDate:
FRI, 21 JUN 2024 09:17:03 -04
Issue No: Vol. 71, No. 8 (2024)
- Hybrid Spatial and Temporal Computing Histogrammer in Soft Processor Core
of a FPGA Device-
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Authors:
Enrico Ronconi;Fabio Garzetti;Nicola Lusardi;Andrea Costa;Angelo Geraci;
Pages: 3683 - 3694
Abstract: Multi-channel data management is crucial in a world where big data processing is extensively used in research and business. Histogramming is a common technique employed to detect, analyze, and store enormous volumes of data in real-time, making it useful for industrial applications in fields such as biology, chemistry, medical imaging, and spectroscopy. Due for them programming simplicity and low-cost large amount of memory, general-purpose temporal computing processors are commonly used, but they lack the ability to perform parallel computation at high-performance. Field-Programmable Gate Array (FPGA) is a powerful parallel computing solution proposed by both the scientific and industrial worlds, but it is equipped with little memory for these applications. Thus, a hybrid spatial/temporal computing histogram generator has been proposed, which uses a low-area multi-channel histogramming engine in programmable logic which is expanded thanks to an external Double Data Rate Synchronous Dynamic Random Access Memory (DDR) driven by a MicroBlaze Soft Processor Core. The proposed system has been validated on a Xilinx 28-nm 7-Series Artix-7 XC7A100T FPGA hosted on a Nexys4 Evaluation Board. Thanks to this hybrid solution, up to 128 channels can handle in a low-end FPGA occupies 207 LUTs and 325 flip-flops per channel plus a total 630 kb of total BRAM shared between all channels; a power consumption of 10.1 mW per channel is measured.
PubDate:
TUE, 04 JUN 2024 09:18:39 -04
Issue No: Vol. 71, No. 8 (2024)
- A Real-Time Sparsity-Aware 3D-CNN Processor for Mobile Hand Gesture
Recognition-
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Authors:
Seungbin Kim;Jueun Jung;Kyuho Jason Lee;
Pages: 3695 - 3707
Abstract: A sparsity-aware 3D-convolution neural network (3D-CNN) accelerator is proposed for the real-time mobile hand gesture recognition (HGR) system. The complex computation of 3D-convolution with the video data makes it difficult for real-time operation, especially in a resource-constrained mobile platform. To facilitate real-time implementation of HGR, this paper proposes three key features: 1) Spatio-temporal Variation Encoding and Inter-frame Differential Aware Network for highly sparse and lightweight network, reducing 94.03% parameters with only 2.57% accuracy loss on NvGesture dataset; 2) the ROI-only Computation architecture for utilizing activation sparsity to reduce the number of MAC operations and the external memory bandwidth by 84.3% and 72.3%, respectively; 3) Weight Sparsity-aware PE and Sparsity-distribution-aware Workload Allocation speed up the inference by $19.8\times $ . As a result, the low-latency 3D-CNN accelerator utilizes both activation and weight sparsity with data mapping to maximize the reusability of 3D-CNN, achieving $31\times $ faster inference than the state-of-the-art. The proposed processor is designed in 65 nm CMOS technology. It consumes 35 mW of power and achieves 46.25 TOPS/W of energy efficiency. As a result, the system realized 1.584 ms inference latency for real-time HGR in a mobile platform.
PubDate:
TUE, 11 JUN 2024 09:17:48 -04
Issue No: Vol. 71, No. 8 (2024)
- Energy Efficient Memristive Transiently Chaotic Neural Network for
Combinatorial Optimization-
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Authors:
Han Bao;Pengyu Ren;Kehong Xu;Ling Yang;Houji Zhou;Jiancong Li;Yi Li;Xiangshui Miao;
Pages: 3708 - 3716
Abstract: The utilization of memristive analog-digital mixed in-memory computing has significantly tackled the issues of massive computing resources and time delays in solving combinatorial optimization problems. However, further improvements in computing energy efficiency are still desirable for resource-constrained conditions and practical applications. Therefore, in this work, a memristive analog transiently chaotic neural network (TCNN) system is proposed to solve the traveling salesman problems (TSPs), which is consisted of 1) a memristor array to perform matrix-vector multiplication for the network iteration; 2) neuronal modules and nonlinear activation function modules to emulate the basic functions of the network; 3) chaotic simulated annealing (CSA) modules to improve the solution performance at extremely low hardware overhead. Based on these, after mapping the TSPs onto the memristor array, the proposed TCNN can self-iterate to convergence states to solve the problems with high performance. Compared to prior analog-digital mixed ones, the analog system can eliminate the extra control and data conversions during the network solving process, and achieve an $8\times $ reduction in the total energy consumption in consecutive solving tasks.
PubDate:
WED, 12 JUN 2024 09:17:14 -04
Issue No: Vol. 71, No. 8 (2024)
- Quantification of Cascading Failure Propagation in Power Systems
-
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Authors:
Meixuan Jade Li;Chi K. Tse;
Pages: 3717 - 3725
Abstract: This paper studies cascading failure propagation in power systems and presents methods for the quantification of important properties of failure propagation. First, the topological properties of cascading failure propagation are examined. This includes an analysis of the electrical distance between consecutive failures, shedding light on the spatial spread of failures. Additionally, the formation of islands in cascading failure processes is explored to understand their topological characteristics. Second, the paper measures the evolution of a power system during cascading failure processes, considering both the topological changes of the overall system and the propagation rates of system loss. This analysis provides a measurable comprehension of how the system evolves and adapts as failures propagate. Third, this study investigates system loss and analyzes the contributions of various failure mechanisms to the overall system loss. Numerical experiments yield valuable insights into the propagation of cascading failures, leading to several significant conclusions. The findings from this research can inform the development of effective strategies for resilience enhancement and risk mitigation.
PubDate:
THU, 11 APR 2024 09:18:56 -04
Issue No: Vol. 71, No. 8 (2024)
- Multi-Image Encryption Algorithm Based on Novel Spatiotemporal Chaotic
System and Fractal Geometry-
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Authors:
Lilian Huang;Han Gao;
Pages: 3726 - 3739
Abstract: With the rapid development of communication technology, an increasing amount of image information relies on network transmission. While this enhances transmission efficiency, it also raises the risk of illegal attacks. Therefore, this paper proposes a novel multi-image encryption algorithm based on a new spatiotemporal chaos system and fractal geometry. The algorithm begins by designing a new Chebyshev Improved Coupled Sine Map Lattice (CICSML) system based on the Coupled Map Lattice (CML) spatiotemporal chaos system. Dynamical behavior testing results indicate that, compared to traditional chaos systems, the CICSML system can perform chaotic iterations in both time and space, generating a larger number of chaotic sequences, possessing a broader parameter space, and featuring a wider chaotic region. Secondly, the algorithm uses fractal matrix and Hilbert curve scan scrambling to generate index control sequences for the synchronous scrambling diffusion phase. The initial value sensitivity of fractal matrix and the efficiency of Hilbert curve scan scrambling effectively enhance the security and efficiency of the encryption algorithm. Finally, the algorithm employs the principle of multi-image encryption based on indexed image transformation to encrypt multiple images simultaneously. Experimental simulations and performance analysis results show that the algorithm has good security and strong resistance to attacks.
PubDate:
TUE, 25 JUN 2024 09:30:13 -04
Issue No: Vol. 71, No. 8 (2024)
- Macromodeling of Nonlinear High-Speed Circuits Using Novel Hybrid
Bidirectional High-Order Deep Recurrent Neural Network-
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Authors:
Saeedeh Zebhi;Sayed Alireza Sadrossadat;Weicong Na;Qi-Jun Zhang;
Pages: 3740 - 3753
Abstract: A new structure and macromodeling approach which is an advance over high-order recurrent neural network named bidirectional high-order deep recurrent neural network (BIHODRNN) is proposed in this paper for the first time for nonlinear circuits. In the proposed structure, besides the fully connected weights to the neurons of multiple previous time steps of the same hidden layer in conventional high-order recurrent neural network (HORNN), there are additional fully connected weights to the neurons of that hidden layer for multiple next times steps. Due to more training parameters compared to conventional RNN and HORNN, the proposed BIHODRNN can train and predict more complex relationships in a faster and more efficient way and can better capture long-term dependencies. Also, because of bidirectional structure with multiple orders to the next time steps, it can predict the output signals beyond the training time intervals with much better accuracy. To improve the accuracy of the proposed BIHODRNN even more, another structure and method called Hybrid BIHODRNN was presented in this paper. By combining layers of different orders and different directionality in Hybrid BIHODRNN, the training parameters are significantly decreased leading to the reduction of overfitting problem and increasing the model accuracy. Furthermore, the proposed BIHODRNN and its hybrid version need smaller number of training data compared to the HODRNN for generating a model with similar accuracy. Moreover, two proposed approaches are notably faster than the transistor-level models in circuit simulators for acquiring similar accuracy. The superiorities of the proposed approaches are investigated by modeling two nonlinear circuit examples, namely, 5-coupled and 3-coupled line high-speed interconnects both driven by a four-stage driver.
PubDate:
TUE, 07 MAY 2024 09:16:39 -04
Issue No: Vol. 71, No. 8 (2024)
- Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits
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Authors:
Qi Xu;Lijie Wang;Jing Wang;Lin Cheng;Song Chen;Yi Kang;
Pages: 3754 - 3763
Abstract: In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices’ information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F1-score.
PubDate:
FRI, 03 MAY 2024 09:19:44 -04
Issue No: Vol. 71, No. 8 (2024)
- A Universal Discrete Memristor With Application to Multi-Attractor
Generation-
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Authors:
Sen Zhang;Yongxin Li;Daorong Lu;Xiaoping Wang;Zhigang Zeng;
Pages: 3764 - 3774
Abstract: Discrete memristors have been employed in discrete maps for the purpose of chaos generation and regulation. In this paper, a novel universal model for discrete memristors is proposed to generate multi-attractors. The classical Hénon map and Rulkov neuron are chosen as two examples to verify the effectiveness of the proposed memristor. Coexisting homogeneous attractors are identified in the phase space by memristor-induced offset boosting. An arbitrarily desired number of coexisting attractors is extracted by the appropriate feedback strength of the memristor. What adds further interest to this case is that the amplitude is rescaled by a memristor-related parameter that works well over an infinite range. Number-related parameters are extracted to rescale the oscillation range of the chaotic signals. Moreover, CH32-based circuit implementation is built, which aligns with numerical simulation results. Finally, coexisting homogeneous chaotic signals are tested to explore their robust performance in the application of pseudo-random number generator.
PubDate:
FRI, 21 JUN 2024 09:17:03 -04
Issue No: Vol. 71, No. 8 (2024)
- A Fully Probabilistic Model for Sigmoid Approximation and Its Hardware-
Efficient Implementation-
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Authors:
Wenhao Lu;Minshan Lu;Xiangfen Zhang;Zhongzhiguang Lu;Miao Sun;Boyi Dong;Zhou Shu;
Pages: 3775 - 3786
Abstract: The sigmoid function is a representative activation function in shallow neural networks. Its hardware realization is challenging due to the complex exponential and reciprocal operations. Existing studies applied piecewise models to approximate sigmoid function and employed numerical methods or non-uniform input segmentations to mitigate fitting inaccuracies. However, the breakpoints introduce inevitable approximation precision loss. Besides, additional fitting processes greatly increase hardware complexity and power consumption. This paper presents a hardware-friendly sigmoidal approximation from the perspective of probability theory. We find that for a given input, the output of a sigmoid function can be approximated by the probability that the sum of this input and a Gaussian random variable is greater than or equal to zero. As the derived theorem does not involve piecewise expressions, the precision loss caused by the breakpoint issue is avoided. A low-complexity binary-search-based address localization method is proposed to optimize our theorem for hardware implementation. For the optimized scheme, an efficient implemented circuit is also presented. Our scheme’s approximation ability and hardware efficiency are validated through software modeling and FPGA- and ASIC-based experiments. Feedforward neural network-based classification applications demonstrate that building networks with the proposed sigmoid approximator has only a tiny recognition rate loss.
PubDate:
MON, 24 JUN 2024 09:16:22 -04
Issue No: Vol. 71, No. 8 (2024)
- Stabilization of Noisy Sampled-Data Networked Control Systems: Application
to Interleaved Flyback Modular Integrated Converter Circuit-
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Authors:
Tianjiao Liu;Jianwei Xia;Guoliang Chen;Ju H. Park;Xiangpeng Xie;
Pages: 3787 - 3798
Abstract: This paper is concerned with noisy sampled-data networked control systems with stochastic network-induced delays and noisy sampling intervals using a stochastic discrete integral quadratic constraint (DIQC) approach. Initially, the noisy sampled-data networked control system is discretized into a stochastic discrete-time system. This system is then transformed into a feedback interconnected system with zero initial conditions. Next, a stochastic DIQC method is developed to obtain a novel stability condition for the noisy sampled-data networked control system. Based on this criterion, a two-stage algorithm is presented to design suitable controllers to ensure the closed-loop system under study is uniformly exponentially stable. Finally, a numerical examples and a fourth-order interleaved flyback modular integrated converter circuit are given to validate the efficiency of the proposed results.
PubDate:
MON, 01 APR 2024 11:06:12 -04
Issue No: Vol. 71, No. 8 (2024)
- Differential Flatness of Single-Input Commensurate Delay Systems With
Applications to Trajectory Planning, Tracking, and Transformation to Fully
Actuated Systems-
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Authors:
Zhao-Yan Li;Yu Liu;Bin Zhou;
Pages: 3799 - 3809
Abstract: This paper studies the differential flatness of time-delay systems (TDSs). Based on factorizations in the pseudo-polynomials ring, a flat output for the single-input linear commensurate TDS (namely, the delays in the system are multiplies of a certain unit delay) is constructed explicitly. Then the TDS can be converted into a high-order fully actuated system (HOFAS) model with the generalized state as the flat output, and the finite spectrum assignment (FSA) problem can be solved immediately by using the HOFAS approach, which provides some new insight into the study of the FSA problem. By parameterizing the considered TDS via the constructed flat output and applying the interpolation theory, the state trajectory planning problem and state tracking problem are solved, resulting a two-degree-of-freedom (2DOF) controller. Numerical examples demonstrates the effectiveness of the presented approach.
PubDate:
WED, 20 MAR 2024 09:23:43 -04
Issue No: Vol. 71, No. 8 (2024)
- Imitation-Based Reinforcement Learning for Markov Jump Systems and Its
Application-
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Authors:
Jiacheng Wu;Jing Wang;Hao Shen;Ju H. Park;
Pages: 3810 - 3819
Abstract: In this paper, the imitation reinforcement learning-based control problem is studied for discrete-time Markov jump systems with external disturbances. First, zero-sum game method is introduced to deal with external disturbances, where control input and external disturbances are regarded as two rival players in adversarial environments. Then, the imitation reinforcement learning problem is formulated, where learner Markov jump systems aim to learn the optimal behavior of expert Markov jump systems. Considering that the dynamics information of both learner systems and expert systems is accurately known, an offline parallel imitation learning algorithm is designed for learner systems to mimic expert behaviors, which contains three steps: 1) policy evaluation, 2) search for weight matrix, and 3) policy improvement. On this basis, by observing the optimal behavior of expert systems, an online imitation reinforcement learning algorithm is presented for learner systems with completely unknown system dynamics. Moreover, rigorous proofs of convergence and stability analysis are provided to guarantee the performance of proposed algorithms. Finally, the effectiveness of the proposed method is verified by a single-machine infinite-bus power systems.
PubDate:
TUE, 23 APR 2024 09:16:23 -04
Issue No: Vol. 71, No. 8 (2024)
- Simplified ADP-Based Distributed Event-Triggered Fault-Tolerant Control of
Heterogeneous Nonlinear Multiagent Systems With Full-State Constraints-
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Authors:
Donghao Liu;Zehui Mao;Bin Jiang;Liang Xu;
Pages: 3820 - 3832
Abstract: This paper considers the distributed fault-tolerant consensus for heterogeneous nonlinear multiagent systems (HNMASs) with actuator faults and full-state constraints via adaptive dynamic programming (ADP). In order to handle the state constraint problem with multiple constraint types, a unified universal barrier function is introduced to convert the original constrained system into a non-constrained system. For the purpose of improving control efficiency and guaranteeing system reliability, a novel value function including fault estimations and control inputs is established. Considering the limitation of the computation and communication resources, a simplified ADP method incorporating the dynamic event-triggered strategy is developed to learn a distributed event-triggered fault-tolerant control policy. It is strictly proven that the HNMASs’ stability and the neural network weights’ convergence are guaranteed by the Lyapunov theory in the sense of uniform ultimate boundedness. Simulations are presented to verify the proposed control policy.
PubDate:
WED, 24 APR 2024 09:16:29 -04
Issue No: Vol. 71, No. 8 (2024)
- H∞ State Estimation for Two-Time-Scale Markov Jump Complex Networks
Under Analog Fading Channels: A Hidden-Markov-Model-Based Method-
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Authors:
Feng Li;Youzhi Cai;Lei Su;Hao Shen;Shengyuan Xu;
Pages: 3833 - 3842
Abstract: In this paper, the asynchronous state estimation problem of two-time-scale Markov jump complex networks under analog fading channels is investigated, in which the mode of the designed state estimator is asynchronous to the system mode and the asynchronous probabilities are partially known. The two-time-scale phenomenon of complex networks is modeled by a singular perturbation parameter and the changes in connection mode between the complex networks are subject to a Markov chain. The output measurements are transmitted via analog fading channels and fading gains are used to represent the magnitude of the decline of the transmitted information. The purpose of this study is to design an asynchronous state estimator related to the asynchronous mode of the network topology such that the stochastic stability with an $H_{\infty }$ performance index of the resultant error dynamics can be guaranteed. By designing the Lyapunov function which is associated with the singular perturbation parameter and the system mode, the stochastic stability condition of the estimation error system is derived. A new decoupling method to obtain the state estimator gains is proposed, which removes the limitation on the relaxation matrix of previous research results. Finally, the effectiveness of the methods are verified by a numerical simulation example and a capacitor-resistance circuit model.
PubDate:
TUE, 12 MAR 2024 09:16:36 -04
Issue No: Vol. 71, No. 8 (2024)
- Distributed Non-Cooperative Games and Distributed Learning in Linear and
Nonlinear Systems: An Overview-
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Authors:
Fuxiao Tan;Kuankuan Qi;
Pages: 3843 - 3856
Abstract: As an important research direction of distributed intelligence, distributed non-cooperative game (DNCG) mainly involves algebraic graph theory, distributed learning, multi-agent system (MAS) and distributed control theory, which has been received more and more attention. Although significant progress has been made in solving DNCGs, DNCGs in linear and nonlinear systems based on distributed learning methods have not been fully summarized. Therefore, based on distributed learning methods, this paper provides a recent review of distributed zero-sum games (DZSGs) in linear and nonlinear systems. First, the classical directed communication graphs widely used in DZSGs with a fixed topological structure have been investigated. Second, this paper details the four types of MASs suitable for DZSGs, which are prepared for the introduction of DZSGs below. Then, a table summarizes the 12 types of classical MASs that have been widely used in DZSGs. Moreover, the DZSG problems in four types of linear and nonlinear systems have also been investigated, which established a foundation for the subsequent distributed algorithms. Furthermore, this article simultaneously studied the existing classic distributed algorithms for DZSG problems under four different system types, which presented the research status of DZSG problems for 12 systems in the form of a table. Finally, the further research directions of DNCGs have been summarized and the promising and challenging research directions for the future have also been proposed in the paper.
PubDate:
TUE, 26 MAR 2024 09:17:35 -04
Issue No: Vol. 71, No. 8 (2024)
- Dynamic Event-Triggered Consensus Control for Interval Type-2 Fuzzy
Multi-Agent Systems-
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Authors:
Zhenbin Du;Xiangpeng Xie;Zifang Qu;Yangyang Hu;Vladimir Stojanovic;
Pages: 3857 - 3866
Abstract: This study investigates a fuzzy consensus problem for nonlinear multi-agent systems (MASs) with parameter uncertainties via dynamic event-triggered mechanism. The interval type-2 (IT2) fuzzy systems are used to model MASs, and a dynamic event-triggered fuzzy controller is presented. A Lyapunov-Krasovskii functional is constructed in which the sampling property is included, based on which the sufficient condition is determined for dynamic event-triggered fuzzy controller, while all agents are guaranteed to be consensus exponentially. Finally, the MASs of tunnel diode circuit and one-link manipulator are used to verify the efficiency of the presented control method, respectively.
PubDate:
WED, 06 MAR 2024 09:17:12 -04
Issue No: Vol. 71, No. 8 (2024)
- Distributed Frequency Interactive Damping Control for Multiple VSGs in
Islanded Microgrids-
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Authors:
Shujin Chen;Hua Han;Zhenxi Wu;Zhenzhen Luo;Zhangjie Liu;Yonglu Liu;Chi K. Tse;
Pages: 3867 - 3879
Abstract: Frequency damping control is a crucial aspect of islanded microgrids utilizing multiple virtual synchronous generators (VSGs). This paper studies the effects of line impedance mismatches and transient frequency out-of-sync leading to frequency interactive oscillation in VSGs. To address this issue, we propose a distributed interactive damping and zero-error control method that utilizes sparse communications. The objective of this method is to effectively suppress frequency oscillation by minimizing the differences in frequency dynamics among all VSGs. By implementing this approach, a low rate of change of frequency (RoCoF), accurate active power sharing, and zero frequency deviation are ensured. Through dynamic performance analysis, frequency characteristic analysis, and stability analysis based on LaSalle’s invariance principle, we demonstrate significant improvements in system stability, as well as dynamic and steady state performances. Finally, simulation and experimental results obtained under load changes, short-circuits, and communication faults validate the effectiveness of the proposed control method.
PubDate:
FRI, 17 MAY 2024 09:16:24 -04
Issue No: Vol. 71, No. 8 (2024)
- Fuzzy-Based Bipartite Quasi-Synchronization of Fractional-Order
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Authors:
Yao Xu;Zhuozhen Jiang;Xiangpeng Xie;Wenxue Li;Yongbao Wu;
Pages: 3880 - 3890
Abstract: This paper investigates the T-S fuzzy-based bipartite quasi-synchronization of fractional-order heterogeneous coupled reaction-diffusion neural networks. In the considered neural networks, interactions between adjacent neurons are time-varying, cooperative, and competitive, and heterogeneity and T-S fuzzy system rule are simultaneously introduced to characterize the parameter uncertainty arising from complexity and ambiguity in the real world. A new time-varying graph-theoretic Lyapunov function is given for time-varying coupled reaction-diffusion neural networks. Meanwhile, a more general fractional-order derivative law is provided to estimate the derivative of this function, which includes the existing fractional-order derivative laws. Based on a fuzzy-based aperiodically intermittent control, some sufficient conditions are offered for the bipartite quasi-synchronization under a time-varying graph-theoretic Lyapunov function, and the allowable error bound is given. Finally, we carry out some simulations numerically to show the validity of the theory.
PubDate:
TUE, 26 MAR 2024 09:17:35 -04
Issue No: Vol. 71, No. 8 (2024)
- Accurate Modeling of Transformer-Based Voltage-Multiplier Considering
Reverse Recovery Process of the Leakage Inductance in Step-up Converter-
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Authors:
Ningrui Yang;Zou Li;Jun Zeng;Junfeng Liu;Renjun Hu;Gengning Ying;Zhixing Yan;Man-Chung Wong;Fangren Zhang;
Pages: 3891 - 3903
Abstract: The advent of third-generation semiconductors brings the switching frequency into a much higher level, which enables high-frequency transformer with a smaller footprint in power electronics. Due to its inherent ability of voltage amplification, the transformer-based voltage-multiplier becomes prevalent in step-up converters which are the inevitable parts in the usage of low-voltage renewable resources. Though its feasibility has been verified in many researches, an uncertain error in voltage conversion ratio exists between the reality and ideal, which leaves a theoretical gap. Accordingly, the key affecting characteristics, the reverse recovery process of the leakage inductance, is considered and analyzed in this paper. The power transmission mechanism is clarified, and the root-mean-square error of the gain can be reduced from 24.31% to 3.13%, and the maximum output power together with power effect on the gain are obtained. With the conclusion of this paper, parameters of power supply can be optimized at the beginning of design to satisfy the demand of maximum output power and gain over a wide power range, which can save the unnecessary trial-and-error during the case-by-case design.
PubDate:
MON, 24 JUN 2024 09:16:22 -04
Issue No: Vol. 71, No. 8 (2024)
- A Single-Inductor Multiple-Output DC–DC Converter With Fixed-Frequency
Victim-Last Charge Control for Reduced Cross Regulation-
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Authors:
Yang Li;Mo Huang;Rui P. Martins;Yan Lu;
Pages: 3904 - 3914
Abstract: This paper presents a single-inductor multiple-output (SIMO) DC-DC converter with fixed-frequency victim-last charge control. This scheme switches the load-transient channel (victim) to the last of the charging sequence, addressing the inherent cross-regulation issue in conventional charge control SIMO. We first analyze why the conventional fixed-frequency charge control has such an issue. Then, we present the working principle of the proposed scheme. After that, we propose a charge-error calibration technique that minimizes the side effects caused by victim-last control, ensuring a smooth order switching of the original last channel. We implemented and fabricated the proposed SIMO DC-DC converter in a 0.18- $\mu $ m BCD process. Measurement results show that we are able to reduce the cross-regulation to 0.057mV/mA with a 225-mA load step under fixed switching frequency. The measured peak efficiency is 84.1%.
PubDate:
THU, 16 MAY 2024 09:16:30 -04
Issue No: Vol. 71, No. 8 (2024)
- A Multi-Break Mechanical Switch Applicable for Medium Voltage Natural
Commutation DC Circuit Breakers-
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Authors:
Zhizheng Gan;Lu Qu;Zhanqing Yu;Xin Yan;Rong Zeng;Biao Zhao;Yulong Huang;Wei Li;
Pages: 3915 - 3925
Abstract: Hybrid DC circuit breakers (HDCCBs) are among the most promising solutions for DC breaking. HDCCBs based on forced commutation have the shortcomings of conduction loss or high cost, which hinders their large-scale application. HDCCBs based on natural commutation, despite their lower cost and smaller volume, are limited by the arc voltage. Therefore, this paper proposes a type of multibreak mechanical switch applicable for medium-voltage natural commutation HDCCBs. Possessing the advantages of compact size and high arc voltage, the switch consists of a four-break gas chamber and a vacuum chamber, the former of which realizes the series connection of multiple arcs through a bridge contact structure. The vacuum chamber is used to bear the turn-off overvoltage. Combined with high-speed observation methods, the mechanical characteristics and arc characteristics of the multibreak mechanical switch are analyzed, and the influence mechanism of different factors on the arc characteristics of the four-break chamber is revealed. On this basis, a principle prototype of the 15 kV medium-voltage natural commutation HDCCB was developed, and breaking tests were carried out. The breaking current can reach 15 kA, and the breaking time is less than 3 ms.
PubDate:
WED, 24 JUL 2024 09:16:56 -04
Issue No: Vol. 71, No. 8 (2024)
- Single-Phase Standalone Multi-Port DC/AC Inverter for Multiple Energy
Production and Storage Units-
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Authors:
Michail Dakanalis;Eftichios Koutroulis;Fotios D. Kanellos;
Pages: 3926 - 3936
Abstract: Multi-port power converters enable the combination of renewable energy sources and energy storage. This paper presents a single-phase standalone multi-port inverter (MPI) that integrates a photovoltaic (PV) array, a battery storage unit, a supercapacitor (SC) bank, and electric vehicle (EV) battery. The proposed MPI regulates the power flow between these ports to ensure optimal energy management and reliable operation of the AC power-supply system. The PV array is directly connected to the DC-link, eliminating the need for an additional power converter and reducing the volume and cost of the overall MPI. The energy management algorithm is designed to independently control each port and maintain a power balance between the input and output of the proposed MPI. Compared to conventional MPI architectures, the multi-port DC/AC inverter proposed in this paper contains less power devices, resulting in reduced switching power losses and implementation cost. Experimental results demonstrate the effectiveness of the proposed system in regulating each port independently under various power flow scenarios, with a maximum efficiency of 95.3%.
PubDate:
FRI, 07 JUN 2024 09:16:49 -04
Issue No: Vol. 71, No. 8 (2024)
- TechRxiv: Share Your Preprint Research with the World!
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Pages: 3937 - 3937
Abstract: null
PubDate:
WED, 31 JUL 2024 09:18:16 -04
Issue No: Vol. 71, No. 8 (2024)
- IEEE Transactions on Circuits and Systems--I: Regular Papers Information
for Authors-
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Pages: 3938 - 3938
Abstract: null
PubDate:
WED, 31 JUL 2024 09:18:15 -04
Issue No: Vol. 71, No. 8 (2024)
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