JournalTOCs

SILICON
Journal Prestige (SJR): 0.355

Citation Impact (citeScore): 1
Number of Followers: 0

Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1876-9918 - ISSN (Online) 1876-990X
Published by Springer-Verlag

[2469 journals]

Simulation and Drain Current Performance analysis of High-K Gate
Dielectric FinFET
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  Abstract: Abstract In this paper, we design, simulate and analyze FinFET with different materials, corresponding variation in ID VS VGS, transconductance, subthreshold slope. There is an increase in ON current on using a high-k dielectric material and subsequently an improvement in other parameters like subthreshold slope and transconductance.
  PubDate: 2022-06-01
Subthreshold Analytical Model of Asymmetric Gate Stack Triple Metal Gate
all Around MOSFET (AGSTMGAAFET) for Improved Analog Applications
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  Abstract: Abstract In this paper, we have proposed a 2D analytical model for Asymmetric gate stack triple metal gate MOSFET(AGSTMGAAFET) and performed a comparative analysis with the simulation results obtained using the SILVACO 3D simulation software. Existing devices such as gate all around single metal (SMGAAFET), gate all around triple metal (TMGAAFET), gate stack single metal (GSSMGAAFET), gate stack triple metal (GSTMGAAFET) and asymmetric gate stack single metal (AGSTMGAAFET) have been compared with our proposed structure AGSTMGAAFET. Our device provides excellent performance in terms of drain current, transconductance, output conductance, current gain, maximum transducer power gain which shows our device’s suitability for various analog applications moreover the potential and electric field plots obtained have twostep profile and extremely low electric field near the drain region which ordains our device with the ability to suppress various SCE’s like DIBL and hot-carrier effect. The analytical model and simulation results show good convergence in values which validate the correctness of the proposed model.
  PubDate: 2022-06-01
Performance of Etched Silica FBG for Simultaneous Strain Temperature
Measurement
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  Abstract: Abstract In this paper, we have proposed an etched silica Fiber Bragg Gratings (FBGs) based interrogation technique using an optical spectrum analyser (OSA). The efficiency of the proposed system has extensively been investigated for measuring the temperature and strain simultaneously with higher sensitivity and accuracy covering a larger measurement range. A Single mode-Multi mode-Single mode fiber (SMS) which acts as a bandpass filter is employed in the circuitry for an efficient and fast interrogation technique. We recorded a remarkable enhancement in sensitivity of 20.30 pm/°C and 2.89 pm/μɛ over the temperature and strain range of 25–225 °C and 50–2050 μɛ, respectively. These data were recorded with the strain resolution of ±10 μɛ whereas the resolution for the temperature is ±0.50 °C. The experimental results show the capability of the sensor for measuring the strain and temperature simultaneously with higher intrinsic sensitivity and resolution. The performance of the proposed sensor has been compared with various reported techniques.
  PubDate: 2022-06-01
Design and Temperature Assessment of Junctionless Nanosheet FET for
Nanoscale Applications
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  Abstract: Abstract Nanosheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics are investigated for the first time using extended source/drain and with high-k gate stack. The detailed DC performance analysis like transfer characteristics (ID-VGS), output characteristics (ID-VDS), drain induced barrier lowering (DIBL), subthreshold swing (SS) and ION/IOFF ratio are evaluated from 200 K to 350 K. We also analyzed the temperature effect on the ON-OFF performance metric (Q), dynamic power, and power consumption. Furthermore, to understand the device performance on various process parameters like doping and work function variations are presented at 300 K. The proposed device exhibits good ION/IOFF switching behavior with IOFF reaching less than nA for all temperatures. The cutoff frequency (fT) is determined to be in the THz range the Q ranges between 1.5 to 2.2 μS-dec/mV for temperatures between 200 K to 350 K at LG of 10 nm. Moreover, the scaling effect of nanosheet at various gate lengths (LG = 5 to 20 nm) are also presented. From simulation analysis we notice that analog/RF performance parameters of a JL nanosheet FET are less sensitive to temperature variations. At extremely scaled LG the JL nanosheet FET exhibits lesser power consumption, power and decreases with increase in temperature. Thus, the proposed JL nanosheet FET demonstrates as a strong potential contender for low power and high frequency applications at nano-regime.
  PubDate: 2022-06-01
Silicon Carbide Recovery from Cutting Fluid Waste: Evolution of Recycling
Performance for Valorization with Higher Added Value
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  Abstract: Abstract The amount of cutting fluid waste composed of polyethylene glycol, silicon carbide, silicon and metals fragments (e.g. Fe, Zn, Mn and Ni) increase as silicon wafer production raises. In the present work, we propose a low-cost and easy approach to recover SiC particles from slurry waste. The process consists to combine acid leaching, alkaline dissolution and deoxidation. This research focuses too on the impact of native silicon dioxide layer evolution occurring on the surfaces of SiC particles on the recovering efficiency and purity. The effect fluorhydric acid concentration was explored. A double wall cell was used as magnetic reactor in order to achieve the dissolution of metal fragments and silicon dissolution under highly-alkaline conditions (pH ≥ 13) at a temperature above 60 °C. The morphology evolution of SiC grains after several sawing operations of silicon ingot is also discussed. The SiC powder was successfully recycled by converting all the silicon species into sodium silicate solution with a recovery efficiency and purity of 98.8% and 97.69% respectively. The recovered SiC was characterized by XRD, SEM-EDAX and optical microscopy.
  PubDate: 2022-06-01
Optimization of Aging, Coating Temperature and Reinforcement Ratio on
Biosilica Toughened in-situ Al-TiB2 Metal Matrix Composite: a Taguchi Grey
Relational Approach
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  Abstract: Abstract The aim of this study was to optimize metal matrix composite manufacturing process parameters such as ageing period, coating temperature, and reinforcement ratio in order to produce high-performance aluminum metal matrix composites for variety of applications. Using the Taguchi L9 orthogonal array scheme and the grey relational approach, the biosilica toughened in-situ Al-TiB2 metal matrix composites were prepared. The ageing period was found to be the most controlling process parameter among other variables, according to the study. Similarly, the process variables such as aging time of 300 min, coating temperature of 70 oC and reinforcement ratio of 0.6 (A1B2C3) were found to be new optimum process variables. The SEM micrographs of composite’s surface confirm the decent deposition of Ni-P at 70 oC. The grey relational grade value was improved from 0.678 to 0.696 for optimized process variables. The tensile strength of 187.62 MPa, surface hardness of 95.23 BHN and specific wear rate of 0.004 mm3/Nm with COF of 0.42 was the outcome of the optimized study. The grey relational grade value of confirmation experiment is improved by 1.31 % from the predicted mean value of experiment A1B3C3 with GRG of 0.687.
  PubDate: 2022-06-01
Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs
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  Abstract: Abstract In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (Ron) along with increased breakdown voltage (Vbr) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (ID) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (fmax) and cut-off frequency (ft). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak gm, ID, fmax and ft with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.
  PubDate: 2022-06-01
Synthesis and Characterization of the Starch/silicone Oil Composite and
Elaboration of its Films
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  Abstract: Abstract Synthesis of the starch/silicone oil composite carried out and its structural characterization by FTIR, Raman and 29Si NMR allowed to identify functional groups of the composite. The synthesis conditions were a starch/silicone oil mass ratio of 2.0 and a temperature of 150 oC to obtain a yield of 84.63 %. SEM analysis showed that the starch granules were covered by silicone oil, this caused a decrease in the crystallinity of starch. Composite films have higher thermal stability compared to native starch. Mechanical properties and electrical conductivity of the starch/silicone oil composite film increase with respect to starch-only films. While the crystallinity of both films is similar. The results obtained in this work indicate that starch/silicone oil composites can be an alternative to make films with a potential use for the packaging industry.
  PubDate: 2022-06-01
Design and Analysis of Triple Metal Vertical TFET Gate Stacked with N-Type
SiGe Delta-Doped Layer
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  Abstract: Abstract This work deals with the novel characterization of n + SiGe δ-doped layer with the combination of gate stacking method in Vertical TFET device by using TCAD simulation tool. The vertical structure will enhance the device’s scalability because of vertical electron tunneling for vertical electrical field. Therefore, higher ON state current offers due to parallel movement of charge carriers to the gate electric field. The introduction to the optimized n + Si0.2Ge0.8 δ-doped layer will further reduce the off-state leakage current and enhance device performance because it minimizes the tunneling bandwidth between the source and channel junction. Triple metal gate is introduced to mitigate the unwanted ambipolar conduction and optimized the work function at tunneling gate, control gate and auxiliary gate with the value of 4.15 eV, 4.3 eV and 4.15 eV. Four of the different combinations have been discussed and compared with and without presence of the gate stack and n + δ-doped layer. The reported data reveals that among all different structures, the existence of gate staking method and SiGe δ-doped layer will show the 40% improvement with existing simulations. A high current ratio of the order (~1013), with substantially benchmarking results of steeper subthreshold slope (9.75 mV/decade), is achieved. The simulation results conclude the n + δ-doped TMG vertical TFET as a sustainable candidate for ultralow-power applications.
  PubDate: 2022-06-01
A Physics Based Threshold Voltage Modeling of Trigate Junctionless FinFETs
Considering Gaussian Doping
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  Abstract: Abstract In this paper, the analytical modeling of Trigate Junctionless FinFETs has been explored. The analytical model expresses the potential distribution, minimum center potential and threshold voltage. The variable separation method has been used to develop the potential distribution and threshold voltage. Further, the analytical model analyzed for different device parameters of Fin width, Fin height, Gate oxide thickness and gate work function. The analytical model results are compared with Synopsys TCAD results which proves the validation of proposed analytical model.
  PubDate: 2022-06-01
Impedance Characterization of AlGaN/GaN/Si High Electron Mobility
Transistors
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  Abstract: Abstract AlGaN/GaN HEMTs grown on high resistive silicon (111) substrate grown by molecular beam epitaxy have been investigated using impedance measurements. Passivation of the HEMT devices is made in order to improve the electron transport. As has been found from conductance data, the electron traps are eliminated after passivation. The impedance spectroscopy has been, on the other hand, studied from the electrical transport. As a result, a complex impedance plot was revealed an equivalent circuit models indicating single semicircles and the solid interface.
  PubDate: 2022-06-01
Geometrical Model for the Growth Mechanism of Si Nanopores
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  Abstract: Abstract The importance of silicon nanopore fabrication lies, in part, on being a high demand emergent technology to make ultrafast DNA sequencing. Other important applications include separation of single stranded and double stranded DNA in solution, the length determination of polymers, as well as in the synthesis of different types of sensors. In this article, a theoretical model is proposed to describe the growth of a silicon nanopore as a dynamical phenomenon, resulting from the electromigration and diffusion currents of the ionic species produced during a wet etching process. This model allows to evaluate the time dependence of the nanopore size from the measured current and the physicochemical properties of the etching agents responsible of the ionic transport. The nanopore growing model reported here can be useful to characterize the fabrication of size-controlled pores, that can be adapted for applications in proteomics and genomics sensing.
  PubDate: 2022-06-01
Investigation of Variability in Device Design on Saturation
Characteristics of Nanowire Tunnel FETs
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  Abstract: Abstract Estimation of the saturation voltages of beyond CMOS devices is essential for the accurate circuit design and analysis. In this work, we look at the influence of device design parameters on the saturation voltage (VDSAT) of a Tunnel Field Effect Transistor (TFET) using 3D TCAD Numerical Simulations. The variation in channel length, underlap at gate-drain, source/drain doping, and the source/channel material are some of the vital optimization parameters in the design and optimization of TFET based circuits. We observe, with the increasing value of drain bias (VDS), TFET device initially enters in the soft saturation state and subsequently a deep saturation state is attained. These voltages are altered with device variability and hence the analog performance. An increase in drain (source) doping increases (decreases) the soft saturation voltage of TFETs. It is also found that an early onset of saturation can be achieved by the gate-drain underlap in TFETs. The impact of short channel lengths is to worsen the perfect saturation phenomenon in Tunnel FETs. In addition, the reduction in nanowire diameter delays the saturation by few milivolts.
  PubDate: 2022-06-01
Efficiency Enhancement in Dye Sensitized Solar Cell Using 1D Photonic
Crystal
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  Abstract: Abstract A detailed theoretical investigation of one dimensional SiO2/TiO2 photonic crystal based ZnO-Pt dye sensitized solar cell with N719 dye is carried out. The optical properties of the theoretically designed dye sensitized solar cell such as transmittance, absorptance and reflectance are calculated using transfer matrix method in order to calculate numerically the key parameters like open circuit voltage (VOC), short circuit current (Jsc) and efficiency of the DSSC. The efficiency of the porous one-dimensional 1D SiO2/TiO2 photonic crystal coupled ZnO-Pt dye sensitized solar cell is studied for various periods of photonic crystal layers. It is found that the desired integrated system enables to maximize the absorption in the selective spectrum region (400-900 nm) and hence the maximum efficiency achieved is 4.5% for a ZnO-Pt dye sensitized solar cell having a 1D SiO2/TiO2 photonic crystal.
  PubDate: 2022-06-01
Coulomb Blockade Effect through Single Electron Tunneling Method in
Cylindrical Gate Organic Light Emitting Transistor Configuration
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  Abstract: Abstract In this paper, comparison among single gate organic light emitting transistor (SG-OLET), dual gate organic light emitting transistor (DG-OLET) and cylindrical organic light emitting transistor (C-OLET) are discussed in detail. Where the device structural and material parameter includes the pentacene(400 nm) as an organic semiconductor, PMMA/SiO2 (200 nm) is an insulator, the source and drain of Au (35 nm) along with Ni/Ti (5 nm) contact pads for tunneling electrons from source to drain and gate electrode of Si (200 nm). The extracted performance parameters for DG-OLET are drive current (Ids), threshold voltage (Vth), mobility (μ), and current on-off ratio (Ion/Ioff) are of 9.0 μA, 0.5 V, 1.1cm2/Vs and 2*108, respectively at Vgs of -3 V and Vds of 0 to -3 V. The observed results of DG-OLET are significantly higher in comparison to SG-OLET, whereas results of C-OLET is approximately comparable. Afterward, quantum dots (QDs) based single and dual OLETs are analyzed and observed the significantly higher drive current in both SG and DG-OLET devices in comparison to pentacene OSC based devices. Thereafter, coulomb blockade concept is discussed in-depth, because there is a need of coupling to their surroundings of electrodes by these structures which can either add or subtract electrons from the electrodes. Subsequently, single electron tunnelling (SET) phenomena is explained thoroughly. This method permits the optical and electrical behavior of the single-island structures of the SET. Light production is controlled by the gate voltage that controls the hole current. The results also indicate that OLET with high brightness can be fabricated by use of a light emitting conducting polymer. Besides this, performance of CG-OLET is investigated and additionally, mathematical model for cylindrical gate OLET is described. The DG-OLET is realized that helps in higher charge carrier modulation in OSC channel layer, whereas Cylindrical -OLET will be utilized in wearable electronics for medical and space technology applications.
  PubDate: 2022-06-01
Tribological, Thermal and Corrosive Behaviour of Aluminium Alloy 2219
Reinforced by Si3N4 Nanosized Powder
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  Abstract: Abstract The Metal Matrix Composite (MMC) technique is the most effective contrast method when compared with other techniques. By using the method of high energy stir casting, Aluminium alloy Al2219 is reinforced with various percentages of Si3N4 (0, 3, 6, and 9 %) particles. X-ray diffraction along with Scanning electron microscope was performed to characterize the composite. The mechanical and thermal behaviours such as differential thermal analysis thermo gravimetric analysis/, tensile, wear and hardness behaviours were investigated. By using electro chemical potentiodynamic polarization test, the consequence of heat treatment on the corrosion behaviour of the composites when compared to its matrix in 3.5 % NaCl when at 600 rpm was also investigated. In this experimental study, the wear of the aluminium composites was significantly decreased on addition of Si3N4 particles. The study also revealed that, since the inclusion of Si3N4 in the samples and compared to the base aluminium alloy, the mechanical properties of the composites, such as wear resistance, hardness and tensile strength increased by percentage. The surface morphology and Scanning electron microscope analysis of worn surfaces in the test pieces unfold that with the increase in reinforcement content, wear rate decreases.
  PubDate: 2022-06-01
Multi Response Optimization of ECDM Process Parameters for Machining of
Microchannel in Silica Glass Using Taguchi–GRA Technique
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  Abstract: Abstract In this work, machining of microchannel in silica glass was successfully carried out using electro chemical discharge machining (ECDM) process. The experiments were planned according to L27 orthogonal array with applied voltage, stand-off distance (SOD), electrolyte concentration, pulse frequency and pulse-on-time (TON) as control factors. The material removal rate (MRR), overcut (OC) and tool wear rate (TWR) were considered as response characteristics. In this study the effects of control parameters on MRR, OC and TWR have been investigated. The increase in applied voltage, electrolyte concentration and pulse on time lead to the improvement in the output characteristics which is attributed to formation of heavily crowded hydrogen bubbles and further coalescence of hydrogen bubbles promotes the occurrence of sparks which resulted in higher values of MRR, OC and TWR. The multi-objective optimization of ECDM was carried out through grey relational analysis (GRA) method. Optimal combination of process parameters achieved from GRA was 45 V applied voltage, 25 wt.% electrolyte concentration, 1.5 mm SOD, 400 Hz pulse frequency and 45 μs TON. ANOVA for GRG study revealed that the applied voltage (70.33%) was most significant factor affecting output responses followed by electrolyte concentration (11.69%), pulse frequency (4.98%) and SOD (4.13%). Furthermore, the regression equations were formulated for the optimum combination to predict the collaboration and higher-order effects of the control parameters. In addition, confirmation test was conducted for the optimal setting of process parameters and the comparison of experimental results exhibited a good agreement with predicted values. The microstructural observation of machined surface for the optimum combination was carried out.
  PubDate: 2022-06-01
Some Electrophysical Properties of Polycrystalline Silicon Obtained in a
Solar Oven
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  Abstract: Abstract The article describes the results of the study of the microstructure and some electrophysical properties of silicon obtained by re-melting in a solar oven. It was found that the granularity of polycrystalline silicon consists of Si atoms with a size of 10–15 μm, the roughness of its surface. It is shown that at T ≤ 600 K the concentration of charge carriers increases due to an increase in the concentration of ionized impurity atoms, which, in turn, leads to a decrease in the resistivity of polycrystalline silicon. The position at T ~ 600–700 K is based on the decrease in the free path of the charge carriers as a result of thermal vibrations of the crystal lattice. The situation at T ≥ 700 K was explained by the emergence of new recombination centers specific to localized traps. Polycrystalline silicon heated by sunlight does not create a barrier effect of traps localized in the grain boundary regions from polycrystalline silicon obtained by other methods. This can expand the possibilities of creating highly efficient semiconductor devices, solar cells, thermoelectric materials for micro- and nanoelectronics, photovoltaics.
  PubDate: 2022-06-01
Dry Machining Performance Studies on TiAlSiN Coated Inserts in Turning of
AISI 420 Martensitic Stainless Steel and Multi-Criteria Decision Making
Using Taguchi - DEAR Approach
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  Abstract: Abstract The key objective of this research study is to examine the performance of TiAlSiN coated insert while performing dry machining of AISI 420 martensitic stainless steel on quantified output responses. This paper seeks to optimize process parameters namely speed, feed, and depth of cut during turning process, such as surface roughness, flank wear, and material removal rate simultaneously. TiAlSiN thin film was coated on the carbide tool through high power impulses magnetron sputtering. To confirm the existence of coated elements, SEM and XRD studies were performed. For coated and pure inserts, microhardness was measured, whereas the TiAlSiN coated tool possesses 43.34% higher than pure inserts. The dry machining was performed with three process parameters, each in three phases. The experimentation was performed based on Taguchi’s design of experiments (DoE). In this study, a Multi-Criteria decision making (MCDM) approach encompassing Data Envelopment Analysis based Ranking Methodology (DEAR) with Taguchi’s design was applied. The multi-response performance index (MRPI) was calculated and their impact on the machining parameters was scientifically examined. The parameter combination of cutting speed: 240 m/min; feed rate: 0.20 mm/rev and depth of cut: 0.50 mm was observed to be the optimal input parameters.
  PubDate: 2022-06-01
Tuning the Characteristics of Novel (PVA-Li-Si3N4) Structures for
Renewable and Electronics Fields
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  Abstract: Abstract In present work, the polyvinyl alcohol-lithium-silicon nitride (PVA-Li-Si3N4) novel structures were designed to use in various renewable and electronics approaches. The structure, optical and electronic characteristics of PVA-Li-Si3N4 structures were studied. The Density functional theory (DFT) was used to study of the influence of Li-Si3N4 on characteristics of PVA structure. The structure and electronic characteristics of the PVA-Li-Si3N4 were studied in relations of the calculated energy, ionization potentials, HOMO-LUMO gap, and electron affinity. The PVA-Li-Si3N4 structures are optimized successfully with Gaussian 09 package. The final results showed the PVA-Li-Si3N4 structures can be used in different optic and optoelectronics applications.
  PubDate: 2022-06-01