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 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [5 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2355 journals]
• A hybrid DAC switching technique for SAR ADCs
• Authors: Sharath R. Srinivasan; Poras T. Balsara
Pages: 179 - 187
Abstract: In recent years, the area of Wireless Sensor Networks has seen a tremendous growth and is instrumental in a multitude of applications ranging from health monitoring to geo fencing. Analog-to-Digital Converters (ADCs) are vital to any low-cost, energy-efficient sensor node in that they convert the sensed signal into its digital counterpart, which is then used processed by the digital circuitry. In this paper, a Capacitive Digital-to-Analog Converter (CDAC) switching technique is proposed that is aimed toward the design of an energy-efficient ADC. The presented switching technique is $$97.85\%$$ more energy-efficient than the traditional CDAC architecture. Besides its energy efficiency, the technique reduces the overall size of the CDAC and its settling time. Theoretical analysis has been presented along with detailed simulation results as a proof of concept.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0974-7
Issue No: Vol. 92, No. 2 (2017)

• Noise shaping Riemann: an energy efficient data conversion scheme
• Authors: Yoan Veyrac; Francois Rivet; Yann Deval
Pages: 189 - 197
Abstract: This paper presents a novel conversion scheme for time signals, especially suited for wireless communication applications. The digital/analog data representation paradigm is discussed and critical aspects are determined. It involves digital information coding, two-way digital/analog conversion and their respective efficiency. The proposed conversion scheme relies on a slight oversampling ratio (OSR), combined with a differentiating coding and a $$1^\mathrm{st}$$ order noise shaping loop. It achieves a resolution increased by 2.5 effective number of bits per doubling of the OSR. The resulting conversion efficiency combined with a moderate digital coding complexity leads to a substantial improvement of the energy cost of conversion compared to conventional Nyquist rate architectures. The efficiency gain is even higher for converters limited by thermal noise. It can reach a ten fold improvement for OSR around 10, which makes this architecture a good option for the handling of radio frequency signals.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0980-9
Issue No: Vol. 92, No. 2 (2017)

• Design and analysis of high-speed split-segmented switched-capacitor DACs
• Authors: Quoc-Tai Duong; Ameya Bhide; Atila Alvandpour
Pages: 199 - 217
Abstract: In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area W–C u is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, C u ) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0981-8
Issue No: Vol. 92, No. 2 (2017)

• A simple circuit technique to relax the feedback timing of ΔΣ ADC for
high-speed and high-accuracy applications
• Authors: Youngho Jung; Gabor C. Temes
Pages: 219 - 223
Abstract: A novel and simple circuit technique to relax the feedback timing of input feed-forward ΔΣ analog-to-digital converter (ADC) is proposed for wideband and high-accuracy applications. The proposed method allows the use of low-speed comparator and DEM logic even for high-speed operation which helps to reduce the power consumption. A delta-sigma ADC with relaxed feedback timing was designed and simulated. The results verify the advantages of the proposed technique.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0993-4
Issue No: Vol. 92, No. 2 (2017)

• Design and analysis of low-power and area efficient N-bit parallel binary
comparator
• Authors: Chang Chua; R. B. N. Kumar; B. Sireesha
Pages: 225 - 231
Abstract: This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR–NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180nm—technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto $$25\%$$ , area (number of transistors) reduces upto $$36\%$$ and improves the delay performance $$27\%$$ compared to existing technique.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0996-1
Issue No: Vol. 92, No. 2 (2017)

• A 500 MHz low offset fully differential latched comparator
• Authors: Saeed Naghavi; Niloofar Sharifi; Mozhdeh Nematzadeh; Tohid Moradi Khanshan; Adib Abrishamifar; Zia Daei Kuzekanani; Jafar Sobhi
Pages: 233 - 245
Abstract: A fully differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a positive feedback or latch stage and the offset cancellation circuitry. The effect of kick-back noise can be significantly reduced by using a pre-amplifier stage. Also, the offset and noise of the latch and offset cancellation stages are attenuated by the gain of the pre-amplifier when referred to the input. Latches regenerate faster than pre-amplifiers and provide a full swing digital output for the comparator. The last stage is the offset cancellation circuitry. The main advantage of the proposed offset cancellation technique is that it does not need to make any interrupt in normal operation of comparator to eliminate offset error. As a result, higher speeds for the comparator can be achieved. Moreover, the power consumption of the proposed offset cancellation circuitry is negligible compared to the overall power consumption. In order to evaluate the performance of the comparator, simulations are performed in a 0.18 μm standard CMOS technology. Simulation results show that the offset values of the pre-amplifier and latch stages are significantly eliminated by this cancellation technique and only about 450 μV offset voltage will be referred to the input due to offset error of the offset cancellation circuitry. The proposed comparator operates at 500 MHz clock frequency and dissipates 373 μW from a 1.8 supply. Also, it has a propagation delay of 138 ps and kick-back noise of 0.54 mV.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0998-z
Issue No: Vol. 92, No. 2 (2017)

• Mitigating the thermally induced single event crosstalk
• Authors: Selahattin Sayil; Pankaj Bhowmik
Pages: 247 - 253
Abstract: With advances in technology scaling, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. With scaling, interconnects are also being laid closer to each other causing increased cross-coupling noise effects. Due to strong coupling among wires, SE transients can easily contaminate electronically unrelated circuit paths via SE crosstalk noise effects increasing SE susceptibility of CMOS circuits. This work reports that varying temperature profiles on nearby interconnects can further alleviate SE crosstalk noise effects. The increased temperature affects both interconnect resistance and driving strength of transistors. If temperature induced effects are not properly considered, standard measures taken such as driver sizing may fail causing a new reliability issue. This work first discusses these effects and then proposes a mitigation method for thermally induced SE crosstalk based on adaptive body biasing of driver transistors and a temperature sensor. Simulation results demonstrate that, the proposed method can successfully mitigate thermally induced crosstalk noise by 86% on average.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0992-5
Issue No: Vol. 92, No. 2 (2017)

• A new NLEO based technique for the detection of burst–suppression
patterns in multichannel neonatal EEG signals
• Authors: Parisa Mirzaei; Ghasem Azemi
Pages: 255 - 262
Abstract: In this paper, we propose a new method, based on the nonlinear energy operator (NLEO), to automatically detect burst–suppression (B–S) patterns in multichannel newborn electroencephalograms (EEGs). The proposed approach consists of two algorithms: (1) per-brain region B–S detection and (2) global B–S detection. At first, B–S patterns are detected in each channel using NLEO. Average of NLEO values obtained for all the channels is then calculated to detect the presence of B–S patterns in each brain region. After local B–S detection, the global B–S detection algorithm classifies a sample-point as burst if most of regions are bursting. Otherwise, the sample-point is classified as suppression. The proposed method is validated using a database composed of multichannel EEG signals acquired from 6 neonates. The experimental results show that the proposed approach can detect bursts which occur locally and classify global B–S patterns with a very high accuracy of 98%.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0989-0
Issue No: Vol. 92, No. 2 (2017)

• ZigBee-based indoor localization system with the personal dynamic
positioning method and modified particle filter estimation
• Authors: Mahmut Aykaç; Ergun Erçelebi; Noor Baha Aldin
Pages: 263 - 279
Abstract: We introduce a portable Wireless Sensor Network; which characterized by its great precision, fast detection, real time-monitoring and cheapness. The received signal strength indication (RSSI) is used for estimating the location of the target based on the trilateration algorithm. One of the biggest issues when acquiring a precise location is the numerous calculations that are required within particle filtering. Therefore, we have suggested a modified particle filtering (MPF) using a ZigBee model; in order to minimize both error and huge computations within the indoor environment based on the variance and gradient data-resampling. Increasing the particle weight near the estimated position using RSSI localization helps in avoiding undesired estimations. The MPF algorithm has been enhanced to predict a moving target within an indoor location with an average accuracy of approximately 1.5–2 m while consuming less power. The efficient number of particles has been improved, in addition to the estimated error; in comparison to the classical methods. The results prove that our algorithm can effectively meet the general indoor environmental demands with significant improvements over other algorithms and good position’s evaluation.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0969-4
Issue No: Vol. 92, No. 2 (2017)

• Minimum energy point tracking based on adaptive voltage scaling circuit
• Authors: Dongjun Wang; Ping Luo; Yi Bao; Shaowei Zhen; Yajuan He
Pages: 281 - 291
Abstract: In order to realize the low-voltage and low-power dissipation designing of digital circuits, minimum energy point tracking (MEPT) based on adaptive voltage scaling (AVS) circuit is proposed in this paper. With process, voltage and temperature and frequency variance, the supply voltage of digital circuits is decreased dramatically by AVS, and equals to minimum voltage point (MVP), and advantageously in reducing dynamic energy consumption. Based on the MVP, in order to effectively decrease energy consumption of digital circuits, minimum energy point (MEP) of digital circuits is searched via comparing energy dissipation under different supply voltage by MEPT. Therefore, the supply voltage and energy consumption of digital circuits are decreased dramatically by the proposed novel circuit. The proposed circuit has been implemented and fabricated in a standard 0.18 μm CMOS process. The experimental results show that, when operating frequency of load keeps 1.319 MHz, the MVP and MEP of load are 425 and 450 mV, respectively. For operation frequency 5.334 MHz, the MEP changes from 625 to 550 mV with the degree of activity of load difference. Comparing with the traditional fixed voltage circuits, the maximum saving 91% of dynamic energy is realized by the proposed circuit.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0986-3
Issue No: Vol. 92, No. 2 (2017)

• A low load- and cross-regulation SIDO converter using an adaptive current

• Authors: Young-Ho Jung; Seong-Kwan Hong; Oh-Kyong Kwon
Pages: 293 - 301
Abstract: In this paper, a single-inductor dual-output (SIDO) converter is proposed to generate stable output voltages with low load- and cross-regulations for mobile applications. The proposed converter, which operates in the buck–boost or boost mode, employs an adaptive current sensor and a low-dropout regulator with a selectable charge pump to achieve low load- and cross-regulations. In addition, an error amplifier and comparators are implemented to provide stable dual output voltages of 1.8 and 3.3 V at an input voltage range of between 1.0 and 3.2 V. The proposed SIDO converter was fabricated using a 0.18-μm CMOS process technology and occupies a chip area of 1568 μm × 728 μm. The measurement results show that the maximum power efficiency, load-regulation, and cross-regulation are 89.2%, 0.120 and 0.088 mV/mA, respectively, when the load current changes from 10 to 50 mA.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0990-7
Issue No: Vol. 92, No. 2 (2017)

• SDTSPC-technique for low power noise aware 1-bit full adder
• Authors: Preeti Verma; Ajay K. Sharma; Arti Noor; Vinay S. Pandey
Pages: 303 - 314
Abstract: This paper presents a new design named as SDTSPC (Stacked and diode transistor based TSPC) logic for 1-bit full adder to achieve low power noise aware design. Gated transistors are used as stacked transistors from supply to ground path in both sum and carry circuits. One diode connected transistor is placed in series with evaluation transistor to achieve further improved performance in terms of reduced bouncing noise. Analysis is done for power consumption and propagation delay during active and idle mode of operation for both low (25 °C) and high (110 °C) die temperature. Comparing SDTSPC with recently proposed static 1-bit hybrid full adder we get more than 90% improvement in PDP while 30.7% improvement when compared to dynamic TSPC based 1-bit full adder. Corner analysis verifies that our design has the least effect of process exaggeration on PDP and with varying temperature and supply voltage this design keeps lowest value of current among other techniques. SDTSPC design has reduced ground and supply bounce noise. The proposed design is also compared with several previously proposed designs and it is found to have best power delay product (PDP). Further, SDTSPC technique is implemented on 32-bit ripple carry adder as an prolongation of technique.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0994-3
Issue No: Vol. 92, No. 2 (2017)

• A novel 9T SRAM architecture for low leakage and high performance
• Authors: Rohit Lorenzo; Saurabh Chaudhury
Pages: 315 - 325
Abstract: A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0997-0
Issue No: Vol. 92, No. 2 (2017)

• Sorting-free digital median filter for SOCs
• Authors: Saleh Abdel-hafeez; Behrooz Parhami; Arwa Damir
Pages: 327 - 339
Abstract: In this work, we propose a new median-finding algorithm which computes the median value in an input list of integers on-the-fly, without any data-sorting operations. We present a complete digital CMOS implementation, associated timing diagrams, and a formal mathematical proof, which show the overall average number of clock cycles for median-finding to be linearly proportional to the input length, that is, O(N) average-time complexity, when N is less than about 100. Hence, our proposed sorting-free median algorithm is suitable for practical applications on 3 × 3 and 5 × 5 image scan matrices, which are in common use for hand-held devices and entertainment graphics applications. Our proposed hardware precludes the need for SRAM memory or complex circuitry, such as pipelining structures, but rather uses simple registers to hold the input values, performing comparison-swapping on 3 values, along with counting, to derive the median value. There is no restriction on the input sequence with regard to having repeated elements. We evaluate an ASIC design of our sorting-free median algorithm using 90 nm TSMC technology, with 1 V supply voltage and a clock frequency of 2 GHz, on example cases of 3 × 3 (9 values) and 5 × 5 (25 values) image-scan matrices. The resulting designs have a minimum transistor-count ranging from 3202 to 5203. Results show that our sorting-free median algorithm, when used on 512 × 512 images with 8-bit pixels, takes 0.364 and 1.394 ms to scan the complete image using 3 × 3 and 5 × 5 scan matrices, respectively, with the associated power consumption ranging from 3.24 to 1.66 mW.
PubDate: 2017-08-01
DOI: 10.1007/s10470-017-0991-6
Issue No: Vol. 92, No. 2 (2017)

• A multi-band low noise amplifier with strong immunity to interferers
• Authors: Zaira Zahir; Gaurab Banerjee; Mohamad A. Zeidan; Jacob A. Abraham
Abstract: A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable $$\pi$$ network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point ( $$IIP_3$$ ) ranges from −15 to 0 dBm. Implemented in a 0.13  $$\upmu$$ m CMOS technology, the LNA occupies an active area of about 0.29 mm $$^2$$ . This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.
PubDate: 2017-07-20
DOI: 10.1007/s10470-017-1020-5

• Bulk-driven class AB fully-balanced differential difference amplifier
• Authors: Fabian Khateb; Spyridon Vlassis; Tomasz Kulej; George Souliotis
Abstract: This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.
PubDate: 2017-07-17
DOI: 10.1007/s10470-017-1024-1

• Low power VLSI architecture design of BMC, BPSC and PC schemes
• Authors: G. Rajakumar; A. Andrew Roobert; T. S. Arun Samuel; D. Gracia Nirmala Rani
Abstract: Line coding is used to tune the wave form based on the properties of the physical channel. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. The first objective of the proposed work is to design Generation and Degeneration operations of BMC, BPSC and PC techniques in a single chip. The second objective is to reduce the area and power consumption, by modifying the number of MOS devices used to design the system and by adjusting the width of the MOS devices. The proposed system is designed with 59 transistors and simulated using Cadence® 90 nm technology. This occupies 1290 µm2. Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data has equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.
PubDate: 2017-07-17
DOI: 10.1007/s10470-017-1025-0

• A CMOS MF energy harvesting and data demodulator receiver for wide area
low duty cycle applications with 250 mV start-up voltage
• Authors: Teerasak Lee; Henry Kennedy; Rares Bodnar; William Redman-White
Abstract: A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm2 and can deliver 10.3 μW at 3 V to an external battery or capacitor.
PubDate: 2017-07-05
DOI: 10.1007/s10470-017-1000-9

• Special issue: Selected papers from NorCAS 2016, the 2nd Nordic circuits
and systems conference
• Authors: Erik Bruun
PubDate: 2017-07-04
DOI: 10.1007/s10470-017-1023-2

• Lossless grounded FDNR simulator and its applications using OTRA
• Authors: Bal Chand Nagar; Sajal K. Paul
Abstract: In this paper, a new grounded positive lossless frequency dependent negative resistance (FDNR) simulator and two of its applications are presented. The proposed FDNR uses single OTRA and requires five number of passive components; two resistances and three capacitances. The workability of the proposed simulator is demonstrated through the realization of a single resistance controlled oscillator (SRCO) and a fifth order elliptic filter. A detail non-ideality analysis is also done for both FDNR and SRCO. In addition the sensitivity, non-ideality effect and frequency stability analysis of SRCO have been presented. Monte Carlo simulation of the SRCO output has been given and discussed. Moreover, the layout of OTRA, FDNR and SRCO and their post layout simulations in 180 nm are given. PSPICE simulation and experimental results are included to verify theory.
PubDate: 2017-07-04
DOI: 10.1007/s10470-017-1021-4

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