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 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [7 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2352 journals]
• Transmitter leakage cancellation technique for CMOS SAW-less radio
front-ends
• Authors: Maryamsadat Shokrekhodaei; Aminghasem Safarian; Mojtaba Atarodi
Pages: 383 - 394
Abstract: A novel method of transmitter (TX) leakage cancellation is presented to improve the dynamic range of the receiver for wideband code division multiple access applications. The large TX leakage is attenuated within the low noise amplifier (LNA) output using a feed-forward path without any LNA noise figure degradation. A prototype has been designed and laid out in 0.18 μm CMOS technology. It achieves a maximum TX rejection of 18.5 dB with only 5.2 mA current consumption from 1.8 V supply voltage. LNA P-1dBCP (1 dB gain compression point) against TX leakage improves by more than 10 dB. Post layout simulations verify these results. Proposed structure dispels the requirement of off-chip surface acoustic wave filter.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1054-8
Issue No: Vol. 93, No. 3 (2017)

• Impulse response analysis of carrier-modulated multiband RF-interconnect
(MRFI)
• Authors: Yanghyo Kim; Wei-Han Cho; Yuan Du; Jason Cong; Tatsuo Itoh; Mau-Chung Frank Chang
Pages: 395 - 413
Abstract: Impulse response of energy-efficient multiband RF-interconnect (MRFI) is analyzed to quantify its information capacity for transmitting digital data via various types of physical wires. Our analyses in frequency domain (also transferrable to time domain if needed) indicate that a baseband-equivalent impulse response can be established for MRFI under coherently communicated systems. We can further express such response in an explicit form for MRFI with low-pass transmission nature. It also reveals its distinct capability in signal equalization as a result of its RF-carrier down-conversion process. Furthermore, the analysis offers a guidance of how to construct baseband-equivalent impulse response when transmission lines contain non-ideal effects such as frequency notches and in-band ripples.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1058-4
Issue No: Vol. 93, No. 3 (2017)

• A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations
• Authors: Imen Ghorbel; Fayrouz Haddad; Wenceslas Rahajandraibe; Mourad Loulou
Pages: 415 - 426
Abstract: Internet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm2. The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of −116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is −107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 μW from 0.6 V supply voltage, making it suitable for ultra low power applications.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1047-7
Issue No: Vol. 93, No. 3 (2017)

• Making use of semiconductor manufacturing process variations: FinFET-based
physical unclonable functions for efficient security integration in the
IoT
• Authors: Venkata P. Yanambaka; Saraju P. Mohanty; Elias Kougianos
Pages: 429 - 441
Abstract: In a typical design environment, semiconductor manufacturing variations are considered as challenges for nanoelectronic circuit design engineers. This has led to multi-front research on process variations analysis and its mitigations. As a paradigm shift of that trend the present article explores the use of semiconductor manufacturing variations for enhancing security of systems using FinFET technology as an example. FinFETs were introduced to replace high- $$\kappa$$ transistors in nanoelectronic applications. From microprocessors to graphic processing units, FinFETs are being used commercially today. Along with the technological advancements in computing and networking, the number of cyber attacks has also increased. Simultaneously, numerous implementations of the Internet of Things are already present. In this environment, one small security flaw is enough to place the entire network in danger. Encrypting communications in such an environment is vital. Physical unclonable functions (PUFs) can be used to encrypt device to device communications and are the main focus of this paper. PUFs are hardware primitives which rely on semiconductor manufacturing variations to generate characteristics which are used for this purpose. Two different designs of a ring oscillator PUF are introduced, one with low power consumption trading off device performance and one high-performance trading off device power consumption. There is an 11% decrease in power consumption with the low power model along with a simple design and fabrication. Performance of the device can be increased with almost no increase in power consumption.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1053-9
Issue No: Vol. 93, No. 3 (2017)

• A fast training method for memristor crossbar based multi-layer neural
networks
• Authors: Raqibul Hasan; Tarek M. Taha; Chris Yakopcic
Pages: 443 - 454
Abstract: Memristor crossbar arrays carry out multiply–add operations in parallel in the analog domain which is the dominant operation in a neural network application. On-chip training of memristor neural network systems have the significant advantage of being able to get around device variability and faults. This paper presents a novel technique for on-chip training of multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed system utilizes a novel variant of the back-propagation (BP) algorithm to reduce both circuit area and training time. During training, all the memristors in a crossbar are updated in four steps in parallel. We evaluated the training of the proposed system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. The proposed training algorithm trained the nonlinearly separable functions with a slight loss in accuracy compared to training with the traditional BP algorithm.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1051-y
Issue No: Vol. 93, No. 3 (2017)

• Performance and simulation accuracy evaluation of analog circuits with
enclosed layout transistors
• Authors: Guilherme S. Cardoso; Tiago R. Balen
Pages: 455 - 466
Abstract: This paper presents an investigation on two important issues related to the application of enclosed layout transistor (ELT) to the design of analog building blocks: the performance impacts, related to the geometrical asymmetry and capacitances of drain and source terminals and the possible errors of commercial design tools when performing the layout versus schematic and layout extraction tasks. A common-source (CS) amplifier is considered as case study, to which the ELT layout technique is applied. SPICE simulations are performed, considering different methodologies to estimate the effective aspect ratio (W/L) of the ELT devices. The extracted equivalent W/L using a commercial design tool is compared with well-known mathematical models presented in the literature. Simulations were carried out considering three different channel lengths for the CS amplifier. The possibility of setting the transistor drain as inner or outer terminal of the ELT was also investigated. According to obtained results, considering a 0.18 µm technology, there may be significant performance differences, both in DC and AC behavior of the amplifier, and significant divergences of the extracted W/L, when compared to the analyzed models. Additionally, in order to improve the achievable aspect ratio range of square ELTs, we propose to use parallel and series associations of enclosed devices. Depending on the desired W/L, it is also possible to save silicon area with such associations.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1050-z
Issue No: Vol. 93, No. 3 (2017)

• Analysis of effect of feedback current variation in CT Delta-Sigma
modulators with Gm-C integrators
• Authors: Hua Tang
Pages: 467 - 476
Abstract: In design of Continuous-time Delta-Sigma modulators, the feedback DAC (Digital-to-Analog Converter) is typically implemented with a switched current circuit. It is desired that these DAC current circuits provide constant current across clock cycles for each modulator output level. However, when Delta-Sigma modulators are implemented with Gm-C integrators, the DAC feedback current circuits are directly connected to the integrator outputs that may have high-swing voltages and this results in varying DAC feedback current. In this paper, we analyze the effect of feedback current variation caused by high-swing integrator output voltages in Delta-Sigma modulators built with Gm-C integrators. It is shown that feedback current variation may significantly degrade the performance of Delta-Sigma modulators mainly due to the non-linearity of current variation dependence on the integrator output voltage, while mismatch of current variation has minor effect.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1049-5
Issue No: Vol. 93, No. 3 (2017)

• Parametric fault detection of analog circuits based on Bhattacharyya
measure
• Authors: Supriyo Srimani; Manas Kumar Parai; Kasturi Ghosh; Hafizur Rahaman
Pages: 477 - 488
Abstract: This paper presents a fault detection algorithm to detect parametric fault in linear and weakly non-linear analog circuits by Bhattacharyya measure, a statistical metric. Linear feedback shift register (LFSR) generated pseudo-random bit sequences are fed to digital-to-analog converter (DAC) to obtain random analog input stimuli for the circuit under test (CUT). Bhattacharyya coefficient is measured from the probability density function (PDF) of the output. The non-Gaussian auto-regressive model is used to estimate the PDF. Component tolerance is mapped into statistical space by Monte Carlo simulation. The proposed methodology is validated through three benchmark circuits: continuous-time low pass state variable filter circuit, fourth order low pass Chebyshev filter circuit and cascade amplifier. All the circuits are simulated with CADENCE Virtuoso using UMC-180nm technology. Defect screening is also measured with linear regression analysis. Detectability of the proposed method for parametric fault is reasonably large in comparison to functional test method.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1052-x
Issue No: Vol. 93, No. 3 (2017)

• Design and analysis of high Transconductance Current Follower
Transconductance Amplifier (CFTA) and its applications
• Authors: Shweta Kumari; Maneesha Gupta
Pages: 489 - 506
Abstract: A high transconductance Current Follower Transconductance Amplifier (CFTA) is proposed in this paper. The proposed CFTA consists of current follower and transconductance stage with NMOS cross-coupling to enhance the transconductance. The NMOS cross coupling stage forms negative transconductance which results in higher transconductance and wider tuning range without affecting its output swing and bandwidth performance. The proposed CFTA operates at ±0.6 V supply voltage, provides 8.5 mS transconductance and dissipates 1.7 mW power. To verify the high performance of proposed CFTA, a current mode quadrature oscillator and biquad filter have been designed and simulated. Cadence virtuoso schematic composer has been used to verify the performance of proposed CFTA and its applications with TSMC 0.18 µm technology parameters.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1036-x
Issue No: Vol. 93, No. 3 (2017)

• Design and analysis of a high speed double-tail comparator with isomorphic
latch-preamplifier pairs and tail bootstrapping
• Authors: S. Rahmani; M. B. Ghaznavi-Ghoushchi
Pages: 507 - 521
Abstract: Analog comparators are the basic circuit elements in analog to digital converters. In this paper, we present a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping. We used NAND gates because of its higher speed than the NOR gate, as SR-NAND-latch in second stage. The first stage is composed of two parts, preamplifier and voltage boosting block. Preamplifier utilized in a structure similar to latch, and voltages boosting increases the effective supply voltage in clock transition times, results in reduced delay. This results in a desirable speed at lower supply with reduced power consumption. The presented comparator is designed and simulated in both of 0.18-μm and 65-nm CMOS technologies. Simulation results in 0.18-μm show delay of proposed comparator reduced about 35% than conventional comparator. The proposed comparator operates correctly by 2.8 GHz at 1.1 V supply voltage with only 1.3 mW power. The simulation results in 65-nm CMOS technology show that delay and power consumption of isomorphic latch-preamplifier have significant reduction than the results in 180-nm. The proposed comparator is well-suited for mix-signal applications and SAR-ADC.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1048-6
Issue No: Vol. 93, No. 3 (2017)

• Ultra low power beta multiplier-based current reference circuit
• Authors: Shailesh Singh Chouhan; Kari Halonen
Pages: 523 - 529
Abstract: This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1–2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1057-5
Issue No: Vol. 93, No. 3 (2017)

• Design of low leakage process tolerant SRAM cell
• Authors: D. Anitha; K. Manjunathachari; P. Sathish Kumar; G. Prasad
Pages: 531 - 538
Abstract: In this paper, a novel 8 Transistor Static Random Access Memory (SRAM) cell is proposed to reduce the static power introduced by sub threshold and gate leakages, thus reducing the total power dissipation. The power dissipation of the proposed cell in standby mode has reduced considerably, compared to the conventional 6 Transistor SRAM cell and NC SRAM cell. A better stability is achieved in this cell under different process corners. The proposed technique reduces the standby power to 6.22 nW, which is almost negligible compared to that of a 6T SRAM cell (4.23 uW). Hence, the proposed cell is more suitable for standby mode operation. The total power of the proposed cell is reduced by 25.6% and the read-stability is increased by 40% compared to the conventional 6T SRAM cell. Cadence (Virtuoso) tools are used for simulation with gpdk 45-nm process technology.
PubDate: 2017-12-01
DOI: 10.1007/s10470-017-1061-9
Issue No: Vol. 93, No. 3 (2017)

• A novel full-wave rectifier/sinusoidal frequency doubler topology based on
CFOAs
• Authors: Erkan Yuce; Shahram Minaei; Muhammed A. Ibrahim
Pages: 351 - 362
Abstract: A novel topology for realizing voltage-mode (VM) full-wave rectifier/sinusoidal frequency doubler based on current feedback operational amplifiers (CFOAs) and n-channel metal-oxide semiconductor (NMOS) transistors is proposed in this study. The proposed full-wave rectifier structure employs two CFOAs and three enhancement-mode NMOS transistors. With a slight modification, the sinusoidal frequency doubler circuit can be adopted from the full-wave rectifier circuit by replacing a grounded resistor instead of one of the NMOS transistors. Both of the proposed circuits enjoy low output and high input impedance properties which make them convenient for cascading easily with other VM circuits without needing any extra buffer circuits. No passive component matching conditions are needed. The proposed circuits are simulated by using SPICE program to verify the theoretical analysis.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1033-0
Issue No: Vol. 93, No. 2 (2017)

• Memristor-based approximate matrix multiplier
• Authors: Mohsen Nourazar; Vahid Rashtchi; Ali Azarpeyvand; Farshad Merrikh-Bayat
Pages: 363 - 373
Abstract: The parallel structure of matrix multipliers makes them fascinating candidates to benefit from memristors’ high density architecture. This paper first explains a memristor-based analog vector–matrix multiplier suitable for approximate computing. According to the existence of fast and efficient converters, namely, DACs and ADCs, in the field of approximate computing and the programmability of memristors, the presented vector–matrix multiplier is combined with digital circuits which it leads to a matrix–matrix multiplier as an extension. In this work, opamps’ characteristics such as power and speed, distribution of matrix elements, and memristors’ faults have been considered and their effects on performance, accuracy, and efficiency of the proposed multiplier have been analyzed. Also, a new structure for handling negative numbers has been proposed. All the circuits have been simulated using “Ngspice mixed-signal circuit simulator” in C++ programming environment. The simulation results revealed that the multiplier’s analog core brought gains in terms of performance and energy when acceptable ranges of inaccuracies in results could be tolerated.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1029-9
Issue No: Vol. 93, No. 2 (2017)

• Real-time motion estimation diamond search algorithm for the new high
efficiency video coding on FPGA
• Authors: Randa Khemiri; Hassan Kibeya; Hassen Loukil; Fatma Ezahra Sayadi; Mohamed Atri; Nouri Masmoudi
Abstract: High efficiency video coding (HEVC) is the latest video coding standard aimed to replace the H.264/AVC standard according to its high coding performance, which allows it to be mostly suitable for application in high definition videos. However, this performance is accompanied by a high computational complexity due principally to the motion estimation (ME) algorithm. As in H.264/AVC, the ME in HEVC is a highly computational demanding part that takes the largest part of the whole encoding time. Hence, many fast algorithms have been proposed in order to reduce computation, but, the majority, do not study how they can be effectively implemented by hardware. In this paper, two hardware architectures of the diamond pattern search algorithm for HEVC video coding with sequential and parallel techniques, are proposed. These architectures are based on parallel processing techniques. The sequential and parallel VHDL codes have been verified and can achieve at a high frequency on a Virtex-7 field-programmable gate-array design (FPGA) circuit. Compared to other designs, our parallel design provides better efficient implementation of available resources on FPGA. Our architecture can meet the real-time processing of the FHD @ 30 frames per second.
PubDate: 2017-11-10
DOI: 10.1007/s10470-017-1072-6

• Ultra-low-power bulk-driven fully differential subthreshold OTAs with
partial positive feedback for G m -C filters
• Authors: Tripurari Sharan; Priyanka Chetri; Vijaya Bhadauria
Abstract: This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA1 and (1:4) in OTA2. The OTA2 offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency Gm-C filter suitable for bio-signal applications. The proposed OTA2 has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of − 72 dB, for 1.2 Vp–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA1.
PubDate: 2017-11-09
DOI: 10.1007/s10470-017-1065-5

• A closed-loop interface for capacitive micro-accelerometers with
pulse-width-modulation force feedback
• Authors: Tao Yin; Zhenhua Ye; Guocheng Huang; Huanming Wu; Haigang Yang
Abstract: This paper presents an electromechanical closed-loop interface for the high performance capacitive micro-accelerometer. To overcome the problem that the linearity of the traditional analogue force feedback scheme is sensitive to the mismatch in the MEMS transducer, a pulse-width-modulation (PWM) force feedback method is developed in this paper. Elaborate non-linearity analysis of the PWM force feedback and a comparison with traditional analog feedback method is presented. A prototype interface circuit is designed and fabricated in a standard 0.35 μm CMOS process which measures 6.25 mm2. The noise floor of the system is 10 μg/√Hz and the signal bandwidth is 1.2 kHz, respectively. The system shows a DC nonlinearity of 1.6‰ without extra linearization circuit with an input range of ± 1.4 g when interface to a commercial accelerometer device.
PubDate: 2017-11-06
DOI: 10.1007/s10470-017-1064-6

• Over rail-to-rail fully differential voltage-to-current converters for nm
scale CMOS technology
• Authors: Andrzej Handkiewicz; Szymon Szczȩsny; Marek Kropidłowski
Abstract: The converters presented in this paper are based on long channel complementary MOS transistors, instead of the commonly used differential amplifiers or differential transistor pairs which are difficult to implement in low voltage, nm scale CMOS technology. Nonlinearities of drain currents can be cancelled in the fully differential structure. As a result, the low power, nanometre standard digital CMOS technology converters are obtained. Layout examples are designed in 65 nm TSMC technology. Post-layout simulations show that the range of input voltage over rail-to-rail is achieved with very good linearity and reduced harmonic distortion.
PubDate: 2017-11-06
DOI: 10.1007/s10470-017-1071-7

• A 2-GHz 32-bit ROM-based direct-digital frequency synthesizer in
0.13 μm CMOS
• Authors: Xuan Guo; Danyu Wu; Lei Zhou; Huasen Liu; Jin Wu; Xinyu Liu
Abstract: A 32-bit read-only memory (ROM)-based direct digital frequency synthesizer with a maximum operating frequency of 2 GHz is presented. The proposed ROM-based design is capable of increasing the operation speed of traditional ROM-based DDFS by eliminating the complex control circuits and adopting a novel pseudo differential ROM. With a 14-bit partially segmented DAC based on Q2 Random Walk switching scheme, the prototype DDFS produces a minimum spurious-free dynamic range of 46.38 dBc up to Nyquist frequency at the clock frequency of 2 GHz. This 0.13 μm CMOS chip occupies an active area of 0.55 mm2 and dissipates 450 mW with a 1.2-V digital supply and 3.3-V analog supply.
PubDate: 2017-11-06
DOI: 10.1007/s10470-017-1070-8

• Correction to: A subthreshold low-power CMOS LC-VCO with high immunity to
PVT variations
• Authors: Imen Ghorbel; Fayrouz Haddad; Wenceslas Rahajandraibe; Mourad Loulou
Abstract: The original publication of the article contains an error in the author Dr. Loulou’s biography. The correct version of the biography is given below.
PubDate: 2017-10-25
DOI: 10.1007/s10470-017-1068-2

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