Authors:Angsuman Sarkar, Arpan Deyasi, Jyotsna Kumar Mandal, Chandan Kumar Sarkar, Zoran Jakšić Abstract: Nanoelectronic devices of various kinds of are essential for VLSI circuits. The struggle to follow Moore’s law is becoming increasingly difficult and complex, requiring multitudinous novel approaches in order to continue decreasing dimensions of the devices which are already firmly established in the nano-world. As an example, the most advanced state of the art VLSI’s (microprocessors) currently can contain more than 50 billion transistors per chip. As far as the actual physical dimensions are concerned, in 2021 the IBM company announced their 2 nm chip.The efforts behind such achievements are enormous. This special issue on advanced planar nanoelectronics investigates some points of interest related to the physics of such devices, as well as their simulation, thus giving its contribution to the existing trends in this rapidly evolving and constantly expanding field. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Dhananjaya Tripathy, Debiprasad Priyabrata Acharya, Prakash Kumar Rout, Sudhansu Mohan Biswal Pages: 001 - 011 Abstract: This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is a reduction in oxide (SiO2) layer thickness. The parameters like energy and consumed power of FinFET get better when the oxide (SiO2) layer thickness increases. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Remya Jayachandran, Dhanaraj Kakkanattu Jagalchandran, Perinkolam Chidambaram Subramaniam Pages: 013 - 028 Abstract: Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 µm SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 Ω. The gain tuning of up to 5 V/V is achieved with RL equal to 50 Ω, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 kΩ exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Surajit Bosu, Baibaswata Bhattacharjee Pages: 029 - 041 Abstract: High-speed signal computation and communication are an essential part of modern communication that increases optical necessity. Therefore, researchers developed different types of digital devices in the all-optical domain. Due to the versatile gain medium of reflective semiconductor optical amplifiers (RSOAs), it has various important applications in passive optical networks. In comparison with semiconductor optical amplifier (SOA), RSOAs exhibit better gain performance because of their double pass property. Therefore, RSOA shows better switching properties. In this communication, co-propagation scheme of RSOA is used to design and analyze a frequency encoded dibit-based parity generator. Taking the advantages of RSOA like high switching speed, low noise, high gain, and low power consumption, the proposed design achieves these qualities. This design simulated in MATLAB and simulated outputs accurately verify the truth table. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Bibek Chettri, Abinash Thapa, Sanat Kumar Das, Pronita Chettri, Bikash Sharma Pages: 043 - 059 Abstract: In this work we present the atomistic computational study of the adsorption properties of Co doped MoS2 adsorbed ammonia (NH3) and methane (CH4). The adsorption distance, adsorption energy (Ead), charge transfer (Qt), bandgap, Density of States (DOS), Projected Density of States (PDOS), transport properties, sensitivity and recovery time have been reported. The diffusion property of the system was calculated using Nudge Elastic Band (NEB) method. The calculated results depict that after suitable doping of Co on MoS2 monolayer decreases the resistivity of the system and makes it more suitable for application as a sensor. After adsorbing NH3 and CH4, Co doped MoS2 bandgap, DOS and PDOS become more enhanced. The adsorption energy calculated for NH3 and CH4 adsorbed Co doped MoS2 are -0.9 eV and -1.4 eV. The reaction is exothermic and spontaneous. The I-V curve for Co doped MoS2 for CH4 and NH3 adsorption shows a linear increase in current up to 1.4 V and 2 V, respectively, then a rapid decline in current after increasing a few volts. The Co doped MoS2 based sensor has a better relative resistance state, indicating that it can be employed as a sensor. The sensitivity for CH4 and NH3 were 124 % and 360.5 %, respectively, at 2 V. With a recovery time of 0.01s, the NH3 system is the fastest. In a high-temperature condition/environment, the Co doped MoS2 monolayer has the potential to adsorb NH3 and CH4 gas molecules. According to NEB, CH4 gas molecules on Co doped MoS2 has the lowest energy barrier as compared to NH3 gas molecules. Our results indicate that adsorbing NH3 and CH4 molecules in the interlayer is an effective method for producing Co doped MoS2 monolayers for use as spintronics sensor materials. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Pranati Ghoshal, Chanchal Dey, Sunit Kumar Sen Pages: 061 - 070 Abstract: A modified variable resolution semiflash ADC, based on ‘bit segmentation scheme’, is presented. Its speed and comparator count are identical to a normal flash ADC. An 8-bit ADC has 256 different bit combinations. Sixteen consecutive bit combinations from the MSB side – beginning with the first one, remain unaltered for such an ADC. It continues this way till the last group of sixteen bits. In the designed circuit, the four MSB and four LSB bits are determined in the first and second part of the clock. Following the same logic, the bits in a 16-bit ADC can be found out in only two clock cycles by employing only fifteen comparators. It implies that a higher resolution ADC can easily be determined with low power and small die area. It is tested in P-SIM Professional 9 for an 8-bit ADC and curves drawn to establish the validity of the proposal. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Shradha Singh Parihar, Nitin Malik Pages: 071 - 092 Abstract: To integrate network load and line uncertainties in the radial distribution network (RDN), the probabilistic and possibilistic method has been applied. The load uncertainty is considered to vary as Gaussian distribution function whereas line uncertainty is varied at a fixed proportion. A voltage stability index is proposed to assign solar PV-DG optimally followed by application of PSO technique to determine the optimal power rating of DG. Standard IEEE 33- and 69-bus RDN are considered for the analysis. The impact of various uncertainties in the presence of optimally integrated solar PV-DG has been carried out on 69-bus network. The results obtained are superior to fuzzy-arithmetic algorithm. Faster convergence characteristic is obtained and analyzed at different degree of belongingness and realistic load models. The narrower interval width indicates that the observed results are numerically stable. To improve network performance, the technique takes into account long-term changes in the load profile during the planning stage. The significant drop in network power losses, upgraded bus voltage profile and noteworthy energy loss savings are observed due to the introduction of renewable DG. The results are also statistically verified. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Asghar Salehi, Mohammad Hossein Ershadi, Mehdi Baharizadeh Pages: 093 - 106 Abstract: In this paper a new non-isolated high step-up interleaved cascade converter is presented. In comparison with the conventional cascade boost converter, the proposed converter has a higher voltage gain, lower input current ripple and reduced voltage stress for the switches and diodes. Besides, unlike the conventional cascade boost converter, in the proposed converter the input current is shared between inductors and hence the converter can be implemented with lower current rated inductors. Thus, the converter size and conduction losses are reduced and the efficiency is increased. The proposed converter is analyzed and experimental results of a 200W laboratory prototype are presented. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Shailesh Jakodiya, Ram Chandra Gurjar, Radhe Shyam Gamad Pages: 107 - 120 Abstract: This paper proposed a fully MOS-based voltage-controlled oscillator (VCO) with tuning range and low phase noise, replacing the most often used NMOS-based inductor-capacitor tank arranged in cross-coupled topology with a high-Q active inductor. This study mainly focuses on VCO design using a MOS-based active inductor and is implemented and verified using UMC 180nm CMOS technology. The proposed VCO is resistorless and consists of an active inductor, two MOS capacitors, and the buffer circuits. The fundamental principle of this MOS-based VCO concept is to use MOS based inductor to replace the passive inductor, which is an active inductor that gives less area and low power usage. At 1 MHz frequency offset, the phase noise achieved by this proposed configuration is -102.78dBc/Hz. In the proposed VCO architecture, the frequency tuning range is 0.5GHz to 1.7GHz. This VCO design can accomplish this acceptable tuning range by altering the regulating voltage from 0.7V to 1.8V. This suggested architecture of proposed VCO design has the power consumption of 9mW with a 1.8V supply voltage. The suggested VCO has been shown to be a good fit for low-power RF circuit applications while preserving acceptable performance metrics. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Miloš Stevanović, Aleksandar Janjic, Sreten Stojanović, Dragan Tasić Pages: 121 - 136 Abstract: The paper discusses the problem of the energy losses reduction in electrical networks using a battery energy storage system. One of the main research interests is to define the optimal battery location and control, for the given battery characteristics (battery size, maximum charge / discharge power, discharge depth, etc.), network configuration, network load, and daily load diagram. Battery management involves determining the state of the battery over one period (whether charging or discharging) and with what power it operates. Optimization techniques were used, which were applied to the model described in the paper. The model consists of a fitness function and a constraint. The fitness function is the dependence of the power losses in the network on the current battery power, and it is suggested that the function be fit by a n - order power function. The constraints apply to the very characteristics of the battery for storing electricity. At any time interval, the maximum power that the battery can receive or inject must be met. At any time, the stored energy in the battery must not exceed certain limits. The power of losses in the network is represented as the power of injection into the nodes of the network. The optimization problem was successfully solved by applying a genetic algorithm (GA), when determining optimal battery management. Finally, the optimal battery management algorithm is implemented on the test network. The results of the simulations are presented and discussed. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
Authors:Sheilla Atieno Odhiambo, Gilbert De Mey, Carla Hertleer, Lieva Van Langenhove Pages: 137 - 143 Abstract: Capacitors have been made on textile substrates. Stainless steel yarns were used as electrodes. The dielectric material was a mixture of PEDOT and PSS. Stainless steel yarns were used as the electrodes. These capacitors are developed to be inserted in wearable textiles, a research field called smart textiles. After charging, a spontaneous discharge was observed lasting for several hours. By connecting a small resistance or even a short circuit for a certain time, it was observed that the voltage starts to rise afterwards when the load resistor or the short circuit was removed. This phenomenon is known as dielectric absorption. It was observed for the PEDOT:PSS cells that the voltage recovery is relatively high as compared to other materials. PubDate: 2022-03-25 Issue No:Vol. 35, No. 1 (2022)
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