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Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Reha Uzsoy;
Pages: 153 - 153 Abstract: In this first Editorial of 2022, I am happy to welcome Dr. Martin Braun of Intel to our Editorial Board. Dr. Braun has a long record of distinguished accomplishments in the semiconductor industry with Texas Instruments and Intel in a variety of roles. He brings to TSM his expertise in advanced process control, data analytics and factory and supply chain management. We look forward to working with him these coming years. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Alain Diebold;
Pages: 154 - 154 Abstract: The IEEE Transactions on Semiconductor Manufacturing congratulates Yonghwi Kwon and Youngsoo Shin whose paper Optical Proximity Correction Using Bidirectional Recurrent Neural Network With Attention Mechanism was selected as the Best paper for 2021. The paper was selected from all the papers that appeared in 2021 by a team of Associate Editors. This paper applied recurrent neural networks to optical proximity correction for lithographic processing for integrated circuits. The challenge in determining a correction value comes from correlation: correction of one segment affects the correction value of other segments due to the optical proximity effect. This paper broke new ground by showing that Recurrent Neural Networks, which has been mainly applied to time series data, can be effectively applied to spatial data. Clearly, Machine Learning is rapidly moving from R&D into full flow manufacturing where the interplay between each aspect of a single process step has exponential increased in complexity requiring new approaches. Three additional papers were recognized with an Honorable Mention: PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Gian Antonio Susto;Alain Diebold;Andreas Kyek;Chia-Yen Lee;Nital S. Patel;
Pages: 155 - 157 Abstract: The constantly increasing availability of data, the rapid expansion in computational and storage capacities of information technology systems, and algorithmic advances in Machine Learning (ML) and Artificial Intelligence (AI) are making a huge impact in the manufacturing industry for improving efficiency, operations and throughput. The semiconductor industry, being one of the most data-intensive industries, has seen the diffusion of several ML-based technologies in recent years. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Chen-Fu Chien;Wei-Tse Hung;Eddy Ting-Yi Liao;
Pages: 158 - 165 Abstract: Fault detection and classification has been employed to enhance yield and product quality for smart semiconductor manufacturing. For early detection of abnormal events that cause defects, the status variables identification data collected by the sensors embedded in advanced machines can be analyzed to derive the actions for advanced process control and advanced equipment control. However, the validity and effectiveness of fault detection and classification technologies may highly depend on domain knowledge and experience of the process engineers who should redefine the monitoring rules quickly when new process excursion occurred especially when ramping up new technologies and products. Motivated by realistic needs, this study aims to propose a novel strategy to empower intelligent fault detection and classification that employed convolutional neural network to analyze the feature SVID data and determine the conditions of the wafers, while shorten the cycle time for self-learning from domain knowledge and redefining new monitoring rules for fault classification in real time. This approach is validated with an empirical study in a leading semiconductor manufacturing company in Taiwan. The results have demonstrated the practical viability of the developed solution. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Hana T. T. Jebril;Martin Pleschberger;Gian Antonio Susto;
Pages: 166 - 173 Abstract: Data-driven Fault Detection and Classification approaches are becoming increasingly important in semiconductor manufacturing and in other industries aiming at implementing the Zero-defect paradigm. Two of the main challenges in developing such solutions are: (i) the complexity of sensor data, that typically presents themselves in the form of time-series, requiring the employment of time-consuming and possibly sub-optimal feature extraction approaches; (ii) the fact that faults/defects may be caused by more than a single process, but in many cases they are generated by a cascade of processes. In this paper, we tackle the first issue, by considering a two-stage case study consisting of a deposition process and a rapid thermal process. The proposed approach is based on convolutional deep autoencoders employed to perform feature extraction from time-series sensor data in frontend production equipment. We will show on the reported case study, how the proposed approach outperfoms key numbers-based approaches typically used in the industry. To allow reproducibility of the reported results and to foster research in the field, we publicly share the data used in this work. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Sun Ho Kim;Chan Young Kim;Da Hoon Seol;Jeong Eun Choi;Sang Jeen Hong;
Pages: 174 - 185 Abstract: In the semiconductor manufacturing, which consists of significantly precise and diverse unit processes, minute defects can cause significantly large risk, which is directly related to the yield. Through fault detection and classification (FDC), the equipment status is monitored, and the potential causes of faults can be investigated. In the mass production process, unbalanced data problems are also important, including preprocessing methods for data analysis in real time. This study proposes a stepwise FDC method with a process fault detection (FD) and faulty equipment part classification. Fault detection (FD) is proposed using a one-class support vector machine (OC-SVM) to determine anomalies that occur during a process, and fault classification (FC) is followed by the importance between variables that determine whether a fault exists is extracted using extreme gradient boosting (XGBoost). Variables whose importance has been confirmed, are reclassified to a part-level based on the variable name, and defects are notified to the part-level level. An empirical study to validate the proposed data-based framework for fault detection and diagnosis was performed under the scenario of unexpected failure of two ${mathbf {mathrm {SF}}}_{mathbf {6}}/{mathbf {mathrm {O}}}_{mathbf {2}}$ mass flow controllers (MFCs). The experimental results confirmed that the application-oriented proposed framework performed well in FDC operations and showed that it can provide part-level notification to engineers. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Shu-Kai S. Fan;Du-Ming Tsai;Chih-Hung Jen;Chia-Yu Hsu;Fei He;Li-Ting Juan;
Pages: 186 - 197 Abstract: Semiconductor manufacturing plays a crucial role in the world’s economic growth and technology development and is the backbone of the high value-added electronic device manufacturing industry. In this paper, a new anomaly detection framework by means of data visualization is proposed for semiconductor manufacturing. Firstly, t-Distributed Stochastic Neighbor Embedding (t-SNE) in unsupervised learning is used to transform the high-dimensional raw trace data, corresponding to normal wafers, into a two-dimensional map, with the purpose of visually observing the distribution of normal wafers. The t-SNE algorithm cannot be used at run time for a new test sample since it requires the whole dataset for the embedding transformation, and is computationally very expensive. The Multilayer Perceptron (MLP) neural network is then applied as a regressor for the real-time t-SNE embedding of a new test data. The envelope of t-SNE score estimates for a set of normal wafers is circumscribed and used as the 2D control boundary based on the Delaunay Triangulation (D.T.). A new test sample with its MLP estimated embedding points outside the D.T boundary is identified as defective. Lastly, a real-world dataset in semiconductor manufacturing is used to illustrate the proposed data visualization tool for anomaly detection. The experimental results show that a multilayer perceptron in combination with t-SNE and Delaunay Triangulation performs very well for data visualization and automated detection of anomalies. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Po-Cheng Shen;Chia-Yen Lee;
Pages: 198 - 209 Abstract: Semiconductor manufacturers use the wafer bin map recognition (WBMR) system to identify failure modes in processing. This study proposes an WBMR system embedded with three modules: data preprocessing, region classification, and systematic pattern recognition. After using a revised Jaccard index to separate random patterns from systematic patterns, we compare three data augmentation techniques, particularly autoencoder-based, to find the best augmented method that addresses any data imbalance problems between the defect classes. We propose an adaptive algorithm to determine the amount of generated data. We describe the two tools, t-distributed stochastic neighbor embedding (t-SNE) and earth mover’s distances (EMD) we use to quantify and visualize the information content of the augmented dataset. Finally, we use an inception architecture of convolutional neural network (CNN) to improve the WBMR system’s recognition accuracy. An empirical study of the semiconductor assembly manufacturer and a public dataset validate that our proposed WBMR system effectively recognizes different types of defective patterns. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Chau-Shing Wang;Jing-Er Chiu;
Pages: 210 - 219 Abstract: The wire bonding process is one of the most critical processes in semiconductor packaging. The electrical performance and reliability of IC chips must be evaluated by probe testing before wire bonding. In the probe test, the probe usually leaves traces on the surface of the pad. Large probe marks tend to cause a decrease in bond adhesion and so increase the possibility of ball bond lifting from the pads. Shear force is an important measure of the adhesion between the ball and pad. The prediction of the shear force helps to understand the bonding quality in advance. In this study, the six features of the probe marks were extracted by the automatic image recognition method. Using three machine learning techniques (logistic regression, support vector machine, and random forest) based on principal component analysis (PCA), the shear force is estimated based on six features before wire bonding. The results indicate that the proposed PCA-based random forest could identify bad chips with 97.92% accuracy before wire bonding. Unnecessary chips can be found early, and unnecessary wire bonding can be avoided, thereby saving process time and cost. The proposed method would improve the efficiency and quality yield of the semiconductor packaging process. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Chia-Yu Hsu;Yi-Wei Lu;Jia-Hong Yan;
Pages: 220 - 228 Abstract: Predictive maintenance (PdM) is useful for engineers to schedule maintenance flexibly, to operate equipment efficiently, and also to avoid unexpected downtime. Remaining useful life (RUL) prediction is critical for PdM before the need for component replacement. Data-driven approaches have attracted more attention for RUL prediction in flexible production. Compared with statistical-based and conventional machine learning approaches, deep learning-based approaches can extract critical features from raw equipment sensor data without prior knowledge from a domain expert. This study proposes a temporal convolution-based long-short term memory (TCLSTM) network with attention mechanism to extract features from equipment sensor data and to build a regression model for RUL prediction. Temporal convolutional networks (TCN) are used for feature extraction. LSTM and attention layers are used to learn temporal dependencies among the extracted features. The fully connected network consists of dense layers and is used to build the RUL prediction model. To evaluate the effectiveness of the proposed method, an empirical dataset from a semiconductor ion mill etching process was used. According to the comparison results, the proposed TCLSTM network with attention mechanism has the lowest prediction error and outperforms TCN, LSTM, and other machine learning approaches. The experimental results demonstrate the practical viability of the proposed approach. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Christopher I. Lang;Alexander Jansen;Sima Didari;Prashanth Kothnur;Duane S. Boning;
Pages: 229 - 240 Abstract: We present a method for empirically modeling and optimizing variations in sputtering deposition processes using Gaussian Process (GP) machine learning methods. Our predictive models can be trained with limited training data to enable rapid sputtering process tuning. As a first case, we model the effect of process recipe parameters such as chamber pressure and power on sputtered film thickness uniformity. A second more challenging case is also demonstrated: modeling film thickness spatial uniformity as a function of equipment configuration parameters. The effects of the chamber configuration variables are complex, motivating incorporation of prior process knowledge into the GP framework by utilizing a physics-based solver. Because adjusting equipment configuration parameters and obtaining corresponding wafer fabrication data is costly, a key metric is the expected number of tunes required until process constraints are met. Using past experimental data, we show that tunes using the GP-based predictive model are expected to converge in significantly fewer iterations compared to tunes using polynomial, gradient boosted regression tree, multivariate spline, and deep learning based modeling methods. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Huidong Zhang;Tianheng Feng;Dragan Djurdjanovic;
Pages: 241 - 255 Abstract: Control of overlay errors in lithography process in semiconductor manufacturing uses in-process measurements of overlay errors from markers distributed across a wafer to adapt controllable process parameters on the relevant lithography tools in order to minimize future errors. Intuitively speaking, the use of a larger number of measurement markers should lead to improvements in one’s ability to control the overlay errors. However, those gains come with simultaneous increases in the metrology times, which negatively impacts throughput. Therefore, one should carefully and strategically select markers which most efficiently enable suppression of overlay errors. This paper proposes a novel optimization framework that couples a recently introduced approach for robust control of overlay errors in photolithography processes with a strategic selection of overlay measurement markers to enable improved control of overlay errors using a reduced number of measurements. Application of the newly proposed method to the data and models from an industrial-scale semiconductor lithography process shows that the newly proposed combination of the robust overlay control paradigm and optimized marker selection enables improved overlay control, even with a significantly reduced number of markers. Thus, the new methodology enables reduction of measurement times and subsequent overall cycle times, without deteriorating the outgoing product quality. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Ohyung Kwon;Nayeon Lee;Kangil Kim;
Pages: 256 - 265 Abstract: As the critical dimension of transistors has become lower and the stacked layer of semiconductors has become higher, virtual diagnostics to monitor the status of plasma in an etching process has been important because of the reliability of process. In this study, we proposed the model to predict a plasma density of the etch equipment with high accuracy using OES data despite a small number of process conditions. The proposed model could improve the prediction performance of multilayer perceptron by using pre-trained variational auto-encoder as an initializer and had the best performance of several regression methods. At application point of view, it is expected that the model can be used to monitor a plasma density when a wafer is absent from the chamber. Moreover, using the proposed model can more easily understand the status of plasma rather than monitoring thousands of sensor data even without the knowledge about plasma. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Jinli Zhang;Hailong You;Renxu Jia;Xiaowen Wang;
Pages: 266 - 271 Abstract: Chip test escapes can pass the complete test procedure but fail prematurely in system applications. Statistical testing methods can screen chip test escapes by analyzing test data without additional physical measurements. This paper proposes a screening method to reduce chip test escapes using multi-correlation analysis of parameters. This method takes the strength of locational correlation or structural correlation as criterion information. The main steps of the method are as follows: first, quantifying the strength of locational correlation or structural correlation of the chip parameters, then verifying the statistical distribution of the characterization and setting the screening limit, and finally, screening the chip test escapes. Silicon carbide junction barrier Schottky diode (JBS) measurement data are used to verify the method. The results show that when the location information of the chip on the wafer is known, the screening effect based on locational correlation is significantly better than the method specified in AEC Q101. Without additional physical measurements, screening methods based on structural correlation can further identify the remaining chip test escapes in single-parameter screening. This screening method can be used to supplement the existing measurement technology to reduce the cost of packaging, testing, and aging testing. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Katherine Shu-Min Li;Leon Li-Yang Chen;Peter Yi-Yu Liao;Sying-Jyan Wang;Andrew Yi-Ann Huang;Leon Chou;Nova Cheng-Yeh Tsai;Ken Chau-Cheung Cheng;Gus Chang-Hung Han;Chen-Shiun Lee;Jwu E. Chen;Hsing-Chung Liang;Chung-Lung Hsu;
Pages: 272 - 281 Abstract: Spatial failure patterns in wafer defect maps are very useful for root cause analysis, which is essential for yield optimization in the manufacturing process. Especially, the scratch defect type is the most challenging pattern to recognize because the position, shape, size and curvature vary widely from one scratch to another. Discontinuity points within scratches also contribute to the low recognition rate, and such points are often hidden defective dies that become reliability threat. Previous studies on defect pattern identification show that the recognition rate for scratches is among the lowest in all patterns even if the overall accuracy is high. In this paper, we propose a novel scratch pattern recognition method. In this paper, image processing techniques are applied to recognize scratch patterns in wafer maps. The Hough transform is first employed to identify line segments, from which scratches can be reconstructed. In contrast to previous machine-learning based methods, there is no need to train a complicated prediction model so that the computation time is small. The method is validated by using wafer maps from six real products and public data. Experimental results show that the proposed method achieves high recall, precision and accuracy in all cases. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Min Yong Lee;Yeoung Je Choi;Gyeong Taek Lee;Jongkwan Choi;Chang Ouk Kim;
Pages: 282 - 290 Abstract: In semiconductor manufacturing processes, yield analysis aims to increase the yield by determining and managing the causes of low yield. The variable data collected from semiconductor manufacturing processes, in which hundreds of unit processes are implemented according to specific conditions and sequences, are interdependent, and the variables related to previous processes influence the variables in subsequent processes. Therefore, the order of processes should be considered when building a model that searches for the causes of low yield. However, there have been few studies in this area. This paper proposes a low-yield root cause search method considering the order of processes using a long short-term memory with attention mechanism (LSTM-AM) model. Specifically, the LSTM-AM model is applied to data classified according to the process structure of semiconductor products, and the causes of low yield are determined considering the order of processes by extracting attention weights. Experiments are conducted to verify the suitability of the proposed method using real yield data from a semiconductor company. The experimental results confirm that the proposed method outperforms the existing low yield root cause search methods in terms of low yield prediction. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Katherine Shu-Min Li;Xu-Hao Jiang;Leon Li-Yang Chen;Sying-Jyan Wang;Andrew Yi-Ann Huang;Jwu E. Chen;Hsing-Chung Liang;Chun-Lung Hsu;
Pages: 291 - 299 Abstract: Wafer map defect patterns provide valuable information for root cause analysis and yield learning. Previous studies show that supervised machine learning (ML) methods can achieve good defect pattern recognition rate. However, the effectiveness of these methods rely on accurately labeled samples, which leads to two problems. First, oftentimes there are mislabeled data, which may prevent an accurate model from being established. Secondly, defect patterns that are not defined a priori will not be recognized. In this paper, we propose a semi-supervised learning method to deal with these problems. Labeled wafer maps are first used to train a prediction model, and questionable samples are excluded in the process. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns for enhanced labeling. The proposed approach is validated using the WM-811K database. With the proposed method, we are able to define five new defect pattern types, and the 14 defect types can be recognized with high accuracy. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Fuzuo Zhang;Qinghua Tao;Yuanyuan Yan;Xin Li;Fuquan Zhang;Ying Gao;Bing Yang;Huangang Wang;
Pages: 300 - 308 Abstract: Beyond the widely-studied scheduling of wafers within cluster tools, a novel and important perspective is raised in this paper to tackle an upper-level optimization problem in real-world production, i.e., the assignment of hybrid types of wafer lots to a set of cluster tools with parallel modules to minimize the maximum completion time for the lots. The main difficulty in addressing such a problem is that the objective, i.e., the maximum completion time, cannot be calculated explicitly beforehand. To make this problem tractable, the associated maximal overlap among tools is utilized to heuristically evaluate the objective for the problem. Besides, since the cluster tools for processing are identical, we further tackle this problem as a clustering issue. Accordingly, a clustering algorithm based on greedy searching is proposed to allocate wafer lots into cluster tools while minimizing the maximal overlap. To elucidate our method and its significance in real-world production, the wet bench tool in wet cleaning process is taken as a case study. We compare the proposed algorithm with the empirical method in fabs and several intelligent optimization algorithms, and the experimental results verify the effectiveness of our proposed method in terms of improved efficiency. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Hua Shao;Rui Chen;Lisong Dong;Chen Li;Qi Yan;Taian Fan;Yayi Wei;
Pages: 309 - 317 Abstract: Silicon oxynitride (SiOxNy) is a common barrier material in thin-film encapsulation (TFE) organic light-emitting diode (OLED). Substrate defects, voids and film internal defects occur during SiOxNy deposition process and result in poor film conformity and barrier failure. In this work, a mathematical model is built to evaluate experimental deposition rate and a high accuracy two dimensional model is proposed to predict the SiOxNy thin film profile evolution on arbitrary substrate in plasma enhanced chemical vapor deposition (PECVD) process. Based on level set method, image processing algorithm, iterative algorithm and velocity extension algorithm are proposed to ensure the high accuracy simulation. A series of design of experiments (DOEs) of SiOxNy film deposition are conducted to validate the model. For numerical deposition rate, the model predicted value fits the experimental data quite well and the offset in between has a root-mean-square error of 2.33%. For film’s cross section profile, satisfactory agreement between model and scanning electron microscope (SEM) image is obtained, we use the step coverage as quantitative index for film uniformity, and the index’s prediction errors are all less than 4%. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Jing Lu;Ao Deng;Ping Xiao;
Pages: 318 - 323 Abstract: A new polishing pad based on the sol-gel (SG) technique is fabricated and can polish the single crystal diamond (SCD) substrate at high speed. In this work, the base material, fillers, and coating height of the polishing pad are selected. Pressed polymer fiber is used as the base material, talcum powder is chosen as filler, and the coating height of the gel formulation system on the surface of the base material is between 20 and 40 $mu text{m}$ . The surface morphology of SCD substrate was observed with a 3D optical surface profiler. The surface roughness decreased from 78.024 nm to 6.126 nm in 2 h and the material removal rate of the SCD (100) was about 135 nm/h. The Raman spectroscopy result shows that there was phase transformation on the surface of the SCD substrate after polishing. The material removal mechanism was proposed based on the result. During the scratch of the diamond abrasive, the diamond on the surface of the SCD substrate was transformed into amorphous carbon. Then the amorphous carbon was removed mechanically. The new gel polishing pad can polish the SCD substrate with high efficiency. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
José L. Gómez-Sirvent;Francisco López de la Rosa;Roberto Sánchez-Reolid;Antonio Fernández-Caballero;Rafael Morales;
Pages: 324 - 331 Abstract: Semiconductors are essential components in many electronic devices. Because wafers are produced quickly and in large quantities, defects occur that adversely affect semiconductor properties. This makes it necessary to install powerful and robust inspection systems which use artificial intelligence techniques in the early stages of the manufacturing chain in order to detect and classify those defects. This paper proposes a method for defect detection and classification on images of semiconductor wafer materials obtained by means of a scanning electron microscope based in the following stages: (i) use of computer vision techniques to isolate the defect from the background; (ii) use of several descriptors based on shape, size, texture, histogram, and key-points to create a feature vector for the characterization of the defect; (iii) application of an exhaustive search as a feature selection method to determine the optimal subset of feature descriptors; and (iv) evaluation of the feature descriptors by using a support vector machine classifier providing the optimal set with highest F1-score metrics. Finally, the effectiveness of the proposed approach is compared with five popular feature selection methods, reporting better classification results than the latter. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Tee Lin;Ming-Hsuan Hu;Omid Ali Zargar;Wei-Hao Lai;Graham Leggett;
Pages: 332 - 340 Abstract: With the rapid development of semiconductor-based products, semiconductor and integrated circuit (IC) design industries have become indicators of global technological advance in this field. As IC structure becomes smaller and smaller, improved process technology and equipment are necessary to maintain and improve wafer yield rates and quality. Among them, the etching technology in the process has a close relationship with the size of IC structure. According to extensive research and analyses put forward by predecessors, the etching process and methods that affect the yield rates and quality of wafers have been well characterized. This study investigates the spray etching method of the single nozzle and double nozzle. Using computational fluid dynamics software developed by Ansys Fluent, the fluid is injected from the center as the starting point at the same flow rate and speed, and according to 2, 4, and 8 seconds of a different cycle and nozzle forms, moving back and forth to supply liquid on the surface of the 300 mm disc. It is assumed that fluid properties do not change with temperature. Additionally, the chemical reaction and thermal reaction of the etching process are not considered. Changes in the surface flow field resulting from different nozzles and cycle conditions are observed. This study involved setting up a set of flow field visualization systems, replacing the etching liquid with colored water, using a digital camera to capture the relationship between the gray index and the thickness of the water film, and calculate the film thickness. The average film thickness deviation ( ${t}_{avg}$ ) and variable quantity ( ${dt}$ ) were characterized and used as a means to compare performance. The results show that the average film thickness deviation of the double nozzles is higher than the single nozzle, and variable q-antity ( ${dt}$ ) is lower than that of the single nozzles. In general, the double nozzles increase the thickness and stability of the liquid film thickness on the surface of the disc. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Yuxiang Wei;Huan Wang;
Pages: 341 - 352 Abstract: Defect pattern recognition (DPR) of wafer maps can be essential as the accurate classification helps with the fabrication process improvement and thus avoiding further defects. During fabrication, various defect patterns may be mixed. In contrast to single-type DPR, mixed-type DPR can be much more complicated due to the varied spatial features, numerous types, uncertain number of defects, etc. To effectively recognize the mixed-type defects, we proposed a novel multi-scale information fusion transformer framework (MSF-Trans). Specifically, an MSF-Network is proposed to focus on the detailed features of wafer maps, which can also selectively enhance valuable information. Subsequently, the Transformer architecture is introduced, which used multi-head attention mechanism to encode the global context features of wafer maps, thereby modeling the internal relationship between wafer maps and defect patterns. MSF-Trans fully integrates the advantages of convolutional network and transformer in detailed feature learning and global feature learning. MSF-Trans is evaluated on a real dataset with 38 defect patterns. The results show that MSF-Trans has excellent defect recognition ability and is significantly better than the existing deep learning algorithms. Further interpretable analysis indicates that MSF-Trans can effectively recognize the defect pattern and enhance learning of valuable information, which facilitates the recognition of mixed-type defects. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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Authors:
Tee Lin;Omid Ali Zargar;Ming-Hsuan Hu;Che-Yu Lin;Graham Leggett;
Pages: 353 - 362 Abstract: In recent years, the semiconductor industry has continued to advance production techniques and reduce chip feature size. The presence of unwanted moisture during the construction of these features increases the risk of chip defects and reduced yield. During production, smaller integrated circuit (IC) products are more sensitive to the presence of moisture. Therefore, increasing the efficiency of moisture control techniques is very important to decrease the product defect rate. Front opening unified pods (FOUPs) are the plastic enclosure boxes that are designed to provide a cleaner environment for semiconductor wafers during manufacturing and storage. Clean dry air (CDA) or nitrogen (N2) can purge moist air out from the FOUP. For the first time, in this study the effect of purge flow rate on the moisture removal efficiency of a loaded FOUP was examined accurately via smoke flow visualization, particle image velocimetry (PIV) and relative humidity (RH) measurement. Moreover, two different wafer arrangements of top-empty and bottom-empty FOUP were investigated. The findings show the bottom-empty FOUP arrangement results in higher purge performance compared to the top-empty FOUP arrangement. Four purge flow rates of 130, 200, 300 and 400 LPM were examined. The findings also show that when the purge flow rate was set to 200 LPM, the lowest level of relative humidity was measured inside the FOUP. Therefore, the purge flow rate of 200 LPM and the bottom- empty FOUP arrangement can minimize the humidity invasion into a loaded FOUP. The findings from this study can be beneficial to the industry to optimize the purge flow rate and to define the most efficient arrangement of the wafers inside the FOUP during manufacturing and storage. This can increase the product quality and reduce energy consumption by decreasing product defects and increasing yield. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Jung-Chuan Chou;Ruei-Hong Syu;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Yu-Hsun Nien;Yu-Che Lin;Zhen-Rong Yong;Yi-Ting Wu;
Pages: 363 - 371 Abstract: In our study, the dye-sensitized solar cells (DSSCs) with double-layer thin films were fabricated. The active bottom layer of the structure was mainly made of the commercially available titanium dioxide (TiO2) nanoparticles. TiO2 hollow microspheres (THS) were doped into the TiO2 composite material and used as the scattering top layer. The THS prepared by the one-pot hydrothermal method was composed of irregularly arranged nanoparticles. Meanwhile, we also characterized the synthesized hollow TiO2 microspheres by both the scanning electron microscope (FE-SEM) and the X-ray diffractometer (XRD). Besides, we produced DSSCs with different weight percentages (0.5wt%, 1wt%, and 2wt%) of THS photoanodes. The DSSCs based on pure TiO2 showed the short-circuit current (JSC) of 8.33 mA/cm2 and the photovoltaic conversion efficiency (PCE) of 3.75%. The DSSCs manufactured using 1wt%-THS photoanode had JSC of 12.02 mA/cm2 and a PCE of 5.01%. When compared with the JSC and PCE based on pure TiO2 DSSCs, a significant improvement in the structure was observed. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Katherine Shu-Min Li;Leon Li-Yang Chen;Ken Chau-Cheung Cheng;Peter Yi-Yu Liao;Sying-Jyan Wang;Andrew Yi-Ann Huang;Leon Chou;Nova Cheng-Yen Tsai;Chen-Shiun Lee;
Pages: 372 - 374 Abstract: Wafer failure pattern recognition can be used for root cause analysis, which is very important for yield learning. Recently, TestDNA was proposed to improve diagnosis resolution with data collected from wafer test. Previous studies on wafer failure pattern recognition using machine learning achieve good classification results. In this letter, we propose to enhance the classification accuracy with the help of spatial information and ensemble learning algorithms. Experimental results indicate that the proposed method can further improve the accuracy by 8.9%. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Pages: 375 - 376 Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Pages: 377 - 378 Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. PubDate:
May 2022
Issue No:Vol. 35, No. 2 (2022)
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