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Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Edoardo Bonizzoni;Sebastian Hoyos;
Pages: 2393 - 2393 Abstract: This special issue of the IEEE Transactions on Circuits and Systems—Part II: Express Briefs (TCAS-II) continues the successful tradition of the co-publication initiative started few years ago by the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS). This year ISCAS is held in Austin, Texas, United States of America, on May $28^{mathrm{ th}}$ – June $1^{mathrm{ st}}$ , and the process for this Special Issue was carried out as soon as the paper selection was done. As TCAS-II only publishes 5-page briefs, and hence both conference and journal versions of selected works would be largely overlapped, the papers included in this Issue will not appear in the Proceedings of the IEEE ISCAS. Also, similar to what is done by other IEEE Societies, IEEE CASS intends to shift the role of IEEE conferences towards more networking events as well as opportunities for discussions on ongoing research efforts. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Shanthi Pavan;
Pages: 2394 - 2397 Abstract: CMOS fixed- $g_{m}$ bias circuits are, as the name suggests, those that generate a bias current which keeps the transconductance of a MOS transistor equal to a constant (off-chip) conductance. Such circuits are useful in many analog and mixed-signal subsystems like filters and data-converters. This brief derives the textbook fixed- $g_{m}$ bias circuit from first principles, and shows these ideas can be used to generate alternative circuits. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Simon Grosche;Andy Regensky;Alexander Sinn;Jürgen Seiler;André Kaup;
Pages: 2398 - 2402 Abstract: Recently, non-regular three-quarter sampling has shown to deliver an increased image quality of image sensors by using differently oriented L-shaped pixels compared to the same number of square pixels. A three-quarter sampling sensor can be understood as a conventional low-resolution sensor where one quadrant of each square pixel is opaque. Subsequent to the measurement, the data can be reconstructed on a regular grid with twice the resolution in both spatial dimensions using an appropriate reconstruction algorithm. For this reconstruction, local joint sparse deconvolution and extrapolation (L-JSDE) has shown to perform very well. As a disadvantage, L-JSDE requires long computation times of several dozen minutes per megapixel. In this paper, we propose a faster version of L-JSDE called recurrent L-JSDE (RL-JSDE) which is a reformulation of L-JSDE. For reasonable recurrent measurement patterns, RL-JSDE provides significant speedups on both CPU and GPU without sacrificing image quality. Compared to L-JSDE, 20-fold and 733-fold speedups are achieved on CPU and GPU, respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ashira L. Jayaweera;Darukeesan Pakiyarajah;Chamira U. S. Edussooriya;
Pages: 2403 - 2407 Abstract: The number of coefficients of multi-dimensional (M-D) finite-extent impulse response (FIR) filters increases exponentially with the number of dimensions leading to significantly high computational complexities. In this brief, we propose a minimax design method for M-D FIR filters having sparse coefficients, therefore, having low computational complexities. We consider the design of M-D FIR filters with arbitrary frequency responses and low group delays of which the coefficients are complex valued. We formulate the minimax design as a second-order cone programming problem. Design examples confirm that M-D sparse FIR filters designed using the proposed method provide more than 60% reduction in the computational complexity for a similar error in the frequency response approximation compared to M-D FIR nonsparse filters designed using previously proposed minimax methods. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Foad Arvani;Tony Chan Carusone;
Pages: 2408 - 2412 Abstract: Time-correlated single-photon counting (TCSPC) 3D imaging requires the digitization of photon arrival times across an array of single-photon avalanche diodes (SPADs). The most critical performance metrics of time-to-digital converters (TDC) in TCSPC applications are their conversion rate (CR), area, and power consumption. This brief presents a multi-channel RO-based TDC architecture whose power consumption scales with its configurable resolution for power-sensitive applications. Further power savings are achieved by sharing one RO among multiple TDC channels. We have demonstrated that sharing one RO among five channels reduces the power consumption by more than 75% relative to non-shared architectures. Here, a 5-channel 12-bit TDC is fabricated in 65 nm CMOS with an area of 1920 $mu {mathrm{ m}}^{2}$ per channel. It demonstrates CR up to 125 MHz and offers a resolution configurable over the range of 24–133 ps. At a CR of 125 MHz, the TDC power consumption per channel is 0.1 mW and 1 mW per channel at 133 ps and 24 ps resolution, respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Guanzhi Li;Aining Zhang;Qizhi Zhang;Di Wu;Choujun Zhan;
Pages: 2413 - 2417 Abstract: Accurate prediction of a stock price is a challenging task due to the complexity, chaos, and non-linearity nature of financial systems. In this brief, we proposed a multi-indicator feature selection method for stock price prediction based on Pearson correlation coefficient (PCC) and Broad Learning System (BLS), named the PCC-BLS framework. Firstly, PCC was used to select the input features from 35 features, including original stock price, technical indicators, and financial indicators. Secondly, these screened input features were used for rapid information feature extraction and training a BLS. Four stocks recorded on the Shanghai Stock Exchange or Shenzhen Stock Exchange were adopted to evaluate the performance of the proposed method. In addition, we compared the forecasting results with ten machine learning methods, including Support Vector Regression (SVR), Adaptive Boosting (Adaboost), Bootstrap aggregating (Bagging), Random Forest (RF), Gradient Boosting Decision Tree (GBDT), Multi-layer Perceptron (MLP), Convolutional Neural Network (CNN), and Long Short-Term Memory (LSTM), Gated Recurrent Unit (GRU) and Broad Learning System (BLS). Among all algorithms used in this brief, the proposed model showed the best performance with the highest model fitting ability. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ming Yan;Dalton Martini Colombo;Michael S. Freund;Kamal El-Sankary;
Pages: 2418 - 2422 Abstract: This brief presents a PVT (process, voltage, temperature) compensated CMOS resistor to frequency read-out circuit for resistive sensing applications. Resistive sensing is used in different applications, such as olfactory sensing. An accurate read-out circuit is needed to detect the resistance values for on-chip sensor arrays. Existing techniques suffer from PVT variations and require a large silicon chip area. The proposed design offers a simple, accurate, PVT insensitive sensor read-out circuit where a closed-loop configuration, a switched capacitor resistor, operational amplifier integrator, and a voltage-controlled oscillator are used. The design is implemented and fabricated using TSMC 180 nm CMOS technology. The value for the measured sensor’s resistance ranges between 10k and 100M $Omega $ with an accuracy of 0.1% while the chip area is $0.0455{ {mm}}^{{2}}$ with $98.1mu {W}$ power consumption. Also, the settling time for the step resistance change is about $2 mu text{s}$ . PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Mohsen Riahi Alam;M. Hassan Najafi;Nima Taherinejad;Mohsen Imani;Raju Gottumukkala;
Pages: 2423 - 2427 Abstract: Stochastic Computing (SC) is an alternative computing paradigm that promises high robustness to noise and outstanding area- and power-efficiency compared to traditional binary. It also enables the design of fully parallel and scalable computations. Despite its advantage, SC suffers from long latency and high energy consumption compared to conventional binary computing, especially with current CMOS technology. The cost of conversion between binary and stochastic representation takes a significant cost with CMOS circuits. In-Memory Computation (IMC) is introduced to accelerate Big Data applications by removing the data movement between memory and processing units, and by providing massive parallelism. In this work, we explore the efforts in employing IMC for fast and energy-efficient SC system design. We specially focus on memristors as an emerging technology that promises efficient memory and computation beyond CMOS. We discuss the potentials and challenges for realizing efficient SC systems in memory. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Zizhen Huang;Jianlin Zhong;Chunwei Xie;Ruoyang Wu;Xiaojin Zhao;
Pages: 2428 - 2432 Abstract: In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~ $121.8times $ under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Sangwoo Ha;Sangjin Kim;Donghyeon Han;Soyeon Um;Hoi-Jun Yoo;
Pages: 2433 - 2437 Abstract: Computing-in-memory (CIM) shows high energy-efficiency through the analog DNN computation inside the memory macros. However, as the DNN size increases, the energy-efficiency of CIM is reduced by external memory access (EMA). One of the promising solutions is eDRAM based CIM to increase memory capacity with a high density cell. Although the eDRAM-CIM has a higher density than the SRAM-CIM, it suffers from both poor robustness and a low signal-to-noise ratio (SNR). In this brief, the energy-efficient eDRAM-CIM macro is proposed while improving computational robustness and SNR with three key features: 1) High SNR voltage-based accumulation with segmented BL architecture (SBLA), resulting in 17.1 dB higher SNR, 2) canceling PVT/leakage-induced error with common-mode error canceling (CMEC) circuit, resulting in 51.4% PVT variation reduction and 51.4% refresh power reduction, 3) a ReLU-based zero-gating ADC (ZG-ADC), resulting in ADC power reduction up to 58.1%. According to these new features, the proposed eDRAM-CIM macro achieves 81.5-to-115.0 TOPS/W energy-efficiency with 209-to-295 $mu text{W}$ power consumption when 4b $times $ 4b MAC operation is performed with 250 MHz core frequency. The proposed macro also achieves 91.52% accuracy at the CIFAR-10 object classification dataset (ResNet-20) without accuracy drop even with PVT variation. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Marco Sarmiento;Khai-Duy Nguyen;Ckristian Duran;Ronaldo Serrano;Trong-Thuc Hoang;Koichiro Ishibashi;Cong-Kha Pham;
Pages: 2438 - 2442 Abstract: The Internet-of-Things applications use embedded processors to execute lightweight tasks for sensing and management of communications. These applications use different energy reducing strategies such as clock gating and domain switching. However, some power supplies for sensor systems are designed for low-power delivery rather than low-energy battery consumption. Regarding power consumption, it is important to choose the system-based processor in which some variables are taken into account. Depending on the final IoT application, such variables are power consumption, area, performance, and software tools. This brief presents an 8bits and 32bits based System on Chip (SoC) in a General Purpose (GP) CMOS technology. The two processors are implemented in the same tape-out and the same peripherals. The experiment results show a $1.69~mu text{W}$ and $1.76~mu text{W}$ in the 32bits and 8bits SoC, respectively. In terms of area, the 32bits processor is 46% overhead of the 8bits processor, with 6.6-kGE over 3.6-kGE. Finally, the 32bits SoC presents a 1.11 DMIPS and 8bits SoC a 1.38 DMIPS. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Seokchan Song;Soyeon Kim;Gwangtae Park;Donghyeon Han;Hoi-Jun Yoo;
Pages: 2443 - 2447 Abstract: Online training is essential to maintain a high object detection (OD) in various environments. However, additional computation workload, EMA, and high bit precision is the problem of conventional online learning scheme on mobile devices. Therefore, a low power real-time online learning OD processor is proposed with three key features. First, multi-scale linear quantization (MSLQ) and MSLQ-aware PE structure are proposed for low-bit computation. Second, channel-wise gradient skipping is proposed to reduce computation and EMA based on temporal correlation. These schemes reduce ~56% of computation burden and ~30% of EMA, and also improve detection accuracy. Lastly, gradient norm clipping with norm estimation achieves 3.8 mAP improvement at YouTube-Objects dataset by fast adaptation with under 1% of the additional computation. Finally, the proposed online learning OD processor is implemented in 28 nm CMOS technology and occupies 1.2 mm2. The proposed processor achieves 78 mAP of detection accuracy at the YouTube-Objects dataset. Compared to the previous OD processor, this brief shows state-of-the-art performance by achieving 49.5 mW power consumption and 34.4 frame-per-second real-time online learning OD on mobile devices. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Liqun Feng;Woogeun Rhee;Zhihua Wang;
Pages: 2448 - 2452 Abstract: This brief describes an efficient way to reduce the quantization noise of delta-sigma fractional-N PLLs by using an injection-locked oscillator (ILO) in the feedback path. For further noise reduction, the use of cascaded ILOs is proposed. Behaving like a type-I high-order PLL, the cascaded ILOs effectively suppress the quantization noise like a high-order phase-domain low-pass filter (PDLPF). We show that the proposed ILO-based PDLPF significantly improves the out-of-band phase noise for wideband fractional-N PLLs as well as the in-band phase noise for fractional-N bang-bang PLLs (BBPLLs). Post-layout simulation results show that a $Delta Sigma $ fractional-N BBPLL with a 3-stage ILO can achieve the in-band noise reduction of 25 dB without having a nested PLL. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Christian Brignone;Gioia Mancini;Eleonora Grassucci;Aurelio Uncini;Danilo Comminiello;
Pages: 2453 - 2457 Abstract: In recent years, several approaches have been proposed for the task of Sound Event Localization and Detection (SELD) with multiple overlapping sound events in the 3D sound field. However, accuracy improvements have been often achieved at the expense of more complex networks and a larger number of parameters. In this brief, we propose an efficient and lightweight Quaternion Temporal Convolutional Network for the SELD task (QSELD-TCN), which combines the advantages of the quaternion-valued processing and the effectiveness of the Temporal Convolutional Network (TCN). The proposed approach involves a representation of the Ambisonic signal components as a single quaternion and, accordingly, the use of quaternion-valued layers through the whole structure of the neural network. This results in a considerable saving of parameters with respect to the corresponding real-valued model. In particular, a quaternion implementation of the TCN block is presented, exploiting TCN ability in capturing long-term dependencies and the effectiveness of quaternion convolutional layers in grasping correlations among input dimensions. The proposed approach implies less runtime memory and lower storage memory, and it achieves faster inference time with respect to the state-of-the-art methods, making its implementation possible even in devices with limited resources. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Charalampos Eleftheriadis;Georgios Karakonstantis;
Pages: 2458 - 2462 Abstract: This brief presents a new energy efficient Fast- Fourier Transform (FFT) architecture for real-valued applications. The proposed architecture decimates the FFT in time domain with bit-reversed inputs which allows to avoid the use of all costly complex FFTs operations required by the existing schemes. This leads to the reduction of the required memory by a factor of 2 while processing two inputs in parallel, thus doubling the throughput and improving the energy efficiency compared to the current real-valued FFT designs. Furthermore, the output frequencies are computed at their natural order by using a novel memory management technique, without requiring any reordering circuit unlike existing works. In summary for a $N$ point FFT the proposed architecture leads to an increased throughput of 2 samples per clock cycle, requiring $N-2$ memory cells, $8logN-8$ real adders and $3logN-4$ real multipliers. Our results show that we can achieve up to 46.86% energy savings when compared with recent real-valued FFT architectures. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yiming Shi;Zhihai Rong;
Pages: 2463 - 2467 Abstract: Based on two-player two-action and three-action game models, this brief studies the dynamics of Q-learning and Frequency Adjusted Q-(FAQ-) learning algorithms in multi-agent systems, and discloses the underlying mechanisms of these algorithms through the perspective of evolutionary dynamics. It is showed that the dynamics of FAQ-learning or Q-learning with Boltzmann exploration mechanism corresponds to the evolutionary dynamics of selection mechanism with the linear or super-exponential growth, respectively. Hence, FAQ-learning algorithm can converge to the equilibrium state of a game model, whereas, the convergence of Q-learning algorithm is related with the initial states of the population. Therefore, the continuous evolutionary dynamics with selection mechanism can predict the learning process of discrete Q-learning like algorithms well. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ruibin Mao;Bo Wen;Mingrui Jiang;Jiezhi Chen;Can Li;
Pages: 2468 - 2472 Abstract: Nanoscale memristors in a crossbar configuration have demonstrated their ability to accelerate modern computing workloads in various applications, including machine learning, image processing, and data analytics. Modeling the crossbar behavior is critical to software-hardware co-design, but most previous works focused on single or several memristor devices. So, challenges still exist in large-scale crossbar implementations due to non-idealities that only emerge at the system level. In this brief, we build a crossbar model based on experimentally characterized device statistics in large crossbar arrays. We identify different types of imperfections, including statistical device relaxation, fluctuation, peripheral circuits, etc. The experimentally-validated model is then used to co-optimize analog matrix multiplication and neural network applications. Specifically, we propose and implement defect-aware training and verify that the neural network trained with our algorithm can provide better accuracy and reliability when deployed to physical crossbars. Finally, we achieve an experimental accuracy of 93.4% on the MNIST dataset in a physical crossbar by training based on our crossbar model to compensate for statistical stochasticity, 8.4% higher than the vanilla model. More importantly, the accuracy remains larger than 90.0% after two days, while the accuracy with the vanilla model drops to 73.2% because of conductance relaxation. The method is also scaleable to more practical networks and demonstrates a 92.3% CIFAR-10 accuracy with the VGG-16 model on the simulated crossbar model. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Vasileios Ntinas;Alon Ascoli;Ioannis Messaris;Yongmin Wang;Vikas Rana;Stephan Menzel;Ronald Tetzlaff;
Pages: 2473 - 2477 Abstract: Memristors are promising nanoelectronic devices for the implementation of future AI-driven sensor-processor electronic systems, which are essential for the ongoing digitalization of our world. Accurate and computationally cost-effective models for the manufactured memristors are essential for the design of such systems, especially for the simulation of large circuits. In this brief we address the simplification of the JART memristor model, a generic physics-based model of Valence Change Mechanism (VCM) memristors which accurately describes the dynamic behavior of fabricated memristor devices. Furthermore, the proposed model and simplification methodology have the potential to capture the dynamics of a wide range of memristor devices. Importantly, the implicit description of the current through the memristor is replaced by an explicit mathematical relationship. The proper reproduction of memristor dynamics, verified by applying the system-theoretic Dynamic Route Map (DRM) graphical analysis tool, applicable to first-order systems, can be observed through the proposed simplified model and enables the time-efficient simulation of large arrays of VCM devices. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Luís Crespo;Pedro Tomás;Nuno Roma;Nuno Neves;
Pages: 2478 - 2482 Abstract: Transprecision computing targets energy-efficiency with multiple floating-point modules with different precisions to suit application requirements. Variable-precision architectures aim at making a more efficient hardware resource utilization, but they often rely on the IEEE-754 standard, without low-precision arithmetic support. Alternatively, the Posit format is particularly well-suited for low-precision arithmetic. However, for higher precisions, hardware requirements become prohibitive. Accordingly, this brief proposes a new unified Posit/IEEE-754 Vector Multiply-Accumulate (VMAC) unit, comprising a vectorized variable-precision datapath with shared support for the Posit and IEEE-754 formats. A 28nm ASIC implementation resulted in 50% less area and $2.9times $ less power consumption than typical transprecision setups. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Kevin Pelzers;Haoming Xin;Eugenio Cantatore;Pieter Harpe;
Pages: 2483 - 2487 Abstract: This brief presents the analysis, design, and measurements of a compact analog frontend for a catheter-integrated ultrasound imaging digitizer. This frontend requires several functions, including single-ended-to-differential conversion, AC coupling, amplification, anti-aliasing, and the capability to drive the subsequent ADC. To minimize chip area and to maximize power efficiency, a 2-stage frontend was designed, where the active stages are built using self-biased inverter-based amplifiers. The measured prototype in 40nm CMOS offers a gain of up to 15dB and a bandwidth up to 20MHz, while consuming up to $162mu text{W}$ from a 1.1V supply. The peak FoM of 158dB(J−1) and chip area of 0.0054mm2 are in line with state-of-the-art filters, while the proposed design includes the aforementioned extra functionalities as well. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Anil Kumar Nayak;Igor M. Filanovsky;Kambiz Moez;Amalendu Patnaik;
Pages: 2488 - 2492 Abstract: This brief describes a transition from conductor-backed-coplanar waveguide (CB-CPW) with substrate-integrated coaxial line (SICL) to substrate integrated waveguide (SIW). The transition is designed for the C-band frequency range. The CB-CPW slot lines play the main role in widening the bandwidth. These CPW slot lines are providing excitation of both even and odd mode waves in SIW, which improves the impedance bandwidth. Using the proposed concept, the measured single-mode fractional impedance bandwidth of 63.34%, the minimum insertion loss of 0.16 dB, and the overall loss below 25% are achieved. The simulated results are found to be in good agreement with the experimental ones obtained for the prototype developed in the laboratory. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Ajay Singhvi;Aidan Fitzpatrick;Johannes Daniel Scharwies;José R. Dinneny;Amin Arbabian;
Pages: 2493 - 2497 Abstract: Information about the root system architecture of plants is of great value in modern crop science. However, there is a dearth of tools that can provide field-scale measurements of below-ground parameters in a non-destructive and non-invasive fashion. In this brief, we propose a multi-modal, non-contact thermoacoustic sensing system to address this measurement gap and discuss various system design aspects in the context of below-ground sensing. We also demonstrate the first thermoacoustic images of plant material (potatoes) in a soil medium, with the use of highly sensitive capacitive micromachined ultrasound transducers enabling non-contact detection and $cm$ -scale image resolution. Finally, we show high correlation (adj. $R^{2} = 0.95$ ) between the measured biomass content and the reconstructed thermoacoustic images of the potato tubers. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yang Liu;Jing Liu;Jieyu Lin;Mengyang Zhao;Liang Song;
Pages: 2498 - 2502 Abstract: The key to video anomaly detection is understanding the appearance and motion differences between normal and abnormal events. However, previous works either considered the characteristics of appearance or motion in isolation or treated them without distinction, making the model fail to exploit the unique characteristics of both. In this brief, we propose an appearance-motion united auto-encoder (AMAE) framework to jointly learn the prototypical spatial and temporal patterns of normal events. The AMAE framework includes a spatial auto-encoder to learn appearance normality, a temporal auto-encoder to learn motion normality, and a channel attention-based spatial-temporal decoder to fuse the spatial-temporal features. The experimental results on standard benchmarks demonstrate the validity of the united appearance-motion normality learning. The proposed AMAE framework outperforms the state-of-the-art methods with AUCs of 97.4%, 88.2%, and 73.6% on the UCSD Ped2, CUHK Avenue, and ShanghaiTech datasets, respectively. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Hao Zhang;Seok-Bum Ko;
Pages: 2503 - 2507 Abstract: In this brief, a variable-precision approximate floating-point multiplier is proposed for energy efficient deep learning computation. The proposed architecture supports approximate multiplication with BFloat16 format. As the input and output activations of deep learning models usually follow normal distribution, inspired by the posit format, for numbers with different values, different precisions can be applied to represent them. In the proposed architecture, posit encoding is used to change the level of approximation, and the precision of the computation is controlled by the value of product exponent. For large exponent, smaller precision multiplication is applied to mantissa and for small exponent, higher precision computation is applied. Truncation is used as approximate method in the proposed design while the number of bit positions to be truncated is controlled by the values of the product exponent. The proposed design can achieve 19% area reduction and 42% power reduction compared to the normal BFloat16 multiplier. When applying the proposed multiplier in deep learning computation, almost the same accuracy as that of normal BFloat16 multiplier can be achieved. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Yang Liu;Jing Liu;Mengyang Zhao;Shuang Li;Liang Song;
Pages: 2508 - 2512 Abstract: Video anomaly detection (VAD) under weak supervision aims to temporally locate abnormal clips using the easy-to-obtain video-level labels. In this brief, we introduce the underlying thought of unsupervised VAD to the weakly supervised VAD and propose a collaborative normality learning framework to obtain more discriminative deep representations. Specifically, a deep auto-encoder is first trained in an unsupervised manner to learn the prototypical spatial-temporal patterns of normal videos. Then, both the normal and abnormal videos are used to train a regression module, where the objective is to make the average score of the abnormal videos higher than the maximum score of the normal videos. Finally, the clips in abnormal videos with an anomaly score lower than the average are regarded as normal and used to fine-tune the trained auto-encoder. The unsupervised auto-encoder collaborates with the weakly supervised regression model to extract prototypical features of normal clips, making the learned features of normal and abnormal events more distinguishable. Experimental results on three benchmark datasets show that the proposed framework achieves comparable performance to the state-of-the-art methods. Additionally, the results of ablation studies demonstrate the validity of collaborative normality learning. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Madhav Pathak;Shuo Xie;Cheng Huang;Ratnesh Kumar;
Pages: 2513 - 2517 Abstract: Triboelectric Nanogenerators (TENG) suitable for mechanical energy harvesting typically have ultra-high open-circuit voltage in several hundreds of volts, challenging the energy extraction circuit (EEC) design required for charging load battery/capacitor. Here, we present a novel multi-shot switched EEC that extracts energy in multiple discrete steps to regulate the TENG voltage below the breakdown limit of the technology (70 V in our case), making it suitable for Integrated Circuit (IC) implementation. The proposed strategy maintains high TENG voltage just below the breakdown limit to offer a high electrostatic retardation, enhancing the work done against it by the mechanical source in the form of transduced electrical energy. Mathematical derivation of the circuit’s output shows a constant transduction power at all load voltages, fully eliminating Maximum Power Point (MPP) Tracking and saving power for the same. The design and simulation of the proposed EEC in TSMC 0.18 $mu text{m}$ BCD process achieve a maximum power conversion efficiency of 63.3% and a 1.91x gain over even an ideal conventional Full Wave Rectifier (FWR) circuit at its optimal MPP load (gain will be higher for a real FWR implementation). PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Jinge Li;Chunqi Shi;Zhaoqi Chen;Hao Deng;Jinghong Chen;Runxi Zhang;
Pages: 2518 - 2522 Abstract: This brief presents a 24 GHz dual-mode frequency synthesizer designed in a 55-nm CMOS technology supporting both Doppler and frequency modulated continuous wave (FMCW) radars. The effects of chirp linearity and delta-sigma modulation (DSM) resolution on the rms FM error is analyzed. A design procedure for the PLL loop bandwidth and time interval of the frequency step to reduce the rms FM error is proposed. A voltage-controlled oscillator (VCO) featuring a four-coil transformer load is developed providing differential local oscillation (LO) signals for the transmitter (TX) and quadrature LO signals for the 2-channel receiver (RX). The prototype is designed with a loop bandwidth of 350 kHz, a frequency step time interval of $2 ~mu s$ , and a VCO tuning linearity of 26%. In the FMCW mode, it achieved an rms FM error of 68.8 kHz over a 1.25 GHz chirp bandwidth. In the Doppler mode, the VCO operates in the free-running mode to save power consumption. An 8-bit digital-to-analog converter (DAC) is used to provide the VCO control voltage compensating process and voltage variations. The free-running VCO operates at a 24.125 GHz and has a frequency error of less than 1 MHz. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Weijun Ma;Junyuan Fang;Jiajing Wu;
Pages: 2523 - 2527 Abstract: Large scale networked systems are playing an indispensable role in modern society, and thus the robustness of these systems against random failures or malicious attacks has become a critical research issue. As a major threat to network robustness, cascading failures have attracted increasing research attention in the past decades. Previous studies have put forward many heuristic methods to investigate the network robustness against cascading failure problems. However, most of them assume that the attackers can obtain the complete topology information of the network, which may not be available in practice. To tackle this problem, we use the link prediction methods to restore the missing information (i.e., the topological structure of networks) of the network first, and then utilize the predicted information to further help distinguish the critical nodes in the network systems from the attacker’s perspective. Simulation results on both synthetic and real-world networks have demonstrated the effectiveness of the proposed method. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Tao Huang;Dan Lin;Jiajing Wu;
Pages: 2528 - 2532 Abstract: Accounts in Ethereum are found to be involved in various services or businesses. Account classification can help us detect illegal behavior, track transactions, and de-anonymize the Ethereum transaction system. In this brief, we make use of Graph Convolutional Network (GCN) to solve the account classification problem in Ethereum. We model the Ethereum transaction records as a large-scale transaction network and find that the network is with high heterophily, in which accounts with different features and different labels are connected. In order to solve this problem, we propose a GCN-based model called EH-GCN. The experimental results on a realistic Ethereum dataset show that the proposed method achieves the most advanced classification performance, and results on benchmarks show it produces a competitive performance under homophily. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Issa Salameh;Eby G. Friedman;Shahar Kvatinsky;
Pages: 2533 - 2537 Abstract: Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, $2phi $ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel $2phi $ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These $2phi $ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Authors:
Yijun Xia;Jieli Liu;Jiajing Wu;
Pages: 2538 - 2542 Abstract: In recent years, the losses caused by phishing scams on Ethereum have reached a level that cannot be ignored. In such a phishing detection scenario, network embedding is seen as an effective solution. In this brief, we propose an attributed ego-graph embedding framework to distinguish phishing accounts. We first obtain the account labels from an authority site and the transaction records from Ethereum on-chain blocks. Then we extract ego-graphs for each labeled account to represent it. To learn representations for ego-graphs, we utilize non-linear substructures sampled from ego-graphs and use a skip-gram model. Finally, a classifier is applied to graph embeddings to predict phishing accounts. To overcome the limit that transaction attributes are not encoded into ego-graph embeddings, we give nodes and subgraphs with richer attribute-based semantics. Specifically, we propose a novel node relabeling strategy based on Ethereum transaction attributes including transaction amount, number, and direction, and differentiating nodes and subgraphs by new labels. Through this, structural and attributed features of the Ethereum transaction networks can be learned at the same time. Experimental results show that our framework achieves effective performance on class imbalanced phishing detection on Ethereum. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
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Authors:
Nikos Temenos;Paul P. Sotiriadis;
Pages: 2543 - 2547 Abstract: Non-scaling Stochastic Computing adder and subtracter architectures are introduced. They are modeled using Markov Chains to obtain important statistical properties enabling their design optimization. To demonstrate their efficacy, they are used to realize a stochastic computing-based image sharpening filter which is simulated in MATLAB and Synopsys. The filter’s computational efficiency is showcased with standard image processing metrics while its hardware resources are compared to those of the standard binary filter, highlighting the advantages of the proposed approach. PubDate:
May 2022
Issue No:Vol. 69, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
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