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Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Domine M. W. Leenaerts;
Pages: 1243 - 1243 Abstract: This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) features a Special Section on key invited papers presented at the 2021 Radio Frequency Integrated Circuits Symposium (RFIC Symposium), held in hybrid mode on June 6–8 (in-person) and June 21–July 20, 2021 (online). The RFIC Symposium is the world’s premier conference focused on RF and millimeter-wave (mm-wave)-integrated circuits and systems technology. It shares the venue with the IEEE MTT-S International Microwave Symposium (IMS) as part of the Microwave Week and is co-sponsored by the IEEE Solid-State Circuits Society. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Naga Sasikanth Mannem;Tzu-Yuan Huang;Elham Erfani;Sensen Li;David Munzer;Matthieu R. Bloch;Hua Wang;
Pages: 1244 - 1256 Abstract: A primary advantage of antenna arrays is their spatial selectivity, which has been widely utilized to support various applications, such as beam-steering, blocker rejection, massive multi-in--multi-out (MIMO), targeting communication, radar, and imaging. In this article, we exploit and engineer this spatial selectivity in an MIMO array for directionally secured wireless communication. We propose constellation decomposition array (CDA) and spatial carrier aggregation (SCA) schemes to achieve high throughput keyless physical layer security using antenna arrays. In CDA, lower order quadratic-amplitude modulation (QAM) signals are fed into an MIMO array and are spatially combined in the target direction to realize desired higher order QAM signals but distort the modulation in unintended directions. In SCA, we feed different carriers to different elements in an MIMO array to perform spectral carrier aggregation spatially. In addition, we adopt temporal swapping to further enhance security by creating one-to-many symbol mapping in unintended directions. The concept is demonstrated on an eight-channel MIMO transmitter (TX) fabricated in 45-nm CMOS silicon on insulator (SOI) and on-board antenna array for over-the-air (OTA) measurements. Using four channels of the TX array in the CDA mode, an information beamwidth of 5°/10° is realized by spatially constructing a single carrier 64QAM signal using three QPSK signals or one QPSK signal plus one 16QAM signal with a total 64QAM data rate up to 3 Gb/s. Using SCA with two carriers of 64QAM signals and temporal swapping, an rms error vector magnitude (EVM) of 6.3% at broadside with an aggregated data rate of 1.2 Gb/s is achieved, in contrast to greatly distorted rms EVM of 10% at only 4° angle. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Venumadhav Bhagavatula;Fan Zhang;Chechun Kuo;Anirban Sarkar;Ashutosh Verma;Tienyu Chang;Xiaohua Yu;Dae-Young Yoon;Ivan Siu-Chuang Lu;Sang Won Son;Thomas Byunghak Cho;
Pages: 1257 - 1266 Abstract: A fifth-generation (5G) frequency range 2 (FR2) transmitter front end with a fully integrated power detector for enabling closed-loop power control is presented. The power detection path includes a miniature broad-side directional coupler, a sense pair, and a current-mode successive approximation analog-to-digital converter. The stacked power amplifier (PA) implemented in a 28-nm CMOS silicon on insulator (SOI) process delivers 12.5-dBm output power with a power-added efficiency of 10% and an error vector magnitude (EVM) lower than −25 dB with a CP-OFDM/64-QAM/400-MHz bandwidth signal. The PA supports 5G frequency bands n257/n258/n261 covering a frequency range from 24.25 to 29.5 GHz. With a matched output load, the power detector has less than ±0.15-dB error over a 15-dB power dynamic range and 85° temperature range. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Hyun-Chul Park;Seokhyeon Kim;Jooseok Lee;Junho Jung;Seungjae Baek;Taewan Kim;Daehyun Kang;Donggyu Minn;Sung-Gi Yang;
Pages: 1267 - 1279 Abstract: We present a broadband parallel-combined compact Doherty power amplifier (PA) in a 28-nm bulk complementary metal–oxide–semiconductor (CMOS) device technology for fifth-generation (5G) millimeter-wave (mm-Wave) frequency band (n257, n258, and n261) applications. The proposed Doherty PA has a single transformer (TF)-based output matching network and an equivalent quarter-wavelength line placed between the carrier and peaking amplifiers, absorbing transistors’ output parasitic capacitances. Therefore, the Doherty PA occupies a very small die area and has a wide bandwidth characteristic compared with the conventional Doherty PA output matching network topologies (e.g., parallel- and series-combined Doherty PA output matching networks). The two-stage differential Doherty PA is implemented, which shows a saturation output power ( $P_{mathrm {OUT}}$ ) of >18.8 dBm and a peak power-added efficiency (PAE) of >30% at 27 GHz. It also exhibits a linear $P_{mathrm {OUT}}$ of 12.4 dBm and an average PAE of 20.2% for 100 MHz 5G NR signal ( $P_{mathrm {OUT}}$ of 11.4 dBm and PAE of 18.1% for 8 $times $ 100 MHz carriers) at the EVM of −25 dB. Over the frequency range of 24.5–29.5 GHz, the PA achieves a linear $P_{mathrm {OUT}}$ of >11.2 dBm and a PAE of >14.5% (drain efficiency >20.8%). This PA occupies 640 $mu text{m},,times $ 250 $mu text{m}$ (core only) and is successfully integrated into a 32-channel RF phased-array transceiver IC for the first time. The IC die area is 10.2 mm $times $ 6.4 mm and consumes about 120 mW per channel at $P_{mathrm {OUT}}$ of 10.0 dBm. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Abdulrahman Alhamed;Gökhan Gültepe;Gabriel M. Rebeiz;
Pages: 1280 - 1290 Abstract: This article introduces a millimeter-wave (mm-wave) multi-band transmit (Tx) phased-array design supp- orting the fifth-generation (5G) new radio frequency range 2 (NR FR2) bands. An eight-element phased-array module is presented employing two wideband 16–52 GHz $4{times }1$ Tx beamformer chips and tapered slot Vivaldi antenna array. The beamformer chips are designed in a SiGe BiCMOS process and flipped on a printed circuit board (PCB). The SiGe integrated circuit (IC) has four differential radio frequency (RF) beamforming channels each consisting of an active balun, analog adder-based phase shifter (PS), variable gain amplifier (VGA), and a two-stage class-AB power amplifier (PA). The RF input signal is distributed to the four channels using a compact Wilkinson network. The measured peak gain is 28.3 dB with 13.5–14.7 dBm output $P_{1{mathrm {dB}}}$ and 14–15.4 dBm $P_{{mathrm {sat}}}$ at 20–50 GHz. Each channel dissipates 250 mW from 2 V and 3-V supplies at $P_{1,{mathrm{ dB}}}$ . The beamformer chip is tested using 64-QAM waveforms and achieves a data rate of 2.4 Gb/s at 5.2% rms EVM and 9.6-dBm average power. The eight-element phased-array module shows a broadband performance with excellent patterns and ±60° scanning capability and with a peak effective isotropic radiated power (EIRP) of 32–34 dBm at 19.5–51 GHz. At an EIRP of 21–22 dBm, 400-MHz 256-QAM 5G-NR compliant waveforms are transmitted with < 2.98% EVM demonstrating 5G NR FR2 operation. T- the author’s knowledge, this work achieves the highest bandwidth phased array with a peak EIRP of 34 dBm enabling the construction of multi-standard/multi-band 5G phased-array systems. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Tolga Dinc;Sachin Kalia;Siraj Akhtar;Baher Haroun;Benjamin Cook;Swaminathan Sankaran;
Pages: 1291 - 1299 Abstract: This article presents high-efficiency power amplifiers (PAs) implemented in Texas Instruments’ (TI) 130-nm BiCMOS process for $V$ - and $E$ -band millimeter-wave (mmWave) radar sensors. A new Class-E output network based on a doubly tuned (DT) transformer is proposed to enable high-efficiency mmWave operation. The proposed Class-E network allows increasing PA device size beyond the traditional Class-E design limits while preserving nonoverlapping Class-E current and voltage waveforms. Design examples for single-ended and differential implementation of the proposed Class-E network are presented in this article. Three PA prototypes (a 79-GHz two-stage PA, a 63-GHz single-stage PA, and a 79-GHz single-stage PA) have been designed and fabricated in a high-volume production 130-nm BiCMOS process. A Class-E interstage network with a split-and-combine 45° transformer is employed in the two-stage PA to ease driving the last stage PA devices. Device layout optimization for improved efficiency is described in this article. The measurement results achieve a peak power-added efficiency (PAE) of 30.5%/34.7%/32.6% with an output power of 17/18.1/17 dBm for the 79-GHz two-stage, 63-GHz single-stage, and 79-GHz single-stage PAs, respectively. To the best of our knowledge, these are the record PAE numbers reported for $V$ - and $E$ -band PAs in any silicon process, demonstrating the efficacy of the proposed DT transformer-based Class-E output network. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Xinyan Tang;Johan Nguyen;Giovanni Mangraviti;Zhiwei Zong;Piet Wambacq;
Pages: 1300 - 1313 Abstract: This article presents novel methodologies and practical design considerations for a $D$ -band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology for beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch (SW) topology, including the power amplifier (PA) output and the low noise amplifier (LNA) input matching networks, to minimize the losses in both Tx and Rx modes. Based on this synthesis, an asymmetric T/R SW topology is realized with intrinsic electrostatic discharge (ESD) protection. Both the stacked-field-effect transistor (FET) PA and LNA adopt differential topologies with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics. Passive gain-boosting techniques are used for both PA and LNA to enhance different TRx specifications. A reusable unit-cell layout strategy is applied for transistor arrays to accelerate the multiple-stage PA implementation and maintain uniform performance and minimal parasitics. At 140 GHz, the Tx achieves a power gain $G_{p}$ of 33.6/35.7 dB, a saturated output power $P_{mathrm{ sat}}$ of 12.5/14.7 dBm, a peak power-added efficiency (PAE) of 10.8/11.3%, and an output 1-dB compression point (OP1dB) of 9.4/11.2 dBm with nominal/boosted supplies. An average output power ( ${P_{out}}_{avg}$ )/PAE of 4.9 dBm/2% is obtained for a 4-GHz bandwidth 64-QAM single-carrier signal at an error-vector magnitude (EVM) of −24.8 dB. Moreover, its Tx-mode reliability has been assessed. At 140 GHz, the Rx achieves a 20-dB $G_{p}$ , a −24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA/LNA core area of 0.024/0.032 mm2, respectively. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Yunfan Wang;Wenhua Chen;Xingcun Li;Jiaxian Chen;Long Chen;Fei Huang;Shuyang Li;Zhaozhuo Wang;
Pages: 1314 - 1331 Abstract: In this article, a highly efficient terahertz (THz) beam-steerable integrated radiator based on tunable boundary conditions is presented. The boundary conditions seen by the central slot radiator are tuned by the switched slots, and the corresponding radiation patterns can be altered. This technique enables a beam-steerable THz antenna with high radiation efficiency. In addition, the DC-THz efficiency of the harmonic voltage-control oscillator (VCO) is boosted through the 2-D harmonic boosting technique. Based on the two techniques above, the THz beam-steerable radiator has been implemented in a 130-nm SiGe BiCMOS process ( $f_{T}/f_{mathrm {max}} =300$ /450 GHz). Without silicon lens, it achieves 60° scan ranges in the $E$ -plane, an equivalent isotropic radiated power (EIRP) of 2.2 dBm, −2.8 dBm radiation power, 0.91% DC-THz efficiency, and the tuning range of 11.5% for the supply of 1.7 V. With silicon lens, it achieves the EIRP of 21.66 dBm, 0.56-dBm radiation power, 2.22% DC-THz efficiency, and tuning range of 10.8% for the supply of 1.6 V. Among the silicon-based beam-steerable radiators over 300 GHz, it achieves state-of-the-art dc-to-THz efficiency. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Siwei Li;Gabriel M. Rebeiz;
Pages: 1332 - 1343 Abstract: This article presents fully integrated power amplifiers (PAs) with eight-way low-loss power combining for $D$ -band applications in the GlobalFoundries CMOS 45RFSOI process. The eight-way power combining (four-way differential) common source (C.S.) and cascode amplifiers are implemented using four-stage differential PA unit cells as building blocks. The eight-way power combining network is composed of a four-way balun-short-transmission-line (balun-STL) combiner and a conventional quarter wavelength transmission line (QWL TL) combiner. The simulated two-stage eight-way combiner in situ (loaded) ohmic loss is only 1.1–1.4 dB at 130–150 GHz. The eight-way power-combining C.S. amplifier has a small-signal gain of 24 dB at 140 GHz with a 1.2-V supply and a 3-dB bandwidth of 131–150 GHz. The saturated output power (Psat) and output 1-dB compression point (OP1 dB) are 16.8–17.5 and 13–14.2 dBm at 130–150 GHz, respectively. The corresponding peak power-added efficiency (PAE) is 11.7%–14.2%. The eight-way power combining cascode amplifier achieves a small-signal gain of 24.8 dB at 135 GHz with a 3-dB bandwidth of 133–148 GHz. The corresponding Psat is 16.3–19 dBm at 125–150 GHz with a peak PAE of 6.5%–12.1%. To the best of our knowledge, these PAs achieve the highest Psat and OP1 dB at the $D$ -band in CMOS. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Muhammad Ibrahim Wasiq Khan;Jongchan Woo;Xiang Yi;Mohamed I. Ibrahim;Rabia Tugce Yazicigil;Anantha P. Chandrakasan;Ruonan Han;
Pages: 1344 - 1357 Abstract: This article reports the first chip-based demonstration (at any frequency) of a transceiver front end that transmits and receives electromagnetic waves with a helical distribution of wavefront phase [namely, orbital angular momentum (OAM)]. The CMOS chip consists of eight 0.31-THz modulator/detector units, with an integrated patch antenna, which are placed in a uniform circular pattern with a diameter of one free-space wavelength. The chip transmits OAM modes that are digitally switched among the $m,,=0$ (plane wave), +1 (left-handed), −1 (right-handed), and $(+1)+(-1)$ (superposition) states. The chip is also reconfigurable into a receiver mode that identifies different OAM modes with >10-dB rejection of mismatched modes. The array, driven by only one 310-GHz signal generation path, has a measured EIRP of −4.8 dBm and consumes 154 mW of dc power in the OAM source mode. In the receiver mode, it has a measured conversion loss of $sim 30$ dB and consumes 166 mW of dc power. Using a low-cost 65-nm bulk CMOS technology, the terahertz (THz)-OAM chip has an area of only 2.1 $times $ 2.6 mm2, which is the smallest among all prior OAM prototypes. The output OAM beam profiles and modes’ orthogonality are experimentally verified. The dynamic mode switching capability of the chip is also verified in the time domain across 1-m distance, and a full-silicon OAM link is demonstrated. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Xiaoteng Zhao;Yong Chen;Lin Wang;Pui-In Mak;Franco Maloberti;Rui P. Martins;
Pages: 1358 - 1371 Abstract: This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input between 47.6 and 58.8 Gb/s. The core area is 0.056 mm2. Both the achieved energy efficiency (0.22–0.25 pJ/bit) and the acquisition speed [9.8 (Gb/s)/ $mu text{s}$ ] compare favorably with the state of the art. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Sachin Kalia;Salvatore Finocchiaro;Tolga Dinc;Bichoy Bahr;Ashwin Raghunathan;Gerd Schuppener;Siraj Akhtar;Tobias Fritz;Baher S. Haroun;Benjamin Cook;Swaminathan Sankaran;
Pages: 1372 - 1384 Abstract: A 20-GHz fractional- ${N}$ analog phase-locked loop (PLL) leveraging a novel high-speed charge pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable 2.5-GHz frequency reference using Texas Instrument’s indigenous bulk acoustic wave (BAW) resonator is demonstrated. The low noise high-frequency reference allows for significant lowering of the division modulus leading to enhanced suppression of CP, phase-frequency detector (PFD), and loop-filter (LF) noise. A low noise class-C transformer-coupled voltage-controlled oscillator (VCO) further allows for excellent jitter performance over wide integration bandwidths (BWs) while still working with a nominally low PLL loop BW. Capability is built into the design to characterize the PLL with either BAW or external reference. The design is implemented and fabricated in the GlobalFoundries 22-nm fully depleted silicon on insulator (FD-SOI) process. The class-C VCO is measured to be centered at $sim $ 19.7 GHz with 16% tuning range (TR) while maintaining a flat $vert {rm FOM}vert sim $ 188 dBc/Hz (10-MHz offset) over the entire TR. The PLL measures an excellent jitter and $vert {rm FOM}_{j}vert $ of 65/92 fs and $sim $ 249/245 dB in integer/fractional modes, respectively. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Kejian Shi;Hooman Darabi;Asad A. Abidi;
Pages: 1385 - 1396 Abstract: An electrical balance duplexer (EBD) supports dual-band TX-RX isolation enabling frequency-division duplexing (FDD) operation at 5-7 GHz for Wi-Fi 6/6E. A programmable balance network in the EBD can balance the antenna impedance ( $Z_{text {ANT}}$ ) in the TX channel and RX channel independently and simultaneously. An on-chip passive bandstop filter as a part of the balance network is implemented, achieving sub-2-dB passband insertion loss (IL) and >20-dB stopband rejection with 10% frequency spacing. This filter separates two impedance tuners in the balance network and enables the independent tunability at two bands. A comprehensive and rigorous analysis of general LCR two-ports shows the limit of the $s_{21}$ frequency selectivity when built with finite- $Q$ elements. The analysis guides the filter design, which guarantees the maximum frequency selectivity. The analysis is then extended to LCR ${N}$ -ports as the complete analysis. The EBD provides >40-dB isolation in an 80-MHz channel bandwidth in the TX band (5-6 GHz), for any $Z_{text {ANT}}(f_{text {TX}})$ within VSWR = 2, and independently in the RX band (6-7 GHz) when $Q_{text {ANT}}< 4.3$ . The EBD is designed for ≤4-dB RX IL and ≤3.8-dB TX IL, and it supports +29-dBm TX output. The EBD is implemented in Towerjazz 65-nm RF silicon-on-insulator (SOI) CMOS technology and occupies an area of 2.3 mm PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Saeid Daneshgar;Hao Li;Taehwan Kim;Ganesh Balamurugan;
Pages: 1397 - 1408 Abstract: We review the design trade-offs that exist in CMOS inverter-based shunt-feedback transimpedance amplifier (SF-TIA) when optimizing for energy efficiency. We analyze the performance of series and shunt inductive peaking techniques for bandwidth enhancement and identify the most effective one for low-power CMOS TIAs. As a design example, we present a 128-Gb/s single-ended linear transimpedance amplifier (TIA) intended for use in receivers for 400-G Ethernet optical modules and co-packaged optics. The inverter-based SF-TIA is implemented in a 22-nm fin field-effect transistor (FinFET) CMOS technology, supporting a data rate of 128-Gb/s PAM4 with a dc transimpedance gain of $59.3~{mathrm{ dB}}{cdot }Omega $ while dissipating only 11.2 mW of power from a 0.8-V supply. It achieves a 3-dB transimpedance bandwidth of 45.5 GHz with a total integrated input referred noise current of $2.7~mu text{A}_{text{rms}}$ . These results improve upon the state-of-the-art BiCMOS/CMOS linear TIAs, demonstrating the potential for building highly integrated, low-cost, high-sensitivity 100+G CMOS optical receivers using FinFET CMOS process technology. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Guillaume Tochou;Robin Benarrouch;David Gaidioz;Andreia Cathelin;Antoine Frappé;Andreas Kaiser;Jan Rabaey;
Pages: 1409 - 1420 Abstract: Human body communications require energy-efficient transceivers to connect diverse devices on the human body for wellness and medical applications. This article presents a fully digital pulse-based transmitter (TX) for capacitive body-coupled communications (c-BCCs) in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS. The TX is operating at 450 MHz where surface-wave (SW) propagation is the dominant mechanism of c-BCC, offering a larger bandwidth with a more stable channel. The heavily duty-cycled TX uses a 90-MHz free-running oscillator and edge combiners to generate OOK Gaussian-shaped pulses through a switched-capacitor power amplifier (PA). Wide range forward body biasing (FBB), specific to FD-SOI technology, allows frequency tuning and adaptive efficiency optimization as a function of data rate. The proposed TX consumes 17–76 $mu text{W}$ for flexible data rates from 0.1 to 27 Mb/s (170 down to 2.8 pJ/b) with up to 14% system efficiency under 0.5-V supply voltage. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Christopher Sutardja;Ajay Singhvi;Aidan Fitzpatrick;Andreia Cathelin;Amin Arbabian;
Pages: 1421 - 1431 Abstract: Microwave-induced thermoacoustic (TA) imaging, combining high microwave contrast with high ultrasonic resolution has the potential to revolutionize applications such as continuous healthcare monitoring, point-of-care imaging, and biometric authentication. However, the size, cost, and integration of a high-power microwave transmitter is a key bottleneck in making TA imaging truly portable, affordable, and ubiquitous. Toward that end, this work presents a compact 4.9-GHz pulsed power amplifier (PA) with a 4.87-mm2 active area implemented in a 55-nm BiCMOS technology, operating in a duty-cycled mode and achieving 37.3-dBm peak output power—the highest demonstrated peak power in PAs fabricated on a silicon substrate with deep submicron CMOS integration. We also reconstruct the first known high-fidelity TA images of tissue phantoms using an integrated silicon PA. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Anoop Narayan Bhat;Ronan A. R. van der Zee;Bram Nauta;
Pages: 1432 - 1445 Abstract: In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows $ < -$ 44-dBc third harmonic distortion (HD3) up to 1.5- $text{V}_{textrm {p-p}}$ output swing over 0.01–5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and $pm 5{^circ }$ , respectively. The chip is powered from a 5-V supply and dissipates 925 mW. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Yiyu Shen;Robert Bootsman;Morteza S. Alavi;Leo C. N. de Vreede;
Pages: 1446 - 1456 Abstract: This article presents a wideband $2 times 12$ -bit direct-digital RF modulator (DDRM) operating in a 0.5-to-3-GHz band for 5G transmitters. The proposed digital Cartesian modulator features an advanced IQ-mapping technique to boost RF power by 3 dB and suppress the $I/Q$ image. To verify the proposed concept, a 40-nm CMOS prototype is implemented whose RF peak output power at 2 GHz is more than 14 dBm. It achieves an adjacent-channel leakage ratio (ACLR) of −52 dBc and an error vector magnitude (EVM) of −40 dB for a 20-MHz 256-QAM signal at 2.4 GHz. With a 320-MHz 256-QAM signal, the measured ACLR and EVM performances are better than −43 dBc and −32 dB at 2.4 GHz, respectively, without using any digital pre-distortion. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Shi Bu;Sudhakar Pamarti;
Pages: 1457 - 1469 Abstract: A filtering-by-aliasing (FA) receiver front-end based on a slice-based time-varying architecture was described by Bu and Pamarti (2021). Unlike prior FA architectures, it demonstrated, using a 28-nm CMOS prototype IC, a time-invariant input impedance that enables dual-channel operation with high linearity. Up to 50-dB stopband rejection with a transition bandwidth (BW) of only 3.2 times the RF BW, out-of-band IIP3 of +35 dBm, blocker 1-dB compression point of +12 dBm, and local oscillator (LO) leakage power better than −81 dBm were achieved, using a 0.9-V supply. This article elaborates on the design of this prototype, presents detailed analyses of the slice-based architecture, and shows how it addresses many of the prior FA receivers’ problems. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Amr Khashaba;Junheng Zhu;Nilanjan Pal;Mostafa Gamal Ahmed;Pavan Kumar Hanumolu;
Pages: 1470 - 1479 Abstract: Highly stable on-chip frequency references offer the possibility of replacing crystal oscillators in many cost-and form-factor-constrained applications. However, achieving good frequency stability in a power-efficient manner across process, voltage, and temperature variations possess many design challenges. This article describes these challenges and presents a method for improving the integrated RC oscillator’s frequency accuracy by overcoming them. We show that the impact of resistor temperature coefficient (TC) on the accuracy of output frequency can be mitigated by using a parallel combination of two switched resistors that are digitally controlled by pulse-density modulated sequences. By trimming at only two temperatures, a prototype frequency-locked loop (FLL)-based 32-MHz oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of 530 ppm (8.4 ppm/°C), 80-ppm/V voltage sensitivity, 2.5-ppm Allan deviation, and 1- $mu text{W}$ /MHz power efficiency. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Hongshuai Zhang;Yan Zhu;Chi-Hang Chan;Rui P. Martins;
Pages: 1480 - 1491 Abstract: This article presents an inherent gain error-tolerant noise-shaping (NS) successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC). The architecture is hybrid with a pure passive-feedforward (FF) NS SAR ADC in the first stage of the pipeline, realizing an $N$ -0 (2-0) multistage NS sigma–delta (MASH). The $N$ th order from the first stage shapes not only the quantization error and comparator noise but also the interstage gain and nonlinearity error, which greatly relaxes the gain accuracy constraint in the conventional pipelined architecture. In addition to gain, a code-counter-based (CCB) background offset calibration is introduced to mitigate the interstage offset with low cost. The prototype further adopts partial interleaving in the first stage for high speed while sharing the integration capacitors in the feed-forward (FF) structure for a compact area. The 2-0 MASH runs at 400 MS/s and achieves 25-MHz bandwidth with 8 $times $ OSR, consuming 1.26-mW power from a 1-V supply. Within a gain error range of −16% to +12%, the SNDR of the ADC deviates less than 3 dB from the nominal 75-dB SNDR. Fabricated in a 28-nm CMOS process, it exhibits a 178-dB Schreier figure of merit (FoMS). PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Jaegeun Song;Yunsoo Park;Chaegang Lim;Yohan Choi;Soonsung Ahn;Sooho Park;Chulwoo Kim;
Pages: 1492 - 1503 Abstract: This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Yi-Wei Huang;Tai-Haur Kuo;
Pages: 1504 - 1516 Abstract: Background capacitor-current-sensor (CCS) calibration (CAL) is proposed for dc–dc converters to achieve fast load-transient response for small undershoot $V_{mathrm {US}}$ , overshoot $V_{mathrm {OS}}$ , and short settling time $t_{mathrm {S}}$ in the output voltage $V_{mathrm {O}}$ . The CCS’ impedance $Z_{mathrm {Cs}}$ is calibrated to a scaled replica of the output capacitor’s impedance $Z_{mathrm {Co}}$ , which varies with printed-circuit-board parasitics, process-voltage-temperature variations, and aging. Thus, the CCS shunts a current $I_{mathrm {Cs}}$ equal to a scaled output-capacitor current $I_{mathrm {Co}}$ , which instantly and accurately reflects load-current $I_{mathrm {load}}$ transients. The CAL operates at a fixed switching frequency $f_{mathrm {SW}}$ . At this $f_{mathrm {SW}}$ , although $Z_{mathrm {Cs}}$ is dominated by its inductive part, this work can still calibrate its capacitive and resistive parts based on the time derivatives dVO/dt and dICs/dt, respectively. This fixed- $f_{mathrm {SW}}$ CAL overcomes the bottleneck of the prior state-of-the-art CCS CAL, which must hop $f_{mathrm {SW}}$ to lower values to calibrate $Z_{mathrm {Cs}}$ capacitive and resistive parts, thereby enlarging $V_{mathrm {O}}$ steady-state ripples and transient fluctuations during CAL. Thus, only this fixed- $f_{mathrm {SW}}$ CAL is suitable for background operation. Moreover, this CAL can be interrupted by a load-transient or dynamic-voltage-scaling event and be reactivated in quasi-steady state. The shortest CAL period is 8.8 $mu text{s}$ at $f_{mathrm {SW}} = 30$ MHz without interruption. A buck converter with this CCS CAL is fabricated in 0.18- $mu text{m}$ CMOS process and occupies 2.25 mm2. Under a 2-A/4-ns step-up (step-down) load transient, the measured $V_{mathrm {US}}$ ( $V_{mathrm {OS}}$ ) and $t_{mathrm {S}}$ are 36 mV (29 mV) and 56 ns (45 ns), respectively. Compared with prior state of the arts, this work achieves much smaller $V_{mathrm {O}}$ ripples and fluctuations during CAL, shorter CAL period, and faster load-transient r PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Takashi Toi;Junji Wadatsumi;Hiroyuki Kobayashi;Yutaka Shimizu;Yuji Satoh;Makoto Morimoto;Rui Ito;Mitsuyuki Ashida;Yuta Tsubouchi;Mai Nozawa;Go Urakawa;Jun Deguchi;Ryuichi Fujimoto;
Pages: 1517 - 1526 Abstract: This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers of pins and wires near the NAND controller is limited. Although a daisy-chain-based interface can resolve this tradeoff, it requires the additional overheads of bridge chips and procedures for distinguishing between bridge chips. In order to address these challenges, this article presents three key techniques: 1) ring topology; 2) PAM-4-based four-channel multiplexing; and 3) cascaded clock and data recovery (CDR) circuits with phase-error-dependent bang-bang phase detector (PED-BBPD). The fabricated transceiver for the proposed interface using a 28-nm CMOS process achieves energy efficiency of 3.69 pJ/b at 25.6-Gb/s PRBS31 with a bit error rate (BER) of less than $10^{-15}$ through a short channel with 1.84-dB loss. The proposed interface mitigates the overhead of the bridge chips with higher data rate than previous works, and it can achieve a state-of-the-art figure of merit of 1.80 PKG Gb/s/mW, defined as “No. of NAND packages (PKGs) $times $ data rate/power consumption,” with a controller and four bridge chips. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Yusang Chun;Mohamed Megahed;Ashwin Ramachandran;Tejasvi Anand;
Pages: 1527 - 1541 Abstract: This article presents a pulse-amplitude-modulated (PAM)-8 wireline transceiver with receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization (FFE) technique. The receiver converts the voltage-modulated signals or PAM signals into PWM signals and processes them using inverter-based delay elements having a rail-to-rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 to 39.6 Gb/s and compensates 14-dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65-nm CMOS. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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Authors:
Huiyu Mo;Wenping Zhu;Wenjing Hu;Qiang Li;Ang Li;Shouyi Yin;Shaojun Wei;Leibo Liu;
Pages: 1542 - 1557 Abstract: In this article, a quantized network acceleration processor (QNAP) is proposed to efficiently accelerate CNN processing by eliminating most unessential operations based on algorithm-hardware co-optimizations. First, an effective-weight-based convolution (EWC) is proposed to distinguish a group of effective weights (EWs) to replace the other unique weights. Therefore, the input activations corresponding to the same EW can be accumulated first and then multiplied by the EW to reduce amounts of multiplication operations, which is efficiently supported by the dedicated process elements in QNAP. The experimental results show that energy efficiency is improved by 1.59 $times $ –3.20 $times $ compared with different UCNN implementations. Second, an error-compensation-based prediction (ECP) method adopts trained compensated values to replace partly unimportant partial sums to further reduce potentially redundant addition operations caused by the ReLU function. Compared with SnaPEA and Pred on AlexNet, 1.23 $times $ and 1.75 $times $ higher energy efficiencies (TOPS/W) are achieved by ECP, respectively, with marginal accuracy loss. Third, the residual pipeline mode is proposed to efficiently implement residual blocks with a 1.5 $times $ lower memory footprint, a 1.18 $times $ lower power consumption, and a 13.15% higher hardware utilization on average than existing works. Finally, the QNAP processor is fabricated in the TSMC 28-nm CMOS process with a core area of 1.9 mm2. Benchmarked with AlexNet,-VGGNet, GoogLeNet, and ResNet on ImageNet at 470 MHz and 0.9 V, the processor achieves 117.4 frames per second with 131.6-mW power consumption on average, which outperforms the state-of-the-art processors by 1.77 $times $ –24.20 $times $ in energy efficiency. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Pages: 1558 - 1558 Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Please help us test our new pre-print finding feature by giving the pre-print link a rating. A 5 star rating indicates the linked pre-print has the exact same content as the published article.
Pages: 1560 - 1560 Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. PubDate:
May 2022
Issue No:Vol. 57, No. 5 (2022)
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