Subjects -> ENGINEERING (Total: 2677 journals)
    - CHEMICAL ENGINEERING (235 journals)
    - CIVIL ENGINEERING (237 journals)
    - ELECTRICAL ENGINEERING (176 journals)
    - ENGINEERING (1308 journals)
    - ENGINEERING MECHANICS AND MATERIALS (452 journals)
    - HYDRAULIC ENGINEERING (56 journals)
    - INDUSTRIAL ENGINEERING (98 journals)
    - MECHANICAL ENGINEERING (115 journals)

ENGINEERING (1308 journals)                  1 2 3 4 5 6 7 | Last

Showing 1 - 200 of 1205 Journals sorted by number of followers
Composite Structures     Hybrid Journal   (Followers: 255)
IEEE Spectrum     Full-text available via subscription   (Followers: 227)
Composites Part B : Engineering     Hybrid Journal   (Followers: 227)
ACS Nano     Hybrid Journal   (Followers: 187)
Composites Part A : Applied Science and Manufacturing     Hybrid Journal   (Followers: 185)
Composites Science and Technology     Hybrid Journal   (Followers: 158)
IEEE Geoscience and Remote Sensing Letters     Hybrid Journal   (Followers: 156)
IEEE Instrumentation & Measurement Magazine     Hybrid Journal   (Followers: 149)
IEEE Communications Magazine     Full-text available via subscription   (Followers: 140)
IEEE Engineering Management Review     Full-text available via subscription   (Followers: 117)
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 112)
IEEE Transactions on Control Systems Technology     Hybrid Journal   (Followers: 111)
IEEE Transactions on Instrumentation and Measurement     Hybrid Journal   (Followers: 110)
IEEE Transactions on Signal Processing     Hybrid Journal   (Followers: 92)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 88)
IEEE Industry Applications Magazine     Full-text available via subscription   (Followers: 82)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 79)
IEEE Transactions on Engineering Management     Hybrid Journal   (Followers: 75)
Engineering Failure Analysis     Hybrid Journal   (Followers: 68)
IEEE Microwave Magazine     Full-text available via subscription   (Followers: 63)
IEEE Signal Processing Letters     Hybrid Journal   (Followers: 60)
IEEE Transactions on Reliability     Hybrid Journal   (Followers: 54)
Experimental Techniques     Hybrid Journal   (Followers: 51)
IET Radar, Sonar & Navigation     Open Access   (Followers: 50)
IEEE Transactions on Microwave Theory and Techniques     Hybrid Journal   (Followers: 49)
Control Engineering Practice     Hybrid Journal   (Followers: 46)
IEEE Journal of Selected Topics in Signal Processing     Hybrid Journal   (Followers: 43)
IEEE Potentials     Full-text available via subscription   (Followers: 42)
Biotechnology Progress     Hybrid Journal   (Followers: 39)
IEEE Journal on Selected Areas in Communications     Hybrid Journal   (Followers: 39)
International Journal for Numerical Methods in Engineering     Hybrid Journal   (Followers: 37)
Heat Transfer Engineering     Hybrid Journal   (Followers: 36)
IET Microwaves, Antennas & Propagation     Open Access   (Followers: 35)
Digital Signal Processing     Hybrid Journal   (Followers: 35)
IEEE Microwave and Wireless Components Letters     Hybrid Journal   (Followers: 35)
IEEE Transactions on Knowledge and Data Engineering     Hybrid Journal   (Followers: 32)
AIChE Journal     Hybrid Journal   (Followers: 31)
Computing in Science & Engineering     Full-text available via subscription   (Followers: 31)
Flow, Turbulence and Combustion     Hybrid Journal   (Followers: 30)
Coastal Management     Hybrid Journal   (Followers: 30)
Computers & Geosciences     Hybrid Journal   (Followers: 30)
Canadian Geotechnical Journal     Hybrid Journal   (Followers: 29)
Géotechnique     Hybrid Journal   (Followers: 28)
GPS Solutions     Hybrid Journal   (Followers: 28)
Fluid Dynamics     Hybrid Journal   (Followers: 27)
Advances in Engineering Software     Hybrid Journal   (Followers: 27)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 27)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 27)
IEEE Transactions on Power Delivery     Hybrid Journal   (Followers: 26)
Applied Energy     Partially Free   (Followers: 26)
IEEE Journal of Solid-State Circuits     Full-text available via subscription   (Followers: 24)
Engineering & Technology     Hybrid Journal   (Followers: 23)
Corrosion Science     Hybrid Journal   (Followers: 23)
Implementation Science     Open Access   (Followers: 22)
IET Image Processing     Open Access   (Followers: 22)
IEEE Transactions on Electronics Packaging Manufacturing     Hybrid Journal   (Followers: 21)
IET Signal Processing     Open Access   (Followers: 21)
Intermetallics     Hybrid Journal   (Followers: 21)
Combustion, Explosion, and Shock Waves     Hybrid Journal   (Followers: 21)
International Journal for Numerical Methods in Fluids     Hybrid Journal   (Followers: 20)
IEEE Transactions on Circuits and Systems II: Express Briefs     Hybrid Journal   (Followers: 20)
Engineering Optimization     Hybrid Journal   (Followers: 19)
International Communications in Heat and Mass Transfer     Hybrid Journal   (Followers: 19)
IET Circuits, Devices & Systems     Open Access   (Followers: 18)
Advanced Synthesis & Catalysis     Hybrid Journal   (Followers: 18)
International Journal of Adhesion and Adhesives     Hybrid Journal   (Followers: 18)
IEEE/ACM Transactions on Computational Biology and Bioinformatics     Hybrid Journal   (Followers: 18)
Integration     Hybrid Journal   (Followers: 18)
Experiments in Fluids     Hybrid Journal   (Followers: 17)
Engineering Geology     Hybrid Journal   (Followers: 17)
Computational Geosciences     Hybrid Journal   (Followers: 17)
IEEE Transactions on Intelligent Transportation Systems     Hybrid Journal   (Followers: 17)
IEEE Transactions on Energy Conversion     Hybrid Journal   (Followers: 16)
Bulletin of Engineering Geology and the Environment     Hybrid Journal   (Followers: 16)
Coastal Engineering     Hybrid Journal   (Followers: 15)
European Journal of Mass Spectrometry     Hybrid Journal   (Followers: 15)
Electrophoresis     Hybrid Journal   (Followers: 15)
Energy Conversion and Management     Hybrid Journal   (Followers: 15)
IEEE Transactions on Magnetics     Hybrid Journal   (Followers: 14)
IEEE Journal of Biomedical and Health Informatics     Hybrid Journal   (Followers: 14)
IEEE Transactions on Automation Science and Engineering     Full-text available via subscription   (Followers: 13)
IEEE Transactions on Evolutionary Computation     Hybrid Journal   (Followers: 13)
Human Factors in Ergonomics & Manufacturing     Hybrid Journal   (Followers: 13)
Electromagnetics     Hybrid Journal   (Followers: 13)
Computers and Geotechnics     Hybrid Journal   (Followers: 13)
IEEE Transactions on Semiconductor Manufacturing     Hybrid Journal   (Followers: 12)
IET Renewable Power Generation     Open Access   (Followers: 12)
Heat Transfer - Asian Research     Hybrid Journal   (Followers: 11)
IEEE Journal of Oceanic Engineering     Hybrid Journal   (Followers: 11)
CIRP Annals - Manufacturing Technology     Hybrid Journal   (Followers: 11)
Biomedical Engineering     Hybrid Journal   (Followers: 11)
IEEE Transactions on Professional Communication     Hybrid Journal   (Followers: 11)
IEEE Transactions on Education     Hybrid Journal   (Followers: 11)
IEEE Transactions on Nuclear Science     Hybrid Journal   (Followers: 10)
IEEE Transactions on Plasma Science     Hybrid Journal   (Followers: 10)
Proceedings of the Institution of Civil Engineers - Geotechnical Engineering     Hybrid Journal   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 10)
Computational Optimization and Applications     Hybrid Journal   (Followers: 9)
Computers & Mathematics with Applications     Full-text available via subscription   (Followers: 9)
Fuel Cells Bulletin     Full-text available via subscription   (Followers: 9)
Applied Catalysis B: Environmental     Hybrid Journal   (Followers: 9)
European Journal of Engineering Education     Hybrid Journal   (Followers: 9)
Annals of Science     Hybrid Journal   (Followers: 9)
Fuel Cells     Hybrid Journal   (Followers: 8)
Proceedings of the Institution of Civil Engineers - Bridge Engineering     Hybrid Journal   (Followers: 8)
IEEE Technology and Society Magazine     Full-text available via subscription   (Followers: 8)
IEEE Transactions on Advanced Packaging     Full-text available via subscription   (Followers: 8)
Adaptive Behavior     Hybrid Journal   (Followers: 8)
Biomedical Microdevices     Hybrid Journal   (Followers: 8)
Clay Minerals     Hybrid Journal   (Followers: 8)
Continuum Mechanics and Thermodynamics     Hybrid Journal   (Followers: 8)
Energy Engineering     Full-text available via subscription   (Followers: 8)
Geothermics     Hybrid Journal   (Followers: 7)
International Journal of Applied Ceramic Technology     Hybrid Journal   (Followers: 7)
Biomicrofluidics     Open Access   (Followers: 7)
Acta Geotechnica     Hybrid Journal   (Followers: 7)
IEEE Journal of Selected Topics in Quantum Electronics     Hybrid Journal   (Followers: 7)
Advances in OptoElectronics     Open Access   (Followers: 7)
Fuel and Energy Abstracts     Full-text available via subscription   (Followers: 7)
Environmental and Ecological Statistics     Hybrid Journal   (Followers: 7)
IEEE Vehicular Technology Magazine     Full-text available via subscription   (Followers: 7)
Basin Research     Hybrid Journal   (Followers: 7)
Discrete Optimization     Full-text available via subscription   (Followers: 7)
Designs, Codes and Cryptography     Hybrid Journal   (Followers: 7)
Computers and Electronics in Agriculture     Hybrid Journal   (Followers: 7)
Applied Catalysis A: General     Hybrid Journal   (Followers: 7)
Computer Applications in Engineering Education     Hybrid Journal   (Followers: 6)
Fusion Engineering and Design     Hybrid Journal   (Followers: 6)
Computing and Visualization in Science     Hybrid Journal   (Followers: 6)
Applied Clay Science     Hybrid Journal   (Followers: 6)
Formal Methods in System Design     Hybrid Journal   (Followers: 6)
Catalysis Communications     Hybrid Journal   (Followers: 6)
Composite Interfaces     Hybrid Journal   (Followers: 6)
IET Science, Measurement & Technology     Open Access   (Followers: 5)
International Journal of Adaptive Control and Signal Processing     Hybrid Journal   (Followers: 5)
IEEE Transactions on Applied Superconductivity     Hybrid Journal   (Followers: 5)
IEEE Transactions on Vehicular Technology     Hybrid Journal   (Followers: 5)
International Journal of Architectural Computing     Full-text available via subscription   (Followers: 5)
Engineering With Computers     Hybrid Journal   (Followers: 5)
Proceedings of the Institution of Civil Engineers - Engineering Sustainability     Hybrid Journal   (Followers: 5)
Archives of Computational Methods in Engineering     Hybrid Journal   (Followers: 5)
Finite Fields and Their Applications     Full-text available via subscription   (Followers: 5)
Focus on Powder Coatings     Full-text available via subscription   (Followers: 5)
Active and Passive Electronic Components     Open Access   (Followers: 5)
Catalysis Surveys from Asia     Hybrid Journal   (Followers: 4)
Grass and Forage Science     Hybrid Journal   (Followers: 4)
Applied Numerical Mathematics     Hybrid Journal   (Followers: 4)
Annals of Pure and Applied Logic     Open Access   (Followers: 4)
Filtration & Separation     Full-text available via subscription   (Followers: 4)
Graphs and Combinatorics     Hybrid Journal   (Followers: 4)
Fluid Phase Equilibria     Hybrid Journal   (Followers: 4)
Current Applied Physics     Full-text available via subscription   (Followers: 4)
Catalysis Today     Hybrid Journal   (Followers: 4)
Concurrent Engineering     Hybrid Journal   (Followers: 4)
Proceedings of the Institution of Civil Engineers - Ground Improvement     Hybrid Journal   (Followers: 4)
Adsorption     Hybrid Journal   (Followers: 4)
Frontiers in Energy     Hybrid Journal   (Followers: 4)
Catalysis Letters     Hybrid Journal   (Followers: 3)
IET Optoelectronics     Open Access   (Followers: 3)
Informatik-Spektrum     Hybrid Journal   (Followers: 3)
Cellular and Molecular Neurobiology     Hybrid Journal   (Followers: 3)
European Journal of Combinatorics     Full-text available via subscription   (Followers: 3)
Engineering Computations     Hybrid Journal   (Followers: 3)
Applicable Algebra in Engineering, Communication and Computing     Hybrid Journal   (Followers: 3)
Chaos : An Interdisciplinary Journal of Nonlinear Science     Hybrid Journal   (Followers: 3)
Focus on Pigments     Full-text available via subscription   (Followers: 3)
Annals of Combinatorics     Hybrid Journal   (Followers: 3)
Frontiers of Environmental Science & Engineering     Hybrid Journal   (Followers: 3)
Fuzzy Sets and Systems     Hybrid Journal   (Followers: 3)
Assembly Automation     Hybrid Journal   (Followers: 2)
International Journal of Abrasive Technology     Hybrid Journal   (Followers: 2)
Aerobiologia     Hybrid Journal   (Followers: 2)
IET Generation, Transmission & Distribution     Open Access   (Followers: 2)
Historical Records of Australian Science     Hybrid Journal   (Followers: 2)
Comptes Rendus : Mécanique     Open Access   (Followers: 2)
Chinese Journal of Catalysis     Full-text available via subscription   (Followers: 2)
IEEE Latin America Transactions     Full-text available via subscription   (Followers: 2)
Communications in Numerical Methods in Engineering     Hybrid Journal   (Followers: 2)
ESAIM: Control Optimisation and Calculus of Variations     Open Access   (Followers: 2)
Focus on Surfactants     Full-text available via subscription   (Followers: 2)
Engineering Analysis with Boundary Elements     Hybrid Journal   (Followers: 2)
Chaos, Solitons & Fractals     Hybrid Journal   (Followers: 1)
Foundations of Science     Hybrid Journal   (Followers: 1)
Forschung     Hybrid Journal   (Followers: 1)
European Journal of Lipid Science and Technology     Hybrid Journal   (Followers: 1)
Antarctic Science     Hybrid Journal   (Followers: 1)
Épités - Épitészettudomány     Full-text available via subscription   (Followers: 1)
Dyes and Pigments     Hybrid Journal   (Followers: 1)
Bautechnik     Hybrid Journal   (Followers: 1)
Biointerphases     Open Access   (Followers: 1)
Designed Monomers and Polymers     Open Access   (Followers: 1)
Color Research & Application     Hybrid Journal   (Followers: 1)
Abstract and Applied Analysis     Open Access   (Followers: 1)
Focus on Catalysts     Full-text available via subscription  
ESAIM: Proceedings     Open Access  
Environmetrics     Hybrid Journal  
COMBINATORICA     Hybrid Journal  
Chinese Science Bulletin     Open Access  
Calphad     Hybrid Journal  
Boundary Value Problems     Open Access  

        1 2 3 4 5 6 7 | Last

Similar Journals
Journal Cover
IEEE Journal of Solid-State Circuits
Journal Prestige (SJR): 1.665
Citation Impact (citeScore): 5
Number of Followers: 24  
 
  Full-text available via subscription Subscription journal
ISSN (Print) 0018-9200
Published by IEEE Homepage  [228 journals]
  • IEEE JOURNAL OF SOLID-STATE CIRCUITS

    • Free pre-print version: Loading...

      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • Information For Authors

    • Free pre-print version: Loading...

      Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • Low-Loss Heterogeneous Integrations With High Output Power Radar
           Applications at W-Band

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      Authors: Xiao Yang;Yin-Shan Huang;Liang Zhou;Zhe Zhao;Dong-Xin Ni;Cheng-Rui Zhang;Jun-Fa Mao;Jiang-An Han;Xu Cheng;Xian-Jin Deng;
      Pages: 1563 - 1577
      Abstract: This study presents a design of a 94-GHz high-performance and highly compact frequency-modulated continuous-wave radar sensor. In this sensor, an $X$ -band CMOS-based all-digital phase-locked loop chip, $W$ -band SiGe-based transceiver monolithic microwave integrated circuit (MMIC), and $W$ -band GaN-based MMIC power amplifier (PA) are heterogeneously integrated (HI). Each part of the 130-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) SiGe-based transceiver MMIC is designed to include a low-noise amplifier, PA, octupler, mixer, and lange coupler. The fabrication process of our in-house silicon-based MEMS photosensitive composite film is developed to provide very high-density integration and very low insertion loss of interconnections between chips. The HI front end of the radar sensor is measured on-wafer with a high output power of 22 dBm. Moreover, a low double-sideband noise figure (NF) of 10.2 dB is obtained. Bonding–substrate integrated waveguide (SIW)–WG transitions between the heterogeneously integrated front end and the antenna are specially designed and verified. A 2.3-dB degradation is observed, where 19.7 dBm is measured at the transmitter WG WR-10-flange. Thus, the sensor offers a 55-dB dynamic range at a 2-m position with an expectation of a long-distance target-detection range. The radar sensor has an 11.7-cm range resolution and is only $60times 40times $ 8 mm3 in size, with a weight of only 78 g.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • Optically Synchronized Phased Arrays in CMOS

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      Authors: Matan Gal-Katziri;Craig Ives;Armina Khakpour;Ali Hajimiri;
      Pages: 1578 - 1593
      Abstract: Optical synchronization of large-span arrays offers significant benefits over electrical methods in terms of the weight, cost, power dissipation, and complexity of the clock distribution network. This work presents the analysis and design of the first phased array transmitter synchronized using a fully monolithic CMOS optical receiver. We demonstrate a bulk CMOS, 8-element, 28-GHz phased array building block with an on-chip photodiode (PD) that receives and processes the optical clock and uses an integrated PLL to generate eight independent phase-programmable RF outputs. The system demonstrates beam steering, data transmission, and remote synchronization of array elements at 28 GHz with fiber lengths up to 25 m, in order to show the scaling benefits of our approach. The provision of small footprint and cost-effective CMOS transceivers with integrated optoelectronic receivers enables exciting opportunities for low-cost and ultralight array systems.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • Even-Harmonic Class-E CMOS Oscillator

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      Authors: Mohammad Barzgari;Ali Ghafari;Amir Nikpaik;Ali Medi;
      Pages: 1594 - 1609
      Abstract: This article proposes the theory and implementation of an even-harmonic class- $E$ CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high- $Q$ resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator’s figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class- $E$ oscillator is implemented in a 0.18- $mu text{m}$ CMOS technology. At 4 GHz, it exhibits a phase noise of −152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm2.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based
           Complex-Domain Efficiency Enhancement

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      Authors: Yicheng Li;Yun Yin;Diyang Zheng;Xianglong Jia;Jie Lin;Fu Gao;Yiting Zhu;Liang Xiong;Na Yan;Ye Lu;Hongtao Xu;
      Pages: 1610 - 1622
      Abstract: This article presents a 15-bit quadrature digital power amplifier (DPA) with in-phase and quadrature (IQ)-cell-sharing and transformer-based Doherty operation, which compensates the 3-dB power loss in traditional quadrature architecture and enhances efficiency. Efficiency enhancement at 3-/6-dB power backoffs (PBOs) is obtained on the IQ complex plane to improve average efficiency. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is implemented for compact die size. Fabricated in a 55-nm CMOS technology, the DPA is powered by 1.2-/2.4-V supply voltages and the core circuit only occupies 1.05 $times $ 1.14-mm2 chip area. It achieves 29.3-dBm peak output power with power added efficiency (PAE) of 43.1%. With 10-MHz 64-quadratic-amplitude modulation (QAM) local thermal equilibrium (LTE) signal, the DPA achieves $P_{mathrm {avg}}$ of 23.62 dBm and the average PAE of 24.4% with −25.6-dB error vector magnitude (EVM) at 0.85 GHz without using any digital predistortion (DPD) technique. Moreover, for 20-MHz 64-QAM wireless local area network (WLAN) signal, $P_{mathrm {avg}}$ of 21.01 dBm and the average PAE of 20.1% are obtained with −25.1-dB EVM.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 220-GHz Energy-Efficient High-Data-Rate Wireless ASK Transmitter Array

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      Authors: Bahareh Hadidian;Farzad Khoeini;S. M. Hossein Naghavi;Andreia Cathelin;Ehsan Afshari;
      Pages: 1623 - 1634
      Abstract: In this work, we present a wireless energy-efficient fully integrated amplitude shift keying (ASK) transmitter (TX) array at 220 GHz. Each TX cell consists of an oscillator, a modulation switch, an on-chip antenna, and baseband amplifiers. The oscillator uses a harmonic generation technique that is optimized for maximum output power and efficiency. The ASK scheme is used for data modulation and is implemented with a fast switch that does not consume any dc power. Three of these TX cells are coherently coupled together to increase the signal-to-noise ratio (SNR) and, hence, the data rate. This also enables the possibility of having a four-level spatial ASK modulation. Fabricated in a 55-nm SiGe bipolar complementary metal oxide semiconductor (BiCMOS) process, the array dissipates 165.2 mW of dc power and generates 4.2-dBm effective isotropic radiated power (EIRP). The chip demonstrates a 20-Gb/s data transmission rate with on-off keying (OOK) modulation at a 28-cm distance using low-cost Teflon lenses. The measured energy efficiency of the array is 8.26 pJ/bit. To the best of our knowledge, this work demonstrates the best energy efficiency among TX arrays at this frequency range.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With
           32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation

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      Authors: Siwei Li;Zhe Zhang;Gabriel M. Rebeiz;
      Pages: 1635 - 1648
      Abstract: This article presents a 140-GHz eight-element wafer-scale phased-array transmitter based on intermediate-frequency (IF) beamforming with 5-bit phase and 4-bit gain control in the GlobalFoundries 45RFSOI process. The chip contains a shared local-oscillator (LO) multiplier chain and distribution network for a phased-array transmitter system solution. Image rejection filters are designed before the RF front-end power amplifiers (PAs) to suppress the image and improve the PA linearity. A differential on-chip antenna feed is electromagnetically coupled to a high-efficiency microstrip antenna on a 100- $mu text{m}$ -thick quartz superstrate, and the antennas are placed $lambda $ /2 (~140 GHz) apart in the horizontal and vertical directions. The $4times 2$ element phased-array chip with attached quartz superstrate is wirebonded to a printed circuit board containing IF and LO ports and scans to ±30° in the elevation plane ( $E$ -plane). The measured array peak electronic gain is 21 dB with an RF 3-dB bandwidth of 136–147 GHz and an IF bandwidth of 3–4 GHz. The measured array peak effective isotropic radiated power (EIRP) is 30–32 dBm at 134–142 GHz. To evaluate the over-the-air (OTA) performance, a transmit (Tx) array-horn communication link is demonstrated with quadrature phase shift keying (QPSK), 16-quadrature amplitude modulation (QAM), and 64-QAM waveforms, supporting up to 16–18-Gb/s data rates. Also, a transmit–receive phased-array wireless link at 0.65 m is demonstrated with 11–12-Gb/s data ra-es using 16- and 64-QAM waveforms. To the best of our knowledge, this article presents the first CMOS wafer-scale phased-array transmitter at 140 GHz with high EIRP and data rate.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for
           Fluorescence Microendoscopy

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      Authors: Ahmet T. Erdogan;Tarek Al Abbas;Neil Finlayson;Charlotte Hopkinson;Istvan Gyongy;Oscar Almer;Neale A. W. Dutton;Robert K. Henderson;
      Pages: 1649 - 1660
      Abstract: A miniaturized 1.4 mm $times ,, 1.4$ mm, $128times120$ single-photon avalanche diode (SPAD) image sensor with a five-wire interface is designed for time-resolved fluorescence microendoscopy. This is the first endoscopic chip-on-tip sensor capable of fluorescence lifetime imaging microscopy (FLIM). The sensor provides a novel, compact means to extend the photon counting dynamic range (DR) by partitioning the required bit depth between in-pixel counters and off-pixel noiseless frame summation. The sensor is implemented in STMicroelectronics 40-/90-nm 3-D-stacked backside-illuminated (BSI) CMOS process with 8- $mu text{m}$ pixels and 45% fill factor. The sensor capabilities are demonstrated through FLIM examples, including ex vivo human lung tissue, obtained at video rate.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal
           Coded Exposure for Compressive Focal-Stack Depth Sensing

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      Authors: Yi Luo;Shahriar Mirabbasi;
      Pages: 1661 - 1672
      Abstract: In this article, we present a CMOS image sensor (CIS) for coded-exposure-based compressive focal-stack imaging. The proposed CIS has a pixel design, which includes two capacitive trans-impedance amplifiers (CTIAs) and a static random access memory (SRAM), and is capable of per-frame exposure encoding with adjustable spatiotemporal resolutions. A proof-of-concept CIS prototype with a 192 $times $ 192 pixel array is designed and fabricated in a 0.13- $mu text{m}$ CMOS process with a pixel size of 12.6 $times $ 12.6 $mu text{m}^{2}$ . Operating at 30 frames per second (fps), the CIS demonstrates spatial–temporal coded exposure at a maximum rate of 768 masks/frame. The column-wise 10-bit single-slope (SS) analog-to-digital converter (ADC) includes a ramp-slope adaptation feature used for power optimization. During a frame of coded exposure, a linear focal sweep is implemented by a voice-coil motor (VCM) lens mounted in front of the proposed CIS. Through the sparse reconstruction of the coded image, a focal stack consisting of a volume of defocused images is used to synthesize the scene depth map. By introducing coded exposure, the proposed on-chip compressive focal-stack imaging approach facilitates a frame-saving method for passive depth sensing in machine vision and other imaging applications.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic
           Amplifier

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      Authors: Zihao Zheng;Lai Wei;Jorge Lagos;Ewout Martens;Yan Zhu;Chi-Hang Chan;Jan Craninckx;Rui P. Martins;
      Pages: 1673 - 1683
      Abstract: This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm2 in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM).
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

    • Free pre-print version: Loading...

      Authors: Viet Nguyen;Filippo Schembari;Robert Bogdan Staszewski;
      Pages: 1684 - 1699
      Abstract: This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm2 and consumes 15.9 $mu text {W}$ , resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier
           in 65 nm CMOS

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      Authors: R. Gautam;Saurabh Saxena;
      Pages: 1700 - 1711
      Abstract: We present a low-power and low jitter two-stage 2.46–4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an $8times $ clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a $64times $ – $128times $ clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fsrms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving −53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fsrms at 4.92 GHz, −28.2-dBc reference spur, and 3-mW power consumption.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog
           Closed Loop for Supply Noise Compensation

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      Authors: Hyojun Kim;Woosong Jung;Kwandong Kim;Sungwoo Kim;Woo-Seok Choi;Deog-Kyoon Jeong;
      Pages: 1712 - 1722
      Abstract: This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20- $text{m}textrm {V}_{textrm {rms}}$ white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 $textrm {mm} {^{mathrm{ 2}}}$ , respectively.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With
           Adaptively Optimized Noise Shaping

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      Authors: Simone M. Dartizio;Francesco Tesolin;Mario Mercandelli;Alessio Santiccioli;Abanob Shehata;Saleh Karman;Luca Bertulessi;Francesco Buccoleri;Luca Avallone;Angelo Parisi;Andrea L. Lacaita;Michael P. Kennedy;Carlo Samori;Salvatore Levantino;
      Pages: 1723 - 1735
      Abstract: This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm2 and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer- $N$ synthesized channels, 79.7 fs for typical fractional- $N$ channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of −51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of −252.8 dB and −251.6 dB for integer- $N$ and fractional- $N$ channels, respectively.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With
           Frequency-Tracking Loop for Wireline Applications

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      Authors: Dongseok Shin;Hyung Seok Kim;Chuan-Chang Liu;Priya Wali;Savyasaachi Keshava Murthy;Yongping Fan;
      Pages: 1736 - 1748
      Abstract: This article presents a 23.9–29.4 GHz digital LC-phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM LC-digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The LC-PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm2.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and

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      Authors: Yue Chen;Jiang Gong;Robert Bogdan Staszewski;Masoud Babaie;
      Pages: 1749 - 1764
      Abstract: In this article, we present a 4.5–5.1-GHz fractional- $N$ digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc–dc converter. Supply pushing of its inductor–capacitor ( $LC$ ) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on- chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter,
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL
           Supporting BLE Frequency Modulation

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      Authors: Yuming He;Johan van den Heuvel;Paul Mateman;Erwin Allebes;Stefano Traferro;Johan Dijkhuis;Keigo Bunsen;Peter Vis;Arjan Breeschoten;Yao-Hong Liu;Tomohiro Matsumoto;Christian Bachmann;
      Pages: 1765 - 1775
      Abstract: This article presents an injection-locked (IL) ring-oscillator-based fractional- ${N}$ digital phase locked loop (DPLL) supporting Bluetooth low energy (BLE) frequency modulation with an frequency-shift keying (FSK) error between 2.4% and 3.3%. As the fractional spur cannot be suppressed by IL-DPLL, this work proposes a random edge injection (REI) to reduce the spur. This technique also speeds up the convergence time of gain calibration of the digital-to-time converter (DTC). Furthermore, the proposed background calibration schemes allow the DPLL to achieve stable performance across all BLE channels, including both integer- ${N}$ and fractional- ${N}$ channels. This work was fabricated in the 40-nm CMOS technology occupying a 0.09-mm2 area. A fractional spur of −44 dBc and a reference spur of are achieved while consuming 2.76 mW when REI is activated. The background calibrations also ensure stable performance across BLE channels.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase,
           Injection-Locked Ring Oscillator and a Quadrature DLL

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      Authors: Zhaowen Wang;Yudong Zhang;Yuka Onizuka;Peter R. Kinget;
      Pages: 1776 - 1787
      Abstract: We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked loop (QDLL). The QDLL tunes the ring oscillator (ROSC) self-oscillation frequency ( ${f}_{{0}}$ ) and provides it with multi-phase injection signals. The proposed architecture breaks the intrinsic tradeoff between jitter and phase accuracy in two-phase injection-locked ROSCs. The MPCG’s eight-phase output clock drives a 7-bit phase interpolator (PI) for phase and frequency deskew. A 1.2-V 65-nm CMOS MPCG prototype chip has a better-than-1° eight-phase accuracy and $58.8~mathrm {fs}_{mathrm {rms}}$ jitter (integrated from 100 kHz to 1 GHz), while consuming 15.6 mW at 7 GHz, yielding a −252.7-dB figure of merit ( $mathrm {FOM}_{mathrm {jitter}}$ ). The peak-to-peak integral nonlinearity (INL) and the peak-to-peak differential nonlinearity (DNL) of the PI are less than 1.9 and 1.2 LSB, respectively, across a frequency range from 5 to 8 GHz.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider
           by Five With Concurrent Dual-Path Multi-Injection Topology

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      Authors: Alessandro Garghetti;Andrea L. Lacaita;David Seebacher;Matteo Bassi;Salvatore Levantino;
      Pages: 1788 - 1799
      Abstract: Based on a detailed analysis of harmonic generation in ring-based injection-locked frequency dividers (ILFDs), this article shows that concurrent injection signals can be generated in these stages by driving both tail and direct injectors with the same input signal. Based on this result, a novel ring-based divide-by-five ILFD is presented, where multi-injection is reinforced by a dual-path scheme, largely broadening the locking range with no penalty in power dissipation. The stage, implemented in a 28-nm CMOS process, operates over the 8-to-101.6-GHz frequency range achieving a >20% locking over the 13.6–69.1-GHz interval, with 5.6-mW maximum power consumption from a 0.9-V supply. The stage also achieves 101.6 GHz, the highest operating frequency among state-of-the-art CMOS ILFDs by five, with 2.6% locking range.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust
           Technique for Mitigating Chopping Ripples

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      Authors: Liang Fang;Ping Gui;
      Pages: 1800 - 1811
      Abstract: Capacitively coupled chopper instrumentation amplifier (CCIA) is a classical topology for designing low-noise, low-power instrumentation amplifiers (IAs). However, CCIA has two significant limitations: chopping ripple and limited input impedance. Especially for ultra-low-noise applications, the chopping ripple of CCIA can easily saturate the amplifier. Hence, ripple reduction (RR) is required in the CCIA design. This article presents a CCIA with a newly proposed chopping RR technique, dynamic offset zeroing (DOZ). By introducing an ultra-low duty cycle zeroing phase in the normal chopping operation, the proposed DOZ technique can suppress the chopping ripple with a measured state-of-the-art reduction ratio of 61 dB while introducing negligible noise, power, and circuit overhead. In addition, a highly linear three-terminal varactor is proposed in a positive feedback loop (PFL) to boost the limited input impedance of the CCIA to be above 1 $text{G}Omega $ . The presented CCIA is implemented in a 180-nm CMOS technology and achieves a 13-nV/ $surd $ Hz input-referred noise density and a noise efficiency factor (NEF) of 1.3 while consuming 4.5- $mu text{W}$ power.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream
           Feature Extractor

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      Authors: Seungjong Lee;Taewook Kang;John Bell;Mohammad Haghighat;Alberto Martinez;Michael P. Flynn;
      Pages: 1812 - 1823
      Abstract: Beamforming is an essential tool for speaker selection and rejection of environmental noise in automatic speech recognition. This work harnesses the efficiency of delay-and-sum (DAS) beamforming by combining it with constant-directivity beamforming (CDB) and frequency-domain feature extraction. CDB facilitates DAS by restricting the bandwidth for different microphone configurations. An array of sigma–delta modulators (SDMs) digitizes eight microphone inputs. The design takes advantage of bitstream processing of the modulator outputs for beamforming and extracting 60 Mel spectrum power features. The prototype device is fabricated in the 40-nm CMOS and occupies 1.1 mm2. Each SDM consumes 91 mW and has a measured signal-to-noise and distortion ratio of 84 dB for an 8-kHz bandwidth. The beamformer and feature extractor consume a dynamic power of 76 and 122 mW, respectively. The entire power consumption of the prototype is 3.95 mW, including leakage power. Processing the Mel spectrum outputs with a DNN, the keyword spotting accuracy in the presence of noise improves from 74% without beamforming to 93% with beamforming.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision
           Time-Based Charge Balancing and Stimulation-Side Artifact Suppression

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      Authors: Haoran Pu;Omid Malekzadeh-Arasteh;Ahmad Reza Danesh;Zoran Nenadic;An H. Do;Payam Heydari;
      Pages: 1824 - 1840
      Abstract: This article presents a multipolar neural stimulation and mixed-signal neural data acquisition (DAQ) chipset for fully implantable bi-directional brain–computer interfaces (BD-BCIs). The stimulation system employs four 40 V compliant current-stimulators, each capable of sourcing/sinking a maximum 12.75 mA stimulation current, connected to 16 output channels through a high-voltage (HV) switch fabric. A novel time-based charge balancing (TBCB) technique is introduced to reduce the residual voltage on the electrode-electrolyte interface during the inter-pulse time interval, achieving 2 mV charge balancing precision. Additionally, an analytical study of the charge balancing accuracy for the proposed technique is provided. The recording system incorporates a dual-mode DAQ architecture that consists of a 32-element front-end array and a mixed-signal back-end including analog-to-digital converters (ADCs) for both training (i.e., full-band) and decoding (i.e., baseband) operations. Leveraging the flexibility of the multipolar operation, stimulation-side contour shaping (SSCS) artifact cancellation is adopted to significantly suppress stimulation artifacts by up to 45 dB. SSCS method prevents the recording front-ends from saturation and greatly relaxes the dynamic range requirement of the recording system, enabling a truly bi-directional operation. The prototype chipset is fabricated in an HV 180-nm CMOS process and demonstrates a significant performance improvement compared to the prior art.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO
           for Microprocessors

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      Authors: Xiangyu Mao;Yan Lu;Rui P. Martins;
      Pages: 1841 - 1853
      Abstract: High-performance microprocessors need high current (ampere-level), high accuracy, and fast-response power supplies. Comparing to analog and digital low-dropout (LDO) regulators, the switching LDO can be a better candidate for such requirements, as it can drive large power transistor(s) fast and accurately. However, conventional switching LDOs need large load capacitance to reduce the output ripple, which restricts their applications. This article presents a 1.5-A fully-integrated switching LDO for microprocessors, with an easily scalable load capability. Here, we introduce three techniques together to relief the output capacitance requirement: 1) four-phase 500-MHz pulsewidth modulation (PWM) with inherent current balancing; 2) current-limited power cells resisting processor voltage and temperature (PVT) variations; and 3) hybrid fast-slow power transistors. Therefore, we reduce significantly the load capacitance to maximum load current ratio $C_{mathrm {L}} / I_{mathrm {MAX}}$ when compared with the prior switching LDOs. Also, the proposed dual-loop architecture not only achieves a fast transient response, but also provides high-accuracy regulation. In addition, we design the tunable active voltage positioning (AVP). Fabricated in 28-nm CMOS, the proposed switching LDO measures a maximum 70-mV undershoot with a 1-A load current step with 10-ns edge time. The measured load regulation is 1 mV/A and the line regulation is 1.5 mV/V. Also, we obtain a good power supply rejection (PSR) of −63 dB at 10 kHz and −20 dB at 1 MHz. The PWM automatically moves to a pulse-skipping mode at light load, reducing the quiescent current to 1.8 mA, while the peak current efficiency is 99.27%.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Cascaded Hybrid Switched-Capacitor DC–DC Converter Capable of Fast
           Self Startup for USB Power Delivery

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      Authors: Ziyu Xia;Jason T. Stauth;
      Pages: 1854 - 1864
      Abstract: Hybrid switched-capacitor (SC) dc–dc converters show promise in applications that require high conversion ratios and small physical size. However, the problem of flying capacitor voltage imbalance, especially during transients, remains a major challenge that limits the adoption of such converters. This article presents a highly integrated hybrid switched-capacitor (SC) converter for universal serial bus (USB) powered applications, featuring fast balancing dynamics. The topology consists of two cascaded stages to increase the conversion ratio. The output voltage regulation and flying capacitor active balance are both achieved by modified ripple injection control (MRIC), with an additional phase skipping technique further improving the transient response during startup. Fabricated in 0.18 $mu text{m}$ complementary metal-oxide-semiconductor (CMOS) technology, the converter prototype has a peak efficiency of 96.9% for 5:1.2 V conversion. Safe startup can be achieved with the input voltage rising from 0 to 5 V within 8 $mu text{s}$ (0.62 V/ $mu text{s}$ slew rate).
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Self-Resonant Boost Converter for Photovoltaic Energy Harvesting With a
           Tracking Efficiency>90% Over an Ultra-Wide Source Range

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      Authors: Seneke Chamith Chandrarathna;Jong-Wook Lee;
      Pages: 1865 - 1876
      Abstract: Herein, we present a self-resonant boost converter integrated circuit (IC) for ultra-wide range source tracking of a photovoltaic generator (PVG). The tracking is efficiently achieved using a self-controlled resonant frequency generator (SRFG). The SRFG, which is realized using a harmonic oscillator, defines the switching frequency of the converter by operating under three conditions: underdamping, overdamping, and critical damping. The maximum power point tracking (MPPT) controller, which synchronously operates with the SRFG, tracks the light irradiance of the PVG over a 75 $times $ operating range of source resistance (20–1500 $Omega $ ). The MPPT is achieved by controlling the ON-time of the power switch using a programmable delay controller (PDC). The proposed SRFG and the MPPT controller are realized using 31 and 38 nW, respectively. The zero current switching (ZCS) controller is realized using 20 nW. The total power consumption of the converter is 125 nW. The converter IC is fabricated in a 180-nm CMOS process with a 2- $mu text{m}$ -thick top-metal option. Measured results show that the boost converter achieves tracking efficiencies> 90% over an ultra-wide range of source resistance (20–1500 $Omega $ ), corresponding to the illuminance range (3000–5 lux). The measured peak end-to-end efficiency is 86% at 250-mV input and 20- $Omega $ source resistance. Using a commercial PVG module, the converter delivers the maximum output power of 120 $mu text{W}$ with - peak conversion efficiency of 89%. The boost converter performs a self-startup at 80-mV input using an on-chip transformer-based startup circuit (OTSC).
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A High Conversion Ratio and 97.4% High Efficiency Three-Switch Boost
           Converter With Duty-Dependent Charge Topology for 1.2-A High Driving
           Current and 20% Reduction of Inductor DC Current in MiniLED Applications

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      Authors: Si-Yi Li;Yen-An Lin;Zheng-Lun Huang;Jia-Jyun Lee;Ke-Horng Chen;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai;
      Pages: 1877 - 1887
      Abstract: This article presents a three-switch (3S) boost converter with hysteresis current control applied in MiniLED panels. It uses only three power switches to achieve high conversion ratio (=7.5) and low inductor current (20% lower than conventional boost converters). Meanwhile, the charging time of the flying capacitor will increase as the duty cycle increases. It enables the proposed 3S boost converter to have a high drive current (=1.2 A). In addition, the right half-plane (RHP) zero of the proposed topology is related to the switching frequency. By dynamically adjusting the position of RHP zero during transients, the recovery time and output voltage drop can be reduced at the same time. When the load increases from 120 mA to 1.2 A, the recovery time can be accelerated to 42 $mu text{s}$ , and the maximum efficiency can reach 97.4%.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier
           for Bidirectional Device-to-Device Wireless Fast Charging

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      Authors: Fangyu Mao;Yan Lu;Rui P. Martins;
      Pages: 1888 - 1898
      Abstract: This article proposes a reconfigurable single-stage regulating asymmetrical full-wave step-down rectifier (SDR) for fast wireless charging. The SDR is reconfigurable into a step-up power amplifier (SUPA) for device-to-device (D2D) wireless charging. The SDR and SUPA can have a direct connection with the battery without an additional voltage regulator module (VRM). With the single-stage structure, the transmitting (TX) and receiving (RX) ac voltages across the resonant coil can be boosted, which greatly reduces the coil currents and losses, improving the D2D charging power. A reconfigurable controller for the TX/RX mode selection, as well as the switching timing control, is designed. The chip is fabricated in 0.35- $mu text{m}$ CMOS that contains 20-V devices. For the asymmetrical operation, one GaN device is used for the high current path. Also, zero-voltage switching (ZVS) is realized for all the power transistors with one small (180 nH in the 4015 package) power inductor. The bidirectional D2D WPT system achieves a maximum charging power of 5.1 W with a D2D total efficiency of 46.3% and a charging distance of 1.6 cm. Finally, the peak total efficiency is 51.4% with a charging power of 3.4 W and a charging distance of 1 cm.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface
           Circuit With Cold Startup and Fast-Searching ZCD

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      Authors: Qin Kuai;Ho-Yin Leung;Qiping Wan;Philip K. T. Mok;
      Pages: 1899 - 1912
      Abstract: This article presents an auto-polarity thermoelectric energy-harvesting interface circuit based on a single-inductor boost/buck–boost hybrid converter. The power stage is configured automatically as a boost converter for a positive input voltage or a buck–boost converter for a negative input voltage. A collaborative efficiency-improving scheme of frequency selection and maximum power point tracking (MPPT) is implemented for input power ranging from 1 to 800 $mu text{W}$ . An improved digital zero-current detection (ZCD) technique with fast searching is proposed to turn off power switches accurately. Dual-polarity cold startup is realized with the aid of a pair of cross-coupled Dickson charge pumps. This work is fabricated with a 0.13- $mu text{m}$ CMOS process. From the measured results, the interface starts up from a 140- or −160-mV thermoelectric generator (TEG) voltage. It boosts input voltages ranging from 10 mV to 0.4 V and from −10 mV to −0.4 V to a 1.2-V output voltage. It achieves a peak end-to-end efficiency of 90% with a 0.3-V input voltage or 88% with a −0.4-V input voltage. Moreover, end-to-end efficiencies are higher than 80% for input voltages from 90 mV to 0.4 V and from −110 mV to −0.4 V.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for
           3-D-Stacked IC

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      Authors: Ji-Young Kim;Jongsoo Lee;Kiryong Kim;Sunghwan Joo;Byoung Mo Moon;Kyomin Sohn;Seong-Ook Jung;
      Pages: 1913 - 1923
      Abstract: A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 27 – 1 pseudorandom binary sequence at 5 Gb/s.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for
           Quantized Neural Networks

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      Authors: Sungju Ryu;Hyungjun Kim;Wooseok Yi;Eunhwan Kim;Yulhwa Kim;Taesu Kim;Jae-Joon Kim;
      Pages: 1924 - 1935
      Abstract: We introduce an area/energy-efficient precision-scalable neural network accelerator architecture. Previous precision-scalable hardware accelerators have limitations such as the under-utilization of multipliers for low bit-width operations and the large area overhead to support various bit precisions. To mitigate the problems, we first propose a bitwise summation, which reduces the area overhead for the bit-width scaling. In addition, we present a channel-wise aligning scheme (CAS) to efficiently fetch inputs and weights from on-chip SRAM buffers and a channel-first and pixel-last tiling (CFPL) scheme to maximize the utilization of multipliers on various kernel sizes. A test chip was implemented in 28-nm CMOS technology, and the experimental results show that the throughput and energy efficiency of our chip are up to 7.7 $times $ and 1.64 $times $ higher than those of the state-of-the-art designs, respectively. Moreover, additional 1.5–3.4 $times $ throughput gains can be achieved using the CFPL method compared to the CAS.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
  • A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory
           Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for
           Security-Aware Mobile Device

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      Authors: Yen-Cheng Chiu;Tung-Cheng Chang;Chun-Ying Lee;Je-Min Hung;Kuang-Tang Chang;Cheng-Xin Xue;Ssu-Yen Wu;Hui-Yao Kao;Peng Chen;Hsiao-Yu Huang;Shih-Hsih Teng;Chieh-Pu Lo;Yi-Chun Shih;Yu-Der Chih;Tsung-Yung Jonathan Chang;Yier Jin;Meng-Fan Chang;
      Pages: 1936 - 1949
      Abstract: The development of security-aware mobile devices using wide-input–output (IO) nonvolatile memory (NVM) is hindered by high peak current, large area overhead for high read bandwidth (BWR), and considerable energy consumption for data movement between NVM and logic blocks. Furthermore, data stored in NVM are vulnerable to reverse-engineering attacks. This work presents a high BWR security-aware near-memory-computing spin-transfer torque magnetic random-access memory (STT-MRAM) macro using a multi-bit current-mode sense amplifier (MB-CSA) to reduce peak current and energy consumption for wide-IO access, a near-memory shift-and-rotate functionality (NSRF) in conjunction with the MB-CSA to reduce area overhead and enable the completion of read and logic operations within a single cycle, and a reverse-engineering-proof XOR–based memory data protector to protect data stored in NVM against reverse-engineering attacks. A 1-Mb 1024-b read STT-MRAM macro with data protector fabricated using foundry embedded 22-nm STT-MRAM. This work achieved 42.67 GB/s for BWR and 0.23 pJ/b. Inclusion of the NSRF circuit reduced area overhead by 33.3% while increasing latency by only 170 ps.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
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      Pages: 1950 - 1950
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
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      Pages: 1951 - 1951
      Abstract: Advertisement.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
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      Pages: 1952 - 1952
      Abstract: Advertisement.
      PubDate: June 2022
      Issue No: Vol. 57, No. 6 (2022)
       
 
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