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International Journals Digital Communication and Analog Signals
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ISSN (Online) 2455-0329
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[21 journals]

Steganography on Audio File: A Review
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  Authors: Rahul R, R Apoorva, Rajath Rajath, Sakshith Varambally, K. S. Shivaprakasha
  Pages: 1 - 6
  Abstract: Security of the message is more crucial and significant since the majority of real-time applications employ digital communication. One such method that can be used to conceal the information is steganography. Steganography is the method of hiding secret information such as image, text, audio in a carrier file such as Audio File, Video file or Image. Audio Steganography is preferred over other cover files due to its large redundancy. In this paper, we have made an attempt in studying research based on audio steganographic techniques. Different types of audio steganography have been compared and analysed.
  PubDate: 2023-03-10
  Issue No: Vol. 8, No. 2 (2023)
High frequency design approach and feasibility study of HBT based W-band
(90.0GHz-100.0GHz) amplifier using 130nm SiGe based BiCMOS technology
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  Authors: Shib sankar singh, M.Madhav Kumar, Divya Kumar Garg
  Pages: 1 - 7
  Abstract: This paper present high frequency design approach and feasibility study of HBT (Hetero Junction Bipolar Transistor) based two stage cascode amplifiers at W-band (90.0GHz-100.0GHz). The proposed amplifier has design using 130nm SiGe based BiCMOS technology. This paper used low cost technology for designing of w-band amplifier and this is novelty of this paper. The schematic design and feasibility study has been carried out using Cadence software. The selection of active device, input and output matching and impacts of passive components have been analyzed for designing of amplifier at W-band frequency range. The schematic designed two stage amplifier achieved +18.794±2.0dB of small signal gain, better than - 15dB of input return loss and better than -8.0dB of output return loss in simulation. This amplifier achieved +5.93dBm of linear output power (+1 dB compression output power (P1 dB)) and +8.14dBm of saturated output power in simulation at 95GHz. This amplifier achieved less than +7% of %THD (Total Harmonic distortion). This schematic design amplifier includes the effect of all pads and bond wires of both stages of amplifier. The total current consumption of two stage amplifier has only 30.0mA with supply voltage of 3.3volt.
  PubDate: 2022-05-24
  DOI: 10.37628/jdcas.v7i2.1658
  Issue No: Vol. 8, No. 2 (2022)
Routing Algorithms
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  Authors: H. Fathima
  Pages: 8 - 16
  Abstract: The algorithmic steps involved in the Particle Swarm Optimization Algorithm are as follows: Ant, Bee, GA, PSO, Ant-GA, Ant-PSO, Ant-Bee, GA-PSO, Bee-GA, Bee-PSO are the various optimization techniques used in packet delivery between networks. Routing is the process of transporting data from a source to a destination in a network. The simulation time and throughput determine the output of these algorithms. The experiments are carried out using the NS2 software platform, which is built on the fundamentals of C, C++, and TCL Scripting Language. The algorithm’s results revealed that the GA-PSO performs significantly better than the other algorithms in terms of packet delivery between networks
  PubDate: 2022-05-24
  DOI: 10.37628/jdcas.v7i2.1659
  Issue No: Vol. 8, No. 2 (2022)
Design and Simulation of UART Communication Module using Different
Approach
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  Authors: Teerth Patel, Usha Mehta
  Pages: 17 - 23
  Abstract: Various Microcontrollers, microprocessors, and many other devices used different types of communication methods to send and receive data. For this purpose, they used different types of communication protocols according to their requirement. UART stands for Universal Asynchronous Receiver and Transmitter is a serial communication protocol that is ideal to be used between short distances for transmitting and receiving data where cost needs to be reduced by trading off with speed. This paper is focused on the design of the UART module which includes a Baud Rate Generator, Receiver, and Transmitter. The HDL code for design is written in Verilog HDL. The Synthesis and Simulation of the design were done in Xilinx Vivado 2020.2.
  PubDate: 2022-05-24
  DOI: 10.37628/jdcas.v7i2.1660
  Issue No: Vol. 8, No. 2 (2022)
Efficient Implementation of the AES Using FPGA
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  Authors: Kavita Nehra, Rakesh Kumar
  Pages: 20 - 26
  Abstract: Rijndael encryption, developed by Joan Daemen and Vincent Rijmen and recently designated as the official Advanced Encryption Standard (AES), is well suited for hardware use.A few articles discuss the practical structures of ASIC and FPGA (FPGAs). This study proposes an effective way to integrate Rijndael encryption and encoding into a single FPGA architecture with minimal space constraints. The proposed project is equivalent to the smallest Xilinx FPGA, manages 208 Mbps data transmission, uses 163 pieces and three blocks of RAM, and exceeds similarly well-known designs by 68 percent according to the Phryput / Area rating. This paper also includes coarisons with other FPGA families' DES, tripleDES, and AES implementations (such as the Xilinx Virtex-II).
  PubDate: 2022-02-03
  Issue No: Vol. 8, No. 2 (2022)
Hamming Coded Watermarking for Image Authentication and Evaluation by
Image Transmission using Digital Modulation Schemes
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  Authors: Aditya R, Patel Vraj Bhaveshkumar
  Pages: 24 - 30
  Abstract: Proposed watermarking scheme for image authentication and tampered detection. Here, image encoded with a message is generated, after embedding watermark symbol within a colour cover image. The message information is converted to hexadecimal values from its ASCII representation. To encode this and embed the watermark, (7, 4) Hamming code is used. These bits will be divided into 7-bit blocks which will spread across the width of the image. The proposed scheme decodes the encoded message successfully from watermarked image. The authentication has been tested using transmission of watermarked image over AWGN channel using BPSK, DPSK and ASK modulation schemes with convolutional encoders. Experimental results show that the watermark extraction achieves 100% accuracy over 9 dB SNR value for the said modulation schemes.
  PubDate: 2022-05-24
  Issue No: Vol. 8, No. 2 (2022)
Performance Analysis of BER and SNR of BPSK in AWGN Channel
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  Authors: Promise Elechi, Bakare B.I, Umaoro J.I.
  Pages: 27 - 38
  Abstract: Modulation of digital signals has also been a challenge for decades in the communication industries, despite its higher advantage over the analogue method of modulations. The digital techniques still face the same attenuation issue which is also known as bit error rate distortion. In other words, the BPSK has been one of the easiest and better option when it comes to choosing a modulation method because if it low bit error rates over the others. In this research work Bit Error Rate performance of BPSK modulation over AWGN channel is analyzed. Both AWGN channels are used to simulate BPSK signals. The simulation results show that the simulated bit error rate for BPSK modulation is in good agreement with the theoretical bit error rate. Lastly the BPSK performance was compared to DBPSK and QPSK with a MATLAB/SIMULINK result which shows that the BPSK has a lower better BER performance of 0.05663 over QPSK and DPSK.
  PubDate: 2022-02-23
  Issue No: Vol. 8, No. 2 (2022)
A Hybrid BPS-DCT Based Digital Image Watermarking Technique
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  Authors: Dr. Priyanka, Sandeep garg
  Pages: 31 - 40
  Abstract: In this paper a hybrid algorithm using Bit Plane Slicing (BPS) and Discrete Cosine Transform (DCT) for digital image watermarking is proposed. There are two main requirements for digital image watermarking: imperceptibility and robustness. Imperceptibility is measured by Peak Signal to Noise Ratio and robustness is obtained by correlation between original and extracted watermark image. In this algorithm an image and watermark is first sliced into its bit planes using BPS. After this DCT of LSB and first bit planes of both the images i.e. watermark image and original image is taken. Now these two images are embedded using watermarking algorithm. Simulation results are presented for various attacks such as salt and pepper noise, filtering, enhancement, compression etc. The algorithm was implemented in MATLAB 2010b. The performance is compared with NEA algorithm and Cox’s modified algorithm. It was observed that PSNR of proposed algorithm was higher than NEA and Cox’s modified algorithm and MSE is less than these two algorithms.
  PubDate: 2022-06-04
  Issue No: Vol. 8, No. 2 (2022)
Weighted Fair Queuing in Wireless Networks
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  Authors: Pooja Mishra
  Pages: 39 - 46
  Abstract: Due to the rapid growth of wireless data services, the issues of providing different quality of services and fair channel access have become more and more crucial. In wireless networks, there are many mature fair queuing algorithms that can provide fairness and bounded delay properties. However, they cannot be directly applied to wireless networks because of the bursty and location-dependent error characteristics of wireless channels. So many fair queuing algorithms designed for wireless networks are proposed. In this paper, we introduce the concept of fair queuing and Weighted Fair Queuing (WFQ) in wireline networks. We have discuss the problems and difficulties to apply them to wireless networks, and provide a comprehensive survey of recent research on wireless fair queuing algorithms.
  PubDate: 2022-02-23
  DOI: 10.37628/jdcas.v7i1.1579
  Issue No: Vol. 8, No. 2 (2022)
Design & Simulation of LNA in 90nm CMOS Technology for Radio Receiver
using the Cadence Simulation Tool
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  Authors: Dhananjay Nayak
  Pages: 1 - 9
  Abstract: Due to its successful operation in the 2.4 GHz frequency region, often known as the ISM (Industrial, Scientific, and Medical) band, RFICs play a vital role in communication systems. The major parts being used transceivers for frequency translation & amplification are LNA and Mixers. Different types of mixers and LNAs are employed, and different strategies are used to optimize them. In this paper an approach for design and simulation of cascode LNA is discussed to increase to efficiency & Radio Frequency (RF) performance of LNA. More emphasis is put here on the optimization of design. The LNA parameters show how the amplifier is going to work for the proposed design. A low noise amplifier simulated in 90nm CMOS technology. The proposed cascode LNA consists of two transistors. It exhibits 2.5-dB noise figure and 23-dB gain at 2.4 GHz while consuming only 44 nW, this results are confirmed after post layout simulations. These straightforward and analytical conclusions are particularly important since they may be used not only to build CMOS LNA circuits, and to characterise and diagnose them, whether functional prototypes or built. The Communication System's core building block or key component is a Low Noise Amplifier. Any radio receiver is made up of a Low Noise Amplifier, a mixer, and a Filter (Power Efficient Active Filter), with the LNA playing a critical part in the circuit as an amplifier.
  PubDate: 2022-06-29
  Issue No: Vol. 8, No. 1 (2022)
Amplitude Characteristics of Strong Ground Motion Accelerograms - A Review
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  Authors: M. Beena Mol, L. Prinza, Jerald ., Johny Elton, Ignisha Rajathi
  Pages: 10 - 15
  Abstract: This literature review discusses the characteristics of the strong ground motion accelerograms. The characteristics of accelerograms are essential to understand the basic loading pattern of the earthquake forces on the structure. Data from the KiK-net digital borehole accelerograph arrays in Japan are used to investigate the duration, total power, rms amplitude, and peak ground acceleration (PGA) of three significant earthquakes. We look into relationships among duration, PGA on the surface, hypo central distance, instrumental seismic intensity, and site-specific factors. This article also examines the relationship between length and PGA. This paper reviews the amplitude characteristics namely the peak ground acceleration, peak ground velocity and peak ground displacement, and duration parameters namely the significant duration and the bracketed duration
  PubDate: 2022-07-12
  Issue No: Vol. 8, No. 1 (2022)
Intelligent Parking System
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  Authors: Ignisha Rajathi G, R. Vedhapriyavadhana, SL Jayalakshmi, R. Girija
  Pages: 16 - 22
  Abstract: Nowadays, the need for vehicle parking is increasing day by day and has turned into an important issue. Car owners and drivers in India are still struggling with fuel waste and time waste and finding when and where we need to park our car which needs a good amount of lighting due to the usage of a manual vehicle parking system. Also, when there is no special system in place, chaos occurs in parking spaces as damage will be incurred to vehicles while cars are going in or out of the parking space. So, a new car parking system has been introduced to tackle these problems. Hence, this research looks into smart parking methods to find and book the proper parking space efficiently
  PubDate: 2022-07-12
  Issue No: Vol. 8, No. 1 (2022)
House Price Prediction using Machine Learning Algorithms
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  Authors: A.Sufia Farez, ADDALA VANDANA, G. VARSHA, B. BALA KRISHNA
  Pages: 23 - 29
  Abstract: House Prices depend on various factors such as location, features of the house, construction and so on. To factor all these aspects and predict an accurate price of the house can be very tricky. The following paper proposes a system that considers every aspect of a house that effects its pricing and gives an accurate prediction of the house. The system accomplishes this utilising Gradient Boosting, Random Forest, and Decision Tree algorithms. A real time dataset with complete information regarding every single house in the area is used to help give an accurate prediction and minimize the error in the system. The system can be optimized without making changes in the core of it. The system is flexible and not solely dependent on one algorithm but on different algorithms.
  PubDate: 2022-07-22
  Issue No: Vol. 8, No. 1 (2022)
ANALYSIS OF OPTICAL NETWORK SIMULATOR FOR RING TOPOLOGY
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  Authors: Aditya Mahajan, Tejaswin Patel, Rani S Bhandari, Supriya Rajankar
  Pages: 30 - 35
  Abstract: Optical Networks are limited and often hard to configure. One method to overcoming these limitations is to use optical network simulators for extending networks. We modifying the simulation software and the best design of an optical network using one of the best simulations which are called Optisystem software. In this paper, we created the Wavelength Division Multiplexer (WDM) internal circuit in the Optisystem simulator for knowing how it works individually and after that, we created a ring topology using Add-Drop Wave Division Multiplexer as a node of ring topology. How the transmission and reception are done in ring topology in response times, type of signal coding, and spectral width of the light source are affected by the performance of the optical fiber communication such as cable length, data rate, etc
  PubDate: 2022-07-18
  DOI: 10.37628/jdcas.v8i1.1721
  Issue No: Vol. 8, No. 1 (2022)