JournalTOCs

Journal of Minerals and Materials Characterization and Engineering
Number of Followers: 3

This is an Open Access Journal

Open Access journal
ISSN (Print) 1539-2511
Published by Scientific Research Publishing

[243 journals]

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
- PubDate: Wed, 06 Jan 2021 00:00:00 GMT
Large-scale Cellular Automata on FPGAs: A New Generic Architecture and a
Framework
- Abstract: Nikolaos Kyparissas, Apostolos Dollas
  
  Cellular automata (CA) are discrete mathematical models discovered in the 1940s by John von Neumann and Stanislaw Ulam and have been used extensively in many scientific disciplines ever since. The present work evolved from a Field Programmable Gate Array– (FPGA) based design to simulate urban growth into a generic architecture that is automatically generated by a framework to efficiently compute complex cellular automata with large 29 × 29 neighborhoods in Cartesian or toroidal grids, with 16 or 256 states per cell. The new architecture and the framework are presented in detail, including results in terms of modeling capabilities and performance. Large neighborhoods greatly enhance CA modeling capabilities, such as the implementation of anisotropic rules.
  PubDate: Fri, 11 Dec 2020 00:00:00 GMT
PipeArch: Generic and Context-Switch Capable Data Processing on FPGAs
- Abstract: Kaan Kara, Gustavo Alonso
  
  Data processing systems based on FPGAs offer high performance and energy efficiency for a variety of applications. However, these advantages are achieved through highly specialized designs. The high degree of specialization leads to accelerators with narrow functionality and designs adhering to a rigid execution flow. For multi-tenant systems this limits the scope of applicability of FPGA-based accelerators, because, first, supporting a single operation is unlikely to have any significant impact on the overall performance of the system, and, second, serving multiple users satisfactorily is difficult due to simplistic scheduling policies enforced when using the accelerator. Standard operating system and database management system features that would help address these limitations, such as context-switching, preemptive scheduling, and thread migration are practically non-existent in current FPGA accelerator efforts.
  PubDate: Thu, 05 Nov 2020 00:00:00 GMT
Parallel Unary Computing Based on Function Derivatives
- Abstract: Soheil Mohajer, Zhiheng Wang, Kia Bazargan, Yuyang Li
  
  The binary number representation has dominated digital logic for decades due to its compact storage requirements. An alternative representation is the unary number system: We use N bits, from which the first M are 1 and the rest are 0 to represent the value M/N. One-hot representation is a variation of the unary number system where it has one 1 in the N bits, where the 1’s position represents its value. We present a novel method that first converts binary numbers to unary using thermometer (one-hot) encoders and then uses a “scaling network” followed by voting gates that we call “alternator logic,” followed by a decoder to convert the numbers back to the binary format.
  PubDate: Wed, 28 Oct 2020 00:00:00 GMT
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit
Using Field Programmable Gate Array–System on Chip Technology
- Abstract: Alexander E. Beasley, C. T. Clarke, R. J. Watson
  
  FPGA-SoC technology provides a heterogeneous platform for advanced, high-performance systems. The System on Chip (SoC) architecture combines traditional single and multiple core processor topologies with flexible FPGA fabric. Dynamic reconfiguration allows the hardware accelerators to be changed at run-time. This article presents a novel OpenGL compliant GPU design implemented on an FPGA. The design uses an FPGA-SoC environment allowing the embedded processor to offload graphics operation onto a more suitable architecture. To the authors’ knowledge, this is a first. The graphics processor consists of GLSL compliant shaders, an efficient Barycentric Rasterizer, and a draw mode manager. Performance analysis shows the throughput of the shaders to be hundreds of millions of vertices per second.
  PubDate: Wed, 02 Sep 2020 00:00:00 GMT
CoNFV: A Heterogeneous Platform for Scalable Network Function
Virtualization
- Abstract: Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier
  
  Network function virtualization (NFV) is a powerful networking approach that leverages computing resources to perform a time-varying set of network processing functions. Although microprocessors can be used for this purpose, their performance limitations and lack of specialization present implementation challenges. In this article, we describe a new heterogeneous hardware-software NFV platform called CoNFV that provides scalability and programmability while supporting significant hardware-level parallelism and reconfiguration. Our computing platform takes advantage of both field-programmable gate arrays (FPGAs) and microprocessors to implement numerous virtual network functions (VNF) that can be dynamically customized to specific network flow needs. The most distinctive feature of our system is the use of global network state to coordinate NFV operations.
  PubDate: Tue, 18 Aug 2020 00:00:00 GMT

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