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[243 journals]

IEEE Transactions on Circuits and Systems—I:Regular Papers
publication information
- Pages: C2 - C2
  Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
IEEE Circuits and Systems Society Information
- Pages: C3 - C3
  Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
The Challenges and Emerging Technologies for Low-Power Artificial
Intelligence IoT Systems
- Authors: Le Ye;Zhixuan Wang;Ying Liu;Peiyu Chen;Heyi Li;Hao Zhang;Meng Wu;Wei He;Linxiao Shen;Yihan Zhang;Zhichao Tan;Yangyuan Wang;Ru Huang;
  Pages: 4821 - 4834
  Abstract: The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Editorial Special Issue for 50th Birthday of Memristor Theory and
Application of Neuromorphic Computing Based on Memristor - Part II
- Authors: Tingwen Huang;Yiran Chen;Zhigang Zeng;Leon Chua;
  Pages: 4835 - 4836
  Abstract: In 1971, Dr. Leon Chua, known as the father of nonlinear circuits and cellular neural networks, postulated the existence of memristor, a portmanteau of memory resistor, in his seminal paper: “Memristor—The missing circuit element” published in IEEE Transactions on Circuit Theory, the predecessor of IEEE Transactions on Circuits and Systems—I: Regular Papers. In 2008, Hewlett-Packard researchers made nanomemristor devices for the first time, setting off an upsurge of memristor research. The emergence of nanomemristor devices is expected to realize nonvolatile RAM. Moreover, the integration, power consumption, and read–write speed of the RAM based on memristor are superior to those of traditional RAMs. The hardware network based on memristor synaptic devices is an important development direction of neuromorphic computing. It is a powerful technical candidate to break through the traditional von Neumann computing architecture in the post-Moore era, which will provide a feasible scheme about a technological breakthrough for surpassing Moore’s law.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal
Signal Generation
- Authors: Sung Mo Kang;Donguk Choi;Jason K. Eshraghian;Peng Zhou;Jieun Kim;Bai-Sun Kong;Xiaojian Zhu;Ahmet Samil Demirkol;Alon Ascoli;Ronald Tetzlaff;Wei D. Lu;Leon O. Chua;
  Pages: 4837 - 4850
  Abstract: We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
QuantBayes: Weight Optimization for Memristive Neural Networks via
Quantization-Aware Bayesian Inference
- Authors: Yue Zhou;Xiaofang Hu;Lidan Wang;Guangdong Zhou;Shukai Duan;
  Pages: 4851 - 4861
  Abstract: The memristor-based neuromorphic computing system (NCS) with emerging storage and computing integration architecture has drawn extensive attention. Because of the unique nonvolatility and programmability, the memristor is an ideal nano-device to realize neural synapses in VLSI circuit implementation of neural networks. However, in the hardware implementation, the performance of the memristive neural network is always affected by quantization error, writing error, and conductance drift, which seriously hinders its applications in practice. In this paper, a novel weight optimization scheme combining quantization and Bayesian inference is proposed to alleviate this problem. Specifically, the weight deviation in the memristive neural network is transformed into the weight uncertainty in the Bayesian neural network, which can make the network insensitive to unexpected weight changes. A quantization regularization term is designed and utilized during the training process of the Bayesian neural network, reducing the quantization error and improving the robustness of the network. Furthermore, a partial training method is raised to extend the applicability of the proposed scheme in large-scale neural networks. Finally, the experiments on a Multilayer Perceptron and LeNet demonstrate that the proposed weight optimization scheme can significantly enhance the robustness of memristive neural networks.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Design Flow for Hybrid CMOS/Memristor Systems—Part I: Modeling and
Verification Steps
- Authors: Sachin Maheshwari;Spyros Stathopoulos;Jiaqi Wang;Alexander Serb;Yihan Pan;Andrea Mifsud;Lieuwe B. Leene;Jiawei Shen;Christos Papavassiliou;Timothy G. Constandinou;Themistoklis Prodromakis;
  Pages: 4862 - 4875
  Abstract: Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Design Flow for Hybrid CMOS/Memristor Systems—Part II: Circuit
Schematics and Layout
- Authors: Sachin Maheshwari;Spyros Stathopoulos;Jiaqi Wang;Alexander Serb;Yihan Pan;Andrea Mifsud;Lieuwe B. Leene;Jiawei Shen;Christos Papavassiliou;Timothy G. Constandinou;Themistoklis Prodromakis;
  Pages: 4876 - 4888
  Abstract: The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
A Universal, Analog, In-Memory Computing Primitive for Linear Algebra
Using Memristors
- Authors: Piergiulio Mannocci;Giacomo Pedretti;Elisabetta Giannone;Enrico Melacarne;Zhong Sun;Daniele Ielmini;
  Pages: 4889 - 4899
  Abstract: The increasing demand for data-intensive computing applications, such as artificial intelligence (AI) and more specifically machine learning (ML), raises the need for novel computing hardware architectures capable of massive parallelism in performing core algebraic operations. Among the new paradigms, in-memory computing (IMC) with analogue devices is attracting significant interest for its large-scale integration potential, together with unrivaled speed and energy performance. Here, we present a fully-analogue, universal primitive capable of executing linear algebra operations such as regression, generalized least-square minimization and linear system solution with and without preconditioning. We study the impact of the main circuit parameters on accuracy and bandwidth with analytical closed-form expressions and SPICE simulations. Scaling challenges due to parasitic resistance/capacitance and their impact on key parameters such as bandwidth and accuracy are discussed. Finally, a comparison with existing solvers belonging to the same IMC framework is made to assess advantages and disadvantages of the proposed circuit.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Optimization Schemes for In-Memory Linear Regression Circuit With
Memristor Arrays
- Authors: Shiqing Wang;Zhong Sun;Yuheng Liu;Shengyu Bao;Yimao Cai;Daniele Ielmini;Ru Huang;
  Pages: 4900 - 4909
  Abstract: Recently, an in-memory analog circuit based on crosspoint memristor arrays was reported, which enables solving linear regression problems in one step and can be used to train many other machine learning algorithms. To explore its potential for computing accelerator applications, it is of fundamental importance to improve the computing speed of the circuit, i.e., the circuit response towards correct outputs. In this work, we comprehensively studied the transfer function of this circuit, resulting in a quadratic eigenvalue problem that describes the distribution of poles. The minimal real part of non-zero eigenvalues defines the dominant pole, which in turn dominates the response time. Simulations for multiple linear regression solutions with different datasets evidence that, the computing time does not necessarily increase with problem size. The dominant pole is related to parameters in the circuit, including feedback conductance, and gain bandwidth products of operational amplifiers. By optimizing these parameters synergistically, the dominant pole shifts to higher frequencies and the computing speed is consequently optimized. Our results provide a guideline for design and optimization of in-memory machine learning accelerators with analog memristor arrays. Also, issues including power consumption, impact of noise and variation of sources and memristors are investigated to offer a comprehensive evaluation of the circuit performance.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Analog Solutions of Discrete Markov Chains via Memristor Crossbars
- Authors: Gianluca Zoppo;Anil Korkmaz;Francesco Marrone;Samuel Palermo;Fernando Corinto;R. Stanley Williams;
  Pages: 4910 - 4923
  Abstract: Problems involving discrete Markov Chains are solved mathematically using matrix methods. Recently, several research groups have demonstrated that matrix-vector multiplication can be performed analytically in a single time step with an electronic circuit that incorporates an open-loop memristor crossbar that is effectively a resistive random-access memory. Ielmini and co-workers have taken this a step further by demonstrating that linear algebraic systems can also be solved in a single time step using similar hardware with feedback. These two approaches can both be applied to Markov chains, in the first case using matrix-vector multiplication to compute successive updates to a discrete Markov process and in the second directly calculating the stationary distribution by solving a constrained eigenvector problem. We present circuit models for open-loop and feedback configurations, and perform detailed analyses that include memristor programming errors, thermal noise sources and element nonidealities in realistic circuit simulations to determine both the precision and accuracy of the analog solutions. We provide mathematical tools to formally describe the trade-offs in the circuit model between power consumption and the magnitude of errors. We compare the two approaches by analyzing Markov chains that lead to two different types of matrices, essentially random and ill-conditioned, and observe that ill-conditioned matrices suffer from significantly larger errors. We compare our analog results to those from digital computations and find a significant power efficiency advantage for the crossbar approach for similar precision results.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
A Dynamic Event-Triggered Approach to State Estimation for Switched
Memristive Neural Networks With Nonhomogeneous Sojourn Probabilities
- Authors: Jun Cheng;Lidan Liang;Ju H. Park;Huaicheng Yan;Kezan Li;
  Pages: 4924 - 4934
  Abstract: This paper investigates the state estimation for switched memristive neural networks with nonhomogeneous sojourn probabilities. Essentially different from most current literature, a novel switching law is developed to depict the dynamic behavior of switched memristive neural networks, in which the sojourn probabilities of each subsystem are assumed to be nonhomogeneous, and a higher-level deterministic switching signal is proposed to regulate proper feedback switching information by means of the average dwell time approach. Meanwhile, to alleviate the constraint network bandwidth resource efficiently, a dynamic event-triggered mechanism with a novel threshold parameter is proposed in determining if the current data should be released or not. By resorting to the Lyapunov functional technique and the stochastic analysis strategy, some sufficient conditions are addressed to ensure the stochastic stability of the augmented switched memristive neural networks. In the end, the effectiveness and superiority of the developed results are verified by a numerical example.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
A Double-Memristor Hyperchaotic Oscillator With Complete Amplitude Control
- Authors: Yicheng Jiang;Chunbiao Li;Chuang Zhang;Yibo Zhao;Hongyan Zang;
  Pages: 4935 - 4944
  Abstract: Two generalized flux-controlled memristors are applied for hyperchaos generation, and following a four-dimensional hyperchaotic oscillator is constructed. The applied two memristors share a common internal control variable. The new hyperchaotic oscillator exhibits complex dynamics including coexisting chaos and attractor merging. A single constant can realize offset boosting revising the oscillation distribution in phase space. Meanwhile, an amplitude knob rescales the variable making it convenient to construct an analog circuit. The implementation of an analog circuit verifies the consistency with numerical simulation and theoretical analysis.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Generating Any Number of Diversified Hidden Attractors via Memristor
Coupling
- Authors: Sen Zhang;Chunbiao Li;Jiahao Zheng;Xiaoping Wang;Zhigang Zeng;Guanrong Chen;
  Pages: 4945 - 4956
  Abstract: Memristors are widely used to construct multi-scroll/wing chaotic systems with complex dynamics. However, the generation of a multi-scroll/wing attractor is typically not induced by the memristor but depends on other nonlinear functions in the system, which does not take advantage of the unique features of the memristor for chaos-based applications. To address this issue, the present paper introduces a memristor coupling (MC) method to construct a novel memristive Sprott A system (MSAS) through coupling a flux-controlled memristor with multi-piecewise linear memductance into the chaotic Sprott A system. From theoretical analysis and numerical simulations, the MSAS is shown to be able to generate any number of multi-type hidden attractors, including multi-one-scroll, multi-double-scroll and multi-double-wing hidden attractors. In addition, it has two kinds of multistabilities, that is, heterogeneous multistability and homogeneous multistability. Based on these unique properties, different numbers of coexisting heterogeneous hidden attractors and coexisting homogeneous hidden attractors are derived respectively by switching the memristor initial states. These interesting dynamical properties are comprehensively investigated using nonlinear analysis tools. Furthermore, hardware experiments are implemented to demonstrate the feasibility of the MSAS and the effectiveness of the MC method. Finally, a new pseudo-random number generator (PRNG) is proposed to explore the practical applications of the MSAS. Performance evaluation results verify the high-quality randomness of the designed PRNG.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Finite-/Fixed-Time Synchronization of Memristor Chaotic Systems and Image
Encryption Application
- Authors: Leimin Wang;Shan Jiang;Ming-Feng Ge;Cheng Hu;Junhao Hu;
  Pages: 4957 - 4969
  Abstract: In this paper, a unified framework is proposed to address the synchronization problem of memristor chaotic systems (MCSs) via the sliding-mode control method. By employing the presented unified framework, the finite-time and fixed-time synchronization of MCSs can be realized simultaneously. On the one hand, based on the Lyapunov stability and sliding-mode control theories, the finite-/fixed-time synchronization results are obtained. It is proved that the trajectories of error states come near and get to the designed sliding-mode surface, stay on it accordingly and approach the origin in a finite/fixed time. On the other hand, we develop an image encryption algorithm as well as its implementation process to show the application of the synchronization. Finally, the theoretical results and the corresponding image encryption application are carried out by numerical simulations and statistical performances.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Improved Hopfield Network Optimization Using Manufacturable Three-Terminal
Electronic Synapses
- Authors: Su-In Yi;Suhas Kumar;R. Stanley Williams;
  Pages: 4970 - 4978
  Abstract: We illustrate novel optimization techniques via simulations for Hopfield networks constructed from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic circuit elements. We first present a computationally-light, memristor-based, highly accurate static compact model for the SONOS synapses used in our simulations. We then show how to exploit analog errors in programming resistances and current leakage, and the continuous tunability of the SONOS synapses to enable transient chaotic group dynamics, to accelerate the convergence of a Hopfield network. We project improvements in energy consumption and time to solution relative to existing CPUs and GPUs by at least 4 orders of magnitude, and also exceed the projected performance of two-terminal memristor-based crossbars in addition to a 100-fold increase in error-resilient array size (i.e. problem size).
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
NbO₂-Mott Memristor: A Circuit- Theoretic Investigation
- Authors: Ioannis Messaris;Timothy D. Brown;Ahmet S. Demirkol;Alon Ascoli;M. Moner Al Chawa;R. Stanley Williams;Ronald Tetzlaff;Leon O. Chua;
  Pages: 4979 - 4992
  Abstract: This paper presents a circuit-theoretic analysis of a NbO2-Mott memristor fabricated at Hewlett-Packard Labs. It investigates mechanisms behind the origin of complexity based on local activity, which characterizes the behavior of this outstanding nanodevice. We propose an accurate, particularly simplified version of a recently introduced physical model suitable for large-scale circuit simulations. Following the concept of local activity, we then conduct a small-signal circuit-theoretic derivation of the impedance and associated small-signal equivalent circuit elements to analyze device stability and frequency response. Finally, our analysis reveals locally active operating regions, as well as regions where the device dynamics are positioned on the edge of chaos. The latter regions are crucial for designing bio-inspired computing systems.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Generalized Relationship Between Frequency Response and Settling Time of
CMOS OTAs: Toward Many-Stage Design
- Authors: Mahmood A. Mohammed;Gordon W. Roberts;
  Pages: 4993 - 5006
  Abstract: The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Two- and Three-Way Filtering Power Dividers With Harmonic Suppression
Using Triangle Patch Resonator
- Authors: Yanyuan Zhu;Jianpeng Wang;Jiasheng Hong;Jian-Xin Chen;Wen Wu;
  Pages: 5007 - 5017
  Abstract: This paper presents a new approach to design filtering power dividers (FPD) with regular triangle patch resonator (RTPR). According to the electric-field (E-field) distributions of the resonator modes, the TM10 and TM11 modes have been selected to realize two- and three-way power dividers respectively, showcasing the flexible characteristic of the RTPR. Afterwards, an in-phase multiway excitation scheme for the RTPR is developed to well excite the designated modes and suppress multiple spurious modes, simultaneously. Subsequently, to further reject the harmonics so as to extend the upper stopband greatly, shorting posts are deployed at the locations with null electric field distribution for the specified operation mode. Ultimately, to validate the design concept, a two-way and a three-way second-order FPD employed at TM10 ( $f_{10}= 1.27$ GHz) with fractional bandwidth (FBW) of 7% and at TM11 ( $f_{11}= 2.2$ GHz) with FBW of 4.5% are designed and measured. The measured results of the two fabricated circuits well agree with the simulated ones. Results indicate that both of the two FPDs exhibit properties of good port-to-port isolation, high selectivity with transmission zeros near both sides of the passband, as well as wide stopband extended to 3.35 and 2.9 times of fundamental operation frequencies, respectively.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
A Complex Band-Pass Filter for Low-Power and High-Performance Transceivers
- Authors: Marco Cavallaro;Germano Nicollini;
  Pages: 5018 - 5028
  Abstract: In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB $_Omega $ and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/ ${sqrt {Hz}}$ . Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only $400~mu text{A}$ from a 1.2-V power supply.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
A 2.1 mW 2 MHz-BW 73.8 dB-SNDR Buffer-Embedded Noise-Shaping SAR ADC
- Authors: Taewoong Kim;Youngcheol Chae;
  Pages: 5029 - 5037
  Abstract: This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CS value, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2 in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Dynamic Write V_MIN and Yield Estimation for Nanoscale SRAMs
- Authors: Shourya Gupta;Benton H. Calhoun;
  Pages: 5038 - 5048
  Abstract: The dynamic write-access operation in an SRAM has a long-tailed distribution that sets the threshold for write-access failures. The distribution takes a long time to evaluate since rare failure events lie in its long and heavily skewed tail. Moreover, advanced FinFET technologies are becoming increasingly reliant on assist techniques to resolve these rare failures in the tail for improved dynamic performance and stability. In this work, we present various analytical approaches that work well in both super-threshold and subthreshold regions of operation to quickly determine the write-access failure probability. For FinFET based SRAMs, we present a modified sensitivity analysis-based method to evaluate the write-access operation distribution and discuss the evaluation of contention-limited write-access failures. The impact of various write-assist techniques on the performance and stability of FinFET SRAMs is also discussed. All simulations are performed using commercial 65nm bulk planar and 12nm FinFET technologies.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Efficient Soft-Output Gauss–Seidel Data Detector for Massive MIMO
Systems
- Authors: Chuan Zhang;Zhizhen Wu;Christoph Studer;Zaichen Zhang;Xiaohu You;
  Pages: 5049 - 5060
  Abstract: For massive multiple-input multiple-output (MIMO) systems, linear minimum mean-square error (MMSE) detection has been shown to achieve near-optimal performance but suffers from excessively high complexity due to the large-scale matrix inversion. Being matrix inversion free, detection algorithms based on the Gauss–Seidel (GS) method have been proved more efficient than conventional Neumann series expansion-based ones. In this paper, an efficient GS-based soft-output data detector for massive MIMO and a corresponding VLSI architecture are proposed. To accelerate the convergence of the GS method, a new initial solution is proposed. Several optimizations on the VLSI architecture level are proposed to further reduce the processing latency and area. Our reference implementation results on a Xilinx Virtex-7 XC7VX690T FPGA for a 128 base-station antenna and eight user massive MIMO system show that our GS-based data detector achieves a throughput of 732 Mb/s with close-to-MMSE error-rate performance. Our implementation results demonstrate that the proposed solution has advantages over the existing designs in terms of complexity and efficiency, especially under challenging propagation conditions.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With
512 Fully Connected Spins
- Authors: Ryoma Iimura;Satoshi Kitamura;Takayuki Kawahara;
  Pages: 5061 - 5071
  Abstract: With the development of the Internet of things (IoT), sensors are being mounted on various objects. This trend has prompted demand for low-power, high-performance information processing on the edge side. Here, an Ising model architecture that can efficiently solve optimization problems would be an efficient processing solution for edges. In this study, we implemented a 512- spin fully connected Ising model on an LSI chip fabricated in a 28-nm CMOS process. The fully connected Ising model was implemented in the chip by using pseudo-annealing (PA), which is easier to implement than simulated annealing (SA). In addition, we devised a multi-spin-thread structure, concurrent update structure, and a folded interaction placement for accuracy, speed, and compactness. Because eight spin threads are implemented, the calculation throughput could be increased by a factor of eight in comparison with a single spin-thread implementation. Moreover, as a measure of solution accuracy, the average route length of a 22-city traveling salesman problem was reduced by 19% and the standard deviation (SD) was reduced by 46%. Likewise, the average cut value of a 512- node max-cut problem was increased by 1.6% and SD was decreased by 60%. The concurrent update almost doubled the calculation speed in comparison with the case of no concurrent update. In addition, the circuit area was reduced by about 38% as a result of the folded interaction placement. The time required to obtain a solution was 128 ms. The chip at annealing processing (main processing) had a power consumption of 12 mW at 1 MHz.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
An Efficient Digital Realization of Retinal Light Adaptation in Cone
Photoreceptors
- Authors: Milad Ghanbarpour;Ali Naderi;Saeed Haghiri;Arash Ahmadi;
  Pages: 5072 - 5080
  Abstract: In recent years, hardware modeling for various parts of the body’s sensitive organs, including the brain and nervous system, heart and eyes, has been considered for the treatment of diseases and rehabilitation, as well as for moving towards the construction of artificial prostheses. The retina is a thin layer that is the innermost layer of the human eye. In this paper, low-cost hardware implementation for retinal cone cells is performed. Existing mathematical models for implementing the behavior of these cells include a series of nonlinear functions that, if implemented directly, would require a large amount of hardware and, in addition, would not have the desired speed. The proposed model uses multi-linear functions to approximate the nonlinear terms and eliminate the multiplication expressions. The simulation results show that the proposed model tracks the behavior of the original model with high precision. There is also a good match between the main model and the proposed model in terms of dynamic behaviors. The results of hardware implementation using the virtex5 XC5VLX20T (2FF323) reconfigurable board (FPGA) show that the proposed model is fully valid and has a lower hardware volume as well as a 4 times higher frequency, and 22% less power consumption than the original model.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware
With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware
Router
- Authors: Junran Pu;Wang Ling Goh;Vishnu P. Nambiar;Ming Ming Wong;Anh Tuan Do;
  Pages: 5081 - 5094
  Abstract: In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm $^{2}~4096$ -neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by $1.9times $ and $9.4times $ when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic
Scheduling for Graph Convolutional Networks
- Authors: Ruiqi Xie;Jun Yin;Jun Han;
  Pages: 5095 - 5107
  Abstract: With the growing applications of Graph Convolutional Networks (GCN), there is also an increasing demand for its efficient hardware acceleration. Compared with CNN tasks, GCN tasks have new challenges such as randomness, sparsity, and nonuniformity, which will lead to poor performance of previous AI accelerators. In this paper, we propose DyGA, a hardware-efficient GCN accelerator, which is featured by strategies of graph partitioning, customized storage policy, traffic-aware dynamic scheduling, and out-of-order execution. Synthesized and evaluated under TSMC 28-nm, the accelerator achieves an average throughput of over 95% of its peak performance with full utilization of hardware on representative graph data sets. Having a high area-efficiency with 0.217 GOPS/K-logic-gates and 8.06 GOPS/KB-PE-buffer, and thus an energy-efficiency of 384GOPS/W, the proposed accelerator outperforms previous state-of-the-art works in the sparse data processing.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Leveraging Negative Capacitance CNTFETs for Image Processing: An
Ultra-Efficient Ternary Image Edge Detection Hardware
- Authors: Fereshteh Behbahani;Mohammad Khaleqi Qaleh Jooq;Mohammad Hossein Moaiyeri;Khalil Tamersit;
  Pages: 5108 - 5119
  Abstract: Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four $1times 3$ kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt’s figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Convergence of the Resistive Coupling-Based Waveform Relaxation Method for
Chains of Identical and Symmetric Circuits
- Authors: Tarik Menkad;Anestis Dounavis;
  Pages: 5120 - 5133
  Abstract: The convergence of the waveform relaxation (WR) method is demonstrated for a class of circuits: Chains of identical and symmetrical passive subcircuits. The WR algorithm uses resistive coupling to implement the iteration. Every part is modeled as a symmetric and reciprocal linear two-port network. The iteration matrices of the WR operator are constructed for the Gauss-Jacobi and Gauss-Seidel relaxations in the Fourier domain. An upperbound estimate of the spectral radius of the WR operator is presented. It demonstrates the convergence of the method independently of the number of cascaded parts in the chain and the coupling resistance.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Output Feedback Sliding Mode Control of Markovian Jump Systems and Its
Application to Switched Boost Converter
- Authors: Chunlian Wang;Rui Li;Xiaojie Su;Peng Shi;
  Pages: 5134 - 5144
  Abstract: This paper presents a sliding mode dynamic output feedback controller design for Markovian jump systems under a communication network. For the inaccessible states and uncertain parts of Markovian jump systems, a novel integral-type sliding mode output feedback controller combined with system states and dynamic controller states is proposed. An event-triggered mechanism is introduced to reduce network bandwidth and resources requirements. The augmented dynamic system and complete control framework are presented together. The reachability of the novel integral-type sliding mode is proved. Then, based on delay-dependent Lyapunov functions, free-weighting matrices, and a singular value decomposition approach, a less conservative sufficient condition is proposed to ensure exponential stability with a weighted $mathcal {L}_{2}$ - $mathcal{ L}_{infty}$ disturbance performance. Finally, a numerical and a DC-DC switched boost converter circuit simulations that verify the feasibility and effectiveness of the proposed controller are presented.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Interval Observer-Based Robust Coordination Control of Multi-Agent Systems
Over Directed Networks
- Authors: Xiaoling Wang;Housheng Su;Guo-Ping Jiang;
  Pages: 5145 - 5155
  Abstract: In this paper, the robust coordination control of multi-agent systems (MASs) with uncertainties is considered, where the uncertainties include the external disturbances and the measurement noises as well as the unknown initial states. Motivated by the interval observer of single-agent systems, a distributed interval observer is designed for MASs communicating through a directed network which contains a directed spanning tree by using only the bounding information on the uncertainties and the output information, to implement the interval-valued state estimation on the absolute state of each agent. It also finds that the robust coordination control is a by-part of the distributed interval observer design of this kind of MASs. Moreover, a time-invariant transformation is used to perfect the distributed interval observer design. Finally, numerical simulations are proposed to verify the theoretical results.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Robust H ∞ Control for ICPT Process With Coil Misalignment and Time
Delay: A Sojourn-Probability-Based Switching Case
- Authors: Tang Li;Engang Tian;
  Pages: 5156 - 5167
  Abstract: In this paper, the robust $H_{infty }$ control problem is studied for the inductively coupled power transfer (ICPT) process with coil misalignment, energy bounded interference and time-varying delay. The problem of coil misalignment between the primary and secondary coils are considered, and the time varying coupling coefficient are described in a sojourn-probability-based switch model. A set of random variables are utilized to describe the sojourn probabilities of the finite modes of the coil misalignment. It should be pointed out that the sojourn probability of the $i$ th subsystem is obtained by the off-line statistical test instead of prescribed by hand, which is of more closer physical significance due to its engineering practice. Corresponding to the proposed switching systems, a set of controllers with time-varying delays are constructed. By resorting to the Lyapunov stability theory, the matrix analysis, and the stochastic analysis tools, the delay-dependent sufficient criteria with less conservatism are derived to guarantee the mean square stability of the ICPT system and the given interference attenuation level $gamma $ . The feedback gains of the desired controller can be readily obtained by using the control toolbox in Matlab software. Three cases of the illustrative examples without exception verify the effectiveness of the suggested modeling method and control scheme.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Analysis and Design of Quasi-Circulating Quadrature Hybrid for Full-Duplex
Wireless
- Authors: Dror Regev;Erez Zolkov;Nimrod Ginzberg;Rani Keren;Shimi Shilo;Doron Ezri;Emanuel Cohen;
  Pages: 5168 - 5181
  Abstract: This article presents a new electronic device – the four-port quasi-circulating quadrature hybrid (QCQH), which combines desirable features of electronic circulators and quadrature hybrids. The QCQH comprises three quarter-wavelength transmission lines and a 90° non-reciprocal phase shifter (NRPS) and is suitable for inband full duplex applications. We derive the four-port S-parameter matrix of the QCQH and the transfer functions under termination scenarios of interest. The resulting closed-form expressions are compared with the prior art electronic circulator. A 90° transmission line and lumped transformer alternatives are considered for designing a QCQH based on a two-port N-path circuit. TX isolation and transmission expressions are derived and verified against simulations, and a new wideband leakage cancellation approach is proposed. A TSMC 65 nm CMOS N-path chip is integrated on-board with a discrete, lumped, LCL transformer implementation. TX-to-antenna insertion loss of 1.4 dB and an RX NF of 4.7 dB at the frequency of 1 GHz were measured with a primary passive TX-RX isolation of 21 dB. Total isolation of more than 50 dB for an 80 MHz OFDM WiFi TX signal employing digitally equalized active leakage cancellation was achieved along with better than −40 dB TX EVM with SIC ON.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Analysis and Mitigation of Coupling-Dependent Data Flipping in Wireless
Power and Data Transfer System
- Authors: Hao Qiu;Yuntao Jiang;Yi Shi;Takayasu Sakurai;Makoto Takamiya;
  Pages: 5182 - 5193
  Abstract: Load shift keying (LSK) has been widely used in a wireless power and data transfer (WPDT) system, owing to its low cost and power consumption. It was discovered that the demodulated data can flip when the coupling coefficient ( $k$ ) between the transmitter (TX) and receiver (RX) coils becomes less than a critical value ( $k_{mathrm {DF}}$ ) in a system with four basic compensation topologies (series–series, series–parallel, parallel–series, and parallel–parallel). This problem is called coupling-dependent data flipping (CDDF). Even more seriously, the transferred data cannot be recovered when $k$ equals $k_{mathrm {DF}}$ . On the basis of a comprehensive circuit analysis of CDDF, a universal method applicable to all four compensation topologies was proposed. By monitoring the current through the TX coil rather than its voltage for data demodulation, CDDF can be avoided. Furthermore, a WPDT system was implemented in which the voltage information of the load resistance ( $R_{mathrm {Load}}$ ) was transferred to the TX side to control the source voltage for load power ( $P_{mathrm {Load}}$ ) regulation. Using the conventional method, CDDF along with its corresponding $k_{mathrm {DF}}$ (0.35) was verified. On the other hand, using the proposed method, the data was successfully transferred even when $k$ is less than or equal -o $k_{mathrm {DF}}$ . By a correct data transfer, $P_{mathrm {Load}}$ has been successfully regulated at around 1.1 W with a high system efficiency of up to 60% under the variation in $k$ from 0.09 to 0.45.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
Accurately Modeling Zero-Bias Diode-Based RF Power Harvesters With Wide
Adaptability to Frequency and Power
- Authors: Lei Guo;Xuwang Li;Peng Chu;Ke Wu;
  Pages: 5194 - 5205
  Abstract: This paper proposes an analytical method for effectively evaluating the performances of zero-bias diode-based RF power harvesters. The method allows the accurate calculation of both the diode power conversion efficiency (PCE) and matching efficiency, while showing the wide adaptability to frequency and input power. To calculate the diode PCE accurately, the junction voltage is built based on modeling the diode junction capacitance and turn-on voltage. Using the accurate diode PCE, the equivalent nonlinear resistance of the diode is calculated, and thus the diode impedance is obtained. This helps to design a matching network with required bandwidths and evaluate the corresponding matching efficiency. The total PCE of the RF power harvester is finally obtained by multiplying the diode PCE and matching efficiency. For verification, dual-band RF power harvesters based on diodes of SMS7630 and HSMS-2850 are developed to cover the two 5G frequency bands for three telecom operators in China (2.515-2.675, 3.4-3.5 & 3.5-3.6 GHz). They are designed to operate in the low power range of −25-−5 dBm for low power harvesting scenarios. Compared with the simulated results, the calculation discrepancy of less than 3.12% can be achieved in evaluating the total PCEs of the RF power harvesters. Prototypes of the designed RF power harvesters were fabricated and measured for validation. It shows that the proposed analytical method can provide design guidelines for developing a multi-band RF power harvester.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
TechRxiv: Share Your Preprint Research with the World!
- Pages: 5206 - 5206
  Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
IEEE Open Access Publishing
- Pages: 5207 - 5207
  Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)
IEEE Transactions on Circuits and Systems—I:Regular Papers
information for authors
- Pages: 5208 - 5208
  Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
  PubDate: Dec. 2021
  Issue No: Vol. 68, No. 12 (2021)

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