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Solid State Electronics Letters
Number of Followers: 0  

  This is an Open Access Journal Open Access journal
ISSN (Online) 2589-2088
Published by Ke Ai Homepage  [34 journals]
  • A constant Q-factor notch filter using voltage difference transconductance
           amplifier

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): K. Roja, K.M. Santhoshini, M. Sarada, Avireni Srinivasulu This paper demonstrates a novel design of Notch filter circuit availing Voltage Difference Transconductance Amplifier (VDTA) active element. The proposed circuit utilizes two VDTA blocks, two capacitors without the use of resistor and operates in voltage-mode. The devised Notch filter circuit uses 150 µA biasing current and operates with ±0.9 V supply voltage. The transconductance value of this element is electronically controllable/tunable with the bias currents. The proposed filter operates at low voltage and is widely used in optical communication systems, biomedical applications and audio applications. The circuit is implemented in the Cadence Virtuoso tool of the gpdk 180 nm CMOS process.
       
  • Current collapse scaling in GaN/AlGaN/SiC high electron mobility
           transistors

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): D.S. Rawal, Amit, Sunil Sharma, Sonalee Kapoor, Robert Laishram, Seema Vinayak This study reports the scaling of current collapse in GaN/AlGaN HEMTs with respect to the un-passivated gate drain distance on the gate edge. The source drain current reduction increased from 4 mA to 28 mA, when un-passivated gap increased from 200 nm to 600 nm respectively mainly due to virtual gate formation at gate edge as a result of applied large reverse bias between the gate/drain electrodes. The length of virtual gate is a function of un-passivated gap that modifies the lateral electric field between gate-drain region and results in variable current reduction due to variation in available traps with gap. The simulated E-field distribution is found to vary strongly with the un-passivated gap up to 200 nm and weakly thereafter. The HEMT knee voltage shifted from 0.5 V to 1.2 V when gap is increased from 200 nm to 600 nm respectively due to electric field distribution modification and hence electron trapping in the un-passivated gap resulting in increased device on-resistance (Ron). The current collapse finally resulted in reduction of device saturated RF power to 1.2 W/mm at 2.2 GHz for HEMT with an un-passivated gap of 600 nm.
       
  • Latch-up issue of drain metal connection split in test circuit with 3D
           TCAD simulation analysis in CMOS application

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): Chun Chiang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su In CMOS integrated circuit (IC), parasitic Silicon-Controlled Rectifier (SCR) path is unavoidable and causes the risk of latch up (LU) issue. In this work, we found that the SCR characteristic would be influenced by the difference of drain metal connection so it would affect the result of LU measurement. Two common test circuits were measured and discussed in the paper. Additionally, 3D TCAD simulations are performed to help the analysis. Finally, holding voltage (Vh) is increased from 1.5 V to 2.0 V and holding current (Ih) is increased from 0.25A to 0.75A with higher leakage current (IL), lower trigger voltage (Vt1) in drain-connection circuit. Therefore, drain-disconnection circuit, which is simulated as minimum spacing SCR path between two nearby circuits in IC design, is worse case that makes us judge the LU risk much rigorously.
       
  • Design methodology of double nulling resistors nested-Miller compensation
           of multistage amplifier

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): Wing-Shan Tam, Chi-Wah Kok This paper presents a methodology to design large capacitive drive amplifier with high gain feed-forward transconductance stage using double nulling resistors nested-Miller compensation. The high gain-bandwidth and large phase margin of the amplifier can be obtained without stringent passive compensation components matching requirement, which enhances the design robustness towards process, voltage and temperature variations. The proposed amplifier circuit topology is simple and can be applied to implement amplifier with rail-to-rail input and output. A design example of three-stage rail-to-rail class-AB amplifier fabricated with 0.35-µ m 1P4M CMOS technology is presented. The performance of the fabricated amplifier is measured which shows the amplifier is suitable for high output drive applications.
       
  • An integrator circuit using voltage difference transconductance amplifier

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): K. Malathi Santhoshini, Sarada Musala, Srinivasulu Avireni This paper illustrates a novel design of voltage-mode Integrator using the active element, namely Voltage Difference Transconductance Amplifier (VDTA). The proposed circuit avails one VDTA element and a single capacitor. This provides more beneficial for the fabrication of ICs in VLSI design. The designed circuit works with ±0.9 V supply voltage, uses a bias current of order 150 µA and also its amplitude is electronically tunable with the bias current. The proposed circuit is designed in a gpdk 180 nm CMOS process using a Cadence Virtuoso tool and also has the power dissipation of order 270 µW. The simulation results are verified experimentally with the commercially available ICs LM13700.
       
  • Influence of electron quantum confinement on the strength of carbon
           nanotube bundles

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): Lucian D. Filip, Valeriu Filip Radial confinement and specific boundary conditions lead to inhomogeneous spatial distributions for conduction electrons in metallic carbon nanotubes.Such uneven spread of negative charge on the surface of a carbon nanotube can induce Coulomb-type interactions between parallel tubes, contributing to the relative friction. Thus, the axial conduction electron density on a single idealized carbon nanotube closed at both ends was obtained in the framework of the two-dimensional quasi-free electron approximation. A Coulomb potential energy between two parallel nanotubes was calculated as a function of the longitudinal offset between them. The study provides a simple method for estimating the friction force related to Coulomb inter-tube interactions appearing during a parallel sliding motion, with implications in the stretching resistance of various carbon nanotube bundles and in designing various nano-electromechanical devices.
       
  • Editorial

    • Abstract: Publication date: January 2019Source: Solid State Electronics Letters, Volume 1, Issue 1Author(s): Chi Wah Kok
       
 
 
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