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Journal Cover International Journal of Research in Computer and Communication Technology
  [6 followers]  Follow
    
  This is an Open Access Journal Open Access journal
   ISSN (Print) 2320-5156 - ISSN (Online) 2278-5841
   Published by Suryansh Publications Homepage  [2 journals]
  • Privacy- Preserving Entire Range Queries in Two-Tiered Sensor Networks:
           SafeQ

    • Authors: Syed Gulam Gouse, R.Kiran Kumar
      Abstract: — Two-layered sensor systems have been generally received since they offer great adaptability, proficient power utilization and capacity sparing. In this paper, we concentrate on a two layered sensor networks. where asset rich stockpiling hubs go about as a middle of the road level between sensor hubs and the sink. The capacity hubs store information from their close-by sensors and process questions from the sink. In this paper, we propose SafeQ, a convention that keeps assailants from picking up data from both sensor gathered information and sink issued questions. SafeQ additionally enables a sink to identify bargained capacity hubs when they get out of hand. To safeguard protection, SafeQ utilizes a novel system to encode the two information and inquiries to such an extent that a capacity hub can effectively process encoded questions over encoded information without knowing their esteems. To save uprightness, we propose two plans — one utilizing merkle hash trees and another utilizing another information structure called neighborhood chains — to produce respectability check data with the goal that a sink can utilize this data to confirm whether the consequence of a question contains precisely the information things that fulfill the inquiry. To enhance execution, we propose a streamlining procedure utilizing Bloom channels to diminish the correspondence cost amongst sensors and capacity hubs.
      PubDate: 2017-11-13
      Issue No: Vol. 6 (2017)
       
  • Thermal Aware BIST Scan Tree Architecture For Low Latency

    • Authors: Rompicharla Indira, Ch. Lakshmana
      Abstract: Expanding chip temperature is a noteworthy unwavering quality worry since different disappointment systems are quickened at high chip temperature, which require warm mindful testing to identify them. Outer gadgets like warm chambers are generally used to warm up the chip to a coveted temperature keeping in mind the end goal to apply the test. Be that as it may, there are numerous confinements for these outer gadgets, which make the warm mindful testing of the FPGA a testing procedure. In this paper, a self-warming methodology for warm mindful testing of FPGAs is displayed, in which the inner assets of FPGA are utilized to manufacture controlled self warming components (SHEs). These controlled SHEs are circulated over the FPGA and coordinated with the implicit individual test (BIST) plan to create the required temperature profile for testing. Along these lines, no outer gadgets for warming up the FPGA are required. The exploratory outcomes demonstrate that an extensive variety of greatest chip temperatures can be accomplished (from 50◦C up to 125◦C onVirtex-5 FPGA) with a high precision (/1◦C).
      PubDate: 2017-11-13
      Issue No: Vol. 6 (2017)
       
 
 
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