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Journal Cover International Journal of Research in Computer and Communication Technology
  [4 followers]  Follow
  This is an Open Access Journal Open Access journal
   ISSN (Print) 2320-5156 - ISSN (Online) 2278-5841
   Published by Suryansh Publications Homepage  [2 journals]
  • Delay reduction for testing using LPFRSE

    • Authors: Md. Nadeem Qamar, Y. Arpitha, G. Chenchamma
      Abstract: Tracing the memory with a BIST approach is phenomenal, but verifying each bit in the memory and tracing the result is a high time consuming, high power utilizing and area constrained process. Here we are approaching for a speed and low power utilizing test using different test pattern generators using ATPG, scan and LP-LFSR. Comparing the area utilization, power utilization, time constrained and finally effective utilization of devices on the chips selected through simulations in Xilinx.
      PubDate: 2016-06-17
      Issue No: Vol. 5 (2016)
  • Loss less Data Compression using DCT to Optimize the compression Ratio

    • Authors: Ch. Shanthi Priya, B.R.K. Singh
      Abstract: This work studies of the problem and demonstrates the viability of the suggested methodology with simulation runs onthe International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits.When the storage nears it limit, they then try to reduce those files size to minimum by using data compression software. Here a new algorithm for data compression, called DISCRETE COSINE transform is proposed. It manipulates the data inside file to without losing any data after decoding to lossless compression and minimizes the size. This basic algorithm is planned to be combining with other data compression algorithms to optimize the compression ratio.
      PubDate: 2016-06-17
      Issue No: Vol. 5 (2016)
  • FPGA Based Signal Security Using FHSS

    • Authors: Pralay Shende, Nilay Neve, Faizan Momin, Rutuja Deshmukh
      Abstract: Security of the data, information is the major topic of concern in the today’s world of technology. Only password protection security is not sufficient from the intentional interference of data. This work is based on the data protection using FHSS (Frequency Hopping Spread Spectrum) which is one of the best techniques in the field of communication where the data is hidden in the background noise by modulating it with high frequency carrier and spreading its bandwidth using pseudorandom sequence [1]. As FPGA’s makes the hardware implementation simple because of its advantages of high speed, flexibility, etc. [2]. The main objective of this work is to build the hardware implementation of FHSS transmitter using FPGA having Xilinx Simulator and verifying the result on Spectrum Analyzer. On the similar hands the receiver can also be design. Along with this, this paper will be giving idea of how the lives can be saved of people living on coastal areas and protection of country using FHSS.
      PubDate: 2016-06-08
      Issue No: Vol. 5 (2016)
  • Performance Efficient Parallel Self Timed Adder Design

    • Authors: Swathi V S, Sheelu Susan Mathews
      Abstract: A performance efficient asynchronous parallel Self Timed Adder(PASTA) is presented in this paper. This adder achieves better performance even without any speedup circuitry/lookahed schem/carry skip unit. Skew problem are solved by Self-timing. The operation is done parallely for the bits that donot require carry chain propagation, this decreases the total delay. Recursive formula is used to perform multibit addition. The halfadders in the design makes it area efficient with minimal interconnection. The absence of clock generation and distribution units also results in less power dissipation. Clockless chips offer power efficiency, robustness and reliability. Digital simulation was done in Xilinx ISE 14.7 and implemented in Sparten 3E FPGA. Analog simulation was done in Tanner tool. An ALU was designed and synthesized using existing adder and proposed adder to show the superiority of the proposed approach.
      PubDate: 2016-06-05
      Issue No: Vol. 5 (2016)
  • High Speed Implementation Of Fused Floating Point Add-Subtract Unit

    • Authors: Linsha L, Anoop E G, Benoy Abraham
      Abstract: Abstract— Most universally useful processors (GPP) and application particular processors (ASP) utilize the coasting guide number-crunching due toward its wide and exact number framework. In any case, the coasting point operations require complex procedures, for example, arrangement, standardization and adjusting. To lessen the overhead, intertwined drifting point arithmetic units are introduced. High speed implementation of various fused-floating point add-subtract units are presented here. A fused floating-point add-subtract unit is proposed which has increased speed and reduced area compared to discrete floating- point adder. The proposed dual path add-subtract unit has increased performance than the fused floating-point add-subtract unit and this is achieved by employing a dual path algorithm. To further improve the speed, proposed architectures are implemented using six different adders and a comparative study is done. The fastest implementation is the dual path fused floating-point add-subtract unit using carry look ahead adder. The proposed designs are implemented for single precision and synthesized using Xilinx ISE 14.7.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Performance Analysis of Pilot Based Channel Estimation in OFDM System
           using Recursive Least Square Estimator

    • Authors: Siyana Shukkoor, Dhanya .G
      Abstract: For a wireless communication system, the channel is unknown a priori to the receiver. Channel parameter estimation is used for improving data transmission performance. To estimate the channel properties and correct the received signal pilot based approaches are widely used. The previous works consider Least Square (LS) and Minimum Mean Square Error (MMSE) channel estimators. Here, pilot based Channel Estimation (CE) employing Recursive Least Square (RLS) estimator is proposed. Two types of pilot based estimation methods are block-type pilot arrangement and comb-type pilot arrangement. Interpolation techniques are used in comb type pilot to infer the channel frequency values of non-pilot subcarriers. Mean Square Error (MSE) Vs Signal to Noise Ratio (SNR) is the parameter used for estimation. MATLAB is used for the simulation of the system model.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Secured Bluetooth Authentication Using Artificial Neural Networks

    • Authors: Menal Dahiya, Sumeet Gill
      Abstract: Authentication in wireless networking is a mechanism to proof identities and avoid masking. The use of wireless devices and technology has made rapid growth in the market. In all such devices, user authentication is done once and is considered authentic forever until it is revoked by the user. We present a model of authentication, where a Bluetooth enabled mobile phone and laptop is taken. In the present paper we simulate the connection between artificial intelligence and cryptography. We take the help of pattern recognition technique of back propagation algorithm of neural network to store the encrypted password as used in any of such devices. In the proposed mechanism the encrypted password are stored as network parameters. Since reverse tracking from weight matrices is a difficult task, such systems become impossible to crack.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Implementation Of Radix-10 Matrix Code Using High Speed Adder For Error

    • Authors: Grace Abraham, Nimmy M Philip, Deepa N R
      Abstract: Memories are most widely used component in electronic systems. As CMOS technology scales down, multiple cell upsets (MCUs) are causing series issues in memory reliability. In order to protect data in memory, error detection and correction codes are used. The problem with existing error correction codes is that they are either single or double error correction codes. To overcome this issue, a radix-10 based matrix code can be used for multiple error detection to protect memory. This system uses an encoder and decoder section. In this paper, this approach further optimizes the delay with the use of fast adders like parallel prefix carry look ahead adder. A Comparison of radix-10 matrix code using different types of adders was made in order to reduce the delay. The design was modeled using verilog, simulated and synthesized using Xilinx ISE 14.7 and Cadence.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Characterization of Accelerometer for Defense Application

    • Authors: Rodney Anthony Manuel, Manisha Madhukar Barse, Ankita Babarao Aware
      Abstract: The speed of the motor is typically measured in RPM (revolutions per minute). This can be obtained in many ways. A strobe light (stroboscope) is one of the tools to measure RPM. Another method can be using optical tachometers to determine spin rate, however they might require a propeller attached to the motor which can slow it down. Apart from these, there are different methods by which spin rate of a rotating object can be calculated. In this paper we have made use of MEMS accelerometer for calculation of spin rate. Micro-electromechanical systems (MEMS) is a technology that combines a computers with small mechanical devices such as sensors, gears, and actuators in semiconductor chips.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Encryption EXIF Metadata for Protection Photographic Image of Copyright

    • Authors: Hendro Wijayanto, Imam Riadi, Yudi Prayudi
      Abstract: Many photographic images that are published to particular interests. This makes it more and more copyright piracy of images. In this study will make a tools and methods that can be used to protect the copyright of the digital image. The most important part of the digital image is a color image composition or texture images and EXIF ​​metadata information contained therein. Image color and texture of the image reflects the beauty of the digital image. While reflecting the EXIF ​​data information from digital image. In the science of cryptography many common cryptographic algorithms to secure data or information from copyright piracy. One of them is the eXtended Tiny Encryption Algorithm (XTEA) which is a cryptographic technique and operates in 64-bit block size and a 128bit key length. EXIF metadata in encrypted with XTEA, then insert it into End of File image, and delete the original EXIF, is expected to secure a digital image of the copyright piracy without changing primary data image. From the results of the encryption-decryption process, EXIF ​​information and pixel digital image can be protected. There is a shrinkage of the size of the file capacity of -25.15% from size of original image, because image have a change in the type of EXIF ​​metadata to JFIF format. This change only in bits header image, so that 74.85% of primary data bits are not changed.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Implementation of Parallel MAC Unit in 8*8 Pre-Encoded NR4SD Multipliers

    • Authors: Justin K Joy, Deepa N R, Nimmy M Philip
      Abstract: This paper describes a merged multiply-accumulate (MAC) hardware along with the pre-encoded non redundant radix-4 signed digit encoding (NR4SD) multiplier. New designs of pre-encoded multipliers are explored by off-line encoding the standard coefficients using NR4SD encoder and storing them in system memory.The NR4SD encoder, CSA tree, the NR4SD multiplier, and the accumulator sections ensure the fastest possible implementation. A fast pipelined 8 * 8 multiplier implementation is proposed in the paper with parallel multiply-accumulate unit. Extensive experimental analysis verifies the gains of the proposed pre-encoded NR4SD multipliers with MAC unit in terms of area complexity and power consumption compared to the conventional MB multiplier.
      PubDate: 2016-06-04
      Issue No: Vol. 5 (2016)
  • Free Hand Motion Based Control Of Robots Using For Military Rescue And
           Searching Applications

    • Authors: P S M Sailaja, M. Raghunath
      Abstract: Signal based (Non-contact) operation of electrical mechanical assemblies is ending up being continuously fancied development. Flexible Sensor based touch less game plans end up being all the more understood after the late accomplishment of touch screen advancement. Immediately Gestures are not routinely used to control neighborhood machines in a front line base. This foresee inspect on the present use of military in devices and possible use for various zones. Diverse sorts of private machines, advanced devices are controlling used as a piece of family units, business endeavors and work environments. These devices are generally controlled by human hand with manual switches. The survey of things is given with varying data techniques. An impeccable representation is to control a robot by hand movement. This idea made it possible to switch path by changing the heading with the usage of hand movements. Present headways open to see movements in free air which uses Common techniques consolidate cameras, significance sensors or capacitive structures. This work is focusing on examination of electric field (E-field) for front line closeness distinguishing which are curved through hand improvements in perceiving advancements. While stood out from the other systems this development can be used quietly, work through various materials and don't have a high computational weight as well. It grants affirmation of new customer interface applications by area, taking after and request of the customer's hand or finger development in free space.   frameworks this innovation can be utilized inconspicuously, work through different materials and don't have a high computational weight too. It permits acknowledgment of new client interface applications by location, following and characterization of the client's hand or finger movement in free space.
      PubDate: 2016-06-03
      Issue No: Vol. 5 (2016)
  • EEG and Picture Based Brain Controlled Pic and Place Robot for Paralyzed

    • Authors: BVV Satya Narayana, G.Rama Krishna
      Abstract: This anticipate talked about around a cerebrum
      controlled biometric in light of Brain–computer
      interfaces (BCI). BCIs are frameworks that can sidestep
      traditional channels of correspondence
      ( i.e., muscles and thoughts )
      to give direct correspondence and control
      between the human cerebrum and physical gadgets by
      interpreting distinctive examples of mind movement into
      summons progressively. With these summons a
      biometric innovation can be controlled.
      Here, we are investigating the mind wave signals.
      Human cerebrum comprises of a large number of
      interconnected neurons. The examples of cooperation
      between these neurons are spoken to as musings and
      passionate states. As indicated by the human musings,
      this example will change which thusly deliver distinctive
      electrical waves. A muscle withdrawal will likewise
      create a special electrical sign. All these electrical waves
      will be detected by the cerebrum wave sensor and it will
      change over the information into bundles and transmit
      through Bluetooth medium. Level analyzer unit (LAU)
      will get the mind wave crude information and it will
      concentrate and process the sign utilizing Mat lab stage.
      At that point the control summons will be transmitted to
      the mechanical module to handle. With this whole
      framework, we can move a robot as indicated by the
      human contemplations and it can be turned by flicker
      muscle withdrawal.
      PubDate: 2016-06-03
      Issue No: Vol. 5 (2016)
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Tel: +00 44 (0)131 4513762
Fax: +00 44 (0)131 4513327
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