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  Subjects -> ELECTRONICS (Total: 207 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advanced Materials Technologies     Hybrid Journal   (Followers: 1)
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 8)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 9)
Advances in Electronics     Open Access   (Followers: 100)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 40)
Advancing Microelectronics     Hybrid Journal  
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 28)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 16)
Australian Journal of Electrical and Electronics Engineering     Hybrid Journal  
Batteries     Open Access   (Followers: 9)
Batteries & Supercaps     Hybrid Journal   (Followers: 5)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 31)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 2)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 9)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 308)
ECTI Transactions on Computer and Information Technology (ECTI-CIT)     Open Access  
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 2)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 124)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 109)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 103)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elektronika ir Elektortechnika     Open Access   (Followers: 2)
Elkha : Jurnal Teknik Elektro     Open Access  
Emitor : Jurnal Teknik Elektro     Open Access   (Followers: 2)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage     Hybrid Journal   (Followers: 1)
Energy Storage Materials     Full-text available via subscription   (Followers: 4)
EPE Journal : European Power Electronics and Drives     Hybrid Journal  
EPJ Quantum Technology     Open Access   (Followers: 1)
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
IACR Transactions on Symmetric Cryptology     Open Access   (Followers: 1)
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 101)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 82)
IEEE Embedded Systems Letters     Hybrid Journal   (Followers: 57)
IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology     Hybrid Journal   (Followers: 3)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 52)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Letters on Electromagnetic Compatibility Practice and Applications     Hybrid Journal   (Followers: 4)
IEEE Magnetics Letters     Hybrid Journal   (Followers: 7)
IEEE Nanotechnology Magazine     Hybrid Journal   (Followers: 42)
IEEE Open Journal of Circuits and Systems     Open Access   (Followers: 3)
IEEE Open Journal of Industry Applications     Open Access   (Followers: 3)
IEEE Open Journal of the Industrial Electronics Society     Open Access   (Followers: 3)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 77)
IEEE Pulse     Hybrid Journal   (Followers: 5)
IEEE Reviews in Biomedical Engineering     Hybrid Journal   (Followers: 23)
IEEE Solid-State Circuits Letters     Hybrid Journal   (Followers: 3)
IEEE Solid-State Circuits Magazine     Hybrid Journal   (Followers: 13)
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 367)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 74)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 62)
IEEE Transactions on Autonomous Mental Development     Hybrid Journal   (Followers: 8)
IEEE Transactions on Biomedical Engineering     Hybrid Journal   (Followers: 39)
IEEE Transactions on Broadcasting     Hybrid Journal   (Followers: 13)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 26)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 46)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Geoscience and Remote Sensing     Hybrid Journal   (Followers: 226)
IEEE Transactions on Haptics     Hybrid Journal   (Followers: 5)
IEEE Transactions on Industrial Electronics     Hybrid Journal   (Followers: 75)
IEEE Transactions on Industry Applications     Hybrid Journal   (Followers: 40)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 27)
IEEE Transactions on Learning Technologies     Full-text available via subscription   (Followers: 12)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 80)
IEEE Transactions on Services Computing     Hybrid Journal   (Followers: 4)
IEEE Transactions on Signal and Information Processing over Networks     Hybrid Journal   (Followers: 14)
IEEE Transactions on Software Engineering     Hybrid Journal   (Followers: 79)
IEEE Women in Engineering Magazine     Hybrid Journal   (Followers: 11)
IEEE/OSA Journal of Optical Communications and Networking     Hybrid Journal   (Followers: 16)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 36)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 60)
IET Smart Grid     Open Access   (Followers: 1)
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 14)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 12)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 3)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 10)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 25)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 12)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 38)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 9)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronic Science and Technology     Open Access   (Followers: 1)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 4)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 187)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 10)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal   (Followers: 1)
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 3)
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 11)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 32)
Journal of Power Electronics     Hybrid Journal   (Followers: 2)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 27)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Microelectronics and Solid State Electronics     Open Access   (Followers: 28)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal   (Followers: 1)
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 9)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 2)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 4)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 11)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 6)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 57)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Solid State Electronics Letters     Open Access  
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Transactions on Cryptographic Hardware and Embedded Systems     Open Access   (Followers: 2)

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Journal Cover
IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 19  
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [229 journals]
  • IEEE Transactions on Electron Devices publication information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • IEEE Transactions on Electron Devices information for authors
    • Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Blank page
    • Abstract: This page or pages intentionally left blank.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Replacement Gate High-k/Metal Gate nMOSFETs Using a Self-Aligned
           Halo-Compensated Channel Implant
    • Authors: Zhi-Cheng Lee;Li-Feng Chin;Kai-Lin Lee;Yao-Chin Cheng;Osbert Cheng;
      Pages: 2232 - 2237
      Abstract: A device design technique for boosting output resistance ( ${R}_{text {out}}$ ) characteristics of long-channel halo-doped nMOSFETs for replacement gate (RMG) high- ${k}$ /metal gate (HK/MG) devices is proposed based on numerical simulations. We show that the self-aligned halo-compensated channel implant (HCCI) that is carried out after dummy poly gate removal provides compensation for the conventional halo doping. This can be utilized to mitigate the magnitude of potential drop beyond saturation at the drain end so that the long-channel ${R}_{text {out}}$ can be boosted relative to the conventional halo-doped device. In addition, we achieve an improved ${V}_{t}$ roll-off behavior, an advantage to hot carrier injection (HCI) characteristics at high voltage operation, and the lowered short-channel drain-induced barrier lowering (DIBL) and intrinsic delay via the optimization of the source/drain (S/D) doping profile. HCCI technique can be implemented using a process flow that is compatible with the RMG HK/MG system-on-chip (SoC) technology in the mass production.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Design Principles of Self-Compensated NBTI-Free Negative Capacitor FinFET
    • Authors: K. Karda;Chandra Mouli;M. A. Alam;
      Pages: 2238 - 2242
      Abstract: The Landau field-effect transistors have been previously investigated to lower the power dissipation of integrated circuits by reducing the subthreshold swing (SS) below the Boltzmann limit of 60 mV/dec. The basic idea is to replace the classical gate insulator with dielectrics that exhibit a negative capacitance (NC) associated with the double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. In this article, we demonstrate that the same NC effect can also be used to achieve the devices more robust to negative-bias temperature instability (NBTI), which continues to be a major reliability challenge for scaled p-type transistors. We demonstrate that with careful design of an NC-based Landau switch, the intrinsic NBTI degradation can be fully compensated while still maintaining hysteresis-free operation and steeper slope needed for the logic switch. In fact, the parasitic capacitances in a FinFET counterintuitively make a negative capacitance field effect transistor (NCFET) more NBTI tolerant. The proposed device is validated using the numerical simulations by technologically relevant p-type SiGe FinFeTs. The results suggest the intriguing possibility that a careful, physics-informed NCFET design can simultaneously achieve reliability performance metrics.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Design and Simulation of Steep-Slope Silicon Cold Source FETs With
           Effective Carrier Distribution Model
    • Authors: Weizhuo Gan;Raphaël J. Prentki;Fei Liu;Jianhui Bu;Kun Luo;Qingzhu Zhang;Huilong Zhu;Wenwu Wang;Tianchun Ye;Huaxiang Yin;Zhenhua Wu;Hong Guo;
      Pages: 2243 - 2248
      Abstract: The cold source field-effect transistor (CSFET), enabled by novel source engineering, is a promising alternative to achieve sub-60 mV/dec steep-slope switching. For the first time, we develop an industry-standard TCAD approach for the CSFET with an effective cold carrier density of states (DOS) model which captures the underlying physics of DOS engineering, cold carrier injection, and thermalization in the device. The simulation scheme uses nonequilibrium Green’s function (NEGF) simulation for calibration. The effects of source engineering, rethermalization, and channel tunneling are extensively investigated on a Si-based double-gate CSFET. Its merits are highlighted by comparison with a conventional MOSFET under various temperatures, thicknesses, and gate lengths, showing improved ${I} _{ {mathrm{scriptscriptstyle ON}}}/{I} _{ {mathrm{scriptscriptstyle OFF}}}$ in ultrascaled MOSFET.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • A Vertical Combo Spacer to Optimize Electrothermal Characteristics of 7-nm
           Nanosheet Gate-All-Around Transistor
    • Authors: Renhua Liu;Xiaojin Li;Yabin Sun;Yanling Shi;
      Pages: 2249 - 2254
      Abstract: In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA) transistor with a vertical combo spacer and different underlap/overlap channels is studied by the 3-D TCAD simulation. To achieve high authoritative evidences, the ${I}_{text {d}}$ – ${V}_{text {g}}$ characteristic with SHE is calibrated with the experimental data. First, the change of electrical characteristic introduced by different dielectrics of a single- ${k}$ spacer is investigated, and the results show that the current of ON-state ( ${I}_{ mathrm{scriptscriptstyle ON}}$ ) is a power function of relative permittivity, whereas the OFF-state ( ${I}_{ mathrm{scriptscriptstyle OFF}}$ ) exhibits a linear dependence. Second, a novel vertically wrapped combo spacer is proposed to achieve a compromise between thermal characteristic and electrical performance for the first time. The electrothermal characteristics of the combo spacer under different underlap/overlap channels are also studied, and the results showed that the combo spacer composed of inner Si3N4 and outer HfO2 has the highest ${I}_{ mathrm{scriptscriptstyle ON}}/{I}_{ mathrm{scriptscriptstyle OFF}}$ but smaller thermal resistance and lower lattice temperature compared with other different combinations. At last, a CMOS inverter with Si3N4/HfO2 combo spacer is demonstrated for its improvement in propagation delay.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • A Predictive 3-D Source/Drain Resistance Compact Model and the Impact on 7
           nm and Scaled FinFETs
    • Authors: Tao Wu;Haowen Luo;Xingsheng Wang;Asen Asenov;Xiangshui Miao;
      Pages: 2255 - 2262
      Abstract: Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd compact model is developed and comprehensively validated in respect of 7-nm bulk FinFET TCAD platform. Our TCAD model was calibrated against GlobalFoundries/Samsung 7-nm FinFET technology experimental data and further validated by 2-D Poisson–Schrodinger simulation. Verilog-A coded SPICE Rsd compact model, coupled with proper transport models, indicates that the degradation of saturation current as well as the proportion of Rsd to total device resistance continues to increase from 45% to 49%, and 52% with the scaling of the FinFET from 7 to 5, and 3-nm FinFETs, with errors of less than 4%. TCAD and compact model simulation results both show that the extension and epitaxial contact regions become dominant while metal contact resistivity can be reduced below 6– ${8} times {10}^{-{9}} ,, Omega cdot text {cm}^{{2}}$ .
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Highly Tunable High-Q Inversion-Mode MOS Varactor in the
           1–325-GHz Band
    • Authors: Marc Margalef-Rovira;Abdelhalim A. Saadi;Loic Vincent;Sylvie Lepilliet;Christophe Gaquière;Daniel Gloria;Cedric Durand;Manuel J. Barragan;Emmanuel Pistono;Sylvain Bourdel;Philippe Ferrari;
      Pages: 2263 - 2269
      Abstract: This article presents the design, experimental results, and modeling of an inversion-mode CMOS varactor integrated in the STMicroelectronics 55-nm BiCMOS technology. The device was characterized from 1 to 325 GHz, demonstrating high-quality factor at millimeter-waves. For instance, a quality factor of 7 at around 190 GHz for a tuning ratio ( ${C}_{text {max}}/{C}_{text {min}}$ ) greater than 4 was measured. This performance overpasses that of accumulation-mode varactors usually provided in CMOS technologies design kits, for frequencies beyond about 100 GHz. In addition, a small-signal electrical model is provided from 100 to 250 GHz.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Diamond Field-Effect Transistors With V2O5-Induced Transfer Doping:
           Scaling to 50-nm Gate Length
    • Authors: Kevin G. Crawford;James D. Weil;Pankaj B. Shah;Dmitry A. Ruzmetov;Mahesh R. Neupane;Khamsouk Kingkeo;A. Glen Birdwell;Tony G. Ivanov;
      Pages: 2270 - 2275
      Abstract: Wereport on the fabrication and measurement of hydrogen-terminated diamond field-effect transistors (FETs) incorporating V2O5 as a surface acceptor material to induce transfer doping. Comparing a range of gate lengths down to 50 nm, we observe inversely scaling peak output current and transconductance. Devices exhibited a peak drain current of ~700 mA/mm and a peak transconductance of ~150 mS/mm, some of the highest reported thus far for a diamond metal semiconductor FET (MESFET). Reduced sheet resistance of the diamond surface after V2O5 deposition was verified by four probe measurement. These results show great potential for improvement of diamond FET devices through scaling of critical dimensions and adoption of robust transition metal oxides such as V2O5.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Drain Current Optimization in DIBS-Grown MgZnO/CdZnO HFET
    • Authors: Md Arif Khan;Pawan Kumar;Mangal Das;Myo Than Htay;Ajay Agarwal;Shaibal Mukherjee;
      Pages: 2276 - 2281
      Abstract: This article reports the fabrication of a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnO (MCO)-based gateless heterostructure field-effect transistor (HFET). In addition, this article presents that by introducing a 30-nm yttria spacer layer, the crystallinity of the CdZnO buffer layer can be enhanced and the interface roughness at the heterojunction of the MCO heterostructure can be reduced. Furthermore, the source and drain metal contacts were optimized for the least specific contact resistivity ( $boldsymbol {rho }_{c}$ ) yielding metal combination and annealing conditions. The results suggest that the introduction of the yttria spacer layer improves the overall conductance [product of sheet carrier density ( ${n}_{s}$ ) and electron mobility ( $boldsymbol {mu }$ )] of MCO up to $3.5times 10^{15},,text{V}^{-1}text{s}^{-1}$ compared to $9times 10^{14},,text{V}^{-1}text{s}^{-1}$ in the non-yttria spacer-based MCO. In addition, the drain current ( ${I}_{d}$ )–drain voltage ( ${V}_{d}$ ) characteristic of the as-developed yttria spacer-based MCO HFET shows a high drain current value (~400 mA/mm). These results establish the DIBS-grown MCO heterostructure as a viable option for low-cost HFETs necessary for the fabrication of large-scale HFET-based power and sensor devices.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Charge-Based Compact Drain Current Modeling of InAs-OI-Si MOSFET Including
           Subband Energies and Band Nonparabolicity
    • Authors: Subir Kumar Maity;Anisul Haque;Soumya Pandit;
      Pages: 2282 - 2289
      Abstract: In this article, we report a physics-based compact model of drain current for InAs-on-insulator MOSFETs. The quantum confinement effect has been incorporated in the proposed model by solving the 1-D Schrödinger–Poisson equations without using any empirical model parameter. The model accurately captures the variation of surface potential, charge density in the inversion layer, and subband energy levels with gate bias inside the quantum well. The conduction-band nonparabolicity effect on modification in eigenenergy, effective mass, and density of states is derived and incorporated into the proposed model. The velocity overshoot effect that originates from the quasi-ballistic nature of carrier transport is also considered in the model. The proposed drain current model has been implemented in Verilog-A to use in the SPICE environment. The model predicted results are in good agreement with the commercial device simulator results and experimental data.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Modeling the Influence of the Acceptor-Type Trap on the 2DEG Density for
           GaN MIS-HEMTs
    • Authors: Yijun Shi;Wanjun Chen;Ruize Sun;Chao Liu;Yajie Xin;Yun Xia;Fangzhou Wang;Xiaorui Xu;Xiaochuan Deng;Tangsheng Chen;Bo Zhang;
      Pages: 2290 - 2296
      Abstract: In this article, an analytical model on the influence of the acceptor-type trap on the 2-dimensional electron gas (2DEG) density is proposed for GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Based on the charge-control method, a numerical analysis of the 2DEG in both the subthreshold and above-threshold regions is carried out with the deep-level and band-tail acceptor-type traps at the AlGaN/insulator interface and the AlGaN/GaN interface. In particular, the influence of the acceptor-type trap on the 2DEG density and the gate-control capability in the subthreshold region is modeled for the first time. The results have shown that the acceptor-type trap plays an important role in weakening the gate-control capability of the 2DEG density in the subthreshold region. The experimental results, together with the modeling and numerical calculations, have shown consistent 2DEG density values under various gate voltages, which verify the proposed model.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Impact of AlGaN/GaN Interface and Passivation on the Robustness of
           Low-Noise Amplifiers
    • Authors: Tongde Huang;Olle Axelsson;Johan Bergsten;Mattias Thorsell;Niklas Rorsman;
      Pages: 2297 - 2303
      Abstract: Poststress dc characteristics of AlGaN/GaN HEMTs can be used to study the effect of high-power stress on the noise figure (NF) and gain of low-noise amplifiers (LNAs) subjected to large input overdrives. This enables a shift from circuit- to transistor-level measurements to investigate the impact of variations in HEMT design parameters on the robustness (including both recovery time and survivability) by mimicking LNA operation. Using this method, a tradeoff between survivability and recovery time is demonstrated for different AlGaN/GaN interface profiles (sharp interface, standard interface, and AlN interlayer). Furthermore, the impact of different surface passivation schemes (Si-rich, Si-poor, and bilayer SiNx) on robustness is investigated. The bilayer passivation, which features low leakage current and small gain compression under overdrive stress, exhibits relatively weak survivability. The mechanisms influencing the robustness are analyzed based on transistor physics. The short recovery time is mainly due to impeding the injection of hot electrons into surface traps and high reverse current, whereas the survivability is dependent on the local or global peak electrical fields around the gate under high power stress.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Deep-Level Traps in AlGaN/GaN- and AlInN/GaN-Based HEMTs With Different
           Buffer Doping Technologies
    • Authors: P. Vigneshwara Raja;Mohamed Bouslama;Sujan Sarkar;Khade Ramdas Pandurang;Jean-Christophe Nallatamby;Nandita DasGupta;Amitava DasGupta;
      Pages: 2304 - 2310
      Abstract: Deep-level traps in AlGaN/GaN- and AlInN/GaN-based HEMTs with different buffer doping technologies are identified by drain current transient spectroscopy (DCTS) and low-frequency (LF) output admittance ( ${Y}_{{22}}$ ) dispersion techniques. TCAD simulations are also carried out to determine the spatial location and type of traps. The DCTS and LF ${Y}_{{22}}$ measurements on Al0.25Ga0.75N/GaN HEMT (Fe-doped buffer) reveal a single electron trap at ${E}_{C} - {0.47}$ eV. On the other hand, an electron trap at ${E}_{C} -$ (0.53–0.59) eV and a deep hole trap at ${E}_{V} + {0.82}$ eV are detected in Al0.845In0.155N/AlN/GaN HEMT with unintentionally doped (UID) buffer, while a slow detrapping behavior is noticed at ${E}_{C} - {0.6}$ eV in Al0.83In0.17N/AlN/GaN HEMT with C-doped buffer. The DCTS and LF ${Y}_{{22}}$ measurements yield nearly the same trap signatures, indicating the reliability of the trap characterization techniques used in this article. The simulated LF ${Y}_{{22}}$ characteristics show that all these traps are acceptor-like states located in the buffer layer. The identified trap parameters in various buffers may be helpful to improve the crystalline quality of the epitaxial buffer layers.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Optimum Carbon Concentration in GaN-on-Silicon for Breakdown Enhancement
           in AlGaN/GaN HEMTs
    • Authors: Nayana Remesh;Nagaboopathy Mohan;Srinivasan Raghavan;Rangarajan Muralidharan;Digbijoy N. Nath;
      Pages: 2311 - 2317
      Abstract: This article reports on the experimental and analytical determination of the optimum carbon concentration in GaN to achieve enhanced breakdown in AlGaN/GaN high-electron mobility transistors (HEMTs). The lateral breakdown voltage increases when carbon doping is increased from $3times 10^{{18}}$ to 1019 cm−3 beyond which it decreases, whereas there is no substantial enhancement in the vertical breakdown voltage with carbon doping. We invoke carrier statistics in a compensated semiconductor vis-à-vis the formation energy of carbon-occupying Ga (or N) vacancies to explain the observed buffer leakage. Temperature-dependent data indicate that the buffer leakage current is due to hopping transport, the activation energy of which yields the positions of the defect states within the bandgap. The increase in buffer leakage beyond optimum C concentration is attributed to the formation of shallow donor traps by carbon atoms occupying Ga vacancies (CGa). The observations correlated with the relative intensities of the defect-mediated peaks in the cathodoluminescence (CL) data of the samples. Based on our findings, a C doping beyond 1019 cm−3 is not recommended for GaN buffers in order to achieve high breakdown voltages.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Investigation of Read Disturb and Bipolar Read Scheme on Multilevel
           RRAM-Based Deep Learning Inference Engine
    • Authors: Wonbo Shim;Yandong Luo;Jae-Sun Seo;Shimeng Yu;
      Pages: 2318 - 2323
      Abstract: The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Effects of Charge Quantity Induced by Different Forming Methods in Solid
           Electrolyte GeSO-Based Resistance Switching Device With Copper Electrode
    • Authors: Po-Hsun Chen;Chen-Yi Hsieh;Hong-Yi Yang;
      Pages: 2324 - 2328
      Abstract: In this article, two different resistance switching (RS) behaviors are demonstrated after using dc and constant bias stressed (CBS) forming methods in GeSO-based resistive random access memory (RRAM) with a copper top electrode. Electrical measurements show that the amount of charge during the forming process significantly affects their RS behaviors. Large memory windows appear when applying CBS forming, while traditional dc forming did not exhibit such characteristics. Both current–voltage ( $I-V$ ) fitting and high temperature retention test are used to further investigate the RS property and verify the stability. Finally, conduction models for devices using these different forming methods are also proposed to better illustrate their different conducting behaviors in the GeSO-based RRAM device.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Efficient and Robust Spike-Driven Deep Convolutional Neural Networks Based
           on NOR Flash Computing Array
    • Authors: Yachen Xiang;Peng Huang;Runze Han;Chu Li;Kunliang Wang;Xiaoyan Liu;Jinfeng Kang;
      Pages: 2329 - 2335
      Abstract: In this article, we propose an efficient and robust spike-driven convolutional neural network (SCNN) based on the NOR flash computing array (NFCA), which is mapped by the pretrained convolutional neural network with the same structure. The spike-driven system eliminates the additional analog-to-digital/digital-to-analog (AD/DA) conversion in the NFCA-based CNN. To study the performance of the hardware implementation, an NFCA-based SCNN for the recognition of the Mixed National Institute of Standards and Technology (MNIST) data set is simulated. Simulation results illustrate that the system achieves 97.94% accuracy with the computing speed of $1 times 10^{6}$ frame per second (fps). Compared with the typical mixed-signal NFCA-based CNN, the NFCA-based SCNN saves 97% area and 56% energy consumption. Moreover, the NFCA-based SCNN demonstrates great robustness to 30% image noise with less than 2% accuracy loss. The impact of random telegraph noise (RTN) is also greatly reduced in which less than 1% accuracy decrease can be achieved at the 32-nm technology node.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Amorphous p-Type CuNiSnO Thin-Film Transistors Processed at Low
    • Authors: Xiaohan Cheng;Bojing Lu;Jianguo Lu;Siqin Li;Rongkai Lu;Shilu Yue;Lingxiang Chen;Zhizhen Ye;
      Pages: 2336 - 2341
      Abstract: In this article, we have developed an amorphous CuNiSnO (a-CNTO), which is a p-type amorphous oxide semiconductor (AOS). The a-CNTO thin films were deposited by the pulsed laser deposition method, having high amorphous quality with a rather smooth surface. The a-CNTO films grown at 100 °C exhibited the smoothest surface (root-mean-square roughness of 0.25 nm), highest visible transparency (~85%), and most favorable p-type conductivity (hole concentration of ~1015 cm−3), which are very suitable for electronic device fabrication. Thus, the obtained p-type a-CNTO thin-film transistors (TFTs) have an ON-to- OFF current ratio of $sim 1.2times 10^{{5}}$ , the threshold voltage of −2.3 V, the field-effect mobility of 1.37 cm2/Vs, and subthreshold swing of 0.70 V/decade. As a new kind of p-type AOS, the achievement of the p-type a-CNTO TFTs and the low-temperature processes may open the door for practical applications in transparent and flexible electronics.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Poly-Si Finlike Thin-Film Transistors With Various Wide Drain Designs for
           Radio Frequency and 3-D Integrated Circuits
    • Authors: Hsin-Hui Hu;Chun-Lin Huang;Yao-Jen Lee;Kun-Ming Chen;
      Pages: 2342 - 2345
      Abstract: The dc and high-frequency performance of p-type polycrystalline silicon (poly-Si) finlike thin-film transistors (FinTFTs) with various wide drain region designs are investigated herein. The poly-Si FinTFT with the triangular wide drain design exhibits a high $I_{text{ON}}/I_{text{OFF}}$ current ratio (
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Enhancement-/Depletion-Mode TiO2 Thin-Film Transistors via O2/N2
    • Authors: Jie Zhang;Guangyang Lin;Peng Cui;Meng Jia;Zhengxin Li;Lars Gundlach;Yuping Zeng;
      Pages: 2346 - 2351
      Abstract: Metal-oxide thin-film transistors (TFTs) promise to enable lightweight and low-power applications, such as ultrathin active matrix displays and low-cost RF identification tags. However, most reported high-performance metal-oxide TFTs contain high-cost indium and gallium elements, leading to constraints in cost-sensitive application. Herein, we present enhancement-/depletion-mode (E-/D-mode) TiO2 TFTs via $text{O}_{{2}}/text{N}_{{2}}$ preannealing of TiO2 channel material prior to device fabrication process. It is found that the O2-annealed TiO2 TFTs exhibit improved performances compared to N2-annealed TiO2 TFTs, including increased mobility ( $mu $ ), higher ON-/OFF-current ratio (ION/IOFF), and lower subthreshold swing (SS). This can be attributed to the passivation effects of O2 annealing, which leads to less oxygen vacancies at the channel and channel/oxide interface. On the other hand, the ionized oxygen vacancies result in the increased electron concentration in N2-annealed films and, thus, the negative shift of ${V}_{text {th}}$ in the TFT performance. This article delivers a possible approach to improve oxide TFT performance by passivation of oxygen vacancies. Furthermore, the controlled annealing process has a great potential in the logic inverter applications when both E- and D-mode TFTs are implemented.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Physical Insights Into the Mobility Enhancement in Amorphous InGaZnO
           Thin-Film Transistor by SiO2 Passivation Layer
    • Authors: Panpan Zhang;Subhranu Samanta;Xuanyao Fong;
      Pages: 2352 - 2358
      Abstract: For the first time, the mobility enhancement mechanism due to the SiO2 passivation layer (PVL) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is studied using technology-computer-aided design (TCAD) simulation. Our results indicate that the introduction of oxygen vacancies in shallow donor states around the PVL/a-IGZO interface, which donate more free electrons in the induced accumulation layer of the channel, increases the field-effect mobility of the TFT by $5.7times {}$ . Results of our TCAD simulations are strongly supported by X-ray photoelectron spectroscopy (XPS) measurements. Furthermore, TCAD analysis of a three-stage ring oscillator composed of the sample with PVL indicates 27-MHz oscillation frequency is possible at 10-V supply voltage.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • A Physical-Based Analytical Model for the Kink Current of Polycrystalline
           Silicon TFTs
    • Authors: Yanyan Chen;Xiaoliang Zhou;Dongli Zhang;Huaisheng Wang;Mingxiang Wang;
      Pages: 2359 - 2364
      Abstract: A physical-based analytical kink current model for polycrystalline -silicon (poly-Si) thin-film transistors (TFTs) has been proposed. Two important mechanisms for the kink current, namely carrier impact ionization and the parasitic bipolar junction transistor effect, are physically included in the model without introducing any artificial parameters. The proposed kink current model is fully compatible with existing ON-state drain current models of poly-Si TFTs. Model parameter extraction procedure is presented, which is based on a group of output characteristics of poly-Si TFTs with different channel lengths. The model prediction straightforwardly calculated with a set of extracted parameters is verified by excellent agreement with experimental output characteristics measured from TFTs over a range of channel lengths and gate voltages.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • High-Frequency Rectifiers Based on Organic Thin-Film Transistors on
           Flexible Substrates
    • Authors: Ghada H. Ibrahim;Ute Zschieschang;Hagen Klauk;Leonhard Reindl;
      Pages: 2365 - 2371
      Abstract: Rectifier circuits featuring low threshold voltages and high cutoff frequencies based on p-channel organic thin-film transistors (TFTs) have been designed, fabricated and characterized. The TFTs and circuits were fabricated by shadow-mask lithography on flexible plastic substrates using the vacuum-deposited small-molecule organic semiconductor dinaphtho[2,3-b: $2^prime $ , $3^prime $ -f]thieno[3,2-b] thiophene (DNTT). The TFTs have a gate dielectric with a thickness of 5.3 nm and a channel length of 10 $mu text{m}$ . The study considers the frequency characteristics of diode-connected transistors (transdiodes) and adopts circuit techniques from silicon CMOS technology, namely single-stage and multistage dynamic-threshold-compensated differential rectifiers. The characterization of the rectifier circuits indicates cutoff frequencies up to 4.75 MHz at a peak-to-peak input voltage of 3 V for transdiodes, up to 32 MHz at a peak-to-peak input voltage of 1.5 V for single-stage differential rectifiers and up to 7.5 MHz at a peak-to-peak input voltage of 1.5 V for two-stage rectifiers. The efficiency is 25% for a load of 10 $text{M}Omega $ and below 1% for a load of 1 $text{M}Omega $ .
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Effects of Redundant Electrode Width on Stability of a-InGaZnO Thin-Film
           Transistors Under Hot-Carrier Stress
    • Authors: Dong Lin;Wan-Ching Su;Ting-Chang Chang;Hong-Chih Chen;Yu-Fa Tu;Jianwen Yang;Kuan-Ju Zhou;Yang-Hao Hung;I-Nien Lu;Tsung-Ming Tsai;Qun Zhang;
      Pages: 2372 - 2375
      Abstract: In this article, the effects of redundant electrode width on stability of inverted staggered via-contact structured amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) under hot-carrier stress (HCS) were investigated. It is found that devices with a larger redundant electrode width have a severer degradation behavior after HCS. Capacitance–voltage measurements were conducted to study the degradation mechanism and technology computer-aided design (TCAD) simulation was employed to understand the different degradation behaviors.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Parametric Optimum Design and Performance Improvement of a Thermophotonic
    • Authors: Zhimin Yang;Junyi Wang;Juncheng Guo;Guoxing Lin;Jincan Chen;
      Pages: 2376 - 2380
      Abstract: An irreversible model of the thermophotonic cell (TPC) with a heated forward-based light-emitting diode (LED) as an emitter and a photovoltaic cell (PVC) is established. The performances of the TPC are optimized and compared with those of the thermophotovoltaic cell (TPVC) based on finite-time thermodynamics. The results obtained show that there exist the optimally operating ranges of the voltages and band-gap energies of the LED and PVC. The thermal flow emitted from the heated LED dramatically exceeds that from the pure thermal emitter. The maximum efficiency of the TPC is less than that of the TPVC, whereas the maximum power density of the TPC surpasses that of the TPVC under an arbitrary emitter temperature. The TPC has the advantages of the relatively high optimal band-gap energies and relatively low-operating temperatures so that it is easier to be made than the TPVC.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Design Optimization of Photovoltaic Cell Stacking in a Triple-Well CMOS
    • Authors: Geunhee Hong;Gunhee Han;
      Pages: 2381 - 2385
      Abstract: Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25- $mu text{m}$ standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm2 under an incident illumination with an intensity of $96~mu text{W}$ /mm2, achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Synthesis of Silica-Coated Cs4PbBr6 and Cs4Pb(Br0.4I0.6)6 Quantum Dots
           With Long Lifetime and Enhancement in Quantum Efficiency for WLEDs
           Applications: Lightings With High CRI and Displays With Wide Color Gamut
    • Authors: Ying-Tsuen Lin;Chien-Hao Huang;Chung-Hui Hsieh;Sheng-Yuan Chu;
      Pages: 2386 - 2392
      Abstract: To focus on developing white light-emitting diodes (WLEDs) for lightings with high color rendering index (CRI), low correlated color temperature (CCT), and the displays with wide color gamut, inorganic perovskite quantum dots (QDs) such as CsPbX3 (X = C1, Br, I) were the promising candidate owing to the excellent optoelectronic properties such as high quantum efficiency, narrow emission wavelengths, and tunable emission spectrum. Nevertheless, the CsPbBr3QDs in the form of powders or films had a poor air stability and severe decline of quantum efficiency. Therefore, in this article, a new idea was proposed that 0-D green–red perovskite QDs powders such as Cs4PbBr6 and Cs4Pb(Br0.4I0.6)6 with improved quantum efficiency and long lifetime were first developed by silica-coated method and crystal phase transition in low-temperature synthesis. The quantum efficiency in green Cs4PbBr6 powders could be significantly enhanced from 31.41% to 45.87% and red Cs4Pb(Br0.4I0.6)6 powders was 22.79%. Moreover, the as-prepared perovskite QD powders and commercial YAG phosphors combined with blue chips were applied to high-quality WLEDs for lightings and displays. More importantly, the as-fabricated wide Commission Internationale de l’Eclairage (CIE) color gamut WLEDs for displays possessed 115% National Television System Committee (NTSC) coverage rate and luminous efficiency of 51 lm/W under 20-mA driving current. On the other hand, the constructed WLEDs for high-power lightings would generate a warm white light with a luminous efficiency of 38 lm/W, extremely high CRI of 92.8, and low CCT of 3828 K under 350 mA. Hence, the proposed green–red perovskite QD powders had outstanding po-ential applications in WLEDs.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Fully Depleted MAPS in 110-nm CMOS Process With 100–300-μm
           Active Substrate
    • Authors: Lucio Pancheri;Raffaele A. Giampaolo;Andrea Di Salvo;Serena Mattiazzo;Thomas Corradino;Piero Giubilato;Romualdo Santoro;Massimo Caccia;Giovanni Margutti;Jonhatan E. Olave;Manuel Rolo;Angelo Rivetti;
      Pages: 2393 - 2399
      Abstract: This article presents a fully depleted monolithic active pixel sensor technology compatible with a standard deep submicrometer 110-nm CMOS process. Passive test pixels structures, produced in various flavors, have proved the feasibility of 100- and 300- $mu text{m}$ -thick active substrates. Active pixel sensors with monolithically integrated analog and digital electronics, consisting of a 24 $times $ 24 array of pixels with 50- $mu text{m}$ pitch, have been shown to be fully functional when operating in the full depletion mode. Characterization results obtained with a proton microbeam and a 55Fe radiation source are presented and discussed.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Ring Remote Phosphor Structure for Laser-Driven White Lighting
    • Authors: Bing-Mau Chen;Shang-Ping Ying;Hui-Hsuan Tsai;
      Pages: 2400 - 2405
      Abstract: In this article, a ring remote phosphor (RRP) structure comprising an inverted-cone-lens encapsulant and a surrounding phosphor layer was developed and used for laser-driven white lighting. The inverted-cone-lens encapsulant in the structure redirects light from a blue laser diode (LD) to the surrounding phosphor layer, thus preventing intense light from hitting the phosphor layer on a small surface and, therefore, from considerably reducing luminous efficiency. The design of the inverted-cone-lens surface of the encapsulant was investigated, and 3-D ray-trace simulations were performed to confirm its light distributions. The RRP structure with an inverted-cone-lens encapsulant and a surrounding phosphor layer was fabricated to produce laser-driven white lighting, and the optical characteristics of the RRP structure with different phosphor concentrations were examined. The output luminous flux of the RRP samples increased with increased phosphor concentration, whereas the correlated color temperature (CCT) decreased with an increase in phosphor concentration. Therefore, the RRP structure can be used to generate efficiently high-brightness white light.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography
    • Authors: Chien-Ping Wang;Yi-Pei Tsai;Burn Jeng Lin;Zheng-Yong Liang;Po-Wen Chiu;Jiaw-Ren Shih;Chrong Jung Lin;Ya-Chin King;
      Pages: 2406 - 2413
      Abstract: A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector for realizing efficient eBeam and EUV photon detection. In advanced lithography process, eBeam or EUV level projected on the wafer can be precisely recorded on the on-wafer MDA without power or batteries. The distributions and variations on the beam intensities collected by MDA can be electrically measured in real time or inline through wafer level test after eBeam or EUV exposures. The proposed MDA is expected to provide real-time feedback for the optimization and stable maintenance of advanced photolithography processed critical to the development nanometer CMOS technologies.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Analyzing the Effects of Aluminum-Doped ZnO and Ag Layers for the
           Transparent Electrode Vertical PCSS
    • Authors: Zhong Zheng;Wei Huang;Wei-Wei Han;Er-Wei Shi;
      Pages: 2414 - 2417
      Abstract: To figure out the effects of aluminum-doped ZnO (AZO) and Ag layers for the transparent electrode vertical (TEV) photoconductive semiconductor switch (PCSS) reported in our previous works, several different structures of high power, new vertical, extrinsic-triggered PCSS were designed and their performances are presented. All the PCSSs were fabricated on the vanadium compensated semi-insulating (VCSI) 4H-SiC substrates. The ON-state performance of all device versions was characterized by a test circuit without load resistor. Among all structures, the version with AZO transparent window, AZO subcontact layer, and silver mirror reflector has been testified to be the most reasonable structure, and shows the best results as well. Its minimum ON-state resistance is $6.11~Omega $ at the optical power density of 2.62 MW/cm2. The factor for the best ON-state performance of this structure is attributed to the improvement of utilization efficiency of laser energy, and good contact between the AZO and SiC substrate.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Study on the Photoluminescence Intensity, Thermal Performance, and Color
           Purity of Quantum Dot Light-Emitting Diodes Using a Pumping-Light Absorber
    • Authors: Zong-Tao Li;Cun-Jiang Song;Xue-Wei Du;Jie Xuan;Jia-Sheng Li;Yong Tang;
      Pages: 2418 - 2424
      Abstract: Quantum dots (QDs) have broad application prospects in displays such as full-color light-emitting diodes (LEDs) and micro-LEDs. However, an ultrahigh concentration of QDs is required to eliminate the pumping light for achieving high color purity, leading to significant reduction in the photoluminescence (PL) intensity of the QDs and the generation of much more heat. In this article, the PL intensity, thermal performance, and color purity of QD-LEDs were comprehensively improved by introducing a pumping-light absorber (PLA). Results indicate that the PLA packaging structure achieves a color purity that is similar to that of a conventional structure with ultrahigh QD concentration; the radiant power of blue light was reduced by 81.6% and this leads to a large shift in the color coordinates from (0.18, 0.26) to (0.20, 0.57). Moreover, the PLA packaging structure results in higher electroluminescence (EL) intensity and lower operating temperatures than the conventional structure. This is because of the higher color-conversion efficiency and partial transfer of thermal energy to the PLA layer. In particular, the EL intensity of the QD-LEDs increased by 25.1% and the steady-state temperature was reduced to 58.9 °C, which is 19.75% lower than that of a conventional structure (73.4 °C). In addition, the PLA packaging structure works equally well with ultraviolet (UV) pumping sources to achieve a higher color purity (enhancing the color gamut by 50.1% when using a 405-nm source).
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Optical Pixel Sensor Based on a-Si:H TFTs to Detect Combined Optical
           Signals for Multiuser Interactive Displays
    • Authors: Chih-Lung Lin;Chia-Lun Lee;Chia-En Wu;Fu-Hsing Chen;Wei-Sheng Liao;Ricky W. Chuang;Jian-Shen Yu;
      Pages: 2425 - 2431
      Abstract: This article presents new optical pixel sensors that are based on hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for detecting secondary color optical signals to increase the number of colors of sensed light. Three types of series-connected structure with different photo TFTs enable the sensors to receive secondary color optical input signals that combine any two primary colors, such as magenta (blue and red), cyan (green and blue), and yellow (red and green). The secondary color optical sensors also prevent from being affected by light of a single color to integrate with primary color optical sensors for realizing a six-color sensing mechanism. Moreover, only one photo TFT is used to suppress the effect of ambient white light by compensating photocurrents without increasing the complexity of the proposed sensor structure. The measurements demonstrate that the difference in the output voltages is 15.6 V even under ambient white light with an intensity of 10000 lux, proving that the proposed sensor can yield significantly different sensing results with and without an optical input signal under intense ambient white light. Thus, the proposed sensors increase the number of sensed color light that can be integrated with a large TFT-LCD panel for multiuser interaction.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Ultrahigh-Speed Mid-Infrared Photodetectors With 2-D Electron Gas in a
           CdTe/PbTe Heterojunction
    • Authors: Jiaqi Zhu;Hanlun Xu;Songsong Ma;Zhenglai Wang;Kai Li;Nasir Ali;Jie Zhong;Qiaohui Zhou;Haiming Zhu;Weien Lai;Huizhen Wu;
      Pages: 2432 - 2436
      Abstract: A CdTe/PbTe heterojunction (HJ) yields two-dimensional electron gas (2DEG) with a high electron density and mobility. Ultrahigh-speed and room-temperature operating mid-infrared photodetectors are developed with the 2DEG. The photoresponse of the detectors originates from the intrinsic response of PbTe by virtue of the conduction-band and valence-band alignment of the HJ. The extremely short rise and decay photoresponse time demonstrate a major advantage of the 2DEG. At $ lambda = {3.0},, mu text{m}$ and a bias voltage of 100 mV, the responsivity and detectivity reach 0.94 A/W and ${2} times {10}^{{10}}$ Jones, respectively. The excellent performance of the detectors renders promising applications in novel mid-infrared frequency detection systems.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • N-Buffer Design for Silicon-Based Power Diode Targeting High Dynamic
           Robustness and High Operating Temperature Over 448 K
    • Authors: Katsumi Nakamura;Shin-Ichi Nishizawa;Akihiko Furukawa;
      Pages: 2437 - 2444
      Abstract: In this article, we investigated the destructive behavior of the latest power diode when operating a hard-switching process. From the numerical simulation analysis, the destruction behavior originates in the enhanced impact ionization at the p-n junction on the anode side and current filament in the active region. A relaxing electric field on the anode side and a moderated electric field on the cathode side prevent the above-mentioned behavior. These improvements result from controlling the carrier-plasma layer in the n-buffer layer on the cathode side. This article demonstrates the effective n-buffer technology for the power diode that achieves superior dynamic robustness and high operating temperature over 448 K.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Breakdown Voltage Walk-in Phenomenon and Optimization for the Trench-Gate
           p-Type VDMOS Under Single Avalanche Stress
    • Authors: Xin Tong;Qian Liu;Li Lu;Siyang Liu;Jiaxing Wei;Weifeng Sun;Jianhui Wu;Genyi Wang;Zhuo Yang;Yuanzheng Zhu;
      Pages: 2445 - 2450
      Abstract: An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Bipolar AC (Bipac) Switch With Buried Layer for Specific AC Mains
    • Authors: Hiba Rizk;Abdelhakim Bourennane;Marie Breil;Jean-Pierre Laur;
      Pages: 2451 - 2456
      Abstract: A new vertical bipolar bidirectional switch (Bipac) with a buried layer is proposed for specific ac mains applications (230 V–50 Hz). It is mainly dedicated for the low load current ones (0.5 $text{A}_{text {rms}}$ ) and must support a voltage of 750 V in the blocking state. Moreover, the Si-chip area must not exceed 10 mm2. The study of the new proposed Bipac structure is carried out using 2-D Sentaurus physical simulation. The operating principles are first validated, and then the physical and geometrical parameters of the buried layer are determined to meet the specifications. As compared to the classical Bipac, the Bipac with a buried layer exhibits a much higher current gain that makes it more attractive in replacing the triac in the targeted applications.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Designing Beveled Edge Termination in GaN Vertical p-i-n Diode-Bevel
           Angle, Doping, and Passivation
    • Authors: Ke Zeng;Srabanti Chowdhury;
      Pages: 2457 - 2462
      Abstract: A series of electric field profile simulations in gallium nitride (GaN) p-i-n vertical diodes with negative bevel termination is carried out to optimize the bevel design. The bevel angles are varied from 90° to 0.1° with reasonably small increments to study the impact of the bevel angle on the electric field profile. The doping densities are also varied to study a more generalized trend; a new parameter defined as transition angle $theta _{{text {t}}}$ is proposed to characterize the effectivity of a beveled edge termination. Considering the potential dry etch damage on the bevel side-wall during device fabrication, the fixed surface charge from the dangling bonds and commonly used dielectric passivation are also added separately to investigate their influence. This article presents a comprehensive simulation study of GaN p-i-n diode with negative beveled edge termination, making it a useful guide for designing a simple and effective beveled edge termination, which eventually helps to enable the routine avalanche in GaN p-i-n diodes.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Optimization and Comparison of Drift Region Specific ON-Resistance for
           Vertical Power Hk MOSFETs and SJ MOSFETs With Identical Aspect Ratio
    • Authors: Haimeng Huang;Shaodi Xu;Wenjia Xu;Ke Hu;Junji Cheng;Hao Hu;Bo Yi;
      Pages: 2463 - 2470
      Abstract: This article proposes a MATLAB-based optimization methodology of the drift region specific ON-resistance ( ${R}_{on,sp}$ ) both for the high-permittivity ( $text{H}{k}$ ) MOSFETs and superjunction (SJ) MOSFETs with design parameters expressed by breakdown voltage (BV) and aspect ratio (AR). The optimized method has three distinctive features. First, based on the built-in functions in MATLAB, the proposed method is very efficient to accurately obtain the optimized ${R}_{on,sp}$ ( ${R}_{on,sp(opt)}$ ) and the design parameters for both MOSFETs. Second, as the reflection of the process difficulty in the $text{H}{k}$ or SJ structure, AR is used as one of the design variables. Third, the cubic polynomial functions are used to obtain a more accurate fitting for the optimization. The optimized results demonstrate that for a given BV, the ${R}_{on,sp(opt)}$ for the SJ MOSFET decreases as AR increases, whereas an optimum AR exists for a minimal ${R}_{on,sp(opt)}$ for the $text{H}{k}$ MOSFET. Extensive comparisons demonstrate that when AR is small and BV is large, the ${R}_{on,sp(opt)}$ for the $text{H}{k}$ MOSFET could be lower than that for the SJ MOSFET. Parameter designs are performed for the 900-V $text{H}{k}$ MOSFET and SJ MOSFET. The impacts of important parameter variations on BV and ${R}_{on,sp}$ are also discussed. The validity of the proposed optimization method is demonstrated by the TCAD simulations.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Influence of Different Surface Morphologies on the Performance of
           High-Voltage, Low-Resistance Diamond Schottky Diodes
    • Authors: Philipp Reinke;Fouad Benkhelifa;Lutz Kirste;Heiko Czap;Lucas Pinti;Verena Zürbig;Volker Cimalla;Christoph Nebel;Oliver Ambacher;
      Pages: 2471 - 2477
      Abstract: Vertical diamond Schottky diodes with blocking voltages ${V}_{text {BD}}> {2.4}$ kV and ON-resistances ${R}_{textsf {ON}} < {400}~text{m}Omega $ cm 2 were fabricated on homoepitaxially grown diamond layers with different surface morphologies. The morphology (smooth as-grown, hillock-rich, polished) influences the Schottky barrier, the carrier transport properties, and ultimately the device performance. The smooth as-grown sample exhibited a low reverse current density ${J}_{text {Rev}} < {10},,^{mathrm{ -4}}$ A/cm 2 for reverse voltages up to 2.2 kV. The hillock-rich sample blocked similar voltages with a slight increase in the reverse current density ( ${J}_{text {Rev}} < {10},,^{mathrm{ -3}}$ A/cm 2). The calculated 1-D breakdown field, however, was reduced by 30%, indicating a field enhancement induced by the inhomogeneous surface. The polished sample demonstrated a similar breakdown voltage and reverse current density as the smooth as-grown sample, suggesting that a polished surface can be suitable for device fabrication. However, statistical analysis of several diodes of each sample showed the importance of the substrate quality: a high density of defects both reduces the feasible device area and increases the reverse current density. In forward direction, the hillock-rich sample exhibited a secondary Schottky barrier, which could be fit with a modified thermionic emission (TEM) model employing the Lambert W-function. Both polished and smooth samples showed nearly ideal TEM with ideality factors 1.08 and 1.03, respectively. Compared with the literature,-all three diodes exhibit an improved Baliga figure of merit for diamond Schottky diodes with ${V}_{text {BD}}>{2}$ kV.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Mechanisms of Asymmetrical Turn-On and Turn-Off and the Origin of Dynamic
           CGD Hysteresis for Hard-Switching Superjunction MOSFETs
    • Authors: H. Kang;E. M. Findlay;F. Udrea;
      Pages: 2478 - 2481
      Abstract: The dV / dt in superjunction metal–oxide–semiconductor field-effect transistors (MOSFETs) during the turn-off transient has been shown to be higher than during the turn-on, which can be attributed to a shorter Miller plateau. In this article, we will show that these asymmetrical turn-on and turn-off characteristics are indirectly detected by the hysteresis of the dynamic gate-to-drain capacitance, ${C}_{text {GD}}$ . Moreover, this article reveals the mechanisms behind the asymmetrical switching and the origin of the hysteresis, which have been shown to be caused by the difference in the ${C}_{text {GD}}$ displacement current paths for the turn-off and the turn-on.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • A Trench-Field-Plate High-Voltage Power MOSFET
    • Authors: Chao Xiao;Wentao Yang;Yong Liu;Xianda Zhou;Hao Feng;Johnny K. O. Sin;
      Pages: 2482 - 2488
      Abstract: In this article, a trench-field-plate (TFP) high-voltage power MOSFET is proposed. Instead of using a conventional n− drift region, the TFP power MOSFET features benzocyclobutene dielectric in the sidewall of deep trenches in the drift region and a sloped field plate (FP) inside each of the trenches. The TFP structure employed in the drift region modulates the electric field in the OFF-state, resulting in a higher breakdown voltage (BV) than that of conventional power MOSFETs. Simulation results show that the specific ON-resistance of the TFP power MOSFET is approximately one-third that of the conventional power MOSFET and about 50% lower than that of the silicon limit for the same BV. In addition, compared with superjunction devices, the TFP power MOSFET is able to provide better reverse recovery characteristics, including a reduction in peak reverse recovery current ( ${I}_{{text {RRM}}}{)}$ and reverse recovery charge ( ${Q}_{{text {RR}}} {)}$ by 24% and 37%, respectively. Moreover, a p-i-n diode employing the TFP structure is fabricated, which is essentially identical to a power MOSFET in the OFF-state, to demonstrate the BV characteristics. The fabricated TFP p-i-n diode has a BV of 522 V, which is 2.3 times that of a conventional p-i-n diode fabricated on the same substrate.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • High-k HfxZr1-xO₂ Ferroelectric Insulator by Utilizing High Pressure
    • Authors: Dipjyoti Das;Sanghun Jeon;
      Pages: 2489 - 2494
      Abstract: In this article, we report the fabrication of Zr-rich high- ${k}$ ferroelectric hafnium zirconium oxide (HZO) capacitor with TiN as the top and bottom electrodes demonstrating an equivalent oxide thickness (EOT) of 5.7 Å and remanent polarization ( ${P}_{r}$ ) of $sim 16~mu text{C}$ /cm2. High- ${k}$ value and low EOT was achieved by utilizing multiphase region of HZO as well as high pressure post metallization annealing (HPPMA). Despite the high- ${k}$ value of Zr-rich HZO films, the emergence of multiphase region at higher physical thickness when annealed using rapid thermal annealing (RTA) limits its EOT value. On the contrary, multiphase emerges at a smaller physical thickness in HPPMA due to the formation of more o-phase as revealed by grazing incidence X-ray diffractometer (GIXRD). The smaller physical thickness of HPPMA together with the demonstration of significantly higher dielectric constant (>50) by HZO in the vicinity of multiphase, was therefore, found to be very effective in reducing the EOT.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Integration, BEOL, and Thermal Stress Impact on CMOS-Compatible
           Titanium-Based Contacts for III–V Devices on a 300-mm Platform
    • Authors: F. Boyer;K. Dabertrand;C. Jany;P. Gergaud;N. Coudurier;F. Nemouchi;M. Grégoire;Q. Rafhay;Ph. Rodriguez;
      Pages: 2495 - 2502
      Abstract: Titanium-based contacts are envisioned for the integration of III–V device contacts on a 300-mm platform, such as photodetectors, semiconductor optical amplifiers (SOAs), and III–V silicon hybrid lasers. For the first time, the impact of the thermal budgets of process integration, back-end of line (BEOL), and long-term thermal stress on the electrical characteristics of the Ti/p-In0.53Ga0.47As and Ti/n-InP contacts has been investigated. Additional physical characterizations have been used to supplement the electrical properties on both systems. Results have indicated that, given a thermal budget between 350 °C and 450 °C during 60 s right after metal deposition, 1) Ti as a contact metal has led to contact resistivity in low $10^{-{5}},,Omega cdot text {cm}^{{2}}$ for p-contacts and in mid $10^{-{5}},,Omega cdot text {cm}^{{2}}$ for n-contacts, which is in accordance with the device requirements; and 2) process integration, BEOL, and long-term thermal stress will not induce any change of the electrical properties. In the scope of III–V silicon hybrid laser contact integration, Ti has hence been evidenced as a suitable candidate for both p- and n-contacts.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Experimental Study of 1/f1+α Noise in Transient Leakage Current of
           Metal–Insulator–Metal With Stacked High-k Polycrystalline Films
    • Authors: Hsin-Jyun Lin;Koji Akiyama;Yoshihiro Hirota;Yasushi Akasaka;Genji Nakamura;Hiroyuki Nagai;Tamotsu Morimoto;Hiroshi Watanabe;
      Pages: 2503 - 2509
      Abstract: We have observed and analyzed the ${1}/{f}^{{1}+alpha }$ noise in transient leakage current through a metal–insulator–metal stacked high- ${k}$ capacitor of TiN–ZrO2–TiO2–TiN. The ZrO2 and TiO2 films, formed by atomic layer deposition, are polycrystalline and show geometrical variety at interfaces (i.e., grain boundaries). Two types of transient leakage current are observed: 1) the monotonically decreasing component with power law dependence and 2) the uneven component having power law dependence. To analyze the uneven component in time domain, we assumed that the power law decay occurs due to a gradual change in the redistribution of electrons between interfaces of ZrO2–TiN and ZrO2–TiO2. The frequency-domain analysis shows that the ${1}/{f}^{{1}+alpha }$ noise comes from the transient leakage of direct tunneling and trap-assisted tunneling ( $alpha> {0}$ ). In particular, the noise in the uneven component, the random telegraph noise part ( ${alpha sim {1}}{)}$ , relates to local trap states in a grain boundary affected by phonon scattering. In addition, the analytical method we developed in this article shows an excellent agreement with various measurements of the transient gate leakage current.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Sublithographic Patterning of Spin-Coated SiARC Films Using Tilted Ion
    • Authors: Thomas R. Rembert;Shalini Sharma;Luis Garcia;Daniel Connelly;Taji Tomoya;Tatsuya Sakai;Leonard Rubin;Tsu-Jae King Liu;
      Pages: 2510 - 2515
      Abstract: Tilted ion implantation (TII) used in conjunction with preexisting masking features on the surface of a wafer is a relatively low-cost method for sublithographic patterning. Previous demonstrations of this method utilized a thin thermally grown layer of silicon oxide (SiO2) as the implanted layer, with amorphous-silicon masking features, to form patterns with feature sizes as small as 9 nm. In this article, this method is adapted to be compatible with back-end-of-line (BEOL) processing using silicon-containing antireflection coating (SiARC) as the implanted layer, with photoresist masking features formed using deep-ultraviolet (DUV) lithography. Negative-tone patterning of an ~15-nm-thick SiARC film is achieved by implanting Ar+ ions to selectively reduce its wet etch rate, allowing for the subsequent selective removal of the SiARC material from unimplanted regions. Patterned features down to 20 nm in lateral dimension are demonstrated.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Impact of Electrical Stress on Defect Generation in Thin GeO2/Ge Gate
           Stacks Fabricated by Thermal Oxidation
    • Authors: Sicong Yuan;Zhuo Chen;Junkang Li;Minzhi Tian;Rui Zhang;
      Pages: 2516 - 2521
      Abstract: The impact of electrical stress on the defect generation behaviors in thin GeO2/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO2/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence ( ${Q} _{{text {inj}}}$ ), and the fix charge generation is attributed to both ${Q} _{{text {inj}}}$ and GeO2 thickness.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • The Effect of Torsional Bending on Reliability and Lifetime of Printed
           Silver Conductors
    • Authors: Esa Hannila;Kari Remes;Timo Kurkela;Tuomas Happonen;Kimmo Keränen;Tapio Fabritius;
      Pages: 2522 - 2528
      Abstract: Capability of high-speed and low-cost manufacturing makes the printing techniques a very promising approach for large-area flexible electronics mass manufacturing. Due to fast and intensive technology development, the lack of knowledge about the reliability and lifetime of printed electronics is obvious, requiring further investigation. Especially, the effect of torsional bending on lifetime is a mostly unexplored field of reliability testing. In this article, a torsional bending test of parallel printed silver conductors (0.3-, 0.5-mm pitch) on polymer substrate (polyethylene terephthalate, 125- $mu text{m}$ thickness) was conducted and analyzed. According to the experimental results, torsional bending causes wear-out type failures in conductors and the length-to-width (LTW) ratio of the sample’s substrate was observed to have a significant impact on reliability. If the LTW ratio is smaller than 3, the lifetime of printed conductor seems to collapse and samples lasted for approximately only 17 bending cycles on average. Lifetime was improved by increasing the LTW ratio and samples withstood over hundreds of cycles with LTW ratio of higher than 15. However, the distance of a conductor from the edge of the substrate was not observed to have any significant influence on the reliability under torsional bending.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Interesting Odd–Even Effect, Ohmic Contact, Negative Differential
           Resistance, and Current Stabilizer Behavior in All-Carbon
           Graphyne/Carbon-Chain Junctions
    • Authors: Jiangni Yun;Huan An;Renjing Huang;Mingzhi Guo;Yanni Zhang;Peng Kang;
      Pages: 2529 - 2535
      Abstract: A new and simple kind of all-carbon junction nanodevice, which is free of metal electrodes, is constructed by carbon chains seamlessly connected to two graphyne nanoribbons (GYNRs) electrodes. The electron transport properties of the constructed nanodevices are systematically investigated using self-consistent charge density-functional tight-binding combined with nonequilibrium Green’s function (NEGF) formalism. The effects of contact type and contact position on the electron transport properties of these devices are discussed. The calculated results show that the electron transport properties can be well modulated by the contact geometry of the carbon chain. In GYNRs connected by both horizontal and tilted single-carbon chain, an evident even–odd behavior of conductivity is observed. In addition, the linear, monotonous currents in a wide bias voltage range show good Ohmic contact. The negative differential resistance also appears under both positive and reverse bias voltages, indicating applications in bidirectional tunnel diodes. Comprehensive analyses of the physical mechanisms for the odd–even behavior are given. Remarkably, in GYNRs connected by double-carbon chains, a noticeable current stabilizer behavior occurs, suggesting that the graphyne nanodevices contacted with double-carbon chains can be used as a current stabilizer in circuits. This article provides valuable insight into all-carbon functional nanodevices.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Analytical Model for Low-Frequency Noise in Junctionless Nanowire
    • Authors: Renan Trevisoli;Marcelo Antonio Pavanello;Carlos Eduardo Capovilla;Sylvain Barraud;Rodrigo Trevisoli Doria;
      Pages: 2536 - 2543
      Abstract: This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model’s applicability and accuracy.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon
           Carbide MOSFETs
    • Authors: Ujjwal Karki;Nomar S. González-Santini;Fang Z. Peng;
      Pages: 2544 - 2552
      Abstract: Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Thermal Brownian Motion of Skyrmion for True Random Number Generation
    • Authors: Yong Yao;Xing Chen;Wang Kang;Youguang Zhang;Weisheng Zhao;
      Pages: 2553 - 2558
      Abstract: True random number generators (TRNGs) have received extensive research owing to their wide applications in information processing, transmission, and encryption. Recently, TRNGs have also been employed in emerging stochastic/probabilistic computing paradigms. TRNGs can be designed based on, for example, oscillator sampling, noise amplifying, and quantum physical effect with the aid of peripheral postprocessing circuitry. With the rapid development of emerging nanoscale devices, such as resistive devices, spintronic devices, and photonic devices, a rich variety of TRNG prototypes have been proposed in the literature. Very recently, skyrmion has emerged as a promising candidate for implementing TRNGs because of the nanometer size and, more importantly, the intrinsic thermal Brownian motion dynamics. In this article, we propose for the first time a TRNG based on the continuous skyrmion thermal Brownian motion in a confined geometry at room temperature. Random bitstream (with equal probability of ~50% for bits “0” and “1”) can be obtained by periodically detecting the relative position of the skyrmion without the need for any additional activations. Furthermore, we implemented a probability-adjustable TRNG, in which a desired probability for bit “0” and bit “1” can be acquired by adding an anisotropy gradient in the device through the voltage-controlled magnetic anisotropy (VCMA) effect. The behaviors of the proposed skyrmion-based TRNGs were studied by using micromagnetic simulations, and the generated random bitstream was tested by the National Institute of Standards and Technology (NIST) suits. Our results demonstrated that the proposed skyrmion-based TRNGs can achieve good randomness with high frequency (>1 GHz) and energy efficiency (< 10 fJ-bit).
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Automated Mini-Platform With 3-D Printed Paper Microstrips for Image
           Processing-Based Viscosity Measurement of Biological Samples
    • Authors: Puneeth S B;Nikhil Munigela;Sai Akhil Puranam;Sanket Goel;
      Pages: 2559 - 2565
      Abstract: Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ( $mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • New Room Temperature Ammonia Gas Sensor Synthesized by a Tantalum
           Pentoxide (Ta2O5) Dielectric and Catalytic Platinum (Pt) Metals
    • Authors: Bo-You Liu;Wen-Chau Liu;
      Pages: 2566 - 2572
      Abstract: A new room temperature (25 °C) ammonia gas sensor based on a metal-oxide-semiconductor (MOS) diode is reported. The device structure is synthesized by a sputtered tantalum pentoxide (Ta2O5) dielectric, evaporated platinum nanoparticles (Pt NPs), and a Pt thin film on a GaN/AlGaN heterostructure. Pt NPs can effectively increase the specific surface area and related catalytic reactivity of Pt metal. In experiment, the studied Pt NP/Pt/Ta2O5/GaN/AlGaN MOS device shows good ammonia sensing properties including a high sensing response of 74.4 under 1000 ppm NH3/air gas and a sub-ppm (100 ppb) detecting level at room temperature. The studied MOS diode has the advantages of low power, low cost, and a widespread concentration range (0.1–1000 ppm NH3/air) for ammonia sensing operation. The ammonia sensing mechanism and a thermodynamic analysis to study the related interface coverage are included in this article. The studied MOS diode also exhibits advantages of good selectivity toward ammonia gas and a simple device structure.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • A V-Band Overmoded Coaxial Millimeter-Wave Oscillator Based on a New
           Method of Asymmetric Modes Suppression
    • Authors: Siyao Chen;Jun Zhang;Jiande Zhang;Haitao Wang;
      Pages: 2573 - 2579
      Abstract: In the design of the coaxial millimeter-wave Cerenkov devices due to the low starting current and high temporal growth, asymmetric quasi-TEv1 modes are always preferentially excited. This article proposes a new method of hybrid modes coupling to suppress the asymmetric modes. The results show that when the quasi-TEM (N −1) $pi $ /N mode couples with the TM01 ( ${N} -{3}) pi $ /N mode, the asymmetric modes can be suppressed effectively. The external ${Q}$ -factor, electric field distribution, and the beam conductance of the hybrid modes are analyzed theoretically to explain the mechanism of the asymmetric modes suppression. According to this method, a coaxial ${V}$ -band millimeter-wave oscillator is proposed. The 3-D particle-in-cell simulation results show that the symmetric modes are generated and all the asymmetric modes are suppressed successfully. When the diode voltage is 355 kV and beam current is 3 kA, the dominant frequency is 62.6 GHz and the output power is 322 MW, corresponding to a beam–wave conversion efficiency of 30.2%.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Influence of the Surface Tungsten Distribution on the Emission Properties
           of Barium Tungsten Cathode
    • Authors: Jihua Shang;Xinyu Yang;Ziyu Wang;Mengyuan Hu;Cuiliu Han;Jiuxing Zhang;
      Pages: 2580 - 2584
      Abstract: The porous tungsten matrixes of barium tungsten cathodes are prepared by spark plasma sintering (SPS). By adjusting the raw powder particle diameter and the porosity, the matrixes with different average distances between the pores are obtained. The microstructure and the emission performance of the barium tungsten cathode are analyzed using scanning electron microscopy (SEM), electron emission measurement system, and X-ray photoelectron spectroscopy (XPS). The average distances between the pores of three cathodes are 5.08, 5.74, and $6.91,mu text{m}$ , respectively. The cathode with a distance of $5.74,,mu text{m}$ has the best zero-field current density and the lowest work function. With the increase in the pulsewidth, the variation rate of the current density for the 5.74- $mu text{m}$ cathode is the smallest, indicating the emission stability is the best. The best emission performance can be ascribed to the formation of the optimal Ba–O dipoles’ coverage on the cathode surface.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Multiple-GPU-Based Simulation of Ka-Band Helix Traveling
           Wave Tube
    • Authors: Xiaoyue Wang;Qi Chen;Mingzhi Li;
      Pages: 2585 - 2592
      Abstract: The finite-difference time-domain (FDTD) algorithm and the particle-in-cell (PIC) method-based simulation are classic approaches to design and optimize the helix traveling wave tubes (TWTs). In this article, a multiple-graphics processing unit (GPU)-based 3-D-FDTD-PIC parallel program is developed to complete the full-wave simulation of a Ka-band helix TWT in the time domain. The specific parallel simulation scheme is given. The code based on compute unified device architecture (CUDA) and message passing interface (MPI) can run on a scalable heterogeneous cluster consisting of multiple CPUs and GPUs, substantially improving the simulation speed and shortening the development period of TWTs. In this article, the specific parameters of the experimental TWT are given. The simulation results are found basically consistent with the measured values and theoretical analysis, verifying the correctness of this code. Moreover, this program can realistically restore the physical processes occurring in the tube in a short period of time, which means it can be applied as an efficient simulation tool for further research of TWTs or even other microwave power devices based on beam–wave interaction.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
    • Authors: Vita Pi-Ho Hu;Hung-Han Lin;Yen-Kai Lin;Chenming Hu;
      Pages: 2593 - 2599
      Abstract: We investigate the GaAs0.51Sb0.49/In0.53Ga0.47As negative-capacitance vertical-tunnel FET (NCVT-FET) to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. By TCAD optimization of the device, small ${I}_{{mathrm {OFF}}}$ (10 pA/ $mu text{m}$ ) and large ${I}_{text{ON}}$ ( $405~mu text{A}/mu text{m}$ ) at ${V}_{text {DD}} = {0.5}$ V with 14 mV/dec sub- ${V}_{text {t}}$ swing over 4 dec of current were obtained. Even at ${V}_{text {DD}} ={0.1}$ V, the optimized NCVT-FET has 10 pA/ $mu text{m}~{I}_{text{OFF}}$ , $5.86~mu text{A}/mu text{m}~{I}_{text{ON}}$ ( $144times $ higher than the nominal TFET), and ${I}_{text{ON}}/{I}_{text{OFF}}$ ratio of ${6} times {10}^{{5}}$ .
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Simulation-Based Ultralow Energy and High-Speed LIF Neuron Using Silicon
           Bipolar Impact Ionization MOSFET for Spiking Neural Networks
    • Authors: Alok Kumar Kamal;Jawar Singh;
      Pages: 2600 - 2606
      Abstract: The silicon bipolar impact ionization MOSFET offers potential for the realization of leaky integrated fire (LIF) silicon neuron due to the presence of parasitic bipolar junction transistor (BJT) in the floating body. In this article, we have proposed an L-shaped gate bipolar impact ionization MOS (L-BIMOS) with reduced breakdown voltage ( ${V}_{B} = {1.68}$ V) and demonstrated the functioning of LIF neuron based on the positive feedback mechanism of parasitic BJT. Using the 2-D TCAD simulations, we manifest that the proposed L-BIMOS exhibits a low threshold voltage (0.2 V) for firing a spike, and the minimum energy required to fire a single spike for L-BIMOS is calculated to be 0.18 pJ, which makes the proposed device 194 times more energy efficient than the PD-SOI MOSFET silicon neuron and ${5}times {10}^{{3}}$ times more energy efficient than the analog/digital circuit-based conventional neurons. Furthermore, the proposed L-BIMOS silicon neuron exhibits spiking frequency in the gigahertz range when the drain is biased at ${V}_{text {DG}} = {2.0}$ V.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Assessing the Role of a Semiconductor’s Anisotropic Permittivity in
           Hafnium Disulfide Monolayer Field-Effect Transistors
    • Authors: Robert K. A. Bennett;Demin Yin;Youngki Yoon;
      Pages: 2607 - 2613
      Abstract: 2-D semiconductors show great promise to serve as channel materials in next-generation field-effect transistors (FETs). The permittivity of many 2-D semiconductors is anisotropic, though many recent simulation works studying 2-D FETs have treated these materials as though they have isotropic permittivities. Because there have been no works that investigate the role of each element of a semiconductor’s anisotropic permittivity on a device’s performance, the impact that this isotropic approximation has on a simulation’s accuracy is unknown. Furthermore, the impact of a semiconductor’s anisotropic permittivity on a device’s performance cannot be explained using existing theory. In this simulation study, we investigate, for the first time, the impact of a semiconductor’s anisotropic permittivity on the performance of FETs. Our main findings are that the isotropic approximation becomes inaccurate as the channel lengths of FETs are scaled down and that short-channel effects become less significant when the semiconductor’s in-plane permittivity decreases or its out-of-plane permittivity increases. We also find that the capacitance of the semiconductor in the out-of-plane direction (i.e., the capacitance associated with the out-of-plane permittivity) more significantly influences a device’s gate capacitance when equivalent oxide thickness (EOT) decreases. Therefore, EOT alone cannot be used to assess total gate control in aggressively scaled 2-D devices.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Band-to-Band Tunneling Based Ultra-Energy-Efficient Silicon Neuron
    • Authors: Tanmay Chavan;Sangya Dutta;Nihar R. Mohapatra;Udayan Ganguly;
      Pages: 2614 - 2620
      Abstract: The human brain comprises about a hundred billion neurons connected through quadrillion synapses. Spiking neural networks (SNNs) take inspiration from the brain to model complex cognitive and learning tasks. Neuromorphic engineering implements SNNs in hardware, aspiring to mimic the brain at scale (i.e., 100 billion neurons) with biological area and energy efficiency. The design of ultra-energy-efficient and compact neurons is essential for the large-scale implementation of SNNs in hardware. In this article, we have experimentally demonstrated a partially depleted (PD) silicon-on-insulator (SOI) MOSFET-based leaky integrate-and-fire (LIF) neuron, where energy efficiency and area efficiency are enabled by two elements of the design–first is the tunneling-based operation and the second is a compact subthreshold SOI control circuit design. Band-to-band tunneling (BTBT)-induced hole storage in the body is used for the “integrate” function of the neuron. A compact control circuit “fires” a spike when the body’s potential exceeds the firing threshold. The neuron then “resets” by removing the stored holes from the body contact of the device. Additionally, the control circuit provides “leakiness” in the neuron, which is an essential property of the biological neurons. The proposed neuron provides $10times $ higher area efficiency compared to the CMOS design with equivalent energy/spike. Alternatively, it has a $10^{4}times $ higher energy efficiency at area-equivalent neuron technologies. Biologically comparable energy efficiency and area efficiency, along with CMOS compatibility, make the proposed device attractive for large-scale hardware -mplementation of SNNs.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Compact Model of Dzyaloshinskii Domain Wall Motion-Based MTJ for Spin
           Neural Networks
    • Authors: Chao Wang;Zhaohao Wang;Min Wang;Xueying Zhang;Youguang Zhang;Weisheng Zhao;
      Pages: 2621 - 2626
      Abstract: Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Deep Gate Field Penetration Au:ZrO2 Metal–Insulator
           Tunneling Transistor
    • Authors: A. J. McDermott;A. Y. Elezzabi;
      Pages: 2627 - 2632
      Abstract: A new class of metal–insulator tunneling transistor (MITT) devices is proposed and investigated. The planar dual-gate structure allows for complete gate field penetration of the transistor channel to modulate tunneling current across the channel. For a 5-nm channel length, with contact geometries that reflect the reality of fabricating at such a scale, we show that a 10% decrease in the effective electron tunneling length results in a $5.5times $ increase in current up to $4.4{times }10^{-6} mA/mu {}m$ . The device demonstrates an ON-/ OFF-current ratio that is $2.5times $ greater than that of a complementary metal–oxide–semiconductor (CMOS)-style MITT with a 5-nm channel length. Without the use of a second gate insulator, the source-to-drain current density is more than 104 times greater than the source-to-gate leakage current density, indicating the efficacy of the presented realistic MITT implementation.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus
           GAA-FET Versus UFET
    • Authors: Uttam Kumar Das;Tarun Kanti Bhattacharyya;
      Pages: 2633 - 2638
      Abstract: The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current ( ${I}_{eff}$ ) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in total current driving capability ( ${I}_{eff}$ ). Therefore, to enable future devices, we explored electrostatics and effective drive current ( ${I}_{eff}$ ) in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced device simulator, TCAD Sentaurus.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Transformable Junctionless Transistor (T-JLT)
    • Authors: Jin-Woo Han;Jungsik Kim;M. Meyyappan;
      Pages: 2639 - 2644
      Abstract: A conductivity type transformable junctionless transistor (T-JLT) is proposed. Two complementary doped, i.e., n- and p-type, polysilicon films thinner than 5 nm are arranged orthogonally with a dielectric in between, where each film plays a role as a source, a channel, a drain, and a gate, respectively. The role of the film is interchangeable by contact allocation. By swapping the contact assignment, the n- and p-type transistors attain the given device structure. This versatility reduces approximately four or two ion implantations and the associated implant-masking lithography steps compared to the conventional inversion mode or JLT technologies, respectively. For the n-FET mode with a film thickness of 5 nm and doping concentration of ${1} times {10}^{{19}}$ /cm3, a threshold voltage of 0.42 V, a subthreshold swing of 172 mV/dec, an ON-current of $77.6~mu text{A}/mu text{m}$ , and an OFF-current of 100 fA/ $mu text{m}$ were obtained.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Separation of Lateral Migration Components by Hole During the Short-Term
           Retention Operation in 3-D NAND Flash Memories
    • Authors: Shinkeun Kim;Haesoo Kim;Changbeom Woo;Gil-Bok Choi;Moon-Sik Seo;Hyunyoung Shim;Keum Hwan Noh;Hyungcheol Shin;
      Pages: 2645 - 2647
      Abstract: In this brief, we modeled the charge loss in the program verify level 1 (PV1) during the short-term retention operation. As a result, we confirmed that the charge loss in the lateral direction [lateral migration (LM)] was affected by the residual hole at the edge of the target word line (WL). Unlike the other PV levels, LM could be modeled separately in the PV1 by LM caused by electrons (LME) and LM caused by the residual hole (LMH). Also, PV1, which stores a relatively small amount of electrons compared to the other PV levels, was hardly affected by the adjacent cells, so there was almost no difference between solid (S/P) and checker-board (C/P). In order to model the PV1 state, we carried out the modeling considering the four charge loss mechanisms based on the short-term retention data measured at various temperatures (25–115 °C).
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Investigation of Electrical Characteristic Behavior Induced by
           Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
    • Authors: Sihyun Kim;Munhyeon Kim;Donghyun Ryu;Kitae Lee;Soyoun Kim;Junil Lee;Ryoongbin Lee;Sangwan Kim;Jong-Ho Lee;Byung-Gook Park;
      Pages: 2648 - 2652
      Abstract: In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Low Temperature Processing of Electronic Materials for Cuttung Edge
    • Pages: 2653 - 2654
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • Introducing IEEE Collabratec
    • Pages: 2655 - 2655
      Abstract: Advertisement.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
  • IEEE Open Access Publishing
    • Pages: 2656 - 2656
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: June 2020
      Issue No: Vol. 67, No. 6 (2020)
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