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  Subjects -> ELECTRONICS (Total: 179 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 78)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 313)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 266)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 105)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 92)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 189)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 66)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 71)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 24)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access  
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 167)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 19  
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [191 journals]
  • IEEE Transactions on Electron Devices publication information
    • Abstract: Provides a listing of current staff, committee members and society officers.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • IEEE Transactions on Electron Devices information for authors
    • Abstract: Provides instructions and guidelines to prospective authors who wish to submit manuscripts.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • [Blank page]
    • Abstract: This page or pages intentionally left blank.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Drain-Engineered TFET With Fully Suppressed Ambipolarity for
           High-Frequency Application
    • Authors: Mohd Rizwan Uddin Shaikh;Sajad A Loan;
      Pages: 1628 - 1634
      Abstract: In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel fieldeffect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length (λ) by varying the silicon film (tSi,v) and the oxide (tSi,v) thicknesses at the channel-drain junction to overcome the limitations of high ambipolar leakage in the conventional double-gate TFET (DG-TFET). A 2-D calibrated simulation study has revealed the doubling of on-current (ION) and significantly suppressed ambipolar leakage (IAMB) in the proposed device as compared to the conventional DG-TFET. Furthermore, a five orders of magnitude improvement in ION/IOFF, 73% increase in transconductance (gm), 62% increase in cutoff frequency (fT), 72% increase in gain-bandwidth product, and 54% improvement in fall propagation delay (tpHL) are achieved in the proposed device.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • ${p}$+ -FinFET+Applications&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Jayeeta&;Nilay+Pradhan;Dipankar+Biswas;Sudipta+Das;Suddhasatta+Mahapatra;Saurabh+Lodha;">Impact of Punch-through Stop Implants on Channel Doping and Junction
           Leakage for Ge ${p}$ -FinFET Applications
    • Authors: Jayeeta Biswas;Nilay Pradhan;Dipankar Biswas;Sudipta Das;Suddhasatta Mahapatra;Saurabh Lodha;
      Pages: 1635 - 1641
      Abstract: Fin field-effect transistor (FinFET) scaling beyond the 10-nm node requires formation of a junction isolation region between the source and the drain to suppress sub-fin leakage current. In this paper, heavy species such as Sb and As were implanted at room temperature to form a punch-through stop (PTS) layer in n-Ge substrates. The impact of PTS implants on channel doping and defects, as well as junction leakage, was investigated for bulk Ge p-FinFET applications. We report retrograde doping profiles with a low surface (channel) dopant concentration of 4-5 × 1016 cm-3 for Sb PTS implants post 550 °C and 650 °C activation anneals. Besides achieving low effective channel doping, the 650 °C high-temperature activation anneal post PTS implant also helps in the reduction of channel defect density. Furthermore, low junction leakage currents are also demonstrated for Sb and As PTS implants with 550 °C and 650 °C activation anneals. To avoid damaging the FinFET channel layer due to PTS ion implantation, Ge homoepitaxy was also studied post Sb PTS implants. However, Sb PTS implants activated at 650 °C without Ge epitaxy exhibit the best results in terms of low channel dopant and defect concentrations, besides junction leakage.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With
           a Diode
    • Authors: Da-Wei Lai;Stephen Sque;Wim Peters;Theo Smedes;
      Pages: 1642 - 1647
      Abstract: We demonstrate a gate-lifted nMOS electrostatic discharge (ESD) protection device triggered by a p-n-p in series with a diode in a 0.18-μm bulk CMOS technologyfor 5-V mobile applications up to 85 °C. This voltage-triggering scheme is suitable for fail-safe, open-drain, supply, and surge protections. In addition, the robust ESD performance is boosted by parasitic embedded-silicon-controlledrectifier action in the high-current regime. No extra masks nor additional RC control circuitry are required for this implementation.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of
           CMOS Integrated Circuits
    • Authors: Chun-Cheng Chen;Ming-Dou Ker;
      Pages: 1648 - 1655
      Abstract: A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18-μm 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input-output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET's to the power rails (VDD or VSS). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si
    • Authors: Jang Hyun Kim;Sangwan Kim;Byung-Gook Park;
      Pages: 1656 - 1661
      Abstract: This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current (ION) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and 104 ON/OFF current ratio (ION/IOFF) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ID regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient
           Circuit-Level Modeling
    • Authors: K.-U. Giering;K. Puschkarsky;H. Reisinger;G. Rzepa;G. Rott;R. Vollertsen;T. Grasser;R. Jancke;
      Pages: 1662 - 1668
      Abstract: We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy of both models is evidenced from single-FET analog-stress and circuit-level ring oscillator experiments. Their numerical efficiency allows direct coupling to circuit simulators and permits to accurately account for NBTI already during circuit design. Furthermore, one of the models calculates the time-dependent NBTI variability of single-FET and of circuit performance parameters. We demonstrate our NBTI models on a ring oscillator and calculate the mean drift and statistical distribution of its oscillation frequency.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Experimental Investigation of Remote Coulomb Scattering on Mobility
           Degradation of Ge pMOSFET by Various PDA Ambiences
    • Authors: Lixing Zhou;Xiaolei Wang;Kai Han;Xueli Ma;Yanrong Wang;Jinjuan Xiang;Hong Yang;Jing Zhang;Chao Zhao;Tianchun Ye;Wenwu Wang;
      Pages: 1669 - 1674
      Abstract: The impact of various postdeposition annealing (PDA) ambiences (N2, O2, and NH3) on the hole mobility of germanium (Ge) pMOSFET with GeO2/Al2O3 gate-stack is investigated. It is found that the mobility is about 10% higher after N2 PDA, while it is about 10% smaller after O2 and NH3 PDA than that without PDA. The physical origin is attributed to the remote Coulomb scattering. The Ge/GeO2 interface charge Q1 decreases, but the GeO2/Al2O3 interface dipole Qdipole increases after PDA in N2, O2, and NH3. The higher mobility after N2 PDA is due to a smaller Q1 and Qdipole, while the lower mobility after O2 and NH3 PDA is due to a larger Qdipole. All these three PDA ambiences are beneficial to reduce the gate leakage current. Therefore, PDA in N2 is a balance approach for both the hole mobility improvement and gate leakage current reduction.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • The Role of Near-Interface Traps in Modulating the Barrier Height of SiC
           Schottky Diodes
    • Authors: Jordan R. Nicholls;Sima Dimitrijev;Philip Tanner;Jisheng Han;
      Pages: 1675 - 1680
      Abstract: The role of traps in the operation of Schottky barrier diodes is poorly understood. To explore this, SiC Schottky barrier diodes with a high density of near-interface traps were intentionally fabricated. By applying forward current stress, we demonstrate that the barrier height can be changed by changing the occupancy of the traps. The response time of these traps extends from seconds to hundreds of seconds. We also show that these traps can subsequently be emptied by thermal emission or by tunneling. The results are inconsistent with the existence of an interfacial oxide layer, which shows that the traps are distributed in both energy and lateral depth and, consequently, clarifies their role in creating the Schottky barrier.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Quantifying Temperature-Dependent Substrate Loss in GaN-on-Si RF
    • Authors: Hareesh Chandrasekar;Michael J. Uren;Michael A. Casbon;Hassan Hirshy;Abdalla Eblabla;Khaled Elgaid;James W. Pomeroy;Paul J. Tasker;Martin Kuball;
      Pages: 1681 - 1687
      Abstract: Intrinsic limits to temperature-dependent substrate loss for GaN-on-Si technology, due to the change in resistivity of the substrate with temperature, are evaluated using an experimentally validated device simulation framework. Effect of room temperature substrate resistivity on temperature-dependent coplanar waveguide (CPW) line loss at various operating frequency bands is then presented. CPW lines for GaN-on-high-resistivity Si are shown to have a pronounced temperature dependence for temperatures above 150 °C and have lower substrate losses for frequencies above the X-band. On the other hand, GaN-on-low-resistivity Si is shown to be more temperature insensitive and has lower substrate losses than even highly resistive Si for lower operating frequencies. The effect of various CPW geometries on substrate loss is also presented to generalize the discussion. These results are expected to act as a benchmark for temperature-dependent substrate loss in GaN-on-Si RF technology.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Field Plate Designs in All-GaN Cascode Heterojunction Field-Effect
    • Authors: Sheng Jiang;Kean Boon Lee;Zaffar H. Zaidi;Michael J. Uren;Martin Kuball;Peter A. Houston;
      Pages: 1688 - 1693
      Abstract: Different source field plate (FP) connections are compared for the all-GaN integrated cascode device to address the capacitance matching and turn-off controllability issues reported in the conventional GaN plus Si cascode. The experimental results suggest that the cascode device with an FP connected to the source terminal can significantly suppress the off-state internode voltage, leading to minimized capacitive energy loss and reduced overvoltage stress at the internode. This is attributed to the reduced ratio of the drain-source capacitance of the depletion mode cascode part to the total capacitance at the cascode internode. An additional FP on the E-mode cascode part is proposed to further suppress the off-state internode voltage and benefit the device. Cascode devices with the source FP connecting to the enhancement mode gate have an improved switching controllability via gate resistance during turn-off and hence enhanced dv/dt immunity in the drain loop.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Electrical Characteristic of AlGaN/GaN High-Electron-Mobility Transistors
           With Recess Gate Structure
    • Authors: Niraj Man Shrestha;Yiming Li;Tetsuya Suemitsu;Seiji Samukawa;
      Pages: 1694 - 1698
      Abstract: AlGaN/GaN high-electron-mobility transistors (HEMTs) with nonrecess and recess gates are simulated by solving a set of drift-diffusion equations for electrostatic potential and electron-hole concentrations with self-heating model. The approach is first calibrated for both HEMT devices with experimentally measured data, to provide the best accuracy of the simulation. Recess gate device suffers from high potential to the channel, increased parasitic resistances, and deep level traps in barrier due to surface roughness. In addition, selective thinning of the barrier and increase parasitic resistance results in 17% reduction on the carrier concentration. The carrier mobility degradation due to surface roughness and electron velocity lessen due to high electric field result shrinkage of current density with considerable shift of the threshold voltage toward positive value. Even though transconductance does not seems to be remarkably changed for 3-nm recess gate, its value increases on deeper recess. This paper reveals that surface roughness is crucial issue that has dominant role behind the low current density in the recess gate structure. The detail physical understanding of the recess technology will be helpful to minimize the performance deterioration of the explored devices.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Deep Sub-60 mV/decade Subthreshold Swing in AlGaN/GaN FinMISHFETs with
           M-Plane Sidewall Channel
    • Authors: Quan Dai;Dong-Hyeok Son;Young-Jun Yoon;Jeong-Gil Kim;Xiaoshi Jin;In-Man Kang;Dae-Hyun Kim;Yue Xu;Sorin Cristoloveanu;Jung-Hee Lee;
      Pages: 1699 - 1703
      Abstract: AlGaN/GaN FinMISHFETs with m-plane sidewall surface channel and various fin widths (Wfin) were fabricated and characterized. The investigated devices have much higher current drivability due to the uniform and smooth surface of m-plane than those with the a-plane sidewall surface channel. The AlGaN/GaN FinMISHFETs with Wfin smaller than 36 nm exhibit normally-off operation, high Ion/Ioff ratio of 108, and remarkable subthresholdswing (SS) smaller than 40 mV/decade in the wide current range of at least three orders. Combined with a positive threshold voltage, SS values smaller than 60 mV/decade in a wide current rage of at least three orders are among the world's best subthreshold characteristics. Furthermore, when Wfin is 31 nm, the off-state drain current is as low as 10-12 A. We show that this sharp switch is due to the simultaneous turn-on of the 2-D electron gas and the m-plane sidewall surface channel. The simulation results are carried out to show the gate-induced variation of the electron concentration within the fin structure, and the assumption of considering gate width as a function of gate bias is also developed to explain the reason for deep sub-60mV/decade in the demonstrated devices.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Energy-Localized Near-Interface Traps Active in the Strong-Accumulation
           Region of 4H-SiC MOS Capacitors
    • Authors: Peyush Pande;Sima Dimitrijev;Daniel Haasmann;Hamid Amini Moghadam;Philip Tanner;Jisheng Han;
      Pages: 1704 - 1709
      Abstract: Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and 1 μs by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using
           a Thin-SiO2/Al2O3 Gate-Stack
    • Authors: J. Urresti;F. Arith;S. Olsen;N. Wright;A. O’Neill;
      Pages: 1710 - 1716
      Abstract: High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm2/V· s, and a peak field effect mobility of 154 cm2/V s, in 2-μ m gate length MOSFETs. The gate-stackwas designed to minimize interface states and comprised a 0.7-nm thermally grown SiO2 on 4H-SiC, followed by Al2O3 and a metal gate contact. In this way, carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range of 6 x 1011-5 x 1010cm-2eV-1 is also obtained. Temperature-dependent electrical data reveal that the high mobility results from conduction being phononlimited, rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in the Si devices. Expressions for electric field-dependent contributions to mobility are presented. A steep subthreshold slope of 127 mV/decade indicates low electrical defect density. A temperature coefficient of -4.6 mV/K in threshold voltage is similar to that in the Si MOSFETs.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Enhanced Reconfigurable Physical Unclonable Function Based on Stochastic
           Nature of Multilevel Cell RRAM
    • Authors: Gyo Sub Lee;Gun-Hwan Kim;Kisung Kwak;Doo Seok Jeong;Hyunsu Ju;
      Pages: 1717 - 1721
      Abstract: The physical unclonable function (PUF) based on resistive random-access memory (RRAM) possesses a distinctive advantage that can offer higher security and lower cost than the traditional complementary metal-oxide-semiconductor-based cryptographic devices and other conventional PUFs. The intrinsic stochasticity of RRAM devices successfully provides attractive properties to implement PUF. In this paper, we present a novel multistate-based RRAM PUF to realize strong tolerance against attack. By applying multilevel states with bit shuffling to the RRAM PUF, the randomness and uniqueness were enhanced close to ideal values. In addition, the bit error rate was dramatically reduced using the temperature compensation mechanism. Moreover, our new method not only enables the generation of larger challenge-response pairs (CRPs) with less footprint but also can reconfigure CRPs.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Adaptive Quantization as a Device-Algorithm Co-Design Approach to Improve
           the Performance of In-Memory Unsupervised Learning With SNNs
    • Authors: Yuhan Shi;Zhisheng Huang;Sangheon Oh;Nathan Kaslan;Jungwoo Song;Duygu Kuzum;
      Pages: 1722 - 1728
      Abstract: Off-chip memory access is the primary bottleneck toward accelerating neural network operations and reducing energy consumption. In-memory training and computation using emerging nonvolatile memories (eNVMs) have been proposed to address this problem. However, a small number of conductance states limit in-memory online learning performance. Here, we introduce a device-algorithm co-design approach and its application to phase change memory (PCM) for improving learning accuracy. We present an adaptive quantization method, which compensates the accuracy loss due to limited conductance levels and enables high-accuracy unsupervised learning with low-precision eNVM devices. We develop a spiking neural network framework for NeuroSim platform to compare online learning performance of PCM arrays for analog and digital implementations and benchmark the tradeoffs in energy consumption, latency, and area.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process
    • Authors: Ren-Jay Kuo;Fu-Cheng Chang;Ya-Chin King;Chrong-Jung Lin;
      Pages: 1729 - 1733
      Abstract: A new antifuse one-time programmable (OTP) memory array by the 16-nm FinFET high-κ metal gate process is proposed and demonstrated. The OTP cells are programed by gate dielectric breakdown. The asymmetric I-V characteristics can be achieved by controlling the current compliance level during its programming operation. Based on the diode-like postbreakdown I-V characteristics, a high-density cross-point array without cell selectors is demonstrated, by the advanced FinFET CMOS technology.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell
    • Authors: Wei-Liang Lin;Wen-Jer Tsai;C. C. Cheng;S. H. Ku;Lenvis Liu;S. W. Hwang;Tao-Cheng Lu;Kuang-Chao Chen;Tseung-Yuen Tseng;Chih-Yuan Lu;
      Pages: 1734 - 1740
      Abstract: Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in “pseudo” charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Investigation of the Impact of External Stress on Memory Characteristics
           by Modifying the Backside of Substrate
    • Authors: Young-Taek Oh;Jae-Min Sim;Nguyen Van Toan;Hisashi Kino;Takahito Ono;Tetsu Tanaka;Yun-Heub Song;
      Pages: 1741 - 1746
      Abstract: The effects of the external stress on memory device characteristics are numerically discussed, and experimental observations are made, based on the wafer curvature method for extraction of stress. An analysis of the interface state is then performed. The external force applied to the device was controlled by depositing a metal film on the wafer backside; then, the residual stress induced on the substrate was extracted. We observed that the dangling bond generated by the residual stress increases the trap site and deteriorates the interface properties. A resulting degradation of cell characteristics occurred, including an increase in the leakage current and degradation of the memory window, featuring a reduction in the oxide/nitride/oxide trap density, which worsens as the magnitude of stress increases. From these results, we concluded that minimizing the stress is essential for retaining the cell characteristics. Especially, our results are expected to be of great help in determining the effect of external force on the memory characteristics during the back-end-of-line processing.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Study on High-Density Integration Resistive Random Access Memory Array
           From Multiphysics Perspective by Parallel Computing
    • Authors: Guodong Zhu;Wenchao Chen;Dawei Wang;Hao Xie;Zhenguo Zhao;Pingqi Gao;Jose Schutt-Aine;Wen-Yan Yin;
      Pages: 1747 - 1753
      Abstract: A finite-element method-based parallel computing simulator for multiphysics effects in resistive random access memory (RRAM) array, which is suitable for supercomputer platforms even with thousands of cores, is developed to simulate oxygen vacancy migration, current transport, and thermal conduction. Exponentially fit flux Galerkin method is introduced to improve algorithm convergence when solving the 3-D oxygen vacancy drift-diffusion equation. The accuracy of our algorithm is validated by comparison with commercial software. Scalability of our parallel algorithm is also investigated. The simulation results for the high-density integration RRAM array indicate that the heat generated during the writing process can result in high temperature, and lead to severe reliability problem. Even the RRAM cells without bias voltage applied can be transferred from low-resistance state to high-resistance state unintentionally, and lose their stored information. Increasing the feature size or equivalently decreasing the integration density lowers the power density, hence improves reliability performance. Large electrode thickness with Dirichlet boundary applied on their side surfaces can drain out heat faster and enhance reliability of RRAM array.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by
           Inserted-Oxide FinFET Technology
    • Authors: Yi-Ting Wu;Fei Ding;Daniel Connelly;Meng-Hsueh Chiang;Jone F. Chen;Tsu-Jae King Liu;
      Pages: 1754 - 1759
      Abstract: A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be selectively rendered nonconducting by dopant ion implantation followed by thermal annealing so that its threshold voltage is greater than the supply voltage (VDD). Furthermore, the position of the inserted-oxide layer can be adjusted to balance the tradeoff between the read stability and write-ability to achieve the lowest minimum cell operating voltage (Vmin). Using a compact transistor model calibrated to 3-D device simulations, doped iFinFET technology is projected to enable Vmin of a minimally sized 6T-SRAM cell to be substantially lower than VDD, eliminating the need for write-assist circuitry and lowering power consumption.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Enhanced Stability in Zr-Doped ZnO TFTs With Minor Influence on Mobility
           by Atomic Layer Deposition
    • Authors: Jun Yang;Yongpeng Zhang;Cunping Qin;Xingwei Ding;Jianhua Zhang;
      Pages: 1760 - 1765
      Abstract: We developed a novel method to fabricate Zr-doped ZnO (ZrZnO) thin films via low-temperature atomic layer deposition technique. ZrZnO films were deposited by diethylzinc (DEZ)/tetrakiszirconium (TDMAZr)/H2O cycles instead of the traditional DEZ/H2O/TDMAZr/H2O cycles and applied in thin-film transistors (TFTs). It is found that ZrZnO-TFTs with a Zn-Zr-O:ZnO atomic ratio of 1:49, i.e., ZrZnO (1:49) exhibit excellent properties, such as a minimum subthreshold swing value of 0.37 V/dec, a maximum ION/IOFF value of 2.4 × 107, a larger mobility of 12.38 cm2/V·s, and a smaller threshold voltage shift (ΔVth) of 0.61 V under temperature stress from 25 °C to 105 °C, which are superior compared with TFTs with ZnO channel doped by ZrO2 layer. The stability of ZnO TFTs was improved greatly by Zr-Zn-O doping. Moreover, the field-effect mobility of ZrZnO-TFTs was rarely influenced. Temperature-stress test was carried out to build up the correlation model in terms of the defect structures, subgap states, and stability. These results could provide a new access to understand the device instability of ZrZnO TFTs.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Submicrometer p-Type SnO Thin-Film Transistors Fabricated by Film Profile
           Engineering Method
    • Authors: Ming-Hung Wu;Horng-Chih Lin;Pei-Wen Li;
      Pages: 1766 - 1771
      Abstract: We reported the fabrication of submicrometer p-type tin monoxide (SnO) thin-film transistors (TFTs) with a channel length of 0.2 μm for back-end-of-line applications using a film profile engineering (FPE) approach. Material analyses indicate that the as-deposited SnO films are amorphous, while be transformed to polycrystalline after a thermal annealing in oxygen ambient. Fabricated p-type SnO FPE-TFTs of a channel length of 0.2 μm were manifested with ON/OFF current ratio higher than 105 and subthreshold slope of 320 mV/decade, superior to the data of submicrometer SnO devices ever reported. The extracted field-effect mobility is about 0.25 cm2/V·s. After ruling out the influence of source/drain series resistance, the intrinsic field-effect mobility is found to be about 1 cm2/V·s.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • $I$+ –+$V$+ +Curve+of+a-InGaZnO4+Thin-Film+Transistor&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Yu-Ching&;Ting-Chang+Chang;Shin-Ping+Huang;Yu-Lin+Tsai;Mao-Chou+Tai;Hong-Yi+Tu;Hong-Chih+Chen;Jen-Wei+Huang;Shengdong+Zhang;">Effects of Ultraviolet Light on the Dual-Sweep $I$ – $V$ Curve of
           a-InGaZnO4 Thin-Film Transistor
    • Authors: Yu-Ching Tsao;Ting-Chang Chang;Shin-Ping Huang;Yu-Lin Tsai;Mao-Chou Tai;Hong-Yi Tu;Hong-Chih Chen;Jen-Wei Huang;Shengdong Zhang;
      Pages: 1772 - 1777
      Abstract: The instability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I-V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I-V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal-insulator-semiconductor-metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Submicrometer Top-Gate Self-Aligned a-IGZO TFTs by Substrate Conformal
           Imprint Lithography
    • Authors: Mamidala Saketh Ram;Laura De Kort;Joris De Riet;Roy Verbeek;Thijs Bel;Gerwin Gelinck;Auke Jisk Kronemeijer;
      Pages: 1778 - 1782
      Abstract: Thin-film transistors (TFTs) are the fundamental building blocks of today's display industry. To achieve higher drive currents and device density, it is essential to scale down the channel lengths of TFTs. To be able to fabricate short-channel TFTs in large volumes is also equally important in order to realize lower fabrication costs and higher throughput. In this paper, we demonstrate the application of substrate conformal imprint lithography (SCIL) to pattern top-gate (TG) self-aligned (SA) amorphous indium gallium zinc oxide TFTs down to channel length LG = 450 nm with good device scaling properties resulting in average field-effect mobility (μFE) = ~10 cm2·V-1·s-1, VON = ~ 0.5 V, and subthreshold swing (SS) = ~0.3 V/decade. The device performance as a function of channel length outlines the importance of dopant diffusion control for realizing submicrometer SA TFTs. The results demonstrate the compatibility of SCIL-based large-area patterning for the realization of submicrometer TG SA TFTs with a potential for high throughput.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Comparative Study on Performance of IGZO Transistors With Sputtered and
           Atomic Layer Deposited Channel Layer
    • Authors: Min Hoe Cho;Hyunju Seol;Aeran Song;Seonjun Choi;Yunheub Song;Pil Sang Yun;Kwun-Bum Chung;Jong Uk Bae;Kwon-Shik Park;Jae Kyeong Jeong;
      Pages: 1783 - 1788
      Abstract: The structural, chemical, and electrical properties of amorphous indium gallium zinc oxide (a-IGZO) films by magnetron sputtering and atomic layer deposition (ALD) were investigated where both a-IGZO films had a comparable cation composition. The ALD-derived a-IGZO film exhibited the higher atomic packing density, the effective suppression of trap-like oxygen vacancy defect (VO), and the enhancement in the hybridization of the sp orbital of In, Ga, and Zn cations compared to those of the sputtered a-IGZO film. Hence, a significant improvement in terms of the field-effect mobility was observed for the thin-film transistors with an In0.50Ga0.34Zn0.16O channel by ALD (36.6 cm2/V·s) compared to that of the sputtered In0.48Ga0.38Zn0.14O transistor (20.1 cm2/V·s); the ION/OFF ratios for both were ~107. Simultaneously, the gate bias stress stability and photobias stress stability were also improved for the IGZO transistors with an ALD-derived channel, which can be explained by its reduced trap-like VO density.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Highly Reliable a-Si:H TFT Gate Driver With Precharging Structure for
           In-Cell Touch AMLCD Applications
    • Authors: Chih-Lung Lin;Po-Cheng Lai;Po-Ting Lee;Bo-Shu Chen;Jui-Hung Chang;Yu-Sheng Lin;
      Pages: 1789 - 1796
      Abstract: This paper presents a novel bidirectional gate driver circuit based on hydrogenated amorphous silicon thin-film transistors (TFTs), especially for use in active-matrix liquid-crystal displays with in-cell touch technology. The proposed circuit exploits the time-division driving method to implement the in-cell touch panels with a high report rate and prevent the distortion of touch signals. The proposed structure employs a highly reliable precharging circuit to ameliorate the degradation of the driving TFT during the long-term touch-sensing stages. The output TFTs in the precharging structure are activated only once at the end of the touch-sensing stage in a frame, effectively extending the lifetime of the circuit. The experimental and simulated results illustrate that the proposed gate driver circuit generates uniform output waveforms regardless of whether the circuit operates in forward and backward transmission or stops in any row. To verify the high reliability of the proposed gate driver circuit, long-term stress tests at 85 °C are conducted. After the proposed circuit is operated for 720 h, the falling time of the output waveforms after the touch-sensing stage slightly varies by only 0.51 μs, confirming that the output TFT in the proposed precharging structure with a low duty ratio of 0.15% can achieve the high reliability of the proposed circuit. Therefore, the proposed gate driver circuit is highly feasible for use in high-reportrate in-cell touch panels.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Small-Signal Compact Circuit Modeling of Group IV Material-Based
           Heterojunction Phototransistors for Optoelectronic Receivers
    • Authors: Harshvardhan Kumar;Rikmantra Basu;Jyoti Gupta;
      Pages: 1797 - 1803
      Abstract: This paper presents an optoelectronics-based compact equivalent circuit model of an n-Ge/p-Ge1-xSnx/n-Ge1-xSnx heterojunction phototransistor (HPT). This paper includes the static electrical and optical characteristics of the device, Gummel characteristics, effect of temperature, and overall noise analysis of HPT based on various parametric variations. We then investigate the effect of parasitic capacitance on the noise performance of the HPT. The estimated results show that the signal-to-noise ratio (SNR) is strongly dependent on not only the operating frequency but also the operating temperature and applied base-bias voltage. Estimated performance shows that SNR of HPT>90 dB up to 100 GHz and>80 dB up to 50 °C can be achieved, which ensured the operation of the device as high-speed and low-noise detector.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Self-Powered Broadband (UV-NIR) Photodetector Based on 3C-SiC/Si
    • Authors: Abu Riduan Md Foisal;Toan Dinh;Viet Thanh Nguyen;Philip Tanner;Hoang-Phuong Phan;Tuan-Khoa Nguyen;Ben Haylock;Erik W. Streed;Mirko Lobino;Dzung Viet Dao;
      Pages: 1804 - 1809
      Abstract: Self-powered photodetectors (PDs) are highly desirable for many applications, ranging from smart cities to optical communications. Herein, we report on a selfpowered broadband [UV to near-infrared (NIR)] PD based on a single-crystalline SiC (100)/Si (100) heterojunction. In self-powered photovoltaic detection mode, the detector exhibits a high responsivity (2500 V/W at 8.0 x 10-6 W/cm2, 521 nm) and specific detectivity (~1013 Jones at 8.0 x 10-6 W/cm2, 521 nm) under UV, visible, and NIR spectral illuminations thanks to the superior rectification property of the heterojunction which results in significantly reducing the dark current. The device also shows high illumination ON/OFF switching ratios, as high as 2.2x107, with an excellent stability and repeatability. A detailed insight about electron- hole pairs generation, separation, and Fermi-energy level shifting at different illumination conditions has been elucidated via energy band diagrams.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • A New Expression for the Gain-Noise Relation of Single-Carrier Avalanche
           Photodiodes With Arbitrary Staircase Multiplication Regions
    • Authors: A. Pilotto;P. Palestri;L. Selmi;M. Antonelli;F. Arfelli;G. Biasiol;G. Cautero;F. Driussi;R. H. Menk;C. Nichetti;T. Steinhartova;
      Pages: 1810 - 1814
      Abstract: We propose a simple expression to relate the total excess noise factor of a single-carrier multiplication staircase avalanche photodiode (APD) to the excess noise factor and gain given by the individual conduction band discontinuities. The formula is valid when electron impact ionization dominates hole impact ionization; hence, it is especially suited for staircase APDs with In-rich multiplication regions, as opposed, for example, to GaAs/AlGaAs systems where hole ionization plays an important role. The formula has been verified by accurate means of numerical simulations based on a newly developed nonlocal history dependent impact ionization model.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • High-Performance Organic Phototransistors With Vertical Structure Design
    • Authors: Guocheng Zhang;Jianfeng Zhong;Qizhen Chen;Yujie Yan;Huipeng Chen;Tailiang Guo;
      Pages: 1815 - 1818
      Abstract: In this paper, a novel vertical phototransistor was reported and compared with planar phototransistors for the first time. As compared with the planar phototransistors, the vertical ones exhibited much better photoelectric performance, which is attributed to an ultrashort photo-generated holes transfer distance and a stronger excitons dissociating electrical field due to their ultrashort channel length (tens of nanometers). Moreover, in order to examine the transport and trapping of different carrier charges separately, the impact of [6,6]-phenyl C61-butyric acid methyl ester (PCBM) dopant on the performance of planar and vertical phototransistors was investigated. The vertical devices exhibited an ultrahigh responsivity (~6600 A/W) as well as an excellent detectivity (~7×1015 Jones) and a fast photoresponse (rise time of 0.28 s), whereas slight changes were observed in the planar ones with doping of PCBM. The high performance of the blend vertical phototransistors is due to the trapping of the photo-generated electrons with PCBM and the effective transport of holes due to the ultrashort channel length. This paper provided a promising pathway for low-cost, high-performance phototransistors.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Computational Modeling of Polycrystalline Silicon on Oxide Passivating
           Contact for Silicon Solar Cells
    • Authors: Rehan Younas;Hassan Imran;Syed Ijlal Hassan Shah;Tarek M. Abdolkader;Nauman Zafar Butt;
      Pages: 1819 - 1826
      Abstract: Polycrystalline silicon on oxide (POLO) junction passivating contacts have recently been demonstrated as carrier selective contacts for high-efficiency silicon solar cells. The carrier transport through these contacts has been attributed to two competing mechanisms: 1) carrier tunneling through ultrathin oxide and 2) transport through weak spots (pinholes) - the nanoscale regions where oxide thickness has been completely or partially compromised during the processing. In this paper, we use two dimensional device simulations to compare the relative effects of these mechanisms on solar cell characteristics with ntype POLO contact. We show that variation in pinhole areal density (Dph) or the tunnel oxide thickness (tox) both result in qualitatively similar trends in the cell characteristics under dark and light. For a given tox, an exponential variation in Dph results in trends that are similar to those for a linear variation in tox. The effect of pinholes on contact resistance (ρc) and saturation current density (Jo) is most significant for relatively thicker oxides (≥ 2 nm). For tox ≤ 1 nm, ρc and Jo become essentially insensitive to pinholes for Dph
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Temperature Dependence of the Turn-On Delay Time of High-Power
    • Authors: O. S. Soboleva;A. A. Podoskin;V. S. Golovin;P. S. Gavrina;V. V. Zolotarev;N. A. Pikhtin;S. O. Slipchenko;T. A. Bagaev;M. A. Ladugin;A. A. Marmalyuk;V. A. Simakov;
      Pages: 1827 - 1830
      Abstract: The temperature dependence of the turn-on delay of a high-power laser-thyristor based on an AlGaAs/GaAs heterostructure has been studied. It was shown that the main factor responsible for the rise in the turn-on delay with increasing temperature is that the generation rate of excess carriers in the p-type base decreases in this case. The temperature dependence of the generation rate of excess carriers in the p-base of the phototransistor part of the structure is due to the change in the useful part of the spontaneous emission and in the impact-ionization rate in the space-charge region of the collector p-n junction. It was found that at low control currents, the key contribution comes from the impact ionization, which results in that a noticeable rise in the delay time is observed with increasing temperature. At high control currents, an important contribution is made by the change in the useful fraction of the absorbed spontaneous emission, which results in that there is hardly any temperature dependence of the delay time.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • An Ultralow Turn-Off Loss SOI-LIGBT With a High-Voltage p-i-n Diode
           Integrated on Field Oxide
    • Authors: Jiayu Wu;Moufu Kong;Bo Yi;Xing Bi Chen;
      Pages: 1831 - 1836
      Abstract: A novel ultralow turn-off loss silicon-on-insulator-lateral insulated-gate bipolar transistor (LIGBT) is proposed and investigated by numerical simulations. The proposed LIGBT features a high-voltage p-i-n diode integrated on the field oxide that is located upon the surface of the drift region. The p-i-n diode serves as a high-voltage level shifter, and the gate signal of the LIGBT can be transmitted to the anode side of the LIGBT to control a low-voltage circuit which is used to short the p-anode/n-buffer junction when the device is turning off. Thus, the injection of the holes from the p-anode region into the n-drift region is prevented, and the turn-off speed of the proposed LIGBT is significantly improved in comparison with the conventional one. The numerical simulation results reveal that the turn-off loss of the proposed 352-V LIGBT is 43.1% of the conventional LIGBT at VON = 1.38 V.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • The Test of a High-Power, Semi-Insulating, Linear-Mode, Vertical 6H-SiC
    • Authors: Qilin Wu;Tao Xun;Yuxin Zhao;Hanwu Yang;Wei Huang;
      Pages: 1837 - 1842
      Abstract: A high-power photoconductive semiconductor switch (PCSS) working in linear mode can be used for RF generation by modulating the illuminating light. Such a PCSS constructed of a semi-insulating 6H silicon carbide (6H-SiC) substrate and its characterization under a high electric field is presented. The PCSS is of a vertical structure, with one hollow/transparent electrode to let through the laser light and the other highly reflective to increase light absorption. First, to optimize the high-voltage withstanding, the factors affecting the field enhancement, such as substrate thickness, electrode profiles, and encapsulating materials, are discussed. Then, the PCSS is assembled and tested, and the 0.8-mm-thick 6H-SiC PCSS is able to work with electric fields up to 225 kV/cm and the power capacity up to 10.6 MW without failure when triggered by a Nd:YAG laser (532-nm, 17-ns full wavelength at half maximum). By varying the optical energy from 3 to 31.9 mJ, the minimum conducting resistance and the peak photocurrent of the PCSS are obtained. The PCSS fails with further increasing voltage, and the cause of the failure was identified to be a bulk breakdown. The result shows that the PCSS can work linearly and it is possible to be used in high-power compact RF generation.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Selective Electroless Copper Deposition by Using Photolithographic
           Polymer/Ag Nanocomposite
    • Authors: Assel Ryspayeva;Thomas D. A. Jones;Mohammadreza Nekouie Esfahani;Matthew P. Shuttleworth;Russell A. Harris;Robert W. Kay;Marc P. Y. Desmulliez;Jose Marques-Hueso;
      Pages: 1843 - 1848
      Abstract: This paper presents a novel, direct, selective, vacuum-free, and low-cost method of electroless copper deposition, allowing additive patterning of nonconductive surfaces. Ag nanoparticles (NPs) synthesized inside a photosensitive polymer are acting as seeds for electroless copper deposition. The resulting copper film surface morphology was studied with scanning electron microscopy. Copper films were shown to display a rough grain like structure, covering substrate uniformly with good metal-substrate adhesion. Copper thickness was studied as a function of the plating time, temperature, and Ag NPs seed concentration. A maximal copper thickness of 0.44 ± 0.05 μm was achieved when plated at 30 °C with 0.4 M Ag(I). The minimum feature resolution of copper patterns, grown with 0.025- and 0.1-M silver salt, is attained down to 10 μm. The maximum electrical conductivity of the copper film prepared with 0.025-, 0.1-, and 0.4-M Ag(I) approaches (0.8 ± 0.1) × 107 S/m, (1.1 ± 0.1) ×107 S/m and (1.6 ± 0.4)×107 S/m, respectively. Electroless copper interconnections and LED circuit on glass substrate were fabricated as a proof of concept demonstrators.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Analysis of Leakage Mechanisms in AlN Nucleation Layers on p-Si and p-SOI
    • Authors: Weihang Zhang;Eddy Simoen;Ming Zhao;Jincheng Zhang;
      Pages: 1849 - 1855
      Abstract: In this paper, the carrier transport mechanisms in AlN nucleation layers grown by MOCVD on p-Si and p-silicon-on-insulator (SOI) substrates were investigated by using electrical characterizations at various electric fields and temperatures on Ni-Au/AlN/Si metal-insulator-semiconductor capacitors. For the case of the AlN on Si substrate, different contact schemes, i.e., top-bottom versus top-top, have been compared. It was found by capacitance-voltage measurements that an inversion channel related to the Shockley-Read-Hall (SRH) minority carrier generation in the silicon bulk and SOI substrates was formed. It showed that the AlN on p-SOI platform exhibited the same leakage mechanisms as for the AlN on the Si substrate. The contact scheme mainly affects the low forward and reverse bias characteristics, by adding a surface leakage contribution. At increasing the forward (positive) gate bias, the carrier transport process becomes in turn ohmic, variable-range hopping, SRH generation, and Fowler-Nordheim (FN) direct tunneling. Moreover, at the reverse bias, the carrier transportation is in turn dominated by the Schottky emission, Poole-Frenkel (PF) conduction, and FN direct tunneling with increasing bias.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • InAs FinFETs Performance Enhancement by Superacid Surface Treatment
    • Authors: Yuping Zeng;Sourabh Khandelwal;Kazy F. Shariar;Zijian Wang;Guangyang Lin;Qi Cheng;Peng Cui;Robert Opila;Ganesh Balakrishnan;Sadhvikas Addamane;Peyman Taheri;Daisuke Kiriya;Mark Hettick;Ali Javey;
      Pages: 1856 - 1861
      Abstract: In this paper, a post superacid (SA) treatment was proposed to enhance the performance of InAs FinFETs on SiO2/Si substrates. Typically, the subthreshold swing (SS) has reduced from 217 to 170 mV/decade and the transconductance (gm) has increased from 6.44 to 26.5 μS/μm after SA treatment. It was found that the interfacial In2O3 at the InAs/ZrO2 interface was effectively reduced after SA treatment due to the strong protonating nature of the SA solution. As a result, the interface trap density was reduced leading to a pronounced reduction of sheet resistance after SA treatment. The modeling of transfer characteristics indicates that the carrier mobility is enhanced by 5.8~7.1 folds after SA treatment due to interfacial traps reduction. The results suggest that SA treatment can be potentially extended to other III-V MOSFETs to enhance the device performances.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Effects of ZrO2/Al2O3 Gate-Stack on the Performance of Planar-Type InGaAs
    • Authors: Dae-Hwan Ahn;Sang-Hee Yoon;Kimihiko Kato;Taiichirou Fukui;Mitsuru Takenaka;Shinichi Takagi;
      Pages: 1862 - 1867
      Abstract: We investigate the impact of gate-stack engineering using W/ZrO2/Al2O3 on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO2 with the dielectric constant of around 40 on In0.53Ga0.47As. On the other hand, the reduction of Dit by insertion of ALD 1-5 cycle Al2O3 interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO2/Al2O3 IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S.Smin) of 55 mV/dec and ION of 0.88 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, and IOFF = 10 pA/μm). Furthermore, the ZrO2/Al2O3 IL gatestack is applied to the optimized In0.75Ga0.25As quantum well (QW) channel TFETs. The low S.Smin of 50 mV/dec and high ION of 1.2 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, IOFF = 10 pA/μm, and CET = 1.1 nm) are demonstrated by combing the present ZrO2-based gate-stack with the optimum In0.75Ga0.25As QW channel structure.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Metal Source-/Drain-Induced Performance Boosting of Sub-7-nm Node
           Nanosheet FETs
    • Authors: Jun-Sik Yoon;Jinsu Jeong;Seunghwan Lee;Rock-Hyun Baek;
      Pages: 1868 - 1873
      Abstract: Sub-7-nm node nanosheet field-effect transistors adopting metal source/drain (S/D) structure were analyzed in depth using fully calibrated TCAD. Metal S/D structure was formed by anisotropic etching of low-k and S/D epi regions followed by metal-line (M0) deposition without additional mask under conventional CMOS process. Larger S/D metal depth increases the contact area between S/D epi and M0, thus increasing current drivability greatly without decreasing contact resistivity. A slight ac performance loss was due to the increase in intrinsic capacitance by the improved drivability. Tensile stress of M0 induces compressive stresses vertical to the channel and tensile stresses along the channel, which reduces and improves dc performances further for p-and n-type devices, respectively. Although the stress in the channel direction decreases by the recessed S/D epi, significant reduction of contact resistance compensates the reduced stress effects and improves RC delay consequently. Greatly recessed S/D epi increases the performance variations due to the channel stress variations as the open critical dimension (CD) varies. But when the open CD is tightly controlled by the latest technology such as extreme ultraviolet radiation, the metal S/D structure is competitive to achieve superior dc/ac performance under device scaling in sub-7-nm node and below.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Carrier Lifetime Measurement in Ultrathin FD-SOI Using Virtual Diodes
    • Authors: Kyung Hwa Lee;Hyung-Jin Park;Maryline Bawedin;Sorin Cristoloveanu;
      Pages: 1874 - 1880
      Abstract: In ultrathin fully depleted SOI PIN structures with underlapped gate, the front and back gates can be biased such as to emulate electrostatic diodes. The gate-induced electrons and holes result in a virtual P-N junction in the center of an undoped body. The current-voltage I-V curves are essentially diode-like but reconfigurable via gate voltage tuning. The virtual P-N and P-I-N diodes are used, for the first time, to evaluate the carrier lifetime in ultrathin SOI layers. This paper presents novel experiments and simulations. The transition between recombination and diffusion current in I-V characteristics enables quick lifetime extraction. A more evolved and accurate technique consists in monitoring the reverse recovery current in virtual diodes. This method reveals a very short carrier lifetime in 7-nm-thick SOI layers where surface recombination prevails. This result is confirmed by adapting a P-I-N-diode technique to sub-10 nm films.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Electrical Switching and Optical Bandgap Studies on Quaternary Ag-Doped
           Ge–Te–In Thin Films
    • Authors: Diptoshi Roy;G. Sreevidya Varma;S. Asokan;Chandasree Das;
      Pages: 1881 - 1886
      Abstract: Amorphous Ge15Te80_xIn5Agx (6≤ x ≤24) thin films prepared in sandwich geometry exhibit memory switching behavior unlike the bulk sample that has shown both threshold switching for less current (1-2 mA) and memory switching for current greater than 2 mA. As anticipated, the threshold voltage of Ge15Te80_xIn5Agx(6≤ x ≤ 24) thin films is found to be lower as contrast to those of bulk counterparts. The compositional dependence of amorphous system shows an extensive plateau in the range of 6 x 12 which literally stands for the intermediate phase after which there is a drastic increase in the threshold field. Shifted rigidity percolation threshold has also been confirmed from the compositional dependence of threshold field of amorphous Ge15Te80_xIn5Agx thin films. In addition, the optical bandgap of a-Ge15Te80_xIn5Agx thin-film sample has been reckoned considering absorption spectra, and the compositional dependence has been described based on average bond energy of the system.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Caution: Abnormal Variability Due to Terrestrial Cosmic Rays in
           Scaled-Down FinFETs
    • Authors: Jungsik Kim;Jeong-Soo Lee;Jin-Woo Han;M. Meyyappan;
      Pages: 1887 - 1891
      Abstract: The variability due to the displacement damage defect is investigated for various bulk FinFET technology nodes. A random displacement damage from point to clustered defects is introduced by natural terrestrial radiation in arbitrary locations in the silicon channel region. Energy level, position, and size of the defect clusters are considered as variables, and the impact on device performance is investigated for various technology nodes with the aid of the TCAD simulation. It is found that even a displacement defect can cause significant device degradation as the technology node scales down beyond the 10-nm node. Particularly, the abnormal variability may become an issue at sub-6-nm node due to a limited volume of the fin width and the comparable size of the cluster defect.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • ${I}$+ –+${V}$+ ,++${C}$+ +${V}$+ ,+and++${G}$+ +${V}$+ +Measurements&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Andrea&;Ben+Kaczer;Milan+Pešić;Attilio+Belmonte;Mihaela+Popovici;Laura+Nyns;Dimitri+Linten;Valeri+V.+Afanas’ev;Ilya+Shlyakhov;Younggon+Lee;Hokyung+Park;Luca+Larcher;">A Sensitivity Map-Based Approach to Profile Defects in MIM Capacitors From
           ${I}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ Measurements
    • Authors: Andrea Padovani;Ben Kaczer;Milan Pešić;Attilio Belmonte;Mihaela Popovici;Laura Nyns;Dimitri Linten;Valeri V. Afanas’ev;Ilya Shlyakhov;Younggon Lee;Hokyung Park;Luca Larcher;
      Pages: 1892 - 1898
      Abstract: We present a defect spectroscopy technique to profile the energy and spatial distribution of defects within a material stack from leakage current (J-V), capacitance (C-V), and conductance (G-V) measurements. The technique relies on the concept of sensitivity maps (SMs) that identify the bandgap regions, where defects affect those electrical characteristics. The information provided by SMs are used to reproduce J-V, C-V, and G-V data measured at different temperatures and frequencies by means of physics-based simulations relying on an accurate description of carrier-defect interactions. The proposed defect spectroscopy technique is applied to ZrO2-based metal-insulator-metal structures of different compositions for dynamic random-access memory capacitor applications. The origin of the observed voltage, temperature, and frequency dependencies of the I-V, C-V, and G-V data is understood, and the atomic structure of the relevant stack defects is identified.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • High-Temperature Impact-Ionization Model for 4H-SiC
    • Authors: Selamnesh Nida;Ulrike Grossner;
      Pages: 1899 - 1904
      Abstract: Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Dielectrically Modulated Source-Engineered Charge-Plasma-Based
           Schottky-FET as a Label-Free Biosensor
    • Authors: Syed Adeebul Hafiz; Iltesha;M. Ehteshamuddin;Sajad A. Loan;
      Pages: 1905 - 1910
      Abstract: In this paper, we propose and simulate a charge-plasma (CP)-based dielectrically modulated (DM) source-engineered Schottky barrier field-effect transistor (SE-SB-FET) as a device for biomolecule sensing. The proposed device employs metal silicide (ErSi1.7) as source/drain regions and Hafnium (workfunction = 3.8 eV) as dual metallic source extensions. The oxide below the source extensions are etched out to create two horizontal L-shaped nanogap cavities for biomolecule detection. The presence of biomolecules is characterized by the change in dielectric constants and the associated charge densities, which, in turn, modulates the Schottky barrier (SB) width at the source-channel (metal/Si) junction, owing to the formation of an electron-CP in an undoped-Si film. A comparative analysis of the SE-SB-FET and the conventional DM-FET in terms of sensitivity has been performed as a function of dielectric constant (K) and the associated charge density (p), along with the thickness (TC) and the length (LC) of the cavity. Furthermore, calibrated simulations reveal that the relative change in ION (sensing parameter herein calculated at VGB = VDS = 1 V) in SE-SB-FET is much better (maximum of 3× for neutral; 2.9× for charged biomolecules at p = -1 × 1011 cm-2). We further observe a significant improvement in sensitivity at low temperature (25× at K = 5; p = 0 at 100 K). Thus, SE-SB-FET biosensor provides better sensing capability for biomolecule detection when compared to the conventional DM-FET biosensor.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Flexible Wearable Humidity Sensor Based on Nanodiamond With Fast Response
    • Authors: Xinglin Yu;Xiangdong Chen;Xiang Yu;Xinpeng Chen;Xing Ding;Xuan Zhao;
      Pages: 1911 - 1916
      Abstract: In this paper, a novel and flexible humidity sensor based on nanodiamond (ND) sensing film was fabricated on a polyimide substrate. A series of flexibility-related humidity testing experiments is also performed. The experimental results demonstrated that the prepared sensor exhibited a subsecond response/recovery time and showed good repeatability under different bending states. It was found that different bending radii had an influence on the humidity sensor's response/recovery time. The response/recovery time is reduced with the increase in bending radius, which is suspected to be related to the interspace change of nanodiamond sensing membrane under different bending radii. Furthermore, due to good flexibility and rapid response, this humidity sensor can be directly attached on finger or wrist for human breath detection, which can provide a more convenient monitoring means for human health activities such as sports and fitness.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • A High-Performance Tunable LED-Compatible Current Regulator Using an
           Integrated Voltage Nanosensor
    • Authors: Zeheng Wang;Shengji Wang;Zhenwei Zhang;Chunpeng Wang;Di Yang;Xinghuan Chen;Zirui Wang;Jun Cao;Yuanzhe Yao;
      Pages: 1917 - 1923
      Abstract: A class of novel tunable light-emission-diode (LED)-compatible current regulator, including the reverse blocking and the reverse conducting device, is proposed by integrating the p-GaN cap with a voltage nanosensor on the AlGaN/GaN platform. Verified by the experimentally calibrated simulation, it is the feedback of the voltage sensor that stabilizes the depletion region of the reverse biased p-GaN/AlGaN/2-DEG junction, which contributes to clamping the voltage effectively. Compared with the proposed regulator, the devices only with the p-GaN cap or the sensor cannot perform the current regulation. Moreover, investigated by varying the p-type concentration of the p-GaN, the length of the sensor as well as the temperature, the proposed device featuring a ripple wave below 4 mA/mm and a temperature coefficient of 4.5 mA · mm-1K-1 exhibits its potential in LED industry and other related applications.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Improving the Properties of L-Ascorbic Acid Biosensor Based on GO/IGZO/Al
           Using Magnetic Beads
    • Authors: Jung-Chuan Chou;You-Xiang Wu;Po-Yu Kuo;Chih-Hsien Lai;Yu-Hsun Nien;Si-Hong Lin;Siao-Jie Yan;Cian-Yi Wu;Yi-Hung Liao;
      Pages: 1924 - 1929
      Abstract: An L-ascorbic acid (L-AA) biosensor based on an indium-gallium-zinc oxide (IGZO)/aluminum (Al) membrane modified by graphene oxide (GO) and magnetic beads (MBs) was produced and trusted to investigate its potential biosensor applications. An atomic force microscope, scanning electron microscope (SEM), and electrochemical impedance spectroscopy (EIS) were used to analyze electron transfer resistance (Ret), surface roughness, and surface morphology. The experimental results show that the L-AA biosensor possessed the average sensitivity of 78.9 mV/decade with a linearity of 0.997. The experimental results from the EIS confirm that Ret can be improved by the addition of GO and MBs. This paper opens a new window for the detection of L-AA based on MBs-ascorbate oxidase/GO/IGZO/Al sensing membranes.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Fine-Tuning Intermolecular and Intramolecular Interactions to Build the
           Films of Tris(Phthalocyaninato) Rare Earth Complexes and Their Comparative
           Performances in Ambipolar Gas Sensing
    • Authors: Shuai Zhao;Xia Kong;Xiangyang Wang;Xiyou Li;Guangwu Yang;Yanli Chen;
      Pages: 1930 - 1936
      Abstract: High-performance ambipolar chemical sensors toward electron-detonating NH3 and electronaccepting NO2 are obtained based on the solution-based films of two ambipolar (p-fluoro)phenoxy substituted tris(phthalocyaninato) rare earth semiconductors with different metal ions, named Gd2[Pc(OPhF)8]3 (1) and Tb2[Pc(OPhF)8]3(2). Measurements over the films fabricated from 1 and 2 by a simple quasi-Langmuir-Shäfer (QLS) method reveal their ambipolar semiconductor nature, with a p-type response in NH3 sensing and n-type response in NO2 sensing, associated with not only suitable highest occupied molecular orbital and lowest unoccupied molecular orbital energy levels but also the different electronic induction effects of the analytes. Interestingly, the devices from the QLS film of 2 with a weaker intermolecular π-π stacking in J-type (edge-to-edge) packing mode display much better sensing properties to both NH3 and NO2, compared to those from QLS film of 1 with a stronger intermolecular π-π stacking in the H-type (face-to-face) packing mode. This is mainly because of the larger specific surface area from the J-aggregate with the more uniform-sized nanoparticles for the QLS film of 2. In particular, the highly sensitive, stable, and reproducible responses to 1-20-ppm NH3 with a limit of detection of 0.15 ppm only in 1 min are obtained from the QLS film of 2 for the first time. This paper unravels, first, the effect of central metal ions of sandwich triple-deckers on molecular stacking mode, film structure, and gas sensing performances, which would be helpful for designing and preparing high-performance ambipolar gas sensor devices by combining the molecular design and the device fabrication technique.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Study of GaN Dual-Drain Magnetic Sensor Performance at Elevated
    • Authors: B. R. Thomas;S. Faramehr;D. C. Moody;J. E. Evans;M. P. Elwin;P. Igić;
      Pages: 1937 - 1941
      Abstract: For the first time, we report on the superior performance of the dual-drain gallium nitride (GaN) magnetic field-effect transistor (MagFET) at elevated temperatures. The IV characteristics of the devices reported here were collected under dc conditions and tested at elevated temperatures, 300, 323, 373, and 448 K using a custom-made heating stage, with a thermal feedback loop to accurately control the temperature. Light exposure experiments were conducted during raised temperature levels using an LED light source of wavelength 470 nm. The relative sensitivity of the GaN dual-drain MagFET was calculated and demonstrated a degradation from 9.78%T-1 at 300 K to 8.36%T-1 at 323 K, 6.10%T-1 at 373 K, and 3.79%T-1 at 448 K. This is equal to a small sensitivity decrease of 0.04%T-1/K. It is proposed that the observed reduction in sensitivity reported herein is due to increased phonon scattering in the 2-D electron gas channel. Despite this reduced sensitivity at elevated temperatures, the lowest sensitivity measured at 448 K surpasses those reported for silicon competitors.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Platinum Nanoparticles Decorated Graphene Oxide Based Resistive Device for
           Enhanced Formaldehyde Sensing: First-Principle Study and its Experimental
    • Authors: Bibhas Manna;Indrajit Chakrabarti;Prasanta Kumar Guha;
      Pages: 1942 - 1949
      Abstract: This paper reports the formaldehyde (HCHO) sensing mechanism of platinum nanoparticles (Pt) supported reduced graphene oxide (RGO)-based resistive sensor devices through the experimental investigation and subsequent density functional theory (DFT) computation. Sensing measurements conducted at room temperature revealed that the Pt facilitated enhanced charge transfer between HCHO molecule and RGO-Pt nanomaterial improves the response of the device by almost 4.5 times against 400 ppm of HCHO concentration as compared to bare RGO counterpart. The device has been found to recover within 350 s for an optimized impulsive heating treatment at 50 °C for 55 s. Moreover, the selectivity test performed for some common indoor volatile organic compounds signifies the RGO-Pt nanohybrid to be more specific toward the HCHO molecule. DFT-based first-principle calculations have also been carried out in terms of stable adsorption geometry, adsorption energy, net electron transfer, charge density difference, and changes in density of states of the HCHO adsorbed complexes. The simulation results suggest that the chemisorption of HCHO through molecular dissociation and strong covalent bond formation on RGO-Pt surface have led to significant changes in its resistivity in contrast to RGO, where HCHO molecule possesses pure physisorption. The simulation results agree quite well with the experimental observations.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Investigation of a Low-Impedance Reltron as a Gigawatt HPM Source
    • Authors: Manpuran Mahto;Pradip Kumar Jain;
      Pages: 1950 - 1953
      Abstract: In this paper, a novel version of reltron has been proposed for the gigawatt power level of microwave generation. It uses a modified modulation cavity structure, in which the electromagnetic field coupling has been made through two coupling cavities instead of one coupling cavity as in the conventional case. This low-impedance device allows higher beam current at lower applied dc pulse potential, producing larger RF power. Particle-in-cell simulation for a typical 500-kV dc voltage and 15-kA beam current, the modified reltron radiates an average power of ~2.2 GW with ~14.7% efficiency. Here, virtual cathodes do not form during device oscillation, which facilitates longer pulse and repetitive pulse operation.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Development and Experimental Verification of an XY-Table for the
           Optimization of the Alignment of High-Power Gyrotrons
    • Authors: Zisis C. Ioannidis;Konstantinos A. Avramidis;Gerd Gantenbein;Stefan Illy;Thorsten Kobarg;Ioannis Gr. Pagonakis;Tomasz Rzesnicki;John Jelonnek;
      Pages: 1954 - 1959
      Abstract: The proper alignment of the electron beam with the interaction cavity is essential in order to achieve efficient operation of modern high-power, high-frequency gyrotrons. However, tolerances, manufacturing, and magnetic field alignment errors may lead to the less optimal positioning of the electron beam in the gyrotron cavity. In this paper, we describe in detail the in-house design and development of a simple and low-cost prototype gyrotron-alignment XY-table, which can be used for the optimization of the alignment of the electron beam with the cavity axis. The efficient operation of the device is verified experimentally by operating the European ITER 170-GHz, 1-MW short-pulse prototype gyrotron in the Oxford Instruments superconducting magnet that is available at the Karlsruhe Institute of Technology gyrotron test-stand and is equipped with a set of dipole coils.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • A Compact Relativistic Magnetron With Lower Output Mode
    • Authors: Fen Qin;Sha Xu;Lu-Rong Lei;Bin-Quan Ju;Dong Wang;
      Pages: 1960 - 1964
      Abstract: A compact relativistic magnetron (RM) with novel axial output configuration is proposed, which extracts lower order cylindrical mode (TM01 or TE11 mode) or coaxial mode (TEM or TE11 mode) in the output region. In this output configuration (namely, multiantenna output RM), several conducting rods are connected to the anode vanes of the magnetron and arranged in the axial direction to serve as the extraction antennas. High-frequency analysis demonstrates that this output structure excites lower order cylindrical RF modes efficiently without the significant expansion of the output waveguide dimension that brings a more compact magnetic field-producing system which reduces the whole volume and weight of the tube remarkably. The maximum microwave efficiency of 47% has been obtained for an L-band RM with the multiantenna output structure in particle-in-cell simulations. Primary experiments had been carried out, which validated that RM with multiantenna output has the capacity to generate high- power microwave over 1 GW.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • A Multiobjective Optimization Design Tool for Traveling-Wave Tubes’
           Electron Optics System
    • Authors: Tao Huang;Qiu-Feng Cao;Jia Liu;Da-Peng Gong;Li Lei;Xiao-Lin Jin;Quan Hu;Zhong-Hai Yang;Bin Li;
      Pages: 1965 - 1970
      Abstract: The nondominated sorting genetic algorithm II and the electron optics simulator were combined to form a multiobjective optimization design tool for electron optics systems of traveling-wave tubes. After determining the objective functions that vary with the macroscopic electrical parameters that need to optimize the electron optics system, the optimization tool is capable of obtaining the optimal solution set automatically. Then, the microscopic electron trajectories of the individuals in the optimal solution set are analyzed to get the final scheme. In the collector optimization, the maximum collector efficiency and the minimum back-streaming current are used as optimization goals. While for the demonstrated electron gun, the maximum waist position is set to be the optimization goal, together with constraints of emitting current and beam waist radius. After analyzing the energy density distribution on the collector inner surface or the laminar flow of the electron gun, the final scheme is determined from the optimal solution set.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Electrostatic Doping-Based All GNR Tunnel FET: An Energy-Efficient Design
           for Power Electronics
    • Authors: Weixiang Zhang;Tarek Ragab;Cemal Basaran;
      Pages: 1971 - 1978
      Abstract: Electrostatic doping (ED)-based graphene nanoribbon (GNR) tunneling field-effect transistor (TFET) with trigate design is studied. The transfer and output characteristics of the GNR-TFET are explored using extended Hückel semiempirical method. An ION/IOFF ratio as high as 1014 is obtained with the ON-state current on the order of 103 μA/μm. A sub-60 mv/decade subthreshold swing is also observed (35 mv/decade). Armchair GNR with widths of 11 and 9 dimmers is found to be the best geometry to obtain a high ION/IOFF ratio, and channel length of greater than 6.9 nm suppresses short-channel effect. The scaling behavior of the ED-based GNR-TFET is also studied. It is observed that a smaller gate-to-gate distance facilitate large ON-state current and small OFF-state current. Moreover, it is shown that for a high-quality switching performance, the lowest required built-in gate voltage must provide enough energy differential ΔE between the source- and drain-side energy bands.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Analysis of Negative-Capacitance Germanium FinFET With the Presence of
           Fixed Trap Charges
    • Authors: Monika Bansal;Harsupreet Kaur;
      Pages: 1979 - 1984
      Abstract: In this paper, the effect of negativecapacitance (NC) on germanium FinFET (GeFinFET) with the presence of fixed trap charges (Nftc) has been studied. The analysis of various parameters of NCGeFinFET has shown that the positive trap charges improve the device characteristics whereas the negative trap charges (NTC) degrade the performance of devices. Therefore, we have optimized properties of ferroelectric (FE) to suppress the degradation caused by NTC. Furthermore, the impact of Nftc has been studied on the output characteristics of NCGeFinFET inverter, and it has been shown that the degradation due to NTC reduces by optimizing the FE properties. It has also been demonstrated that NCGeFinFET exhibits excellently improved characteristics as compared to GeFinFET.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With
           Staggered Tunneling Junction
    • Authors: Hongjuan Wang;Genquan Han;Xiangwei Jiang;Yan Liu;Jincheng Zhang;Yue Hao;
      Pages: 1985 - 1989
      Abstract: Vertical tunneling FET utilizing hetero-line architecture with GeSn/SiGeSn staggered tunneling junction (TJ) is designed and theoretically characterized. Utilizing vertical spacer etching and selective growth techniques, p+ GeSn source/n+ SiGeSn pockets line tunneling can be realized, which strengthens the boosting effect of staggered TJ. It is demonstrated that, in addition to reducing the tunneling barrier by increasing Sn composition, the device performance can be improved by optimizing length and thickness of n+ SiGeSn pocket.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • SkyLogic—A Proposal for a Skyrmion-Based Logic Device
    • Authors: Meghna G. Mankalale;Zhengyang Zhao;Jian-Ping Wang;Sachin S. Sapatnekar;
      Pages: 1990 - 1996
      Abstract: This paper proposes a novel logic device (SkyLogic) based on skyrmions that are magnetic vortex-like structures having low depinning current density and are robust to defects. A charge current sent through a polarizer ferromagnet (P-FM) nucleates a skyrmion at the input end of an intragate FM interconnect with perpendicular magnetic anisotropy (PMA-FM). The output end of the PMA-FM forms the free layer of an magnetic tunnel junction (MTJ) stack. A spin Hall metal (SHM) is placed beneath the PMA-FM. The skyrmion is propagated to the output end of the PMA-FM by passing a charge current through the SHM. The resistance of the MTJ stack is low (high) when a skyrmion is present (absent) in the free layer, thereby realizing an inverter. A framework is developed to analyze the performance of the SkyLogic device. A circuit-level technique is developed that counters the transverse displacement of skyrmion in the PMA-FM and allows the use of high current densities for the fast propagation. The design space exploration of the PMA-FM material parameters is performed to obtain an optimal design point. At the optimal point, we obtain an inverter delay of 434 ps with a switching energy of 7.1 fJ.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • An MoS2-Based Piezoelectric FET: A Computational Study of Material
           Properties and Device Design
    • Authors: Moslem Alidoosty-Shahraki;Mahdi Pourfath;David Esseni;
      Pages: 1997 - 2003
      Abstract: In this paper, we show that MoS2 multilayers have mechanical and electrical properties that qualify them as promising channel materials for an n-type piezoelectric FET (PZ-FET). We present extensive density functional theory calculations to investigate the effects of a compressive, out-of-plane stress on MoS2 monolayers and multilayers and extract the corresponding stiffness, as well as the sensitivity to stress of the conduction and valence band edge, and of the effective masses. Then, we use these material properties and a top-of-the-barrier ballistic transistor model to evaluate numerically the IDS versus VG characteristics of n-type PZ-FETs with an MoS2 channel material. Our results indicate that MoS2 multilayers are the best material option for n-type PZ-FETs, which can reach a subthreshold swing of about 40 mV/decade for a 5-nm-thick piezoelectric layer. This is because the weak interlayer van der Waals bonding makes the conduction band edge in MoS2 multilayers very sensitive to vertical compressive stress. The simulated MoS2 PZ-FETs exhibit large ION/IOFF ratios at low voltage and have better subthreshold steepness compared with the counterpart device employing a 3-D semiconductor.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
    • Authors: Wei-Xiang You;Pin Su;Chenming Hu;
      Pages: 2004 - 2009
      Abstract: This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Impact of Quantum Confinement on Band-to-Band Tunneling of Line-Tunneling
           Type L-Shaped Tunnel Field-Effect Transistor
    • Authors: Faraz Najam;Yun Seop Yu;
      Pages: 2010 - 2016
      Abstract: An L-shaped tunnel field-effect transistor (LTFET) employs an overlapped gate/channel/source architecture to maximize band-to-band tunneling (BTBT) area. The overlapped channel is very thin and suffers from the geometrical quantum confinement effect (QCE). The analysis of QCE in LTFET has been shown to significantly affect the BTBT in LTFET. As a consequence of QCE, conduction band in the overlapped channel becomes a discrete set of energy subbands, whereas the valence band in the source is continuous. The discretization of conduction band reduces the BTBT drain-source current (Ids) of LTFET. QCE also forces the lateral and parasitic component of BTBT to dominate for a significant portion of the gate-bias swing.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Spintronic Processing Unit in Spin Transfer Torque Magnetic Random Access
    • Authors: He Zhang;Wang Kang;Kaihua Cao;Bi Wu;Youguang Zhang;Weisheng Zhao;
      Pages: 2017 - 2022
      Abstract: Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform-spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks-data storage and logic computing-using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Analysis and Modeling of Inner Fringing Field Effect on Negative
           Capacitance FinFETs
    • Authors: Yen-Kai Lin;Harshit Agarwal;Pragya Kushwaha;Ming-Yen Kao;Yu-Hung Liao;Korok Chatterjee;Sayeef Salahuddin;Chenming Hu;
      Pages: 2023 - 2027
      Abstract: We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Toward Microwave S- and X-Parameter Approaches for the Characterization of
           Ferroelectrics for Applications in FeFETs and NCFETs
    • Authors: Zhi Cheng Yuan;Prasad S. Gudem;Michael Wong;Ji Kai Wang;Terence B. Hook;Paul Solomon;Diego Kienle;Mani Vaidyanathan;
      Pages: 2028 - 2035
      Abstract: Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau-Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Enhanced Performance of MSM UV Photodetectors by Molecular Modification of
           Gallium Nitride Using Porphyrin Organic Molecules
    • Authors: Manjari Garg;Bhera Ram Tak;V. Ramgopal Rao;Rajendra Singh;
      Pages: 2036 - 2039
      Abstract: In this brief, we present a novel surface modification process for gallium nitride (GaN) epitaxial films leading to enhanced ultraviolet (UV) photodetection. The adsorption of a layer of thiol-functionalized porphyrin-based organic molecules on the GaN surface has been carried out. The effect of surface modification was seen in the form of a significant reduction in the surface potential of GaN by ~250 mV and five-fold enhancement in the near-band-edge photoluminescence intensity, both indicating surface passivation of GaN. Consequently, reverse current for Nickel (Ni) Schottky contacts on molecularly modified GaN was decreased by 3 orders of magnitude, in dark at room temperature. Upon illumination by UV light, Ni/molecular layer/GaN interdigitated structures showed considerably improved photodetector (PD) characteristics such as responsivity for the visible-blind spectral region, photo-to-dark current ratio, and UV-to-visible rejection ratio. Such metal-molecular layer semiconductor device structures can be useful for the fabrication of more efficient GaN-based UV PDs, mitigating the adverse effects of electronic surface states in these materials.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Slingshot Pull-In Operation for Low-Voltage Nanoelectromechanical Memory
    • Authors: Woo Young Choi;Hyug Su Kwon;
      Pages: 2040 - 2043
      Abstract: A novel “slingshot” pull-in operation is proposed to lower the operation voltage (VDD) of nanoelectromechanical (NEM) memory switches for the implementation of monolithic 3-D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. According to the theoretical calculation and experimental data, the proposed “slingshot” pull-in operation lowers VDD of the NEM memory switches by ~0.84 times. It contributes to the overall VDD reduction and chip density boost of M3D CMOS-NEM RL circuits.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • New Diode-Triggered Silicon-Controlled Rectifier for Robust Electrostatic
           Discharge Protection at High Temperatures
    • Authors: Fei Hou;Jizhi Liu;Zhiwei Liu;Wen Huang;Tianxun Gong;Bin Yu;Juin J. Liou;
      Pages: 2044 - 2048
      Abstract: The diode-triggered silicon-controlled rectifier (DTSCR) is an important device for the electrostatic discharge (ESD) protection of low-voltage integrated circuits, and its trigger voltage is determined by the forward turn-on voltage of diode string and the voltage drops on the parasitic resistors of metal interconnects. For the conventional DTSCR, the voltage drops on the parasitic resistors are often negligible so its triggering voltage is mainly determined by the forward turn-on voltage of diode string, which decreases with increasing temperature due to the inherited negative temperature coefficient. In this paper, an improved and novel device called thermal-stable DTSCR (TSDTSCR) is proposed to offer an improved ESD protection stability at elevated temperatures. This is done by changing and optimizing the 3-D layout. In particular, the experimental results show that the trigger voltage drop of the TSDTSCR can be reduced to 13.5% at 125 °C, comparing to 27.18% of the DTSCR. The holding voltage of the TSDTSCR is also more stable than that of the DTSCR over a wide range of temperatures.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Call for Papers - T-ED special issue on Memory Devices and Technologies
           for the Next Decade
    • Pages: 2049 - 2050
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
  • Call for papers for a special issue of IEEE Transactions on Electron
           Devices on "ultra wide band gap semiconductors for power control and
    • Pages: 2051 - 2052
      Abstract: This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications.
      PubDate: April 2019
      Issue No: Vol. 66, No. 4 (2019)
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Tel: +00 44 (0)131 4513762
Fax: +00 44 (0)131 4513327
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