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  Subjects -> ELECTRONICS (Total: 175 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 76)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 305)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 35)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 44)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 253)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 104)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 85)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 91)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 50)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 2)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 185)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 96)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 65)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 69)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 55)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 39)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 70)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 11)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 45)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 57)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 12)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 23)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 162)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 6)
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 8)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Journal Cover
IEEE Transactions on Electron Devices
Journal Prestige (SJR): 0.839
Citation Impact (citeScore): 3
Number of Followers: 19  
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0018-9383
Published by IEEE Homepage  [191 journals]
  • IEEE Transactions on Electron Devices publication information
    • Abstract: "Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication."
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • IEEE Transactions on Electron Devices information for authors
    • Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Blank page
    • Abstract: This page or pages intentionally left blank.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • A SPICE Compatible Compact Model for Hot-Carrier Degradation in MOSFETs
           Under Different Experimental Conditions
    • Authors: Uma Sharma;Souvik Mahapatra;
      Pages: 839 - 846
      Abstract: A compact hot-carrier degradation (HCD) time kinetics model is proposed for conventional, lightly doped drain, and drain extended MOSFETs and FinFETs. It can predict measured data obtained using different methods such as shift in threshold voltage ( $Delta {V}_{text {T}}$ ), linear ( $Delta {I}_{text {DLIN}}$ ) and saturation ( $Delta {I}_{text {DSAT}}$ ) drain current, and charge pumping current ( $Delta {I}_{text {CP}}$ ), for off- and on-state stress conditions. The influences of the gate $({V}_{text {G}}$ ) and drain ( ${V}_{text {D}}$ ) bias for large ${V}_{text {D}}$ range and wide ${V}_{text {G}}/{V}_{text {D}}$ combinations, temperature ( ${T}$ ), and channel length $({L}_{text {CH}}$ ) have been analyzed. The impact of ${L}_{text {CH}}$ variation on ${V}_{text {G}}$ dependence of HCD has been modeled. The model parameters are listed for different devices.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Investigation of the Effects and the Random-Dopant-Induced Variations of
           Source/Drain Extension of 7-nm Strained SiGe n-Type FinFETs
    • Authors: Keng-Ming Liu;En-Ching Chen;
      Pages: 847 - 854
      Abstract: In this paper, we simulated the effects of the source/drain extensions (SDEs) of the 7-nm strained SiGe n-type FinFETs and the random dopant fluctuations (RDFs) therein by TCAD tools. First, we simulated different SDE lengths and doping concentrations to examine their effects on the device characteristics. Second, we simulated the RDF in SDE to examine the device variability. Simulation results show that increasing the SDE length and decreasing the SDE doping concentration are beneficial for the device characteristics. For the device variability, increasing the SDE length and decreasing the SDE doping concentration reduce the threshold voltage variation ( $sigma {V}_{T}$ ), on-current variation ( $sigma {I}_{ mathrm{scriptscriptstyle ON}}$ ), and off-current variation ( $sigma {I}_{ mathrm{scriptscriptstyle OFF}}$ ). Therefore, the SDE optimization is critical for both the device performance and the device variability of the 7-nm FinFETs.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • An Analytical Model for the Effective Drive Current in CMOS Circuits
    • Authors: Sergey Pidin;
      Pages: 855 - 860
      Abstract: Inverter delay is often evaluated as $textit {CV}_{text {dd}}/{I}_{text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{text {dd}}$ is the supply voltage, and ${I}_{text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $textit {CV}_{text {dd}}/{I}_{text {eff}}$ delay metrics. However, $textit {CV}_{text {dd}}/{I}_{text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{text {stack}}$ ) developed in this paper maintains simplicity of the original ${I}_{text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accurac- was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $textit {CV}_{text {dd}}/{I}_{text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $textit {CV}_{text {dd}}/{I}_{text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB
           FD-SOI MOS Transistors: Analysis and Optimization Guidelines
    • Authors: Mandar S. Bhoir;Yogesh Singh Chauhan;Nihar R. Mohapatra;
      Pages: 861 - 867
      Abstract: In this paper, we present physical insights into the role of substrate on the anomalous frequency behavior of small-signal transconductance and output conductance in the ultrathin body and buried oxide fully depleted silicon-on-insulator MOS transistors. Using the simple dc analysis, we attribute this anomalous behavior to the negative feedback originating from both minority and majority carriers in the substrate at different frequency ranges. Through measurements and detailed TCAD simulations, we have shown that back-gate bias and substrate doping strongly modulate the frequency behavior of transconductance and output conductance. It is finally proposed that circuit/device designers can smartly use the back-gate bias and substrate doping to minimize the substrate effect and improve the frequency response of the device intrinsic gain.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • An Impact Ionization MOSFET With Reduced Breakdown Voltage Based on
           Back-Gate Misalignment
    • Authors: Gaurav Musalgaonkar;Shubham Sahay;Raghvendra Sahai Saxena;Mamidala Jagadesh Kumar;
      Pages: 868 - 875
      Abstract: In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (~6 mV/dec) at a significantly low-supply voltage of ( ${V}_{text {DS}}= {0.59}$ V), which is ~48% lower than that of the corresponding single-gate IMOS ( ${V}_{text {DS}}= {1.15}$ V).
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • ${V}_{mathrm{{TH}}}$+ +Shift+in+p-GaN+Gate+HEMTs+Under+Forward+Gate+Stress&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Yuanyuan&;Qi+Zhou;Qian+Cheng;Pengcheng+Wei;Liyang+Zhu;Dong+Wei;Anbang+Zhang;Wanjun+Chen;Bo+Zhang;">Carrier Transport Mechanisms Underlying the Bidirectional
           ${V}_{mathrm{{TH}}}$ Shift in p-GaN Gate HEMTs Under Forward Gate Stress
    • Authors: Yuanyuan Shi;Qi Zhou;Qian Cheng;Pengcheng Wei;Liyang Zhu;Dong Wei;Anbang Zhang;Wanjun Chen;Bo Zhang;
      Pages: 876 - 882
      Abstract: The threshold voltage ( ${V} _{text {TH}}$ ) instability of p-GaN/AlGaN/GaN HEMTs was investigated under forward gate stress. A unique bidirectional ${V} _{text {TH}}$ shift ( $Delta {V}_{text {TH}}$ ) with the critical gate voltage ( ${V} _{text {G}}$ ) of 6 V was observed. The carrier transport mechanisms underlying the $Delta {V} _{text {TH}}$ were extensively investigated through the voltage-dependent, time-resolved, and temperature-dependent gate current. The gate current is decomposed into electron and hole current in three distinct regions with respect to ${V} _{text {G}}$ , which are off-state for ${V} _{text {G}} < {1.2}$ V ( ${V} _{text {TH}}$ ), on-state for $1.2~{V} < {V}_{text {G}} < {5}$ V and “gate-injected” region for ${V} _{text {G}}> {5}$ V. In off-state, the electrons were thermally activated and transport towards the gate, while electron-trapping governed by the space charge limited conduction (SCLC) in AlGaN barrier was observed in on-state and “gate-injected” region. Such an electron-trapping effect results in the positive ${V} _{text {TH}}$ shift for ${V} _{text {G}} < {6}$ V. Meanwhile, the marginal hole transport from gate by thermal activation was also captured by gate current, which features negligible impact on ${V} _{text {TH}}$ . However, for ${V} _{text {G}}> {6}$ V, a drastic hole injection triggered by high ${V} _{text {G}}$ takes place that causes subsequent hole-trapping in AlGaN barrier and hole-injection into GaN buffer. The injected holes enhance the positive charge in the gate region and turned the positively shifted ${V} _{text {TH}}$ into a negative shift.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Influence of GaN- and Si3N4-Passivation Layers on the Performance of
           AlGaN/GaN Diodes With a Gated Edge Termination
    • Authors: Eliana Acurio;Felice Crupi;Nicolò Ronchi;Brice De Jaeger;Benoit Bakeroot;Stefaan Decoutere;Lionel Trojman;
      Pages: 883 - 889
      Abstract: This paper analyses the influence of the GaN and Si3N4 passivation (or “cap”) layer on the top of the AlGaN barrier layer on the performance and reliability of Schottky barrier diodes with a gated edge termination (GET-SBDs). Both GaN cap and Si3N4 cap devices show similar dc characteristics but a higher density of traps at the SiO2/GaN interface or/and an increase of the total dielectric constant in the access region result in higher $R_{mathrm{ON}}$ -dispersion in GaN cap devices. The leakage current at medium/low temperatures in both types of devices shows two low-voltage-independent activation energies, suggesting thermionic and field-emission processes to be responsible for the conduction. Furthermore, a voltage-dependent activation energy in the high-temperature range occurs from low voltages in the GaN cap devices and limits their breakdown voltage ( ${V}_{mathsf {BD}}$ ). Time-dependent dielectric breakdown measurements show a tighter distribution in Si3N4 cap devices (Weibull slope $beta = {3.3}$ ) compared to GaN cap devices ( $beta = 1.8$ ). Additional measurements in plasma-enhanced atomic layer deposition (PEALD)-Si3N4 capacitors with different cap layers and TCAD simulations show an electric field distribution with a strong peak within the PEALD-Si3N4 dielectric at the GET corner, which could accelerate the formation of a percolation path and provoke the device breakdown in GaN cap SBDs even at low-stress voltages.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Investigation of Trap-Induced Threshold Voltage Instability in GaN-on-Si
    • Authors: Wenyuan Sun;Jungwoo Joh;Srikanth Krishnan;Sameer Pendharkar;Christine M. Jackson;Steven A. Ringel;Aaron R. Arehart;
      Pages: 890 - 895
      Abstract: It is shown that an $E_{rm C}$ –0.90 eV trap in commercial AlGaN/GaN MISHEMTs grown on a Si (111) substrate is responsible for a −1.8-V threshold voltage ( $V_{rm T}$ ) instability using a combination of defect spectroscopy and double-pulsed current–voltage measurements. The $E_{rm C}$ –0.90 eV trap is located in the GaN buffer and is emptied by high drain biases in pinch-off, which raises the trap above the Fermi level in the GaN buffer. This trap also exhibits both fast and slow recovery processes that are explained by the availability of free electrons throughout the depth of the GaN buffer and the trapping process that depletes the free electron concentration. TCAD modeling is used to demonstrate this process and also to show why there is not a significant increase in buffer leakage current after the large negative $V_{rm T}$ shift due to this trap. This demonstrates that optimizing buffer designs are critical for ideal device performance.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Design of Transistors Using High-Permittivity Materials
    • Authors: Zhanbo Xia;Caiyu Wang;Nidhin Kurian Kalarickal;Susanne Stemmer;Siddharth Rajan;
      Pages: 896 - 900
      Abstract: The design and modeling of dielectric superjunction transistors using combinations of ultrahigh permittivity materials and high-mobility materials are described. We show that placing high dielectric permittivity materials in the gate–drain depletion region can reduce electric field variations by screening the field due to depleted charges. This enables simultaneously high sheet charge density and breakdown voltage for scaled field-effect transistors. Using detailed 2-D device simulation of dc and high frequency characteristics, we show that extreme dielectric constant engineering provides unique opportunities for transistor design and has the potential to perform better than state-of-the-art millimeter-wave and terahertz frequency transistors.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Thermophotovoltaic Energy Conversion With GaSb Lattice-Matched
           Ga x In1−x As y Sb1−y Diodes
    • Authors: Xiao-Long Zhang;A-Bao Huang;Yi-Yi Lou;Xin Li;Min Cui;Yu Wang;
      Pages: 901 - 907
      Abstract: Residing on the experimentally available GaInAsSb alloys, thermophotovoltaic (TPV) energy conversion with GaSb lattice-matched GaInAsSb diodes has been systematically studied. It is shown that the dependence of the optimal diode structure and the resulting performances on its bandgap can be uniformly modeled by a quadratic function, and the desirable coefficients versus the evolution of radiator temperature can be further reasonably traced by a cubic function, providing thus an empirical method to rapidly yet flexibly obtain the proper GaInAsSb diode for the specific TPV application.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Assessment of Self-Heating Effects Under Lateral Scaling of GaN HEMTs
    • Authors: Alvaro D. Latorre-Rey;Ky Merrill;John D. Albrecht;Marco Saraniti;
      Pages: 908 - 916
      Abstract: The impact on self-heating mechanisms observed in GaN HEMTs fabricated on Si substrates is studied by means of a cellular Monte Carlo particle-based device simulator. Within this framework, the thermal effects are included through an energy-balance equation for phonons allowing for self-consistently coupling the charge and heat transport. First, the advanced electrothermal model of an experimental device is developed and calibrated to measured dc characteristics, showing an accurate description throughout the ${I}_{textsf {DS}}$ ( ${V}_{textsf {GS}}-{V}_{textsf {DS}}$ ) space, as a result of capturing the temperature dependence of the scattering processes that modify the charge transport. Then, the model is used to assess the effect of lateral scaling, i.e., reducing the source-to-gate ${L}_{textsf {SG}}$ and gate-to-drain ${L}_{textsf {GD}}$ dimensions, in terms of detailed temperature maps obtained for the acoustic and optical phonon modes as well as the electric field and carrier velocity profiles. It is found that the hot spot in the channel is not located at the peak electric field as predicted by previous methods, but instead, it is shifted toward the drain up to 32 nm. Furthermore, it is shown that, while scaled devices offer improved dc and small-signal ac performance, they are subjected to temperatures up to 15% higher in the channel as compared to the original nonscaled device when dissipating the same dc power, and the temperature distribution throughout the device shows a strong correlation with the scaled layout.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • $kappa$+ +Gate-Stack&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Young-Tak&;Myoung-Sun+Lee;Chul-Heung+Kim;Sung+Yun+Woo;Jong-Ho+Bae;Byung-Gook+Park;Jong-Ho+Lee;">Si-Based FET-Type Synaptic Device With Short-Term and Long-Term Plasticity
           Using High- $kappa$ Gate-Stack
    • Authors: Young-Tak Seo;Myoung-Sun Lee;Chul-Heung Kim;Sung Yun Woo;Jong-Ho Bae;Byung-Gook Park;Jong-Ho Lee;
      Pages: 917 - 923
      Abstract: In this paper, we investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based field-effect transistor-type memory device. An Al2O3/HfO2/Si3N4 gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si3N4 and HfO2 layers are designed to implement short-term and long-term memory, respectively. The mechanism of STP and LTP operation has been figured out by analyzing the device response to the potentiation and depression pulses. To investigate the STP operation, paired-pulse facilitation measurement is performed. The retention characteristic is also studied to validate the LTP property of the device. By investigating a device with an Al2O3/Si3N4 stack as a control device, it is shown that the HfO2 layer contributes to LTP in device with Al2O3/HfO2/Si3N4 stack. Thus, it is confirmed that STP and LTP operations can be implemented simultaneously in devices with an Al2O3/HfO2/Si3N4 stack.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • $_{{x}}$+ +Bilayer+Structure&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Haili&;Xumeng+Zhang;Facai+Wu;Qing+Luo;Tiancheng+Gong;Peng+Yuan;Xiaoxin+Xu;Yu+Liu;Shengjie+Zhao;Kaiping+Zhang;Cheng+Lu;Peiwen+Zhang;Jie+Feng;Hangbing+Lv;Ming+Liu;">A Self-Rectifying Resistive Switching Device Based on HfO2/TaO $_{{x}}$
           Bilayer Structure
    • Authors: Haili Ma;Xumeng Zhang;Facai Wu;Qing Luo;Tiancheng Gong;Peng Yuan;Xiaoxin Xu;Yu Liu;Shengjie Zhao;Kaiping Zhang;Cheng Lu;Peiwen Zhang;Jie Feng;Hangbing Lv;Ming Liu;
      Pages: 924 - 928
      Abstract: To effectively solve the crosstalk issue in highdensity crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a highperformance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as ~2 × 103 under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ON” state) cells, in an array of up to 32 × 32 cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrappingwas proposed to elucidatethe impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • SRAMs and DRAMs With Separate Read–Write Ports Augmented by Phase
           Transition Materials
    • Authors: Zhesheng Shen;Srivatsa Srinivasa;Ahmedullah Aziz;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;
      Pages: 929 - 937
      Abstract: We propose SRAMs and DRAM with independent read–write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Self-Organized Al Nanotip Electrodes for Achieving Ultralow-Power and
           Error-Free Memory
    • Authors: José Ramón Durán Retamal;Chin-Hsiang Ho;Kun-Tong Tsai;Jr-jian Ke;Jr-Hau He;
      Pages: 938 - 943
      Abstract: Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98 V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Influence of Size and Shape on the Performance of VCMA-Based MTJs
    • Authors: Venkata Pavan Kumar Miriyala;Xuanyao Fong;Gengchiau Liang;
      Pages: 944 - 949
      Abstract: In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Complementary Integrated Circuits Based on n-Type and p-Type Oxide
           Semiconductors for Applications Beyond Flat-Panel Displays
    • Authors: Yunpeng Li;Jiawei Zhang;Jin Yang;Yvzhuo Yuan;Zhenjia Hu;Zhaojun Lin;Aimin Song;Qian Xin;
      Pages: 950 - 956
      Abstract: Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $sim 1~mu text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Electrode-Adaptive Thin-Film Integrated Logic Circuits
    • Authors: Byeong Hyeon Lee;Kyung-Sang Cho;Ahrum Sohn;Sungwoo Hwang;Sang Yeol Lee;
      Pages: 957 - 962
      Abstract: Amorphous oxide-based thin-film logic circuits have been fabricated using only an n-type amorphous silicon–zinc–tin–oxide (a-SZTO) channel layer with different source/drain electrodes. Enhancement-mode thin-film transistors (TFTs) were fabricated with oxide electrodes. Depletion-mode TFTs were fabricated with metal electrode. Work functions were measured by Kelvin probemicroscopy. The barrier heights ( $Phi _{textsf {B}}$ ) between the a-SZTO channel layer and the electrode were measured to be 1.831, 2.341, and 2.339 eV for the Ti/Al electrode, Indium–silicon–oxide (ISO) electrode, and indium–tin–oxide (ITO) electrode, respectively. The physicalmechanism on the variation of sheet and contact resistances was investigated using a transmission line method, and the change in the resistances is closely related to $Phi _{textsf {B}}$ . Inverters were fabricated, with different $V_{textsf {TH}}$ values adopted simply by using different contact characteristics between various electrodes and the semiconductor channel. High values of voltage gains in inverters were obtained: 12.33 (ISO) and 11.75 (ITO) at $V_{textsf {DD}}= 5$ V. Itwas also confirmed that more complicated n-type-based NAND and NOR thin-film circuits, implementedwith different electrodes, functioned as conventional logic circuits. This simple fabrication method of thin-film logic circuits opens the possibility of implementing next-generation stacked integrated circuit technology.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Electroluminescent Cooling in III–V Intracavity Diodes: Practical
    • Authors: Toufik Sadi;Ivan Radevici;Pyry Kivisaari;Jani Oksanen;
      Pages: 963 - 968
      Abstract: Recent studies of electroluminescent cooling (ELC) in III-V structures demonstrate the need to better understand the factors affecting the efficiency of light emission and energy transport in light-emitting diodes (LEDs). In this paper, we establish the physical and operational requirements for reaching the efficiencies needed for observing ELC in the III-V intracavity double-diode structures at high powers. The experimentally validated modeling framework used in this paper, coupling the drift-diffusion charge transport model with a photon transport model, indicates that the bulk properties of the III-V materials are already sufficient for ELC. Furthermore, the results suggest that the bulk power conversion efficiency of the LED in the devices, which allowed the experimentally measured record high coupling quantum efficiency of 70%, already exceeds 115%. However, as shown here, direct observation of ELC by electrical measurements still requires a combination of a more efficient suppression of the nonradiative surface recombination at the LED walls and the reduction of the detection losses in the photodetector of the intracavity structures.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Quarter Video Graphics Array Digital Pixel Image Sensing With a Linear and
           Wide- Dynamic-Range Response by Using Pixel-Wise 3-D Integration
    • Authors: Masahide Goto;Yuki Honda;Toshihisa Watabe;Kei Hagiwara;Masakazu Nanba;Yoshinori Iguchi;Takuya Saraya;Masaharu Kobayashi;Eiji Higurashi;Hiroshi Toshiyoshi;Toshiro Hiramoto;
      Pages: 969 - 975
      Abstract: We have developed a quarter video graphics array (QVGA) digital pixel image sensor by using the 3-D integration technology. The pulse-frequency modulation (PFM) analog-to-digital converter (ADC) operates as a digital pixel, which overcomes the signal saturation due to the full well capacity of the photodiode (PD). We have also newly designed a PFM-ADC for pixels with a pinned PD and a floating diffusion to comply with the CMOS image sensor process used to attain high sensitivity and low noise. PDs, comparators, logic circuits, and counters are integrated into two silicon-on-insulator layers by pixel-wise 3-D integration with gold electrodes with a ${5}~mu text{m}$ diameter, thereby achieving a QVGA resolution for a 20-mm square chip in the 0.18- and 0.2- $mu text{m}$ process nodes. The developed sensor exhibits both the excellent linearity and a wide-dynamic range of more than 96 dB. Video images with a high bit depth of 16 bit are also obtained to demonstrate the superior image sensing, capable of capturing the real world at high fidelity.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • High-Efficiency Deep-Ultraviolet Light-Emitting Diodes With Efficient
           Carrier Confinement and High Light Extraction
    • Authors: Jih-Yuan Chang;Bo-Ting Liou;Man-Fang Huang;Ya-Hsuan Shih;Fang-Ming Chen;Yen-Kuang Kuo;
      Pages: 976 - 982
      Abstract: In deep-ultraviolet (DUV) light-emitting diodes (LEDs), it is difficult to obtain both efficient carrier confinement and high light extraction, which are quite sensitive to optical polarization and other physical parameters. In this paper, characteristics of DUV LEDs with various n-AlGaN layers and quantum barriers (QBs), and various widths of quantum wells (QWs) are investigated. Specifically, the capability of carrier confinement and properties of optical polarization are analyzed in detail. The simulation results show that LED structure with Al0.64Ga0.36N QBs, n-Al0.7Ga0.3N layer, and 4-nm-thick QWs, which has a peak emission wavelength of 284.5 nm at 60 mA, exhibits high internal quantum efficiency of 25% and high degree of optical polarization of 0.874.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Noise Characteristics of MgZnO-Based
           Metal–Semiconductor–Metal Photodetector
    • Authors: Zhaoling Li;Ping Wang;Yan Liu;Han Yang;Xinlu Guo;Yintang Yang;
      Pages: 983 - 990
      Abstract: The noise characteristics of wurtzite MgZnO metal-semiconductor-metal photodetectors (PDs) are investigated by a proposed equivalent noise circuit model considering the effects of thermal noise and shot noise induced by the resistances and fluctuations of photogenerated carriers, respectively. Then, the impact of series and enhanced gain peaking techniques on the noise properties of the PDs is studied in detail. To verify the accuracy and effectiveness of this model, the computed noise power spectral density results are compared with the simulated data from Multisim. Results show that the output noise power is mainly determined by thermal noise when the PD works in a high-frequency region. These two gain peaking techniques, specifically, the enhanced gain peaking can decrease the shot noise power and the thermal noise power due to the leakage resistance by approximately 40 dBm/Hz, respectively, because of the introduction of gain peaking inductance and capacitance. At an applied bias of 1 V, the achieved noise equivalent power and the corresponding normalized detectivity of the thermal noise due to the parasitic resistance of the enhanced gain peaked circuit are approximately 1.28 x 10-7 W and 1.64 x 1012 Jones, respectively, with an incident light wavelength of 266 nm. This paper is valuable for developing high-speed MgZnO PDs.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Turn-OFF Transient Analysis of Superjunction IGBT
    • Authors: Zhigang Wang;Hao Zhang;James B. Kuo;
      Pages: 991 - 998
      Abstract: A turn-OFF transient analysis of the superjunction (SJ) insulated-gate bipolar transistor (IGBT) based on an analytical model as a function of structural parameters is presented in this paper. The physical phenomenon dependent on the doping density of the n-/p-pillar of the SJ IGBT could be explained using the analytical model to predict the static and transient characteristics. From this model, tradeoff between turn-OFF loss and ON-state voltage has been obtained, as verified by the TCAD simulations with a good agreement.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • General Expression for Plasma Extraction Transit-Time Oscillations From
           Silicon-Bipolar Power Semiconductor Devices
    • Authors: Katsuaki Saito;Takashi Wada;Yasushi Sasajima;
      Pages: 999 - 1005
      Abstract: We propose a general expression for plasma extraction transit-time oscillations (PETT-Oscs) from silicon-bipolar power semiconductor devices. PETT-Oscs are generated when the transition time for the hole to fly into the depletion region and be accelerated by the electric field harmonizes with the resonant frequency of the loops through stray inductances and p-n junction capacitances. A physical model of PETT leads to an expression that takes into account its dependence on voltage and dopant density. The average carrier speed in the depletion region and the junction temperature dependence are fitted to the experimental results. The validity of the proposed general expression for PETT-Osc is verified successfully through state-of-the-art insulated-gate bipolar transistor module design. PETT-Osc from the package is estimated to generate at the typical operating conditions. The expression guiding the prevention method for PETT-Osc and the completed module does not show PETT-Osc in the operational range. The expression indicates the existence of PETT-Osc outside of the operational range, although it does not appear in the voltage and current for the collector or the gate. However, precise measurement using an antenna revealed the presence of PETT-Osc at the predicted conditions.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Parameter Extraction and Power/Performance Analysis of Monolithic 3-D
           Inverter (M3INV)
    • Authors: Tae Jun Ahn;Rakesh Perumal;Sung Kyu Lim;Yun Seop Yu;
      Pages: 1006 - 1011
      Abstract: An equivalent circuit model of monolithic 3-D inverter (M3INV) considering the electrical coupling between the stacked metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. We conduct the parameter extraction with technology computer-aided design (TCAD) simulations, where LETI-UTSOI model in HSPICE is used for the bottom PFET and the top NFETs. Their parameters are extracted by fitting their current–voltage (for dc analysis) and capacitance–voltage (for transient ac analysis) characteristics. The parameters extracted from the LETI-UTSOI model contain the electrical coupling at the gate of the bottom MOSFET. In order to extract external capacitances such as monolithic intertier via (MIV)-to-MIV and MIV-to-contact in M3INV, we use two structures, the first that contains MIVs and metal lines and the second that does not. We observe that the dc and transient characteristics of M3INVs built using our extracted parameters match the TCAD mixed-mode circuit simulation results considerably well. Finally, we build and analyze ring oscillators using our M3INV to demonstrate the coupling impact on power and performance.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Comprehensive Investigation on Electrical Properties of nLDMOS and pLDMOS
           Under Mechanical Strain
    • Authors: Wangran Wu;Yaohui Wang;Guangan Yang;Siyang Liu;Jing Zhu;Weifeng Sun;
      Pages: 1012 - 1017
      Abstract: In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • A Novel Insulated Gate Triggered Thyristor With Schottky Barrier for
           Improved Repetitive Pulse Life and High-di/dt Characteristics
    • Authors: Chao Liu;Wanjun Chen;Yijun Shi;Hong Tao;Qijun Zhou;Huiling Zuo;Bin Qiao;Yun Xia;Ziyan Xiao;Wuhao Gao;Nan Chen;Xiaorui Xu;Qi Zhou;Zhaoji Li;Bo Zhang;
      Pages: 1018 - 1025
      Abstract: In this paper, a novel insulated gate triggered thyristor with the Schottky barrier (SB-IGTT) is proposed for improved the repetitive pulse life and high-di/dt characteristics. Different from the conventional cathode shorted MOS-controlled thyristor (CS-MCT), an SB is specially imbedded to enlarge the effective turn-on area and enhance the electron–hole plasma spread during short duration pulse, which contributes significantly to relaxing the thermal concentration and improving the repetitive pulse life as well as achieves superior di/dt characteristics. The experimental results show that the proposed SB-IGTT continuously undergoes more than 220 000 shots at the pulse frequency of 5 Hz, yielding a $10times $ longer repetitive pulse life than the conventional CS-MCT. Simultaneously, SB-IGTT performs a di/dt up to 120 kA/ $mu text{s}$ with peak current near 10 kA, increasing di/dt by about 20%. Improved repetitive pulse life and simultaneous superior di/dt characteristics indicate that the proposed SB-IGTT is suitable for repetitive pulse power applications.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Impact of Termination Region on Switching Loss for SiC MOSFET
    • Authors: Xuan Li;Ben Tan;Alex Q. Huang;Bo Zhang;Yumeng Zhang;Xiaochuan Deng;Zhaoji Li;Xu She;Fangzhou Wang;Xing Huang;
      Pages: 1026 - 1031
      Abstract: Due to outstanding properties of silicon carbide (SiC) and unipolar current conduction mechanism, the active chip size of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is significantly shrunk, which significantly improves switching performance. However, the termination region cannot be scaled down due to the existence of high breakdown electric field enclosing active region. Therefore, a SiC MOSFET switching loss model considering termination region effect is proposed in this paper with revealing physical insights into termination region during switching process. Furthermore, through theoretical analysis, model establishment, and simulation results, the loss breakdown under various blocking voltages (800, 1000, and 1200 V) for 1-, 3-, and 6-A current rated devices is obtained. ${E}_{textsf {term}}$ and ${E}_{textsf {acti}}$ as intrinsic loss of turn-on process make a significant contribution to the total switching loss under fast gate drive condition. The model shows that the turn-on and turn-off losses are under and overestimated, respectively, by using the commonly used electrical measurement. The loss from termination region aggravates the underestimation of turn-on loss and overestimation of turn-off loss further. The proposed loss estimation equation could provide accurate loss to help choose device and design power circuit for power electronic community. The results also raise new perspective to edge termination of efficient/reliable SiC MOSFET for device people.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Nonlinear Electrothermal Model for Investigating Transient Temperature
           Responses of a Through-Silicon Via Array Applied With Gaussian Pulses in
           3-D IC
    • Authors: Jingrui Chai;Gang Dong;Yintang Yang;
      Pages: 1032 - 1040
      Abstract: In this paper, a through-silicon via (TSV) array under Gaussian pulse is studied comprehensively with a rigorous consideration of its electrothermal characteristics. To enhance the computational efficiency and reduce the memory cost, we develop a unified radial point interpolation method (RPIM) to handle these TSV electrothermal coupling problems. The comparison between the results of the proposed formulas and fine-grid finite-element method (FEM) shows that the RPIM has a very high accuracy and reduces computational time by up to 88% in comparison with the fine-grid FEM. The transient temperature responses are studied in detail for three layouts of single-layered TSV arrays with different silicon dioxide layer thicknesses and areas enclosed by TSVs. Furthermore, the two-layered TSV array structure including microbumps and RDLs is simulated electrothermally to verify the scalability of this method. Our work demonstrated the capability of addressing a large number of TSV arrays and the proposed method enables faster and more accurate electrothermal design of TSV-based 3-D ICs.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • $mu$+ -Tips+for+AMOLEDs&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Gieun&;Jinyoung+Lee;Dong-Kyun+Shin;Jongwoon+Park;">Roll-to-Roll Fabrication of PEDOT:PSS Stripes Using Slot-Die Head With
           $mu$ -Tips for AMOLEDs
    • Authors: Gieun Kim;Jinyoung Lee;Dong-Kyun Shin;Jongwoon Park;
      Pages: 1041 - 1049
      Abstract: Stripe coating offers an approach to remove the pixel bank structure used to confine ink droplets. For potential application in solution-processable active-matrix organic light-emitting diode displays, we fabricate fine and dense stripes of poly(3,4-ethylenedioxythiophene): poly(4-styrenesulfonate)(PEDOT:PSS) using a slot-die head with the dual plate (shim plate with slit channels and meniscus-guiding plate with μ-tips as narrow as pixels). We analyze the flow distribution of the aqueous PEDOT:PSS solution near the μ-tip by varying the dual-plate configuration (μ-tip width, μ-tip length, and shim plate thickness) together with the process variable (i.e., coating speed) and offer design guidelines for the roll-to-roll fabrication of a fine stripe pattern. It can be achieved by reducing the μ-tip length as well as the shim plate thickness and increasing the coating speed until the flow breaks up. This scheme also enables us to raise the stripe density without defects. It is found that the μ-tip length is crucial for coatings of dense stripes. If μ-tip is long, it is not feasible to fabricate dense stripes regardless of the shim plate thickness due to an increase in resistance to flow. It is also found that the wettability of the solution serves as one of the critical parameters that determine the stripe profiles. We have fabricated 100 stripes with the average width of 227 μm and interstripe width nonuniformity as low as 9.2%. Finally, we have fabricated organic light-emitting diodes (OLEDs) atop the conductive PEDOT:PSS stripes and successfully obtained light emission from OLED stripes.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Gate Metal and Cap Layer Effects on Ge nMOSFETs Low-Frequency Noise
    • Authors: Liang He;Pan Zhao;Jiahao Liu;Yahui Su;Hua Chen;Xiaofei Jia;Hiroaki Arimura;Jerome Mitard;Liesbet Witters;Naoto Horiguchi;Nadine Collaert;Cor Claeys;Eddy Simoen;
      Pages: 1050 - 1056
      Abstract: Low-frequency noise is used to estimate the quality of the gate stack for planar Ge nMOSFETs with different effective work function metals and cap layers. It is shown that replacing TiN by a TiAl-based metal gate will induce a significant decline of the threshold voltage ${V}_{T}$ and noise power spectral density, indicating the introduction of Al will induce an advantageous effect on the trap density in the underlying HfO2. Meanwhile, the application of a LaOx cap tends to reduce ${V}_{T}$ and the trap density in the gate oxide, which could attribute to the La in-diffusion in the gate stack. The 1/f noise analysis shows that the noise could mainly be associated with number fluctuations and correlated mobility fluctuations.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Effects of Postannealing on the Characteristics and Reliability of
           Polyfluorene Organic Light-Emitting Diodes
    • Authors: W. X. Shi;N. Liu;Y. M. Zhou;X. A. Cao;
      Pages: 1057 - 1062
      Abstract: We studied the effects of postannealing on the performance of polyfluorene organic light-emitting diodes (OLEDs) with a pure poly(9,9' -dioctylfluorene-co-benzothiadiazole) (F8BT) emissive layer. After annealing at 150 °C-200 °C, the OLED exhibited the lowest voltage and highest luminance. This correlated well with the highest crystallinity of the F8BT film, as revealed by X-ray diffraction. As the temperature was raised up to 300 °C, the voltage at 50 mA/cm2 increased by 2.7 V, and the luminance decreased by 44%, whereas the device lifetime was markedly extended by as much as 13 times. The loss of crystallinity at high temperatures suggested that structural disorders were created, resulting in degraded charge transport and radiative process. Our study demonstrates the necessity of posttreatment above the glass transition temperature to obtain desirable efficiency and lifetime of solution-processed polyfluorene OLEDs.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • An Efficient Room Temperature Ethanol Sensor Device Based on p-n
           Homojunction of TiO2 Nanostructures
    • Authors: B. Bhowmik;K. Dutta;P. Bhattacharyya;
      Pages: 1063 - 1068
      Abstract: In this paper, an efficient room temperature ethanol sensor device based on p-n homojunction of p-TiO2 nanoparticles (NPs) and n-TiO2 nanotubes (NTs) is reported. p-TiO2 NPs were prepared by low-temperature sol-gel method and coated on n-TiO2 NTs (NPs) grown by electrochemical anodization. Field emission scanning electron microscopy and X-ray diffraction authenticated the formation of stable homojunction between p-type anatase TiO2 NPs and n-type anatase TiO2 NTs. Current-voltage characteristics of the device, in the lower voltage range (0-1.26 V) for 30 °C, followed nonlinear characteristics (Schottky). With increase in voltages (>1.26 V) and temperature (40 °C-100 °C) such nonlinear behavior moves toward more linear ones. The gas sensing performance of the homojunction device was studied at room temperature with alcohols as the test species. The device offered the maximum response magnitude of ~57% (toward ethanol) at 100 ppm with appreciably fast response time and recovery time of ~30 and ~16 s, respectively. Dramatic increase in the effective depletion region area distributed throughout the nanotubular voids and the associated localized electric filed originated from the electrostatic charge separation therein (which helps in easy dissociation of target species) is possibly responsible for such efficient room temperature sensing performance.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • On-Chip Thermionic Electron Emitter Arrays Based on Horizontally Aligned
           Single-Walled Carbon Nanotubes
    • Authors: Yuwei Wang;Li Fang;Li Xiang;Gongtao Wu;Yi Zeng;Qing Chen;Xianlong Wei;
      Pages: 1069 - 1074
      Abstract: Thermionic electron emitter, a critical component in vacuum electronic devices, usually suffers from bulky size, difficulty to integrate, and slow temporal response. Here, to overcome these problems, we fabricate and test a new miniature electron emitter: on-chip thermionic electron emitter arrays based on horizontally aligned single-walled carbon nanotubes. The devices are fabricated and integrated on a Si chip with microfabrication technologies, providing compactness as well as fast temporal response. Emitter arrays with a packing density of up to ~ 0.4 × 107 emitters/cm2 and an emission density of 1.73 mA/cm2 at a bias voltage of 2.64 V are realized. The turn-on/off response times of the devices are measured to be ~150/500 ns, which are 5 orders of magnitude faster than those of their bulky counterparts. The advantages of on-chip nature, high degree of integration, and fast temporal response make the thermionic emitter arrays promising in miniature vacuum electronic devices.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Scaling Procedures and Post-Optimization for the Design of High-Efficiency
    • Authors: Jinchi Cai;Igor Syratchev;Zening Lui;
      Pages: 1075 - 1081
      Abstract: A semianalytical parametric scaling procedure (PSP) for klystron design has been developed. The PSP allows existing klystron designs to be scaled to different operating frequencies, beam power, and perveance, while maintaining the electron bunching and deceleration processes. For the fixed layout of a klystron RF circuit, the PSP provides parameters of the scaled klystron which are nearly optimal. The theoretical background and step by step derivation of the scaling principles are presented. The effectiveness of the PSP is shown through a generic five-cavity L-band klystron.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Investigation of Gate-Stress Engineering in Negative Capacitance FETs
           Using Ferroelectric Hafnium Aluminum Oxides
    • Authors: Chun-Hu Cheng;Chia-Chi Fan;Chien Liu;Hsiao-Hsuan Hsu;Hsuan-Han Chen;Chih-Chieh Hsu;Shih-An Wang;Chun-Yen Chang;
      Pages: 1082 - 1086
      Abstract: In this paper, we reported a ferroelectric HfAlOx negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlOx transistor with GS engineering percentage of $text{I}_{ mathrm{scriptscriptstyle ON}}$ enhancement and 27% $text{V}_{T}$ reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • A Numerical Simulation of C3N Nanoribbon-Based Field-Effect
    • Authors: Tiancheng Zhang;Hui Zeng;Dazhi Ding;R. S. Chen;
      Pages: 1087 - 1091
      Abstract: In this paper, the electron transport properties of a C3N nanoribbon-based field-effect transistor (FET) in the ballistic regime have been simulated. Using the density-functional theory (DFT) to obtain the band structures, we found that the armchair-edged C3N nanoribbons are semiconductors, and their bandgaps are determined by their widths, while the zigzag-edged ribbons present the metallic properties. We have carried out calculations to study the transport properties of armchair-edged C3N nanoribbon by using DFT combined with the nonequilibrium Green’s function. Our simulation results revealed that both bandgap and current on/off ratio are reduced as the width increasing. Moreover, the gate length, channel length, and ribbon’s width are found to have prominent influences on the transfer characteristics. The armchair-edged C3N nanoribbon-based FETs have the highest current on/off ratio of 106 and the ideal subthreshold swing of 61.2 mV/dec, which make it promising for potential applications of FET.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • A Hammerstein–Wiener Model for Single-Electron Transistors
    • Authors: Beatriz dos Santos Pês;Elder Oroski;Janaina Gonçalves Guimarães;Marlio J. C. Bonfim;
      Pages: 1092 - 1099
      Abstract: This paper proposes a new dynamic behavior model for single-electron transistors (SETs). A comprehensive review of modeling techniques and previous models was carried out aiming to remark the originality of the new proposed technique. Once established that SET is a nonlinear system, five classes of nonlinear models were simulated and compared to each other. Characteristic SET curves obtained using Simulation of Nanostructures were used as benchmark. The mean squared error (mse) was used as metric, and the simulation time was computed for each model. Regarding these two criteria-least mse and least simulation time-the Hammerstein-Wiener model outperformed the others models.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Analysis on Performance of Ferroelectric NC-FETs Based on Real-Space
           Gibbs-Free Energy With Atomic Channel Structure
    • Authors: Xiaoyi Zhang;Xiao Gong;Gengchiau Liang;
      Pages: 1100 - 1106
      Abstract: Ferroelectric (FE) negative capacitance (NC) MOSFETs is investigated in depth with a full real-space atomic simulator. For the first time, Gibbs-free energy of the whole atomic system is employed to determine the appropriate operation region in polarization-electric-field ( ${P}$ – ${E}$ ) path of the FE layer for FE MOSFETs. With different FE thicknesses, the operation path of the FE layer in MOS structures can be hysteresis or hysteresis-free. For MOSFET structures, the operation path of FE layer will vary with different FE materials. With proper device parameters, the NC effect in FE layer can be obtained with minimum Gibbs-free energy of the MOS and MOSFET structures. The body factor, ${dV}_{G}/{d} Psi _{S}$ , is obtained with the real-space structure to reflect the influence of the FE layer and optimize the device performance. With the FE layer of the same thickness, the NC-FET with longer channel has a larger body factor which causes the tradeoff between low tunneling current and small body factor. This tradeoff makes it difficult to improve the subthreshold swing by changing the gate length. In addition, the effect of floating metal layer between FE and SiO2 layers in NC-FETs is studied in detail with atomic level real-space analysis for different gate lengths. The metal layer has a stronger influence on the electric characteristics of NC-FETs with longer channel.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • ${k}$+ +Encapsulation+on+Performance+of+MoS2+Transistor&rft.title=IEEE+Transactions+on+Electron+Devices&rft.issn=0018-9383&;&rft.aufirst=Jing-Ping&;Wen-Xuan+Xie;Lu+Liu;Xinyuan+Zhao;Xingjuan+Song;Pui-To+Lai;Wing-Man+Tang;">Effects of Trapped Charges in Gate Dielectric and High- ${k}$
           Encapsulation on Performance of MoS2 Transistor
    • Authors: Jing-Ping Xu;Wen-Xuan Xie;Lu Liu;Xinyuan Zhao;Xingjuan Song;Pui-To Lai;Wing-Man Tang;
      Pages: 1107 - 1112
      Abstract: The effects of trapped charges in gate dielectric and high- ${k}$ encapsulation layer on the performance of MoS2 transistor are investigated by using SiO2 with different thicknesses as the gate dielectric and HfO2 as the encapsulation layer of the MoS2 surface. Results indicate that the positive trapped charges in SiO2 can increase the electrons in MoS2 for screening the scattering of charged impurity (CI) in SiO2 and at the SiO2/MoS2 interface to increase the carrier mobility. However, the CI scattering becomes stronger for thicker gate dielectric with more trapped charges and can dominate the electron screening effect to reduce the mobility. On the other hand, with the HfO2 encapsulation, the OFF-currents of the devices greatly increase and their threshold voltages shift negatively due to more electrons induced by more positive charges trapped in HfO2. Moreover, the screening effect of these electrons on the CI scattering results in a mobility increase, which increases with the magnitude of the CI scattering. A 51% improvement in mobility is obtained for the sample suffering from the strongest CI scattering, fully demonstrating the effective screening role of high- ${k}$ dielectric on the CI scattering.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Damage-Free ALD Blocking Oxide Layer on Functionalized Graphene Nanosheets
           as Nonvolatile Memories
    • Authors: Kai-Ping Chang;Jer-Chyi Wang;Han-Hsiang Tai;Wen-Kuan Yeh;Kai-Shin Li;Chao Sung Lai;
      Pages: 1113 - 1117
      Abstract: In this brief, nonvolatile memory (NVM) devices, based on the capacitor structure with the graphene nanosheets (GNSs) as the discrete charge storage media and atomic-layer-deposited (ALD) Al2O3 dielectric as the blocking oxide (BO) layer, have been demonstrated. The GNSs are formed by using the gold (Au) nanoparticles as the self-aligned mask and functionalized by using the NH3 plasma to enrich the charge trapping centers. In addition, the ALD Al2O3 layer is adopted as the BO layer of the GNS NVMs, resulting in a damage-free deposition on GNSs, compared to the conventional chemical-vapor-deposited SiO2 layer. The GNS NVM devices with a 15-nm-thick ALD Al2O3 BO layer can exhibit an excellent endurance of more than 105 cycles and superior data retention of lower than 30% charge loss for 10 years, suitable for future NVM applications.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Research of Single-Event Burnout and Hardening of AlGaN/GaN-Based MISFET
    • Authors: Xin Luo;Ying Wang;Yue Hao;Xing-ji Li;Chao-Ming Liu;Xin-Xing Fei;Cheng-Hao Yu;Fei Cao;
      Pages: 1118 - 1122
      Abstract: This brief first time presents single-event burnout (SEB) simulation results for conventional AlGaN/ GaN gate field plate MISFET (GFP-C MISFET), simultaneously, a hardened MISFET with electrode connected doped plugs in the buffer (EC-DP MISFET) is proposed for the first time. The SEB triggering mechanisms contain the back-channel effect and following impact ionization dominated by electron in the high field region. By comparing the simulation results from the GFP-C MISFET and proposed hardened EC-DP MISFET, the carriers induced by heavy ion can be quickly absorbed to drain and source electrode through EC-DP, so that the proposed EC-DP MISFET can achieve better SEB performance than conventional one. With a heavy ion having the linear energy transfer value of 0.6-pC/ $mu text{m}$ striking vertically, SEB threshold voltage obtained in GFP-C MISFET and hardened EC-DP MISFET is 280 and 338 V, respectively.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Comment on “An Analytical Model for Tunnel Barrier Modulation in Triple
           Metal Double Gate TFET”
    • Authors: A. Ananda;S. S. Chauhan;A. Prakash;
      Pages: 1123 - 1124
      Abstract: We have studied carefully the paper of Bagga and Sarkar, which describes tunnel barrier modulation of double-gate tunnel FET with triple metal and deals with its analytical model. However, some expressions are erroneous in the paper. We believe it needs to be rectified further for the scientific correctness of the result. Therefore, we would like to submit some remarks, as follows, pertaining to the errors occurred. In this comment, the previously presented expressions at page 2137 of Section III-A regarding limits of dimension of the metal gate and other expressions in boundary conditions have been corrected. The symbols, having usual meanings, have been retained for easy comparison between this and reference journal.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Author’s Reply
    • Authors: Navjeet Bagga;Subir Kumar Sarkar;
      Pages: 1125 - 1125
      Abstract: We appreciate the comments given by A. Ananda, S. S. Chauhan, and A. Prakash with respect to [1], where an analytical model of triple-metal double-gate tunnel FET has been proposed. In our opinion, the manuscript [1] contains some misprint/mistakes which were pointed out in the comments. These are as follows.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Erratum to “Reliability Improvement of GaN Devices on Free-Standing GaN
           Substrates” [Aug 18 3379-3387]
    • Authors: Dongliang Zhang;Xinhong Cheng;Wai Tung Ng;Lingyan Shen;Li Zheng;Qian Wang;Ru Qian;Ziyue Gu;Dengpeng Wu;Wen Zhou;Hongyue Zhu;Yuehui Yu;
      Pages: 1126 - 1126
      Abstract: The authors would like to make correction to [1], affiliations on page 1, because one of the affiliations in [1] was missing.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Call for Papers for a Special Issue of IEEE Transactions on Electron
           Devices on Reliability of CMOS Logic, Memory, Power and Beyond CMOS
    • Pages: 1127 - 1127
      Abstract: Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
  • Introducing IEEE Collabratec
    • Pages: 1128 - 1128
      Abstract: Advertisement, IEEE.
      PubDate: Feb. 2019
      Issue No: Vol. 66, No. 2 (2019)
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