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  Subjects -> ELECTRONICS (Total: 188 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 7)
Advances in Electronics     Open Access   (Followers: 94)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Power Electronics     Open Access   (Followers: 39)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 345)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 26)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 14)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 30)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 22)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 38)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 13)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 9)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 305)
ECTI Transactions on Computer and Information Technology (ECTI-CIT)     Open Access  
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 1)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 123)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 103)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 102)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 55)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access   (Followers: 1)
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 208)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 100)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 81)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 51)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 75)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 73)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 58)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 26)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 44)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 78)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access  
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 57)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 74)
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 38)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 11)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 3)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 10)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 25)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 11)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 35)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 9)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 3)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 177)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 10)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 3)
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 11)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 29)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Microelectronics and Solid State Electronics     Open Access   (Followers: 28)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 42)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal   (Followers: 1)
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 9)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 2)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 56)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 78)
Solid State Electronics Letters     Open Access  
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Transactions on Electrical and Electronic Materials     Hybrid Journal  
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Ural Radio Engineering Journal     Open Access  
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Journal Cover
IEEE Journal of the Electron Devices Society
Journal Prestige (SJR): 1.016
Citation Impact (citeScore): 3
Number of Followers: 9  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2168-6734
Published by IEEE Homepage  [191 journals]
  • Editorial Exciting Progress

    • Authors: Mikael Östling;
      Pages: 1 - 1
      Abstract: We enter 2019 with enforced spirit and confidence. The Journal of Electron Devices Society has developed extremely well over the past few years.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Low-Temperature MoS2 Film Formation Using Sputtering and
           H2S Annealing

    • Authors: Jun’ichi Shimizu;Takumi Ohashi;Kentaro Matsuura;Iriya Muneta;Kakushima Kuniyuki;Kazuo Tsutsui;Nobuyuki Ikarashi;Hitoshi Wakabayashi;
      Pages: 2 - 6
      Abstract: Low-carrier density and high-crystallinity molybdenum disulfide (MoS2) films were fabricated by low-temperature and clean process based on a UHV RF sputtering system. This paper focuses on improving crystallinity and reducing the number of sulfur defects of sputtered-MoS2 film. We have fabricated MoS2 films at lower than 400°C using the sputtering and H2S post-deposition annealing processes. Consequently, MoS2 films with high crystallinity and appropriate S/Mo ratio were obtained. Eventually, a low carrier density of 3.5 × 1017 cm-3 and the Hall-effect mobility of 12 cm2 V-1 s-1 were achieved.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effects of Interface States on Ge-On-SOI Photodiodes

    • Authors: Chong Li;Ben Li;Shihong Qin;Jiale Su;Xiaoying He;Xia Guo;
      Pages: 7 - 12
      Abstract: The 4.2% mismatch at the Si/Ge interface has a significant impact on Si/Ge photodetectors. However, few researchers have attempted to determine the major noise source or study the effects of the Si/Ge interface on the dark current, the responsivity and the 3-dB bandwidth of these devices. In this letter, we found that the dark current was dominated by generation-recombination processes that were enhanced by trap-assisted-tunneling around the interface below 220 K, with a characteristic tunneling energy of E00 = 14 meV corresponding to an effective mass of m* = 18m0. This behavior can be explained by the rise in the heavy-hole band caused by the compressive strain on the Ge layer. When the temperature increased above 240 K, Shockley-Read-Hall recombination was clearly observed and believed to be dominant. The responsivity, the collection efficiency and the absorption efficiency were all extracted at 850 nm, 1310 nm, and 1550 nm. The absorption coefficient around the interface was found to be lower than that of the bulk material. In addition, comparison of the measured 3-dB frequency (~20.6 GHz @ -0.5 V) with the theoretical value (~29.37 GHz) indicated that defects have little effect on the bandwidth at high frequencies.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Hybrid Phototransistor Neuromorphic Synapse

    • Authors: Yu Liu;Wen Huang;Xiawa Wang;Renrong Liang;Jing Wang;Bin Yu;Tian-Ling Ren;Jun Xu;
      Pages: 13 - 17
      Abstract: In this paper, a synaptic transistor based on the indium zinc oxide (IZO)-hafnium oxide (HfO2) thin film structure was demonstrated. Blue light pulses (470 nm) were used as the presynaptic stimulus, the IZO channel was used as the postsynaptic membrane, and the HfO2 electrolyte film was regarded as the synaptic cleft. The synaptic transistor exhibited the behavior of paired-pulse facilitation. With different light power densities, the channel current of the transistor can be regulated to different levels, corresponding to different synaptic weights. In addition, the transistor showed the brain's memory behaviors including the short-term memory and the transition from the short to the long term memory. The synaptic behaviors of the transistor can be explained by the trapping and releasing processes of the photo-generated carriers.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • SPICE Modeling of Insulator Metal Transition: Model of the Critical

    • Authors: Sherif Amer;Md Sakib Hasan;Md Musabbir Adnan;Garrett S. Rose;
      Pages: 18 - 25
      Abstract: This paper proposes a compact SPICE phenomenological model for insulator metal transition (IMT) devices. The proposed model captures the interplay of electric field and Joule heating to effect a transition from a high resistance insulating state to a low resistance metallic state. The model is corroborated against experimental results and electrothermal simulations available in the literature. The proposed model is implemented in Verilog-A and is fully compatible with commercial SPICE simulators such as Spectre from Cadence, used in this paper. An IMT-based artificial neuron is then designed and simulated using the proposed IMT compact model and design expressions for the operation of the proposed neuron are derived. The simulation results agree with the expected neuron behavior as well as the simulation results of other similar neurons proposed in the literature. This paper will enable circuit designers to design and simulate IMT-based systems and help them explore the full potential of such novel devices.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Electrical Stability of Solution-Processed a-IGZO TFTs Exposed to
           High-Humidity Ambient for Long Periods

    • Authors: Seung-Un Lee;Jaewook Jeong;
      Pages: 26 - 32
      Abstract: The variations in the electrical and mechanical properties of solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors exposed to high-humidity ambient conditions for long periods were analyzed. When the TFT was exposed to high-humidity conditions, field-effect mobility severely decreased, while ON/OFF current ratio improved and subthreshold slope value remained nearly constant, which is different from that exposed to low-humidity condition. We found that the H2O molecules induce mechanical peeling of the active layer such that they act as acceptor-like deep states, which is very different from the prior results under low humidity condition. The variations in electrical characteristics were systematically analyzed using a technology-CAD simulation before and after exposure to highhumidity conditions.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • The Vacancy Pool Model for Amorphous In-Ga-Zn-O Thin-Film Transistors

    • Authors: Ya-Hsiang Tai;Han-Wen Liu;Po-Chun Chan;
      Pages: 33 - 37
      Abstract: In this paper, the reaction rate of oxygen vacancy (VO) by the derivatives of threshold voltage (Vth) in the amorphous indium-gallium-zinc oxide thin-film transistors under light pulses with altering duty ratios is investigated. More importantly, after collecting and analyzing a lot of experimental results, a comprehensive model named VO pool is proposed. The proposed model can more universally describe the characteristic of VO reacting to the light and its degradation behavior under various kinds of stress condition.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Proton Conductor Gated Synaptic Transistor Based on Transparent IGZO for
           Realizing Electrical and UV Light Stimulus

    • Authors: Weijun Cheng;Renrong Liang;He Tian;Chuanchuan Sun;Chunsheng Jiang;Xiawa Wang;Jing Wang;Tian-Ling Ren;Jun Xu;
      Pages: 38 - 45
      Abstract: Synaptic transistors mimicking the biological synapse's short term plasticity and short-term memory property were demonstrated using the amorphous indium-gallium-zinc oxide channel in combination with the nanogranular SiO2 as the gate oxide. The lowest energy consumption was ~1.08 pJ per pulse activity and the operating voltage was within 100 mV. The device's plasticity and memory characteristics can be explained by the movement of protons in the insulating layer. The proton relaxation was revealed by two ways of dual sweeping: continuous and discontinuous sweepings. We observed that the excitatory postsynaptic current (EPSC) rose as the voltage decreased anomaly during the backward sweeping process. In the electrical stimulus, both the short-term potentiation and depression were observed for this proposed device. The amplitude of the EPSC changed with the pulse number following a saturating exponential function. For the electrical stimulus under constant illumination, the UV light wavelength, intensity and duration time were found to have little effect on the paired pulse facilitation. While in the light stimulus, the light frequency promoted the paired pulse facilitation and had more effect on the synapse's plasticity than the other light pulse parameters including intensity, numbers and width.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Self-Organized Ge Nanospherical Gate/SiO2/Si0.15Ge0.85–Nanosheet n-FETs
           Featuring High ON-OFF Drain Current Ratio

    • Authors: Po-Hsiang Liao;Kang-Ping Peng;Horng-Chih Lin;Thomas George;Pei-Wen Li;
      Pages: 46 - 51
      Abstract: We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure is simultaneously produced in a single oxidation step as a consequence of an exquisitely controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials at 900 °C. Process-controlled tunability of nanospherical gate of 60-100 nm in diameter, gate oxide thickness of 3 nm, and Si0.15Ge0.85 nanosheet with compressive strain of -2.5% was achieved. Superior gate modulation is evidenced by subthreshold slope of 150 mV/dec and ION/IOFF> 5 × 108 (IOFF 500 μA/μm) measured at VG= +1V , VD = +1 V, and T = 80 K for our device with channel length of 75 nm.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Homo-Junction Bottom-Gate Amorphous In–Ga–Zn–O TFTs With
           Metal-Induced Source/Drain Regions

    • Authors: Yang Shao;Xiaoliang Zhou;Huan Yang;Baozhu Chang;Ting Liang;Yi Wang;Shengdong Zhang;
      Pages: 52 - 56
      Abstract: A fabrication process for homo-junction bottom-gate (HJBG) amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is proposed, in which the a-IGZO section as source/drain (S/D) regions is induced into a low resistance state by coating a thin metal Al film and then performing a thermal annealing in oxygen, with the channel region protected from back etching by depositing and patterning a protective layer. The experimental results show that with a 5 nm Al film and annealing at 200 °C, the sheet resistance of the S/D a-IGZO is reduced to 803 Ω/EI, and keeps stable during a subsequent thermal treatment. In addition, the thin Al2O3 film generated by the annealing contributes to an improved thermal stability and ambient atmosphere immunity for the fabricated HJBG TFTs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $boldsymbol{beta}$+ -Ga2O3+Rectifiers&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jiancheng&;Fan+Ren;Yen-Ting+Chen;Yu-Te+Liao;Chin-Wei+Chang;Jenshan+Lin;Marko+J.+Tadjer;S.+J.+Pearton;Akito+Kuramata;">Dynamic Switching Characteristics of 1 A Forward Current
           $boldsymbol{beta}$ -Ga2O3 Rectifiers

    • Authors: Jiancheng Yang;Fan Ren;Yen-Ting Chen;Yu-Te Liao;Chin-Wei Chang;Jenshan Lin;Marko J. Tadjer;S. J. Pearton;Akito Kuramata;
      Pages: 57 - 61
      Abstract: An inductive load test circuit was used to measure the switching performance of fieldplated edge-terminated Schottky rectifiers with a reverse breakdown voltage of 760 V (0.1 cm diameter, 7.85 × 10-3cm2 area) and an absolute forward current of 1 A on 8 μm thick epitaxial ß-Ga2O3 drift layers. The recovery characteristics for these vertical geometry ß-Ga2O3 Schottky rectifiers switching from forward current of 1 A to reverse off-state voltage of -300 V showed a recovery time (trr) of 64 ns. There was no significant temperature dependence of trr up to 150 °C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A New Low Turn-Off Loss SOI Lateral Insulated Gate Bipolar Transistor With
           Buried Variation of Lateral Doping Layer

    • Authors: Tao Tian;Sheng-Li Zhang;Yu-Feng Guo;Jun Zhang;David Z. Pan;Ke-Meng Yang;
      Pages: 62 - 69
      Abstract: In this paper, we propose a new low turn-off loss silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with buried variation of lateral doping (VLD) layer. The proposed device features a VLD layer inserted in the drift region, which increases the doping dose (Q) and gradient (G) compared with Uniform P-buried (UPB) SOI LIGBT. The larger capacitance effect induced by lager Q and faster depletion leads to the lower rising anode voltage and reduced storage charge in the drift region. Therefore, a considerable low turn-off loss (Eoff) can be obtained. It is worth to note that owing to reshaped electric field in the new structure, the excess carriers of the drift region could be removed more quickly. Furthermore, larger G of the VLD layer improves the tradeoff between breakdown voltage and turn-off loss. The results of 2-D simulation indicate that the Eoff of the proposed device can reduce by 29.4% and 69.7% at 100 A·cm-2 and 200 A·cm-2, respectively, when compared with UPB SOI LIGBT.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

    • Authors: Olli-Pekka Kilpi;Johannes Svensson;Erik Lind;Lars-Erik Wernersson;
      Pages: 70 - 75
      Abstract: Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effect of Hot Electron Stress on AlGaN/GaN HEMTs of Hydrogen Poisoning

    • Authors: J. He;Y. Q. Chen;Z. Y. He;Y. F. En;C. Liu;Y. Huang;Z. Li;M. H. Tang;
      Pages: 76 - 81
      Abstract: We have investigated the effect of hot electron stress on the electrical properties of AlGaN/GaN high electron mobility transistors (HEMTs) of hydrogen poisoning. The AlGaN/GaN HEMTs were biased at the semi-on state, and they suffered from the hot electron stress. The devices of hydrogen poisoning were degraded, while there is almost no degradation for the fresh ones. The hot electron stress leads to the significantly positive shift of threshold voltage and the notable decrease of drain-to-source current for the AlGaN/GaN HEMTs of hydrogen poisoning. For the AlGaN/GaN HEMTs of hydrogen poisoning, the trap density increases by about one order of magnitude after the hot electron stress experiment. The physical mechanism can be attributed to electrically active traps due to the dehydrogenation of passivated point defects at AlGaN surface, AlGaN barrier layer, and heterostructure interface. The results of this paper may be useful in the design and application of AlGaN/GaN HEMTs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • High Performance Single Crystalline Diamond Normally-Off Field Effect

    • Authors: Zeyang Ren;Wanjiao Chen;Jinfeng Zhang;Jincheng Zhang;Chunfu Zhang;Guansheng Yuan;Kai Su;Zhiyu Lin;Yue Hao;
      Pages: 82 - 87
      Abstract: High performance normally-off hydrogen-terminated diamond (H-diamond) MOSFETs were fabricated on single crystalline diamond grown in our lab. The device with 2-μm gate length shows threshold voltage of -1.0 V, and a drain current of 51.6 mA/mm at VGS = VDS = -4.5 V and an on-resistance of 65.39 Ω·mm. The transconductance keeps increasing when VGS shifts from VTH toward more negative direction, and reaches the record high value of 20 mS/mm at VGS of -4.5 V, which benefitted from the almost constant mobility of the holes in the gate voltage range of -4 V
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A High-Performance InAs/GaSb Core-Shell Nanowire Line-Tunneling TFET: An
           Atomistic Mode-Space NEGF Study

    • Authors: Aryan Afzalian;Gerben Doornbos;Tzer-Min Shen;Matthias Passlack;Jeff Wu;
      Pages: 88 - 99
      Abstract: Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” current increases significantly with the core diameter dC and outperforms the best III-V axial “point-tunneling” NW heterojunction TFET ION by up to 6× for dC = 6.6 nm. Reaching such a high level of current at low supply voltage, however, requires and involves specific and sometime unanticipated optimizations and physics that are thoroughly investigated here. In spite of the commonly accepted view, we also show and explain the weak gate-length dependency observed for the line-tunneling current in a III-V TFET. We further investigate the effect of electron-phonon scattering and discrete dopant impurity band tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET inverter performance significantly outperforms that of the axial TFETs. The low-power (LP) VDD = 0.35V CS-inverter delay is comparable to that of the high-performance (HP) Si CMOS using VDD = 0.55, which shows promise for an LP TFET technology with HP speed.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to
           Venus Surface Atmospheric Conditions

    • Authors: Philip G. Neudeck;Liangyu Chen;Roger D. Meredith;Dorothy Lukco;David J. Spry;Leah M. Nakley;Gary W. Hunter;
      Pages: 100 - 110
      Abstract: Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet's extreme conditions of ~460°C, ~9.3 MPa (~92 Earth atmospheres) chemically reactive environment. Here, we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost threefold and were accomplished using prototype SiC JFET chips of more than sevenfold increased complexity. The demonstrated advancement marks a significant step toward realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A New High-Gain Operational Amplifier Using Transconductance-Enhancement
           Topology Integrated With Metal Oxide TFTs

    • Authors: Zhuo-Jia Chen;Wen-Xing Xu;Jian-Dong Wu;Lei Zhou;Wei-Jing Wu;Jian-Hua Zou;Miao Xu;Lei Wang;Yu-Rong Liu;Jun-Biao Peng;
      Pages: 111 - 117
      Abstract: This paper presents an integrated operational amplifier (OPAMP) consisting of only n-type metal oxide thin-film transistors. In addition to using positive feedback in the input differential pair, a transconductance-enhancement topology is applied to improve the gain of the OPAMP. The OPAMP has a voltage gain (Av) of 29.54 dB over a 3-dB bandwidth of 9.33 kHz at a supply voltage of 15 V. The unity-gain frequency, phase margin (PM), and dc power consumption (PDC) are 180.2 kHz, 21.5° PM and 5.07 mW, respectively.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Comprehensive Analysis and Optimal Design of Ge/GeSn/Ge p-n-p Infrared
           Heterojunction Phototransistors

    • Authors: Ankit Kumar Pandey;Rikmantra Basu;Harshvardhan Kumar;Guo-En Chang;
      Pages: 118 - 126
      Abstract: We present a comprehensive analysis of practical p-n-p Ge/Ge1-xSnx/Ge heterojunction phototransistors (HPTs) for design optimization for efficient infrared detection. Our design includes a Ge1-xSnx narrow-bandgap semiconductor as the active layer in the base layer, enabling extension of the photodetection range from near-infrared to mid-infrared to perform wide-range infrared detection. We calculate the current gain, signal-to-noise ratio (SNR), and optical responsivity and investigate their dependences on the structural parameters to optimize the proposed Ge1-xSnx p-n-p HPTs. The results show that the SNR is strongly dependent on the operation frequency and that the introduction of Sn into the base layer can improve the SNR in the high-frequency region. In addition, the current gain strongly depends on the Sn content in the Ge1-xSnx base layer, and a Sn content of 6%-9% maximizes the optical responsivity achievable in the infrared range. These results provide useful guidelines for designing and optimizing practical p-n-p Ge1-xSnx HPTs for high-performance infrared photodetection.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Extraction of Contact Resistance and DC Modeling in Metal Oxide TFTs

    • Authors: Na Li;Wanling Deng;Xixiong Wei;Weijing Wu;Junkai Huang;
      Pages: 127 - 133
      Abstract: Based on the device physics, a simple and fast method of extracting contact resistance in metal oxide thin-film transistors (MOTFTs) is proposed through the I-V characteristics. This method divides the channel into two parts: the contact channel and the intrinsic channel, and assumes the electrons injected into the active layer at the source side are completed in the line injection. Using the I-V characteristics, the contact voltage can be obtained, and then the contact resistance can be extracted. The results indicate that contact resistance in MOTFTs depends on Vg, Vd, and L. Applying the extraction results, a dc drain current model considering contact resistance is proposed. Using this model, we can accurately describe the measurements of MOTFTs with channel lengths scaling from 50 μm to 10 μm. Through the extensive comparisons between the model results and the numerical iteration or experimental data, the validity of the method is strongly supported. This extraction method uses non-numerical iteration, which is simple, fast, and accurate.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ferroelectric HfO2 Tunnel Junction Memory With High TER and Multi-Level
           Operation Featuring Metal Replacement Process

    • Authors: Masaharu Kobayashi;Yusaku Tagawa;Fei Mo;Takuya Saraya;Toshiro Hiramoto;
      Pages: 134 - 139
      Abstract: We have investigated device design of HfO2-based ferroelectric tunnel junction (FTJ) memory. Asymmetry of dielectric screening property in top and bottom electrodes is the key for high tunneling electroresistance (TER) ratio. Thus, metal and semiconductor electrodes are proposed. There exists a design space of ferroelectric material parameters to achieve high TER ratio under the constraint of depolarizing field. We have developed an FTJ fabrication process to realize the design. Large polarization charge and symmetric switching voltage are obtained by top metal replacement process. High TER ratio>30 and multi-level cell operation have been successfully demonstrated. Retention characteristics is promising, however, endurance characteristics should be improved for reliable operation.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Study on Selectivity and Temperature Coefficients of the Chloride Ion
           Sensors With RuOx Thin Film

    • Authors: Shi-Chang Tseng;Tong-Yu Wu;Jung-Chuan Chou;Yi-Hung Liao;Chih-Hsien Lai;Jian-Syun Chen;Min-Siang Huang;Siao-Jie Yan;Si-Hong Lin;
      Pages: 140 - 149
      Abstract: This paper investigated the response time, chloride selectivity, and temperature coefficients of the arrayed flexible ruthenium oxide chloride ion sensor in sodium chloride (NaCl) solutions with concentrations from 10-5 M to 1 M. The response time was 7 s in 1 M NaCl solution at room temperature, showing that the sensor had the characteristics of the fast response. The selectivity coefficients of the SO42- ion, NO3- ion, CO32- ion, ClO- ion, and ClO4- ion were 0.001, 0.056, 0.004, 0.015, and 0.006, respectively. The chloride ion sensing device had the good chloride selectivity. Finally, the sensitivity was investigated with different solution temperatures from 5 °C to 50 °C. The sensitivity was increased with higher solution temperature. The temperature coefficient of the sensitivity of the chloride ion sensing device was approximately 0.681 mV/pCl °C between 5 °C and 35 °C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of Retention Noise for 3-D TLC NAND Flash Memory

    • Authors: Kunliang Wang;Gang Du;Zhiyuan Lun;Xiaoyan Liu;
      Pages: 150 - 157
      Abstract: In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated. Three main noise sources, consisting of essential EES (EEES), electron numbers fluctuation, and device parameters fluctuation to broaden the retention Vth distributions are comprehensively considered, and the corresponding analytic models are developed. The impact of device parameters fluctuation is relatively larger than EEES and electron numbers fluctuation for our measured 3-D TLC NAND flash memory devices. Using the proposed models, the calculated Vth distributions after different data retention times have good agreements with the measurements, which validate our proposed models. This paper provides a method to predict the Vth distributions accurately and efficiently, and can help in improving reliability of 3-D TLC and quad-level program cell NAND flash memory.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Reliable Technology for Advanced SiC-MOS Devices Based on Fabrication of
           High Quality Silicon Oxide Layers by Converting a-Si

    • Authors: Razvan Pascu;Cosmin Romanitan;Pericle Varasteanu;Mihaela Kusko;
      Pages: 158 - 167
      Abstract: An alternative technological approach is proposed to obtain a SiO2 film on SiC using processes that finally reduce the effective fabrication costs. Accordingly, we report achieving of a high-quality oxide on 4H-SiC substrate using a process flow that consists in a preliminary deposition by sputtering, at room temperature, of an amorphous Si thin layer, followed by its oxidation at a relative low temperature (1100 °C) for SiC MOS technology. The X-ray reflectivity measurements demonstrated that the resulted oxide has a comparable roughness with the one thermally grown and presents the advantage of an almost threefold thinner interfacial layer. The improvement of the oxide/semiconductor interface was further validated by the electrical investigation of the fabricated MOS structures, where a significant diminishing of the effective oxide charge density, interface traps density, and near interface oxide traps density was assessed. Thus, we demonstrated that, for a specified thickness of the oxide layer on SiC, the proposed technological flow not only significantly reduces the standard duration of the process necessary and consequently the associated fabrication cost, but, more important, leads to superior oxides and interfaces, in terms of both micro-physical and electrical properties.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile
           Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method

    • Authors: Lun-Chun Chen;Hung-Bin Chen;Yu-Shuo Chang;Shih-Han Lin;Ming-Hung Han;Jia-Jiun Wu;Mu-Shih Yeh;Yu-Ru Lin;Yung-Chun Wu;
      Pages: 168 - 173
      Abstract: A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Symmetrical and Crossed Double-Sided Passivation Emitter and Surface Field
           Solar Cells for Bifacial Applications

    • Authors: Jyi-Tsong Lin;Kon-Yu Ho;Steve W. Haga;Wen-Hao Chen;
      Pages: 174 - 179
      Abstract: This paper proposes symmetrical and crossed double-sided passivation emitter and surface field solar cells for bifacial applications which are fully compatible with the passivated emitter and rear contact (PERC) fabrication process. Our simulations use Silvaco TCAD Atlas, calibrated by real measurements. At an ideal albedo level where light enters both sides equally, these symmetrical and crossed structures boost energy by 88.78% and 106.74%, respectively. The reason for the crossed structure's better performance is that it has a surrounding electric field. The crossed structure also obtains a 40.18 mA/cm2 short-circuit current (Jsc), a 0.67 V open-circuit voltage (Voc), an 81.07% fill factor and a 21.93% conversion efficiency (η). Compared with PERC+, the crossed structure improves low bifaciality factor (φη) and increases η by 6.44% and energy boost by 31.41% for bifacial. For more-realistic albedo levels, the structure also performs strongly. At the spectral albedo level of snow, the energy boost of the crossed structure is 102.06%, which is close to the performance at ideal albedo. At the spectral albedo level of white sand, the energy boost is 77.13%. At lower albedos, the energy boost remains between 20% and 30%.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Different Isolation Processes for Free-Standing GaN p-n Power Diode With
           Ultra-High Current Injection

    • Authors: Chia-Jui Yu;Chun-Kai Chang;Chien-Ju Chen;Jyun-Hao Liao;Meng-Chyi Wu;
      Pages: 180 - 185
      Abstract: In this paper, we report on the fabrication and high performance of power p-n diodes grown on free-standing (FS) GaN substrate. The key technique to enhance the high breakdown voltage and suppress the surface leakage current is the isolation process. The mesa-structure diode is generally formed by utilizing the inductively coupled plasma reactive ion etching; however, it always induces high surface damages and thus causes a high leakage current. In this paper, we propose a planar structure by employing the oxygen ion implantation to frame the isolation region. By following the crucial process, the fabricated mesaand planar-type diodes exhibit the turn-on voltages of 3.5 and 3.7 V, specific on-resistance (RONA) of 0.42 and 0.46 mΩ-cm2, and breakdown voltage (VB) of 2640 and 2880 V, respectively. The corresponding Baliga's figures of merit (BFOM, i.e., V2B/RONA) are 16.6 and 18 GW/cm2, respectively. The BFOM of 18 GW/cm2 is the highest reported value for FS-GaN diode. From the temperature dependent measurements, the planar-type diode also shows the better leakage current and thermal stability than the mesa-type diode.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • External Resistor-Free Gate Configuration Phase Transition FDSOI MOSFET

    • Authors: Jaemin Shin;Changhwan Shin;
      Pages: 186 - 190
      Abstract: Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A SiC BJT-Based Negative Resistance Oscillator for High-Temperature

    • Authors: Muhammad Waqar Hussain;Hossein Elahipanah;John E. Zumbro;Saul Rodriguez;Bengt Gunnar Malm;Homer A. Mantooth;Ana Rusu;
      Pages: 191 - 195
      Abstract: This brief presents a 59.5 MHz negative resistance oscillator for high-temperature operation. The oscillator employs an in-house 4H-silicon carbide BJT, integrated with the required circuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room temperature up to 400 °C. The oscillator delivers an output power of 11.2 dBm into a 50 Ω load at 25 °C, which decreases to 8.4 dBm at 400 °C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased with a collector current of 35 mA from a 12-V supply and has a maximum dc power consumption of 431 mW.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Au Nanoparticles-Decorated Surface Plasmon Enhanced ZnO Nanorods
           Ultraviolet Photodetector on Flexible Transparent Mica Substrate

    • Authors: Hainan Zhang;Yunfei Zhao;Xiangshun Geng;Yao Huang;Yuxing Li;Houfang Liu;Yu Liu;Yutao Li;Xuefeng Wang;He Tian;Renrong Liang;Tian-Ling Ren;
      Pages: 196 - 202
      Abstract: An ultraviolet (UV) photodetector based on hydrothermally processed ZnO nanorods (ZnO NRs) decorated by gold nanoparticles (Au NPs) was demonstrated to exhibit extraordinary optoelectronic properties. Due the implementation of Au NPs, the UV responsivity and specific detectivity reached 70 A/W and 3.41 × 1012 cm Hz1/2 W-1, respectively, which were enhanced by approximately four times at an excitation wavelength of 365 nm compared with those of pristine ZnO NRs. Moreover, such photodetector shows good flexibility as well due to the mica substrate, which maintains almost constant performances under different bending radii of curvature and repeatable bending test more than 200 cycles. The photodetector also exhibits good transparency, giving it the potential of integration with other light photodetectors. In addition, a schematic band-diagram and the accompanying finite-difference time-domain analysis were performed to reveal the electron transfer and electric field distribution of ZnO NRs decorated with Au NPs. Our results revealed that the noble metal modified plasmon-enhanced ZnO NRs photodetector with high responsivity, low cost has a great potential for application in manufacturing flexible and transparent integrated optoelectronics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Scaling Down Effect on Low Frequency Noise in Polycrystalline Silicon
           Thin-Film Transistors

    • Authors: Yuan Liu;Shu-Ting Cai;Chao-Yang Han;Ya-Yi Chen;Li Wang;Xiao-Ming Xiong;Rongsheng Chen;
      Pages: 203 - 209
      Abstract: Scaling down effects on conduction and low frequency noise characteristics are investigated in a set of p-type polycrystalline silicon thin-film transistors (poly-Si TFTs) with fixed channel width (W=8 μm) and different channel lengths (L=2, 4, 8, 12, and 20 μm). First, short channel effects on threshold voltage, field effect mobility, and sub-threshold swing are examined, while the presence of contact may induce to the degradation of field effect mobility in the short channel devices. Subsequently, the drain current noise power spectral densities are measured at varied effective gate voltages and drain currents. The slopes of normalized noise against effective gate voltage are varied from -1.1 to -2 with decreasing channel length, which indicates that poly-Si TFTs varied from bulk dominated devices to interface dominated devices. Based on ΔN-Δμ model, the flat-band voltage noise spectral density and coulomb scattering coefficient are extracted. Therefore, measured normalized noises are simulated by considering of contact resistance. Finally, short channel effects on some noise parameters (such as Hooge's parameter, etc.) are studied and discussed.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low
           Voltage IoT Applications

    • Authors: Jheng-Sin Liu;Michael B. Clavel;Mantu K. Hudait;
      Pages: 210 - 218
      Abstract: A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage (0.3 V ≥ VDD ≤ 0.6 V) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Accurate Graphene-Metal Junction Characterization

    • Authors: Matthias König;Günther Ruhl;Amit Gahoi;Sebastian Wittmann;Tobias Preis;Joerg-Martin Batke;Ioan Costina;Max C. Lemme;
      Pages: 219 - 226
      Abstract: A reliable method is proposed for measuring specific contact resistivity (pC) for graphenemetal contacts, which is based on a contact end resistance measurement. We investigate the proposed method with simulations and confirm that the sheet resistance under the metal contact (RSK) plays an important role, as it influences the potential barrier at the graphene-metal junction. Two different complementary metal-oxide-semiconductor-compatible aluminum-based contacts are investigated to demonstrate the importance of the sheet resistance under the metal contact: the difference in RSK arises from the formation of insulating aluminum oxide (Al2O3) and aluminum carbide (Al4C3) interfacial layers, which depends on the graphene pretreatment and process conditions. Auger electron spectroscopy and X-ray photoelectron spectroscopy support electrical data. The method allows direct measurements of contact parameters with one contact pair and enables small test structures. It is further more reliable than the conventional transfer length method when the sheet resistance of the material under the contact is large. The proposed method is thus ideal for geometrically small contacts where it minimizes measurement errors and it can be applied in particular to study emerging devices and materials.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Random Telegraph Noises in CMOS Image Sensors Caused by Variable
           Gate-Induced Sense Node Leakage Due to X-Ray Irradiation

    • Authors: Calvin Yi-Ping Chao;Thomas M.-H. Wu;Shang-Fu Yeh;Kuo-Yu Chou;Honyih Tu;Chih-Lin Lee;Chin Yin;Philippe Paillet;Vincent Goiffon;
      Pages: 227 - 238
      Abstract: The effects of X-ray irradiation on the random noises, especially the random telegraph noises (RTN), of a 45-nm on 65-nm stacked CMOS image sensor with 8.3M 1.1 μm pixels are investigated. It is found that before X-ray irradiation the dominant type of RTN among the noisiest pixels is the source follower (SF) MOSFET channel RTN. In contrast, after X-ray irradiation up to a total ionizing dose of 1 Mrad(SiO2), the RTN becomes dominated by the variable transfer-gate-induced sense node (SN) leakage. These two different types of RTN can be distinguished by their dependence on the transfer gate (TG) OFF voltage and the time between the correlated double sampling (CDS). The magnitude of the RTN from the variable SN leakage is proportional to the CDS time and can be suppressed effectively by increasing the TG OFF voltage, whereas the SF RTN is independent of the CDS time or the TG OFF voltage.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $mu$+ m+CMOS+Process&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Xiao&;Nicola+D’ascenzo;Werner+Brockherde;Stefan+Dreiner;Andrei+Schmidt;Qingguo+Xie;">Silicon Photomultipliers With Area Up to 9 mm2 in a 0.35- $mu$ m CMOS

    • Authors: Xiao Liang;Nicola D’ascenzo;Werner Brockherde;Stefan Dreiner;Andrei Schmidt;Qingguo Xie;
      Pages: 239 - 251
      Abstract: Silicon photomultipliers produced using standard complementary metal oxide semiconductor (CMOS) processes are at the basis of modern applications of sensors for weak photon fluxes. They allow in fact to integrate transistor-based electronic components within sensors and provide intelligent read-out strategies. In this paper, we investigate the scalability of a 0.35-μm CMOS process to large area devices. We report the design and characterization of SiPMs with a total area of 1, 4, and 9 mm2. Cross talk, photon detection efficiency at 420 nm, gain at 2.5 V overvoltage and breakdown voltage temperature coefficient do not depend on the total area of the sensor and are 10%, 35%, 2.5 x 106, and 35 mV/K, respectively. The dark count rate scales with the total area of the device as 180 kHz/mm2. The total output capacitance, the decay time of the single photon signal, and the single photon time resolution depend on the area of the device. We obtain a capacitance of 66.9, 270.2, and 554.0 pF, a decay time of (27.1±0.1) ns, (50.8±0.1) ns, and (78.2±0.1) ns and a single photon time resolution of (77.97±0.51) ps, (201.67 ± 0.98) ps, and (282.28 ± 0.86) ps for the 1, 4, and 9 mm2 SiPMs, respectively.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Highly Reliable Contacts to Silicon Enabled by Low Temperature Sputtered
           Graphenic Carbon

    • Authors: Max Stelzer;Moritz Jung;Ursula Wurstbauer;Alexander Holleitner;Franz Kreupl;
      Pages: 252 - 260
      Abstract: Titanium silicide (TiSi) contacts are frequently used metal-silicon contacts but are known to diffuse into the active region under high current density stress pulses. Recently, we demonstrated that graphenic carbon (GC) deposited by CVD at 1000 °C on silicon has the same low Schottky barrier as TiSi, but a much improved reliability against high current density stress pulses. In this paper, we demonstrate now that the deposition of GC is possible at 100 °C - 400 °C by a sputter process. We show that the sputtered carbon-silicon contact is over 1 billion times more stable against high current density pulses than the conventionally used TiSi-Si junction, while it has the same or even a lower Schottky barrier. SC can be doped by nitrogen (CN) and this results in an even lower resistivity and improved stability. Scalability of the CN thickness down to 5 nm is demonstrated. The finding that there is a low temperature approach for using the excellent carbon properties has important consequences for the reliability of contacts to silicon and opens up the use of GC in a vast number of other applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Simple Analytic Modeling Method for SPAD Timing Jitter Prediction

    • Authors: Feiyang Sun;Yue Xu;Zhong Wu;Jun Zhang;
      Pages: 261 - 267
      Abstract: Timing jitter as a key performance of single-photon avalanche diode (SPAD) detectors plays a significant role in determining the fast temporal response behavior of the SPAD device. Nevertheless, few analytic models are developed to directly calculate the characteristic of timing jitter for its modeling difficulty. In this paper, we propose a simple analytic modeling method, which can predict the temporal response of SPADs, without using time-consuming Monte Carlo simulation. Model investigation incorporates avalanche current, avalanche buildup time, and jitter tail under different conditions. Furthermore, the key model parameters provided by Geiger mode technology computer-aided design simulation allow an accurate prediction on timing jitter. Analytical results indicate that for an SPAD device structure with a shallow P+/N-well junction in a 0.18-μm CMOS technology, the Gaussian peak response with about 110-ps full-width at half-maximum and the exponential jitter tail are in good agreement with the measured data, validating the accuracy, and feasibility of this modeling method.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ferroelectric Field Effect Transistors Based on PZT and IGZO

    • Authors: Cristina Besleaga;Roxana Radu;Liliana-Marinela Balescu;Viorica Stancu;Andreea Costas;Viorel Dumitru;George Stan;Lucian Pintilie;
      Pages: 268 - 275
      Abstract: Ferroelectric field effect transistors (FeFETs) based on lead zirconate titanate (PZT) ferroelectric material and amorphous-indium-gallium-zinc oxide (a-IGZO) were developed and characterized. The PZT material was processed by a sol-gel method and then used as ferroelectric gate. The a-IGZO thin films, having the role of channel semiconductor, were deposited by radio-frequency magnetron sputtering, at a temperature of ~50°C. Characteristics of a typical field effect transistor with SiO2 gate insulator, grown on highly doped silicon, and of the PZT-based FeFET were compared. It was proven that the FeFETs had promising performances in terms of Ion/Ioff ratio (i.e., 106) and IDS retention behavior.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact

    • Authors: Jyi-Tsong Lin;Wei-Tse Sun;Hung-Hsiu Lin;Yi-Jie Chen;Nupur Navlakha;Abhinav Kranti;
      Pages: 276 - 281
      Abstract: In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes. As the device is free from physical doping, the problems associated with random dopant fluctuations will be eliminated in the proposed doping-less topology. Our simulation results show that a programming window of 28.7 μA/μm at a gate length of 10 nm with the retention time of 466 ms at 27 °C and 79 ms at 85 °C can be achieved with the proposed doping-less 1T-DRAM, which is much better than a conventional charge-plasma based doping-less 1T DRAM.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of Nitrous Oxide Nitridation Temperatures on P-Type Pi-Gate
           Poly-Si Junctionless Accumulation Mode TFTs

    • Authors: Dong-Ru Hsieh;Kun-Cheng Lin;Tien-Sheng Chao;
      Pages: 282 - 286
      Abstract: In this paper, the influence of nitrous oxide (N2O) nitridation temperatures on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) TFTs is experimentally investigated. The tetraethoxysilane (TEOS) gate oxide quality for PG JAM TFTs can be significantly improved by increasing N2O nitridation temperatures (TN) from 700°C to 800°C in N2O ambient, resulting in the improvement of average subthreshold swing (A.S.S.), increase of on current (ION), and enhancement of TEOS gate oxide breakdown E-field (EOBD). PG JAM TFTs by means of a proper channel doping concentration (Nch = 5 × 1018 cm-3) and a suitable TN (800°C) exhibit a steep A.S.S. ~96 mV/dec. and a large EOBD~12.1 MV/cm.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Counter-Doped Multizone Junction Termination Extension Structures in
           Vertical GaN Diodes

    • Authors: Mohammed Shurrab;Amna Siddiqui;Shakti Singh;
      Pages: 287 - 294
      Abstract: GaN is an attractive wide bandgap semiconductor for power applications, owing to its superior electrical properties, such as high critical electric field and saturation drift velocity. Recent advancements in developing native GaN substrates has drawn attention toward exploring vertical GaN power diodes with high breakdown voltages (VBR). In practice, effective edge terminations techniques, such as junction termination extension (JTE) structures, play a crucial role in realizing high-voltage devices. Though certain challenges in fabricating GaN diodes, such as difficulty in forming p-type region, makes it difficult to realize edge termination, hence impeding the development and adoption of such devices. This paper aims to address these challenges by presenting the design and methodology of forming multi-zone, counterdoped JTE structures in vertical GaN diodes, which attains close to theoretical breakdown voltage for a wide range of tolerance in implant dose variation. Extensive device simulations using experimental data and including the effects of surface charges and implant profiles, are performed to present realistic results. The results suggest that>80% of ideal VBR is achievable for a wide range of doping concentration (2.4 × 1017 cm-3) with a maximum VBR reaching 96% of the ideal value. This paper serves as the first step toward leveraging the current challenges in the fabrication of GaN diodes, by proposing optimum design techniques for realizing vertical GaN diodes with high breakdown voltages.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric
           Properties Variation on Negative Capacitance FETs

    • Authors: Vita Pi-Ho Hu;Pin-Chieh Chiu;Yi-Chun Lu;
      Pages: 295 - 302
      Abstract: In this paper, the impacts of work function variation (WFV), line-edge roughness (LER), and ferroelectric properties variation on the threshold voltage, subthreshold swing (SS), Ion, and Ioff variations are analyzed comprehensively for negative capacitance ultra-thin body SOI MOSFETs (NCSOI) compared with SOI MOSFETs (SOI). For LER induced threshold voltage variation (σVt), NC-SOI MOSFETs exhibit smaller σVt (= 3.8 mV) than the SOI MOSFETs (σVt = 17.6 mV). For analyzing WFV of NC-SOI MOSFETs, two scenarios are considered including (I) same WFV patterns, and (II) different WFV patterns between the external and internal metal gates. Compared with SOI, NC-SOI with scenario (I) exhibits comparable WFV induced σVt (= 16.2 mV), and NC-SOI with scenario (II) exhibits larger WFV induced σVt (= 28.5 mV). In scenario (II), different WFV patterns between the internal and external gates result in VFE (voltage drop across the ferroelectric layer) variations, which increases the WFV induced σVt for NC-SOI. LER dominates energy-delay product variations (σEDP), and NC-SOI MOSFETs show smaller σEDP than SOI MOSFETs. Besides, NC-SOI MOSFETs with thicker ferroelectric layer thickness (TFE), larger coercive electric field (EC), and smaller remnant polarization (P0) show smaller LER induced σVt and σSS. Ferroelectric properties variations show negligible impact on the WFV induced σVt and σSS.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Rapidly Measuring Charge Carrier Mobility of Organic Semiconductor Films
           Upon a Point-Contact Four-Probes Method

    • Authors: Dongfan Li;Shengtao Li;Wanlong Lu;Shi Feng;Peng Wei;Yupeng Hu;Xudong Wang;Guanghao Lu;
      Pages: 303 - 308
      Abstract: Field-effect mobility (μFET) of organic semiconductor films plays a key role in the performance of field-effect transistors (FETs). Numerical extraction of μFET from organic FET characteristics is not only time-consuming due to patterning of source/drain electrodes, but also frequently unreliable because of the contact resistances (RC) between source/drain electrodes and semiconductors. Here, we propose an approach to rapidly evaluate μ by a point-contact four-probes method (μPFP) for organic semiconductor films. Four tip-like probes quickly contact the semiconductor film surface directly, without deposition of the conventional source/drain electrodes, to simultaneously inject current and measure the electric potential. The charge density and thus conductance of the film is manipulated upon scanning gate voltage, from which the extraction of μPFP, in good agreement with μFET, could be realized in a few seconds. This method, with easily accessible setup and numerical model, substantially accelerates the evaluation of μPFP, and thus could help screen materials and optimize film morphology for organic FETs applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • IGZO TFT Gate Driver Circuit With Improved Output Pulse

    • Authors: Jin-Ho Kim;Jongsu Oh;Keechan Park;Jae-Hong Jeon;Yong-Sang Kim;
      Pages: 309 - 314
      Abstract: We propose a new gate driver circuit with an improved output pulse using depletion mode amorphous indium gallium zinc oxide thin film transistors. The previous reported gate driver circuit of our group has a weak point. It is that the peak voltage of the output pulse is decreased during the output pulse duration. A peak voltage drop of output pulse is larger by an increase the leakage current of the pull-down transistor as an increase of the threshold voltage (Vth) in the negative direction. Also, a power consumption is increase by that. In this paper, the new gate driver circuit is proposed to solve this weak point. The peak voltage drop of the output pulse of the new gate driver circuit is not occurred as an increase of the pull-down transistor Vth in the negative direction. The peak voltage of the output pulse of the previous reported circuit is 27.5 and 26.2 V at the transistor Vth of 0.5 and -2.9 V, respectively. However, the peak voltage of the output pulse of the new gate driver circuit is 27.8 and 27.6 V at the transistor Vth of 0.5 and -2.9 V, respectively.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Automatic Fault Detection Circuit for Integrated Gate Drivers of
           Active-Matrix Displays

    • Authors: Byung-Chang Yu;Jongbin Kim;Seung-Hyuck Lee;Hoon-Ju Chung;Seung-Woo Lee;
      Pages: 315 - 321
      Abstract: This paper presents automatic fault detection circuit for integrated gate drivers. The proposed circuit consists of one capacitor and two TFTs per scan line. The circuit can detect three types of faults, such as line disconnection (LD), low voltage stuck (LVS), and high voltage stuck (HVS) for the gate driver due to external physical stress. Simulation results showed the proposed circuit operates well. In order to verify the circuit operation, it was fabricated with indium gallium zinc oxide thin film transistors process. The measurement results also verified that our proposed fault detection circuit could detect the types and locations of the LD and LVS of the gate driver successfully. However, we found that HVS can be detected, but further study is needed to accurately detect the position of HVS in the proposed circuit.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Contact Engineering of Trilayer Black Phosphorus With Scandium and Gold

    • Authors: Yi-Chia Tsai;Blanka Magyari-Köpe;Yiming Li;Seiji Samukawa;Yoshio Nishi;Simon M. Sze;
      Pages: 322 - 328
      Abstract: High contact resistance keeps black phosphorus (BP) from fully wielding its excellent material property. Using first-principles calculations, we analyze the interfacial binding behavior and the impact of binding on the other layers of a trilayer BP. We found that the interfacial charge density and charge transfer of Scandium (Sc)-contacted trilayer BP are 2.67 and 3.29 times greater than Au-contacted trilayer BP, respectively. Moreover, the interfacial tunneling barrier height and width of Sc-contacted trilayer BP are 0 eV and 1.851 Å, which are significantly smaller than that of 5.1 eV and 2.447 Å observed in Au-contacted trilayer BP. All these facts suggest a strong bonding and efficient carrier transmission between Sc contact and trilayer BP substrate. Therefore, we conclude that the Sc electrode can lead to a superior performance that is consistent with the experiment.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency

    • Authors: Bhawna Tiwari;Pydi Ganga Bahubalindruni;Ana Santa;Jorge Martins;Priyanka Mittal;João Goes;Rodrigo Martins;Elvira Fortunato;Pedro Barquinha;
      Pages: 329 - 334
      Abstract: This paper presents the experimental characterization of different rectifier circuits using indium-gallium-zinc-oxide thin-film transistor technologies either at NFC or a high frequency range (13.56 MHz) of RFID. These circuits include a single ended rectifier, its differential counterpart, a bridge rectifier, and a cross-coupled full wave rectifier. Diodes were implemented with transistors using conventional processing steps, without requiring short channel devices (L=15 μm). Hence, there is no need for either extra masks or processing steps unlike the Schottky diode-based implementation. These circuits were fabricated on a PEN substrate with an annealing temperature not exceeding 180°C. This paper finds a direct application in flexible low-cost RFID tags since they enable integration of the required electronics to implement tags with the same fabrication steps.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Near-Linear Potentiation Mechanism of Gated Schottky Diode as a Synaptic

    • Authors: Jong-Ho Bae;Suhwan Lim;Dongseok Kwon;Jai-Ho Eum;Sung-Tae Lee;Hyeongsu Kim;Byung-Gook Park;Jong-Ho Lee;
      Pages: 335 - 343
      Abstract: The operation principle and near-linear potentiation mechanism of reconfigurable gated Schottky diodes (GSDs) are analyzed using calibrated device simulation. The reconfigurable GSD has two bottom gates and SiO2/Si3N4/SiO2 gate insulator stack. According to the polarity of the bottom gate bias, electrons, or holes are induced in the poly-Si active layer and the type of Schottky diodes is reconfigured. In the same manner, the reverse-biased current of GSD is modulated by applying bottom gate bias or storing charge in the Si3N4 charge storage layer. The reverse-biased current of GSD is exponentially proportional to the charge stored in the Si3N4 layer. By representing the amount of stored charge as a logarithmic relation to the number of potentiation pulses, the number of potentiation pulses, and the current of GSD has a power relation. It has been demonstrated that the GSD current exhibits near-linear potentiation characteristics when the exponent of the power relation is close to 1.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $Delta+V_{text{DIBLSS}}/(I_{text{on}}/I_{text{off}})$+ +and++$Delta+V_{text{DIBL}}/(I_{text{on}}/I_{text{off}})$+ &rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Yi-Chuen&;Luke+Hu;Tzu-Feng+Chang;Chih-Yi+Wang;Steven+Hsu;Osbert+Cheng;Chien-Ting+Lin;Yu-Shiang+Lin;Zen-Jay+Tsai;Ted+Wang;Touber+Tseng;Chih-Wei+Yang;Chin-Yang+Hsieh;">Monitoring of FinFET Characteristics Using $Delta
           V_{text{DIBLSS}}/(I_{text{on}}/I_{text{off}})$ and $Delta

    • Authors: Yi-Chuen Eng;Luke Hu;Tzu-Feng Chang;Chih-Yi Wang;Steven Hsu;Osbert Cheng;Chien-Ting Lin;Yu-Shiang Lin;Zen-Jay Tsai;Ted Wang;Touber Tseng;Chih-Wei Yang;Chin-Yang Hsieh;
      Pages: 344 - 350
      Abstract: In this paper, we present a descriptive analysis of a performance index, ΔVDIBLSS/(Ion/Ioff), used for performance monitoring. Scaled nand p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified ΔVDIBL/(Ion/Ioff) for monitoring the electrical characteristics of MOSFET devices is proposed due to the “quick measurements” required in the last step of the semiconductor manufacturing process. ΔVDIBL/(Ion/Ioff) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for ΔVDIBL/(Ion/Ioff) is much quicker than for ΔVDIBLSS/(Ion/Ioff), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as Ion/Ioff and intrinsic gain, gm × ro, are reported using ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff). ΔVDIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since Ion/Ioff is a sensitive function of threshold voltage, the estimates of the ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are hard to achieve.-However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of a Hybrid Approach for Normally-Off GaN HEMTs Using
           Fluorine Treatment and Recess Etch Techniques

    • Authors: Gokhan Kurt;Melisa Ekin Gulseren;Gurur Salkim;Sertac Ural;Omer Ahmet Kayal;Mustafa Ozturk;Bayram Butun;Mehmet Kabak;Ekmel Ozbay;
      Pages: 351 - 357
      Abstract: A hybrid approach for obtaining normally off high electron mobility transistors (HEMTs) combining fluorine treatment, recess etch techniques, and AlGaN buffer was studied. The effects of process variations (recess etch depth and fluorine treatment duration) and epitaxial differences (AlGaN and carbon doped GaN buffers) on the DC characteristics of the normally off HEMTs were investigated. Two different epitaxial structures and three different process variations were compared. Epitaxial structures prepared with an AlGaN buffer showed a higher threshold voltage (Vth = +3.59 V) than those prepared with a GaN buffer (Vth = +1.85 V).
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Assessment and Optimization of the Circadian Performance of
           Smartphone-Based Virtual Reality Displays

    • Authors: Tingzhu Wu;Shijie Liang;Lili Zheng;Yue Lin;Ziquan Guo;Yulin Gao;Yijun Lu;Sung-Wen Huang Chen;Chun-Fu Lee;Jia-Rou Zhou;Hao-Chung Kuo;Zhong Chen;
      Pages: 358 - 367
      Abstract: The non-visual effects of blue light in displays mean that excessive use of smartphones can disturb the human circadian rhythm. Thus, the impact of virtual reality (VR) headsets, which are worn closer to the human eye, may be even more serious. In this paper, based on non-visual parameters, such as the circadian action factor (CAF) and circadian illuminance, the circadian performance of smartphone-based VR displays is quantitatively evaluated by an evaluation system we designed. Moreover, we investigate the improvements in the circadian performance of VR headsets resulting from three practical methods for reducing the blue light content. Finally, a theoretical method of shifting the green-light wavelength of the screen close to 555 nm to optimize the CAF of VR headsets is proposed. Overall, the results of this paper are of significant value in quantifying the effects of VR displays on circadian rhythms and improving the safety of VR headsets with regard to human health.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • On the Physical Mechanism of Transient Negative Capacitance Effect in Deep
           Subthreshold Region

    • Authors: Chengji Jin;Takuya Saraya;Toshiro Hiramoto;Masaharu Kobayashi;
      Pages: 368 - 374
      Abstract: We have investigated the physical mechanism of steep subthreshold slope (SS) in ferroelectric FET (FeFET) based on a dynamic ferroelectric (FE) model without traversing the negative capacitance (NC) region of the S-shaped polarization-voltage predicted by Landau theory. The dynamic FE model is applied to an FE-dielectric (FE-DE) series capacitor as well as FeFET after calibration and verification by transient measurement of an FE-HfO2 capacitor. By investigating current through the FE-DE series capacitor and the gate capacitor of FeFET, we find that incomplete screening of spontaneous polarization charge results in transient NC and sub-60 mV/dec SS. Also, it should be noted that, for FeFET, small depletion layer capacitance has an important role to cause strong depolarization effect and thus steep SS. Moreover, reverse drain induced barrier lowering happens even with this FE model. The model presented in this paper provides a reasonable interpretation for the previously reported steep SS of NC FETs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • ZnON MIS Thin-Film Diodes

    • Authors: Mohamad Hazwan Mohd Daut;John F. Wager;Arokia Nathan;
      Pages: 375 - 381
      Abstract: Zinc oxynitride metal-insulator-semiconductor diodes are fabricated and characterized. Although these devices display excellent rectification, their temperature-dependent current-voltage characteristics are not explicable using analysis methodologies currently available in the literature. Therefore, we employ a simple curve fitting strategy in order to elucidate measured trends. It is found that the forward current trends are describable using three parameters, i.e., reverse saturation current, ideality factor, and series resistance, whereas the reverse current temperature dependence only requires one parameter, i.e., shunt resistance. All four of these model parameters are found to be strongly temperature dependent.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • The Effect of Tungsten Volume on Residual Stress and Cell Characteristics
           in MONOS

    • Authors: Young-Taek Oh;Jae-Min Sim;Hisashi Kino;Deok-Kee Kim;Tetsu Tanaka;Yun-Heub Song;
      Pages: 382 - 387
      Abstract: The effect of residual stress during the tungsten deposition process were investigated using metal-oxide-nitride-oxide-semiconductor (MONOS) devices. The variation of residual stress due to tungsten volume was measured under tensile and compressive stress conditions. Residual stress increased in proportion to the deposition volume. Stress influenced the Si/SiO2 interface and caused deterioration of the electrical properties, which was experimentally observed during measurements of the interface trap densities and memory windows. We confirmed that residual stress led to degradation of the cell characteristics of MONOS devices, and the absolute value of stress significantly affected these issues regardless of the polarity. From our experiments results, we can predict the degradation of cell characteristics in memory devices, and confirm the need for appropriate stress control in manufacturing process.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Low-Power Thin-Film Si Heterojunction FET Noise Amplifier for Generation
           of True Random Numbers

    • Authors: Bahman Hekmatshoar;Ghavam G. Shahidi;
      Pages: 388 - 392
      Abstract: A low-power noise amplifier is implemented with thin-film Si heterojunction field-effect transistors (HJFETs) and its suitability for generation of true random numbers is investigated. The HJFETs are operated at near subthreshold to obtain a large output resistance and therefore a high intrinsic gain at a low operation power. It is found that the noise output of a proof-of-concept 4-stage amplifier with a voltage gain of ~5000, bandwidth of ~1 KHz, power consumption of ~100 nW, and a dc-blocking output capacitance of 250 pF is suitable for generation of statistically true random numbers at a rate of 100 bit/s without requiring post-processing. The described technique may find application in emerging technologies, such as large-area, flexible, and/or wearable devices that benefit from enhanced security and low-power computing.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas

    • Authors: N. André;M. Rack;L. Nyssens;C. Gimeno;D. Oueslati;K. Ben Ali;S. Gilet;C. Craeye;J.-P. Raskin;D. Flandre;
      Pages: 393 - 397
      Abstract: In this paper, measurements and simulations of miniature monopole antennas for ultra-wideband (UWB) GHz intra- and inter-chips communication and biomedical applications are presented. Folded designs on four substrates are studied: 1) standard bulk; 2) high-resistivity bulk; 3) ultra low-loss radiofrequency silicon-on-insulator (RF SOI); and 4) quartz. Among the Si-based substrates, RF SOI with its trap-rich sublayer demonstrates the best performances with the lowest RF power losses and centimetric transmission distance between antennas. Transmitted power between two antennas was measured from 0.01 to 20 GHz. Using substrate characterization of resistivity, permittivity, and loss tangent based on measured coplanar waveguide lines on the same substrates, good agreement is obtained between the return losses of simulated antennas on each substrate and numerical solutions, confirming the impact of the substrate properties. An antenna bandwidth of 680 MHz is demonstrated at 6.0 GHz meeting the criterion for UWB radio communications in the 6-10 GHz band.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Complete Small-Signal MOSFET Model and Parameter Extraction Technique
           for Millimeter Wave Applications

    • Authors: Yang Cao;Wei Zhang;Jun Fu;Quan Wang;Linlin Liu;Ao Guo;
      Pages: 398 - 403
      Abstract: In this paper, we propose a parameter extraction method for a complete MOSFET small signal equivalent circuit model addressing nearly all the parasitic and non-quasi-static (NQS) effects. Extraction and de-embedding of drain/source/gate series resistances and the substrate network are found to be necessary for obtaining the intrinsic elements of the small-signal equivalent circuit. We demonstrate for the first time, a step-by-step procedure for the extraction and de-embedding of the extrinsic model parameters directly from measurements. As a result, a precise intrinsic parameters derivation in the saturation region is presented. Moreover, for the intrinsic small signal equivalent circuit, a gate drain branch is supplemented in parallel to describe parasitic gate-drain coupling under high frequency up to 60 GHz together with the NQS effects. Finally, the presented parameter extraction method is verified by comparing with the corresponding measurement data from the 40-nm RF CMOS process of Shanghai Huali Microelectronics Corporation.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $I-V$+ +Linearity+in+TaOx-Based+RRAM+Devices+for+Neuromorphic+Applications&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Changhyuck&;Andrea+Padovani;Bastien+Beltrando;Donguk+Lee;Myunghoon+Kwak;Seokjae+Lim;Luca+Larcher;Vincenzo+Della+Marca;Hyunsang+Hwang;">Investigation of $I-V$ Linearity in TaOx-Based RRAM Devices for
           Neuromorphic Applications

    • Authors: Changhyuck Sung;Andrea Padovani;Bastien Beltrando;Donguk Lee;Myunghoon Kwak;Seokjae Lim;Luca Larcher;Vincenzo Della Marca;Hyunsang Hwang;
      Pages: 404 - 408
      Abstract: We perform experiments and device simulations to investigate the origin of current-voltage (I-V) linearity of TaOX-based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the electrical characteristics (linear or nonlinear I-V) to the microscopic properties of the conductive filament (CF). Our findings indicate that the shape and the thermal properties of the CF region are crucial to achieve linear I-V characteristics. These results allow optimizing the I-V curve linearity of TaOX-based RRAM devices, explaining the wide range of linear I-V characteristics experimentally observed on RRAM device obtained. When weight sum operation using SPICE simulations is performed, the read current is improved under the condition of linear I-V characteristics due to current loss minimization.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Compact Charge Modeling of Double-Gate MOSFETs Considering the
           Density-Gradient Equation

    • Authors: Sung-Min Hong;
      Pages: 409 - 416
      Abstract: A compact charge model for double-gate metal-oxide-semiconductor field-effect transistors with the quantum confinement effect is presented. In addition to the Poisson equation, the density-gradient equation with a realistic boundary condition is considered to include the quantum confinement effect. The coupled governing equations are rigorously integrated. Contribution of the density-gradient equation is clearly identified. Based on the resultant integrated equation, a compact charge model is proposed. Expressions for model parameters are found. Numerical examples for various double-gate MOS structures are shown.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation on the Activation Energy of Device Degradation and Switching
           Time in AlGaN/GaN HEMTs for High-Frequency Application

    • Authors: Jianming Lei;Rui Wang;Guo Yang;Jin Wang;Dunjun Chen;Hai Lu;Rong Zhang;Youdou Zheng;
      Pages: 417 - 424
      Abstract: In this paper, the influence of traps on the dynamic on-resistance (Rdson) and switching time of AlGaN/GaN high-electron-mobility transistors is validated by means of a switching power converter with floating buck-boost topology. A new scheme based on the voltage-dependent dynamic Rdson is proposed to extract the average activation energy of device degradation. The average activation energy obtained is 2.25 eV at 50-200 V and 2.60 eV at 200-600 V. In addition, the dynamic Rdson is accurately extracted by a unique extraction circuit with high switching frequency up to 1 MHz and high off-state voltage up to 600 V. Meanwhile, the switching times at turn-on and turn-off transitions are captured in a floating buck-boost converter, showing that the transconductance decreases with increasing drain voltage. Furthermore, the effect of parasitic output capacitor on the dynamic Rdson is investigated by an experimental method. Finally, a proper hard operating mode is proposed to alleviate the influence of the trapping effect on the performance of switching power converters.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Evaluation of Bulk and SOI FeFET Architecture for Non-Volatile Memory

    • Authors: Antik Mallick;Nikhil Shukla;
      Pages: 425 - 429
      Abstract: The stress induced by the capping electrode is critical to stabilizing the ferroelectric phase in Si-doped HfO2 which is being actively explored for embedded non-volatile memory applications. While TiN is commonly used as the electrode of choice owing to its thermodynamic stability with HfO2, its work function (WF) (=4.8eV) results in reduced memory window (MW), and higher interlayer field (EIL) in bulk Ferroelectric FETs (FeFETs). This is attributed to the built-in electric-field that arises from the WF difference between the metal and the semiconductor. This effectively reduces the ferroelectric hysteresis, and thus, the MW at the read current. Optimizing the MW and the EIL would entail changing the WF, and thus, the capping electrode-essential to retaining the desired ferroelectric properties. We, therefore, propose using the silicon on insulator (SOI)-FeFET architecture which provides an additional knob-back-gate bias (Vbg)-to optimize the MW while reducing the EIL. Further, we show that unlike the bulk FeFET, where a small deviation from the optimal WF dramatically shrinks the MW, the SOIFeFET facilitates a relatively constant MW over a wide range of Vbg. Thus, the SOI-FeFET simplifies the MW & EIL optimization and provides an improved MW versus EIL trade-off in comparison to the bulk FeFET.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Improved Ultraviolet Detection and Device Performance of Al2O3-Dielectric
           In0.17Al0.83N/AlN/GaN MOS-HFETs

    • Authors: Ching-Sung Lee;Xue-Cheng Yao;Yi-Ping Huang;Wei-Chou Hsu;
      Pages: 430 - 434
      Abstract: Ultraviolet (UV) detection and electrical characteristics of In0.17Al0.83N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with Al2O3 gate-dielectric and passivation formed by using ultrasonic spray pyrolysis deposition (USPD) are studied with respect to a conventional Schottky-gate HFET. The present MOS-HFET (Schottky-gate HFET) has demonstrated superior spectral responsivity (SR) of 360 (340) A/W at 350 nm at VGS = 5(3) V and VDS = 6(7) V, maximum drain-source saturation current density (IDS,max) of 810.5 (546.6) mA/mm, maximum extrinsic transconductance of (gm,max) of 180.4 (221.2) mS/mm, gate-voltage swing (GVS) of 2.4 (0.5) V, on/off current ratio (Ion/Ioff) of 5.5 x 108 (1.7 x 105), two-terminal off-state gate-drain breakdown voltage (BVGD) of -158.5 (-127) V, three-terminal drain-source breakdown voltage (BVDS) of 162 (83.4) V at VGS = -10 V, and power-added efficiency (P.A.E.) of 26.3% (16.5%) at 2.4 GHz at 300 K. In addition to the improved device performance, this paper demonstrates, for the first time, the UV sensing based on an InAlN/AlN/GaN MOS-HFET design.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Improving the Scalability of SOI-Based Tunnel FETs Using Ground Plane in
           Buried Oxide

    • Authors: Shelly Garg;Sneh Saurabh;
      Pages: 435 - 443
      Abstract: Tunnel field-effect transistors (TFETs) are known to exhibit degraded electrical characteristics at smaller channel lengths, primarily due to direct source-to-drain band-to-band tunneling (BTBT). In this paper, we propose a technique to suppress direct source-to-drain BTBT by increasing the effective distance between the source and the drain. We propose to add a ground plane (GP) in the buried oxide of a silicon-on-insulator (SOI) TFET which depletes the drain and increases the effective source-to-drain distance. Using 2-D device simulations it is shown that the introduction of the ground plane is effective in reducing OFF-state current and ambipolar current, as well as, in improving the average subthreshold swing for the small channel length SOI-TFETs. Additionally, the addition of GP is helpful in ameliorating the short-channel effects, such as drain-induced barrier lowering and threshold voltage roll-off.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Operation Up to 500 °C of Al0.85Ga0.15N/Al0.7Ga0.3N High Electron
           Mobility Transistors

    • Authors: Patrick H. Carey;Fan Ren;Albert G. Baca;Brianna A. Klein;Andrew A. Allerman;Andrew M. Armstrong;Erica A. Douglas;Robert J. Kaplar;Paul G. Kotula;Stephen J. Pearton;
      Pages: 444 - 452
      Abstract: AlGaN channel high electron mobility transistors (HEMTs) are the potential next step after GaN channel HEMTs, as the high aluminum content channel leads to an ultra-wide bandgap, higher breakdown field, and improved high temperature operation. Al0.85Ga0.15N/Al0.7Ga0.3N (85/70) HEMTs were operated up to 500 °C in ambient causing only 58% reduction of dc current relative to 25 °C measurement. The low gate leakage current contributed to high gate voltage operation up to +10 V under Vds = 10 V, with ION/IOFF ratios of> 2 × 1011 and 3 × 106 at 25 and 500 °C, respectively. Gate-lag measurements at 100 kHz and 10% duty cycle were ideal and only slight loss of pulsed current at high gate voltages was observed. Low interfacial defects give rise to high quality pulsed characteristics and a low subthreshold swing value of 80 mV/dec at room temperature. Herein is an analysis of AlGaN-channel HEMTs and their potential future for high power and high temperature applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impacts of HfO2/ZnO Stack-Structured Charge-Trap Layers Controlled by
           Atomic Layer Deposition on Nonvolatile Memory Characteristics of
           In-Ga-Zn-O Channel Charge-Trap Memory Thin-Film Transistors

    • Authors: So-Yeong Na;Sung-Min Yoon;
      Pages: 453 - 461
      Abstract: We fabricated the charge-trap memory thin film transistors (CTM-TFTs) using InGaZnO (IGZO) active channel and HfO2/ZnO stack-structured charge-trap layer (CTL). To investigate the effects of the number and thickness of HfO2 layers inserted between the ZnO within the stack structured CTLs on the device characteristics, 2-nm-thick HfO2 thin films were inlaid once, twice, and four times, and 4-nm-thick HfO2 layers were introduced twice between the ZnO layers. The CTM-TFTs using the stack structured CTLs with 4-nm-thick HfO2 layers showed good memory characteristics, including large memory window (MW) of 25 V and rapid program/erase (P/E) speed of 500 μs because of high total trap density of HfO2 with a sufficient thickness to provide charge-trap centers. On the contrary, relatively narrow MW of 16 V and slower P/E speed of 100 ms were obtained for memory device using the stacked CTL with four HfO2 layers of 2 nm. The HfO2 layer with a thickness as thin as 2 nm was supposed to act as just dielectric films deactivating the trapping or migration of electron charges due to too thin film thickness. The gate-stack structures confirmed from STEM images suggested that the modulations in memory device characteristics with different CTL structures resulted from the variations in designs of stack structured CTLs when the interface qualities within the gate-stacks were well prepared. Moreover, the detailed fabrication conditions were found to be important control parameters to reproducibly obtain reliable memory device characteristics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Compensation Method for Variations in Subthreshold Slope and Threshold
           Voltage of Thin-Film Transistors for AMOLED Displays

    • Authors: Nack-Hyeon Keum;Chong-Chul Chai;Seong-Kwan Hong;Oh-Kyong Kwon;
      Pages: 462 - 469
      Abstract: In this paper, we propose a compensation method for variations in the subthreshold slope (SS) and threshold voltage (Vth) of the low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) in an attempt to improve the image quality of the active matrix organic light-emitting diode (AMOLED) displays for mobile applications. The proposed compensation method provides a uniform voltage to the OLED according to the gray level without being affected by variations in the SS and Vth of the LTPS TFTs. To verify the performance of the proposed compensation method, a test pattern, including two pixel circuits designed for 5.7-inch quadruple high-definition AMOLED display was fabricated and measured. The measurement results showed that the proposed compensation method achieved an emission current error of the pixel circuit of only ±3.1 LSB at the 255th gray level. Therefore, the proposed compensation method is very suitable for AMOLED displays requiring high image quality.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Modeling of Al Doping During 4H-SiC Chemical-Vapor-Deposition Trench

    • Authors: Kazuhiro Mochizuki;Ryoji Kosugi;Yoshiyuki Yonezawa;Hajime Okumura;
      Pages: 470 - 475
      Abstract: Aluminum doping during 4H-SiC chemical-vapor-deposition (CVD) trench filling was numerically modeled toward precise design of high-voltage superjunction devices. As a first-order approximation, growth-rate- and surface-normal-scaling functions were determined based on the reported experimental results. Simulated isoconcentration contours of aluminum were confirmed to qualitatively agree with the reported imaging of doping in SiC by scanning spreading resistance microscopy. Improvement of the proposed models based on additional experiments should contribute to reducing the development time for 4H-SiC superjunction devices fabricated using CVD trench filling.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • On the Ammonia Sensing Performance and Transmission Approach of a
           Platinum/Nickel Oxide/GaN-Based Metal-Oxide-Semiconductor Diode

    • Authors: I-Ping Liu;Ching-Hong Chang;Yen-Ming Huang;Kun-Wei Lin;
      Pages: 476 - 482
      Abstract: New platinum (Pt)/nickel oxide (NiO)/GaN-based metal-oxide-semiconductor (MOS) diodetype ammonia sensor was fabricated and studied. In addition, a new grey polynomial differential recovery (GPDR) model was developed for the application of data transmission. The studied Pt/NiO/GaNbased MOS diode shows good ammonia sensing performance at relatively high temperatures (≥423 K). A very high sensing response of 244.2 under 1000 ppm NH3/air gas and a low detecting level of 2 ppm NH3/air are obtained at 423 K. The studied device also shows operating flexibility in the applied forward and reverse voltages, and good reversibility in ammonia sensing. In order to expand the practical application of ammonia sensing, a GPDR model was developed to effectively reduce data redundancy by 64.22% and achieve a recovery rate of 99.79% compared with the original data. Therefore, the studied sensor device provides promise for ammonia sensing applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin

    • Authors: Yu Pan;Huaxiang Yin;Kailiang Huang;Zhaohao Zhang;Qingzhu Zhang;Kunpeng Jia;Zhenhua Wu;Kun Luo;Jiahan Yu;Junfeng Li;Wenwu Wang;Tianchun Ye;
      Pages: 483 - 488
      Abstract: To allow the use of molybdenum disulfide (MoS2) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS2 transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS2 device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS2 transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 106. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Employing Drain-Bias Dependent Electrical Characteristics of Poly-Si TFTs
           to Improve Gray Level Control in Low Power AMOLED Displays

    • Authors: Xinghua Xu;Botian Huang;Jiali Fan;Jiaqing Zhao;Xiaojun Guo;
      Pages: 489 - 494
      Abstract: With development of high efficiency organic light emitting diodes (OLEDs), and high mobility polycrystalline silicon (poly-Si) thin-film transistors (TFTs), low power and high resolution active matrix OLED (AMOLED) displays are becoming popular for mobile applications. However, they suffer from poor control of lower gray levels, with the driving TFT being operated in the subthreshold regime. In this paper, with help of non-ideal drain-bias dependent electrical characteristics of poly-Si TFTs, operation of the driving TFT can be moved out from the subthreshold regime to allow better control of the gray levels. As a result, a dynamic voltage scaling (DVS) method is developed, and shown to be able to improve the luminous uniformity for better image quality, while effectively reducing the static power consumption.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • ${c}$+ -Axis-Aligned+Crystalline+In-Ga-Zn+Oxide+FET+With+a+Gate+Length+of+21+nm+Suitable+for+Memory+Applications&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Hitoshi&;Kazuaki+Ohshima;Kazuki+Tsuda;Noriko+Matsumoto;Tatsuki+Koshida;Satoru+Ohshita;Hiromi+Sawai;Yuichi+Yanagisawa;Shiori+Saga;Ryo+Arasawa;Takako+Seki;Ryunosuke+Honda;Haruyuki+Baba;Daigo+Shimada;Hajime+Kimura;Ryo+Tokumaru;Tomoaki+Atsumi;Kiyoshi+Kato;Shunpei+Yamazaki;">A ${c}$ -Axis-Aligned Crystalline In-Ga-Zn Oxide FET With a Gate Length of
           21 nm Suitable for Memory Applications

    • Authors: Hitoshi Kunitake;Kazuaki Ohshima;Kazuki Tsuda;Noriko Matsumoto;Tatsuki Koshida;Satoru Ohshita;Hiromi Sawai;Yuichi Yanagisawa;Shiori Saga;Ryo Arasawa;Takako Seki;Ryunosuke Honda;Haruyuki Baba;Daigo Shimada;Hajime Kimura;Ryo Tokumaru;Tomoaki Atsumi;Kiyoshi Kato;Shunpei Yamazaki;
      Pages: 495 - 502
      Abstract: We fabricated a field-effect transistor (FET) with a gate length of 21 nm whose channel material is a c-axis-aligned crystalline In-Ga-Zn oxide (CAAC-IGZO). A CAAC-IGZO FET with a gate length of 21 nm has an extremely low off-state leakage current, a practical driving capability, and tolerance against high temperatures. CAAC-IGZO FETs enable low-power integrated circuits, such as logic and memory in high-temperature environments. Performance estimation of a memory cell using the CAAC-IGZO FET with a gate length of 21 nm revealed that a write time of less than 1 ns and a data retention time of more than 1 h would be possible at 85 °C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effect of Grain Boundary Protrusion on Electrical Performance of Low
           Temperature Polycrystalline Silicon Thin Film Transistors

    • Authors: Mohammad Masum Billah;Abu Bakar Siddik;Jung Bae Kim;Lai Zhao;Soo Young Choi;Dong Kil Yim;Jin Jang;
      Pages: 503 - 511
      Abstract: We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of ~350 nm and a protrusion height of ~35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration (~5 x 1016 cm-3) at GB protrusion site was obtained as compared to the grain (~3 x 1018 cm-3). Trapping concentration at GB is much higher, which leads to the reduction in the mobility.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $beta$+ -Ga2O3+Field-Effect+Transistor&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jiyeon&;Oukjae+Lee;Geonwook+Yoo;">Effect of Al2O3 Passivation on Electrical Properties of $beta$ -Ga2O3
           Field-Effect Transistor

    • Authors: Jiyeon Ma;Oukjae Lee;Geonwook Yoo;
      Pages: 512 - 516
      Abstract: We report on the effect of Al2O3 surface passivation on electrical properties of beta-gallium oxide (β-Ga2O3) nanomembrane field-effect transistor (FET). The fabricated bottom-gate β -Ga2O3(100) FET exhibits enhanced channel conductance and reduced hysteresis after the conformal atomic layer deposited Al2O3 passivation investigated by high-resolution transmission electron microscope (HR-TEM) analysis. Moreover, abnormal positive threshold voltage (VTH) shifts under negative bias stress are turned into negative VTH shifts, and off-state breakdown characteristics is improved as well. A modeling work using physics-based TCAD shows reduced surface depletion effect after the surface passivation. The results demonstrate that high-quality ALD-Al2O3 surface passivation is an effective method to improve electrical properties of the bottom-gate β-Ga2O3 FET and its device applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Crystallization Speed in Ge-Rich PCM Cells as a Function of Process and
           Programming Conditions

    • Authors: E. Gomiero;G. Samanni;J. Jasse;C. Jahan;O. Weber;R. Berthelon;R. Ranica;L. Favennec;V. Caubet;D. Ristoiu;J. P. Reynard;L. Clement;P. Zuliani;R. Annunziata;F. Arnaud;
      Pages: 517 - 521
      Abstract: Quenching-time characterization is the way to measure the speed of chalcogenide material to transform from the amorphous (RESET) state to the crystalline (SET) one after application of a proper programming pulse. It is here proposed to study the impact of process and programming conditions on cell performances, highlighting possible composition variation, and modifications of the physical dimension of the PCM active volume (the dome).
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Highly Reliable Inference System of Neural Networks Using Gated Schottky

    • Authors: Suhwan Lim;Dongseok Kwon;Jai-Ho Eum;Sung-Tae Lee;Jong-Ho Bae;Hyeongsu Kim;Chul-Heung Kim;Byung-Gook Park;Jong-Ho Lee;
      Pages: 522 - 528
      Abstract: An inference system using gated Schottky diode (GSD) is proposed for highly reliable hardware-based neural networks (HNNs). We explain the characteristics of the GSD and present circuits that take into account the characteristics of the device. The reverse current of the GSD, which is the synaptic current, is saturated with respect to input voltage, which results in immunity of input and output noise and overcoming the IR drop problem in metal wire. In order to take advantages of this saturated I-V characteristics, pulse-width modulation (PWM) of input data instead of amplitude modulation is proposed. In addition, by applying identical pulses to the bottom gate, the synaptic current of the GSD increases linearly, which makes it easy to transfer the calculated weights to the conductance of GSDs. By considering these characteristics, electronic circuits for PWM, current sum, and activation function are designed. Through SPICE simulation, we evaluate the inference accuracy of a 2-layer neural network. The classification accuracy rate of 100 images of MNIST test sets is 94% accuracy obtained with software.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Skyrmion-Induced Memristive Magnetic Tunnel Junction for Ternary Neural

    • Authors: Biao Pan;Deming Zhang;Xueying Zhang;Haotian Wang;Jinyu Bai;Jianlei Yang;Youguang Zhang;Wang Kang;Weisheng Zhao;
      Pages: 529 - 533
      Abstract: Novel skyrmion-magnetic tunnel junction (SK-MTJ) devices were investigated for the first time to implement the ternary neural networks (TNN). In the SK-MTJ, an extra magnetoresistance state beyond binary parallel and anti-parallel MTJ states was achieved by forming a skyrmion vortex structure in the free layer. Based on the SK-MTJ, we propose a synaptic architecture with bit-cell design of +1, 0, and -1 to replace the full precision floating point arithmetic with equivalent bit-wise multiplication operation. To explore the feasibility of the SK-MTJ-based synaptic devices for TNN application, circuitlevel simulations for image recognition task were conducted. The recognition rate can reach up to 99% with 5% device variation and an average power consumption of 29.23 μW.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $C-V$+ +Characteristics+of+InAsSb-Based+nBn+Infrared+Detectors+With+N-+and+P-Type+Barrier+Layers+Through+Numerical+Modeling&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Andreu&;Ilya+Prigozhin;Enrico+Bellotti;">Understanding the $C-V$ Characteristics of InAsSb-Based nBn Infrared
           Detectors With N- and P-Type Barrier Layers Through Numerical Modeling

    • Authors: Andreu Glasmann;Ilya Prigozhin;Enrico Bellotti;
      Pages: 534 - 543
      Abstract: Capacitance-voltage (C-V) profiling is a useful technique for accurate and non-destructive determination of carrier concentrations in semiconductor materials. Recently, this measurement has been applied to the infrared barrier detector to determine the doping densities of the absorber and contact layers. This paper provides three contributions to the development of barrier detectors. First, we develop a physics-based semi-analytical model for computing the C-V characteristics derived from metal-oxide-semiconductor and heterojunction device physics and show that it is in agreement with results obtained from drift-diffusion simulations. Second, we assess the possibility of using the developed model to determine not only the absorber and contact doping densities, but also the doping density and thickness of the barrier layer. Lastly, we use the same drift-diffusion methodology to conduct a comprehensive parametric study of the C-V profile for a variety of absorber n-type doping densities, barrier N- and P-type doping densities, barrier thicknesses, and contact layer n-type doping densities. We also offer an extensive discussion of the role of the various device parameters on shaping the C-V profile. While this paper uses the InAsSb and AlAsSb material system, the analysis can be extended to other materials used to implement barrier devices, such as HgCdTe or superlattices.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effects of Crystallinity on the Electrical Characteristics of
           Counter-Doped Polycrystalline Germanium Thin-Film Transistor via
           Continuous-Wave Laser Crystallization

    • Authors: Yi-Shao Li;Chun-Yi Wu;Chan-Yu Liao;Jun-Dao Luo;Kai-Chi Chuang;Wei-Shuo Li;Huang-Chung Cheng;
      Pages: 544 - 550
      Abstract: The crystallinity of polycrystalline germanium (poly-Ge) films were demonstrated through continuous-wave laser crystallization (CLC) with Gaussian-distribution beam profile. The different grain sizes of CLC poly-Ge were observed in their three crystallization regions, which were 2 μm, 680 nm, and 90 nm for the central, transition, and edge regions, respectively. Furthermore, the relation between crystallinity and carrier types in these three regions of counter-doped CLC poly-Ge films were investigated. In the central and transition regions, the CLC poly-Ge films with relatively low hole concentration were easily converted to n-type poly-Ge films through a counter-doping process. In contrast, the edge region with poor crystallinity exhibited p-type behavior due to high defect-generated hole concentration. According to these material properties of counter-doped CLC poly-Ge films, the corresponding transfer characteristics of p-channel poly-Ge thin-film transistor for three crystallization regions were further investigated. Subsequently, high-performance p-channel poly-Ge thin-film transistors in the central region exhibited a superior field-effect mobility of 792.2 cm2/V-s.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • 2-Bit/Cell Operation of Hf0.5Zr0.5O2 Based FeFET Memory Devices for NAND

    • Authors: Binjian Zeng;Min Liao;Qiangxiang Peng;Wenwu Xiao;Jiajia Liao;Shuaizhi Zheng;Yichun Zhou;
      Pages: 551 - 556
      Abstract: The multilevel memory performances of ferroelectric field effect transistor (FeFET) with Hf0.5Zr0.5O2 (HZO) ferroelectric thin film are investigated. First, similar retention characteristics are observed for intermediate and saturated polarization states of HZO ferroelectric thin film, which enables memories for multi-bit data storage. And then, 2-bit/cell operation of HZO-based FeFET is demonstrated utilizing two NAND architecture compatible write schemes of varying program pulse amplitude and width. Low cycle-to-cycle variability, long retention to extrapolation of 10 years at 85°C, and endurance of 500 cycles are achieved for the both schemes. Moreover, the mechanism for multilevel memory operations of the FeFET is illustrated based on the polarization switching dynamics of HZO ferroelectric thin film.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Enhancement of the Luminance Uniformity in Large-Size Organic
           Light-Emitting Devices Based on In–Ga–Zn–O Thin-Film Transistors by
           Using a New Compensation Method

    • Authors: Hong Jae Shin;Tae Whan Kim;
      Pages: 557 - 560
      Abstract: The variations in the threshold voltage and the mobility of In-Ga-Zn-O thin-film transistors (TFTs) were significantly compensated by the proposed compensation method. The luminance difference at each pixel in the large-size organic light-emitting devices (OLEDs) was dramatically decreased less than 10% due to the stich mural and the applied data voltage difference at low gray scale level. Luminance uniformities of up to 99% were achieved for all gray levels of the OLEDs by using the external circuit and optical compensation with angle calibration.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • High Current Output Hydrogenated Diamond Triple-Gate MOSFETs

    • Authors: Jiangwei Liu;Hirotaka Ohsato;Bo Da;Yasuo Koide;
      Pages: 561 - 565
      Abstract: Planar-type and novel triple-gate fin-type hydrogenated diamond (H-diamond) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated on a single-crystalline diamond substrate. The ratio between the height of the lateral side and the width of planar side for each fin of the triple-gate MOSFETs was as high as 1.45. The leakage current densities at an electrical field strength of -1.5 MV cm-1 for both the planar-type and triple-gate fin-type MOSFETs were around 10-6 A cm-2. Both MOSFETs operated well with on/off ratios as high as 1010. The current output maximum normalized by the gate width of the triple-gate H-diamond MOSFET was -271.3 mA mm-1, almost double that of the planar-type MOSFET. The results of this paper are expected to pave the way towards the fabrication of high current out and downscaled H-diamond MOSFETs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Fully Printed Ultra-Thin Charge Amplifier for On-Skin Biosignal

    • Authors: Mika-Matti Laurila;Hiroyuki Matsui;Rei Shiwaku;Mikko Peltokangas;Jarmo Verho;Karem Lozano Montero;Tomohito Sekine;Antti Vehkaoja;Niku Oksala;Shizuo Tokito;Matti Mäntysalo;
      Pages: 566 - 574
      Abstract: In this contribution, we propose a fully printed charge amplifier for on-skin biosignal measurements. The amplifier is fabricated on an ultra-thin parylene substrate and consists of organic transistors, integrated bias and feedback resistors, and a feedback capacitor. The fabrication process utilizes inkjet-printed Ag ink for source, drain, gate, and capacitor electrode metallization as well as for the interconnects between the amplifier elements. Dispensed polystyrene, 2,7-dihexyl-dithieno[2,3-d;2',3'-d']benzo[1,2-b;4,5-b']dithiophene (PS:DTBDT-C6), is used as the transistor channel material, dispensed poly(3-hexylthiophene) (P3HT) as the high-resistivity material for the printed resistors, and parylene as the capacitor dielectric. A pass band optimized for pulse-wave measurement (60 mHz to 36 Hz) is achieved with a maximum charge amplification of 1.6 V/nC. To demonstrate the potential of the proposed printed amplifier, a radial arterial pulsewave signal recorded with a printed piezoelectric poly(vinylidenefluoride-co-trifluoroethylene) (PVDF-TrFE) sensor was fed to it and the output was analyzed to quantify the similarity of the pulse-wave features calculated from the original signal and the amplifier output. The amplified signal contains all the essential features of a pulse wave, such as both systolic waves, the dicrotic notch, and diastolic wave, which enable the accurate derivation of the clinically relevant indices utilized in the evaluation of vascular health.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Multi-Level Memory Comprising Only Amorphous Oxide Thin Film Transistors

    • Authors: Jongbin Kim;Seung-Hyuck Lee;Hoon-Ju Chung;Seung-Woo Lee;
      Pages: 575 - 580
      Abstract: A multi-level memory circuit with only amorphous oxide thin-film transistors (Ox-TFTs) is proposed. The proposed circuit comprises two Ox-TFTs and a capacitor. The proposed multi-level memory can modulate threshold voltage freely depending on programming voltages. Low leakage current of Ox-TFT enables the proposed circuit to operate as a memory. We measured transfer characteristics of the proposed circuit and investigated the threshold voltage shift by a simple capacitance model. We found that the proposed memory cell can be used as a multi-level memory.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Dynamic Control of AlGaN/GaN HEMT Characteristics by Implementation of a
           p-GaN Body-Diode-Based Back-Gate

    • Authors: Isra Mahaboob;Michael Yakimov;Kasey Hogan;Emma Rocco;Sean Tozier;F. Shahedipour-Sandvik;
      Pages: 581 - 588
      Abstract: We report on the implementation of dynamic body-bias technique to improve the performance of AlGaN/GaN high electron mobility transistors (HEMTs) with the successful integration of body-diode. In this configuration, p-GaN body-diode-based back-gate control is used to shift the threshold voltage and dynamically modulate the ON/OFF characteristics of a normally-ON AlGaN/GaN HEMT. A fourth back-gate terminal is connected to the p-GaN layer to control the depletion width of the body-diode, which in turn modulates the 2-D electron gas (2DEG) density. A positive/negative shift in the threshold voltage is measured by increasing/decreasing the depletion width below the channel. A positive back-gate bias application in the ON-state is shown to increase the 2DEG current density resulting in higher ON-current. The application of a negative back-gate bias is shown to be effective in the positive shift of the threshold voltage, in reducing the 2DEG channel current and in increasing the OFF-state break-down voltage. We have experimentally demonstrated enhanced effect of body-diode-based back-gate control in shifting the threshold voltage of a normally-ON HEMT toward normally-OFF mode. The optimum back-gate voltage range which can be applied during both ON and OFF states has been experimentally determined.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impact of the Stacking Order of HfO x and AlO x Dielectric Films on RRAM
           Switching Mechanisms to Behave Digital Resistive Switching and Synaptic

    • Authors: Kai-Chi Chuang;Chi-Yan Chu;He-Xin Zhang;Jun-Dao Luo;Wei-Shuo Li;Yi-Shao Li;Huang-Chung Cheng;
      Pages: 589 - 595
      Abstract: Resistive random access memory (RRAM) devices with analog resistive switching are expected to be beneficial for neuromorphic applications, and consecutive voltage sweeps or pulses can be applied to change the device conductance and behave synaptic characteristics. In this paper, RRAM devices with a reverse stacking order of 6-nm-thick HfOx and 2-nm-thick AlOx dielectric films were fabricated. The device with TiN/Ti/AlOx/HfOx/TiN stacked layers exhibited digital resistive switching, while the other device with TiN/Ti/HfOx/AlOx/TiN stacked layers could demonstrate synaptic characteristics that were analog set and reset processes under consecutive positive and negative voltage sweeps or a train of potentiation and depression pulses. Moreover, this device could also implement synaptic learning rules, spike-timing-dependent plasticity (STDP). Varying temperature measurements and linear fittings of the measured data were conducted to analyze current conduction mechanisms. As a result, the variation of resistive switching behavior between these two devices is attributed to the varying effectiveness of the oxygen scavenging ability of the Ti layer when put into contact with either AlOx or HfOx. Moreover, AlOx functioned as a diffusion limiting layer (DLL) in the device with TiN/Ti/HfOx/AlOx/TiN stacked layers, and gradual modulation of the production and annihilation of oxygen vacancies is the cause of synaptic characteristics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • High Performance Ga2O3 Metal-Oxide-Semiconductor Field-Effect Transistors
           on an AlN/Si Substrate

    • Authors: Dian Lei;Kaizhen Han;Ying Wu;Zhihong Liu;Xiao Gong;
      Pages: 596 - 600
      Abstract: We propose and demonstrate Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) on a high thermal conductivity AlN/Si substrate to improve the heat dissipation capability and keep their cost-effectiveness. Owing to the optimized source/drain contact and Al2O3/Ga2O3 interface, a drain current of 580 mA/mm and peak intrinsic transconductance Gm,int of 35.5 mS/mm were achieved, which are among the highest for all the reported top-gate Ga2O3 MOSFETs. A peak mobility of 82.9 cm2/V·s, a high saturation velocity vsat of 1.1 × 107 cm/s, and a low interface trap density of 1.1 × 1012 cm-2eV-1 are also obtained. Pulse measurement reveals the good heat dissipation capability of the AlN/Si substrate. A three terminal off-state breakdown voltage Vbr of 118 V, a small specific on resistance Ron,sp of 1.44 mΩ·cm2, and power figure-of-merit of 9.7 MW/cm2 are achieved in a device with LGD of 1.14 gym. These excellent results indicate the great potential of Ga2O3 MOSFETs on AlN/Si substrate for future power electronics applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A New Dual-Direction SCR With High Holding Voltage and Low Dynamic
           Resistance for 5 V Application

    • Authors: Kyoung-Il Do;Byung-Seok Lee;Yong-Seo Koo;
      Pages: 601 - 605
      Abstract: Dual-directional silicon-controlled rectifiers (DDSCRs), which provide both positive and negative electrostatic discharge (ESD) surge paths, are ESD protection devices with an excellent area efficiency. However, DDSCRs have a low holding voltage for use in 5 V-class applications, with a relatively high on-state resistance because of the elongated ESD surge path compared to unidirectional SCRs. In this paper, we propose a novel DDSCR with a higher holding voltage and a better ESD tolerance than conventional low-triggering DDSCRs (LTDDSCRs), realized by operating two additional parasitic bipolar transistors. The proposed ESD protection device was developed through a 0.18-μm CMOS process, and a timeline pulse system was used to verify its properties. The measurement results show that the proposed ESD protection device exhibits an improved tolerance and a high holding voltage and is expected to be reliable in 5 V-class applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • TCAD Analysis of the Four-Terminal Poly-Si TFTs on Suppression Mechanisms
           of the DC and AC Hot-Carrier Degradation

    • Authors: Ting Gao;Mingxiang Wang;Huaisheng Wang;Dongli Zhang;
      Pages: 606 - 612
      Abstract: Four-terminal poly-Si thin-film transistors (TFTs), with a counter-doped body terminal connected to the floating channel, can suppress both dc and dynamic hot-carrier (HC) degradation of TFTs. With 3-D TCAD simulation, we clarify the underlying mechanisms of the suppression effect and analyze its dependence on the position and width of the body terminal. Under dc HC condition, a wider body terminal or that closer to the drain collects more holes generated from impact ionization in the drain depletion region and suppresses the parasitic bipolar junction transistor effect, subsequently reduces the kink current more effectively. Under dynamic HC condition, the body terminal injects holes at the end of the falling time of the gate pulse, partially removes the non-equilibrium state, significantly relieves the transient maximum electric field in the drain depletion region, thus suppresses the dynamic HC degradation. A wider body terminal can inject more holes and the holes injected by that closer to the drain diffuse to drain depletion region first, thus suppress the dynamic HC degradation better.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • First Demonstration of Short-Circuit Capability for a 1.2 kV SiC

    • Authors: Masataka Okawa;Ruito Aiba;Taiga Kanamori;Yusuke Kobayashi;Shinsuke Harada;Hiroshi Yano;Noriyuki Iwamuro;
      Pages: 613 - 620
      Abstract: In this paper, the authors report a unique short circuit failure mechanism of a 1.2 kV silicon carbide (SiC) SBD-wall-integrated trench MOSFET (SWITCH-MOS), using numerical simulations and experimental validation. When the Schottky barrier height in the SWITCH-MOS was set at 1.20 eV, the short-circuit withstand time was roughly half that of a conventional SiC trench MOSFET. This is because, in the SWITCH-MOS, the thermionic-field emission electrons passing through the embedded SBD continue flowing into the high electric field in the n- drift region, even after the gate is turned off. This causes heat generation in the device, resulting in thermal runaway. Using a novel methodology for improving the short-circuit capability, it was confirmed that metal with a high Schottky barrier height of 1.75 eV can significantly improve the SWITCH-MOS short-circuit capability, making it comparable to that of conventional SiC trench MOSFETs, and suggesting SWITCH-MOS devices may be superior power devices for use in high frequency inverters.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Tunnel Field-Effect Transistor With Segmented Channel

    • Authors: Jaesoo Park;Changhwan Shin;
      Pages: 621 - 625
      Abstract: A tunnel field-effect transistor with segmented channels (Seg-TFET) on a corrugated substrate is proposed. The Seg-TFET takes advantage of using three stripes and the selective contact configuration to define the direction of current, and thereby its device performance can be improved. Furthermore, the process flow of the Seg-TFET demonstrates a substantiation of the new device structure. Consequently, its current flow is simply defined by adjusting the appropriate contact configuration at metal-zero-level without any additional front-end-of-line process.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Atomistic Study of Lateral Charge Diffusion Degradation During
           Program/Erase Cycling in 3-D NAND Flash Memory

    • Authors: Jixuan Wu;Jiezhi Chen;Xiangwei Jiang;
      Pages: 626 - 631
      Abstract: Impacts of lateral charge diffusion on the retention characteristics of charge-trapping (CT) 3-D NAND flash memory are comprehensively studied in this paper. Atomistic study through ab initio calculation is carried out to understand the correlations between P/E stress induced shallow trap generations and pre-existing traps in Si3N4. It is shown that more shallow traps will be generated with a combination of electron/hole injections and free hydrogen (H) during P/E cycling. Our results strongly suggest that process optimizations to control free H in Si3N4 CT layer could be a key point for robust retention characteristics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • High-Performance Amorphous Zinc–Tin–Oxide Thin-Film Transistors With
           Low Tin Concentration

    • Authors: Shufeng Weng;Rongsheng Chen;Wei Zhong;Sunbin Deng;Guijun Li;Fion Sze Yan Yeung;Linfeng Lan;Zhijian Chen;Hoi-Sing Kwok;
      Pages: 632 - 637
      Abstract: In this paper, we present thin-film transistors (TFTs) with a zinc-tin-oxide (ZTO) layer achieved through magnetron co-sputtering. Amorphous ZTO TFTs with an Sn concentration of 2.49%, 6.95%, 7.11%, 11.95%, and 16.47% were fabricated, to investigate the effect of low-doped Sn. With a doping of 2.49% Sn, the electrical characteristics of TFTs can be obviously improved. After annealing at 440 °C, the optimal TFTs displayed a field-effect mobility of 8.71 cm2/V·s, a high Ion/off ratio of over 108, a subthreshold swing of 0.17 V/decade, and a turn-on voltage of -0.4 V, even with an Sn concentration of only 11.95%. Meanwhile, the shift of turn-on voltage under negative gate bias stress was only -0.4 V.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Test System for Thin Film Transistor Parameter Extraction in Active Matrix

    • Authors: Sanil Daniel;Aswathi Nair;Sanjiv Sambandan;
      Pages: 638 - 644
      Abstract: Thin film transistor (TFT) active matrix backplanes are used in large area electronic systems, such as displays and image sensors. With backplanes being fabricated on wearable and flexible substrates, the possibilities of operational faults in backplanes have increased. These faults could either be hard faults, such as line opens or shorts or could be softer faults, such as time dependent variations in the TFT transfer characteristics. Real time diagnosis of these faults require built-in-self-test systems. While many such systems have been demonstrated to diagnose hard faults, an easily realizable system to identify soft faults, such as variations in transistor transconductance remain an open challenge. In this paper, we discuss a system that extracts the transconductance by charging and then discharging the pixel capacitor at various gate voltages for an active matrix liquid crystal display backplane. This permits a plot of the time averaged current versus the gate voltage from which the spatial variation of transconductance can be extracted. The details of the design are discussed and a proof of concept with a 3×4 amorphous silicon backplane is demonstrated.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effects of Gate Stack Composition and Thickness in 2-D Negative
           Capacitance FETs

    • Authors: Yuh-Chen Lin;Felicia McGuire;Steven Noyce;Nicholas Williams;Zhihui Cheng;Joseph Andrews;Aaron D. Franklin;
      Pages: 645 - 649
      Abstract: Negative capacitance (NC) field-effect transistors (FETs) with 2-D semiconducting channels have become increasingly attractive due to their ability to produce sub-60 mV/dec switching behavior in a physically scalable device. However, it has yet to be determined how gate control, including threshold voltage, of 2-D NC-FETs is impacted by gate dielectric composition, along with dielectric and ferroelectric layer thicknesses. Here, we show the threshold voltage shifts positively under increasing ferroelectric thickness and negatively with increasing dielectric thickness. This shifting behavior is observed in devices without an interfacial metal layer between the ferroelectric hafnium zirconium oxide (HfZrO2 or HZO) and dielectric. Because the interface between the ferroelectric and dielectric is critical in driving NC behavior, we also study 2-D NC-FETs with 4 nm HZO paired with different dielectrics. These results reveal that the HZO/Al2O3 interface is more favorable than either the HZO/ZrO2 or HZO/HfO2 interfaces. Finally, the impact of an interfacial metal layer is discussed by comparing the 2-D NC-FET performance of similar devices with and without this layer.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Incorporating Resistance Into the Transition From Field Emission to Space
           Charge Limited Emission With Collisions

    • Authors: Samuel D. Dynako;Adam M. Darr;Allen L. Garner;
      Pages: 650 - 654
      Abstract: Field emitters and microplasmas often use series resistors to mitigate the rapid increase in current density that reduces device stability. This paper investigates the impact of external resistance on the transition of electron emission mechanism as a function of applied voltage Vapp, gap distance D, and electron mobility μ. For low μ (high gas pressure), the circuit transitions from Fowler-Nordheim (FN) to space charge limited emission by Mott-Gurney (MG) and Child-Langmuir (CL) before reaching Ohm's law (OL). At higher μ, a triple point arises where the asymptotic solutions for FN, MG, and CL intersect. This triple point is uniquely defined by D, μ, or gap voltage Vg while also defining a specific gap impedance Ztp. When R ≤ Ztp, the electron emission transitions from FN to MG to CL to OL with increasing Vapp while MG and CL are bypassed at higher R. For a given R, increasing the applied voltage or emission current causes the gap to appear as a short.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A High Performance Operational Amplifier Using Coplanar Dual Gate a-IGZO

    • Authors: Abidur Rahaman;Yuanfeng Chen;Md. Mehedi Hasan;Jin Jang;
      Pages: 655 - 661
      Abstract: We fabricate an operational amplifier (op-amp) composed with the coplanar amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The circuit consisted of 19-TFTs and designed on a glass substrate in both dual gate (DG) and single gate (SG) structure for performance evaluation. Having the yield of a total voltage gain (Av) of 23.5 dB, a cutoff frequency (fc) of 500 kHz, a unit gain frequency (fug) of 2.37 MHz, gain-bandwidth product (GBWP) of 7500 kHz, a slew rate (up/down) of (2.1/1.2) V/μs, and a phase margin (PM) of 102° at a supply voltage of ±10 V, the fabricated DG TFT op-amp demonstrates good performance among all a-IGZO-based literature.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Barrier Inhomogeneity of Schottky Diode on Nonpolar AlN Grown by Physical
           Vapor Transport

    • Authors: Qin Zhou;Honglei Wu;Hui Li;Xi Tang;Zuoyan Qin;Dan Dong;Yan Lin;Chengjin Lu;Ran Qiu;Ruisheng Zheng;Jiannong Wang;Baikui Li;
      Pages: 662 - 667
      Abstract: An aluminum nitride (AlN) Schottky barrier diode (SBD) was fabricated on a nonpolar AlN crystal grown on tungsten substrate by physical vapor transport. The Ni/Au-AlN SBD features a low ideality factor n of 3.3 and an effective Schottky barrier height (SBH) of 1.05 eV at room temperature. The ideality factor n decreases and the effective SBH increases at high temperatures. The temperature dependences of n and SBH were explained using an inhomogeneous model. A mean SBH of 2.105 eV was obtained for the Ni-AlN Schottky junction from the inhomogeneity analysis of the current-voltage characteristics. An equation in which the parameters have explicit physical meanings in thermionic emission theory is proposed to describe the current-voltage characteristics of inhomogeneous SBDs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Efficient Atomistic Simulation of Heterostructure Field-Effect Transistors

    • Authors: Yongsoo Ahn;Mincheol Shin;
      Pages: 668 - 676
      Abstract: In this paper, atomistic-level quantum mechanical simulations are performed for nanoscale field-effect transistors (FETs) with lateral or vertical heterojunction, within the non-equilibrium Green's function formalism. For efficient simulation of such heterostructure FETs, a novel approach is developed where the Green's functions are calculated by complementarily using the two algorithms of the recursive Green's function and the R -matrix. The R -matrix algorithm is extended to seamlessly combine the two methods on the open system and an algorithm for the electron correlation function based on the extended R -matrix algorithm is also developed. The proposed method significantly reduces simulation time, making rigorous atomistic simulations of heterojunction FETs possible. As an application, device simulations are performed for the germanane/InSe vertical tunneling FET (VTFET) modeled through the first-principles density functional theory. Our simulation results reveal that the germanane/InSe VTFET is a promising candidate for future low power applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $p^{{+}}/{n}$+ +Collector+Structure&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Kui&;Weijia+Zhang;Wai+Tung+Ng;">Novel Low Turn-Off Loss Trench-Gate FS-IGBT With a Hybrid $p^{{+}}/{n}$
           Collector Structure

    • Authors: Kui Ma;Weijia Zhang;Wai Tung Ng;
      Pages: 677 - 681
      Abstract: A trench-gate field stop insulated gate bipolar transistor (TFS-IGBT) with a novel hybrid p+/n collector structure is proposed to enhance the trade-off relationship between the on-state voltage drop (Von) and the turn-off energy loss (Eoff). The proposed hybrid collector structure consists of a p+/n layer between the p± collector and the field stop layer. During turn-on, the p+ regions in the hybrid p+/n layer provide high carrier injection efficiency. During turn-off transient, the n-regions in the hybrid p+/n collector provide fast carrier extraction paths for holes. 2-D numerical simulations comparing a conventional TFS-IGBT, an injection efficiency controlled IGBT with the proposed hybrid p+/n collector TFS-IGBT (HC-IGBT) having similar device structures show that for a 1.2 kV rating and with Von at 1.5 V, the HC-IGBT has an advantage in Eoff reduction by 69% and 22%, respectively. Finally, backside mask alignment is not needed for fabricating the proposed hybrid p+/n collector structure.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive
           Field Plate

    • Authors: Junji Cheng;Shiying Wu;Weizhen Chen;Haimeng Huang;Bo Yi;
      Pages: 682 - 689
      Abstract: An improved trench lateral double-diffused MOSFET (T-LDMOS) is proposed. It has a quasi vertical super junction (QVSJ) drift region and adopts a resistive field plate (RFP) to help QVSJ satisfy charge-balance. The realization of RFP barely complicates the device fabrication, but it motivates QVSJ to significantly improve the relationship between breakdown voltage (BV) and specific on-state resistance (RON,SP). The simulation results show that compared with the conventional QVSJ T-LDMOS, the proposed one gains the RON,SP reduced by about 79% under the same BV requirement of about 500 V. It therefore presents an excellent figure of merit (FOM) (FOM = BV2/RON,SP, Baliga's FOM) up to 29.8 MW/cm2, which is superior to the prior art and exhibits a bright prospect of saving energy.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Precise Extraction of Dynamic R dson Under High Frequency and High Voltage
           by a Double-Diode-Isolation Method

    • Authors: Jianming Lei;Rui Wang;Guo Yang;Jin Wang;Fulong Jiang;Dunjun Chen;Hai Lu;Rong Zhang;Youdou Zheng;
      Pages: 690 - 695
      Abstract: A double-diode-isolation method with low parasitic capacitance devices and reverse clamping is proposed to accurately extract the high-frequency and high-voltage dynamic on-resistance (Rdson) of AlGaN/GaN high electron mobility transistor (HEMT) power devices. The response time required for the drain voltage to drop back to the on-voltage of this testing circuit can reach 100 ns, and the forward voltage drop of the isolation diode is monitored in real time using low-voltage probes. A low value constant current source is built to power the testing circuit at only several mA to avoid additional self-heating effect. With these improvements, we can obtain a test frequency of more than 1 MHz, a test voltage of more than 600 V and an accuracy of higher than 97.8% for the extraction of dynamic Rdson.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Top-Bottom Gate Coupling Effect on Low Frequency Noise in a Schottky
           Junction Gated Silicon Nanowire Field-Effect Transistor

    • Authors: Xi Chen;Si Chen;Paul Solomon;Zhen Zhang;
      Pages: 696 - 700
      Abstract: In this letter, strong low frequency noise (LFN) reduction is observed when the buried oxide (BOX)/silicon interface of a Schottky junction gated silicon nanowire field-effect transistor (SJGFET) is depleted by a substrate bias. Such LFN reduction is mainly attributed to the dramatic reduction in Coulomb scattering when carriers are pushed away from the interface. The BOX/silicon interface depletion can also be achieved by sidewall Schottky junction gates in a narrow channel SJGFET, leading to an optimal LFN performance without the need of any substrate bias.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Design of Power- and Variability-Aware Nonvolatile RRAM Cell Using
           Memristor as a Memory Element

    • Authors: Soumitra Pal;Subhankar Bose;Wing-Hung Ki;Aminul Islam;
      Pages: 701 - 709
      Abstract: A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM (RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile memory elements, CNFETs are employed as high-performance switches. The proposed cell is capable of implementing bit-interleaving architecture and various error correction coding (ECC) schemes can be applied to mitigate soft-errors. The 3T2R cell has been compared with the standard 6T SRAM (S6T) and 2T2R cells. At a supply voltage of 2 V, the 3T2R cell exhibits 7.24× shorter write delay (TWA) and 2.89× lower variability in TWA than that of 2T2R. Moreover, it exhibits 5.08 × /4.33× lower variability in TRA and 1.46 × 107 × /2.07× lower hold power (HPWR) dissipation than that of S6T/ 2T2R at VDD = 2 V. In addition, it exhibits tolerance to variations in Vth of memristor while being immune to resistance-state drift and random telegraph noise (RTN)-induced instabilities during the read operation. The vastly superior characteristics of CNFET devices over MOSFETs, in combination with memristor technology, leads to such appreciable improvement in design metrics of the proposed design.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

    • Authors: Songnan Guo;Xing Bi Chen;
      Pages: 710 - 716
      Abstract: A silicon-on-insulator (SOI) p-channel lateral double-diffused MOSFET (p-LDMOS), conducting not only holes but also electrons, is proposed and investigated by TCAD simulations. Its most important advantage is the greatly improved relationship between the breakdown voltage (BV) and the specific on-resistance (Ron,sp). The improvement is mainly attributed to two aspects. First, many holes can accumulate in the p-drift region in the on-state, which provides a low-resistance path for hole conduction. Second, a paralleled n-LDMOS is, meanwhile, automatically triggered to form a new path for electrons. Electrons have higher mobility than holes; thus, the device performance is further improved. Based on a simulation comparison with the previous p-LDMOS at the same BV of 300 V, the Ron,sp of the proposed p-LDMOS decreased by 78% and the figure of merit (FOM) increased approximately 3.4 times. Moreover, the proposed device still has the conventional three-terminal style, and its fabrication process is compatible with CMOS technology.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor
           for Large Size High-Resolution Liquid Crystal Displays

    • Authors: Qungang Ma;Haihong Wang;Liufei Zhou;Jiali Fan;Congwei Liao;Xiaojun Guo;Shengdong Zhang;
      Pages: 717 - 721
      Abstract: Amorphous IGZO thin-film transistors (TFTs) in an etch stop layer (ESL) structure was processed on 2500 mm × 2200 mm size substrate. The fabricated devices exhibit enhancement mode characteristics, and excellent uniformity over large area. The presented good operational stabilities under both positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) tests can well meet the requirements for pixel switching. However, considering even threshold voltage shift under long term positive bias stress might affect proper operation of the gate driver on array (GOA), a design with a pulse gating scheme is proposed, consisting of 13 TFTs and 1 capacitor, to avoid long term continuous bias stressing of the TFT. With the proposed GOA design, a 32-inch QUHD (7680×4320) highresolution liquid crystal display (LCD) panel with a 7 mm wide bezel is achieved. The reliability of the GOA circuit is well proved through standard aging tests.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ultra-Low Level Light Detection Based on the Poisson Statistics Algorithm
           and a Double Time Windows Technique With Silicon Photomultiplier

    • Authors: Jian Liu;Lei Dai;Baozhou Zhang;Kun Liang;Ru Yang;Dejun Han;
      Pages: 722 - 727
      Abstract: In this paper, we present a method to detect ultra-low level light ranging from several mean photoelectrons (MPEs) down to 10-5 MPEs. It is based on the Poisson statistics algorithm and a double time windows technique with a silicon photomultiplier (SiPM) and a field programmable gate array (FPGA). It measures the mean incident photoelectron number of pulsed light with zero peak statistics of the Poisson distribution to reduce the influence of the correlation noises and the dark count rate (DCR) fluctuation. The linear measurement ranges from ~10-4 MPEs to ~10 MPEs (i.e., ~97 dB) were demonstrated with double 35-ns time windows at room temperature. Its upper detection limit is determined by the availability for the zero peak counts of the Poisson distribution, and the lower detection limit is mainly determined by the DCR of the SiPM. By narrowing the time window to ~550 ps or decreasing the operating temperature of SiPM to -30 °C, the detection limit can be further decreased to ~10-5 MPEs. This method, with capability to record the arrival time of incident photons, demonstrated an instrument response function (IRF) of ~214.9 ps (FWHM), showing its compatibility to the time correlated photon counting (TCPC) technique and the time of flight (TOF) measurement.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Area-Efficient and Snapback-Free SOI LIGBT With L-Shaped Extraction Path

    • Authors: Tao Tian;Yu-Feng Guo;Jia-Fei Yao;Jun Zhang;Kemeng Yang;Man Li;
      Pages: 728 - 734
      Abstract: A novel area-efficient snapback-free silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time in this paper. The device features an N+ anode, three separated P+ anodes, and a P-buried layer (PBL) in the N-buffer of the anode region. The N-buffer between all these components above forms a 3-D L-shaped extraction path. The L-shaped extraction path not only makes the device area-efficient but also increases the anode distributed resistance (RSA). Therefore, the snapback effect could be suppressed, and the tradeoff between the on-state voltage (Von) and turn-off energy (Eoff) is improved effectively. Simulation results show that the proposed device eliminates the snapback effect with 63% and 77% reduction of the anode region area compared with the segmented trenches in the anode region (STA) LIGBT and the separated shorted anode (SSA) LIGBT, respectively. At the same Von, the LEP LIGBT reduces the turn-off time (toff) and Eoff by 40% and 28%, respectively, compared with the STA LIGBT. Moreover, at the same Eoff, the LEP LIGBT reduces Von by 17%, compared with the SSA LIGBT.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Optimization of Zn2SiO4 Anode Structure for Deep Ultraviolet Generation
           With Carbon Nanotube Emitters

    • Authors: Sung Tae Yoo;Hye In Lee;Kyu Chang Park;
      Pages: 735 - 739
      Abstract: Ultraviolet (UV) light is applied to various industrial and medical devices. In particular, deep UV light with short wavelengths could minimize the damage to human cells when it is used to virus and bacterial sterilization. We optimized the Zn2SiO4 anode structure to improve deep UV light generation with a carbon nanotube (CNT) cold cathode based electron beam (C-beam) pumping. Annealing at 1000 °C and 400 mTorr produces anode with the highest deep UV intensity. Using a 100-nm SiOx layer between Zn2SiO4 and quartz substrate, the intensity of deep UV light at a wavelength of 226 nm was increased by 1.8 times.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Toward Reliable Multi-Level Operation in RRAM Arrays: Improving
           Post-Algorithm Stability and Assessing Endurance/Data Retention

    • Authors: Eduardo Pérez;Cristian Zambelli;Mamathamba Kalishettyhalli Mahadevaiah;Piero Olivo;Christian Wenger;
      Pages: 740 - 747
      Abstract: Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 °C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $mu$+ m+InP+DHBT+Technology+With+400-GHz++${f}_{{T}}$+ +and++${f}_{text{MAX}}$+ +and+4.5-V+BVCE0+for+High+Speed+and+High+Frequency+Integrated+Circuits&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=V.&;M.+Riet;C.+Mismer;R.+Hersent;F.+Jorge;A.+Konczykowska;J.-Y.+Dupuy;">0.7- $mu$ m InP DHBT Technology With 400-GHz ${f}_{{T}}$ and
           ${f}_{text{MAX}}$ and 4.5-V BVCE0 for High Speed and High Frequency
           Integrated Circuits

    • Authors: V. Nodjiadjim;M. Riet;C. Mismer;R. Hersent;F. Jorge;A. Konczykowska;J.-Y. Dupuy;
      Pages: 748 - 752
      Abstract: We report the performances of a 0.7-μm InP/GaInAs DHBT developed in III-V Lab demonstrating both fT and f MAX of 400 GHz as well as a high fabrication yield and homogeneity on a 3-inch wafer. This technology is used for the fabrication of a very high speed 2:1 multiplexing selector operating up to 212-Gb/s, establishing a speed record. A 5.4-Vpp 100-Gb/s distributed differential selector-driver, as well as a 4.3-Vpp 64-GBd 8-pulse-amplitude-modulation (PAM) (192 Gb/s) high-speed power digital-to-analog converter (DAC) were also realized in this technology.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Foreword Special Section on Flexible Electronics From the Selected
           Extended Papers Presented at 2018 IFETC

    • Authors: Gaozhi Xiao;Samar K. Saha;Taya Chu;Ye Tao;Arokia Nathan;
      Pages: 753 - 755
      Abstract: This Special Section is devoted to the research and development activities of all areas of flexible electronics science and technology. We have a selected number of high impact technical papers presented at the first IEEE International Flexible Electronics Technology Conference (IFETC) in 2018 for publication in J-EDS. The first IFETC was held in Ottawa, Ontario, Canada from the 7th to 9th August, 2018. The conference was financially sponsored by the IEEE Council on RFID, and technically sponsored by the National Research Council Canada, IEEE Electron Device Society, and the IEEE Instrumentation and Measurement Society. The conference was dedicated to the advances in flexible electronics in all areas of science and technology, and provided an opportunity for scientists, researchers, engineers, developers, and users in the field to share, discuss, and witness new concepts and ideas. A wide spectrum of academic research results was presented, with potential applications in current industrial technology and new application driven domains.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Printing Contractive Silver Conductive Inks Using Interface Interactions
           to Overcome Dewetting

    • Authors: Kevin Ton;Ta-Ya Chu;Zhiyi Zhang;Ye Tao;
      Pages: 756 - 760
      Abstract: Surface energy incompatibility between ink and substrate is a significant obstacle for inkjet printing of electronic components, causing printed lines to dewet and break apart. In this paper, it was demonstrated that smooth, continuous silver lines could be printed via control of ink-substrate interactions, despite the tendency of the ink to dewet from the substrate. The silver lines were printed using dropon-demand inkjet printing of silver nanoparticle ink onto non-crosslinked SU-8 coated polyethylene terephthalate (PET). The lines were subsequently heated to control dewetting and cause contraction from 60 μm to 14 μm. The SU-8 film underneath the silver line was dissolved and redistributed to form a ridged concave structure that prevented the lines from bulging and breaking apart. Additionally, photonic sintering was used to achieve low resistivity of 0.06 μΩm for the narrow printed lines.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Adopting Hybrid Integrated Flexible Electronics in Products:
           Case—Personal Activity Meter

    • Authors: Terho Kololuoma;Mikko Keränen;Timo Kurkela;Tuomas Happonen;Marko Korkalainen;Minna Kehusmaa;Lúcia Gomes;Aida Branco;Sami Ihme;Carlos Pinheiro;Ilkka Kaisto;Ashley Colley;Kari Rönkä;
      Pages: 761 - 768
      Abstract: In this case study, the possibilities of hybrid integration of printed and flexible electronics in combination with conventional electronic components to create new types of product concepts is demonstrated. The final result is a personal activity meter demonstrator, which is realized by utilizing various flexible electronics manufacturing and integration techniques. Roll-to-roll printing was used to print the electronic backplane as well as co-planar electrochromic (EC) display. A pick-and-place assembled microcontroller unit and accelerometer, together with passive components, provided the brains for the system. Injection molding was then utilized to create a structural electronics system including an EC display. To validate the feasibility and scalability of the processes used, 100 pieces of the personal activity meter were fabricated. Modeling with continuum computational fluid dynamics and numerical heat transfer, using the high-performance finite volume method, showed that high filling pressure and shear-stress are the key factors causing broken devices. The stability of the devices in harsh environmental conditions as well as in bending seem to be slightly improved in the over molded samples.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Flexible Green Perovskite Light Emitting Diodes

    • Authors: Giuseppe Cantarella;Sudhir Kumar;Christian Vogt;Stefan Knobelspies;Alain Takabayashi;Jakub Jagielski;Niko Münzenrieder;Alwin Daus;Luisa Petti;Giovanni A. Salvatore;Paolo Lugli;Chih-Jen Shih;Gerhard Tröster;
      Pages: 769 - 775
      Abstract: Flexible perovskite light-emitting diodes (LEDs) have attracted increasing interest to realize ultrathin, light weight, highly conformable, and nonfragile vivid displays. Solution-processed lead halide perovskite offers numerous distinctive characteristics, such as pure emission color, tunable bandgaps, and low fabrication cost. In this paper, green perovskite LEDs (PeLEDs) are fabricated on 50-μm thick polyimide substrates. Using colloidal 2-D formamidinium lead bromide perovskite emitter, the PeLEDs show a high current efficiency (ηCE) of 5.3 cd A-1 with a peak emission at 529 ± 1 nm and a narrow width of 22.8 nm. The resultant green emission shows color saturation> 95%, in the Rec. 2020 standard gamut area. To demonstrate mechanical flexibility, the device functionality is tested by dynamic bending experiments down to 10 mm for up to 5000 cycles, resulting in device lifetime over 36 h in a glove box and a drop of ηCE and external quantum efficiency (ïext) as low as 15% and 18%, respectively. For the selective activation of multiple PeLEDs, 7×7 passive arrays on rigid and flexible substrates are demonstrated. Moreover, preliminary results of active matrices show the compatibility of PeLEDs with oxide-based thin-film transistors (TFTs) for display applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of
           Large-Area Electronics

    • Authors: Joachim N. Burghartz;Golzar Alavi;Björn Albrecht;Thomas Deuble;Mourad Elsobky;Saleh Ferwana;Christine Harendt;Yigit Mahsereci;Harald Richter;Zili Yu;
      Pages: 776 - 783
      Abstract: This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Controlling the Surface Properties of an Inkjet-Printed Reactive Oxygen
           Species Scavenger for Flexible Bioelectronics Applications in Neural

    • Authors: Ashkan Shafiee;Elham Ghadiri;Muhamad Mat Salleh;Muhammad Yahaya;Anthony Atala;
      Pages: 784 - 791
      Abstract: Neural damage caused by reactive oxygen species (ROS) can trigger several acute or chronic conditions, such as Alzheimer's, Huntington's, and Parkinson's diseases. However, ROS scavengers hold great promise for enabling DNA repair in neurons; damaged cells using ROS-scavenging agents may be able to recover their functionality and resilience. Moreover, in bioelectronics for neural applications, thin films with adequate properties are crucial for the proper performance of an electronic device. Therefore, precise and reliable deposition techniques that can control the characteristics of thin films are imperative when fabricating bioelectronic devices integrated with cellular systems. To that end, inkjet printing is a promising method with unique advantages, such as computer-assisted protocols and efficient consumption of materials. We report the printing of a functional electronic material that exhibits ROS scavenging behavior (Manganese [III] 5, 10, 15, 20-tetra [4-pyridyl]-21H, 23H-porphine chloride tetrakis [methochloride]) using a modified inkjet printer. Different printed pattern schemes that were designed based on the amount of overlap among sequential droplets were used to tune the surface morphology of the inkjet-printed thin films with a wide range of roughness (8.84-41.20 nm). Furthermore, post-printing processes (such as plasma treatment) were used to optimize surface energy. Such inkjet printing methods of functional electronic materials that can simultaneously be used as ROS scavengers, would advance bioelectronics applications in neural studies.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A 6-TFT Charge-Transfer Self-Compensating Pixel Circuit for Flexible

    • Authors: Qing Li;Czang-Ho Lee;Mohsen Asad;William S. Wong;Manoj Sachdev;
      Pages: 792 - 800
      Abstract: In this paper, a self-compensating 6 thin-film transistor (TFT) pixel circuit with special layout considerations has been proposed to mitigate the impact of the electrical instability of hydrogenated amorphous silicon TFTs as well as applied mechanical strain. The proposed pixel circuit has been fabricated onto flexible polyethylene naphthalate (PEN) substrate and the measurement results demonstrated less than ±3% variation of its output current after an accelerated 24-h stress test under flat, tensile strain, and compressive strain conditions. In addition, the proposed pixel circuit only required a pair of signals to operate, which reduced the complexity on external IC drivers.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Robust Oxide Thin-Film Transistors With Embedded CNT Buried Layer for
           Stretchable Electronics

    • Authors: Md Mehedi Hasan;Mohammad Masum Billah;Xiuling Li;Jin Jang;
      Pages: 801 - 807
      Abstract: We report the impact of carbon nanotube (CNT) buried layer in the middle of 7 μm polyimide (PI) substrate on the electrical performance of amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) by repetitive mechanical stretching. TFT arrays on 3 mm × 3 mm PI layers were attached on 40 μm polydimethylsiloxane (PDMS) substrate by double-sided PI tape. A negative threshold voltage shift (ΔVTh(V)) of -3 V has been found under 70% mechanical stretching for the TFTs on the conventional PI substrate, whereas the TFTs with CNT layer inside PI substrate exhibited robust TFT performance. The fabricated oxide TFTs reported here with CNT inside PI substrate shows field effect mobility (μFE) ~ 14 cm2/V·s at pristine state, and changed
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Introduction to the Special Section on the 2018 IEEE S3S Conference

    • Authors: Ali Khakifirooz;Nobuyuki Sugii;
      Pages: 808 - 809
      Abstract: This special section of the IEEE Journal of Electron Devices Society is dedicated to select papers presented at the 2018 IEEE S3S Conference, which was held Oct. 15–18, 2018 in Burlingame, CA, USA. The papers were selected based their technical merits and relevance to the Journal and with the feedback from the Technical Committee of the conference and session chairs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • 28-nm FDSOI nMOSFET RF Figures of Merits and Parasitic Elements Extraction
           at Cryogenic Temperature Down to 77 K

    • Authors: Babak Kazemi Esfeh;Valeriya Kilchytska;N. Planes;M. Haond;Denis Flandre;Jean-Pierre Raskin;
      Pages: 810 - 816
      Abstract: This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency (fT) and maximum oscillation frequency (fmax), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of fT and fmax by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Process Dependence of Soft Errors Induced by Alpha Particles, Heavy Ions,
           and High Energy Neutrons on Flip Flops in FDSOI

    • Authors: Mitsunori Ebara;Kodai Yamada;Kentaro Kojima;Jun Furuta;Kazutoshi Kobayashi;
      Pages: 817 - 824
      Abstract: Soft-error tolerance depending on threshold voltage of transistors was evaluated by α -particle, heavy-ion, and neutron irradiation. Three chips were fabricated, one embeds low-threshold general-purpose (GP) transistors and the others embed high-threshold low-power (LP) transistors in a 65 nm fully depleted silicon on insulator (FDSOI) process. There were a few errors on LPDFFs (DFFs with LP transistors). Error probability (EP) of LPDFFs was 99.88% smaller than that of GPDFFs (DFFs with GP transistors) by α particles. Average cross sections (CSs) of LPDFFs by heavy ions were 50% smaller than those of GPDFFs. Average soft-error rates (SERs) of LPDFFs by neutrons were 68% smaller than those of GPDFFs. 3-D device simulations revealed that CSs of the LP and GP transistors are changed by fitting methods using the work function of the gate material and doping concentration of the substrate under the BOX layer. The difference is due to the number of carriers in diffusion and silicon thickness of the raised layer above drain and source terminals.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • The Study of Plasma Induced Damage on 65-nm Silicon on Thin BOX Transistor

    • Authors: Yoshiki Yamamoto;Kazuhiko Segi;Shibun Tsuda;Hideki Makiyama;Takumi Hasegawa;Keiichi Maekawa;Hiroki Shinkawata;Tomohiro Yamashita;
      Pages: 825 - 828
      Abstract: This paper reports new findings about the plasma-induced damage on silicon on thin buried oxide (BOX) transistor. The plasma charge collected by source or drain causes Vth shift, which depends on BOX thickness. In addition, the observation was made that the plasma charge collected by an antenna which is connected to the gate electrode has the same degradation effect as an antenna with the same size but being connected to drain or source. The mechanism of this phenomenon is investigated with various test structures.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impact of Self-Heating Effect on Transistor Characterization and
           Reliability Issues in Sub-10 nm Technology Nodes

    • Authors: Yi Zhao;Yiming Qu;
      Pages: 829 - 836
      Abstract: FinFET and fully depleted silicon-on-insulator (FDSOI) structures could further improve transistor's performance and, however, also introduce some new problems, especially the increasingly severer self-heating effect (SHE). In this paper, by utilizing the ultra-fast sub-1 ns measurement technique, I-V characteristics of FinFETs and FDSOI devices at different switch speeds are obtained. Furthermore, dynamic SHE phenomena as well as the time-resolved channel temperature change during transistor's switch on and off are able to be experimentally observed. And, more accurate device parameters like ballistic transport efficiency are extracted by the ultra-fast measurements. Moreover, it is experimentally confirmed that several nanoseconds are required to heat up the channel of transistors by the direct electrical characterization and, therefore, in sub-10 nm devices, SHE might be alleviated under high frequency/speed operations.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A 4Kx8 Innovative Fuse OTP on 22-nm FD-SOI

    • Authors: Shine C. Chung;Wen-Kuang Fang;Fang-Hua Chen;
      Pages: 837 - 845
      Abstract: A 4Kx8 innovative fuse (I-fuse)1 one-time programmable (OTP) based on a 1R1T metal-gate fuse with a strictly electromigration program mode has a 0.744 μm2 cell and 111 μm × 411 μm macro on 22-nm FD-SOI. This macro can be programmed at 1.0-1.45 V with
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Dynamic Coupling Effect in Z2-FET and Its Application for

    • Authors: J. Liu;X. Y. Cao;B. R. Lu;Y. F. Chen;A. Zaslavsky;S. Cristoloveanu;J. Wan;
      Pages: 846 - 854
      Abstract: In this paper, the application of the zero subthreshold swing and zero impact ionization FET (Z2-FET) for photodetection is studied with TCAD simulation. Dynamic coupling effect is utilized to form carrier injection barriers in the partially depleted silicon-on-insulator (PD-SOI) film. Photoelectron accumulation at the front gate interface lowers the hole injection barrier and modulates the turn-on voltage. The light-triggering threshold of the device can be tuned by the front gate voltage, which controls the injection barrier height. We explore two operation modes suited to different applications, and demonstrate the operation of a one-transistor active pixel sensor array. Unlike other image sensors that utilize only one type of carrier, the Z2-FET photodetector uses photo-generated holes to induce high electron currents through internal amplification, leading to a high sensitivity of up to 1.8 × 105 e-/(lux·s).
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • On the Characterization and Separation of Trapping and Ferroelectric
           Behavior in HfZrO FET

    • Authors: Md. Nur Kutubul Alam;Ben Kaczer;Lars-Åke Ragnarsson;Mihaela Popovici;Gerhard Rzepa;Naoto Horiguchi;Marc Heyns;Jan Van Houdt;
      Pages: 855 - 862
      Abstract: N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of ID-VG hysteresis, the hysteresis versus subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the FE layer responsible for charge trapping during device operation is characterized. Transient ID-VG measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High
           Density 3-D SoC Applications

    • Authors: W. Schwarzenbach;B.-Y. Nguyen;L. Ecarnot;S. Loubriat;M. Detard;E. Cela;C. Bertrand-Giuliani;G. Chabanne;C. Maddalon;N. Daval;C. Maleville;
      Pages: 863 - 868
      Abstract: Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™ development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX materials developments are reported, including 4-nm SOI and 15-nm BOX layers, with performances close to production-grade (SOI layer thickness variation at wafer and device scale, SOI layer defect density). To support 3-D sequential integration, layer transfer at low temperature (below 500 °C) with SmartCut is demonstrated, on the path to a cost effective option. Best in class-equivalent to Epi bulk-SOI layers thickness variability at device scale is demonstrated. Excellent SOI and BOX layers thickness uniformities at wafer level are also highlighted while layer integrity from surface to crystalline defect density point of view are already compliant with development grade requirements.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for
           Monolithic 3-D Integration of InGaAs MOSFETs

    • Authors: Sanghyeon Kim;Seong Kwang Kim;Sanghoon Shin;Jae-Hoon Han;Dae-Myeong Geum;Jae-Phil Shim;Subin Lee;Hansung Kim;Gunwu Ju;Jin Dong Song;M. A. Alam;Hyung-Jun Kim;
      Pages: 869 - 877
      Abstract: Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%-30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ultimate Monolithic-3D Integration With 2D Materials: Rationale,
           Prospects, and Challenges

    • Authors: Junkai Jiang;Kamyar Parto;Wei Cao;Kaustav Banerjee;
      Pages: 878 - 887
      Abstract: As a possible pathway to continue Moore's law indefinitely into the future as well as unprecedented beyond-Moore heterogeneous integration, we examine the prospects of building monolithic 3D integrated circuits (M3D-IC) with atomically-thin or 2D van der Waals materials in terms of overcoming the major drawbacks of current 3D-ICs, including low process thermal budget, inter-tier signal delay, chip-overheating, and inter-tier electrical interference problems. Our holistic evaluation includes consideration of the electrical performance, thermal issues, and electromagnetic interference as well as attention to the synthesis methods necessary for low-temperature transfer-free 2D materials growth in M3D fabrication. Both in-plane and out-of-plane heat-dissipation in 3D-ICs made with 2D materials are evaluated and compared with those of bulk materials. Electrostatic and high-frequency electric-field simulations are conducted to assess the screening effect by graphene and effect of scaling down the inter-layer dielectric (ILD) thickness. Our analysis reveals for the first time that the 2D-based M3D integration can offer>ten-folds higher integration density compared with through-silicon-via (TSV)-based 3D integration, and>150% integration density improvement with respect to conventional M3D integration. Therefore, 2D materials provide a significantly better platform, with respect to bulk materials (such as Si, Ge, GaN), for realizing ultra-high-density M3D-ICs of ultimate thinness for next-generation electronics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of the Scalability of Emerging Nanotube Junctionless FETs
           Using an Intrinsic Pocket

    • Authors: Aakash Kumar Jain;Jaspreet Singh;Mamidala Jagadesh Kumar;
      Pages: 888 - 896
      Abstract: The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio (ION/IOFF) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive (ION/IOFF) ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive (ION/IOFF) ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show t-at incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced (ION/IOFF) ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Abnormal Positive Bias Temperature Instability Induced by Dipole Doped
           N-Type MOSCAP

    • Authors: Fu-Yuan Jin;Ting-Chang Chang;Chien-Yu Lin;Jih-Chien Liao;Fong-Min Ciou;Yu-Shan Lin;Wei-Chun Hung;Kai-Chun Chang;Yun-Hsuan Lin;Yen-Cheng Chang;Ting-Tzu Kuo;
      Pages: 897 - 901
      Abstract: This work performs fundamental electrical measurements and a positive bias temperature instability (PBTI) test on an N-type metal oxide semiconductor capacitor (MOSCAP) and a La2O3 dipole-doped N-type MOSCAP. Experimental results show that the dipole-doped N-type MOSCAP has a lower threshold voltage and gate current leakage than do the N-type MOSCAP. After positive bias stress, an abnormal gate current leakage decrease appears in both dipole-doped and normal N-type MOSCAPs under short term stress. Analysis of capacitance and gate current measurements indicate that electron trapping and defect generation cause the change in gate current after positive bias stress. Generally, devices with higher gate leakage have more severe degradation after PBTI. However, in this work, the dipole sample shows a lower initial gate current leakage but higher gate current degradation than those found in the control sample after PBTI. Based on the electrical measurement results and the energy band simulation, a conduction model was proposed to explain the abnormal PBTI of the dipole-doped N-type MOSCAP.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Method for Obtaining the Real Off-State Breakdown Voltage of AlGaN/GaN
           MIS-HEMTs in On-Wafer Tests by Optimizing Protective Layer

    • Authors: Sheng Gao;Quanbin Zhou;Xianhui Li;Zijing Xie;Hong Wang;
      Pages: 902 - 907
      Abstract: We demonstrate a method for testing the real off-state breakdown voltage (VBD) of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMTs) in on-wafer tests. The method prevents the arcing over air at high voltage by depositing the protective layer between the pad electrodes of source and drain. The influence of materials and thickness of the protective layer on the high voltage tests of MIS-HEMTs were investigated. We found that it is helpful to obtain the real VBD of the devices by increasing the thickness of the protective layer and selecting a material with a higher critical breakdown field strength. The real VBD of the device with a gate-to-drain spacing of 25 μm is 1164 V when 1.5 μm SiO2 is deposited as the protective layer, which is 141% higher than that of the value tested in air.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Characterization of High-Performance InGaAs QW-MOSFETs With Reliable
           Bi-Layer HfOxNy Gate Stack

    • Authors: Su-Keun Eom;Min-Woo Kong;Ho-Young Cha;Kwang-Seok Seo;
      Pages: 908 - 913
      Abstract: In this work, we report high-performance InGaAs quantum-well MOSFETs with optimized bi-layer high-k gate dielectrics incorporating high-quality plasma-assisted atomic -layer-deposited (PA-ALD) HfOxNy interfacial layer (IL). With more than 1 nm IL deposition to passivate the InGaAs surface, excellent sub-threshold characteristics (SSmin = 68 mV/dec) were achieved through the proposed gate stack technology. We performed positive-bias-temperature-instability (PBTI) measure -ments in order to ensure a reliable gate operation. The proposed bi-layer III-V gate stack achieved the excellent value of maximum gate overdrive voltage (VOV, max) of 0.49 V with CET = 1.04 nm. The proposed gate stack has a great potential for III-V MOSFET technology to low power logic applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • ${beta}$+ -Ga2O3+Nano-Membrane+Field+Effect+Transistors+on+a+High+Thermal+Conductivity+Diamond+Substrate&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jinhyun&;Sami+Alajlouni;Marko+J.+Tadjer;James+C.+Culbertson;Hagyoul+Bae;Mengwei+Si;Hong+Zhou;Peter+A.+Bermel;Ali+Shakouri;Peide+D.+Ye;">High Performance ${beta}$ -Ga2O3 Nano-Membrane Field Effect Transistors on
           a High Thermal Conductivity Diamond Substrate

    • Authors: Jinhyun Noh;Sami Alajlouni;Marko J. Tadjer;James C. Culbertson;Hagyoul Bae;Mengwei Si;Hong Zhou;Peter A. Bermel;Ali Shakouri;Peide D. Ye;
      Pages: 914 - 918
      Abstract: To suppress severe self-heating under high power density, we herein demonstrate top-gate nano-membrane β-gallium oxide (β-Ga2O3) field effect transistors on a high thermal conductivity diamond substrate. The devices exhibit enhanced performance, with a record high maximum drain current of 980 mA/mm for top-gate β-Ga2O3 field effect transistors and 60% less temperature increase from reduced self-heating, compared to the device on a sapphire substrate operating under identical power density. With improved heat dissipation, β-Ga2O3 field effect transistors on a diamond substrate are validated using an ultrafast high-resolution thermoreflectance imaging technique, Raman thermography, and thermal simulations.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • UTBB-Based Single Transistor Image Sensor of Submicron Pixel Using Back
           Gate Modulation

    • Authors: Liqiao Liu;Xiaoyan Liu;Gang Du;
      Pages: 919 - 924
      Abstract: Image sensor has developed for decades. Now, submicron photo sensor device with high performance is required. In this work, a UTBB (ultra-thin body and box) based single transistor image sensor has been investigated. The light collection and signal readout are accomplished by a single transistor, so the pixel of the UTBB image sensor can shrink down to the submicron. The main parameters impacting the performance of the UTBB image sensor such as back voltage, the thickness of the BOX, well doping concentration and well depth are investigated. Besides, the UTBB image sensor can achieve multi-resolution to adapt to different requirements. The performance of the UTBB image sensor is evaluated by TCAD simulations.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Experimental Investigations Into Temperature and Current Dependent
           On-State Resistance Behaviors of 1.2 kV SiC MOSFETs

    • Authors: Kang Hong;Xiao-Yuan Chen;Yu Chen;Ming-Shun Zhang;Jia-Lei Wang;Shan Jiang;Zhou Pang;Han-Mei Yang;Ning Xue;Hua-Yu Gou;Lei Zeng;
      Pages: 925 - 930
      Abstract: Performance characterization for long-time operation of cryogenic SiC MOSFETs remains as a challenge that requires further investigation. This paper presents experimental investigations into temperature and current dependent on-state resistance behaviors of state-of-the-art 1.2 kV SiC MOSFETs from various well-known semiconductor manufacturers. In view of engineering applications, two fitted double-exponential functions are introduced to visually depict the interactions among the on-state resistance, junction temperature and drain current instead of considering the combined effects of electron mobility and ionized dopant concentration inside cryogenic SiC MOSFETs. Optimal operating temperature and current ranges are subsequently extracted to characterize the cryogenic operation performance, and thus to explore some operating and designing guidelines of cryogenic SiC MOSFETs and SiC-based power conversions at 77 K.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Stable Operation of AlGaN/GaN HEMTs for 25 h at 400°C in air

    • Authors: Saleh Kargarrazi;Ananth Saran Yalamarthy;Peter F. Satterthwaite;Scott William Blankenberg;Caitlin Chapin;Debbie G. Senesky;
      Pages: 931 - 935
      Abstract: Extreme environments such as the Venus atmosphere are among the emerging applications that demand electronics that can withstand high-temperature oxidizing conditions. While wide-bandgap technologies for integrated electronics have been developed so far, they either suffer from gate oxide and threshold voltage (Vth) degradation over temperature, large power supply requirements, or intrinsic base current. In this letter, AlGaN/GaN high electron mobility transistors (HEMTs) are suggested as an alternative platform for integrated sensors and analog circuits in extreme environments in oxidizing air atmosphere over a wide temperature range from 22°C to 400°C. An optimal biasing region, with a peak of transconductance (gm,peak) at -2.3 V with a negligible shift over the temperature range was observed. Moreover, remarkably low Vth variation of 0.9% was observed, enabling the design of analog circuits that can operate over the entire temperature range. Finally, the operation of the devices at 400°C and 500°C over 25 hours was experimentally studied, demonstrating the stability of the DC characteristics after the 5 hours of burn-in, at 400°C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • An Novel Thin Layer SOI Carrier-Stored Trench LIGBT With Enhanced Emitter

    • Authors: Bo Yi;Jia Lin;Jiayu Wu;Moufu Kong;Xingbi Chen;
      Pages: 936 - 942
      Abstract: An novel thin layer SOI carrier-stored (CS) trench lateral insulated gate bipolar transistor (TLIGBT) with diode-clamped P-shield layer is proposed. The potential of the P-shield layer is clamped by two series-connected diodes. Therefore, the reverse voltage is sustained by the P-shield/Ndrift junction rather than the P-base/CS junction during the off-state. Thus, the doping concentration of the carrier-stored layer (Ncs) can be significantly improved without compromising the breakdown voltage. Hence, an ultra-low on-state voltage drop (Von) can be obtained. Besides, the two series-connected diodes clamp the drain-to-source voltage of the intrinsic n-MOS in the TLIGBT, which leads to an ultra-low saturation current and improves the short-circuit withstand capability. The simulation results indicate that the turn-off loss (Eoff) at Von = 1.37 V is reduced by 28.8% and 21% compared with those of the conventional carrier-stored LIGBT A and LIGBT B, respectively. Moreover, the saturation current density is reduced by over 53.3% and the short circuit withstand time is improved by more than 2 times than those of the conventional and state-of-the-arts.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Single-Crystalline Si-CMOS Circuit Fabrication on Polyethylene
           Terephthalate Substrate by Meniscus Force-Mediated Layer Transfer

    • Authors: Ryutatsu Mizukami;Tomonori Yamashita;Hiroaki Hanafusa;Seiichiro Higashi;
      Pages: 943 - 948
      Abstract: Single-crystalline silicon (sc-Si) complementary metal-oxide-semiconductor (CMOS) circuits were fabricated on a polyethylene terephthalate (PET) substrate using meniscus force-mediated layer transfer. The introduction of a two-step tapered SiO2 structure formed using low-dose and high-energy pillar shaping ion implantation (I/I) and self-limited SiO2 pillar etching were crucial for obtaining a high transfer yield of 99.86% and simultaneous transfer of both n- and p-channel sc-Si islands to the PET substrate. The fabricated MOS field-effect transistors exhibited a high field effect mobility of 603 cm2 V-1 s-1 (n) and 172 cm2 V-1 s-1 (p), respectively. The CMOS inverters exhibited clear input/output characteristics under a supply voltage of 2.0 V, and high-speed operation of a five-stage ring oscillator (RO) with an operating frequency of 14.6 MHz was realized. Moreover, the oscillation frequency of the RO transferred onto the PET was 3.5 times that of the non-transferred RO owing to the reduction in the parasitic capacitance.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Design of the RRAM-Based Polymorphic Look-Up Table Scheme

    • Authors: Xiaole Cui;Xiang Li;Miaomiao Zhang;Xiaoxin Cui;
      Pages: 949 - 953
      Abstract: The polymorphic gates are the circuit cells that deliver different functions with the different external input, supply voltage or temperature. It is an effective method to resist the reverse engineering attacks, for the attackers cannot distinguish the correct function based on the netlist of the circuit. The researchers have found out that the RRAM based Look-Up Table (LUT) has higher performance and less area, comparing with the CMOS based counterparts. However, the attackers can tell the functions of the previous proposed RRAM based LUTs by measuring the resistance states of the RRAM cells. This work proposes an RRAM based polymorphic gate, which implements 16 basic logic functions with 8 RRAM cells in 4 working cycles. Furthermore, the multi-input LUT scheme is proposed based on the polymorphic gate. It is difficult for the attackers to distinguish the circuit function, because the function of the LUT is determined by the applied voltages and the resistance states of the RRAM devices, and the n-input LUT circuit is implemented with the constant area regardless of the number of inputs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Comparative Study of the Curing Effects of Local and Global Thermal
           Annealing on a FinFET

    • Authors: Jun-Young Park;Geon-Beom Lee;Yang-Kyu Choi;
      Pages: 954 - 958
      Abstract: Recently, localized thermal annealing has been spotlighted as an effective method to cure aged devices. The degraded gate oxide can be successfully cured by local annealing, which utilizes Joule heat inherently generated in the device. But, despite this advantage, there has been no study comparing the curing effects with various other annealing methods. In this study, the curing effects of local annealing and a conventional global annealing method applied to SOI FinFETs are compared. The measured electrical characteristics are discussed to evaluate the damage curing with respect to curing level and variability.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Self-Limited Low-Temperature Trimming and Fully Silicided S/D for
           Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless
           Nanosheet Transistors

    • Authors: Chris Chun-Chih Chung;Chun-Ming Ko;Tien-Sheng Chao;
      Pages: 959 - 963
      Abstract: A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and Ioff is drastically reduced (~two orders of magnitude) with increasing trimming cycles. Full silicidation on the source/drain (FUSI-S/D) is performed to improve Ion. Surprisingly, after silicidation, both Ion and μFE shows degradation despite that the series resistance is improved. An ultrathin body junctionless (UTB-JL) device is fabricated to investigate the degradation cause by direct CV measurement on the device, which can give us an insight into the details of the change with the silicidation.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation on Metal–Oxide Graphene Field-Effect Transistors With
           Clamped Geometries

    • Authors: Marco A. Giambra;Christian Benz;Fan Wu;Maximillian Thürmer;Geethu Balachandran;Antonio Benfante;Riccardo Pernice;Himadri Pandey;Muraleetharan Boopathi;Min-Ho Jang;Jong-Hyun Ahn;Salvatore Stivala;Enrico Calandra;Claudio Arnone;Pasquale Cusumano;Alessandro Busacca;Wolfram H. P. Pernice;Romain Danneau;
      Pages: 964 - 968
      Abstract: In this work, we report on the design, fabrication and characterization of Metal-Oxide Graphene Field-effect Transistors (MOGFETs) exploiting novel clamped gate geometries aimed at enhancing the device transconductance. The fabricated devices employ clamped metal contacts also for source and drain, as well as an optimized graphene meandered pattern for source contacting, in order to reduce parasitic resistance. Our experimental results demonstrate that MOGFETs with the proposed structure show improved high frequency performance, in terms of maximum available gain and transition frequency values, as a consequence of the higher equivalent transconductance obtained.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Comprehensive Study of Stacked Nanosheet-Type Channel Based on
           Junctionless Gate-All-Around Thin-Film Transistors

    • Authors: Yu-Ru Lin;Yu-Hsien Lin;Yi-Yun Yang;Yung-Chun Wu;
      Pages: 969 - 972
      Abstract: As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and compared the electrical characteristics of single-NS and stacked-NS structures. The performance of the multi-gate and gate-all-around transistors was then further analyzed. The stacked gate-all-around thin-film transistor exhibited superior performance and excellent temperature design flexibility. In brief, the stacked gate-all-around structure for thin-film transistors structure has the potential to overcome the challenges associated with downscaling.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Thermal Analysis of Ultimately-Thinned-and-Transfer-Bonded CMOS on
           Mechanically Flexible Foils

    • Authors: Justine Philippe;Arun Bhaskar;Etienne Okada;Flavie Braud;Jean-François Robillard;François Danneville;Christine Raynaud;Daniel Gloria;Emmanuel Dubois;
      Pages: 973 - 978
      Abstract: Thinned CMOS chips transfer-bonded onto a compliant host substrate remain to date the technology of choice for applications requiring both mechanical flexibility and high frequency operation. However, the use of poorly thermally conductive host substrates raises the problem of thermal management of flexible electronics, a topic poorly addressed in literature. In this letter, we report the analysis of flexible SOI-CMOS chips ultimately-thinned-and-transfer-bonded (UTTB) onto polyimide and copper substrates. While the temperature remains limited to ~68°C on the native silicon substrate or after transfer onto a copper host substrate, infrared thermography reveals temperature peaks of up to 118°C on polyimide. The impact of self-heating in flexible SOI-CMOS is correlated with electrical performance for the three types of substrates. Beyond the property of mechanical flexibility it provides, a copper substrate is shown to slightly strengthen electrostatic integrity while maintaining a thermal landscape close to that of silicon.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Numerical Study of a Thyristor Injection Insulated Gate Bipolar Transistor
           (TI-IGBT) Using P-N-P Collector

    • Authors: Mengxuan Jiang;Yulei Wang;
      Pages: 979 - 983
      Abstract: A new thyristor injection concept is proposed to decrease conductivity modulation effects in an Insulated Gate Bipolar Transistor (TI-IGBT), which adds a floating p-type layer and an n-type layer at the collector side. The additional p-layer and n-layer form a parasitic n-p-n transistor to reduce the hole injection efficiency though the potential difference between the floating p-type layer and the field stop (FS) layer, as well as decrease hole concentration near the collector, turn-OFF fall time and turn-OFF loss. TACD simulations shows, a 24% and a 10% reduction in turn-OFF fall time and turn-OFF loss are respectively obtained in the proposed TI-IGBT with the similar breakdown voltage and threshold voltage compared to a conventional FS-IGBT by the potential difference with the various floating p-layer doping. Therefore, the TI-IGBT offers a competitive option for high power converter applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Dynamic Behavior Improvement of Normally-Off p-GaN High-Electron-Mobility
           Transistor Through a Low-Temperature Microwave Annealing Process

    • Authors: Hsien-Chin Chiu;Chia-Hao Liu;Yi-Sheng Chang;Hsuan-Ling Kao;Rong Xuan;Chih-Wei Hu;Feng-Tso Chien;
      Pages: 984 - 989
      Abstract: The surface morphology optimization of ohmic contacts and the Mg out-diffusion suppression of normally off p-GaN gate high-electron-mobility transistors (HEMTs) continue to be challenges in the power electronics industry in terms of the high-frequency switching efficiency. In this study, better current density and reliable dynamic behaviors of p-GaN gate HEMTs were obtained simultaneously by adopting low-temperature microwave annealing (MWA) for the first time. Moreover, HEMTs fabricated using MWA have a higher ION/IOF ratio and lower gate leakage current than the HEMTs fabricated using rapid thermal annealing. Due to the local heating effect, a direct path for electron flow can be formed between the two-dimensional electron gas and the ohmic metals with low bulges surface. Moreover, the Mg out-diffusion of p-GaN gate layer was also suppressed to maintain good current density and low interface traps.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Modeling of the Variation of Lateral Doping (VLD) Lateral Power Devices
           via 1-D Analysis Using Effective Concentration Profile Concept

    • Authors: Jun Zhang;Yu-Feng Guo;Ke-Meng Yang;Chen-Yang Huang;Fang-Ren Hu;
      Pages: 990 - 996
      Abstract: The VLD technique has introduced for the propose of achieving the ideal surface electric field via a non-uniformly doped drift region. Yet, the ideal doping profile is impossible to be fulfilled in practical thus breaking the optimized lateral breakdown characteristic. In addition, the conventional 2-D methods, due to its complexity, are impractical in both explaining its physical nature and providing designing guidance. In this paper, a simple 1-D methodology based on Effective Concentration Profile (ECP) theory is proposed to provide the physical insight of the VLD technique and quantitatively depict its breakdown characteristic. The VLD-ECP concept indicates that the perfectly even surface electric field can be obtained by adjusting the drift region doping dose equals to the Charge Appointment Line (CAL) so that all the charges in drift region contribute to the vertical depletion, thus the lateral structure being an equivalently P-I-N junction. Considering non-ideal doping profile of commercial devices, a designing optimization criterion is proposed to avoid the undesirable lateral breakdown. The analytical results obtained by the proposed model are found to be sufficiently accurate comparing with TCAD simulation results verifying the veracity and effectiveness of the proposed methodology.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Simulation-Based Model of Randomly Distributed Large-Area Field Electron

    • Authors: Johannes Bieker;Richard G. Forbes;Stefan Wilfert;Helmut F. Schlaak;
      Pages: 997 - 1006
      Abstract: With a large-area field electron emitter (LAFE), it is desirable to choose the spacings of individual emitters in such a way that the LAFE-average emission current density and total current are maximised, when the effects of electrostatic depolarization (mutual screening) are taken into account. This paper uses simulations based on a finite element method to investigate how to do this for a LAFE with randomly distributed emitters. The approach is based on finding the apex field enhancement factor and the specific emission current for an emitter, as a function of the average nearest neighbor spacing between emitters. Using electrostatic simulations based on the finite element method, the influence of neighboring emitters on a reference emitter being placed at the LAFE centre is investigated. Arrays with 25 ideal (identical) conical emitters with rounded tops are studied for different emitter densities and applied macroscopic fields. A theoretical average spacing is derived from the Poisson Point Process Theory. An optimum average spacing, and hence optimum emitter density, can be predicted for each macroscopic field.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded
           RRAM Array

    • Authors: Xiaole Cui;Miaomiao Zhang;Qiujun Lin;Xiaoxin Cui;Anqi Pang;
      Pages: 1007 - 1012
      Abstract: An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (MISR)-based response compactor, and both the n-stage LFSR and MISR are implemented by n + 2 in-array RRAM cells. The proposed LFSR/MISR circuit has better performance than the IMPLY-based counterpart, due to the application of the proposed three-cycle XOR gate and two-cycle shift gate with the in-array RRAM cells. And it is more area efficient comparing with the memristor ratioed logic (MRL)-based counterpart. The proposed n-stage LFSR/MISR circuit is tested by the scan chain method. The test method only has the linear time complexity. For the best of our knowledge, it is the first attempt to design the in-array BIST circuit for the RRAM array.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Snapback-Free and Low Turn-Off Loss Reverse-Conducting SOI-LIGBT With
           Embedded Diode and MOSFET

    • Authors: Jiayu Wu;Haimeng Huang;Bo Yi;Hao Hu;Huan Hu;Xing Bi Chen;
      Pages: 1013 - 1017
      Abstract: A novel snapback-free and low turn-off loss reverse-conducting (RC) SOI-LIGBT is proposed and investigated by numerical simulations. An n-MOSFET (MN2) is embedded in the anode side of the LIGBT to short the P-anode/N-buffer junction during the turn-off transient, thus allowing the LIGBT to be turned off rapidly without excessive tail current. In addition, MN2 enable the LIGBT to conduct the reverse conducting current like the freewheeling diode. In the forward-conducting state, MN2 is turned off, then the proposed LIGBT operates like a conventional one and the snap-back is avoided. The gate electrode of MN2 can be controlled synchronously by the gate signal of the LIGBT which is level-shifted by a p-i-n diode (D1) and processed by an anode-controlling circuit, and therefore, the proposed RC-LIGBT still maintains a three-terminal configuration. D1 and MN2 are embedded in the drift region and anode-side of the LIGBT, respectively, and they can be isolated by deep-oxide trenches. The numerical simulation results reveal that the turn-off loss (Eoff) and reverse recovery charge of the proposed LIGBT is reduced by 58.3% and 38.9%, respectively, compared with the conventional LIGBT combining with antiparallel freewheeling diode.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Capacitive Information-Based Force-Voltage Responsivity Stabilization
           Method for Piezoelectric Touch Panels

    • Authors: Anbiao Huang;Shuo Gao;Yanning Dai;Vasileios Kitsos;Wenbin Tian;Lijun Xu;
      Pages: 1018 - 1025
      Abstract: Piezoelectric force touch panels receive increased attentions in recent years. However, user-induced nonstable force-voltage responsivity limits their successful use in interactive displays. In this work, touch-induced capacitive information is used for estimating contact area and touch angle, which are further employed to interpret user performed force amplitude. A promising result of improving the stability of force-voltage responsivity by 85% is achieved, enhancing user experience and advancing the development of piezoelectric force sensing in interactive displays.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A 4410-ppi Resolution Pixel Circuit for High Luminance Uniformity of
           OLEDoS Microdisplays

    • Authors: Jun-Seok Na;Seong-Kwan Hong;Oh-Kyong Kwon;
      Pages: 1026 - 1032
      Abstract: This paper proposes a pixel circuit with high resolution and high luminance uniformity for organic light emitting diode-on-silicon (OLEDoS) microdisplays. The proposed pixel circuit employs a simple structure that consists of four n-channel MOSFETs and one capacitor, resulting in high resolution. In addition, this circuit compensates for the threshold voltage (Vth) variation of the driving transistor caused by the body effect, which increases the Vth as the source-to-body voltage of the driving transistor increases, thus reducing the emission current deviation, resulting in a high luminance uniformity. Moreover, the proposed pixel circuit extends the data voltage range using the capacitive coupling of the storage capacitance and the parasitic capacitance at the gate node of the driving transistor to precisely control the emission current. To verify the performance of the proposed pixel circuit, a test pattern with an array of the proposed 4T1C pixel circuits was fabricated on a single-crystalline silicon wafer as a backplane using a 110 nm standard CMOS process with 5.5 V high-voltage devices. The proposed pixel circuit occupies a unit sub-pixel area of 5.76μm × 1.92μm, which corresponds to a resolution of 4410 pixels per inch. The measurement results show that the emission current deviation error of the proposed pixel circuit ranges between -1.16% and +1.14%, which is improved from between -45.97% to +45.42% achieved in the conventional current-source type 2T1C pixel circuit, which does not compensate for the Vth variation of the driving transistor. Moreover, the measured data voltage range of the proposed pixel circuit is extended to 1.618 V, which is 8.17 times wider than that of the conventional pixel circuit. Therefore, the proposed pixel circuit is very suitable for high resolution and high luminance uniformity of OLEDoS microdisplays.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of 5-nm-Thick Hf0.5Zr0.5O2 Ferroelectric FinFET Dimensions
           for Sub-60-mV/Decade Subthreshold Slope

    • Authors: Meng-Ju Tsai;Pin-Jui Chen;Dun-Bao Ruan;Fu-Ju Hou;Po-Yang Peng;Liu-Gu Chen;Yung-Chun Wu;
      Pages: 1033 - 1037
      Abstract: In this study, ferroelectric Fin field effect transistors (Fe-FinFET) with 5-nm-thick Hf0.5Zr0.5O2 (HZO) layers on silicon-on-insulator substrates were experimentally demonstrated. These devices had completed dimensions of single channel widths (WCh) from 20 nm to 1000 nm and gate lengths (LG) from 100 nm to 2000 nm. In experimental results, when WCh is smaller than 30 nm, and/or when LG> WCh, this proposed 5-nm-HZO Si Fe-FinFET guarantees SS
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Fault-Tolerant Architecture for Reliable Integrated Gate Drivers

    • Authors: Jongbin Kim;Hoon-Ju Chung;Seung-Woo Lee;
      Pages: 1038 - 1046
      Abstract: This paper proposes fault-tolerant (FT) architecture for integrated gate drivers. It can automatically detect faults in the gate driver caused by external physical stress and then immediately repair them as well. As a result, it can contribute to highly reliable display products. The proposed architecture uses redundant circuit structure with fault detection circuit. The detailed algorithm for the proposed method is presented in this paper. Simulation and measurement results verify that the proposed circuit and its driving algorithm operates successfully. Finally, the display system architecture is also suggested for realization of our FT method.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Nondestructive Evaluation of Multijunction Solar Cells for Matching

    • Authors: Chia-Hua Huang;Hao Lo;Chieh Lo;Chia-Chieh Hsu;Wen-Shiung Lour;
      Pages: 1047 - 1054
      Abstract: Nondestructive methods determining current mismatched ratios (CMMRs) between key subcells in a multijunction solar cell were proposed in view of a compensated concept of subcell's current. Various compensated lights were employed to determine key CMMR of InGaP-InGaAs-Ge related triple-junction (3J) solar cells. When a 405 nm compensated light is used, short-circuit currents of 9.37 mA/cm2 and 10.28 mA/cm2 were determined for the InGaP-subcell and InGaAs-subcell, respectively, resulting in a CMMR of 4.4%. Excellent agreement in evaluated properties was obtained when a 532 nm, a 638 nm, and 808 nm compensated lights were used. A 3J solar cell fabricated with an anti-reflected coating was also evaluated. Measured results reveal that an overall short-circuit current of 13.5 mA/cm2 is still limited by the InGaP-subcell, resulting in a conversion efficiency of 27%. Together with determined short-circuit current of 15.5 mA/cm2 for the InGaAs-subcell, a possible optimum conversion efficiency of 29.11% is expected.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Numerical Analysis of the LDMOS With Side Triangular Field Plate

    • Authors: Jiafei Yao;Yu Deng;Yufeng Guo;Zhenyu Zhang;Jun Zhang;Maolin Zhang;
      Pages: 1055 - 1062
      Abstract: A Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) with side triangular field plate (STFP) is proposed for improving the breakdown voltage (BV) and reducing the specific on-resistance (Ron,sp). The main feature of the novel LDMOS is the STFPs at both ends of the drift region, and they are fabricated into the dielectric pillars. With the introduction of the STFPs, the electric field peaks at the P-well/N-drift and N+/N-drift junctions are reduced effectively. The STFPs together with the dielectric pillars modulate the surface and vertical electric field distributions, which enhances the BV. Meanwhile, the doping concentration of the silicon pillars in the drift region is optimized and thus reduces the Ron,sp. The simulation results indicate that the BV of 379 V and the Ron,sp of 37.3 mΩ·cm2 are achieved by the STFP-LDMOS. The figure of merits (FOM) of the STFP-LDMOS is 2.7 times compared with the conventional LDMOS without STFPs. The STFP-LDMOS demonstrates a great trade-off between the Ron,sp and BV.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Unified Degradation Model of a-InGaZnO TFTs Under Negative Gate Bias
           With or Without an Illumination

    • Authors: Shuai Li;Mingxiang Wang;Dongli Zhang;Huaisheng Wang;Qi Shan;
      Pages: 1063 - 1071
      Abstract: Degradation behaviors of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) under negative bias stress (NBS) and negative bias illumination stress (NBIS) are investigated systematically. In some cases, a two-stage degradation behavior of a-IGZO TFTs is observed under both NBS and NBIS, which begins with a small positive shift of threshold voltage (Vth), and is followed by a large negative Vth shift. There is an intrinsic correlation between the degradations of NBS and NBIS. Quantitatively, both stress gate biases (VG) and temperature dependencies of ΔVth of the two degradations are found to be the same and the recovery processes are also very similar. A unified model of NBS and NBIS is proposed to consistently explain the degradation behaviors of a-IGZO TFTs and their correlation.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Phase Change Memory Cell With Reconfigured Electrode for Lower RESET

    • Authors: Shaolin Zhou;Kezhou Li;Yihan Chen;Shaowei Liao;Honglin Zhang;Mansun Chan;
      Pages: 1072 - 1079
      Abstract: To reduce the reset voltage and thus leakage current of the cross-point architecture of phase change memory (PCM), a type of 1S1R cell hierarchy with reconfigured electrode capping around the phase change material is explored in this paper. The electro-thermal behavior during the RESET phase transition is mimicked using a finite element model. Results indicate that the temperature distribution, potential drop and current density across the active region can be reshaped. Especially, the process of temperature evolution for phase transition is accelerated and thus the PCM cell can be reset under a lower voltage, e.g., from 2.2 V to 1.2 V for our typical configuration with a GST width of 40 nm and heater width of 20 nm. As a result, the lower RESET voltage decreases the leakage current and power consumption, potentially leading to an increased integration level for cross-point PCM.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback
           FET Co-Integrated With CMOS

    • Authors: Min-Woo Kwon;Kyungchul Park;Myung-Hyun Baek;Junil Lee;Byung-Gook Park;
      Pages: 1080 - 1084
      Abstract: We have developed a capacitor-less I&F neuron circuit with a dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET and CMOS in a wafer. By implementing the neuron circuit with FBFET, we can overcome the limits of conventional CMOS, reduce energy consumption, and imitate the biological neuron. The floating body of the FBFET can replace the membrane capacitor that occupies a large area and performs leaky integration of the neuron. Due to the extremely low sub-threshold swing of the FBFET (less than 0.528mv/dc), energy consumption of the neuron is significantly reduced by suppressing sub-threshold current. Finally, we analyzed the fabricated neuron circuit operation, retention time of the integrated charges and energy consumption compare to conventional CMOS neuron circuit.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Operation Scheme of Multi-Layer Neural Networks Using NAND Flash Memory as
           High-Density Synaptic Devices

    • Authors: Sung-Tae Lee;Suhwan Lim;Nag Yong Choi;Jong-Ho Bae;Dongseok Kwon;Byung-Gook Park;Jong-Ho Lee;
      Pages: 1085 - 1093
      Abstract: We propose a designing of multi-layer neural networks using 2D NAND flash memory cell as a high-density and reliable synaptic device. Our operation scheme eliminates the waste of NAND flash cells and allows analogue input values. A 3-layer perceptron network with 40,545 synapses is trained on a MNIST database set using an adaptive weight update method for hardware-based multi-layer neural networks. The conductance response of NAND flash cells is measured and it is shown that the unidirectional conductance response is suitable for implementing multi-layer neural networks using NAND flash memory cells as synaptic devices. Using an online-learning, we obtained higher learning accuracy with NAND synaptic devices compared to that with a memristor-based synapse regardless of weight update methods. Using an adaptive weight update method based on a unidirectional conductance response, we obtained a 94.19% learning accuracy with NAND synaptic devices. This accuracy is comparable to 94.69% obtained by synapses based on the ideal perfect linear device. Therefore, NAND flash memory which is mature technology and has great advantage in cell density can be a promising synaptic device for implementing high-density multi-layer neural networks.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Graphene Nano Sheet Fabrication Using Light

    • Authors: Hongliang Sun;
      Pages: 1094 - 1099
      Abstract: The photochemical-reduction methods exhibit many interesting applications in metal and metal oxide nanoparticles with promising properties such as easy-to-handle, easy-to-inkjet and cost-effective. Using the soluble graphene oxide (GO) as a precursor, graphene production can be achieved via photochemical reduction, paving the way for manufacturing graphene products in controllable microscopic patterns. In this work, I used a photochemical method to obtain reduced graphene oxide (rGO), assisted by strong reducing α-aminoalkyl (α-A*) radicals generated by photoinitiator Irgacure-907. The extent of oxygen reduction can be continually controlled by manipulating light dosage and characterized by quantitative measurements of structure, morphology, chemical composition and electrical conductivity. The high quality of obtained rGO makes this photochemical-reduction based technology ideal for inkjet printing microstructures of graphene, thus achieving desirable conductivity, other physical and chemical properties associated.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • An Insight Into Self-Heating Effects and Its Implications on Hot Carrier
           Degradation for Silicon-Nanotube-Based Double Gate-All-Around (DGAA)

    • Authors: Arun Kumar;P. S. T. N. Srinivas;Pramod Kumar Tiwari;
      Pages: 1100 - 1108
      Abstract: Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ultra-High-Image-Density, Large-Size Organic Light-Emitting Device Panels
           Based on Highly Reliable Gate Driver Circuits Integrated by Using InGaZnO
           Thin-Film Transistors

    • Authors: Hong Jae Shin;Tae Whan Kim;
      Pages: 1109 - 1113
      Abstract: Large-size, organic light-emitting device (OLED) panels based on highly reliable gate driver circuits integrated using InGaZnO thin-film transistors (TFTs) were fabricated to achieve ultra-high image density (UHD). These large-size OLED panels were driven by using a novel gate driver circuit not only for displaying images but also for sensing TFT characteristics for external compensation. Regardless of the negative threshold voltage of the TFTs, the proposed gate driver circuit in OLED panels functioned precisely, resulting from a decrease in the leakage current. The falling time of the circuit is approximately $1.6~{{mu }}text{s}$ , which is fast enough to drive UHD OLED displays at 120 Hz. 120 Hz is most commonly used as the operating voltage because images consisting of 12 frames per second can be quickly shown on the display panel without any image sticking. The reliability tests showed that the lifetime of the proposed integrated gate driver is at least $1 times 10^{5}$ h.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A T-Shaped SOI Tunneling Field-Effect Transistor With Novel Operation

    • Authors: Chenhe Liu;Qinghua Ren;Zhixi Chen;Lantian Zhao;Chang Liu;Qiang Liu;Wenjie Yu;Xinke Liu;Qing-Tai Zhao;
      Pages: 1114 - 1118
      Abstract: We present a novel T-shaped tunneling field-effect transistor (TFET) on Si-on-insulator (SOI). The asymmetric source-drain structure can effectively suppress the ambipolar switching. The on-current ( $text{I}_{mathrm{ on}}$ )/off-current ( $text{I}_{mathrm{ off}}$ ) ratio reaches very high value of $sim 10^{8}$ at $text{V}_{mathrm{ ds}}= - 0.5$ V with a smaller tunneling junction width at the drain. The innovative T-shape design allows integration of both TFET and metal-oxide semiconductor field-effect transistors (MOSFET) operation modes in one structure. Both TFET and MOSFET operation modes are experimentally demonstrated in this device structure, which provide the implementation of the selector function with the single device.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With
           Metal–Interlayer–Semiconductor Source/Drain Contact Structure

    • Authors: Seung-Geun Jung;Hyun-Yong Yu;
      Pages: 1119 - 1124
      Abstract: The impact of random dopant fluctuation (RDF) on n-type Ge junctionless FinFETs (JLFETs) with metal–interlayer-semiconductor (MIS) source/drain (S/D) contact structure is firstly investigated via 3-D technology computer aided design (TCAD) simulations. The estimation and evaluation of standard deviations in threshold voltage (Vth), on-state current (Ion), off-state current (Ioff), subthreshold swing (SS), and drain induced barrier lowering (DIBL) by different Ge nanowire doping concentrations and different heights for RDF effects are performed. The results show a decreasing trend of RDF with lower doping concentration of the device. Furthermore, the influence of MIS S/D on RDF of n-type Ge JLFET is assessed through a comparative analysis between an n-type Ge JLFETs with and without MIS S/D structure. The analysis results estimate that MIS S/D can reduce performance variation to approximately 0.0237 V for ${sigma }~text{V}_{mathrm{ th}}$ , 5.75 $times ,,10^{-5}$ A/ $mu {mathrm{ m}}$ for ${sigma }~text{I}_{mathrm{ on}}$ , 4.30 $times ,,10^{-10}$ A/ $mu {mathrm{ m}}$ for ${sigma }~text{I}_{mathrm{ off}}$ , 0.548 mV/dec for ${sigma }$ SS, and 12.3 mV/V for DIBL, without severe performance degradation of the current nominal values. This estimation gives a significant insight on variability prediction of the 7 nm n-type Ge JLFET d-vice with MIS S/D structure.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Flexible HfO2/Graphene Oxide Selector With Fast Switching and
           High Endurance

    • Authors: Yi Zhou;Hong Huang;Jia Han;Kaige Chen;Cong Ye;Zhong Xu;Shiheng Liang;Wen Xiong;Xin Chen;Zhitang Song;Min Zhu;
      Pages: 1125 - 1128
      Abstract: Selector is considered as a promising solution to solve sneak-path current for high-density 3-Dimensional (3D) memories. However, bidirectional selector with fast speed and long lifetime is still extremely needed. In this work, 2D material of graphene oxide containing epoxide, hydroxyl and carboxyl (−COOH, −OH, >C=O) is assembled with HfO2 to form a flexible bi-layer selector. Interestingly, the selector exhibits excellent uniformity, fast switching speed (~160 ns) and remarkable endurance of $sim 5times 10^{8}$ cycles. Moreover, no performance degradation is observed for more than $10^{3}$ times with the bending radii ranging from 40 mm to 20 mm. The high uniformity and excellent endurance may be attributed to the insulating interface layer at the HfO2/GO interface, which plays a vital role on the connection/disrupt of conductive filament (CF). Thus, the incorporation of GO into HfO2 selector may be a feasible way to achieve a promising HfO2-based selector, which have potential applications in high-density 3D integration for flexible electronics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Fabrication of Spray-Coated Semitransparent Organic Solar Cells

    • Authors: Moon Hee Kang;Dong Kyo Heo;Da Hyun Kim;Minsu Lee;Kyungsun Ryu;Yong Hyun Kim;Changhun Yun;
      Pages: 1129 - 1132
      Abstract: We investigated a promising, low-cost method for fabrication of semitransparent organic solar cells by mass production. The active layer of the organic solar cells was added by spray coating with a dual action airbrush. The solution for the active layer was prepared from a rigorously blended poly(3-hexylthiophene-2,5-diyl) (P3HT) and (6,6)-Phenyl-C61 butyric acid methyl ester (PCBM) in 1,2-dichlorobenzene, and the surface morphology of the spray-coated active layer depending on the concentration of the P3HT and PCBM was investigated. The semitransparency achieved, came from the use of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS) as the conductive polymer electrode. For comparison, spin-coated solar cells were also fabricated. Power-conversion efficiency and transparency was achieved from the lower cost spray-coating method that was comparable to those by the traditional spin-coating method. The best spray-coated solar cell exhibited power-conversion efficiency of 1.9% (average or 1.7%) while the best spin-coated solar cell was 2.0% (average of 1.6%), when both were measured under the AM1.5G spectrum 100 mW/cm2 light. Transmittance of the spray-coated solar cell was 52.2% while that of the spin-coated solar cell was 51.2%.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effective Evaluation Strategy Toward Low Temperature Solution-Processed
           Oxide Dielectrics for TFT Device

    • Authors: Wei Cai;Honglong Ning;Shangxiong Zhou;Zhennan Zhu;Rihui Yao;Jianqiu Chen;Ruiqiang Tao;Zhiqiang Fang;Xubing Lu;Junbiao Peng;
      Pages: 1140 - 1144
      Abstract: Solution-processed oxide dielectrics are widely studied as alternatives to SiO2, SiNx in thin film transistors for high capacitance and low energy consuming. However, it’s still a challenge to achieve high quality of solution-processed oxide dielectrics TFT by low-temperature post-treatment. Here, an effective strategy is proposed to evaluate low temperature solution-processed ZrO2 TFT in terms of uniformity, film density and electrical performance by employing TG/DSC, drop analyzer, XRR and a novel ${mu }$ -PCD measurement. Particularly, ${mu }$ -PCD measurement provides valuable information on homogeneity and defect level. The optimized device with ZrNO3 as dielectric precursor and ethyl alcohol as solvent through spin coating process annealed at 200°C shows a saturation mobility of 8.6 cm $^{2}text{V}^{-1}text{S}^{-1}$ , $text{I}_{mathrm{ on}}/text{I}_{mathrm{ off}}$ ratio about $1.1times 10^{6}$ , subthreshold swing about 334 mV/decade with a low leakage current density of $5times 10^{-5}$ A/cm2 at 10V. This article offers a convenient way for precursor optimization towards low leakage current and high homogeneity solution-processed oxide dielectrics for TFT devices.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • High Performance and Highly Robust AlN/GaN HEMTs for Millimeter-Wave

    • Authors: Kathia Harrouche;Riad Kabouche;Etienne Okada;Farid Medjdoub;
      Pages: 1145 - 1150
      Abstract: We report on a 3 nm AlN/GaN HEMT technology for millimeter-wave applications. Electrical characteristics for a 110 nm gate length show a maximum drain current density of 1.2 A/mm, an excellent electron confinement with a low leakage current below $10~mu text{A}$ /mm, a high breakdown voltage and a FT/Fmax of 63/300 GHz at a drain voltage of 20V. Despite residual trapping effects, state of the art large signal characteristics at 40 GHz and 94 GHz are achieved. For instance, an outstanding power added efficiency of 65% has been reached at VDS = 10V in pulsed mode at 40 GHz. Also, an output power density of 8.3 W/mm at VDS = 40V is obtained associated to a power added efficiency of 50%. At 94 GHz, a record CW output power density for Ga-polar GaN transistors has been reached with 4 W/mm. Additionally, room temperature preliminary robustness assessment at 40 GHz has been performed at VDS = 20V. 24 hours RF monitoring showed no degradation during and after the test.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
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