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  Subjects -> ELECTRONICS (Total: 179 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 78)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 315)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 269)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 105)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 92)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 191)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 66)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 71)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 24)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access  
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 168)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Journal Cover
IEEE Journal of the Electron Devices Society
Journal Prestige (SJR): 1.016
Citation Impact (citeScore): 3
Number of Followers: 9  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2168-6734
Published by IEEE Homepage  [191 journals]
  • Editorial Exciting Progress

    • Authors: Mikael Östling;
      Pages: 1 - 1
      Abstract: We enter 2019 with enforced spirit and confidence. The Journal of Electron Devices Society has developed extremely well over the past few years.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Low-Temperature MoS2 Film Formation Using Sputtering and
           H2S Annealing

    • Authors: Jun’ichi Shimizu;Takumi Ohashi;Kentaro Matsuura;Iriya Muneta;Kakushima Kuniyuki;Kazuo Tsutsui;Nobuyuki Ikarashi;Hitoshi Wakabayashi;
      Pages: 2 - 6
      Abstract: Low-carrier density and high-crystallinity molybdenum disulfide (MoS2) films were fabricated by low-temperature and clean process based on a UHV RF sputtering system. This paper focuses on improving crystallinity and reducing the number of sulfur defects of sputtered-MoS2 film. We have fabricated MoS2 films at lower than 400°C using the sputtering and H2S post-deposition annealing processes. Consequently, MoS2 films with high crystallinity and appropriate S/Mo ratio were obtained. Eventually, a low carrier density of 3.5 × 1017 cm-3 and the Hall-effect mobility of 12 cm2 V-1 s-1 were achieved.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effects of Interface States on Ge-On-SOI Photodiodes

    • Authors: Chong Li;Ben Li;Shihong Qin;Jiale Su;Xiaoying He;Xia Guo;
      Pages: 7 - 12
      Abstract: The 4.2% mismatch at the Si/Ge interface has a significant impact on Si/Ge photodetectors. However, few researchers have attempted to determine the major noise source or study the effects of the Si/Ge interface on the dark current, the responsivity and the 3-dB bandwidth of these devices. In this letter, we found that the dark current was dominated by generation-recombination processes that were enhanced by trap-assisted-tunneling around the interface below 220 K, with a characteristic tunneling energy of E00 = 14 meV corresponding to an effective mass of m* = 18m0. This behavior can be explained by the rise in the heavy-hole band caused by the compressive strain on the Ge layer. When the temperature increased above 240 K, Shockley-Read-Hall recombination was clearly observed and believed to be dominant. The responsivity, the collection efficiency and the absorption efficiency were all extracted at 850 nm, 1310 nm, and 1550 nm. The absorption coefficient around the interface was found to be lower than that of the bulk material. In addition, comparison of the measured 3-dB frequency (~20.6 GHz @ -0.5 V) with the theoretical value (~29.37 GHz) indicated that defects have little effect on the bandwidth at high frequencies.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Hybrid Phototransistor Neuromorphic Synapse

    • Authors: Yu Liu;Wen Huang;Xiawa Wang;Renrong Liang;Jing Wang;Bin Yu;Tian-Ling Ren;Jun Xu;
      Pages: 13 - 17
      Abstract: In this paper, a synaptic transistor based on the indium zinc oxide (IZO)-hafnium oxide (HfO2) thin film structure was demonstrated. Blue light pulses (470 nm) were used as the presynaptic stimulus, the IZO channel was used as the postsynaptic membrane, and the HfO2 electrolyte film was regarded as the synaptic cleft. The synaptic transistor exhibited the behavior of paired-pulse facilitation. With different light power densities, the channel current of the transistor can be regulated to different levels, corresponding to different synaptic weights. In addition, the transistor showed the brain's memory behaviors including the short-term memory and the transition from the short to the long term memory. The synaptic behaviors of the transistor can be explained by the trapping and releasing processes of the photo-generated carriers.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • SPICE Modeling of Insulator Metal Transition: Model of the Critical

    • Authors: Sherif Amer;Md Sakib Hasan;Md Musabbir Adnan;Garrett S. Rose;
      Pages: 18 - 25
      Abstract: This paper proposes a compact SPICE phenomenological model for insulator metal transition (IMT) devices. The proposed model captures the interplay of electric field and Joule heating to effect a transition from a high resistance insulating state to a low resistance metallic state. The model is corroborated against experimental results and electrothermal simulations available in the literature. The proposed model is implemented in Verilog-A and is fully compatible with commercial SPICE simulators such as Spectre from Cadence, used in this paper. An IMT-based artificial neuron is then designed and simulated using the proposed IMT compact model and design expressions for the operation of the proposed neuron are derived. The simulation results agree with the expected neuron behavior as well as the simulation results of other similar neurons proposed in the literature. This paper will enable circuit designers to design and simulate IMT-based systems and help them explore the full potential of such novel devices.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Electrical Stability of Solution-Processed a-IGZO TFTs Exposed to
           High-Humidity Ambient for Long Periods

    • Authors: Seung-Un Lee;Jaewook Jeong;
      Pages: 26 - 32
      Abstract: The variations in the electrical and mechanical properties of solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors exposed to high-humidity ambient conditions for long periods were analyzed. When the TFT was exposed to high-humidity conditions, field-effect mobility severely decreased, while ON/OFF current ratio improved and subthreshold slope value remained nearly constant, which is different from that exposed to low-humidity condition. We found that the H2O molecules induce mechanical peeling of the active layer such that they act as acceptor-like deep states, which is very different from the prior results under low humidity condition. The variations in electrical characteristics were systematically analyzed using a technology-CAD simulation before and after exposure to highhumidity conditions.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • The Vacancy Pool Model for Amorphous In-Ga-Zn-O Thin-Film Transistors

    • Authors: Ya-Hsiang Tai;Han-Wen Liu;Po-Chun Chan;
      Pages: 33 - 37
      Abstract: In this paper, the reaction rate of oxygen vacancy (VO) by the derivatives of threshold voltage (Vth) in the amorphous indium-gallium-zinc oxide thin-film transistors under light pulses with altering duty ratios is investigated. More importantly, after collecting and analyzing a lot of experimental results, a comprehensive model named VO pool is proposed. The proposed model can more universally describe the characteristic of VO reacting to the light and its degradation behavior under various kinds of stress condition.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Proton Conductor Gated Synaptic Transistor Based on Transparent IGZO for
           Realizing Electrical and UV Light Stimulus

    • Authors: Weijun Cheng;Renrong Liang;He Tian;Chuanchuan Sun;Chunsheng Jiang;Xiawa Wang;Jing Wang;Tian-Ling Ren;Jun Xu;
      Pages: 38 - 45
      Abstract: Synaptic transistors mimicking the biological synapse's short term plasticity and short-term memory property were demonstrated using the amorphous indium-gallium-zinc oxide channel in combination with the nanogranular SiO2 as the gate oxide. The lowest energy consumption was ~1.08 pJ per pulse activity and the operating voltage was within 100 mV. The device's plasticity and memory characteristics can be explained by the movement of protons in the insulating layer. The proton relaxation was revealed by two ways of dual sweeping: continuous and discontinuous sweepings. We observed that the excitatory postsynaptic current (EPSC) rose as the voltage decreased anomaly during the backward sweeping process. In the electrical stimulus, both the short-term potentiation and depression were observed for this proposed device. The amplitude of the EPSC changed with the pulse number following a saturating exponential function. For the electrical stimulus under constant illumination, the UV light wavelength, intensity and duration time were found to have little effect on the paired pulse facilitation. While in the light stimulus, the light frequency promoted the paired pulse facilitation and had more effect on the synapse's plasticity than the other light pulse parameters including intensity, numbers and width.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Self-Organized Ge Nanospherical Gate/SiO2/Si0.15Ge0.85–Nanosheet n-FETs
           Featuring High ON-OFF Drain Current Ratio

    • Authors: Po-Hsiang Liao;Kang-Ping Peng;Horng-Chih Lin;Thomas George;Pei-Wen Li;
      Pages: 46 - 51
      Abstract: We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure is simultaneously produced in a single oxidation step as a consequence of an exquisitely controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials at 900 °C. Process-controlled tunability of nanospherical gate of 60-100 nm in diameter, gate oxide thickness of 3 nm, and Si0.15Ge0.85 nanosheet with compressive strain of -2.5% was achieved. Superior gate modulation is evidenced by subthreshold slope of 150 mV/dec and ION/IOFF> 5 × 108 (IOFF 500 μA/μm) measured at VG= +1V , VD = +1 V, and T = 80 K for our device with channel length of 75 nm.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Homo-Junction Bottom-Gate Amorphous In–Ga–Zn–O TFTs With
           Metal-Induced Source/Drain Regions

    • Authors: Yang Shao;Xiaoliang Zhou;Huan Yang;Baozhu Chang;Ting Liang;Yi Wang;Shengdong Zhang;
      Pages: 52 - 56
      Abstract: A fabrication process for homo-junction bottom-gate (HJBG) amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is proposed, in which the a-IGZO section as source/drain (S/D) regions is induced into a low resistance state by coating a thin metal Al film and then performing a thermal annealing in oxygen, with the channel region protected from back etching by depositing and patterning a protective layer. The experimental results show that with a 5 nm Al film and annealing at 200 °C, the sheet resistance of the S/D a-IGZO is reduced to 803 Ω/EI, and keeps stable during a subsequent thermal treatment. In addition, the thin Al2O3 film generated by the annealing contributes to an improved thermal stability and ambient atmosphere immunity for the fabricated HJBG TFTs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $boldsymbol{beta}$+ -Ga2O3+Rectifiers&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jiancheng&;Fan+Ren;Yen-Ting+Chen;Yu-Te+Liao;Chin-Wei+Chang;Jenshan+Lin;Marko+J.+Tadjer;S.+J.+Pearton;Akito+Kuramata;">Dynamic Switching Characteristics of 1 A Forward Current
           $boldsymbol{beta}$ -Ga2O3 Rectifiers

    • Authors: Jiancheng Yang;Fan Ren;Yen-Ting Chen;Yu-Te Liao;Chin-Wei Chang;Jenshan Lin;Marko J. Tadjer;S. J. Pearton;Akito Kuramata;
      Pages: 57 - 61
      Abstract: An inductive load test circuit was used to measure the switching performance of fieldplated edge-terminated Schottky rectifiers with a reverse breakdown voltage of 760 V (0.1 cm diameter, 7.85 × 10-3cm2 area) and an absolute forward current of 1 A on 8 μm thick epitaxial ß-Ga2O3 drift layers. The recovery characteristics for these vertical geometry ß-Ga2O3 Schottky rectifiers switching from forward current of 1 A to reverse off-state voltage of -300 V showed a recovery time (trr) of 64 ns. There was no significant temperature dependence of trr up to 150 °C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A New Low Turn-Off Loss SOI Lateral Insulated Gate Bipolar Transistor With
           Buried Variation of Lateral Doping Layer

    • Authors: Tao Tian;Sheng-Li Zhang;Yu-Feng Guo;Jun Zhang;David Z. Pan;Ke-Meng Yang;
      Pages: 62 - 69
      Abstract: In this paper, we propose a new low turn-off loss silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with buried variation of lateral doping (VLD) layer. The proposed device features a VLD layer inserted in the drift region, which increases the doping dose (Q) and gradient (G) compared with Uniform P-buried (UPB) SOI LIGBT. The larger capacitance effect induced by lager Q and faster depletion leads to the lower rising anode voltage and reduced storage charge in the drift region. Therefore, a considerable low turn-off loss (Eoff) can be obtained. It is worth to note that owing to reshaped electric field in the new structure, the excess carriers of the drift region could be removed more quickly. Furthermore, larger G of the VLD layer improves the tradeoff between breakdown voltage and turn-off loss. The results of 2-D simulation indicate that the Eoff of the proposed device can reduce by 29.4% and 69.7% at 100 A·cm-2 and 200 A·cm-2, respectively, when compared with UPB SOI LIGBT.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

    • Authors: Olli-Pekka Kilpi;Johannes Svensson;Erik Lind;Lars-Erik Wernersson;
      Pages: 70 - 75
      Abstract: Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Effect of Hot Electron Stress on AlGaN/GaN HEMTs of Hydrogen Poisoning

    • Authors: J. He;Y. Q. Chen;Z. Y. He;Y. F. En;C. Liu;Y. Huang;Z. Li;M. H. Tang;
      Pages: 76 - 81
      Abstract: We have investigated the effect of hot electron stress on the electrical properties of AlGaN/GaN high electron mobility transistors (HEMTs) of hydrogen poisoning. The AlGaN/GaN HEMTs were biased at the semi-on state, and they suffered from the hot electron stress. The devices of hydrogen poisoning were degraded, while there is almost no degradation for the fresh ones. The hot electron stress leads to the significantly positive shift of threshold voltage and the notable decrease of drain-to-source current for the AlGaN/GaN HEMTs of hydrogen poisoning. For the AlGaN/GaN HEMTs of hydrogen poisoning, the trap density increases by about one order of magnitude after the hot electron stress experiment. The physical mechanism can be attributed to electrically active traps due to the dehydrogenation of passivated point defects at AlGaN surface, AlGaN barrier layer, and heterostructure interface. The results of this paper may be useful in the design and application of AlGaN/GaN HEMTs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • High Performance Single Crystalline Diamond Normally-Off Field Effect

    • Authors: Zeyang Ren;Wanjiao Chen;Jinfeng Zhang;Jincheng Zhang;Chunfu Zhang;Guansheng Yuan;Kai Su;Zhiyu Lin;Yue Hao;
      Pages: 82 - 87
      Abstract: High performance normally-off hydrogen-terminated diamond (H-diamond) MOSFETs were fabricated on single crystalline diamond grown in our lab. The device with 2-μm gate length shows threshold voltage of -1.0 V, and a drain current of 51.6 mA/mm at VGS = VDS = -4.5 V and an on-resistance of 65.39 Ω·mm. The transconductance keeps increasing when VGS shifts from VTH toward more negative direction, and reaches the record high value of 20 mS/mm at VGS of -4.5 V, which benefitted from the almost constant mobility of the holes in the gate voltage range of -4 V
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A High-Performance InAs/GaSb Core-Shell Nanowire Line-Tunneling TFET: An
           Atomistic Mode-Space NEGF Study

    • Authors: Aryan Afzalian;Gerben Doornbos;Tzer-Min Shen;Matthias Passlack;Jeff Wu;
      Pages: 88 - 99
      Abstract: Using a tight-binding mode-space NEGF technique, we explore the essential physics, design and performance potential of the III-V core-shell (CS) nanowire (NW) heterojunction tunneling field-effect transistor (TFET). The CS TFET “line-tunneling” current increases significantly with the core diameter dC and outperforms the best III-V axial “point-tunneling” NW heterojunction TFET ION by up to 6× for dC = 6.6 nm. Reaching such a high level of current at low supply voltage, however, requires and involves specific and sometime unanticipated optimizations and physics that are thoroughly investigated here. In spite of the commonly accepted view, we also show and explain the weak gate-length dependency observed for the line-tunneling current in a III-V TFET. We further investigate the effect of electron-phonon scattering and discrete dopant impurity band tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET inverter performance significantly outperforms that of the axial TFETs. The low-power (LP) VDD = 0.35V CS-inverter delay is comparable to that of the high-performance (HP) Si CMOS using VDD = 0.55, which shows promise for an LP TFET technology with HP speed.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to
           Venus Surface Atmospheric Conditions

    • Authors: Philip G. Neudeck;Liangyu Chen;Roger D. Meredith;Dorothy Lukco;David J. Spry;Leah M. Nakley;Gary W. Hunter;
      Pages: 100 - 110
      Abstract: Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet's extreme conditions of ~460°C, ~9.3 MPa (~92 Earth atmospheres) chemically reactive environment. Here, we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost threefold and were accomplished using prototype SiC JFET chips of more than sevenfold increased complexity. The demonstrated advancement marks a significant step toward realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A New High-Gain Operational Amplifier Using Transconductance-Enhancement
           Topology Integrated With Metal Oxide TFTs

    • Authors: Zhuo-Jia Chen;Wen-Xing Xu;Jian-Dong Wu;Lei Zhou;Wei-Jing Wu;Jian-Hua Zou;Miao Xu;Lei Wang;Yu-Rong Liu;Jun-Biao Peng;
      Pages: 111 - 117
      Abstract: This paper presents an integrated operational amplifier (OPAMP) consisting of only n-type metal oxide thin-film transistors. In addition to using positive feedback in the input differential pair, a transconductance-enhancement topology is applied to improve the gain of the OPAMP. The OPAMP has a voltage gain (Av) of 29.54 dB over a 3-dB bandwidth of 9.33 kHz at a supply voltage of 15 V. The unity-gain frequency, phase margin (PM), and dc power consumption (PDC) are 180.2 kHz, 21.5° PM and 5.07 mW, respectively.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Comprehensive Analysis and Optimal Design of Ge/GeSn/Ge p-n-p Infrared
           Heterojunction Phototransistors

    • Authors: Ankit Kumar Pandey;Rikmantra Basu;Harshvardhan Kumar;Guo-En Chang;
      Pages: 118 - 126
      Abstract: We present a comprehensive analysis of practical p-n-p Ge/Ge1-xSnx/Ge heterojunction phototransistors (HPTs) for design optimization for efficient infrared detection. Our design includes a Ge1-xSnx narrow-bandgap semiconductor as the active layer in the base layer, enabling extension of the photodetection range from near-infrared to mid-infrared to perform wide-range infrared detection. We calculate the current gain, signal-to-noise ratio (SNR), and optical responsivity and investigate their dependences on the structural parameters to optimize the proposed Ge1-xSnx p-n-p HPTs. The results show that the SNR is strongly dependent on the operation frequency and that the introduction of Sn into the base layer can improve the SNR in the high-frequency region. In addition, the current gain strongly depends on the Sn content in the Ge1-xSnx base layer, and a Sn content of 6%-9% maximizes the optical responsivity achievable in the infrared range. These results provide useful guidelines for designing and optimizing practical p-n-p Ge1-xSnx HPTs for high-performance infrared photodetection.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Extraction of Contact Resistance and DC Modeling in Metal Oxide TFTs

    • Authors: Na Li;Wanling Deng;Xixiong Wei;Weijing Wu;Junkai Huang;
      Pages: 127 - 133
      Abstract: Based on the device physics, a simple and fast method of extracting contact resistance in metal oxide thin-film transistors (MOTFTs) is proposed through the I-V characteristics. This method divides the channel into two parts: the contact channel and the intrinsic channel, and assumes the electrons injected into the active layer at the source side are completed in the line injection. Using the I-V characteristics, the contact voltage can be obtained, and then the contact resistance can be extracted. The results indicate that contact resistance in MOTFTs depends on Vg, Vd, and L. Applying the extraction results, a dc drain current model considering contact resistance is proposed. Using this model, we can accurately describe the measurements of MOTFTs with channel lengths scaling from 50 μm to 10 μm. Through the extensive comparisons between the model results and the numerical iteration or experimental data, the validity of the method is strongly supported. This extraction method uses non-numerical iteration, which is simple, fast, and accurate.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ferroelectric HfO2 Tunnel Junction Memory With High TER and Multi-Level
           Operation Featuring Metal Replacement Process

    • Authors: Masaharu Kobayashi;Yusaku Tagawa;Fei Mo;Takuya Saraya;Toshiro Hiramoto;
      Pages: 134 - 139
      Abstract: We have investigated device design of HfO2-based ferroelectric tunnel junction (FTJ) memory. Asymmetry of dielectric screening property in top and bottom electrodes is the key for high tunneling electroresistance (TER) ratio. Thus, metal and semiconductor electrodes are proposed. There exists a design space of ferroelectric material parameters to achieve high TER ratio under the constraint of depolarizing field. We have developed an FTJ fabrication process to realize the design. Large polarization charge and symmetric switching voltage are obtained by top metal replacement process. High TER ratio>30 and multi-level cell operation have been successfully demonstrated. Retention characteristics is promising, however, endurance characteristics should be improved for reliable operation.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Study on Selectivity and Temperature Coefficients of the Chloride Ion
           Sensors With RuOx Thin Film

    • Authors: Shi-Chang Tseng;Tong-Yu Wu;Jung-Chuan Chou;Yi-Hung Liao;Chih-Hsien Lai;Jian-Syun Chen;Min-Siang Huang;Siao-Jie Yan;Si-Hong Lin;
      Pages: 140 - 149
      Abstract: This paper investigated the response time, chloride selectivity, and temperature coefficients of the arrayed flexible ruthenium oxide chloride ion sensor in sodium chloride (NaCl) solutions with concentrations from 10-5 M to 1 M. The response time was 7 s in 1 M NaCl solution at room temperature, showing that the sensor had the characteristics of the fast response. The selectivity coefficients of the SO42- ion, NO3- ion, CO32- ion, ClO- ion, and ClO4- ion were 0.001, 0.056, 0.004, 0.015, and 0.006, respectively. The chloride ion sensing device had the good chloride selectivity. Finally, the sensitivity was investigated with different solution temperatures from 5 °C to 50 °C. The sensitivity was increased with higher solution temperature. The temperature coefficient of the sensitivity of the chloride ion sensing device was approximately 0.681 mV/pCl °C between 5 °C and 35 °C.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of Retention Noise for 3-D TLC NAND Flash Memory

    • Authors: Kunliang Wang;Gang Du;Zhiyuan Lun;Xiaoyan Liu;
      Pages: 150 - 157
      Abstract: In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated. Three main noise sources, consisting of essential EES (EEES), electron numbers fluctuation, and device parameters fluctuation to broaden the retention Vth distributions are comprehensively considered, and the corresponding analytic models are developed. The impact of device parameters fluctuation is relatively larger than EEES and electron numbers fluctuation for our measured 3-D TLC NAND flash memory devices. Using the proposed models, the calculated Vth distributions after different data retention times have good agreements with the measurements, which validate our proposed models. This paper provides a method to predict the Vth distributions accurately and efficiently, and can help in improving reliability of 3-D TLC and quad-level program cell NAND flash memory.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Reliable Technology for Advanced SiC-MOS Devices Based on Fabrication of
           High Quality Silicon Oxide Layers by Converting a-Si

    • Authors: Razvan Pascu;Cosmin Romanitan;Pericle Varasteanu;Mihaela Kusko;
      Pages: 158 - 167
      Abstract: An alternative technological approach is proposed to obtain a SiO2 film on SiC using processes that finally reduce the effective fabrication costs. Accordingly, we report achieving of a high-quality oxide on 4H-SiC substrate using a process flow that consists in a preliminary deposition by sputtering, at room temperature, of an amorphous Si thin layer, followed by its oxidation at a relative low temperature (1100 °C) for SiC MOS technology. The X-ray reflectivity measurements demonstrated that the resulted oxide has a comparable roughness with the one thermally grown and presents the advantage of an almost threefold thinner interfacial layer. The improvement of the oxide/semiconductor interface was further validated by the electrical investigation of the fabricated MOS structures, where a significant diminishing of the effective oxide charge density, interface traps density, and near interface oxide traps density was assessed. Thus, we demonstrated that, for a specified thickness of the oxide layer on SiC, the proposed technological flow not only significantly reduces the standard duration of the process necessary and consequently the associated fabrication cost, but, more important, leads to superior oxides and interfaces, in terms of both micro-physical and electrical properties.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile
           Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method

    • Authors: Lun-Chun Chen;Hung-Bin Chen;Yu-Shuo Chang;Shih-Han Lin;Ming-Hung Han;Jia-Jiun Wu;Mu-Shih Yeh;Yu-Ru Lin;Yung-Chun Wu;
      Pages: 168 - 173
      Abstract: A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Symmetrical and Crossed Double-Sided Passivation Emitter and Surface Field
           Solar Cells for Bifacial Applications

    • Authors: Jyi-Tsong Lin;Kon-Yu Ho;Steve W. Haga;Wen-Hao Chen;
      Pages: 174 - 179
      Abstract: This paper proposes symmetrical and crossed double-sided passivation emitter and surface field solar cells for bifacial applications which are fully compatible with the passivated emitter and rear contact (PERC) fabrication process. Our simulations use Silvaco TCAD Atlas, calibrated by real measurements. At an ideal albedo level where light enters both sides equally, these symmetrical and crossed structures boost energy by 88.78% and 106.74%, respectively. The reason for the crossed structure's better performance is that it has a surrounding electric field. The crossed structure also obtains a 40.18 mA/cm2 short-circuit current (Jsc), a 0.67 V open-circuit voltage (Voc), an 81.07% fill factor and a 21.93% conversion efficiency (η). Compared with PERC+, the crossed structure improves low bifaciality factor (φη) and increases η by 6.44% and energy boost by 31.41% for bifacial. For more-realistic albedo levels, the structure also performs strongly. At the spectral albedo level of snow, the energy boost of the crossed structure is 102.06%, which is close to the performance at ideal albedo. At the spectral albedo level of white sand, the energy boost is 77.13%. At lower albedos, the energy boost remains between 20% and 30%.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Different Isolation Processes for Free-Standing GaN p-n Power Diode With
           Ultra-High Current Injection

    • Authors: Chia-Jui Yu;Chun-Kai Chang;Chien-Ju Chen;Jyun-Hao Liao;Meng-Chyi Wu;
      Pages: 180 - 185
      Abstract: In this paper, we report on the fabrication and high performance of power p-n diodes grown on free-standing (FS) GaN substrate. The key technique to enhance the high breakdown voltage and suppress the surface leakage current is the isolation process. The mesa-structure diode is generally formed by utilizing the inductively coupled plasma reactive ion etching; however, it always induces high surface damages and thus causes a high leakage current. In this paper, we propose a planar structure by employing the oxygen ion implantation to frame the isolation region. By following the crucial process, the fabricated mesaand planar-type diodes exhibit the turn-on voltages of 3.5 and 3.7 V, specific on-resistance (RONA) of 0.42 and 0.46 mΩ-cm2, and breakdown voltage (VB) of 2640 and 2880 V, respectively. The corresponding Baliga's figures of merit (BFOM, i.e., V2B/RONA) are 16.6 and 18 GW/cm2, respectively. The BFOM of 18 GW/cm2 is the highest reported value for FS-GaN diode. From the temperature dependent measurements, the planar-type diode also shows the better leakage current and thermal stability than the mesa-type diode.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • External Resistor-Free Gate Configuration Phase Transition FDSOI MOSFET

    • Authors: Jaemin Shin;Changhwan Shin;
      Pages: 186 - 190
      Abstract: Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A SiC BJT-Based Negative Resistance Oscillator for High-Temperature

    • Authors: Muhammad Waqar Hussain;Hossein Elahipanah;John E. Zumbro;Saul Rodriguez;Bengt Gunnar Malm;Homer A. Mantooth;Ana Rusu;
      Pages: 191 - 195
      Abstract: This brief presents a 59.5 MHz negative resistance oscillator for high-temperature operation. The oscillator employs an in-house 4H-silicon carbide BJT, integrated with the required circuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room temperature up to 400 °C. The oscillator delivers an output power of 11.2 dBm into a 50 Ω load at 25 °C, which decreases to 8.4 dBm at 400 °C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased with a collector current of 35 mA from a 12-V supply and has a maximum dc power consumption of 431 mW.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Au Nanoparticles-Decorated Surface Plasmon Enhanced ZnO Nanorods
           Ultraviolet Photodetector on Flexible Transparent Mica Substrate

    • Authors: Hainan Zhang;Yunfei Zhao;Xiangshun Geng;Yao Huang;Yuxing Li;Houfang Liu;Yu Liu;Yutao Li;Xuefeng Wang;He Tian;Renrong Liang;Tian-Ling Ren;
      Pages: 196 - 202
      Abstract: An ultraviolet (UV) photodetector based on hydrothermally processed ZnO nanorods (ZnO NRs) decorated by gold nanoparticles (Au NPs) was demonstrated to exhibit extraordinary optoelectronic properties. Due the implementation of Au NPs, the UV responsivity and specific detectivity reached 70 A/W and 3.41 × 1012 cm Hz1/2 W-1, respectively, which were enhanced by approximately four times at an excitation wavelength of 365 nm compared with those of pristine ZnO NRs. Moreover, such photodetector shows good flexibility as well due to the mica substrate, which maintains almost constant performances under different bending radii of curvature and repeatable bending test more than 200 cycles. The photodetector also exhibits good transparency, giving it the potential of integration with other light photodetectors. In addition, a schematic band-diagram and the accompanying finite-difference time-domain analysis were performed to reveal the electron transfer and electric field distribution of ZnO NRs decorated with Au NPs. Our results revealed that the noble metal modified plasmon-enhanced ZnO NRs photodetector with high responsivity, low cost has a great potential for application in manufacturing flexible and transparent integrated optoelectronics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Scaling Down Effect on Low Frequency Noise in Polycrystalline Silicon
           Thin-Film Transistors

    • Authors: Yuan Liu;Shu-Ting Cai;Chao-Yang Han;Ya-Yi Chen;Li Wang;Xiao-Ming Xiong;Rongsheng Chen;
      Pages: 203 - 209
      Abstract: Scaling down effects on conduction and low frequency noise characteristics are investigated in a set of p-type polycrystalline silicon thin-film transistors (poly-Si TFTs) with fixed channel width (W=8 μm) and different channel lengths (L=2, 4, 8, 12, and 20 μm). First, short channel effects on threshold voltage, field effect mobility, and sub-threshold swing are examined, while the presence of contact may induce to the degradation of field effect mobility in the short channel devices. Subsequently, the drain current noise power spectral densities are measured at varied effective gate voltages and drain currents. The slopes of normalized noise against effective gate voltage are varied from -1.1 to -2 with decreasing channel length, which indicates that poly-Si TFTs varied from bulk dominated devices to interface dominated devices. Based on ΔN-Δμ model, the flat-band voltage noise spectral density and coulomb scattering coefficient are extracted. Therefore, measured normalized noises are simulated by considering of contact resistance. Finally, short channel effects on some noise parameters (such as Hooge's parameter, etc.) are studied and discussed.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low
           Voltage IoT Applications

    • Authors: Jheng-Sin Liu;Michael B. Clavel;Mantu K. Hudait;
      Pages: 210 - 218
      Abstract: A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage (0.3 V ≥ VDD ≤ 0.6 V) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Accurate Graphene-Metal Junction Characterization

    • Authors: Matthias König;Günther Ruhl;Amit Gahoi;Sebastian Wittmann;Tobias Preis;Joerg-Martin Batke;Ioan Costina;Max C. Lemme;
      Pages: 219 - 226
      Abstract: A reliable method is proposed for measuring specific contact resistivity (pC) for graphenemetal contacts, which is based on a contact end resistance measurement. We investigate the proposed method with simulations and confirm that the sheet resistance under the metal contact (RSK) plays an important role, as it influences the potential barrier at the graphene-metal junction. Two different complementary metal-oxide-semiconductor-compatible aluminum-based contacts are investigated to demonstrate the importance of the sheet resistance under the metal contact: the difference in RSK arises from the formation of insulating aluminum oxide (Al2O3) and aluminum carbide (Al4C3) interfacial layers, which depends on the graphene pretreatment and process conditions. Auger electron spectroscopy and X-ray photoelectron spectroscopy support electrical data. The method allows direct measurements of contact parameters with one contact pair and enables small test structures. It is further more reliable than the conventional transfer length method when the sheet resistance of the material under the contact is large. The proposed method is thus ideal for geometrically small contacts where it minimizes measurement errors and it can be applied in particular to study emerging devices and materials.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Random Telegraph Noises in CMOS Image Sensors Caused by Variable
           Gate-Induced Sense Node Leakage Due to X-Ray Irradiation

    • Authors: Calvin Yi-Ping Chao;Thomas M.-H. Wu;Shang-Fu Yeh;Kuo-Yu Chou;Honyih Tu;Chih-Lin Lee;Chin Yin;Philippe Paillet;Vincent Goiffon;
      Pages: 227 - 238
      Abstract: The effects of X-ray irradiation on the random noises, especially the random telegraph noises (RTN), of a 45-nm on 65-nm stacked CMOS image sensor with 8.3M 1.1 μm pixels are investigated. It is found that before X-ray irradiation the dominant type of RTN among the noisiest pixels is the source follower (SF) MOSFET channel RTN. In contrast, after X-ray irradiation up to a total ionizing dose of 1 Mrad(SiO2), the RTN becomes dominated by the variable transfer-gate-induced sense node (SN) leakage. These two different types of RTN can be distinguished by their dependence on the transfer gate (TG) OFF voltage and the time between the correlated double sampling (CDS). The magnitude of the RTN from the variable SN leakage is proportional to the CDS time and can be suppressed effectively by increasing the TG OFF voltage, whereas the SF RTN is independent of the CDS time or the TG OFF voltage.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $mu$+ m+CMOS+Process&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Xiao&;Nicola+D’ascenzo;Werner+Brockherde;Stefan+Dreiner;Andrei+Schmidt;Qingguo+Xie;">Silicon Photomultipliers With Area Up to 9 mm2 in a 0.35- $mu$ m CMOS

    • Authors: Xiao Liang;Nicola D’ascenzo;Werner Brockherde;Stefan Dreiner;Andrei Schmidt;Qingguo Xie;
      Pages: 239 - 251
      Abstract: Silicon photomultipliers produced using standard complementary metal oxide semiconductor (CMOS) processes are at the basis of modern applications of sensors for weak photon fluxes. They allow in fact to integrate transistor-based electronic components within sensors and provide intelligent read-out strategies. In this paper, we investigate the scalability of a 0.35-μm CMOS process to large area devices. We report the design and characterization of SiPMs with a total area of 1, 4, and 9 mm2. Cross talk, photon detection efficiency at 420 nm, gain at 2.5 V overvoltage and breakdown voltage temperature coefficient do not depend on the total area of the sensor and are 10%, 35%, 2.5 x 106, and 35 mV/K, respectively. The dark count rate scales with the total area of the device as 180 kHz/mm2. The total output capacitance, the decay time of the single photon signal, and the single photon time resolution depend on the area of the device. We obtain a capacitance of 66.9, 270.2, and 554.0 pF, a decay time of (27.1±0.1) ns, (50.8±0.1) ns, and (78.2±0.1) ns and a single photon time resolution of (77.97±0.51) ps, (201.67 ± 0.98) ps, and (282.28 ± 0.86) ps for the 1, 4, and 9 mm2 SiPMs, respectively.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Highly Reliable Contacts to Silicon Enabled by Low Temperature Sputtered
           Graphenic Carbon

    • Authors: Max Stelzer;Moritz Jung;Ursula Wurstbauer;Alexander Holleitner;Franz Kreupl;
      Pages: 252 - 260
      Abstract: Titanium silicide (TiSi) contacts are frequently used metal-silicon contacts but are known to diffuse into the active region under high current density stress pulses. Recently, we demonstrated that graphenic carbon (GC) deposited by CVD at 1000 °C on silicon has the same low Schottky barrier as TiSi, but a much improved reliability against high current density stress pulses. In this paper, we demonstrate now that the deposition of GC is possible at 100 °C - 400 °C by a sputter process. We show that the sputtered carbon-silicon contact is over 1 billion times more stable against high current density pulses than the conventionally used TiSi-Si junction, while it has the same or even a lower Schottky barrier. SC can be doped by nitrogen (CN) and this results in an even lower resistivity and improved stability. Scalability of the CN thickness down to 5 nm is demonstrated. The finding that there is a low temperature approach for using the excellent carbon properties has important consequences for the reliability of contacts to silicon and opens up the use of GC in a vast number of other applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Simple Analytic Modeling Method for SPAD Timing Jitter Prediction

    • Authors: Feiyang Sun;Yue Xu;Zhong Wu;Jun Zhang;
      Pages: 261 - 267
      Abstract: Timing jitter as a key performance of single-photon avalanche diode (SPAD) detectors plays a significant role in determining the fast temporal response behavior of the SPAD device. Nevertheless, few analytic models are developed to directly calculate the characteristic of timing jitter for its modeling difficulty. In this paper, we propose a simple analytic modeling method, which can predict the temporal response of SPADs, without using time-consuming Monte Carlo simulation. Model investigation incorporates avalanche current, avalanche buildup time, and jitter tail under different conditions. Furthermore, the key model parameters provided by Geiger mode technology computer-aided design simulation allow an accurate prediction on timing jitter. Analytical results indicate that for an SPAD device structure with a shallow P+/N-well junction in a 0.18-μm CMOS technology, the Gaussian peak response with about 110-ps full-width at half-maximum and the exponential jitter tail are in good agreement with the measured data, validating the accuracy, and feasibility of this modeling method.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ferroelectric Field Effect Transistors Based on PZT and IGZO

    • Authors: Cristina Besleaga;Roxana Radu;Liliana-Marinela Balescu;Viorica Stancu;Andreea Costas;Viorel Dumitru;George Stan;Lucian Pintilie;
      Pages: 268 - 275
      Abstract: Ferroelectric field effect transistors (FeFETs) based on lead zirconate titanate (PZT) ferroelectric material and amorphous-indium-gallium-zinc oxide (a-IGZO) were developed and characterized. The PZT material was processed by a sol-gel method and then used as ferroelectric gate. The a-IGZO thin films, having the role of channel semiconductor, were deposited by radio-frequency magnetron sputtering, at a temperature of ~50°C. Characteristics of a typical field effect transistor with SiO2 gate insulator, grown on highly doped silicon, and of the PZT-based FeFET were compared. It was proven that the FeFETs had promising performances in terms of Ion/Ioff ratio (i.e., 106) and IDS retention behavior.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact

    • Authors: Jyi-Tsong Lin;Wei-Tse Sun;Hung-Hsiu Lin;Yi-Jie Chen;Nupur Navlakha;Abhinav Kranti;
      Pages: 276 - 281
      Abstract: In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes. As the device is free from physical doping, the problems associated with random dopant fluctuations will be eliminated in the proposed doping-less topology. Our simulation results show that a programming window of 28.7 μA/μm at a gate length of 10 nm with the retention time of 466 ms at 27 °C and 79 ms at 85 °C can be achieved with the proposed doping-less 1T-DRAM, which is much better than a conventional charge-plasma based doping-less 1T DRAM.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of Nitrous Oxide Nitridation Temperatures on P-Type Pi-Gate
           Poly-Si Junctionless Accumulation Mode TFTs

    • Authors: Dong-Ru Hsieh;Kun-Cheng Lin;Tien-Sheng Chao;
      Pages: 282 - 286
      Abstract: In this paper, the influence of nitrous oxide (N2O) nitridation temperatures on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) TFTs is experimentally investigated. The tetraethoxysilane (TEOS) gate oxide quality for PG JAM TFTs can be significantly improved by increasing N2O nitridation temperatures (TN) from 700°C to 800°C in N2O ambient, resulting in the improvement of average subthreshold swing (A.S.S.), increase of on current (ION), and enhancement of TEOS gate oxide breakdown E-field (EOBD). PG JAM TFTs by means of a proper channel doping concentration (Nch = 5 × 1018 cm-3) and a suitable TN (800°C) exhibit a steep A.S.S. ~96 mV/dec. and a large EOBD~12.1 MV/cm.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Counter-Doped Multizone Junction Termination Extension Structures in
           Vertical GaN Diodes

    • Authors: Mohammed Shurrab;Amna Siddiqui;Shakti Singh;
      Pages: 287 - 294
      Abstract: GaN is an attractive wide bandgap semiconductor for power applications, owing to its superior electrical properties, such as high critical electric field and saturation drift velocity. Recent advancements in developing native GaN substrates has drawn attention toward exploring vertical GaN power diodes with high breakdown voltages (VBR). In practice, effective edge terminations techniques, such as junction termination extension (JTE) structures, play a crucial role in realizing high-voltage devices. Though certain challenges in fabricating GaN diodes, such as difficulty in forming p-type region, makes it difficult to realize edge termination, hence impeding the development and adoption of such devices. This paper aims to address these challenges by presenting the design and methodology of forming multi-zone, counterdoped JTE structures in vertical GaN diodes, which attains close to theoretical breakdown voltage for a wide range of tolerance in implant dose variation. Extensive device simulations using experimental data and including the effects of surface charges and implant profiles, are performed to present realistic results. The results suggest that>80% of ideal VBR is achievable for a wide range of doping concentration (2.4 × 1017 cm-3) with a maximum VBR reaching 96% of the ideal value. This paper serves as the first step toward leveraging the current challenges in the fabrication of GaN diodes, by proposing optimum design techniques for realizing vertical GaN diodes with high breakdown voltages.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric
           Properties Variation on Negative Capacitance FETs

    • Authors: Vita Pi-Ho Hu;Pin-Chieh Chiu;Yi-Chun Lu;
      Pages: 295 - 302
      Abstract: In this paper, the impacts of work function variation (WFV), line-edge roughness (LER), and ferroelectric properties variation on the threshold voltage, subthreshold swing (SS), Ion, and Ioff variations are analyzed comprehensively for negative capacitance ultra-thin body SOI MOSFETs (NCSOI) compared with SOI MOSFETs (SOI). For LER induced threshold voltage variation (σVt), NC-SOI MOSFETs exhibit smaller σVt (= 3.8 mV) than the SOI MOSFETs (σVt = 17.6 mV). For analyzing WFV of NC-SOI MOSFETs, two scenarios are considered including (I) same WFV patterns, and (II) different WFV patterns between the external and internal metal gates. Compared with SOI, NC-SOI with scenario (I) exhibits comparable WFV induced σVt (= 16.2 mV), and NC-SOI with scenario (II) exhibits larger WFV induced σVt (= 28.5 mV). In scenario (II), different WFV patterns between the internal and external gates result in VFE (voltage drop across the ferroelectric layer) variations, which increases the WFV induced σVt for NC-SOI. LER dominates energy-delay product variations (σEDP), and NC-SOI MOSFETs show smaller σEDP than SOI MOSFETs. Besides, NC-SOI MOSFETs with thicker ferroelectric layer thickness (TFE), larger coercive electric field (EC), and smaller remnant polarization (P0) show smaller LER induced σVt and σSS. Ferroelectric properties variations show negligible impact on the WFV induced σVt and σSS.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Rapidly Measuring Charge Carrier Mobility of Organic Semiconductor Films
           Upon a Point-Contact Four-Probes Method

    • Authors: Dongfan Li;Shengtao Li;Wanlong Lu;Shi Feng;Peng Wei;Yupeng Hu;Xudong Wang;Guanghao Lu;
      Pages: 303 - 308
      Abstract: Field-effect mobility (μFET) of organic semiconductor films plays a key role in the performance of field-effect transistors (FETs). Numerical extraction of μFET from organic FET characteristics is not only time-consuming due to patterning of source/drain electrodes, but also frequently unreliable because of the contact resistances (RC) between source/drain electrodes and semiconductors. Here, we propose an approach to rapidly evaluate μ by a point-contact four-probes method (μPFP) for organic semiconductor films. Four tip-like probes quickly contact the semiconductor film surface directly, without deposition of the conventional source/drain electrodes, to simultaneously inject current and measure the electric potential. The charge density and thus conductance of the film is manipulated upon scanning gate voltage, from which the extraction of μPFP, in good agreement with μFET, could be realized in a few seconds. This method, with easily accessible setup and numerical model, substantially accelerates the evaluation of μPFP, and thus could help screen materials and optimize film morphology for organic FETs applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • IGZO TFT Gate Driver Circuit With Improved Output Pulse

    • Authors: Jin-Ho Kim;Jongsu Oh;Keechan Park;Jae-Hong Jeon;Yong-Sang Kim;
      Pages: 309 - 314
      Abstract: We propose a new gate driver circuit with an improved output pulse using depletion mode amorphous indium gallium zinc oxide thin film transistors. The previous reported gate driver circuit of our group has a weak point. It is that the peak voltage of the output pulse is decreased during the output pulse duration. A peak voltage drop of output pulse is larger by an increase the leakage current of the pull-down transistor as an increase of the threshold voltage (Vth) in the negative direction. Also, a power consumption is increase by that. In this paper, the new gate driver circuit is proposed to solve this weak point. The peak voltage drop of the output pulse of the new gate driver circuit is not occurred as an increase of the pull-down transistor Vth in the negative direction. The peak voltage of the output pulse of the previous reported circuit is 27.5 and 26.2 V at the transistor Vth of 0.5 and -2.9 V, respectively. However, the peak voltage of the output pulse of the new gate driver circuit is 27.8 and 27.6 V at the transistor Vth of 0.5 and -2.9 V, respectively.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Automatic Fault Detection Circuit for Integrated Gate Drivers of
           Active-Matrix Displays

    • Authors: Byung-Chang Yu;Jongbin Kim;Seung-Hyuck Lee;Hoon-Ju Chung;Seung-Woo Lee;
      Pages: 315 - 321
      Abstract: This paper presents automatic fault detection circuit for integrated gate drivers. The proposed circuit consists of one capacitor and two TFTs per scan line. The circuit can detect three types of faults, such as line disconnection (LD), low voltage stuck (LVS), and high voltage stuck (HVS) for the gate driver due to external physical stress. Simulation results showed the proposed circuit operates well. In order to verify the circuit operation, it was fabricated with indium gallium zinc oxide thin film transistors process. The measurement results also verified that our proposed fault detection circuit could detect the types and locations of the LD and LVS of the gate driver successfully. However, we found that HVS can be detected, but further study is needed to accurately detect the position of HVS in the proposed circuit.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Contact Engineering of Trilayer Black Phosphorus With Scandium and Gold

    • Authors: Yi-Chia Tsai;Blanka Magyari-Köpe;Yiming Li;Seiji Samukawa;Yoshio Nishi;Simon M. Sze;
      Pages: 322 - 328
      Abstract: High contact resistance keeps black phosphorus (BP) from fully wielding its excellent material property. Using first-principles calculations, we analyze the interfacial binding behavior and the impact of binding on the other layers of a trilayer BP. We found that the interfacial charge density and charge transfer of Scandium (Sc)-contacted trilayer BP are 2.67 and 3.29 times greater than Au-contacted trilayer BP, respectively. Moreover, the interfacial tunneling barrier height and width of Sc-contacted trilayer BP are 0 eV and 1.851 Å, which are significantly smaller than that of 5.1 eV and 2.447 Å observed in Au-contacted trilayer BP. All these facts suggest a strong bonding and efficient carrier transmission between Sc contact and trilayer BP substrate. Therefore, we conclude that the Sc electrode can lead to a superior performance that is consistent with the experiment.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency

    • Authors: Bhawna Tiwari;Pydi Ganga Bahubalindruni;Ana Santa;Jorge Martins;Priyanka Mittal;João Goes;Rodrigo Martins;Elvira Fortunato;Pedro Barquinha;
      Pages: 329 - 334
      Abstract: This paper presents the experimental characterization of different rectifier circuits using indium-gallium-zinc-oxide thin-film transistor technologies either at NFC or a high frequency range (13.56 MHz) of RFID. These circuits include a single ended rectifier, its differential counterpart, a bridge rectifier, and a cross-coupled full wave rectifier. Diodes were implemented with transistors using conventional processing steps, without requiring short channel devices (L=15 μm). Hence, there is no need for either extra masks or processing steps unlike the Schottky diode-based implementation. These circuits were fabricated on a PEN substrate with an annealing temperature not exceeding 180°C. This paper finds a direct application in flexible low-cost RFID tags since they enable integration of the required electronics to implement tags with the same fabrication steps.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Near-Linear Potentiation Mechanism of Gated Schottky Diode as a Synaptic

    • Authors: Jong-Ho Bae;Suhwan Lim;Dongseok Kwon;Jai-Ho Eum;Sung-Tae Lee;Hyeongsu Kim;Byung-Gook Park;Jong-Ho Lee;
      Pages: 335 - 343
      Abstract: The operation principle and near-linear potentiation mechanism of reconfigurable gated Schottky diodes (GSDs) are analyzed using calibrated device simulation. The reconfigurable GSD has two bottom gates and SiO2/Si3N4/SiO2 gate insulator stack. According to the polarity of the bottom gate bias, electrons, or holes are induced in the poly-Si active layer and the type of Schottky diodes is reconfigured. In the same manner, the reverse-biased current of GSD is modulated by applying bottom gate bias or storing charge in the Si3N4 charge storage layer. The reverse-biased current of GSD is exponentially proportional to the charge stored in the Si3N4 layer. By representing the amount of stored charge as a logarithmic relation to the number of potentiation pulses, the number of potentiation pulses, and the current of GSD has a power relation. It has been demonstrated that the GSD current exhibits near-linear potentiation characteristics when the exponent of the power relation is close to 1.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $Delta+V_{text{DIBLSS}}/(I_{text{on}}/I_{text{off}})$+ +and++$Delta+V_{text{DIBL}}/(I_{text{on}}/I_{text{off}})$+ &rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Yi-Chuen&;Luke+Hu;Tzu-Feng+Chang;Chih-Yi+Wang;Steven+Hsu;Osbert+Cheng;Chien-Ting+Lin;Yu-Shiang+Lin;Zen-Jay+Tsai;Ted+Wang;Touber+Tseng;Chih-Wei+Yang;Chin-Yang+Hsieh;">Monitoring of FinFET Characteristics Using $Delta
           V_{text{DIBLSS}}/(I_{text{on}}/I_{text{off}})$ and $Delta

    • Authors: Yi-Chuen Eng;Luke Hu;Tzu-Feng Chang;Chih-Yi Wang;Steven Hsu;Osbert Cheng;Chien-Ting Lin;Yu-Shiang Lin;Zen-Jay Tsai;Ted Wang;Touber Tseng;Chih-Wei Yang;Chin-Yang Hsieh;
      Pages: 344 - 350
      Abstract: In this paper, we present a descriptive analysis of a performance index, ΔVDIBLSS/(Ion/Ioff), used for performance monitoring. Scaled nand p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified ΔVDIBL/(Ion/Ioff) for monitoring the electrical characteristics of MOSFET devices is proposed due to the “quick measurements” required in the last step of the semiconductor manufacturing process. ΔVDIBL/(Ion/Ioff) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for ΔVDIBL/(Ion/Ioff) is much quicker than for ΔVDIBLSS/(Ion/Ioff), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as Ion/Ioff and intrinsic gain, gm × ro, are reported using ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff). ΔVDIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since Ion/Ioff is a sensitive function of threshold voltage, the estimates of the ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are hard to achieve.-However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation of a Hybrid Approach for Normally-Off GaN HEMTs Using
           Fluorine Treatment and Recess Etch Techniques

    • Authors: Gokhan Kurt;Melisa Ekin Gulseren;Gurur Salkim;Sertac Ural;Omer Ahmet Kayal;Mustafa Ozturk;Bayram Butun;Mehmet Kabak;Ekmel Ozbay;
      Pages: 351 - 357
      Abstract: A hybrid approach for obtaining normally off high electron mobility transistors (HEMTs) combining fluorine treatment, recess etch techniques, and AlGaN buffer was studied. The effects of process variations (recess etch depth and fluorine treatment duration) and epitaxial differences (AlGaN and carbon doped GaN buffers) on the DC characteristics of the normally off HEMTs were investigated. Two different epitaxial structures and three different process variations were compared. Epitaxial structures prepared with an AlGaN buffer showed a higher threshold voltage (Vth = +3.59 V) than those prepared with a GaN buffer (Vth = +1.85 V).
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Assessment and Optimization of the Circadian Performance of
           Smartphone-Based Virtual Reality Displays

    • Authors: Tingzhu Wu;Shijie Liang;Lili Zheng;Yue Lin;Ziquan Guo;Yulin Gao;Yijun Lu;Sung-Wen Huang Chen;Chun-Fu Lee;Jia-Rou Zhou;Hao-Chung Kuo;Zhong Chen;
      Pages: 358 - 367
      Abstract: The non-visual effects of blue light in displays mean that excessive use of smartphones can disturb the human circadian rhythm. Thus, the impact of virtual reality (VR) headsets, which are worn closer to the human eye, may be even more serious. In this paper, based on non-visual parameters, such as the circadian action factor (CAF) and circadian illuminance, the circadian performance of smartphone-based VR displays is quantitatively evaluated by an evaluation system we designed. Moreover, we investigate the improvements in the circadian performance of VR headsets resulting from three practical methods for reducing the blue light content. Finally, a theoretical method of shifting the green-light wavelength of the screen close to 555 nm to optimize the CAF of VR headsets is proposed. Overall, the results of this paper are of significant value in quantifying the effects of VR displays on circadian rhythms and improving the safety of VR headsets with regard to human health.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • On the Physical Mechanism of Transient Negative Capacitance Effect in Deep
           Subthreshold Region

    • Authors: Chengji Jin;Takuya Saraya;Toshiro Hiramoto;Masaharu Kobayashi;
      Pages: 368 - 374
      Abstract: We have investigated the physical mechanism of steep subthreshold slope (SS) in ferroelectric FET (FeFET) based on a dynamic ferroelectric (FE) model without traversing the negative capacitance (NC) region of the S-shaped polarization-voltage predicted by Landau theory. The dynamic FE model is applied to an FE-dielectric (FE-DE) series capacitor as well as FeFET after calibration and verification by transient measurement of an FE-HfO2 capacitor. By investigating current through the FE-DE series capacitor and the gate capacitor of FeFET, we find that incomplete screening of spontaneous polarization charge results in transient NC and sub-60 mV/dec SS. Also, it should be noted that, for FeFET, small depletion layer capacitance has an important role to cause strong depolarization effect and thus steep SS. Moreover, reverse drain induced barrier lowering happens even with this FE model. The model presented in this paper provides a reasonable interpretation for the previously reported steep SS of NC FETs.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • ZnON MIS Thin-Film Diodes

    • Authors: Mohamad Hazwan Mohd Daut;John F. Wager;Arokia Nathan;
      Pages: 375 - 381
      Abstract: Zinc oxynitride metal-insulator-semiconductor diodes are fabricated and characterized. Although these devices display excellent rectification, their temperature-dependent current-voltage characteristics are not explicable using analysis methodologies currently available in the literature. Therefore, we employ a simple curve fitting strategy in order to elucidate measured trends. It is found that the forward current trends are describable using three parameters, i.e., reverse saturation current, ideality factor, and series resistance, whereas the reverse current temperature dependence only requires one parameter, i.e., shunt resistance. All four of these model parameters are found to be strongly temperature dependent.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • The Effect of Tungsten Volume on Residual Stress and Cell Characteristics
           in MONOS

    • Authors: Young-Taek Oh;Jae-Min Sim;Hisashi Kino;Deok-Kee Kim;Tetsu Tanaka;Yun-Heub Song;
      Pages: 382 - 387
      Abstract: The effect of residual stress during the tungsten deposition process were investigated using metal-oxide-nitride-oxide-semiconductor (MONOS) devices. The variation of residual stress due to tungsten volume was measured under tensile and compressive stress conditions. Residual stress increased in proportion to the deposition volume. Stress influenced the Si/SiO2 interface and caused deterioration of the electrical properties, which was experimentally observed during measurements of the interface trap densities and memory windows. We confirmed that residual stress led to degradation of the cell characteristics of MONOS devices, and the absolute value of stress significantly affected these issues regardless of the polarity. From our experiments results, we can predict the degradation of cell characteristics in memory devices, and confirm the need for appropriate stress control in manufacturing process.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Low-Power Thin-Film Si Heterojunction FET Noise Amplifier for Generation
           of True Random Numbers

    • Authors: Bahman Hekmatshoar;Ghavam G. Shahidi;
      Pages: 388 - 392
      Abstract: A low-power noise amplifier is implemented with thin-film Si heterojunction field-effect transistors (HJFETs) and its suitability for generation of true random numbers is investigated. The HJFETs are operated at near subthreshold to obtain a large output resistance and therefore a high intrinsic gain at a low operation power. It is found that the noise output of a proof-of-concept 4-stage amplifier with a voltage gain of ~5000, bandwidth of ~1 KHz, power consumption of ~100 nW, and a dc-blocking output capacitance of 250 pF is suitable for generation of statistically true random numbers at a rate of 100 bit/s without requiring post-processing. The described technique may find application in emerging technologies, such as large-area, flexible, and/or wearable devices that benefit from enhanced security and low-power computing.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas

    • Authors: N. André;M. Rack;L. Nyssens;C. Gimeno;D. Oueslati;K. Ben Ali;S. Gilet;C. Craeye;J.-P. Raskin;D. Flandre;
      Pages: 393 - 397
      Abstract: In this paper, measurements and simulations of miniature monopole antennas for ultra-wideband (UWB) GHz intra- and inter-chips communication and biomedical applications are presented. Folded designs on four substrates are studied: 1) standard bulk; 2) high-resistivity bulk; 3) ultra low-loss radiofrequency silicon-on-insulator (RF SOI); and 4) quartz. Among the Si-based substrates, RF SOI with its trap-rich sublayer demonstrates the best performances with the lowest RF power losses and centimetric transmission distance between antennas. Transmitted power between two antennas was measured from 0.01 to 20 GHz. Using substrate characterization of resistivity, permittivity, and loss tangent based on measured coplanar waveguide lines on the same substrates, good agreement is obtained between the return losses of simulated antennas on each substrate and numerical solutions, confirming the impact of the substrate properties. An antenna bandwidth of 680 MHz is demonstrated at 6.0 GHz meeting the criterion for UWB radio communications in the 6-10 GHz band.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • A Complete Small-Signal MOSFET Model and Parameter Extraction Technique
           for Millimeter Wave Applications

    • Authors: Yang Cao;Wei Zhang;Jun Fu;Quan Wang;Linlin Liu;Ao Guo;
      Pages: 398 - 403
      Abstract: In this paper, we propose a parameter extraction method for a complete MOSFET small signal equivalent circuit model addressing nearly all the parasitic and non-quasi-static (NQS) effects. Extraction and de-embedding of drain/source/gate series resistances and the substrate network are found to be necessary for obtaining the intrinsic elements of the small-signal equivalent circuit. We demonstrate for the first time, a step-by-step procedure for the extraction and de-embedding of the extrinsic model parameters directly from measurements. As a result, a precise intrinsic parameters derivation in the saturation region is presented. Moreover, for the intrinsic small signal equivalent circuit, a gate drain branch is supplemented in parallel to describe parasitic gate-drain coupling under high frequency up to 60 GHz together with the NQS effects. Finally, the presented parameter extraction method is verified by comparing with the corresponding measurement data from the 40-nm RF CMOS process of Shanghai Huali Microelectronics Corporation.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • $I-V$+ +Linearity+in+TaOx-Based+RRAM+Devices+for+Neuromorphic+Applications&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Changhyuck&;Andrea+Padovani;Bastien+Beltrando;Donguk+Lee;Myunghoon+Kwak;Seokjae+Lim;Luca+Larcher;Vincenzo+Della+Marca;Hyunsang+Hwang;">Investigation of $I-V$ Linearity in TaOx-Based RRAM Devices for
           Neuromorphic Applications

    • Authors: Changhyuck Sung;Andrea Padovani;Bastien Beltrando;Donguk Lee;Myunghoon Kwak;Seokjae Lim;Luca Larcher;Vincenzo Della Marca;Hyunsang Hwang;
      Pages: 404 - 408
      Abstract: We perform experiments and device simulations to investigate the origin of current-voltage (I-V) linearity of TaOX-based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the electrical characteristics (linear or nonlinear I-V) to the microscopic properties of the conductive filament (CF). Our findings indicate that the shape and the thermal properties of the CF region are crucial to achieve linear I-V characteristics. These results allow optimizing the I-V curve linearity of TaOX-based RRAM devices, explaining the wide range of linear I-V characteristics experimentally observed on RRAM device obtained. When weight sum operation using SPICE simulations is performed, the read current is improved under the condition of linear I-V characteristics due to current loss minimization.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Compact Charge Modeling of Double-Gate MOSFETs Considering the
           Density-Gradient Equation

    • Authors: Sung-Min Hong;
      Pages: 409 - 416
      Abstract: A compact charge model for double-gate metal-oxide-semiconductor field-effect transistors with the quantum confinement effect is presented. In addition to the Poisson equation, the density-gradient equation with a realistic boundary condition is considered to include the quantum confinement effect. The coupled governing equations are rigorously integrated. Contribution of the density-gradient equation is clearly identified. Based on the resultant integrated equation, a compact charge model is proposed. Expressions for model parameters are found. Numerical examples for various double-gate MOS structures are shown.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Investigation on the Activation Energy of Device Degradation and Switching
           Time in AlGaN/GaN HEMTs for High-Frequency Application

    • Authors: Jianming Lei;Rui Wang;Guo Yang;Jin Wang;Dunjun Chen;Hai Lu;Rong Zhang;Youdou Zheng;
      Pages: 417 - 424
      Abstract: In this paper, the influence of traps on the dynamic on-resistance (Rdson) and switching time of AlGaN/GaN high-electron-mobility transistors is validated by means of a switching power converter with floating buck-boost topology. A new scheme based on the voltage-dependent dynamic Rdson is proposed to extract the average activation energy of device degradation. The average activation energy obtained is 2.25 eV at 50-200 V and 2.60 eV at 200-600 V. In addition, the dynamic Rdson is accurately extracted by a unique extraction circuit with high switching frequency up to 1 MHz and high off-state voltage up to 600 V. Meanwhile, the switching times at turn-on and turn-off transitions are captured in a floating buck-boost converter, showing that the transconductance decreases with increasing drain voltage. Furthermore, the effect of parasitic output capacitor on the dynamic Rdson is investigated by an experimental method. Finally, a proper hard operating mode is proposed to alleviate the influence of the trapping effect on the performance of switching power converters.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Evaluation of Bulk and SOI FeFET Architecture for Non-Volatile Memory

    • Authors: Antik Mallick;Nikhil Shukla;
      Pages: 425 - 429
      Abstract: The stress induced by the capping electrode is critical to stabilizing the ferroelectric phase in Si-doped HfO2 which is being actively explored for embedded non-volatile memory applications. While TiN is commonly used as the electrode of choice owing to its thermodynamic stability with HfO2, its work function (WF) (=4.8eV) results in reduced memory window (MW), and higher interlayer field ( $text{E}_{mathrm{ IL}}$ ) in bulk Ferroelectric FETs (FeFETs). This is attributed to the built-in electric-field that arises from the WF difference between the metal and the semiconductor. This effectively reduces the ferroelectric hysteresis, and thus, the MW at the read current. Optimizing the MW and the $text{E}_{mathrm{ IL}}$ would entail changing the WF, and thus, the capping electrode—essential to retaining the desired ferroelectric properties. We, therefore, propose using the silicon on insulator (SOI)-FeFET architecture which provides an additional knob—back-gate bias ( $text{V}_{mathrm{ bg}}$ )—to optimize the MW while reducing the $text{E}_{mathrm{ IL}}$ . Further, we show that unlike the bulk FeFET, where a small deviation from the optimal WF dramatically shrinks the MW, the SOI-FeFET facilitates a relatively constant MW over a wide range of $text{V}_{mathrm{ bg}}$ . Thus, the SOI-FeFET simplifies the MW & $text{E}_{mathrm{ IL}}$ optimization and provides an improved MW versus $text{E}_{mathrm{ IL}}$ trade-off in comparison to the bulk FeFET.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Improved Ultraviolet Detection and Device Performance of Al2O3-Dielectric
           In0.17Al0.83N/AlN/GaN MOS-HFETs

    • Authors: Ching-Sung Lee;Xue-Cheng Yao;Yi-Ping Huang;Wei-Chou Hsu;
      Pages: 430 - 434
      Abstract: Ultraviolet (UV) detection and electrical characteristics of In0.17Al0.83N/AlN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOS-HFETs) with Al2O3 gate-dielectric and passivation formed by using ultrasonic spray pyrolysis deposition (USPD) are studied with respect to a conventional Schottky-gate HFET. The present MOS-HFET (Schottky-gate HFET) has demonstrated superior spectral responsivity (SR) of 360 (340) A/W at 350 nm at $V_{mathrm{ GS}} = 5$ (3) V and $V_{mathrm{ DS}} = 6$ (7) V, maximum drain–source saturation current density ( $I_{mathrm{ DS, max}}$ ) of 810.5 (546.6) mA/mm, maximum extrinsic transconductance of ( $g_{m, max }$ ) of 180.4 (221.2) mS/mm, gate-voltage swing (GVS) of 2.4 (0.5) V, on/off current ratio ( $I_{mathrm{ on}}/I_{mathrm{ off}}$ ) of $5.5 times ,,10^{8}$ ( $1.7 times ,,10^{5}$ ), two-terminal off-state gate–drain breakdown voltage (BVGD) of −158.5 (−127) V, three-terminal drain–source breakdown voltage (BVDS) of 162 (83.4) V at $V_{mathrm{ GS}} = -10$ V, and power-added efficiency (P.A.E.) of 26.3% (16.5%) at 2.4 GHz at 300 K. In addition to the improved device performance, this paper demonstrates, for t-e first time, the UV sensing based on an InAlN/AlN/GaN MOS-HFET design.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Improving the Scalability of SOI-Based Tunnel FETs Using Ground Plane in
           Buried Oxide

    • Authors: Shelly Garg;Sneh Saurabh;
      Pages: 435 - 443
      Abstract: Tunnel field-effect transistors (TFETs) are known to exhibit degraded electrical characteristics at smaller channel lengths, primarily due to direct source-to-drain band-to-band tunneling (BTBT). In this paper, we propose a technique to suppress direct source-to-drain BTBT by increasing the effective distance between the source and the drain. We propose to add a ground plane (GP) in the buried oxide of a silicon-on-insulator (SOI) TFET which depletes the drain and increases the effective source-to-drain distance. Using 2-D device simulations it is shown that the introduction of the ground plane is effective in reducing OFF-state current and ambipolar current, as well as, in improving the average subthreshold swing for the small channel length SOI-TFETs. Additionally, the addition of GP is helpful in ameliorating the short-channel effects, such as drain-induced barrier lowering and threshold voltage roll-off.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Operation Up to 500 °C of Al0.85Ga0.15N/Al0.7Ga0.3N High Electron
           Mobility Transistors

    • Authors: Patrick H. Carey;Fan Ren;Albert G. Baca;Brianna A. Klein;Andrew A. Allerman;Andrew M. Armstrong;Erica A. Douglas;Robert J. Kaplar;Paul G. Kotula;Stephen J. Pearton;
      Pages: 444 - 452
      Abstract: AlGaN channel high electron mobility transistors (HEMTs) are the potential next step after GaN channel HEMTs, as the high aluminum content channel leads to an ultra-wide bandgap, higher breakdown field, and improved high temperature operation. Al0.85Ga0.15N/Al0.7Ga0.3N (85/70) HEMTs were operated up to 500 °C in ambient causing only 58% reduction of dc current relative to 25 °C measurement. The low gate leakage current contributed to high gate voltage operation up to +10 V under Vds = 10 V, with $text{I}_{mathrm{ ON}}/text{I}_{mathrm{ OFF}}$ ratios of $> 2 times 10^{11}$ and 3 $times ,,10^{6}$ at 25 and 500 °C, respectively. Gate-lag measurements at 100 kHz and 10% duty cycle were ideal and only slight loss of pulsed current at high gate voltages was observed. Low interfacial defects give rise to high quality pulsed characteristics and a low subthreshold swing value of 80 mV/dec at room temperature. Herein is an analysis of AlGaN-channel HEMTs and their potential future for high power and high temperature applications.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
  • Impacts of HfO2/ZnO Stack-Structured Charge-Trap Layers Controlled by
           Atomic Layer Deposition on Nonvolatile Memory Characteristics of
           In-Ga-Zn-O Channel Charge-Trap Memory Thin-Film Transistors

    • Authors: So-Yeong Na;Sung-Min Yoon;
      Pages: 453 - 461
      Abstract: We fabricated the charge-trap memory thin film transistors (CTM-TFTs) using InGaZnO (IGZO) active channel and HfO2/ZnO stack-structured charge-trap layer (CTL). To investigate the effects of the number and thickness of HfO2 layers inserted between the ZnO within the stack structured CTLs on the device characteristics, 2-nm-thick HfO2 thin films were inlaid once, twice, and four times, and 4-nm-thick HfO2 layers were introduced twice between the ZnO layers. The CTM-TFTs using the stack structured CTLs with 4-nm-thick HfO2 layers showed good memory characteristics, including large memory window (MW) of 25 V and rapid program/erase (P/E) speed of 500 $mu text{s}$ because of high total trap density of HfO2 with a sufficient thickness to provide charge-trap centers. On the contrary, relatively narrow MW of 16 V and slower P/E speed of 100 ms were obtained for memory device using the stacked CTL with four HfO2 layers of 2 nm. The HfO2 layer with a thickness as thin as 2 nm was supposed to act as just dielectric films deactivating the trapping or migration of electron charges due to too thin film thickness. The gate-stack structures confirmed from STEM images suggested that the modulations in memory device characteristics with different CTL structures resulted from the variations in designs of stack structured CTLs when the interface qualities within the gate-stacks were well prepared. Moreover, the detailed fabrication conditions were found to be important control parameters to reproducibly obtain reliable memory device characteristics.
      PubDate: 2019
      Issue No: Vol. 7 (2019)
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Tel: +00 44 (0)131 4513762
Fax: +00 44 (0)131 4513327
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