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  Subjects -> ELECTRONICS (Total: 175 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 76)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 305)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 35)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 44)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 253)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 104)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 85)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 91)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 50)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 2)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 185)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 96)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 65)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 69)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 55)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 39)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 70)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 11)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 45)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 57)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 12)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 23)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 162)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 6)
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 8)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Journal Cover
IEEE Journal of the Electron Devices Society
Journal Prestige (SJR): 1.016
Citation Impact (citeScore): 3
Number of Followers: 9  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2168-6734
Published by IEEE Homepage  [191 journals]
  • IEEE Journal of the Electron Devices Society publication information

    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Dec. 2018
      Issue No: Vol. 6 (2018)
  • IEEE Journal of the Electron Devices Society information for authors

    • Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
      PubDate: Dec. 2018
      Issue No: Vol. 6 (2018)
  • Editorial Toward Faster Publishing and Shorter Turnaround Time

    • Authors: Mikael Östling;
      Pages: 1 - 1
      Abstract: As you all have heard our impact factor has developed very well and is now at 3.14. In addition, we are also reaching higher positions in the open access popularity and JEDS is now the 3rd largest IEEE OA journal (October 2017). We have already seen the increased attention to publish in our journal. This puts of course a higher pressure on our editors and reviewers. I’m planning to recruit a few more editors during the year to cover the increased manuscript flow and also to widen the range of subject fields that we have within the EDS. We already have a rather competitive turnaround time from submission to publish but things can always be faster. The requested response time is down at 2 weeks for review of regular contributions. Let’s keep as a promise to fight any unnecessary delays.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • NbO2-Based Frequency Storable Coupled Oscillators for
           Associative Memory Application

    • Authors: Donguk Lee;Euijun Cha;Jaehyuk Park;Changhyuck Sung;Kibong Moon;Solomon Amsalu Chekol;Hyunsang Hwang;
      Pages: 250 - 253
      Abstract: Oscillatory neural networks with nano-oscillators and synapse devices are a promising alternative to implement neuromorphic systems owing to its fast recognition speed and low power consumption. In this paper, we demonstrate a compact frequency storable oscillator using nanoscale two-terminal NbO2 insulator-metal-transition devices along with TaOx-based resistive switching memory (RRAM) devices. By controlling RRAM resistance, we realized a wide range of analog oscillation frequencies. The synchronization window of two coupled oscillators, which is a key parameter for determining pattern recognition, increases with the increasing coupling capacitance and decreasing RRAM resistance of the reference oscillator. The simple device structure (metal-NbO2-metal-TaOx-metal), small device area (4F2), and frequency storability of NbO2-based coupled oscillator device show a strong potential for future integrated neuromorphic device application.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • InGaAs/AlAs Resonant Tunneling Diodes for THz Applications: An
           Experimental Investigation

    • Authors: Saad G. Muttlak;Omar S. Abdulwahid;J. Sexton;Michael J. Kelly;Mohamed Missous;
      Pages: 254 - 262
      Abstract: This paper presents an experimental study of InGaAs/AlAs resonant tunneling diodes designed to improve the diode characteristics using five different device structures. A promising high peak to valley current ratio of 5.2 was obtained for a very low current density device. As expected, the measured results show a significant increase in the current density with thinner barriers and quantum well widths. This is, however, at the expense of an increase in the peak voltages for high peak current density devices. A 36-mV/μm2 voltage deviation was found for a diode with a peak current density of 10.8 mA/μm2 that we attribute to self-heating of the diodes, and which were confirmed using pulsed dc voltage tests. To demonstrate how the self-oscillation at low frequency can be eliminated, a 25 Ω resistor was integrated in parallel with the diodes. The experimental findings suggest that the partially stabilizing resistor is limited by the absolute value of the negative differential resistance. The equivalent circuit of the diodes was validated using on-wafer S-parameter measurements up to 40 GHz. An estimated high frequency operation limit of 2.7 THz was deduced for RTD sample #327.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors
           in Standard CMOS

    • Authors: Harald Homulle;Lin Song;Edoardo Charbon;Fabio Sebastiano;
      Pages: 263 - 270
      Abstract: Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a significant reduction in current gain and a substantial increase in the base resistance. On the contrary, MOS devices show more stable performance even down to 4 K, but accurate device characterization for the design of such a circuit is currently missing. We present the characterization and analysis over the temperature range from 4 K to 300 K of both substrate bipolar PNP transistors and MOS transistors in standard and dynamic threshold MOS (DTMOS) configurations implemented in a standard 0.16-μm CMOS technology. These results demonstrate that employing MOS or DTMOS enables the operation of bandgap references and temperature sensors in standard CMOS technologies even at deep-cryogenic temperatures.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Analysis and Simulation of Low-Frequency Noise in Indium-Zinc-Oxide
           Thin-Film Transistors

    • Authors: Yuan Liu;Hongyu He;Rongsheng Chen;Yun-Fei En;Bin Li;Yi-Qiang Chen;
      Pages: 271 - 279
      Abstract: Low-frequency noise (LFN) is investigated in a set of indium-zinc-oxide thin-film transistors (IZO TFTs) with fixed channel width (W = 10 μm) and different channel lengths (L = 10, 20, 30, and 40 μm) from sub-threshold, linear to saturation regions. The drain current noise power spectral density is measured as a function of effective gate voltage and drain current. The variation slopes of normalized noise with effective gate voltage are in the range of -1.27 and -1.48, which are close to the prediction of the mobility fluctuation mechanism. According to the ΔN - Δμ model, the flat-band voltage noise spectral density and Coulomb scattering coefficient are extracted. Subsequently, variations of noise with the drain current in the above threshold region are analyzed by considering the band-gap distribution of the tail states. Finally, the BSIM model is also used to model 1/f noise in the IZO TFTs. The noise parameter NOIB is extracted which is inversely proportional to the effective gate voltage. Good agreements are achieved between the simulated and measured results in the linear region.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Experimental Demonstration of a Nonvolatile SRAM With Ferroelectric HfO2
           Capacitor for Normally Off Application

    • Authors: Masaharu Kobayashi;Nozomu Ueyama;Kyungmin Jang;Toshiro Hiramoto;
      Pages: 280 - 285
      Abstract: In order to realize ultralow power Internet-of-Things (IoT) edge devices, standby leakage current must be suppressed because activity of IoT device is very small in an intermittent mode. One of the approaches for ultralow power consumption is normally off computing by utilizing nonvolatile memory. After the discovery of ferroelectricity in HfO2 which is compatible to CMOS integration, ferroelectric nonvolatile memory has been revisited. In this paper, toward normally off computing, we have proposed, designed, and fabricated nonvolatile SRAM integrated with ferroelectric HfO2 capacitor in a simple architecture with two capacitors. Fundamental store and recall operation have been demonstrated. This device technology will open a new path for ultralow power IoT application.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Novel Boosting Scheme Using Asymmetric Pass Voltage for Reducing Program
           Disturbance in 3-Dimensional NAND Flash Memory

    • Authors: Dae Woong Kwon;Junil Lee;Sihyun Kim;Ryoongbin Lee;Sangwan Kim;Jong-Ho Lee;Byung-Gook Park;
      Pages: 286 - 290
      Abstract: In this paper, novel boosting scheme using asymmetric pass voltage (Vpass) is proposed to obtain high channel boosting potential and to reduce program disturbance in 3-D NAND flash memory. The proposed scheme has the same program bias and timing conditions as conventional self-boosting except for Vpass voltages applied to both adjacent word-lines of selected word-line (WLsel). Reduced Vpass (Vpass1 = Vpass - ΔV) is applied to previous word-line (WLn-1) of WLsel and increased Vpass (Vpass2 = Vpass + ΔV) is applied to next word-line (WLn+1). In this scheme, the Vpass1 cuts the channel off and causes local boosting when the channel potentials of inhibit strings are boosted up. Meanwhile, the Vpass2 compensates the program speed reduction of selected cell (cellsel) induced by the decreased voltage of the Vpass1. Through the measurements of program disturbance in fabricated devices, it is revealed that the program disturbance is significantly improved without the reduction of program speed by the proposed scheme. Furthermore, the Vpass1 and Vpass2 are optimized to maximize the improvement.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • On the Formulation of Self-Heating Models for Circuit Simulation

    • Authors: Lining Zhang;Debin Song;Ying Xiao;Xinnan Lin;Mansun Chan;
      Pages: 291 - 297
      Abstract: Different approaches to implement self-heating effects in a compact model are evaluated. The traditional approach using a subcircuit with the addition of an internal node can lead to significant increase in the simulation time. In contrast, by directly solving self-heating equations, the internal node is eliminated in the circuit Jacobian matrix. The resulting simulation time can be shortened in principle up to 60% or more without sacrificing the accuracy. The accuracy and time for self-heating simulations formulated using different approaches are compared in this paper to study their tradeoff. In addition, a generic approach to eliminate the need for internal nodes is proposed and demonstrated using the non-quasi-static effect model.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network

    • Authors: Radhakrishnan Sithanandam;Mamidala Jagadesh Kumar;
      Pages: 298 - 308
      Abstract: For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-insulator (FDSOI), bulk TFET and compared with conventional shallow trench isolation (STI) diode using a well calibrated 3-D technology computer aided design (TCAD) device and process simulation deck. Initial design insights are obtained using the DC characteristics. The quasi-static behavior of a TFET is studied by applying transmission line pulsing (TLP) and very fast TLP (VFTLP) pulses at its drain terminal with gate shorted together and source connected to the ground. During negative TLP pulse at the drain, the TFET becomes a forward biased gated diode and exhibits reduced on-resistance compared to the STI diode. During positive TLP pulse, the tunneling current at the source-channel junction introduces a low impedance current path from drain to source compared to the blocking behavior of the STI diode. A short description of the advantages and challenges of the TFET from ESD perspective are also discussed. Finally, a new TFET ESD network is proposed and shown to exhibit multiple current paths compared to STI diode-based ESD network. From the network simulations, the proposed TFET-based ESD network is shown to exhibit better CDM response and hence providing a robust ESD solution for future system-on-chip design.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Enhanced Hole Injection Into Single Layer WSe2

    • Authors: Michael A. Rodder;Ananth Dodabalapur;
      Pages: 309 - 313
      Abstract: Electronic devices with light-emitting regions composed of single layer transition metal dichalcogenides, such as tungsten diselenide (WSe2), are of great interest due to the formation of a direct bandgap at the single layer limit. Furthermore, increasing injected hole current into the single layer WSe2 is of great importance due to the resulting increase in electroluminescence. In this paper, we demonstrate a 1000× increase in injected hole current into the channel region of an FET composed of a single layer WSe2 channel by incorporation of a thicker (20-30 nm) multilayer WSe2 film under the metal source contact only. By fabrication and analysis of FETs composed of single layer, bi-layer, and tri-layer WSe2 channel regions, we correlate the increase in injected hole current to a decrease in the hole Schottky barrier height at the source contact due to incorporation of the multilayer WSe2 film.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Investigation of Channel Doping Concentration and Reverse Boron

    • Authors: Dong-Ru Hsieh;Yi-De Chan;Po-Yi Kuo;Tien-Sheng Chao;
      Pages: 314 - 319
      Abstract: In this paper, the influence of channel doping concentration and reverse boron penetration on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) FETs has been experimentally investigated and discussed. Effective carrier concentration (Neff) and threshold voltage (VTH) are found to be sensitive to doping concentration. Moreover, the positive shift in VTH and the degradation in the subthreshold behavior for PG JAM FETs are observed after an additional source/drain (S/D) activation process. Using a low thermal-budget S/D activation process, PG JAM FETs with a suitable channel doping concentration can show excellent electrical characteristics: 1) steep subthreshold swing of 86 mV/dec.; 2) low average subthreshold swing (A.S.S.) of 96 mV/dec.; and 3) high ON/OFF current ratio (ION/IOFF) of 7.7 × 107 (ION at VG - VTH = -2 V and VD = -1 V).
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Effects of Al2O3 Capping and Post-Annealing on the Conduction Behavior in
           Few-Layer Black Phosphorus Field-Effect Transistors

    • Authors: H. M. Zheng;J. Gao;S. M. Sun;Q. Ma;Y. P. Wang;B. Zhu;W. J. Liu;H. L. Lu;S. J. Ding;David W. Zhang;
      Pages: 320 - 324
      Abstract: Ambient instability has been proven challenging in black phosphorus field-effect transistors (BP FETs) and a capping layer is thus needed for their practical applications. In this paper, we have examined the effects of Al2O3 capping and O2 post-annealing on the conduction characteristic of BP FETs. With the Al2O3 capping, it forms p-type into ambipolar transport and the electron mobility dramatically increases to 20-110 cm2/V·s in our case. Interestingly, with the O2 post-annealing, the transport can be tuned from ambipolar back to p-type as the annealing time extends. It is attributed that the Al2O3 capping introduces an n-type doping in BP channel while the O2 post-annealing dopes BP back into p-type. Moreover, after the O2 post-annealing the interfacial POx might be formed, resulting in the degradation of subthreshold swing and on/off current ratio.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Dielectric Engineering With the Environment Material in 2-D Semiconductor

    • Authors: Hao Wang;Sheng Chang;Jin He;Qijun Huang;Feng Liu;
      Pages: 325 - 331
      Abstract: A theoretical study that highlights the dielectric constant modulation effect of the surrounding environment material (EM) on 2-D semiconductor devices is presented. With graphene nanoribbon as the vehicle, it is shown that the dielectric constant of the EM can remarkably affect the electrical profiles inside the 2-D material. Using numerical simulations, the effects are illustrated with an unbiased PN junction. The electric potential, electric field, and depletion width are modulated with the EM. Changing the dielectric constant of the EM can be viewed qualitatively as changing the dielectric constant of the 2-D material. It is also demonstrated that the performances of both the MOSFET and the tunnel FET can be boosted with the dielectric engineering of the EM. A new physical insight into the dielectric engineering of 2-D semiconductor devices is presented, which can be utilized to optimize the device performance.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and

    • Authors: Daniel Nagy;Guillermo Indalecio;Antonio J. García-Loureiro;Muhammad A. Elmessary;Karol Kalna;Natalia Seoane;
      Pages: 332 - 340
      Abstract: Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Method to Reduce Forming Voltage Without Degrading Device Performance in
           Hafnium Oxide-Based 1T1R Resistive Random Access Memory

    • Authors: Yu-Ting Su;Hsi-Wen Liu;Po-Hsun Chen;Ting-Chang Chang;Tsung-Ming Tsai;Tian-Jian Chu;Chih-Hung Pan;Cheng-Hsien Wu;Chih-Cheng Yang;Min-Chuan Wang;Shengdong Zhang;Hao Wang;Simon M. Sze;
      Pages: 341 - 345
      Abstract: In this paper, we discover an operation method that can effectively decrease the forming voltage in resistance random access memory (RRAM). Forming voltage can be reduced by either increasing the rising time of the forming-waveform or by increasing the temperature in the forming process. However, the resulting electronic RRAM characteristics after each of these methods differ. While increasing the rising time causes greater damage to the switching layer due to longer accumulation of charge, increasing temperature in the forming process does not. The high temperature-formed RRAM excels in retention and endurance tests, proving an effective means to decrease forming voltage.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Experimental Observation and Simulation Model for Transient

    • Authors: Kyungmin Jang;Nozomu Ueyama;Masaharu Kobayashi;Toshiro Hiramoto;
      Pages: 346 - 353
      Abstract: We have experimentally observed the negative-capacitance transient effect in a ferroelectric HfZrO2 (FE-HZO) capacitor and developed an equivalent circuit model based on the Landau- Khalatnikov (LK) theory. By considering multiple domains (MD) and domain interaction, an MD-LK model precisely reproduced the experimental dynamic characteristics in an FE-HZO capacitor with the various input voltage amplitude and external resistance. The MD-LK model was successfully validated as a dynamic model for FE-HZO capacitor. The MD-LK model is highly expected as a useful simulation model for the dynamic NCFET with a multi-domain FE-HZO gate insulator.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Current Collapse-Free and Self-Heating Performances in Normally Off GaN
           Nanowire GAA-MOSFETs

    • Authors: Ki-Sik Im;Gökhan Atmaca;Chul-Ho Won;Raphaël Caulmilone;Sorin Cristoloveanu;Yong-Tae Kim;Jung-Hee Lee;
      Pages: 354 - 359
      Abstract: Normally off lateral GaN nanowire gate-all-around MOSFETs have been fabricated on the GaN-on-insulator substrate. The dynamic measurement proved that the devices with various nanowire heights exhibit current collapse-free characteristics implying that the electrons in the isolated nanowire channel do not suffer from trapping effects. However, the dc current level measured at high drain and gate voltage is reduced to approximately one half of the value measured in dynamic mode. This is attributed to the difficulty in heat dissipation because the suspended lateral nanowire channel is thermally isolated from the substrate. However, the heat dissipation is mitigated as the nanowire size increases.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Improvement of Power Performance of GaN HEMT by Using Quaternary InAlGaN

    • Authors: Wen Wang;Xinxin Yu;Jianjun Zhou;Dunjun Chen;Kai Zhang;Cen Kong;Yuechan Kong;Zhonghui Li;Tangsheng Chen;
      Pages: 360 - 364
      Abstract: High power performance InAlGaN/GaN high electron mobility transistor (HEMT) as a candidate for high power and high frequency amplifiers has been demonstrated versus the conventional AlGaN/GaN HEMT by using the same device processes. Comparing with its conventional AlGaN/GaN counterpart, the InAlGaN/GaN device exhibits a much larger output current density of 1.94 A/mm due to its higher 2-D electron gas density of 2.0 × 1013 cm-2 by using a thin quaternary InAlGaN barrier layer, and almost twice as large as fT of 142 GHz and fmax of 203 GHz. Through measurements of large-signal characteristics at frequency of 34 GHz and biased at 10 V, the InAlGaN/GaN device shows a high output power density of 2.75 W/mm, which is about 87% increase in comparison with that of its AlGaN/GaN counterpart with an output power density of 1.47 W/mm.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Optimization of Pinned Photodiode Pixels for High-Speed Time of Flight

    • Authors: Fabio Acerbi;Manuel Moreno-Garcia;Gözen Köklü;Radoslaw Marcin Gancarz;Bernhard Büttgen;Alice Biber;Daniel Furrer;David Stoppa;
      Pages: 365 - 375
      Abstract: We discuss optimizations of pinned photodiode (PPD) pixels for indirect time of flight sensors. We focus on the transfer-gate and dumping gate regions optimization, on the PPD dimension and shape to assure fast lateral charge transfer and on the epitaxial layer thickness for a good tradeoff between fast vertical charge transfer and high quantum efficiency at near infrared region. The overall performance of the pixel is quantified by the demodulation contrast of the pixel at specific frequencies. The operation frequency of the device is determined by the required ambiguity range of the application and the required distance noise. In order to reach a reasonable distance noise, the pixel needs to allow modulation frequencies up to 100 MHz. In this paper, we present TCAD simulation and experimental data on demodulation contrast, impulse response time, and quantum efficiency of 10 × 10 μm pixels. We introduce a setup for impulse response measurement and we compare this to the demodulation contrast. We also discuss the optimization of the dump gate and dump diffusion. With the best pixel we measured a quantum efficiency of about 45% at 850 nm, a demodulation contrast of 47% at 80 MHz, and an impulse response time
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Spatiotemporal Summation of a Triple-Terminal Light-Induced Artificial

    • Authors: Xiangfei Shen;Zheng Shi;Shuai Zhang;Bingcheng Zhu;Jialei Yuan;Wei Cai;Yongjin Wang;
      Pages: 376 - 381
      Abstract: In the biological nervous system, repetitive-pulse signals from different presynaptic neurons may correlate to produce a specific association at the postsynaptic neuron for complex neural encoding. Here, the fabrication and characterization of a triple-emitter light-induced synaptic device artificial synapse is proposed to mimic excitatory postsynaptic voltage (EPSV) summation of the biological nervous system. When repetitive-pulse signals with different periods are synchronously applied to three presynaptic terminals, temporal, and spatial EPSV summations lead to synaptic strengthening. Resonant spatiotemporal correlations occur because the continuous activities make the presynaptic inputs correlate with respect to each other. Experimental results demonstrate three different resonant EPSV correlations generated by a combination of each of the two repetitive-pulse signals, which agree well with the simulations based on the convolution operation and the nonlinear distortion function. These results suggest that the multiple-emitter light-induced artificial synapse is promising for the emulation of biological neural networks.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Prospects of Tunnel FETs in the Design of Power Management Circuits for
           Weak Energy Harvesting DC Sources

    • Authors: David Nunes Cavalheiro;Francesc Moll;Stanimir Valtchev;
      Pages: 382 - 391
      Abstract: In this paper, a new tunnel FET (TFET)-based power management circuit (PMC) is proposed for weak dc energy harvesting sources. Thanks to their particular carrier injection mechanisms, TFETs can be used to design efficient energy harvesting circuits by enabling the power extraction from sources which are not only at very low voltage levels (sub-0.1 V) but also at very low power levels (a few nW). As TFET devices are designed as reverse-biased diodes, changes in conventional circuit topologies are required in order to take full advantage of these emerging devices. The circuit design techniques proposed in this paper represent an improvement in output voltage and input power range with respect to previously published TFET-based PMCs. Simulation results show that the TFET-based PMC can sustain itself from a 2.5 nW@50 mV dc source, powering a load at 0.5 V with 29% of efficiency.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Enhancing Near-Infrared Photodetection Efficiency in SPAD With Silicon
           Surface Nanostructuration

    • Authors: Laurent Frey;Michel Marty;Séverine André;Norbert Moussy;
      Pages: 392 - 395
      Abstract: We propose a straightforward technique to increase the near-infrared photo-detection efficiency (PDE) in single photon avalanche photodiodes (SPAD) manufactured in CMOS industrial foundries, without any change in the usual semiconductor process flow. The mask used for the photolithography of shallow trench isolation (STI) is modified to generate sub-wavelength patterns in the silicon area illuminated by incident light. The dimensions of the nanostructures are easily accessible by standard UV-lithography. The resulting improved anti-reflection effect and absorption in Si due to diffraction can provide up to 50% relative gain in PDE at 850-nm wavelength in simulation, while 25% gain is demonstrated in this paper, without degrading the median dark count rate (DCR) at ambient temperature. Some performance degradation is observed with the appearance of after-pulses, possibly due to the absence of surface passivation specific to the nanostructures in this first demonstration. The effect is angularly robust, relatively broadband, and relatively tolerant to fabrication errors. High PDE enables longer range or lower power consumption in applications for distance measurement with an active illumination, such as proximity sensing, 3-D ranging, or 3-D imaging.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • 3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via

    • Authors: Wen-Wei Shen;Yu-Min Lin;Shang-Chun Chen;Hsiang-Hung Chang;Tao-Chih Chang;Wei-Chung Lo;Chien-Chung Lin;Yung-Fa Chou;Ding-Ming Kwai;Ming-Jer Kao;Kuan-Neng Chen;
      Pages: 396 - 402
      Abstract: This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-μm-diameter/50-μm-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-μm diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Compensated Synaptic Device for Improved Recognition Accuracy of
           Neuromorphic System

    • Authors: Chuljun Lee;Sang-Mo Koo;Jong-min Oh;Daeseok Lee;
      Pages: 403 - 407
      Abstract: To improve a pattern recognition accuracy of synaptic device-based neuromorphic system, we tried to obtain symmetric conductance changes between conductance increase process (potentiation) and conductance decrease process (depression). By utilizing compensational voltage division, we achieved more gradual conductance changes during the depression, which led to the symmetric conductance changes between the potentiation and depression. On the basis of the achieved symmetric conductance changes, obviously improved pattern recognition accuracy was obtained on a multilayer perceptron structural simulation.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Method for Determining Trap Distributions of Specific Channel Surfaces
           in InGaAs Tri-Gate MOSFETs

    • Authors: Seiko Netsu;Markus Hellenbrand;Cezar B. Zota;Yasuyuki Miyamoto;Erik Lind;
      Pages: 408 - 412
      Abstract: We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60, and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the {110} side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Drift Field Implementation in Large Pinned Photodiodes for Improved Charge
           Transfer Speed

    • Authors: Donald B. Hondongwa;Eric R. Fossum;
      Pages: 413 - 419
      Abstract: We present a methodology for generating built-in drift fields in large photodiodes. With the aid of TCAD we demonstrate how non-uniform doping profiles can be implemented in a standard CMOS process using a single additional mask and controlled using the implant conditions and mask geometry. We demonstrate that the resulting doping profile creates a built-in drift field and simulates the effect of the drift field on the charge transfer speed. We show that implementing a drift field can improve charge transfer characteristics of the photodiode.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Analysis and Validation of Low-Frequency Noise Reduction in MOSFET
           Circuits Using Variable Duty Cycle Switched Biasing

    • Authors: Kapil Jainwal;Mukul Sarkar;Kushal Shah;
      Pages: 420 - 431
      Abstract: In MOS transistors, low-frequency noise phenomena such as random telegraph signal (RTS), burst, and flicker or 1/f noise are usually attributed to the random nature of the trap state of defects present at the gate Si-SiO2 interface. In a previous work, theoretical modeling and analysis of the RTS and 1/f noise in MOS transistor was presented and it was shown that this 1/f noise power can be reduced by decreasing the duty cycle (D) of switched biasing signal. In this paper, an extended analysis of this 1/f noise reduction model is presented and it is shown that the RTS noise reduction is accompanied with shift in the corner frequency (fc) of the 1/f noise and the value of shift is a function of continuous ON time (Ton) of the device. This 1/f noise reduction is also experimentally demonstrated in this paper using a circuit configuration with multiple identical transistor stages which produce a continuous output instead of a discrete signal. The circuit is implemented in 180 nm standard CMOS technology, from UMC. According to the measurement results, the proposed technique reduces the 1/f noise power by approximately 5.9 dB at switching frequency (fs) of 1 KHz for 2 stage, which is extended up to 16 dB at fs of 5 MHz for six stage configuration.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Thickness Effect on Operational Modes of ZnGa2O4

    • Authors: Li-Chung Cheng;Chiung-Yi Huang;Ray-Hua Horng;
      Pages: 432 - 437
      Abstract: The device mechanism from depletion to enhancement mode for ZnGa2O4 metal-oxide semiconductor field effect transistors (MOSFETs) grown on the sapphire substrate by metalorganic chemical-vapor deposition was studied. It was found that the thickness of the ZnGa2O4 thin-film would affect the operational mode of the MOSFETs. Under the low-voltage operation (VDS = 0.5 V), the transistors exhibited a high on/off ratio from 107 to 104, low subthreshold swing from 150 to 330 mV/dec, high field-effect mobility from 4.2 to 0.054 cm2/V-s and threshold voltages from -17.8 to 4.1 V (using constant current = 1 nA). These electrical properties all depend on the thickness of the ZnGa2O4 thin-film transistors. Finally, the e-mode ZnGa2O4 thin-film transistor with off-state breakdown voltage over 400 V is fabricated.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable
           for SoC Integration

    • Authors: Borna Obradovic;Titash Rakshit;Ryan Hatcher;Jorge Kittl;Rwik Sengupta;Joon Goo Hong;Mark S. Rodder;
      Pages: 438 - 448
      Abstract: A multi-bit digital weight cell for high-performance, inference-only non-GPU-like neuromorphic accelerators is presented. The cell is designed with simplicity of peripheral circuitry in mind. Non-volatile storage of weights which eliminates the need for DRAM access is based on FeFETs and is purely digital. The multiply-and-accumulate operation is performed using passive resistors, gated by FeFETs. The resulting weight cell offers a high degree of linearity and a large ON/OFF ratio. The key performance tradeoffs are investigated, and the device requirements are elucidated.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Suppression of Punch-Through Current in 3 kV 4H-SiC Reverse-Blocking
           MOSFET by Using Highly Doped Drift Layer

    • Authors: Seigo Mori;Masatoshi Aketa;Takui Sakaguchi;Hirokazu Asahara;Takashi Nakamura;Tsunenobu Kimoto;
      Pages: 449 - 453
      Abstract: Low on-resistance 4H-SiC reverse-blocking (RB) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been developed by adopting a non-punch-through (NPT) drift layer in order to suppress the punch-through (PT) current under the reverse-blocking condition. The n-type NPT drift layer was 40-μm thick doped to 3.7 × 1015 cm-3. The forward and reverse breakdown voltages of the fabricated NPT RB MOSFET were 3.6 kV and -3.0 kV, respectively. The differential specific on-resistance was 13.5 mΩ·cm2 at room temperature, which was 33% lower than that of a 3 kV PT RB MOSFET, demonstrating superiority of the developed NPT RB MOSFET as a high-performance bidirectional switch.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Evidence of Bipolar Resistive Switching Memory in Perovskite Solar Cell

    • Authors: Giovanni Landi;Vijaya Subbiah;K. Srinivas Reddy;Andrea Sorrentino;Anandan Sambandam;Praveen C. Ramamurthy;Heinz-Christoph Neitzert;
      Pages: 454 - 463
      Abstract: In hybrid inorganic-organic perovskite solar cells a very stable bipolar resistive switching behavior in the dark current-voltage characteristics at low-voltages has been observed. The possible use of the solar cell as an electrical memory with a moderate on-off contrast but very good stability over a prolonged time has been suggested. The reversible behavior and the long dynamics during the write/erase processes indicate that the physical mechanism behind the switching is related to polarization effects. A detailed analysis of the charge carrier trapping/detrapping, transport, and recombination mechanisms has been performed by taking the ion migration and the consequent charge carrier accumulation within the device into account. The charge transport during the write operation can be described by space-charge-limited conduction process. The formation and subsequent interruption of conducting pathways due to ion migration have been identified as the main cause of the resistive switching within the perovskite material. The strong interaction between the ion movement and the electron transport enables the operation of the perovskite solar cell also as a non-volatile memory.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Graphene Oxide Quantum Dots Embedded Charge Trapping Memory With
           Enhanced Memory Window and Data Retention

    • Authors: Hong Wang;Xiaobing Yan;Xinlei Jia;Zichang Zhang;Chi-Hsiang Ho;Chao Lu;Yuanyuan Zhang;Tao Yang;Jianhui Zhao;Zhenyu Zhou;Mengliu Zhao;Deliang Ren;
      Pages: 464 - 467
      Abstract: Graphene oxide quantum dots (GOQDs) are integrated with a charge trapping layer in a nonvolatile charge trapping memory. The device structures of Pd/SiO2/ZHO/SiO2/Si and Pd/SiO2/ZHO/GOQDs/SiO2/Si are fabricated, measured, and compared. The GOQD-embedded device demonstrates improved memory window size and data retention characteristics. Under a gate sweeping voltage of ±5 V, the memory window of a GOQD-embedded device is 1.67 V, which is 35.7% larger than the same device without using GOQDs. After a retention time of 1.08×104 s, the GOQD-embedded device shows only 1.2% and 3.8% decay in the high-state and low-state capacitances, respectively. The data retention loss of a GOQD-embedded device is reduced by at least 65% when compared to its counterpart, respectively.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Direct Measurement of Active Near-Interface Traps in the
           Strong-Accumulation Region of 4H-SiC MOS Capacitors

    • Authors: Peyush Pande;Sima Dimitrijev;Daniel Haasmann;Hamid Amini Moghadam;Philip Tanner;Jisheng Han;
      Pages: 468 - 474
      Abstract: This brief presents direct electrical measurement of active defects in the strong-accumulation region of N-type 4H-SiC MOS capacitors, which corresponds to the strong-inversion region of N-channel MOSFETs. The results demonstrate the existence of an active defect in the gate oxide, located very close to the SiC surface, with localized energy levels between 0.13 eV and 0.23 eV above the bottom of the conduction band. The observed spatial and energy localizations indicates that this is a well-defined defect.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Development and Fabrication of AlGaInP-Based Flip-Chip Micro-LEDs

    • Authors: Ray-Hua Horng;Huan-Yu Chien;Ken-Yen Chen;Wei-Yu Tseng;Yu-Ting Tsai;Fu-Gow Tarntair;
      Pages: 475 - 479
      Abstract: The fabrication of AlGaInP-based flip-chip micro light-emitting-diodes (LED; emitting area: 4.5 mil × 5 mil) with horizontal electrodes is reported in this paper. The thickness of the epitaxial layer of the thin LED structure was reduced to 50% of that of the traditional thick LED, whereas carrier concentration in the n-type GaAs contact layer was increased to 5×1018 cm-3 to meet the Ohmic contact requirement. At a current injection of 5 mA, the thin LED exhibited a forward voltage, output power, and external quantum efficiency of 1.8 V, 1.9 mW, and 19%, respectively. The optoelectronic performance of the thin LED was as good as that of the traditional thick red LED. The technique proposed by this paper can be used to integrate AlGaInP-based LEDs with nitride LEDs for full-color display applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Punch-Through Stop Doping Profile Control via Interstitial Trapping by
           Oxygen-Insertion Silicon Channel

    • Authors: Hideki Takeuchi;Robert J. Mears;Robert J. Stephenson;Marek Hytha;Daniel Connelly;Pavel Fastenko;Richard Burton;Nyles W. Cody;Doran Weeks;Dmitri Choutov;Nidhi Agrawal;Suman Datta;
      Pages: 481 - 486
      Abstract: Interstitial trapping by oxygen-inserted silicon channel results in blocking of boron and phosphorus transient enhanced diffusion as well as retention of channel boron profiles during the gate oxidation process. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28 nm planar CMOS and 20 nm bulk FinFET devices projected by TCAD are discussed.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Guest Editorial Special Section on the First Electron Devices Technology
           and Manufacturing (EDTM) Conference 2017

    • Authors: Hitoshi Wakabayashi;
      Pages: 485 - 485
      Abstract: The papers in this special section were presented at the first device conference in Asia - Electron Devices Technology and Manufacturing (EDTM) Conference that was held at Toyama International Conference Center, Toyama, Japan from February 28th to March 2nd, 2017.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Pretreatment Effects on High-k/InxGa1–xAs MOS Interface Properties and
           Their Physical Model

    • Authors: Chiaki Yokoyama;Chi-Yu Chang;Mitsuru Takenaka;Shinichi Takagi;
      Pages: 487 - 493
      Abstract: The electrical and physical properties of atomic layer deposition high-k (Al2O3 and HfO2) /InxGa1-xAs (x = 0.53, 0.7, and 1) MOS interfaces with (NH4)Sy, BHF, and HF pretreatment are examined. It is found that, as the In content (x) becomes higher, InxGa1-xAs MOS interfaces with BHF and HF cleaning show better C-V characteristics and lower interface state density (Dit) than with (NH4)Sy pretreatment. Also, the amounts of arsenic oxides, evaluated by X-ray photoelectron spectroscopy, at the high In content Al2O3/InxGa1-xAs MOS interfaces are found to increase with BHF and HF cleaning than with (NH4)Sy cleaning. These results suggest that arsenic oxides can contribute to passivation of high-k/InxGa1-xAs MOS interface defects and the decrease in Dit for x = 0.7 and 1. Finally, we propose a physical model to explain the relationship between possible interface defects responsible for Dit and the pretreatment effects with the different In contents.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current

    • Authors: Min Hee Cho;Namho Jeon;Taek Yong Kim;Moonyoung Jeong;Sungsam Lee;Jong Seo Hong;Hyeong Sun Hong;Satoru Yamada;
      Pages: 494 - 499
      Abstract: This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance such as refresh time (tREF). However, no method is currently available for evaluating variations, which is a serious problem in developing DRAM. Although the average leakage current from a test element group has been used as an index for determining cell leakage, it does not provide the distribution of unit cell leakage current. We find that cell leakage distribution can be calculated from the slope of the retention time-fail bit plot (defined as TF slope). A steep slope indicates a narrow cell leakage distribution, which corresponds to a narrower structural distribution, and therefore a long tREF. Using statistical models and experiments based on extensive data, our results confirm this relationship. Another impact and contribution of TF slope are that the development period can be saved because a wrong decision (which process is better) can be avoided. This method is used successfully as an indicator to estimate selected processes and to facilitate DRAM development.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • High-Mobility and H2-Anneal Tolerant InGaSiO/InGaZnO/InGaSiO Double Hetero
           Channel Thin Film Transistor for Si-LSI Compatible Process

    • Authors: Nobuyoshi Saito;Kentaro Miura;Tomomasa Ueda;Tsutomu Tezuka;Keiji Ikeda;
      Pages: 500 - 505
      Abstract: We demonstrate a high-mobility and H2-anneal tolerant InGaSiO/InGaZnO/InGaSiO double heterochannel (DH) thin film transistor (TFT) for 3-D integration with Si CMOS-LSI applications. A novel oxide semiconductor material, InGaSiO (Si/In ratio> 0.47) was found to exhibit semiconductor property even after H2 annealing at 380 °C, whereas a conventional InGaZnO layer changed into a metallic one. Moreover, the DH channel TFT was operated in an enhancement mode and achieved a high mobility of 30 cm2/Vs after the H2 annealing. The proposed DH channel TFT has a potential as a high-performance back end of line transistor with Si-CMOS process compatibility.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Nano-Structure-Controlled Very Low Resistivity Cu Wires Formed by High
           Purity and Optimized Additives

    • Authors: Jin Onuki;Kunihiro Tamahashi;Takashi Inami;Takatoshi Nagano;Yasushi Sasajima;Shuji Ikeda;
      Pages: 506 - 511
      Abstract: Resistivity increase in nano-level Cu wires is becoming a critical issue for high speed ULSIs. We have established a new manufacturing process utilizing very high purity 9N electrolyte and optimized additives to control nano-structures of Cu wires, and we realized Cu wires for practical use with 50% lower resistivity than those made with the conventional process. Using STEM analyses and phase field simulation, we also ascertained the reason for getting the very low resistivity Cu wires.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • New Compact Electron Cyclotron Resonance Plasma Source for Silicon Nitride
           Film Formation in Minimal Fab System

    • Authors: Tetsuya Goto;Kei-Ichiro Sato;Yuki Yabuta;Shigetoshi Sugawa;Shiro Hara;
      Pages: 512 - 517
      Abstract: A compact magnetic-mirror confined electron cyclotron resonance plasma source for low-damage plasma processings was developed, especially aiming for the realization of high-quality silicon nitride film formation for the sub-micron complementary metal-oxide semiconductor device processes in the minimal fab system. The developed plasma source was installed in the minimal tool, and deposition of silicon nitride film was performed. The magnetic mirror confinement method worked well to excite the high-density plasma with low plasma excitation power of 10 W or less. By adopting the substrate position slightly apart from the core plasma region with the pressure range of 25 Pa, the silicon nitride film having the similar N/Si ratio to the ideal value of Si3N4 could be obtained in the room-temperature deposition. Under this condition, impurity concentration of oxygen in the film could be suppressed less than 1%, which was even smaller than that in the controlled low-pressure chemical-vapor deposited film at 750 °C.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Bipolar Resistive Switching Characteristics in Flexible Pt/MZT/Al Memory
           and Ni/NbO2/Ni Selector Structure

    • Authors: Ke-Jing Lee;Yu-Chi Chang;Cheng-Jung Lee;Li-Wen Wang;Yeong-Her Wang;
      Pages: 518 - 524
      Abstract: The use of a threshold-switching Ni/NbO2/Ni device with a memory-switching Pt/magnesium zirconate titanate/Al device on a flexible substrate was proposed to suppress undesired sneak currents. The proposed flexible one selector and one resistor (1S1R) memory device exhibits a low operation voltage, good ON/OFF ratio of 105, uniform current distribution, excellent flexibility, and stable I-V curve at 85 °C. The good selection and memory properties of the flexible 1S1R memory device are highly promising for high-density and low-power flexible electronic applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Evaluation of Si:HfO2 Ferroelectric Properties in MFM and MFIS

    • Authors: Jackson D. Anderson;Jordan Merkel;David Macmahon;Santosh K. Kurinec;
      Pages: 525 - 534
      Abstract: A 10.5 nm silicon doped HfO2 film is deposited and examined on three different bottom electrodes: a TiN electrode such as would be found in capacitive FeRAM, a lightly doped p-Si substrate as would be present in an FeFET, and an n+ Si electrode. The HfO2 stack deposited on n+ silicon is shown to have a coercive voltage of 2.9 V compared to 1.9 V for the film deposited on TiN. This is shown to be due to a 1.2 nm oxide present at the HfO2/Si interface dropping 36% of the voltage that is applied to the ferroelectric film stack. An FeFET fabricated with the film shows a 0.55 V threshold voltage shift due to ferroelectric polarization charge for a maximum applied gate bias of 5 V. After accounting for non-zero flat-band voltages, a 5 V bias on the transistor gate is shown to correspond to a 5.3 (μC/cm2) remnant polarization in the ferroelectric film. This corresponds with a theoretical maximum threshold voltage shift of 9.46 V, indicating that there is significant room for growth in FeFET performance if materials and processing challenges can be overcome.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring
           Epitaxially Grown Emitter/Collector Regions

    • Authors: Pouya Hashemi;Jeng-Bang Yau;Kevin K. Chan;Tak H. Ning;Ghavam G. Shahidi;
      Pages: 537 - 542
      Abstract: Symmetric lateral NPN bipolar junction transistors on Si-on-insulator having epitaxially grown emitter/collector regions are demonstrated, for the first time. A novel notch-assisted epitaxy scheme has been developed using faceted Si epitaxial (epi) layers as reactive-ion-etch mask to expose the vertical intrinsic-base epi-seeding surfaces and the epi emitter and collector are automatically connected to the extension regions for metal contact and/or for electrical probing. Functional transistors with good quality device I-V characteristics were obtained with post-epi rapid thermal annealing. The results suggest a path forward for devices suitable for low-cost THz electronics applications. Some learning about the fabrication, as revealed from measured device characteristics, are discussed.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Introduction to the Special Section on the 2017 IEEE S3S Conference

    • Authors: Ali Khakifirooz;Nobuyuki Sugii;
      Pages: 540 - 541
      Abstract: The papers in this special section were presented at the 2017 IEEE S3S Conference, which was held Oct. 16 – 19, 2017 in Burlingame, CA.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A SPDT RF Switch Small- and Large-Signal Characteristics on TR-HR SOI

    • Authors: Babak Kazemi Esfeh;Martin Rack;Sergej Makovejev;Frederic Allibert;Jean-Pierre Raskin;
      Pages: 543 - 550
      Abstract: This paper evaluates the small-and large-signal characteristics of a single pole double thru (SPDT) RF antenna switch including its insertion loss, isolation, and nonlinear behavior. It is fabricated on three different types of high resistivity (HR) silicon-on-insulator (SOI) substrates: one standard (HRSOI) and two trap-rich (RFeSI80 and RFeSI90). Using a special test structure, the contribution of substrate and active devices is separated for both in small-and large-signal. It is shown that by using trap-rich substrate technology, a reduction of over 16 dB of 2nd harmonic is achieved compared with HR SOI substrate. In off-state, it is shown that 35 dB increase of harmonic level is due to the nonlinearity of active devices. The effect of body bias on small-and large-signal FoMs of the SPDT is investigated and discussed. It is illustrated that trap-rich HR-SOI substrates having much thinner BOX, still outperform classical HR-SOI wafer.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and

    • Authors: Ramachandran Muralidhar;Robert H. Dennard;Takashi Ando;Isaac Lauer;Terence Hook;
      Pages: 551 - 556
      Abstract: In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate length. We propose a U-channel fully depleted silicon on insulator architecture that starts off with a thicker SOI (8-11 nm) and has a U-shaped channel enabled by a recessed metal gate. This device improves the electrostatics by increasing the overall gate length at fixed metal gate opening, mitigating drain field coupling to the source due to the recessed metal gate region and having thin SOI below the center of the device (4-5 nm). Modeling shows that good electrostatics can be maintained at small metal gate opening to enable pitch scaling. This device provides lower cost options for mobile and IOT technologies.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Interface Coupled Photodetector (ICPD) With High Photoresponsivity Based
           on Silicon-on-Insulator Substrate (SOI)

    • Authors: Jianan Deng;Jinhai Shao;Bingrui Lu;Yifang Chen;Alexander Zaslavsky;Sorin Cristoloveanu;Maryline Bawedin;Jing Wan;
      Pages: 557 - 564
      Abstract: A CMOS-compatible photodetector with high responsivity is reported. This device utilizes the unique interface coupling effect found in fully depleted silicon on insulator (SOI) MOSFETs. Unlike conventional SOI photodetectors, the proposed device shows higher photoresponsivity in thinner Si films due to stronger interface coupling, as confirmed by TCAD simulations. A prototype device fabricated with a simplified process flow achieves a record photoresponsivity up to 3.3 x 104 A/W.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Diode Characteristics of a Super-Steep Subthreshold Slope PN-Body Tied
           SOI-FET for Energy Harvesting Applications

    • Authors: Takayuki Mori;Jiro Ida;Shun Momose;Kenji Itoh;Koichiro Ishibashi;Yasuo Arai;
      Pages: 565 - 570
      Abstract: In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Monolithic Integration of Si-CMOS and III-V-on-Si Through Direct Wafer
           Bonding Process

    • Authors: Kwang Hong Lee;Yue Wang;Bing Wang;Li Zhang;Wardhana Aji Sasangka;Shuh Chin Goh;Shuyu Bao;Kenneth E. Lee;Eugene A. Fitzgerald;Chuan Seng Tan;
      Pages: 571 - 578
      Abstract: Integration of silicon-complementary metal oxide-semiconductor (Si-CMOS) and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT, or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by
           III–V and Ge Materials

    • Authors: Sang-Hyeon Kim;Seong-Kwang Kim;Jae-Phil Shim;Dae-Myeong Geum;Gunwu Ju;Han-Sung Kim;Hee-Jeong Lim;Hyeong-Rak Lim;Jae-Hoon Han;Subin Lee;Ho-Sung Kim;Pavlo Bidenko;Chang-Mo Kang;Dong-Seon Lee;Jin-Dong Song;Won Jun Choi;Hyung-Jun Kim;
      Pages: 579 - 587
      Abstract: Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III-V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality (sensor, display, analog, RF, etc.) via heterogeneous integration. In this paper, we discuss technology for integrating III-V and Ge materials and its applicability to CMOS, thin film photodiodes, mid-infrared photonics platforms, and MicroLED display integration for creating the ultimate 3-D chip of the future.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Germanium on Insulator Fabrication for Monolithic 3-D Integration

    • Authors: Ahmad Abedin;Laura Zurauskaite;A. Asadollahi;Konstantinos Garidis;Ganesh Jayakumar;B. Gunnar Malm;Per-Erik Hellström;Mikael Östling;
      Pages: 588 - 593
      Abstract: A low temperature (Tmax = 350 °C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm-3 were fabricated. Ge pFETs are fabricated (Tmax = 600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Cryogenic Temperature Characterization of a 28-nm FD-SOI Dedicated
           Structure for Advanced CMOS and Quantum Technologies Co-Integration

    • Authors: P. Galy;J. Camirand Lemyre;P. Lemieux;F. Arnaud;D. Drouin;M. Pioro-Ladrière;
      Pages: 594 - 600
      Abstract: Silicon co-integration offers compelling scale-up opportunities for quantum computing. In this framework, cryogenic temperature is required for the coherence of solid-state quantum devices. This paper reports the characterization of an nMOS quantum-dot dedicated structure below 100 mK. The device under test is built in thin silicon film fabricated with 28 nm high-k metal gate ultra-thin body and ultra-thin buried oxide advanced CMOS technology. The MOS structure is functional with improved performances at cryogenic temperature. The results open new research avenues in CMOS co-integration for quantum computing applications within the FD-SOI platform.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness

    • Authors: Guillermo Indalecio;Antonio J. García-Loureiro;Muhammad A. Elmessary;Karol Kalna;Natalia Seoane;
      Pages: 601 - 610
      Abstract: Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However, this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the fluctuation sensitivity map (FSM) is used to analyze the spatial effect of the line edge roughness (LER) variability in key figures-of-merit (FoM) in silicon gate-all-around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyze both 22 and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, and 0.85 nm) and correlation lengths (10 and 20 nm) using in-house 3-D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analyzed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate

    • Authors: Aakash Kumar Jain;Shubham Sahay;Mamidala Jagadesh Kumar;
      Pages: 611 - 621
      Abstract: Nanotube (NT) FETs have been proposed as the most promising architecture for the ultimate scaling of FETs. However, an enhanced L-BTBT restricts their scaling. Therefore, in this paper, for the first time, we explore the application of a dual-material gate (DMG) in the emerging NT junctionless accumulation mode FETs and NT metal-oxide semiconductor FETs to alleviate the detrimental BTBT. The incorporation of DMG reduces the OFF-state current in the NTFETs by more than two orders of magnitude leading to a substantial ON-state to OFF-state current ratio (ION/IOFF) of ~106 for a gate length of 20 nm. This paper shows that the DMG architecture not only improves the static performance significantly but also leads to an enhanced dynamic performance due to a reduction in the total gate capacitance. In addition, we also provide the essential design guidelines for NTFETs in terms of the work function of the dual gates and their respective lengths. Since the NT architecture is essentially vertical, the DMG can be realized by the deposition processes facilitating the scaling of the DMG NTFETs unlike the lateral DMG FETs. Therefore, this paper provides an incentive for experimentally exploring the NTFETs for the future technology nodes.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Effects of Electric Fields on the Switching Properties Improvements of
           RRAM Device With a Field-Enhanced Elevated-Film-Stack Structure

    • Authors: Kai-Chi Chuang;Kuan-Yu Lin;Jun-Dao Luo;Wei-Shuo Li;Yi-Shao Li;Chi-Yan Chu;Huang-Chung Cheng;
      Pages: 622 - 626
      Abstract: In this paper, a resistive random access memory (RRAM) device using a field-enhanced elevated-film-stack (EFS) structure with a 15-nm-thick HfOx dielectric layer was fabricated and measured to achieve a forming voltage (VForming) of 2.04 V, set voltage (VSet) of 0.95 V, and reset voltage (VReset) of -1.22 V, compared to the values of 2.73 V, 1.26 V, and -1.54 V for the planar one with 6-nm-thick HfOx, respectively. These resistive switching characteristics were effectively reduced, and the uniformity of these characteristics from device to device were considerably improved. The improvements of such an EFS-structured RRAM device were attributed to the high local electric fields at the two sharp corners of the EFS structure, which facilitated the formation of conductive filaments, and the distribution of the electric field was verified by technology computer-aided design simulations.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Enhancing the Electrical Uniformity and Reliability of the HfO2-Based RRAM
           Using High-Permittivity Ta2O5 Side Wall

    • Authors: Mei Yuan;Yi-Ting Tseng;Po-Hsun Chen;Chih-Cheng Shih;Hui-Chun Huang;Ting-Chang Chang;Xiaole Cui;Xinnan Lin;Shengdong Zhang;Hang Zhou;
      Pages: 627 - 632
      Abstract: In conventional HfO2-based resistive random access memory (RRAM), SiO2 is usually adopted as side wall spacer (low-k spacer) to define the device feature size. It is found that the forming voltage of the conventional HfO2 RRAM with SiO2 spacer rises when the device size is scaling down from 16.0 μm2 to 0.16 μm2, which is detrimental for application of high density HfO2-based RRAM. In this study, a high permittivity side wall spacer (high-k spacer) Ta2O5 is introduced to replace SiO2 spacer. The Ta2O5 side wall effectively suppress the forming voltage rising issues during RRAM device scaling without introducing costly processing steps. Moreover, compared to the conventional HfO2-based RRAM, the side wall enhanced device exhibits faster switching speed, smaller operation voltage, and higher reliabilities, including endurance and retention. As a result, the use of Ta2O5 side wall significantly enhances the overall switching characteristics of the HfO2-based RRAM device.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Band-Tails Tunneling Resolving the Theory-Experiment Discrepancy in Esaki

    • Authors: Jasper Bizindavyi;Anne S. Verhulst;Quentin Smets;Devin Verreck;Bart Sorée;Guido Groeseneken;
      Pages: 633 - 641
      Abstract: Discrepancies exist between the theoretically predicted and experimentally measured performance of band-to-band tunneling devices, such as Esaki diodes and tunnel field-effect transistors (TFETs). We resolve this discrepancy for highly-doped, direct-bandgap Esaki diodes by successfully calibrating a semi-classical model for high-doping-induced ballistic band-tails tunneling currents at multiple temperatures with two In0.53Ga0.47As Esaki diodes using their SIMS doping profiles, C-V characteristics and their forward-bias current density in the negative differential resistance (NDR) regime. The current swing in the NDR regime is shown not to be linked to the band-tails Urbach energy. We further demonstrate theoretically that the calibrated band-tails contribution is also the dominant band-tails contribution to the subthreshold swing of the corresponding TFETs. Lastly, we verify that the presented procedure is applicable to all direct-bandgap semiconductors by successfully applying it to InAs Esaki diodes in literature.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Random Telegraph Signal Phenomena in Ultra Shallow p+n
           Silicon Avalanche Diodes

    • Authors: Vishal Agarwal;Anne-Johan Annema;Satadal Dutta;Raymond J. E. Hueting;Lis K. Nanver;Bram Nauta;
      Pages: 642 - 652
      Abstract: An extensive time domain analysis of the random telegraph signal (RTS) phenomena in silicon avalanche diodes is presented. Experiments show two distinct types of RTSs classified herein, on the basis of the temporal behavior of the amplitude, as the “decaying” and the “constant” type. These RTSs are analyzed using a model for defects reported earlier, from which their ohmic series resistance and geometrical parameters have been estimated. The results indicate that breakdown of a relatively small area defect results in a “decaying” amplitude type of RTS, and breakdown of a relatively large area defect results in a “constant” amplitude type of RTS. These two types can be explained by the differences in the thermal resistance, which is higher for the former.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Influence of Surface Energy and Roughness on Hole Mobility in
           Solution-Processed Hybrid Organic Thin Film Transistors

    • Authors: Sungsik Lee;Flora M. Li;Arokia Nathan;
      Pages: 653 - 657
      Abstract: We investigate the influence of the surface energy and roughness on the hole mobility in organic thin-film transistors where a poly(3,3”'-dialkylquarterthiophene) (PQT-12) hybridized with an octyltrichlorosilane self-assembled monolayer is employed as the semiconducting layer on a silicon nitride (SiNx) gate insulator. Here, these surface properties are modified with varying the duration of oxygen plasma treatments on the SiNx surface, eluding to a different surface roughness and energy. From our analysis coupled with the experimental results, it is found that the surface roughness (Ra) controls the degree of surface roughness scattering (χSR) while the surface energy (ES) determines the reference mobility (μb), yielding the effective hole mobility expressed as a product of two terms associated with μb and χSR, respectively. It is found that μb follows a power law as a function of ES, and χSR grows exponentially with increasing Ra. In addition, a characteristics scattering length (λc) appears in the mobility expression, which turns out to be a demarcation, suggesting that Ra is required to be at least smaller than λc to minimize χSR.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Built-In Sheet Charge As an Alternative to Dopant Pockets in Tunnel
           Field-Effect Transistors`

    • Authors: Devin Verreck;Anne S. Verhulst;Yang Xiang;Dmitry Yakimets;Salim El Kazzi;Bertrand Parvais;Guido Groeseneken;Nadine Collaert;Anda Mocuta;
      Pages: 658 - 663
      Abstract: Dopant pockets in combination with a III-V heterostructure have become a staple in simulations of tunnel field-effect transistors (TFET) to achieve acceptable on-currents (ION) and to break the ION-subthreshold swing trade-off in pTFETs. Questions on the scalability and variability of these dopant pockets remain, however. We therefore propose an alternative concept using two opposite sheet charges at the tunnel junction that are realized by exploiting different bonding types. With fully quantum mechanical 30-band k.p-based simulations, we investigate two configurations that exhibit such sheet charges both at the device level and in a ring-oscillator: a lattice-matched GaAs-Ge-GaAs heterostructure TFET and a homostructure InGaAs TFET. By comparing to pocketed broken gap GaSb-InAs TFETs, we show that built-in sheet charge is a valid alternative for both nTFET and pTFET, with the prospect of lower variability and better scalability.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Diffusive-Probabilistic Model for Inter-Pixel Crosstalk in HgCdTe Focal
           Plane Arrays

    • Authors: Marco Vallone;Michele Goano;Francesco Bertazzi;Giovanni Ghione;Stefan Hanna;Detlef Eich;Heinrich Figgemeier;
      Pages: 664 - 673
      Abstract: A closed-form probabilistic model for inter-pixel crosstalk in planar HgCdTe focal plane arrays is presented, providing simple expressions of crosstalk as function of device parameters like the pixel pitch, the absorber thickness, and the extension of the carrier depleted region. The method is effective in particular for performing parameter sensitivity studies on inter-pixel crosstalk, as an alternative to large-scale numerical simulations. The model is validated against three-dimensional combined optical and electrical numerical simulations, considering realistic, non-monochromatic illumination.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Threshold Switching Behavior of Ag-SiTe-Based Selector Device and
           Annealing Effect on its Characteristics

    • Authors: Bing Song;Hui Xu;Sen Liu;Haijun Liu;Qingjiang Li;
      Pages: 674 - 679
      Abstract: Programmable metallization cell is one of important threshold switching selectors. We first performed a study on the selector based on amorphous chalcogenide material (Si0.4Te0.6) because of the rigid structure applied in ovonic threshold switch. In the meantime, annealing process is implemented to improve the performance. Results show that devices without annealing process demonstrate a minor threshold switching characteristic, revealing the potential as selector for cross-point memristor array. After implementing annealing process, threshold voltage (Vth), selectivity and endurance of selectors improve. Meanwhile, requirements of high current and a low holding voltage (Vh) for an ideal selector are fulfilled. Using the Ag filament formed during motion of Ag ions, a steep-slope (1.7 mV/dec) for threshold switching with high selectivity (~104) could be achieved. Owing to the faster diffusivity of Ag atoms in solid-electrolytes, the resulting Ag filament easily dissolved under low current regime. It is deduced that performance improvement is due to the defect reduction within annealing process. Finally, time characteristics of selector devices are tested to verify fast switching and recovery speed for practical applicability.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Scalability and Stability Enhancement in Self-Aligned Top-Gate Indium-
           Zinc-Oxide TFTs With Al Reacted Source/Drain

    • Authors: Ting Liang;Yang Shao;Huiling Lu;Xiaoliang Zhou;Xuan Deng;Shengdong Zhang;
      Pages: 680 - 684
      Abstract: A self-aligned fabrication process for top-gate amorphous indium-zinc-oxide (a-IZO) thin-film transistors (TFTs) is demonstrated. Aluminum (Al) thermal treatment is employed to dope the a-IZO layer and thus form the self-aligned source/drain regions. The results show that the sheet resistance of the Al-treated a-IZO layer can be as low as 360 Ω/□. The fabricated top-gate TFTs typically have a mobility of 16.84 cm2/V · s, subthreshold swing of 0.14 V/dec and on/off current ratio of> 109. The Al-treated TFTs show a significant scalability and stability enhancement compared to the conventional Ar plasma-treated ones. This enhancement can be attributed to the thin Al2O3 layer formed on source-drain area that blocks the diffusion of hydrogen or H2O from the passivation layer into the source-drain and channel regions.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Drain-Induced-Barrier-Lowing-Like Effect Induced by Oxygen-Vacancy in
           Scaling-Down via-Contact Type Amorphous InGaZnO Thin-Film Transistors

    • Authors: Chung-I. Yang;Ting-Chang Chang;Po-Yung Liao;Li-Hui Chen;Bo-Wei Chen;Wu-Ching Chou;Guan-Fu Chen;Sung-Chun Lin;Cheng-Yen Yeh;Cheng-Ming Tsai;Ming-Chang Yu;Shengdong Zhang;
      Pages: 685 - 690
      Abstract: This investigation considers a method to ameliorate drain induced barrier lowing behavior in amorphous-indium-gallium-zinc-oxide thin-film transistors. The Vth is found to shift negatively when increasing the ID-VG measurement condition VD from 0.1 to 15 V. The current-voltage curves show that this degradation is caused by the effective channel length (Leff) being shorter than the mask channel length (L). Using the transmission line method to extract Leff, we discover that the degradation will be completely suppressed by an annealing treatment. As a result, the degradation mechanism of shorter channel length a-IGZO thin film transistors is due to oxygen-vacancies which are located between the channel and the source/drain junction.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • SCR-Based ESD Protection Using a Penta-Well for 5 V Applications

    • Authors: Bo-Bae Song;Kyoung-Il Do;Yong-Seo Koo;
      Pages: 691 - 695
      Abstract: This paper proposes a new structure of silicon controlled rectifier (SCR)-based ESD protection circuit using a penta-well for ESD protection in 5 V applications. The proposed circuit exhibits higher holding voltage and current-driving capability than low Ron SCR (LRSCR) ESD protection circuits. The existing LRSCR ESD protection circuit and the proposed ESD protection circuit were fabricated using the 0.18 μm BCD process. The electrical and latch-up characteristics were compared and analyzed using transmission line pulse measurement and a transient-induced latch-up test.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Novel Computing Method for Short Programming Time and Low Energy
           Consumption in HfO2 Based RRAM Arrays

    • Authors: Gilbert Sassine;Carlo Cagli;Jean-François Nodin;Gabriel Molas;Etienne Nowak;
      Pages: 696 - 702
      Abstract: This paper proposes a novel technique for reducing programming time and energy consumption in resistive random access memory (RRAM) arrays based on ramped voltage stress (RVS). RVS method is correlated to conventional constant voltage stress method (CVS) using an analytical model validating RVS as a reliable technique for switching time characterization in RRAM arrays. RVS method is optimized to reduce programming time and energy consumption providing a quantitative and qualitative link between programming method and tails improvement in memory arrays. Switching time distribution is much more controlled: half a decade using optimized RVS in comparison with ~3 decades distribution using conventional CVS method. Energy consumption is reduced by 4 orders of magnitude at +5σ quantiles using our proposed technique compared to CVS.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Contactless Method to Measure 2DEG Charge Density and Band Structure in
           HEMT Structures

    • Authors: Yury Turkulets;Ilan Shalish;
      Pages: 703 - 707
      Abstract: We present a contactless method capable of characterizing a high electron mobility transistor (HEMT) heterostructure at the wafer stage, right after its growth, before any production process has been attempted, to provide the equilibrium band structure and the density of charge of the 2-D electron gas in the quantum well (QW). The method can thus evaluate critical transistor parameters and help to screen out low performance wafers before the actual fabrication. To this end, we use a simple optical spectroscopy at room temperature that measures the surface photovoltage band-edge responses in the heterostructure and uses a model that takes into account the effect of the built-in electric fields on optical absorption in the layers and heterojunctions to evaluate bandgaps, band offsets, and built-in fields. The QW charge is then calculated from the built-in fields. The main advantage of the method is in its capability to provide information on all the different layers in the typical heterostructure simultaneously in a single measurement. The method is not limited to the HEMT structure but may be used on any other heterostructure. It opens the door for a new type of characterization methods suitable for the post-silicon multi-layer multi-semiconductor heterostructure device era.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • The Simulation Study of the SOI Trench LDMOS With Lateral Super Junction

    • Authors: Weizhong Chen;Lijun He;Zhengsheng Han;Yi Huang;
      Pages: 708 - 713
      Abstract: A novel lateral double diffused metal oxide semiconductor (LDMOS) with trench oxide layer, featuring a lateral super junction structure based on the silicon-on-insulator technology is proposed. On the one hand, the lateral super junction combined with the TOL can enhance both the surface and the bulk electric field of the N-drift by the charge compensation. Thus, the breakdown voltage (BV) is improved. On the other hand, the N-Pillar of the lateral super junction provides another current channel for electrons at the forward conduction state, thus the Specific on resistance (Ron,sp) is decreased. As the simulation results show, the proposed LDMOS exhibits trapezoidal electric field distribution with BV of 422V, and double electron channels with Ron,sp of 30.7 mΩ·cm2, thus the figure of merit (FOM) (FOM = BV2/Ron,sp, Baliga's FOM) of 5.82 MW/cm2 is achieved, breaking through the silicon limit.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Improved Uniformity and Endurance Through Suppression of Filament
           Overgrowth in Electrochemical Metallization Memory With AgInSbTe Buffer

    • Authors: Ye Tao;Xuhong Li;Haiyang Xu;Zhongqiang Wang;Wentao Ding;Weizhen Liu;Jiangang Ma;Yichun Liu;
      Pages: 714 - 720
      Abstract: We demonstrated an effective approach to suppress conductive filament (CF) overgrowth through the introduction of a AgInSbTe (AIST) buffer layer into amorphous carbon-based electrochemical metallization memory devices. The overshoot current (IOS) was monitored in real-time for the devices with and without the AIST layer. Our results indicates that the IOS was eliminated after insertion of the buffer layer. The effect of the AIST layer on CF overgrowth suppression could be attributed to the lower VSET and capacity to hold excess Ag-ions. The optimized Pt/a-C/AIST/Ag devices exhibited highly uniform switching parameters, fast switching speed (
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • In-Line Tunnel Field Effect Transistor: Drive Current Improvement

    • Authors: Woojin Park;Amir N. Hanna;Arwa T. Kutbee;Muhammad Mustafa Hussain;
      Pages: 721 - 725
      Abstract: A new architecture of tunnel field effect transistor (TFET) with in-line (vertical) tunneling area is introduced. By adding the vertical tunneling area, the in-line TFET architecture outperformed the normal TFET in terms of the drive current, the subthreshold swing, and the intrinsic time delay, etc. The drive current of the in-line TFET is enhanced nearly 7× compared to the conventional TFET. It also shows a significantly reduced subthreshold swing of 37.2 mV/dec.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Low Power and Low Noise Shift Register for In-Cell Touch Display

    • Authors: Jeongrim Seo;Hyoungsik Nam;
      Pages: 726 - 732
      Abstract: This paper proposes a shift register circuit integrated in in-cell touch display panels that achieves low power operation, low coupling noise, and high long-term reliability with 11 thin film transistors (TFTs) and two capacitors. A time division driving method is utilized to prevent the crosstalk of display signals into touch circuits, and two pre-charging nodes are employed to relieve the uniformity degradation of output signals caused by different stresses on pull-up TFTs. The proposed circuit activates a drain of the first pre-charging TFT only at display scanning periods, which reduces coupling noises and power consumption. In addition, an internal inverter is turned off for touch sensing operations, resulting in a wide range of threshold voltage shift compensation and low power consumption. SPICE simulation results with a low temperature poly silicon TFT model show that the proposed circuit compensates for the threshold voltage shift up to 17 V. In a 60 Hz full-HD display with a 120 Hz touch reporting rate, the noise level of the first pre-charging node is -16.78 dB in between 2.37 and -28.95 dB of two previous circuits, and the total power consumption for 160 stages is substantially reduced to 4.44 mW compared to previous approaches.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Effect of Al2O3 Passivation Layer and Cu Electrodes on High Mobility of
           Amorphous IZO TFT

    • Authors: Shiben Hu;Honglong Ning;Kuankuan Lu;Zhiqiang Fang;Ruiqiang Tao;Rihui Yao;Jianhua Zou;Miao Xu;Lei Wang;Junbiao Peng;
      Pages: 733 - 737
      Abstract: In this paper, we present a high mobility amorphous indium-zinc-oxide (a-IZO) thin film transistor (TFT) based on copper (Cu) source/drain electrodes (S/D) and aluminum oxide (Al2O3) passivation layer (PVL). The mechanism of high mobility for the a-IZO TFT based on Cu S/D with Al2O3 PVL was proposed and experimentally demonstrated. The sputtering of Al2O3 PVL induced a highly conductive channel layer due to the formation of In-rich layer on the back channel. Also, Cu S/D presented Schottky contact behavior compared with Mo S/D which behaved like Ohmic contact. Because the Schottky contact can block leakage current and the highly conductive channel achieved high on-current, the a-IZO TFT based on Cu S/D and Al2O3 PVL performed remarkable saturation mobility up to 412.7 cm2/Vs. This paper presents a feasible way to implement high mobility TFT arrays with Cu electrodes.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS

    • Authors: Bing Wang;Zhigang Wang;James B. Kuo;
      Pages: 739 - 746
      Abstract: An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism. The key feature of this device is the introduction of a Γ-shape P-island window with a relatively high doping concentration to connect the N-drift region to the P-substrate under the source, which is designed to achieve an avalanche breakdown point at the edge of the P-island instead of near the gate contact. Thus, the avalanche current is shortened to the substrate contact through the P-island and the P-substrate, avoiding the avalanche current to pass through the N± source/P-well junction and thus suppressing the activation of the parasitic bipolar transistor with a relaxed self-heating effect especially in the P-well region. As verified by the Medici device simulation results, the SD mechanism of the device under the UIS condition, may endure a remarkably higher avalanche current as compared with the conventional SOI LDMOS device.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Editorial For J-EDS Website

    • Authors: Arokia Nathan;
      Pages: 743 - 743
      Abstract: The IEEE Journal of the Electron Devices Society (J-EDS) has been committed to publishing papers ranging from fundamental to applied research relevant to the broad family of electron devices and has now extended its mandate to provide a home for timely dissemination of new results on all aspects of display and related technologies. This replaces the recently discontinued IEEE/OSA Journal of Display Technology.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Counteracting Threshold-Voltage Drift in Ion-Selective Field Effect
           Transistors (ISFETs) Using Threshold-Setting Ion Implantation

    • Authors: Ali Elyasi;Majid Fouladian;Shahriar Jamasb;
      Pages: 747 - 754
      Abstract: Ion-selective field effect transistors (ISFETs) exhibit instability, commonly known as drift, in the form of a slow, monotonic, temporal increase in the threshold voltage of the device. A method for counteracting instability inspired by a physical model for threshold voltage drift in pH-sensitive ISFETs is presented. This method involves adjusting the charge density at the insulator-semiconductor interface using threshold-setting ion implantation such that the net charge induced in the semiconductor at the operating point of the device is minimized. The proposed method is analytically validated based on characterization and modeling of drift in an Al2O3-gate pH-sensitive ISFET. Counteraction of ISFET drift by ion implantation is also demonstrated using TCAD simulations. The optimum donor-type implant dose of 3.25×1011 cm-2 determined based on ATLAS simulations is in good agreement with the corresponding dose of 6.58 × 1011 cm-2 obtained analytically.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Investigating on Through Glass via Based RF Passives for 3-D Integration

    • Authors: Libo Qian;Jifei Sang;Yinshui Xia;Jian Wang;Peiyi Zhao;
      Pages: 755 - 759
      Abstract: Due to low dielectric loss and low cost, glass is developed as a promising material for advanced interposers in 2.5-D and 3-D integration. In this paper, through glass vias (TGVs) are used to implement inductors for minimal footprint and large quality factor. Based on the proposed physical structure, the impact of various process and design parameters on the electrical characteristics of TGV inductors is investigated with 3-D electromagnetic simulator HFSS. It is observed that TGV inductors have identical inductance and larger quality factor in comparison with their through silicon via counterparts. Using TGV inductors and parallel plate capacitors, a compact 3-D band-pass filter (BPF) is designed and analyzed. Compared with some reported BPFs, the proposed TGV-based circuit has an ultra-compact size and excellent filtering performance.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • High-Gain Transimpedance Amplifier for Flexible Radiation Dosimetry Using
           InGaZnO TFTs

    • Authors: Pydi Ganga Bahubalindruni;Jorge Martins;Ana Santa;Vitor Tavares;Rodrigo Martins;Elvira Fortunato;Pedro Barquinha;
      Pages: 760 - 765
      Abstract: This paper presents a novel high-gain transimpedance amplifier for flexible radiation sensing systems that can be used as large-area dosimeters. The circuit is implemented with indium-gallium-zinc-oxide thin-film-transistors and uses two stages for the amplification of the sensor signal (current). The first stage consists of cascode current mirrors with a diode connected load that performs current amplification and voltage conversion. Then, the first stage is followed by a voltage amplifier based on a positive feedback topology for gain enhancement. The proposed circuit converts nano-ampere (10 nA) currents into hundreds of millivolts (280 mV), showing a gain around 149 dB and a power consumption of 0.45 mW. The sensed radiation dose level, in voltage terms, can drive the next stages in the radiation sensing system, such as analog to digital converters. These radiation sensing devices can find potential applications in real-time, large area, flexible health, and security systems.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • User-Oriented Piezoelectric Force Sensing and Artificial Neural Networks
           in Interactive Displays

    • Authors: Shuo Gao;Jifang Duan;Vasileios Kitsos;David R. Selviah;Arokia Nathan;
      Pages: 766 - 773
      Abstract: Force touch based interactivity has been widely integrated into displays equipped in most of smart electronic systems such as smartphones and tablets. This paper reports on application of artificial neural networks to analyze data generated from piezoelectric based touch panels for providing customized force sensing operation. Based on the experimental results, high force sensing accuracy (93.3%) is achieved when three force levels are used. Two-dimensional sensing, also achieved with the proposed technique, with high detection accuracy (95.2%). The technique presented here not only achieves high accuracy, but also allows users to define the range of force levels through behavioral means thus enhancing interactivity experience.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Inkjet Printed Electrodes in Thin Film Transistors

    • Authors: Ruiqiang Tao;Honglong Ning;Jianqiu Chen;Jianhua Zou;Zhiqiang Fang;Caigui Yang;Yicong Zhou;Jianhua Zhang;Rihui Yao;Junbiao Peng;
      Pages: 774 - 790
      Abstract: Inkjet printing is a non-vacuum, non-contact, low-cost, and direct patterning thin film deposition technique. Compared to traditional processes, it demands less materials and energy, simplifies processing steps and is compatible with the fast fabrication of flexible and large-size devices, thus potential in the application of thin film transistors. In this paper, we have compared the main techniques of inkjet printing, and discussed the formulation of conductive inks, the deposition of high quality electrodes, and the obtaining of high resolution and high performance thin film transistors. Moreover, the faced problems and corresponding solving methods of inkjet printed thin film transistor with low sintering temperature, small line width, short channel, high mobility, and designed structure are summarized by the understanding of the interaction among inkjet printing devices, materials, processes, and the fabrication of transistors, which providing referential significance of the following research effort.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Dual-Surface Modification of AlGaN/GaN HEMTs Using TMAH and Piranha
           Solutions for Enhancing Current and 1/f-Noise Characteristics

    • Authors: M. Siva Pratap Reddy;Won-Sang Park;Ki-Sik Im;Jung-Hee Lee;
      Pages: 791 - 796
      Abstract: We demonstrated dual-surface modification of GaN/AlGaN/GaN high-electron mobility transistors using tetramethylammonium hydroxide (TMAH) and piranha solutions prior to gate metallization. The TMAH-treated device exhibits improved performances with lower I-V hysteresis, in off-state leakage current and gate leakage current. The device performances were further significantly improved with applies additional piranha solution treatment right after the TMAH treatment, especially in hysteresis and 1/f-noise characteristics. It is found that the Schottky barrier height is high and ideality factor is low measured from I-V characteristics for the TMAH and piranha solution treated device. Reasonable gate leakage mechanisms were also discussed using Poole-Frenkel and Schottky emissions. In addition, it is observed that the magnitude of interface state density for the TMAH treatment after the piranha solution treated device shows significantly low compared to other devices. These excellent device-performances are observed due to the reason of dual-surface treatment which effectively decreases the surface trap density with an appropriate etching and passivation of the device surface exposed prior to the gate metallization.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility
           Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for
           High-Speed and Low-Power Logic Applications

    • Authors: Jing-Neng Yao;Yueh-Chin Lin;Heng-Tung Hsu;Kai-Chun Yang;Hisang-Hua Hsu;Simon M. Sze;Edward Yi Chang;
      Pages: 797 - 802
      Abstract: In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 × 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 × 10-5 A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • An Investigation of Anode Hole Injection-Induced Abnormal Body Current in
           n-Channel HfO2/TiN MOSFETs

    • Authors: Jih-Chien Liao;Ting-Chang Chang;Wei-Ren Syong;Kai-Chun Chang;Ying-Hsin Lu;Hsi-Wen Liu;Chien-Yu Lin;Li-Hui Chen;Fu-Yuan Jin;Yu-Hsuan Chen;Chen-Hsin Lien;Osbert Cheng;Cheng-Tung Huang;Yi-Han Ye;
      Pages: 803 - 807
      Abstract: This paper investigates an anode hole injection (AHI)-induced abnormal body current (abn IB) in n-channel HfO2/TiN MOSFETs. Traditionally, body current is independent of gate voltage during initial electrical characteristic measurements. Nevertheless, in this paper, the opposite is found in our experiment. Therefore, two different measurement techniques are employed, with the body current attributed to electrons in the inversion layer under the grounded source/drain. This indicates that the dominant mechanism is AHI rather than electron tunneling from the valence band. Moreover, the abn IB is dominated by tunneling mechanisms because it is independent of temperature.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Effects of Fluorine on the NBTI Reliability and Low-Frequency Noise
           Characteristics of p-MOSFETs

    • Authors: Sung-Kyu Kwon;Hyuk-Min Kwon;In-Shik Han;Jae-Hyung Jang;Sun-Ho Oh;Hyeong-Sub Song;Byoung-Seok Park;Yi-Sun Chung;Jung-Hwan Lee;Si-Bum Kim;Ga-Won Lee;Hi-Deok Lee;
      Pages: 808 - 814
      Abstract: The concurrent effect of fluorine implantation with various energy and dose on reliability and low-frequency noise characteristics of p-MOSFETs was investigated. The ΔVT degradation that represents device lifetime of p-MOSFETs with fluorine implantation under negative-bias temperature instability stress was less than that without fluorine implantation. The device lifetimes were improved as the fluorine implantation energy and dose increase. The power law exponent n with the fluorine implantation was larger than that without fluorine implantation. This was related to boron diffusion within the gate oxide because the F atoms enhance the diffusivity of the boron. The difference of flicker noise levels between simulation and measurement data at 1 kHz was much greater than that at 10 Hz, which means that F atoms were mainly located near the Si/SiO2 interface rather than in the bulk oxide. The fluorine implantation reduced the ID-RTS noise amplitude, which was believed to contribute to the effective passivation of the dominant traps within the gate oxide. Also, the flicker noise was less dependent on implantation energy. But, flicker noise was reduced with increasing implantation dose. Therefore, fluorine implantation is potentially significant for reducing low-frequency noise as well as improving reliability characteristics.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • $beta$+ -Ga2O3+Schottky+Barrier+Diode+on+Sapphire+Substrate+With+Reverse+Blocking+Voltage+of+1.7+kV&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Zhuangzhuang&;Hong+Zhou;Kui+Dang;Yuncong+Cai;Zhaoqing+Feng;Yangyang+Gao;Qian+Feng;Jincheng+Zhang;Yue+Hao;">Lateral $beta$ -Ga2O3 Schottky Barrier Diode on Sapphire Substrate With
           Reverse Blocking Voltage of 1.7 kV

    • Authors: Zhuangzhuang Hu;Hong Zhou;Kui Dang;Yuncong Cai;Zhaoqing Feng;Yangyang Gao;Qian Feng;Jincheng Zhang;Yue Hao;
      Pages: 815 - 820
      Abstract: In this paper, we report on achieving the first high performance lateral β-Ga2O3 Schottky barrier diode (SBD) on sapphire substrate via transferring β-Ga2O3 nano-membrane channel from a low dislocation density bulk β-Ga2O3 substrate. Non field-plated lateral SBDs with Schottky-Ohmic contact distance of 4, 6, 11, and 15 μm demonstrate a reverse breakdown voltage (BV) of 0.64, 0.85, 1.2, and 1.7 kV with on resistance (Ron) of 47, 66, 91, and 190 Ω·mm, respectively. This lateral Ron,sp ~ BV performance is comparable to that of vertical SBDs. Combining with 107 ~ 108 high temperature current on/off ratio, β-Ga2O3 SBD shows its great promise for power rectifying once the β-Ga2O3 drift layer epitaxial growth becomes more mature.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Steep Slope Field-Effect Transistors With B–Te-Based Ovonic
           Threshold Switch Device

    • Authors: Jongmyung Yoo;Donguk Lee;Jaehyuk Park;Jeonghwan Song;Hyunsang Hwang;
      Pages: 821 - 824
      Abstract: In this letter, a new ovonic threshold switch (OTS) device based on simple binary Boron-Tellurium (B-Te) film is developed and implemented in series with the source region of a transistor. The newly developed B-Te-based device shows excellent characteristics such as low operating voltage, low leakage current, abrupt turn-on/off slope, fast switching speed, high endurance, and high thermal stability. Due to the great properties of the B-Te OTS device, the implemented transistor exhibits subthreshold swing less than 10 mV/dec and high on/off current ratio greater than 105. Moreover, we present a direction of implementing an ideal transistor based on simulation results explaining the effect of off-state resistances and threshold voltages of the OTS devices on the IDS-VGS characteristics of the implementer transistor.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • 2.4 kV Vertical GaN PN Diodes on Free Standing GaN Wafer Using
           CMOS-Compatible Contact Materials

    • Authors: Xinke Liu;Hsien-Chin Chiu;Hou-Yu Wang;Cong Hu;Hsiang-Chun Wang;Hsuan-Ling Kao;Feng-Tso Chien;
      Pages: 825 - 829
      Abstract: This paper reports vertical Gallium nitride (GaN) PN diodes on free-standing GaN wafer using a complementary metal-oxide-semiconductor compatible contact materials. Static and switching current-voltage measurements have been carried out to evaluate the fabricated vertical GaN PN diodes. The vertical GaN PN diode in this paper shows turn-on voltage Von of ~3.3-3.4 V, on/off current ratio of ~2.7 × 107, and ideal factor n of ~2.1. The reverse recovery time Trr is 21.2 ns and 23.2 ns, respectively, under a testing temperature of 300 K and 500 K. With an on-state resistance Ron of 3.9 mΩ·cm2 and a breakdown voltage VBR of 2.4 kV, this device achieves a power device figure-of-merit VBR2/Ron of 1.5×109 V2Ω-1cm-2.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Drain-Induced Barrier Lowering in Oxide Semiconductor Thin-Film
           Transistors With Asymmetrical Local Density of States

    • Authors: Hyeon-Jun Lee;Katsumi Abe;Sung Haeng Cho;June-Seo Kim;Seokhwan Bang;Myoung-Jae Lee;
      Pages: 830 - 834
      Abstract: Asymmetrical electrical properties induced by local acceptor-like defect states in oxide semiconductor thin-film transistors are investigated. In addition, we report on the origin of asymmetrical transport characteristics depending on the drain voltage level. In particular, we observe that these asymmetrical properties depend strongly on this level. Numerical calculations demonstrate that potential barrier lowering in the local area occurs at the drain electrode's edge.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Simultaneous Emission AC-OLED Pixel Circuit for Extended Lifetime of OLED

    • Authors: Ki-Hyuk Seol;Young In Kim;Seungjun Park;Hyoungsik Nam;
      Pages: 835 - 840
      Abstract: This paper demonstrates a pixel circuit of seven thin film transistors (TFTs) and two capacitors that drives an AC driven OLED (AC-OLED) at a simultaneous emission scheme. Because the AC-OLED is composed of two OLED units connected in opposite directions, the proposed circuit drives the current programmed once during a frame time in both ways. Since one OLED unit emits the light for about half frame time, the lifetime of OLEDs is ameliorated substantially. In addition, the proposed pixel circuit allows threshold voltage and supply voltage variations to be compensated. SPICE simulation results with a p-channel low temperature poly-silicon TFT model show that the average current non-uniformities are improved to 1.19% and 3.37% for threshold voltage and supply voltage variations of ±0.5 V, respectively.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Physical Insights on Quantum Confinement and Carrier Mobility in Si,
           Si0.45Ge0.55, Ge Gate-All-Around NSFET for 5 nm Technology Node

    • Authors: Jiaxin Yao;Jun Li;Kun Luo;Jiahan Yu;Qingzhu Zhang;Zhaozhao Hou;Jie Gu;Wen Yang;Zhenhua Wu;Huaxiang Yin;Wenwu Wang;
      Pages: 841 - 848
      Abstract: We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around nanosheet field effect transistor for 5-nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses: (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions; (2) Kubo-greenwood model for low field mobility with considering surface roughness and stress; (3) multisub-band Boltzmann transport equation based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics; and (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5-nm node pMOS, and Si is still promising for nMOS due to strong quantum confinement in Ge channel.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Enhancing Driving Performance of a-Si:H Thin-Film Transistors With
           Capacitive Coupling Method for Display Applications

    • Authors: Chih-Lung Lin;Fu-Hsing Chen;Jui-Hung Chang;Yu-Sheng Lin;
      Pages: 849 - 855
      Abstract: A new capacitive coupling method to enhance the driving performance of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) in high-resolution applications is presented. The gate voltage can be enlarged by the entirely transmitted high voltage of a global direct current power source line (VDD). Established models that are based on the measured electrical characteristics of fabricated a-Si:H TFTs with different aspect ratios are used to evaluate the feasibility of this proposed method in the gate driver. The maximum voltage of the gate voltage can be increased from 37.3 V to 47.6 V when VDD is set to 20 V, improving the driving capability of the gate driver by more than 17%, based on the specifications of a 5.99 inch HD + (720 × 1440) panel at a frame rate of 120 Hz.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • InGaAs Junctionless FinFETs With Self-Aligned Ni-InGaAs S/D

    • Authors: Po-Chun Chang;Chih-Jen Hsiao;Franky Juanda Lumbantoruan;Chia-Hsun Wu;Yen-Ku Lin;Yueh-Chin Lin;Simon M. Sze;Edward Yi Chang;
      Pages: 856 - 860
      Abstract: In this paper, the InGaAs junctionless (JL) FinFET with notable electrical performance is demonstrated. The device with Wfin down to 20 nm, EOT of 2.1 nm, and LG = 60 nm shows high ION = 188 μA/μm at VDD = 0.5 V and IOFF = 100 nA/μm, ION/IOFF = 5 × 105, DIBL = 106 mV/V and SS = 96 mV/dec. The device also exhibits a decent extrinsic transconductance (Gm) of 1142 μS/μm at VDS of 0.5 V. This high performance is attributed to the moderate doping concentration to ensure the channel carriers could be effectively depleted and the low RSD realized by self-aligned Ni-InGaAs alloy S/D. Furthermore, we also examine the temperature dependence of the main electrical parameters of the JL transistor.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • ${V}_{text{th}}$+ +Strategies+of+7-nm+node+Nanosheet+FETs+With+Limited+Nanosheet+Spacing&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jun-Sik&;Jinsu+Jeong;Seunghwan+Lee;Rock-Hyun+Baek;">Multi- ${V}_{text{th}}$ Strategies of 7-nm node Nanosheet FETs With
           Limited Nanosheet Spacing

    • Authors: Jun-Sik Yoon;Jinsu Jeong;Seunghwan Lee;Rock-Hyun Baek;
      Pages: 861 - 865
      Abstract: In this paper, multi-threshold voltage (Vth) scheme of 7-nm node nanosheet FETs (NSFETs) with narrow NS spacing were successfully achieved by metal-gate work function (WF) and channel doping (Nch) using fully calibrated 3-D TCAD simulations. The limited NS spacing, which allows TiN capping layer only, makes different WF between the edge and the middle part of NS circumference. Unfortunately, this causes non-linear Vth shifts and dc performance degradation as a function of WF due to one-side turn-on phenomena between the edge and the middle part. Furthermore, the fixed WF of TiN capping layer limits Vth shifts toward ultra-low-power applications. To enable multi-Vth of NSFETs, several possible solutions are addressed: changing the Nch and the WF of TiN capping layer. The higher Nch enables lower off-state current while 50-nm-wide three-stacked NS decreases dc performance variations effectively. Changing the WF of TiN capping layer can extend Vth margins, but degrade DC performance as a trade-off. Nonetheless, 7-nm node NSFETs adopting these techniques have multi-Vth options to satisfy wide ranges from ultra-low-power to high-performance applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • An Experimental Approach to Characterizing the Channel Local Temperature
           Induced by Self-Heating Effect in FinFET

    • Authors: E Ray Hsieh;Meng-Ru Jiang;Jian-Li Lin;Steve S. Chung;Tse Pu Chen;Shih An Huang;Tai-Ju Chen;Osbert Cheng;
      Pages: 866 - 874
      Abstract: In this paper, we have developed a methodology of a lateral profiling technique of the channel local temperature in 14 nm FinFET, incurred by the self-heating effect (SHE). As SHE happens, the thermal source generated near the drain will dissipate toward the source side. Since the interaction between RTN trap and channel carriers is very sensitive to the temperature, the channel local temperature can be extracted through this interaction process between random-telegraph-noise (RTN) trap and carriers, and the position of the channel local temperature can be obtained from the RTN trap position. The results show that the highest temperature happens at the drain edge during SHE and pFinFET exhibits a much higher temperature than that of nFinFET. Furthermore, the distribution of channel local temperature can be described by the Fourier's law of thermal conduction. Averaged channel temperature can be used to extract the thermal resistance, Rth, which increases rapidly as the channel length is scaled down to 20 nm, further degrading the SHE, in terms of a significant short channel effect. We also found that the incremental channel resistance is proportional to the incremental channel local temperature, whose slope indicates the degree of SHE, and the slope of pFinFET is larger than that of nFinFET. Finally, SHE will cause 10% and 14% degradation of IdVds for nand pFinFET respectively. This can be reasonably explained by the decay of saturation velocity in high temperature. The results obtained based on this methodology will help us on the understanding of the SHE impact on a nano-scaled FinFET device.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Plasma Charging Effect on the Reliability of Copper BEOL Structures in
           Advanced FinFET Technologies

    • Authors: Yi-Pei Tsai;Peng-Chun Liou;Chrong Jung Lin;Ya-Chin King;
      Pages: 875 - 883
      Abstract: Plasma induced damage remains a critical concern in VLSI manufacturing process as a result of the introduction of the high-k and low-k dielectric layers and complicated 3D structures in advanced technology nodes. In this paper, the level of plasma induced charging distribution on a wafer is studied comprehensively. A strong correlation between the charging level and the geometry as well as densities ratio of via structures in dual damascene BEOL copper processes is found. In addition, the effect of plasma charging on Cu corrosion is studied in this paper. To investigate the root causes of such failure mode, an in-situ plasma charging recorder is embedded with RC test structures formed by Cu BEOL processes. The recorded charging current has a strong effect on the reliability levels of the via-chain resistors and backend capacitors. Experimental data suggests that plasma charging effect not only leads to gate dielectric stress on transistors but also affects the reliability performances of the copper interconnects.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • InGaAs Capacitor-Less DRAM Cells TCAD Demonstration

    • Authors: Carlos Navarro;Santiago Navarro;Carlos Marquez;Luca Donetti;Carlos Sampedro;Siegfried Karg;H. Riel;Francisco Gamiz;
      Pages: 884 - 892
      Abstract: 2D numerical TCAD simulations are used to infer the behavior of III-V capacitor-less dynamic RAM (DRAM) cells. In particular, indium gallium arsenide on insulator technology is selected to verify the viability of III-V meta-stable-dip RAM cells. The cell performance dependence on several parameters (such as the back-gate voltage, semiconductor thickness, indium/gallium mole fraction or interface traps) and simulation models (like ballisticity or spatial quantum confinement) is analyzed and commented. Functional cells are presented and compared with analogous silicon 1T-DRAM memories to highlight the advantages and drawbacks.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Normally-OFF GaN MIS-HEMT With F− Doped Gate Insulator Using Standard
           Ion Implantation

    • Authors: Chia-Hsun Wu;Ping-Cheng Han;Quang Ho Luc;Ching-Yi Hsu;Ting-En Hsieh;Huan-Chung Wang;Yen-Ku Lin;Po-Chun Chang;Yueh-Chin Lin;Edward Yi Chang;
      Pages: 893 - 899
      Abstract: A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage ( ${V} _{mathrm{ th}}$ ) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F− doped devices. The fabricated F− doped device exhibits a threshold voltage of +0.68 V at ${I} _{mathrm{ DS}}= 5~mu text{A}$ /mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 1010. For thermal stability consideration of fluorine dopant, the ${V} _{mathrm{ th}}$ -thermal stability test and positive bias temperature instability test were also discussed.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Ferroelectric HfZrOx FETs on SOI Substrate With Reverse-DIBL
           (Drain-Induced Barrier Lowering) and NDR (Negative Differential

    • Authors: Kuan-Ting Chen;Siang-Sheng Gu;Zheng-Ying Wang;Chun-Yu Liao;Yu-Chen Chou;Ruo-Chun Hong;Shih-Yao Chen;Hong-Yu Chen;Gao-Yu Siang;Chieh Lo;Pin-Guang Chen;M.-H. Liao;Kai-Shin Li;Shu-Tong Chang;Min-Hung Lee;
      Pages: 900 - 904
      Abstract: Ferroelectric-Hf1−xZrxO2 FETs on silicon on insulator (SOI) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis ( $V_{T}$ -shift), which is based on the capacitance matching concept. The minimum reverse SS = 45 mV/dec and 52 mV/dec are obtained experimentally for SOI and bulk-Si, respectively. The steep SS range (
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Improved Distribution of Resistance Switching Through Localized Ti-Doped
           NiO Layer With InZnOx/CuOx Oxide Diode

    • Authors: Minho Song;Hyunki Lee;David H. Seo;Hyeon-Jun Lee;June-Seo Kim;Hui-Sup Cho;Hong-Kun Lyu;Sunae Seo;Myoung-Jae Lee;
      Pages: 905 - 909
      Abstract: Asymmetric sized single oxide diode (InZnOx/CuOx) with single resistor (Ti-doped NiO) device (1D-1R) was integrated into a crossbar array at room temperature to provide high current through the diode while keeping resistance switching localized in a small area. The Ti (0.1 wt %) doped NiO layer was fabricated inside an inverted cone-structure to localize switching and improve general device performance. We were able observe resistance switching up to around 100 cycles in the 1D-1R structure. In addition, the addition of the diode to the structure acted as an external resistance suppressing overflow current during Ti-doped NiO switching from a high resistance state to a low resistance state, thus improving switching distribution in both low (average = $3.2times 10^{-5} Omega $ , standard deviation = $1.3times 10^{-6} $ ) and high (average = $2.8times 10^{-6} Omega $ , standard deviation = $6.7times 10^{-7}$ ) resistance states.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • $kT/q$+ +Non-Hysteretic+Negative+Capacitance+FET+Using+Capacitance+Matching&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Pavlo&;Subin+Lee;Jae-Hoon+Han;Jin+Dong+Song;Sang-Hyeon+Kim;">Simulation Study on the Design of Sub- $kT/q$ Non-Hysteretic Negative
           Capacitance FET Using Capacitance Matching

    • Authors: Pavlo Bidenko;Subin Lee;Jae-Hoon Han;Jin Dong Song;Sang-Hyeon Kim;
      Pages: 910 - 921
      Abstract: In this paper, approaches to obtain the sub-kT/q non-hysteretic operation mode in negative capacitance (NC) field-effect-transistors for a wide band of applied gate voltages, using capacitance matching, were systematically investigated using TCAD simulation. Unlike certain previous studies, in which the desired operation conditions were received for specific structures and materials, this study presents for the first time a general approach for matching arbitrary MOSFETs with various ferroelectric (FE) materials. This study shows that depending on the initial capacitance matching which represents the best possible subthreshold slope for the preliminary chosen base structure and FE material, any further optimization process can be different. Additionally, for the first time, FE materials were grouped with respect to the shape of their C–V curves in the NC region. This paper shows that with respect to the base structure, certain types of FEs are more preferable to obtain the sub-kT/q operation in a non-hysteretic manner for the wide band of applied voltages. In addition, the impacts of various parameters including the depletion capacitance, supply voltage, gate oxide capacitance, buried oxide capacitance on the capacitance matching were systematically investigated.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Electrothermal Evaluation of AlGaN/GaN Membrane High Electron Mobility
           Transistors by Transient Thermoreflectance

    • Authors: Marko J. Tadjer;Peter E. Raad;Pavel L. Komarov;Karl D. Hobart;Tatyana I. Feygelson;Andrew D. Koehler;Travis J. Anderson;Anindya Nath;Bradford Pate;Fritz J. Kub;
      Pages: 922 - 930
      Abstract: A novel wet etch process for fabrication of large-area AlGaN/GaN membranes is reported, along with an evaluation of membrane-high electron mobility transistor (HEMT) electrothermal performance up to 1.9 W/mm. Hall measurements showed negligible post-etch change in membrane-HEMT sheet resistance, Hall mobility and carrier concentration. Static (dc) current-voltage characteristics showed negligible change in on resistance ( ${R} _{mathrm{ ON}}$ ), although ${I} _{mathrm{DS,MAX}}$ was significantly reduced due to increased self-heating in the absence of the Si substrate. Pulsed output characteristics were similarly affected as self-heating was expected to be still present at ms pulse widths. In the off state, the drain leakage current was measurably lower by about an order of magnitude. Pulsed-mode off-state step stress showed a dynamic on resistance improvement by about a factor of 2 when both sides of the membrane were passivated by SiN. A peak temperature of 148.5 °C was measured on the membrane HEMT using transient thermoreflectance imaging. These initial results indicate that substrate removal does not necessarily cause device degradation, and can be a promising step in improving HEMT reliability in future generations of power devices.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • High Breakdown-Voltage (>2200 V) AlGaN-Channel HEMTs With
           Ohmic/Schottky Hybrid Drains

    • Authors: Weihang Zhang;Jincheng Zhang;Ming Xiao;Li Zhang;Yue Hao;
      Pages: 931 - 935
      Abstract: In this paper, a high breakdown voltage of more than 2200 V in high-electron-mobility transistors (HEMTs) with AlGaN channel and a novel ohmic/Schottky-hybrid drain contact is achieved, which is the record breakdown voltage ever achieved on AlGaN-channel HEMTs. The fabricated device exhibits a high on/off ratio of $7times 10^{9}$ and a low subthreshold swing of 64 mV/decade, enabled by the AlGaN channel and wet treatment. Furthermore, it exhibits excellent high-temperature output characteristics and dynamic ${I} _{D}$ – ${V} _{D}$ characteristics. Even though both the AlGaN channel and the ohmic/Schottky-hybrid drain have certain impact on the on-state resistance because of the higher sheet resistance and drain contact resistance, these results indicate the significance and potential of AlGaN-channel HEMTs with a hybrid drain architecture in high-voltage applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Compact Pixel Circuit for Externally Compensated AMOLED Displays

    • Authors: Hing-Mo Lam;Ying Wang;Min Zhang;Hailong Jiao;Shengdong Zhang;
      Pages: 936 - 941
      Abstract: Nonuniformity and aging are two major issues with the pixel circuits of active-matrix organic light-emitting diode displays. External compensation scheme is typically employed to mitigate these two issues, since various off-panel resources, such as on-chip processors and memory arrays, can be utilized. A new pixel circuit with feedback path for the external compensation scheme is proposed in this paper. The data line and monitor line are shared for two adjacent columns of pixel circuits to increase the aperture opening ratio of display panel. The number of thin-film transistors attached to each data line is reduced by 50% with the proposed pixel circuit compared to the traditional pixel circuit. The average power consumption of the normal display operation is thereby reduced by 15%.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and
           Nanosheet FETs

    • Authors: Jun-Sik Yoon;Jinsu Jeong;Seunghwan Lee;Rock-Hyun Baek;
      Pages: 942 - 947
      Abstract: In this paper, we systematically evaluate dc/ac performances of sub-7-nm node fin field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) using fully calibrated 3-D TCAD. The stress effects of all the devices were carefully considered in terms of carrier mobility and velocity averaged within the active regions. For detailed AC analysis, the parasitic capacitances were extracted and decomposed into several components using TCAD RF simulation platform. FinFETs improved the gate electrostatics by decreasing fin widths to 5 nm, but the fin heights were unable to improve RC delay due to the trade-off between on-state currents and gate capacitances. The NSFETs have better on-state currents than do the FinFETs because of larger effective widths (Weff) under the same device area. Particularly p-type NSFETs have larger compressive stress within the active regions affected by metal gate encircling all around the channels, thus improving carrier mobility and velocity much. On the other hand, the NSFETs have larger gate capacitances because larger Weff increase the gate-to-source/drain overlap and outerfringing capacitances. In spite of that, sub-7-nm node NSFETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Impact of Atomic Layer Deposition High k Films on Slow Trap Density in Ge
           MOS Interfaces With GeOx Interfacial Layers Formed by Plasma Pre-Oxidation

    • Authors: Mengnan Ke;Mitsuru Takenaka;Shinichi Takagi;
      Pages: 950 - 955
      Abstract: For realizing of Ge complementary metal–oxide–semiconductor with a Ge gate stack with thin equivalent oxide thickness, low interface state density ( $text{D}_{mathrm{ it}}$ ) and high reliability. In this paper, we examine the slow trap behaviors in the ALD high-k materials including Al2O3, Y2O3, HfO2, and La2O3 on GeOx/Ge interfaces, where the GeOx interfacial layers are formed by plasma pre-oxidation. The C–V curves, $text{D}_{mathrm{ it}}$ and slow trap density of the high-k/GeOx/n- and p- Ge MOS capacitors are evaluated and compared. The Ge 3d spectra in X-ray photoemission spectroscopy are also compared among the Al2O3, Y2O3, HfO2, and La2O3 on GeOx/Ge structures. It is found that Al2O3 provides the lowest slow trap density for both electrons and holes in comparison with Y2O3, HfO2, and La2O3 high-k films, while similar $text{D}_{mathrm{ it}}$ values are observed among the MOS interfaces with Al2O3, Y2O3, HfO2, and La2O3. The additional slow traps in the MOS capacitors with Y2O3, HfO2, and La2O3 are attributable to any defects in the high-k films and/or the interfaces with GeOx.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Editorial to J-EDS ESSDERC 2017 Special Issue

    • Authors: Montserrat Nafría;Nadine Collaert;
      Pages: 953 - 954
      Abstract: The papers in this special section were presented at the 2017 European Solid-State Device Research Conference (ESSDERC).
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • On the Understanding of Cathode Related Trapping Effects in GaN-on-Si
           Schottky Diodes

    • Authors: Thomas Lorin;William Vandendaele;Romain Gwoziecki;Yannick Baines;Jérôme Biscarrat;Marie-Anne Jaud;Charlotte Gillot;Matthew Charles;Marc Plissonnier;G. Ghibaudo;F. Gaillard;
      Pages: 956 - 964
      Abstract: Cathode related current collapse effect in GaN on Si Schottky barrier diodes is investigated in this paper. Capacitance and current relaxation measurements on diodes and gated-Van Der Pauw are associated with temperature dependent dynamic ${R_{mathrm{ ON}}}$ transients analysis to identify the parasitic trapping locations in the devices. We show here that the main part of the current collapse at the cathode comes from a combination of electron trapping in the passivation layer and in a carbon related trap in the GaN buffer layers ( ${E_{A}} = mathrm {E_{T}} - {E_{V}} simeq 0.9 ,mathrm {eV}$ ) that can be studied independently by using the appropriate stress configurations. These two parasitic effects can lead to long recovery time (>1 ks) after reverse bias stress.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Tunable RF Phase Shifters Based on Vanadium Dioxide Metal Insulator

    • Authors: Emanuele Andrea Casu;Nicolò Oliva;Matteo Cavalieri;Andrei A. Müller;Alessandro Fumarola;Wolfgang A. Vitale;Anna Krammer;Andreas Schüler;Montserrat Fernández-Bolaños;Adrian M. Ionescu;
      Pages: 965 - 971
      Abstract: This paper presents the design, fabrication, and electrical characterization of a reconfigurable RF capacitive shunt switch that exploits the electro-thermally triggered vanadium dioxide (VO2) insulator to metal phase transition. The RF switch is further exploited to build wide-band RF true-time delay tunable phase shifters. By triggering the VO2 switch insulator to metal transition (IMT), the total capacitance can be reconfigured from the series of two metal–insulator–metal (MIM) capacitors to a single MIM capacitor. The effect of bias voltage on losses and phase shift is investigated, explained, and compared to the state of the art in the field. We report thermal actuation of the devices by heating the devices above VO2 IMT temperature. By cascading multiple stages a maximum of 40° per dB loss close to 7 GHz were obtained.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Physical Model for the Hysteresis in MoS2 Transistors

    • Authors: Theresia Knobloch;Gerhard Rzepa;Yury Yu. Illarionov;Michael Waltl;Franz Schanovsky;Bernhard Stampfer;Marco M. Furchi;Thomas Mueller;Tibor Grasser;
      Pages: 972 - 978
      Abstract: Even though the hysteresis in the gate transfer characteristics of two-dimensional (2D) transistors is a frequently encountered phenomenon, the physics behind it are up to now only barely understood, let alone modeled. Here, we demonstrate that the hysteresis phenomenon can be captured accurately by a previously established non-radiative multiphonon model describing charge capture and emission events in the surrounding dielectrics. The charge transfer model is embedded into a drift-diffusion based TCAD simulation environment, which was adapted to 2D devices. Our modeling setup was validated against measurement data on a back-gated single-layer MoS2 transistor with SiO2 as a gate dielectric. We use the modeling approach to gain a thorough understanding of the hysteresis, which will help to control this problem in future devices.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel

    • Authors: Tarun Agarwal;Gianluca Fiori;Bart Soree;Iuliana Radu;Marc Heyns;Wim Dehaene;
      Pages: 979 - 986
      Abstract: In this paper, the 2-D materials-based lateral TFETs are holistically assessed by co-optimizing the material parameters, device designs, and digital circuit figure-of-merits, e.g., energy consumption and delay. Effect of material parameters such as effective mass and bandgap are studied using a two-band quantum simulation approach in the ballistic regime. The selection of 2-D material parameters is discussed from the energy-delay perspective. Single-gate and double-gate 2-D TFETs are compared with the optimum material parameters. Using a simple analytical model for 2-D TFETs, the quantum simulation results for different materials and device designs are analyzed. We show that the gate-to-source fringing fields play a significant role in 2-D TFETs performance. To mitigate the effect of fringing fields on tunneling lengths, an interfacial layer (IL) is introduced between high- $kappa $ and 2-D material, resulting a 3– $4times $ increase in ON current. Using circuit-level metrics, we show that a tri-layer black phosphorus (BP) TFET using IL can outperform monolayer BP MOSFETs for the supply voltages below 0.5 V.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • SPICE Modeling of Photoelectric Effects in Silicon With Generalized

    • Authors: Chiara Rossi;Pietro Buccella;Camillo Stefanucci;Jean-Michel Sallese;
      Pages: 987 - 995
      Abstract: Modeling photoelectric effects in semiconductors with electrical simulators is demonstrated in typical 1-D and 2-D architectures. The concept is based on a coarse meshing of the semiconductor with the so-called generalized lumped devices, where equivalent voltages and currents are used in place of minority carrier excess concentrations and minority carrier gradients, respectively, and where the light-induced excess carrier concentration in silicon is introduced by means of internal current sources. Generation, propagation, and collection of these minority carriers are analyzed for different structures which can behave as photosensors or solar cells. Both static and transient operations are found in good agreement with TCAD numerical simulations while using the same physical and geometrical parameters.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Characterization and Compact Modeling of Nanometer CMOS Transistors at
           Deep-Cryogenic Temperatures

    • Authors: Rosario M. Incandela;Lin Song;Harald Homulle;Edoardo Charbon;Andrei Vladimirescu;Fabio Sebastiano;
      Pages: 996 - 1006
      Abstract: Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $mu text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K

    • Authors: Arnout Beckers;Farzan Jazaeri;Christian Enz;
      Pages: 1007 - 1018
      Abstract: This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on various geometries. The simplified-EKV compact model is used to accurately capture the dc characteristics of this technology down to 4.2 K and to demonstrate the impact of cryogenic temperatures on the essential analog figures-of-merit. A new body-partitioning methodology is then introduced to obtain a set of analytical expressions for the electrostatic profile and the freeze-out layer thickness in field-effect transistors operating from deep-depletion to inversion. The proposed physics-based model relies on the drift-diffusion transport mechanism to obtain the drain current and subthreshold swing, and is validated with the experimental results. This model explains the degradation in subthreshold swing at deep-cryogenic temperatures by the temperature-dependent occupation of interface charge traps. This leads to a degradation of the theoretical limit of the subthreshold swing at deep-cryogenic temperatures.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Built-In Bias Generation in Anti-Ferroelectric Stacks: Methods and Device

    • Authors: Milan Pešić;Taide Li;Valerio Di Lecce;Michael Hoffmann;Monica Materano;Claudia Richter;Benjamin Max;Stefan Slesazeck;Uwe Schroeder;Luca Larcher;Thomas Mikolajick;
      Pages: 1019 - 1025
      Abstract: The discovery of ferroelectric (FE) properties in binary oxides has enabled CMOS compatible and scalable FE memories. Recently, we reported a simple approach to introduce non-volatility into state-of-the-art dynamic random-access memory stacks that show anti-FE (AFE) behavior. By employing a pair of electrodes with different work functions, a built-in bias is generated. Consequently, this bias modulates the energy potential of the AFE and enables two stable non-volatile states. Using this approach, a significant endurance improvement compared to hafnia-based FE memories can be obtained. In this paper, we investigate the possibility to bypass the usage of asymmetric workfunction electrodes. Using the interface-engineering approach, based on fixed charge or dipole formation, we show two additional methods for built-in bias generation within AFE layer stacks. By characterizing the film properties and performance of AFE capacitors, we compare and investigate retention and endurance of both work function-difference-based and interface-based AFE non-volatile memory. Finally, for the first time we present the concept of a binary oxide-based AFE tunnel junction that leverages both an interface and work function engineered AFE stack.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Ultrahigh-Sensitive CMOS pH Sensor Developed in the BEOL of Standard 28 nm
           UTBB FDSOI

    • Authors: Getenet Tesega Ayele;Stephane Monfray;Serge Ecoffey;Frédéric Boeuf;Jean-Pierre Cloarec;Dominique Drouin;Abdelkader Souifi;
      Pages: 1026 - 1032
      Abstract: This paper reports ultrahigh-sensitive and ultralow-power CMOS compatible pH sensors that are developed in the back-end-of-line (BEOL) of industrial 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) transistors. Fabricating the sensing gate and the control gate of the sensors in a capacitive divider circuit, CMOS compatible pH sensors are demonstrated where the front gate bias is applied through a control gate rather than a bulky reference electrode. On the other hand, the strong electrostatic coupling between the front gate and the back gate of FDSOI devices provide an intrinsic signal amplification feature for sensing applications. Utilizing an atomic layer deposited aluminum oxide (Al2O3) as a pH sensing film, pH sensors having a sensitivity of 475 mV/pH and 730 mV/pH in the extended gate and BEOL configuration, respectively, are reported. Sensitivities of both configurations are superior to state-of-the-art low power ion-sensitive field-effect transistors. The small sensing area and the FDSOI-based low power technology of the device make the sensors ideal for the IoT market. The proposed approach has been validated by TCAD simulation, and demonstrated through experimental measurements on proof-of-concept extended gate pH sensors and on sensors that are developed in the BEOL of industrial UTBB FDSOI devices.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Strained Silicon Complementary TFET SRAM: Experimental Demonstration and

    • Authors: G. V. Luong;S. Strangio;A. T. Tiedemann;P. Bernardy;S. Trellenkamp;P. Palestri;S. Mantl;Q. T. Zhao;
      Pages: 1033 - 1040
      Abstract: A half SRAM cell with strained Si nanowire complementary tunnel-FETs (TFETs) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs. Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage of the access-transistor at certain bias configurations leads to malfunctioning storage operation, even without the contribution of the ambipolar behavior. At large $V_{mathrm {{DD}}}$ , lowering of the bit-line bias is needed to mitigate such effect, demonstrating functional hold, read and write operations. Circuit simulations were carried out using a Verilog-A compact model calibrated on the experimental TFETs, providing a better understanding of the TFET SRAM operation at different supply voltages and for different cell sizing and giving an estimate of the dynamic performance of the cell.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Polarity Control of Top Gated Black Phosphorous FETs by Workfunction
           Engineering of Pre-Patterned Au and Ag Embedded Electrodes

    • Authors: Nicolò Oliva;Emanuele Andrea Casu;Wolfgang A. Vitale;Igor Stolichnov;Adrian Mihai Ionescu;
      Pages: 1041 - 1047
      Abstract: We propose and experimentally demonstrate top-gated complementary n- and p-type black phosphorous field effect devices (FETs) by engineering the workfunction of pre-patterned electrodes embedded in a SiO2 bottom layer. Pre-patterned electrodes offer the advantages of reducing the exposure time of exfoliated flakes to oxidant agents with respect to top-contacted devices and maximizing the accessible area for sensing applications. The presented devices are realized by mechanical exfoliation of multilayer black phosphorous flakes on top of pre-patterned embedded source and drain contacts. A capping layer consisting of 15-nm thick Al2O3 is deposited to prevent flakes degradation and serves as top gate dielectric. The silicon substrate can be exploited as back gate to program the FETs threshold voltage. We deposited both Au and Ag embedded contacts to investigate the impact of electrodes workfunction on BP FETs polarity. Au contacted devices show p-type conduction with ON/OFF current ratio 140 and holes mobility up to 40 cm $^{2}text{V}^{-1}text{s}^{-1}$ . Devices with Ag contacts exhibit prevalent n-type conduction with ON/OFF ratio 1700 and electron mobility 2 cm $^{2}text{V}^{-1}text{s}^{-1}$ . The reported results represent a substantial improvement with respect to reported alternative implementations of black phosphorous FETs with pre-patterned, non-embedded electrodes. Moreover, we demonstrate that Ag is a promising metal for electron injection in black phosphorous FETs.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Tunneling Transistors Based on MoS2/MoTe2 Van der
           Waals Heterostructures

    • Authors: Yashwanth Balaji;Quentin Smets;César Javier Lockhart De La Rosa;Anh Khoa Augustin Lu;Daniele Chiappe;Tarun Agarwal;Dennis H. C. Lin;Cedric Huyghebaert;Iuliana Radu;Dan Mocuta;Guido Groeseneken;
      Pages: 1048 - 1055
      Abstract: 2-D transition metal dichalcogenides (TMDs) are promising materials for CMOS application due to their ultrathin channel with excellent electrostatic control. TMDs are especially well suited for tunneling field-effect transistors (TFETs) due to their low-dielectric constant and their promise of atomically sharp and self-passivated interfaces. Here, we experimentally demonstrate band-to-band tunneling (BTBT) in Van der Waals heterostructures formed by MoS2 and MoTe2. Density functional theory simulations of the band structure show our MoS2-MoTe2 heterojunctions have a staggered band alignment, which boosts BTBT compared to a homojunction configuration. Low-temperature measurements and electrostatic simulations provide understanding toward the role of Schottky contacts and the material thickness on device performance. Negative differential transconductance-based devices were also demonstrated using a different device architecture. This paper provides the prerequisites and challenges required to overcome at the contact region to achieve a steep subthreshold slope and high ON-currents with 2-D-based TFETs.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Modeling of Carrier Trapping and Its Impact on Switching Performance

    • Authors: Mitiko Miura-Mattausch;Hideyuki Kikuchihara;Tapas Kumar Maiti;Dondee Navarro;Hans Jürgen Mattausch;
      Pages: 1056 - 1063
      Abstract: Requirements for compact modeling to predict circuit power loss accurately are the focus of this investigation. Most important is the capturing of the differences between an ideal carrier reaction within the used devices and the reality during circuit operation. For this purpose the carrier trapping/detrapping, which occurs during circuit operation, has to be modeled accurately in addition to the conventional device characteristics. Carrier trapping events prevent device operation according to the ideal carrier dynamics and result in energy losses. It is verified that the influence of the carrier trapping, extracted by dc measurements, is not sufficient. Additionally, the dynamic switching performance must be precisely analyzed to extract the time constants involved in the carrier-trapping events. This is achieved by compact modeling based on solving the complete Poisson equation, which provides a simple and accurate modeling approach.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Fabrication and Study on Red Light Micro-LED Displays

    • Authors: Ray-Hua Horng;Huan-Yu Chien;Fu-Gow Tarntair;Dong-Sing Wuu;
      Pages: 1064 - 1069
      Abstract: A red-light micro LED display made of an AlGaInP epilayer with a resolution of $64 times 32$ pixels, a pitch of $175~ mu {mathrm {m}}$ and a luminous area of $1 ~{mathrm {cm}} times 0.5~ {mathrm {cm}}$ was fabricated and characterized in this study. The AlGaInP epilayer was bonded to double polished sapphire substrate by wafer-bonding technique and then removing the absorbing GaAs substrate. In this design, the ITO was applied as one of the conducting electrodes of the emitting surface, which can be beneficial since the emitting light is not shielded by metal electrodes. The other key process for LED panel fabrication is planarization. Polymer material was used to fill the gap between each pixel, which was used to prevent a short or open circuit using the planarization process. The driving mode of this display is passive multi-electrode addressable controlling. The luminance of this micro-LED panel is more than 450 nits with an operating voltage of 3 V which is three times higher than that of the OLED operating in the same driving mode.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate

    • Authors: Stefan Glass;Kimihiko Kato;Lidia Kibkalo;Jean-Michel Hartmann;Shinichi Takagi;Dan Buca;Siegfried Mantl;Zhao Qing-Tai;
      Pages: 1070 - 1076
      Abstract: In this combined experiment and simulation study we investigate a SiGe/Si based gatenormal tunneling field-effect transistor (TFET) with a pillar shaped contact to the tunneling junction which brings forth two significant advantages. The first, is improved electrostatics at the boundary of the tunneling junction which helps to diminish the influence of adverse tunneling paths, and thus, substantially sharpens the device turn on. The second, is a simplified fabrication of a dual-metal gate using a selfaligned process. We demonstrate the feasibility of the process and show the positive effect of a dual-metal gate in experiment. Overall the paper provides general guidelines for the improvement of the subthreshold swing in gate-normal TFETs which are not restrained to the material system.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Titanium Dioxide-Based Memristive Thin Film: A Correlation Study Between
           the Experimental Work and Simulation Program With Integrated Circuit
           Emphasis Hyperbolic Sine Models

    • Authors: Raudah Abu Bakar;Nur Syahirah Kamarozaman;Wan Fazlida Hanim Abdullah;Sukreen Hana Herman;
      Pages: 1077 - 1090
      Abstract: This paper presents a correlation study between experimental results of titanium dioxide (TiO2)-based memristors and various hyperbolic sine function models. The current–voltage (I-V) characteristics of sol-gel-derived TiO2 thin film annealed at 250°C were correlated with the reported hyperbolic sine function simulation program with integrated circuit emphasis memristor models. The correlation study showed that the existing models were not fitted well with our experimental data. The models with the lowest root means square errors were then combined together to achieve better fitting result. Further, experimental results of TiO2 thin films fabricated by varying the annealing temperature at 350 °C and 450 °C were correlated to the proposed model to further elucidate the device operation. The parameters were then analyzed by multiplying and dividing the simulation results by two. It was found that both the Schottky and tunneling mechanisms had a significant impact in shaping the I-V characteristic of annealed TiO2 thin film and device conductivity. The state variable derivative on the other hand caused changes in device threshold voltage. The knowledge gained from the fitting parameters of the proposed model enables us to predict the performance of fabricated memristive device and engineer the process parameters for desired memristive behavior.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Simulation Study of a Super-Junction Deep-Trench LDMOS With a Trapezoidal

    • Authors: Junji Cheng;Ping Li;Weizhen Chen;Bo Yi;Xing Bi Chen;
      Pages: 1091 - 1096
      Abstract: A super-junction (SJ) deep-trench (DT) lateral double-diffused metal-oxide-semiconductor transistor improved by tilting the DT sidewalls is proposed. The incline of sidewalls introduces some vertically varying charges into the SJ drift regions on both sides of the DT. Therefore, the adverse effect of the DT on the surface electric field distribution is withstood, and the device can approach an ideal state of charge-balance. Simulation results show compared with a conventional device, which has the same drift region concentration and the same size but the perpendicular sidewalls, the proposed device presents a better figure of merit over 2.5 times higher. Besides, a feasible fabrication process for the proposal is presented and discussed.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Quantitative TLP Waveform Analysis for GGNmosts

    • Authors: Gijs De Raad;
      Pages: 1097 - 1114
      Abstract: A method to extract internal physical quantities from transmission line pulse (TLP) waveforms of grounded gate nMOS electro-static discharge protections is presented. The extraction method is based on two time-constants that appear in the transient voltage waveforms that are part of any TLP result. The first time-constant relates the measured current to the amount of internally stored charge. The second time-constant is related to the life time of internally stored holes via the lateral diffusion of holes that takes place during current ramp-up. From these two extracted time-constants, a complete set of internal quantities including the amount of stored charge, hole lateral diffusion velocity, and the ratio between the internal hole- and electron current, can be calculated from a single TLP pulse. As a result, trends and correlations in the internal quantities can be shown explicitly. This paper shows a strongly increasing hole- to electron current ratio with increasing peak current density during ramp-up. The extraction method is validated using 3D-TCAD and formal mathematical treatment. Developing the theoretical background to this internal parameter extraction method has led to new physical insights. The most prominent of these is a theoretical relation between the peak current density during current ramp-up and the hole life time.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Vacuum Nano-Triode in Nothing-On-Insulator Configuration Working in
           Terahertz Domain

    • Authors: Cristian Ravariu;
      Pages: 1115 - 1123
      Abstract: This paper presents for the first time a new configuration of the nothing on insulator (NOI) structure: a vacuum NOI-triode. The main novelty of the new structure consists in the gate that is now part of the vacuum region as in conventional triodes. Each NOI-triode is introduced by a technological plan, followed by the concept validation and characteristics analysis. On the other hand, these NOI-triodes evolve from the NOI-transistor configuration. Consequently, some specific parameters to transistors are improved and permanently compared to some fabricated vacuum nano-transistors that are proposed in literature. For instance, the sub-threshold swing is suddenly decreased from 0.65...4 V/dec to 0.090 V/dec. A low swing is responsible to a high cutoff frequency. The paid price for the NOI-triode is a non-null gate current. To preserve the gained advantages and to keep as low as possible the IGate/IAnode ratio, a special work regime must be selected. This paper devotes a large static and dynamic analysis to find the convenient work regime and possible technological solutions. The drive voltages can be decreased to 1 V, ION current of micro-amperes and excellent IOFF current of atto-amperes. The internal capacitances of 0.9 aF recommend the NOI-triodes to 0.35 ... 4 THz working regime.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • $beta$+ -Ga2O3+Nanomembrane+Field-Effect+Transistor&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jiyeon&;Oukjae+Lee;Geonwook+Yoo;">Abnormal Bias-Temperature Stress and Thermal Instability of $beta$ -Ga2O3
           Nanomembrane Field-Effect Transistor

    • Authors: Jiyeon Ma;Oukjae Lee;Geonwook Yoo;
      Pages: 1124 - 1128
      Abstract: In this paper, we report on the electrical and thermal instability of β-Ga2O3 nanomembrane field-effect transistor with a bottom-gate configuration. The fabricated device exhibits high electrical performance of field-effect mobility of up to 60.9 cm2/V·s, on/off-current ratio of 109 and subthreshold slope of 210 mV/dec. However, we observe abnormal positive threshold voltage (VTH) shifts under negative bias-temperature stress at an elevated operating temperature of 80 °C as well as under temperature-dependent transfer characteristics up to 200 °C. This abnormal instability is significantly influenced by the surface depletion effect, and is discussed using energy band diagram. The opposite VTH shift was achieved by applying atomic-layer deposited Al2O3 passivation layer.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Consideration of UFET Architecture for the 5 nm Node and Beyond Logic

    • Authors: Uttam Kumar Das;Geert Eneman;Ravi Shankar R. Velampati;Yogesh Singh Chauhan;K. B. Jinesh;Tarun K. Bhattacharyya;
      Pages: 1129 - 1135
      Abstract: In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and beyond logic transistor. The intended device has a gate formed vertically downward, with added spacers along the gate to S/D sidewall. In doing so, the recessed device having longer channel length (than the defined gate footprint) would be a constructive approach to limit the short channel effects (SCE). The novel transistor has the potential to enable the scaling of gate length (footprint) less than 10 nm and contacted gate pitch below 32 nm, resulting in the smallest active area (on-wafer footprint) for a single device. Novel process steps are simulated depicting easier fabrication while the electrical analysis shows a better electrostatic control over any unwanted leakage flows. Along with the area scaling and SCE control, the planar upper surface allows a vertical integration. Growing another flipped device on top surface permits the designer to implement a logic circuit on a footprint of a single device, achieving ~50% area gain further. TCAD based simulations were performed to design and characterize the performances of an individual device and the vertical inverter.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • $text{m}{Omega}+cdot$+ cm2+for+Power+Device+Applications&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Huan-Chung&;Franky+Juanda+Lumbantoruan;Ting-En+Hsieh;Chia-Hsun+Wu;Yueh-Chin+Lin;Edward+Yi+Chang;">High-Performance LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs With 850-V 0.98-
           $text{m}{Omega} cdot$ cm2 for Power Device Applications

    • Authors: Huan-Chung Wang;Franky Juanda Lumbantoruan;Ting-En Hsieh;Chia-Hsun Wu;Yueh-Chin Lin;Edward Yi Chang;
      Pages: 1136 - 1141
      Abstract: We demonstrate the electrical performances of the quaternary InAlGaN/GaN MIS-HEMTs with high quality SiNx gate dielectric and surface passivation layer deposited by low pressure chemical vapor deposition (LPCVD) at 780 °C. Excellent LPCVD-SiNx/InAlGaN interface and SiNx film quality were obtained, resulting in very high output current density, a very small threshold voltage hysteresis and steep subthreshold slope. The LPCVD-SiNx/InAlGaN/GaN MIS-HEMT device exhibited high on/off current ratio, large gate voltage swing, high breakdown voltage, and very low dynamic on-resistance (RON) degradation, meaning effective current collapse suppression compared to the plasma enhanced chemical vapor deposition -SiNx/InAlGaN/GaN MIS-HEMTs. The corresponding specific on-resistance (RON,sp) for LPCVD-SiNx device was as low as 0.98 mΩ·cm2, yielding a high figure of merit of 737 MW/cm2. These results demonstrate a great potential of the LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs for high-power switching applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • ${Gamma}$+ -Gate+MOS-HFETs+With+Composite+Al2O3/TiO2+Passivation+Oxides&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Ching-Sung&;Xue-Cheng+Yao;Yi-Ping+Huang;Wei-Chou+Hsu;">Al2O3-Dielectric InAlN/AlN/GaN ${Gamma}$ -Gate MOS-HFETs With Composite
           Al2O3/TiO2 Passivation Oxides

    • Authors: Ching-Sung Lee;Xue-Cheng Yao;Yi-Ping Huang;Wei-Chou Hsu;
      Pages: 1142 - 1146
      Abstract: Novel Al2O3-dielectric InAlN/AlN/GaN Γ-Gate metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with composite Al2O3/TiO2 passivation oxides formed by using ultrasonic spray pyrolysis deposition/RF sputtering, respectively, are investigated. The r-gate includes a 1-μm long active gate on the Al2O3 dielectric and a 1-μm long field-plate on the composite Al2O3/TiO2 oxides. The present Γ-Gate MOS-HFET has demonstrated excellent on/off current ratio (Ion/Ioff) of 8.2 x 1010, subthreshold swing of 102.3 mV/dec, maximum extrinsic transconductance of (gm,max) of 210.1 mS/mm, maximum drain-source saturation current density (IDS,max) of 868.3 mA/mm, two-terminal off-state gate-drain breakdown voltage (BVGD) of -311.2 V, three-terminal drain-source breakdown voltage (BVDS) of 237 V at VGS = -10 V, and power-added efficiency of 39.9% at 2.4 GHz. A conventional Schottky-gate HFET and TiO2-dielectric MOS-HFET were also prepared in comparison. The present design has shown superior dc/RF device performance. It is suitable for high-power RF circuit applications.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Role of Shape Factor in Forming Surface Electric Field Basin in RESURF
           Lateral Power Devices and its Optimization Design

    • Authors: Jun Zhang;Yu-Feng Guo;David Z. Pan;
      Pages: 1147 - 1153
      Abstract: The drift region shape factor (Ld/t) plays a sophisticated role in affecting reduced surface field (RESURF) effect and breakdown characteristics. In this paper, based on the effective doping concentration (EDC) theory, an Improved EDC concept is proposed to explore the impact of shape factor on 2-D coupling effect in RESURF lateral power devices. The Improved EDC concept indicates that the sophisticated 2-D coupling in N-well resulting an effective N-I-P type drift region. Thus, the surface electric field basin may exist because of the expansion of vertical depletion region. The proposed model presents a more adaptive trait in describing 2-D coupling effect under various device structure parameters when compared to the conventional EDC model. Furthermore, a corresponding structure optimization criterion is provided to further improve the tradeoff between breakdown voltage, On-resistance and costs. The results obtained by the proposed model are found to be accurate comparing with TCAD simulation results.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • An Optimized 4H-SiC Trench MOS Barrier Schottky (TMBS) Rectifier

    • Authors: Ying Wang;Wen-Ju Wang;Cheng-Hao Yu;Yi-Fei Huang;You-Lei Sun;Jian-Xiang Tang;
      Pages: 1154 - 1158
      Abstract: This paper proposes an optimal 4H-silicon carbide trench MOS barrier Schottky (TMBS) Rectifier. The optimal structure of this rectifier is achieved by adding an Nwrapping region at the P+ shielding of the conventional TMBS structure, which significantly reduces the depletion region formed by the P+ shielding region. As a result, the proposed structure provides a lower ON-resistance comparing with the conventional P+ shielding structure. Moreover, we study the electric characteristics of the proposed structure via numerical simulation. Such a structure improves the specific ON-resistance and figure of merit of the conventional P+ shielding TMBS by 32.2% and 48.4%, respectively, and offers a high breakdown voltage, i.e., up to 1908 V.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • CVD Growth Technologies of Layered MX2 Materials for Real LSI
           Applications—Position and Growth Direction Control and Gas Source

    • Authors: T. Irisawa;N. Okada;W. Mizubayashi;T. Mori;W.-H. Chang;K. Koga;A. Ando;K. Endo;S. Sasaki;T. Endo;Y. Miyata;
      Pages: 1159 - 1163
      Abstract: Position and growth direction control in chemical vapor deposition (CVD) of WS2 and SnS2 by using patterned Si/SiO2 substrates has been demonstrated. It was found that step edges effectively worked as crystal nuclei and lateral crystal growth from the edges with a certain level of growth directionality was observed. Gas source CVD using industrially friendly precursors (WF6, SnCl4, and H2S) has also been developed and WS2 and SnS2 synthesis with wafer-scale uniformity have been obtained.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • A Computationally Efficient Compact Model for Trap-Assisted Carrier
           Transport Through Multi-Stack Gate Dielectrics of HKMG nMOS Transistors

    • Authors: Apoorva Ojha;Nihar R. Mohapatra;
      Pages: 1164 - 1172
      Abstract: This paper analyzes in detail the carrier transport through the multi-stack gate dielectrics of high-K metal gate (HKMG) nMOS transistors under different gate biases and temperatures. The existing uncertainty about the carrier transport mechanisms for different gate biases is resolved through accurate band diagram analysis and gate current measurement under different conditions. The trap assisted tunneling (elastic and inelastic) and Poole-Frenkel conduction are identified as the two dominant mechanisms of carrier transport. These two mechanisms are found to be prevalent in different gate bias ranges and have distinct signatures. A computationally efficient compact model for the gate current in HKMG nMOS transistors is developed capturing the simultaneity of both the carrier transport mechanisms. The proposed model is valid for all gate voltages (accumulation to inversion) and for different temperatures. The accuracy of the proposed model is confirmed by comparing it with the experimental data.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Suppressing Oxidation-Enhanced Diffusion of Boron in Silicon With
           Oxygen-Inserted Layers

    • Authors: Daniel Connelly;Richard Burton;Nyles W. Cody;Pavel Fastenko;Marek Hytha;Robert Stephenson;Hideki Takeuchi;Keith Doran Weeks;Robert Mears;
      Pages: 1173 - 1178
      Abstract: Oxygen-Inserted (OI) layers are shown to shield a buried boron profile from oxidation enhanced diffusion. A TCAD model for the OI layer, including point defect and dopant trapping, as implemented in Sentaurus Process is shown to match experimental results, demonstrating the retention of steeper boron profiles after oxidation. Incorporation of the oxygen insertion layers into a CMOS process increases on-current and reduces threshold variability and mismatch.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • ${V}_{text{BR}}^{text{2}}$+ /+${R}_{text{ON}}$+ )+AlGaN/GaN+Power+HEMT+With+Periodically+C-Doped+GaN+Buffer+and+AlGaN+Back+Barrier&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Jun-Hyeok&;Jeong-Min+Ju;Gökhan+Atmaca;Jeong-Gil+Kim;Seung-Hyeon+Kang;Yong+Soo+Lee;Sang-Heung+Lee;Jong-Won+Lim;Ho-Sang+Kwon;Sefer+Bora+Lişesivdin;Jung-Hee+Lee;">High Figure-of-Merit ( ${V}_{text{BR}}^{text{2}}$ / ${R}_{text{ON}}$ )
           AlGaN/GaN Power HEMT With Periodically C-Doped GaN Buffer and AlGaN Back

    • Authors: Jun-Hyeok Lee;Jeong-Min Ju;Gökhan Atmaca;Jeong-Gil Kim;Seung-Hyeon Kang;Yong Soo Lee;Sang-Heung Lee;Jong-Won Lim;Ho-Sang Kwon;Sefer Bora Lişesivdin;Jung-Hee Lee;
      Pages: 1179 - 1186
      Abstract: In this paper, we investigated characteristics of AlGaN/GaN high-electron mobility transistors (HEMTs) with high resistive buffer structure consisted of periodically carbon-doped (PCD) GaN buffer layer and AlGaN back barrier layer. The PCD structure was proposed for reducing undesirable trapping effects, which resulted in effective suppression of the current collapse compared to that in conventional carbon buffer structure. To further improve the dynamic performances of the device and to increase the electron confinement of the 2-D electron gas (2-DEG) channel, AlGaN back barrier was inserted between the GaN channel and the PCD buffer layer, which results in greatly improved current collapse with slightly improved 2-DEG mobility compared to those of the device without back barrier. The OFF-state leakage current of the device with back-barrier is about 2 orders lower in magnitude than that of device without back barrier, which leads to the breakdown voltage of 2 kV and figure of merit of 2.27 GV2Ω-1cm-2 for the device with LGD of 10 μm, one of the highest values ever reported for the GaN-based HEMTs.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate

    • Authors: Yu-Ru Lin;Yi-Yun Yang;Yu-Hsien Lin;Erry Dwi Kurniawan;Mu-Shih Yeh;Lun-Chun Chen;Yung-Chun Wu;
      Pages: 1187 - 1191
      Abstract: This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures. The stacked nanosheets device structure, fabrication, and electrical characteristics are analyzed. The SNS-GAATFT reveals better performance to multi-gate SNS-TFT. The proposed inversion mode SNS-TFT has properties of the easy process with low cost and compatible with all 3-D Si CMOS and AMOLED applications. Moreover, the SNS-GAATFT is suitable for future monolithic 3-D IC for 2015's ITRS technology roadmap for the year 2024-2030.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Analysis of Read Margin and Write Power Consumption of a 3-D Vertical RRAM
           (VRRAM) Crossbar Array

    • Authors: Sujin Choi;Wookyung Sun;Hyungsoon Shin;
      Pages: 1192 - 1196
      Abstract: In this paper, the read margin (RM) and write power (WP) for various 3-D vertical resistive random-access memory (VRRAM) architectures and bias schemes are analyzed. The optimized bias scheme for each of the read and write operations is demonstrated using HSPICE simulation. The ground and 1/3 bias schemes are desirable for reading a row of cells and a single cell, respectively, whereas the 1/2 bias scheme is more suitable for the write operation. The RM is strongly influenced by the number of word line (WL) layers, which determines the number of half-selected cells. The WP is predominantly affected by the in-plane array size rather than the number of WL layers, as the majority of the power is consumed in the selected WL. Only slight differences between the WL plane and WL even/odd structures are observed in the RM and WP. Therefore, due to the same performance and a double cell bit, a WL even/odd structure is more promising than a WL plane structure for the VRRAM architecture.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Guest Editorial Special Section on the Second Electron Devices Technology
           and Manufacturing (EDTM) Conference 2018

    • Authors: Kazunari Ishimaru;Naoto Horiguchi;Kazuo Nojiri;Paul Lining Zhang;Paul R. Berger;
      Pages: 1197 - 1199
      Abstract: Performance improvement by simple device scaling is running out of steam. Design and Technology Co-Optimization (DTCO) and System and Technology Co-Optimization (STCO) are the hot topics to overcome scaling issues by collaboration among device, circuit, and system communities. Another approach is seeking device innovation from manufacturing side with material and process communities.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Gettering Sinks for Metallic Impurities Formed by Carbon-Cluster Ion
           Implantation in Epitaxial Silicon Wafers for CMOS Image Sensor

    • Authors: Ayumi Onaka-Masada;Ryosuke Okuyama;Satoshi Shigematsu;Hidehiko Okuda;Takeshi Kadono;Ryo Hirose;Yoshihiro Koga;Koji Sueoka;Kazunari Kurita;
      Pages: 1200 - 1206
      Abstract: Gettering sinks for metallic impurities formed by carbon-cluster ion implantation in epitaxial silicon wafers have been investigated using technology computer-aided design and atom probe tomography (APT). We found that the defects formed by carbon-cluster ion implantation consist of carbon and interstitial silicon clusters (carbon-interstitial clusters). Vacancy-type clusters are not dominant gettering sinks for metallic impurities in the carbon-cluster ion implanted region. APT data indicated that the distribution of oxygen atoms in the defects differs between Czochralski-grown silicon and epitaxial silicon wafers. The high gettering efficiency observed in carbon-cluster ion implanted epitaxial silicon wafers in comparison with Czochralski-grown silicon wafers is due to the distribution of oxygen atoms in the defects. Defects not containing O atoms provide strong gettering sinks for metallic impurities. These defects are formed by only carbon-interstitial clusters. Oxygen atoms inside the defects modify the amount of carbon-interstitial cluster formation on the defects. It is suggested that the gettering efficiency for metallic impurities in carbon-cluster ion implanted epitaxial silicon wafer is determined by the amount of carbon-interstitial clusters.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Rigidity Enhancement of GeO2 by Y-Doping for Reliable Ge Gate

    • Authors: Tomonori Nishimura;Xiaoyu Tang;Cimang Lu;Takeaki Yajima;Akira Toriumi;
      Pages: 1207 - 1212
      Abstract: The poor reliability of the GeO2/Ge stack is improved by appropriate cation doping [e.g., Yttrium (Y)-doping] into amorphous GeO2 as a result of the enhancement of the GeO2 network structure stability. In this paper, we discuss the impact of Y-doping on structural modulation of GeO2 on a Ge substrate in thermal treatment. By doping a small amount of Y into amorphous GeO2, the crystallization of GeO2 to $alpha $ -quartz and $alpha $ -cristobalite structures is efficiently suppressed without toughening the local Ge-O bond. This is direct evidence of rigidity enhancement of the GeO2 tetrahedral network structure by cation doping.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • P-Channel and N-Channel Super-Steep Subthreshold Slope PN-Body Tied
           SOI-FET for Ultralow Power CMOS

    • Authors: Takayuki Mori;Jiro Ida;
      Pages: 1213 - 1219
      Abstract: In this paper, n-channel and p-channel super-steep subthreshold slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS (< 1 mV/dec) characteristics while maintaining low off current (< 1 pA/ $mu$ m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Electrode Material Dependence of Resistance Change Behavior in Ta2O5
           Resistive Analog Neuromorphic Device

    • Authors: Hisashi Shima;Makoto Takahashi;Yasuhisa Naitoh;Hiroyuki Akinaga;
      Pages: 1220 - 1226
      Abstract: In a human brain, our closest and very low-power information processor, one neuron transmits electrical signals depending on the electrical stimulation from other neurons. Therefore, it can be regarded as the multi-input one-output system that is the same as an elementary perceptron in the pattern recognition system. In analogy with the actual neurons whose coupling strength varies on a moment-to-moment basis, a flexible control of the weight for each individual input signal is required in order to realize the correct recognition. The analog change of the resistance values observed in the resistance change device is quite suitable for such application. In this contribution, we successfully demonstrate the high-speed analog resistance change in the TiN/TaOx/Ta2O5/TiN resistive analog neuromorphic device (RAND). An introduction of the TiN electrode smoothed the discontinuity in both the resistance switching processes by dc and pulse voltages. On the other hands, digital resistance switching was dominant in TiN/TaOx/Ta2O5/Pt device. We deduce that the electrodes reactivity with oxygen and the interface resistance play a key role for the analog resistance switching. The analog resistance change speed of 200 ns is much faster than the signal transmission speed between neurons and is thought to increase the number of operations per unit energy consumption. By introducing present RAND, the human-brain inspired information processor is expected to become energetically more efficient.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using
           In-Situ ALD Digital O3 Treatment

    • Authors: M.-S. Yeh;G.-L. Luo;F.-J. Hou;P.-J. Sung;C. J. Wang;C.-J. Su;C.-T. WU;Y.-C. Huang;T.-C. Hong;B.-Y. Chen;K.-M. Chen;Y.-C. WU;M. Izawa;M. Miura;M. Morimoto;H. Ishimura;Y.-J. Lee;W.-F. Wu;W.-K. Yeh;
      Pages: 1227 - 1232
      Abstract: Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the $text{I}_{mathrm{ ON}}/text{I}_{mathrm{ OFF}}$ ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low ${V}_{D}= 0.6$ V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Ultra-High-Efficiency Writing in Voltage-Control Spintronics Memory
           (VoCSM): The Most Promising Embedded Memory for Deep Learning

    • Authors: Y. Ohsawa;H. Yoda;N. Shimomura;S. Shirotori;S. Fujita;K. Koi;A. Buyandalai;S. Oikawa;M. Shimizu;Y. Kato;T. Inokuchi;H. Sugiyama;M. Ishikawa;K. Ikegami;S. Takaya;A. Kurobe;
      Pages: 1233 - 1238
      Abstract: Our new proposal of voltage-control spintronics memory (VoCSM) in which spin-orbit torque in conjunction with the voltage-control-magnetic-anisotropy effect works as the writing principle showed small switching current of $37~mu text{A}$ for about 350 $K_{B}T$ switching energy. This indicates VoCSM’s writing efficiency is so high that VoCSM would be applicable for deep learning memories requiring ultra-low power consumption.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked
           6T-SRAM Layout

    • Authors: Eisuke Anju;Iriya Muneta;Kuniyuki Kakushima;Kazuo Tsutsui;Hitoshi Wakabayashi;
      Pages: 1239 - 1245
      Abstract: In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure. This is attributed to an increase in heat dissipation mainly from heat source to bulk wafer. Moreover, we proposed the p/n-stacked nanowire on bulk FinFET and its 6T-SRAM layout. Area of the proposed SRAM was reduced approximately 15%, as compared to the conventional cell layout.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • ${n}$+ MISFETs+With+Top-Gate+and+Al2O3+Passivation+Under+Low+Thermal+Budget+for+Large+Area+Integration&rft.title=IEEE+Journal+of+the+Electron+Devices+Society&rft.issn=2168-6734&;&rft.aufirst=Kentaro&;Jun’Ichi+Shimizu;Mayato+Toyama;Takumi+Ohashi;Iriya+Muneta;Seiya+Ishihara;Kuniyuki+Kakushima;Kazuo+Tsutsui;Atsushi+Ogura;Hitoshi+Wakabayashi;">Sputter-Deposited-MoS2 ${n}$ MISFETs With Top-Gate and Al2O3 Passivation
           Under Low Thermal Budget for Large Area Integration

    • Authors: Kentaro Matsuura;Jun’Ichi Shimizu;Mayato Toyama;Takumi Ohashi;Iriya Muneta;Seiya Ishihara;Kuniyuki Kakushima;Kazuo Tsutsui;Atsushi Ogura;Hitoshi Wakabayashi;
      Pages: 1246 - 1252
      Abstract: We have fabricated large area integrated top-gate ${n}$ MISFETs with sputter-deposited-MoS2 film having n-type operation. A sputtering method enables us to form a large-area MoS2 thin film followed by H2S annealing to compensate sulfur vacancies. Two passivation films of ALD-Al2O3 enhance the process endurance of MoS2 channel. Therefore, we demonstrate TiN-top-gate ${n}$ MISFET, which is a substantial first step to realize industrial chip-level LSIs with MoS2-channel FETs.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • Origin of High Mobility in InSnZnO MOSFETs

    • Authors: Nobuyoshi Saito;Tomomasa Ueda;Tsutomu Tezuka;Keiji Ikeda;
      Pages: 1253 - 1257
      Abstract: The origins of higher mobility characteristics of In-Sn-Zn-O (InSnZnO) MOSFETs than those of conventional In-Ga-Zn-O (InGaZnO) MOSFETs were investigated. Comprehensive analyses of temperature and surface carrier concentration ( ${N} _{s}$ ) dependence of mobility revealed the aspects of potential profile around mobility edge ( ${E} _{c}$ ) in InSnZnO MOSFET. Incorporated Sn atoms were found to increase the potential fluctuation around ${E} _{c}$ at low ${N} _{s}$ compared to conventional InGaZnO MOSFET, but enhance the overlapping of electron orbitals of cations with In atoms, which results in mobility improvement by band transport.
      PubDate: 2018
      Issue No: Vol. 6 (2018)
  • 2018 IndexIEEE Journal of the Electron Devices SocietyVol. 6

    • Pages: 1258 - 1293
      Abstract: Presents the 2018 subject/author index for this publication.
      PubDate: Dec. 2018
      Issue No: Vol. 6 (2018)
School of Mathematical and Computer Sciences
Heriot-Watt University
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