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  Subjects -> ELECTRONICS (Total: 179 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 78)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 315)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 269)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 105)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 92)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 191)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 66)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 71)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 24)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access  
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 168)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [119 journals]
  • A High Precision Output Impedance Calibration Technique for SST
    • Authors: Xu Bai, Jianzhong Zhao, Yumei Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a high precision output impedance calibration technique for source-series terminated (SST) transmitter. Unlike the conventional impedance calibration technique using a digital method, the proposed impedance calibration employs the analog method to implement the impedance calibration. Therefore, there is no trade-off between area overhead and precision of calibration. The proposed analog impedance calibration circuit has three analog impedance control loops, namely, pull-up loop, pull-down loop and shunt-loop. Each loop is composed of a high gain amplifier and a slice-based unit. To reduce the hardware, the shunt loop utilized a slice unit replication design to achieve the shunt-slice calibration. These loops send output voltage to the SST transmitter when they reached stability. Fabricated in 55[math]nm CMOS technology, the power consumption of the calibration circuit is 1.35[math]mW and the total area is 61[math][math]m*83.1[math][math]m, which consumes 6.3% of the total power consumed by the transmitter and occupies 25% of the total area occupied by the complete transmitter. The post-layout simulation result shows that the maximum impedance calibration error of the three loops is less than 0.02%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-11T08:17:37Z
      DOI: 10.1142/S0218126620500255
  • Normally Bypassed Cascaded Sources Multilevel Inverter with RGA
           Optimization for Reduced Output Distortion and Formulaic Passive Filter
    • Authors: G. Chitrakala, N. Stalin, V. Mohan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-11T08:17:37Z
      DOI: 10.1142/S021812662050019X
  • Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications
    • Authors: Imen GHORBEL, Fayrouz Haddad, Wenceslas Rahajandraibe, Mourad Loulou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[math][math]m CMOS process. Measurements present an ultra-low power consumption of only 262[math][math]W drawn from 1[math]V supply voltage. The measured frequency tuning range is about 10% between 2.179[math]GHz and 2.409[math]GHz. The post-layout simulation presents a phase noise (PN) of [math][math]dBc/Hz, while the measured PN is [math][math]dBc/Hz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:53Z
      DOI: 10.1142/S0218126619501226
  • Operation, Control and Verification of Seven-Level Quasi-Z-Source-Based
           [math]-Type Inverter
    • Authors: Ramesh Rahul Jammy, Kirubakaran Annamalai, Chinmay Kumar Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel seven-level Quasi-Z-Source-based [math]-type inverter (7L[math]qZST[math]) is proposed. The proposed inverter is an upgrade of Quasi-Z-source (qZs) network and seven-level [math]-type inverter. The 7L qZST[math] comprises of three qZs-based impedance networks, two bidirectional switches and an [math]-bridge inverter. It owns the advantages of reduced switch count, improved output voltage gain, enhanced reliability and better quality of output voltage and current. The performance of the proposed topology is tested for two different pulse width modulation techniques based on shoot-through control. The first technique offers simple control and operated at a fixed shoot-through duty cycle for realizing output voltage level. The second technique facilitates independent control of each qZs network dc-link voltage and they can be operated at different shoot through duty cycle which overcomes the limitation of first technique with better quality in output voltage. The detailed operation of the proposed topology and control schemes have been elaborated for different switching states for each output voltage level generation. Extensive simulation and experimentation are performed for both the switching schemes to verify their performance under steady state and dynamic conditions. Furthermore, a brief comparison is constructed to highlight the merits of the proposed inverter with conventional topologies.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:52Z
      DOI: 10.1142/S0218126620500231
  • Evolved Fuzzy NN Control for Discrete-Time Nonlinear Systems
    • Authors: Tim Chen, A. Babanin, Assim Muhammad, B. Chapron, C. Y. J. Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To guarantee the asymptotic stability of discrete-time nonlinear systems, this paper proposes an Evolved Bat Algorithm (EBA) fuzzy neural network (NN) controller. In the evolved fuzzy NN modeling, an NN model and linear differential inclusion (LDI) representation are established for arbitrary nonlinear dynamics. This representation is constructed by the use of sector nonlinearity to convert a nonlinear model to the multiple rule base of the linear model, and a new sufficiency condition to guarantee asymptotic stability in the Lyapunov function is implemented in terms of linear matrix inequalities. The proposed method is an enhancement of existing methods which produces good results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:48Z
      DOI: 10.1142/S0218126620500152
  • A Low-Power Clock Generator with a Wide Frequency Tuning Range and Low
           Temperature Variation: Analysis and Design
    • Authors: Ziba Fazel, MaryamSadat Shokrekhodaei, Mojtaba Atarodi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180[math]nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about [math][math]dBc/Hz at 10[math]MHz offset frequency. Frequency changes less than [math] in the temperature range of [math]C–[math]C. The clock generator consumes 0.657[math]mW of power. Results show improvement in comparison to the previous works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:49Z
      DOI: 10.1142/S0218126620500127
  • Distributed Coordinated Attitude Regulation Control for Multiple
           Spacecraft with Time-varying Uncertainties
    • Authors: Zhihao Zhu, Yu Guo, Zhi Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      For multiple spacecrafts under the communication topology containing a spanning tree with the leader as the root, we investigate a distributed coordinated attitude regulation control problem of the spacecraft with unknown time-varying uncertainties and state-dependent disturbances. Aiming at solving the practical problem that the information of the leader may be only available to a subset of the followers, a novel class of distributed finite-time leaders’ state observer for each follower is proposed. Meanwhile, a new self-adjustment matrix is designed to reduce the overshoot of the system. In addition, an adaptive compensation term is designed to reject the impact of the time-varying inertia uncertainties and external state-dependent and state-independent disturbances. On the basis of the distributed finite-time observer, the self-adjustment matrix and the adaptive law, two distributed coordinated attitude regulation control laws are designed. With the first controller, the coordinated attitude regulation system is stable asymptotically, and with the second controller, the system is bounded stable. Both distributed coordinated attitude regulation controllers can guarantee that the follower spacecraft can track a common time-varying trajectory of the leader. Numerical simulation examples validate the effectiveness of the proposed controllers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:46Z
      DOI: 10.1142/S0218126620500188
  • A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR
           Filter Implementation Using Hardware–Software Co-Design
    • Authors: C. Ranjith, S. P. Joy Vasantha Rani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:44Z
      DOI: 10.1142/S0218126620500140
  • Prediction of Pareto Dominance Using an Attribute Tendency Model for
           Expensive Multi-Objective Optimization
    • Authors: Wenbin li, Junqiang Jiang, Xi Chen, Guanqi Guo, Jianjun He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a novel surrogate-assisted multi-objective evolutionary algorithm, MOEA-ATCM, to solve expensive or black-box multi-objective problems with small evaluation budgets. The proposed approach encompasses a state-of-the-art MOEA based on a nondominated sorting genetic algorithm assisted by multi-fidelity optimization methods. A high-fidelity attribute tendency (AT) surrogate model was used to construct a linear decision space by introducing the knowledge of the objective space. A coarse model (CM) based on the AT model and correlation analyses of the objective functions and decision attributes were used to predict the Pareto dominance for candidates in the new decision space constructed by the AT model. Two major roles of MOEA-ATCM were identified: (1) the development of a new multi-fidelity surrogate-model-based method to predict Pareto dominance in a decision space that was then applied to MOEA, which does not need to dynamically update surrogate models in the optimization process and (2) the development of a Pareto dominance prediction method to obtain good nondominated solutions of expensive or black box problems with relatively few objective function evaluations. The advantages of MOEA-ATCM were verified by mathematical benchmark problems and a real-world multi-objective parameter optimization problem.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:36Z
      DOI: 10.1142/S0218126620500218
  • Research on the Linear Acceleration Sensor Signal Acquisition Technology
           Based on the High-Order Anti-Aliasing Cauer Filter
    • Authors: Zhuo Hou, Sanmin Shen, Yong Ye, Jiahao Deng, Yuting Liu, Qing Meng, Zuodong Duan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A linear acceleration sensor integrated into an inertial measurement unit and its signal processing technology are presented in this paper. Based on the characteristics of the acceleration sensor, before analog-to-digital conversion, a design method for optimizing and conditioning the output signal in levels of frequency with the high-order anti-aliasing Cauer filter is proposed. Compared with the previously published papers, here we not only focus on the anti-aliasing filtering effect under a single channel, but also pay more attention to the anti-aliasing filtering effect with more data to the same type of channels with the same cut-off frequency and different types of channels with different cut-off frequencies. Similar to other kinds of filters, this paper points out that the high-order anti-aliasing Cauer filter also has its inherent delay characteristic. And this paper also reveals the qualitative relationship between frequency and time delay in different testing environments by using various delay test data. Compared with the previously published papers, through the simple solution processing with the true attitude data, this paper further estimates the error of simple attitude signal processing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-26T02:58:31Z
      DOI: 10.1142/S0218126620500085
  • Divide and Compact — Stochastic Space Compaction for
           Faster-than-at-Speed Test
    • Authors: Alexander Sprenger, Sybille Hellebrand
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([math]-values). These [math]-values impede the test response compaction. In addition, the number and distribution of the [math]-values vary with the clock frequency, and thus a very flexible [math]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [math]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [math]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [math]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [math]-reduction and fault efficiency can be adapted to user-defined goals.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-18T03:38:53Z
      DOI: 10.1142/S0218126619400012
  • Analysis, Control and FPGA Implementation of a Fractional-Order Modified
           Shinriki Circuit
    • Authors: Karthikeyan Rajagopal, Fahimeh Nazarimehr, Laarem Guessas, Anitha Karthikeyan, Ashokkumar Srinivasan, Sajad Jafari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we introduce a novel integer-order memristor-modified Shinriki circuit (MMSC). We investigate the dynamic properties of the MMSC system and the existence of chaos is proved with positive largest Lyapunov exponent. Bifurcation plots are derived to analyze the parameter dependence of the MMSC system. The fractional-order model of the MMSC system (FOMMSC) is derived and the bifurcation analysis of the FOMMSC system with the fractional orders is carried out. Fractional-order adaptive sliding-mode controllers (FOASMCs) and genetically optimized PID controllers are designed to synchronize identical FOMMSC systems with unknown parameters. Numerical simulations are conducted to validate the theoretical results. FPGA implementation of the FOASMC controllers is presented to show that the proposed control algorithm is hardware realizable. MMSC has trigonometric functions which make the system more complex and the optimization and synchronization of such systems in the integer order itself are harder, so the paper does the same in fractional order. The proposed system is a memristive circuit which can show special features such as multistability, hyperchaos, and multiscroll attractor. Such a system with these features is very rare in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-15T01:31:23Z
      DOI: 10.1142/S0218126619502323
  • A Physics-Based Analytical Model for MgZnO/ZnO HEMT
    • Authors: Yogesh Kumar Verma, Varun Mishra, Santosh Kumar Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a physics-based compact model is developed for novel MgZnO/ZnO high-electron-mobility transistor (HEMT). Poisson’s equation coupled with 1D Schrödinger equation is solved self-consistently in the triangular quantum well to derive an expression of two-dimensional electron gas (2DEG) density with respect to gate voltage at the heterointerface of barrier (MgZnO) and buffer (ZnO) layers. A compact mathematical framework has been devised further for the first time for ZnO-based HEMT to the best of our knowledge using the expression of 2DEG density to compute surface potential, gate charge, gate current, gate capacitance, current–voltage characteristics, output conductance, transconductance and cut-off frequency with respect to gate voltage and along with the drain–source output resistance [math].
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-15T01:31:22Z
      DOI: 10.1142/S0218126620500097
  • Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC
           Converter for Implantable Devices
    • Authors: Najmeh Cheraghi Shirazi, Abumoslem Jannesari, Pooya Torkzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[math]mV and 20[math]MHz clock frequency for 1[math]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[math]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[math][math]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[math]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [math][math][math]m for TBCCCP, [math][math][math]m for ITBCCCP2 and [math][math][math]m for ITBCCCP4.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-13T06:31:07Z
      DOI: 10.1142/S0218126620500139
  • Analysis, Design and Control of an Integrated Three-Level Buck Converter
           under DCM Operation
    • Authors: Wen-Ming Zheng, Wen-Liang Zeng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A three-level buck (TLB) converter has the characteristics of higher voltage conversion efficiency, lower inductor current ripples, output voltage ripples and voltage stresses on switches when compared with the buck converters in continuous conduction mode (CCM). With a TLB converter integrated on a chip, we cannot avoid its discontinuous conduction mode (DCM) operation due to a smaller inductance and load variation. In this paper, we’ll present and discuss the analysis, design and control of a TLB converter under DCM operation, implemented in a 65[math]nm CMOS process. Transistor level simulation results show that when the TLB converter operates at 100[math]MHz with a 5[math]nH on-chip inductor, a 10[math]nF output capacitor and a 10[math]nF flying capacitor, it can achieve an output conversion range of 0.7–1.2[math]V from a 2.4[math]V input supply, with a peak efficiency of 81.5%@120[math]mW. The output load transient response is 100[math]mV with 101[math]ns for undershoot, and 86[math]mV with 110[math]ns for overshoot when [math]–100[math]mA. The maximum output voltage ripple is less than 19[math]mV.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-13T06:31:06Z
      DOI: 10.1142/S0218126620500115
  • Deep Convolutional Neural Network with Optical Flow for Facial
           Micro-Expression Recognition
    • Authors: Qiuyu Li, Jun Yu, Toru Kurihara, Haiyan Zhang, Shu Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Micro-expression is a kind of brief facial movements which could not be controlled by the nervous system. Micro-expression indicates that a person is hiding his true emotion consciously. Micro-expression recognition has various potential applications in public security and clinical medicine. Researches are focused on the automatic micro-expression recognition, because it is hard to recognize the micro-expression by people themselves. This research proposed a novel algorithm for automatic micro-expression recognition which combined a deep multi-task convolutional network for detecting the facial landmarks and a fused deep convolutional network for estimating the optical flow features of the micro-expression. First, the deep multi-task convolutional network is employed to detect facial landmarks with the manifold-related tasks for dividing the facial region. Furthermore, a fused convolutional network is applied for extracting the optical flow features from the facial regions which contain the muscle changes when the micro-expression appears. Because each video clip has many frames, the original optical flow features of the whole video clip will have high number of dimensions and redundant information. This research revises the optical flow features for reducing the redundant dimensions. Finally, a revised optical flow feature is applied for refining the information of the features and a support vector machine classifier is adopted for recognizing the micro-expression. The main contribution of work is combining the deep multi-task learning neural network and the fusion optical flow network for micro-expression recognition and revising the optical flow features for reducing the redundant dimensions. The results of experiments on two spontaneous micro-expression databases prove that our method achieved competitive performance in micro-expression recognition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:22Z
      DOI: 10.1142/S0218126620500061
  • Third-Kind Chebyshev Wavelet Method for the Solution of Fractional Order
           Riccati Differential Equations
    • Authors: Sadiye Nergis Tural-Polat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we derive the numerical solutions of the various fractional-order Riccati type differential equations using the third-kind Chebyshev wavelet operational matrix of fractional order integration (C3WOMFI) method. The operational matrix of fractional order integration method converts the fractional differential equations to a system of algebraic equations. The third-kind Chebyshev wavelet method provides sparse coefficient matrices, therefore the computational load involved for this method is not as severe and also the resulting method is faster. The numerical solutions agree with the exact solutions for non-fractional orders, and also the solutions for the fractional orders approach those of the integer orders as the fractional order coefficient [math] approaches to 1.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:21Z
      DOI: 10.1142/S0218126619502475
  • A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic
           Asynchronous Pipeline Design
    • Authors: Mansi Jhamb, Vinod Kumar Khera, Piyush Pant, Hinduja Pudi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:21Z
      DOI: 10.1142/S0218126619502347
  • An Efficient Load Forecasting in Predictive Control Strategy Using Hybrid
           Neural Network
    • Authors: Shweta Sengar, Xiaodong Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Load forecasting is a difficult task, because the load series is complex and exhibits several levels of seasonality. The load at a given hour is dependent not only on the load at the previous day, but also on the load at the same hour on the previous day and previous week, and because there are many important exogenous variables that must be considered. Most of the researches were simultaneously concentrated on the number of input variables to be considered for the load forecasting problem. In this paper, we concentrate on optimizing the load demand using forecasting of the weather conditions, water consumption, and electrical load. Here, the neural network (NN) power load forecasting model clubbed with Levy-flight from cuckoo search algorithm is proposed, i.e., called hybrid neural network (HNN), and named as LF-HNN, where the Levy-flight is used to automatically select the appropriate spread parameter value for the NN power load forecasting model. The results from the simulation work have demonstrated the value of the LF-HNN approach successfully selected the appropriate operating mode to achieve optimization of the overall energy efficiency of the system using all available energy resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:20Z
      DOI: 10.1142/S0218126620500103
  • A 21-Level Bipolar Single-Phase Modular Multilevel Inverter
    • Authors: Sidharth Sabyasachi, Vijay B. Borghate, Santosh Kumar Maddugari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a module for single-phase multilevel inverter topology. The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge. This results in reduction in filter cost and size. The module can be cascaded for high voltage applications. The same arrangement of voltage source magnitudes in first module is maintained in the remaining cascaded modules. The proposed topology is suitable for the applications like electric vehicle and emergency services like residences and hospitality industries, etc. A set of comparisons between the proposed and recently published topologies are provided to differentiate between them. The topology is simulated and verified in MATLAB/SIMULINK. A hardware prototype is developed in the laboratory for experimental confirmation with various conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:20Z
      DOI: 10.1142/S0218126620500048
  • New Hardware Architecture for Self-Organizing Map Used for Color Vector
    • Authors: Khaled Ben Khalifa, Ahmed Ghazi Blaiech, Mehdi Abadi, Mohamed Hedi Bedoui
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [math] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:19Z
      DOI: 10.1142/S0218126620500024
  • An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future
           3D Chip-Multiprocessors
    • Authors: Arghavan Asad, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy, Farah Mohammadi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:19Z
      DOI: 10.1142/S0218126619502244
  • Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate
           the Reconfiguration Overheads in Reconfigurable Systems
    • Authors: I. Hariharan, M. Kannan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:18Z
      DOI: 10.1142/S0218126619502463
  • A Lion’s Pride Inspired Algorithm for VLSI Floorplanning
    • Authors: Lalin L Laudis, N Ramadass
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:17Z
      DOI: 10.1142/S0218126620500036
  • A Memetic Algorithm-Based Design Space Exploration for Datapath Resource
           Allocation During High-Level Synthesis
    • Authors: Shathanaa Rajmohan, N. Ramasubramanian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      System designers have started adopting high-level synthesis (HLS) for architectural design because of the higher levels of abstraction offered. The HLS tools provide multiple design choices with tradeoff among different design parameters. Design Space Exploration (DSE) involves optimizing the synthesis options to achieve best tradeoffs among the metrics of interest. With the aim of exploring the design space in a feasible amount of time, we present a novel automated DSE approach. In particular, meeting the constraints presented by different parameters of interest is modeled as a multi-objective problem and solved using Memetic algorithm. The effectiveness of different variations of the Memetic algorithm in solving the DSE problem is studied and a Firefly algorithm-based solution is proposed with a novel probabilistic local search mechanism. The proposed approach is compared with existing solutions and the results prove that the proposed approach outperforms both existing solutions and other variations of Memetic algorithms in terms of convergence time and quality of results. In addition to that, a case study has been included to demonstrate the applicability of the approach. Results show that the proposed approach achieves a 33% improvement in cost, [math] improvement in speed and [math] improvement in hypervolume.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:17Z
      DOI: 10.1142/S0218126620500012
  • A New CPFSK Demodulation Approach for Software Defined Radio
    • Authors: Kayol Soares Mayer, Candice Müller, Fernando Cesar Comparsi de Castro, Maria Cristina Felippetto de Castro
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [math], which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes [math], [math] and [math], respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T07:33:56Z
      DOI: 10.1142/S0218126619502438
  • RDMKE: Applying Reuse Distance Analysis to Multiple GPU Kernel Executions
    • Authors: Mohsen Kiani, Amir Rajabzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern GPUs can execute multiple kernels concurrently to keep the hardware resources busy and to boost the overall performance. This approach is called simultaneous multiple kernel execution (MKE). MKE is a promising approach for improving GPU hardware utilization. Although modern GPUs allow MKE, the effects of different MKE scenarios have not adequately studied by the researchers. Since cache memories have significant effects on the overall GPU performance, the effects of MKE on cache performance should be investigated properly. The present study proposes a framework, called RDMKE (short for Reuse Distance-based profiling in MKEs), to provide a method for analyzing GPU cache memory performance in MKE scenarios. The raw memory access information of a kernel is first extracted and then RDMKE enforces a proper ordering to the memory accesses so that it represents a given MKE scenario. Afterward, RDMKE employs reuse distance analysis (RDA) to generate cache-related performance metrics, including hit ratios, transaction counts, cache sets and Miss Status Holding Register reservation fails. In addition, RDMKE provides the user with the RD profiles as a useful locality metric. The simulation results of single kernel executions show a fair correlation between the generated results by RDMKE and GPU performance counters. Further, the simulation results of 28 two-kernel executions indicate that RDMKE can properly capture the nonlinear cache behaviors in MKE scenarios.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-31T08:20:39Z
      DOI: 10.1142/S0218126619502451
  • Determination of Worst-Case Data Using an Adaptive Surrogate Model for
           Real-Time System
    • Authors: Muhammad Rashid, Syed Abdul Baqi Shah, Muhammad Arif, Muhammad Kashif
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The estimation of worst-case execution time (WCET) is a critical activity in the analysis of real-time systems. Evolutionary algorithms are frequently employed for the determination of worst-case data, used in the estimation of WCET. However, in order to employ an evolutionary algorithm, several executions of the application program are required, either on the target hardware or using its simulator. Multiple executions of the application program consume a huge amount of time. In order to reduce the huge execution time, this paper proposes the use of an adaptive surrogate model. The initial training of surrogate model is performed with a cycle-accurate simulator. The initially trained model is then used to assist the evolutionary algorithm by predicting the execution time of an application program. However, contrary to the direct training approach, the surrogate model in this paper is updated (adapted) during the evolution process. The adaptive training of a surrogate model increases its prediction accuracy and reduces the overall time. The validity of proposed methodology is illustrated with multiple sorting algorithms, extensively used in real-time systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:28Z
      DOI: 10.1142/S021812662050005X
  • 2.4 GHz Real-Time Prototyping Tool for OFDM Channel Estimation using USRP2
           and LabVIEW
    • Authors: Kerem Küçük
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless local area networks (WLANs) are currently playing an important role in serving the indoor traffic demand. Therefore, there is a need for software-defined radio platforms (SDRs) that can enable the solutions used in these systems to be tested in real environments as well as simulated results. In this paper, we present the SDR-based wireless receiver platform for determining the real-time WLANs performance and provide the comparison of the different channel estimation methods for IEEE 802.11g based on orthogonal frequency division multiplexing (OFDM) operations. The implementation of the receiver comprises the universal software radio peripheral and National Instruments LabVIEW. To determine the real-time receiver tool performance, we emphasized necessary signal processing techniques and different channel estimation methods with varying experimental parameters in real wireless environments. Experimental results report that the SDR-based receiver tool with the LabVIEW in real-time provides the throughput of the OFDM wireless network. The captured throughput performance concerning frame error rate by the receiver is also scrutinized with different channel estimation methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:26Z
      DOI: 10.1142/S0218126619502360
  • An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant
    • Authors: Ahmad Towhidy, Reza omidi, Karim Mohammadi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:21Z
      DOI: 10.1142/S021812661950244X
  • Analysis and FPGA Implementation of Zero-Forcing Receive Beamforming with
           Signal Space Diversity under Different Interleaving Techniques
    • Authors: Mustafa Anıl Reşat, Adem Çiçek, Serdar Özyurt, Enver Çavuş
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We combine multiple-input multiple-output zero-forcing receive beamforming (ZFRBF) with time and spatial component interleaved signal space diversity (SSD) and analyze the system’s error performance and implementation complexity. A transreceiver system with two transmit and [math] ([math]) receive antennas is considered where the number of simultaneous substreams equals two. The error performance of the proposed scheme with binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) modulations is studied. Under the time component interleaved SSD case, we derive an exact average bit error probability expression for BPSK and a tight approximation on the average symbol error probability for QPSK. The signal constellation rotation angles are accordingly computed. Using a similar approach, the signal constellation rotation angles are also determined for the scenario of spatial component interleaved SSD. It is demonstrated that the performance of the original ZFRBF model can be improved significantly by utilizing SSD especially with the time interleaving method. Another contribution to the literature is to study hardware complexity of the proposed scheme on FPGA. It is shown that while achieving considerable performance gain, SSD introduces only an insignificant increase to the system complexity without any extra bandwidth or time slot usage.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:20Z
      DOI: 10.1142/S0218126620500073
  • A Miniaturized High-Gain (MHG) Ultra-Wideband Unidirectional Monopole
           Antenna for UWB Applications
    • Authors: J. Vijayalakshmi, G. Murugesan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A miniaturized high-gain (MHG) ultra-wideband (UWB) unidirectional monopole antenna with defected ground structure (DGS) is designed for ultra-wideband applications. The MHG antenna is printed on the FR4 substrate material with an overall size of 26.6-mm [math] 29.3-mm [math] 1.6-mm, which operates over the UWB frequency range and achieves the bandwidth between 3.1[math]GHz and 10.6[math]GHz. This high-gain unidirectional antenna exhibits a peak gain of 7.20[math]dB with an efficiency of 95%. The compact antenna is a simple overlay design of circular and rectangular patches with the partial ground plane exhibiting high gain and better directivity. The overlay patch antenna acts as the radiator for wider bandwidth compared to the fundamental design of patch antenna and is matched to an SMA connector via 50[math][math] microstrip feed line. These simulated results are presented using HFSS software package. The designed antennas are fabricated and validated by using Agilent Vector Analyzer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-29T09:21:53Z
      DOI: 10.1142/S021812661950230X
  • Chaotic Oscillator Based on Fractional Order Memcapacitor
    • Authors: Akif Akgul
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Many literatures have discussed fractional order memristor and memcapacitor-based chaotic oscillators but the entire oscillator model is considered to be of fractional order. My interest is to propose a nonlinear oscillator with considering only the memcapacitor element of fractional order. Hence, I propose a fractional order memcapacitor (FMC)-based novel chaotic oscillator. The complete mathematical model for the proposed oscillator is derived and presented in this paper. The dimensionless state equations are then analyzed by using the equilibrium points and their stability, Eigen values, Kaplan–Yorke dimensions and Lyapunov exponents. To understand the complete dynamical behavior, bifurcation graphs are obtained and presented. Finally, the proposed fractional memcapacitor oscillator is implemented by using the shelf components.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:42Z
      DOI: 10.1142/S0218126619502396
  • AFBV: A High-Performance Network Flow Classification Method for
           Multi-Dimensional Fields and FPGA Implementation
    • Authors: Ling Zheng, Zhiliang Qiu, Weina Wang, Weitao Pan, Shiyong Sun, Ya Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[math]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:40Z
      DOI: 10.1142/S0218126619502372
  • Automatic Test Pattern Generation Through Boolean Satisfiability for
           Testing Bridging Faults
    • Authors: Hossein Mokhtarnia, Shahram Etemadi Borujeni, Mohammad Saeed Ehsani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:39Z
      DOI: 10.1142/S0218126619502402
  • Study and Design of Single and Double Layer Square Patch Antennas for UWB
    • Authors: Soufian Lakrit, Hassan Ammor, Soufiane Matah, Jaouad Terhzaz, Abdelouahd Tribak
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the design of Single and Double Layer microstrip patch antennas for ultra-wideband applications. This structure consists of a square patch with a partial ground plane, fed by a 50[math][math] microstrip line. This antenna is designed for a system to detect malignant tumors by microwave imaging. Prototypes of the two antennas are fabricated and tested with a network analyzer. The proposed antenna can achieve an ultra-wide bandwidth with VSWR[math]2 from 3.82[math]GHz to 11.72[math]GHz for single layer antenna and from 3.2[math]GHz to 10.95[math]GHz for double layer antenna, with stable and bi-directional radiation pattern. The gain is good and has a peak value of 6.5[math]dBi. The simulation of this antenna has been performed using Ansoft High Frequency Structure Simulator (HFSS) and Computer Simulation Technology-Microwave Studio (CST).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:38Z
      DOI: 10.1142/S0218126619502335
  • Distributed Amplifier Based on Monolayer Graphene Field Effect Transistor
    • Authors: Ali Safari, Massoud Dousti, Mohammad Bagher Tavakoli
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the ultra-high carrier mobility and ultralow resistivity of Graphene channel, a Graphene field effect transistor (GFET) is an interesting candidate for future RF and microwave electronics. In this paper, the introduction and review of existing compact circuit-level model of GFETs are presented. A compact GFET model based on drift-diffusion transport theory is then implemented in Verilog-A for RF/microwave circuit analysis. Finally, the GFET model is used to design a GFET-based distributed amplifier (DA) using advanced design system (ADS) tools. The simulation results demonstrate a gain of 8[math]dB, an input/output return loss less than [math]10[math]dB, [math]3[math]dB bandwidth from DC up to 5[math]GHz and a dissipation of about 60.45[math]mW for a 1.5[math]V power supply. The main performance characteristics of the distributed amplifier are compared with 0.18[math][math]m CMOS technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:04Z
      DOI: 10.1142/S0218126619502311
  • Compact, Programmable, Two-Stage Configuration for Implantable
           Biopotential Recording Amplifiers
    • Authors: Mohammad Hossein Maghami, Amir Masoud Sodagar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper [math]3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-[math]m technology, and consumes 0.022[math]mm2 and 0.27[math]mm2 of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8[math]V, power consumption of the proposed amplifier is 36.7[math][math]W with the simulated input-referred noise of 4[math][math] over 1[math]Hz–10[math]kHz for each channel. The amplifier also provides an output swing of 0.95 Vpp with a total harmonic distortion of [math]50[math]dB at the frequency of 1[math]kHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:03Z
      DOI: 10.1142/S0218126619200093
  • Efficient PSoC Implementation of Modular Multiplication and Exponentiation
           Based on Serial-Parallel Combination
    • Authors: M. Issad, B. Boudraa, M. Anane, A. M. Bellemou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than the input data length. The design must be scalable to support different security levels. The implementation achieves optimums execution time and HW resources number. In order to satisfy these constraints, Montgomery Power Ladder (MPL) and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution times. The application for 1024-bits data length shows that the MMM run in 6.24[math][math]s and requires 647 slices. The ME is executed in 6.75[math]ms using 2881 slices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:01Z
      DOI: 10.1142/S0218126619502293
  • Wide Tuning Range Varactorless Tunable Active Inductor-Based Voltage
           Controlled Oscillator for Wireless Applications
    • Authors: Omar Faruqe, Md Tawfiq Amin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90[math]nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46[math]GHz for the tuning voltage of 0.3–1.5[math]V. It consumes a low dc power ranging from 2.44[math]mW to 4.79[math]mW for the specified tuning range. The variation of phase noise ranges from [math][math]dBc/Hz to [math][math]dBc/Hz at 1[math]MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of [math][math]dBc/Hz with a differential output power of 1.8[math]dBm at tuning voltage of 0.7[math]V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:01Z
      DOI: 10.1142/S0218126619502426
  • Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection
    • Authors: Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High data rates and error-rate performance approaching close to theoretical limits are key trends for evolving digital wireless communication applications. To address the first requirement, multiple-input multiple-output (MIMO) techniques are adopted in emergent wireless communication standards and applications. On the other hand, turbo concept is used to alleviate the destructive effects of the channel and ensure error-rate performance close to theoretical limits. At the receiver side, the incorporation of MIMO techniques and turbo processing leads to increased complexity that has a severe impact on computation speed, power consumption and implementation area. Because of its increased complexity, the detector is considered critical among all receiver components. Low-complexity algorithms are developed at the cost of decreased performance. Minimum mean-squared error (MMSE) solution with iterative detection and decoding shows an acceptable tradeoff. In this paper, the complexity of the MMSE algorithm in turbo detection context is investigated thoroughly. Algorithmic computations are surveyed to extract the characteristics of all involved parameters. Consequently, several decompositions are applied leading to enhanced performance and to a significant reduction of utilized computations. The complexity of the algorithm is evaluated in terms of real-valued operations. The proposed decompositions save an average of [math] and [math] of required operations for 2 [math] 2 and 4 [math] 4 MIMO systems, respectively. In addition, the hardware implementation designed applying the devised simplifications and decompositions outperforms available state-of-the-art implementations in terms of maximum operating frequency, execution time, and performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:00Z
      DOI: 10.1142/S0218126619502281
  • A Transformation Methodology of Normal Nonlinear Resistors/Conductors to
    • Authors: C. Sánchez-López, V. H. Carbajal-Gómez, M. A. Carrasco-Aguilar, F. E. Morales-López
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work proposes a simple transformation methodology of normal nonlinear resistors/conductors to their inverted topologies in their floating and grounded versions (NNR/C). It is demonstrated that inverted topologies can also be configured as incremental or decremental nonlinear resistors/conductors. The main fingerprints of an NNR/C are holding up after the transformation and it is demonstrated that an inverse nonlinear resistor/conductor becomes a linear resistor/conductor when the operating frequency of the signal source decreases, inverse behavior in comparison with one memristor. Illustrative examples are given for floating and grounded nonlinear resistors and in both configurations. HSPICE simulation results are provided confirming the theory. Moreover, the normal and inverses resistors can be reconfigured in order to be used in future applications such as programmable analog circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:59Z
      DOI: 10.1142/S0218126619300113
  • An Electronically Controllable Voltage-Mode MOSFET-Only Single-Input
           Dual-Output Filter
    • Authors: Abdullah Yesil, Deniz Ozenli, Emre Arslan, Fırat Kacar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new design of voltage mode (VM), single-input dual-output MOSFET-only filter which has electronic tunability property is presented without using passive circuit elements like resistors and capacitors. The filter topology is able to realize low-pass (LP) and band-pass (BP) filter functions with using the same circuit configuration. The proposed filter is laid-out in the Cadence environment using 0.18-[math]m TSMC CMOS technology parameters. The layout area is only 344.4[math][math]m2 and the power consumption is about 170[math][math]W. Furthermore, variations in the center frequency of the BP filter are presented performing Monte Carlo (MC) analysis to reinforce the filter results. Also, the noise performance of the proposed filter is investigated and it is shown that the theoretical and simulation results are in very good agreement.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:59Z
      DOI: 10.1142/S0218126619502220
  • Dynamic Energy Reduction in TCAM Match-Line Sensing Using Charge-Sharing
           and Positive Feedback
    • Authors: Syed Iftekhar Ali, Safayat Bin Hakim
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180[math]nm 1.8[math]V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:57Z
      DOI: 10.1142/S0218126619502384
  • Ultra-Wideband Bandpass Filter Based on a Multi-Stub Loaded Loop Resonator
    • Authors: Xiaodong Xie, Zhizhan Yang, Mingxing Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A multi-stub loaded loop resonator (MSLLR) is proposed in this paper, which exhibits five main resonant modes of interest. Then, an ultra-wideband (UWB) bandpass filter is developed on it. Through direct source/load coupling, two transmission zeros can be created at both sides of the passband of the filter, which improves its frequency selectivity. The measured results of the fabricated filter show that its bandwidth can cover the UWB frequency range and the return loss in the passband is greater than 12.9[math]dB. Frequency selectivity is improved due to two transmission zeros at both sides of the passband. Group delay variation is less than 0.48[math]ns in the passband, which is relatively flat.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:56Z
      DOI: 10.1142/S0218126619200081
  • A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field
           Effect Transistor Including the Capacitive Effects
    • Authors: Sudipta Bardhan, Manodipan Sahoo, Hafizur Rahaman
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ([math]), transconductance ([math]), gate to drain capacitance ([math]) and gate to source capacitance ([math]) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than [math] NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:55Z
      DOI: 10.1142/S0218126619502414
  • A Novel Dual-Band Concurrent Asymmetric Doherty Power Amplifier for
           Wireless Communications
    • Authors: Shaban Rezaei Borjlu, Massoud Dousti
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a different dual-band asymmetric Doherty power amplifier (ADPA) with a novel dual-band bandpass filter (DBBPF) with quad-section stepped impedance resonators (SIRs) is presented. This specific DBBPF rejects the annoying frequencies of the second and third harmonics in the dual-band and contributes considerably to performance improvement of ADPA. This structure is confirmed with the design, simulation, implementation and testing of a 10 W GaN-based ADPA for global system for mobile communications (GSM) and worldwide interoperability for microwave access (WiMAX) applications at 1.84 and 3.5[math]GHz, respectively. In the measurement results, the ADPA defines a drain efficiency (DE) of 63.7% with an output power of 35[math]dBm and power gain is 14.2[math]dB, and a DE of 47.5% with an output power of 34.5[math]dBm and power gain is 10.4[math]dB at the 9[math]dB output power back-off (OBO) from the saturated output power in the two frequency bands. Linearity effects, applying 10[math]MHz 16 QAM signal and a 5[math]MHz WiMAX signal, display an adjacent channel leakage ratio of [math] and [math][math]dBc with the average output power of 36.8/36[math]dBm at 1.84/3.5[math]GHz, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:54Z
      DOI: 10.1142/S0218126619502359
  • A Novel LMMSE-EM Channel Estimator for High Mobility STBC-OFDM System
    • Authors: Jyoti Prasanna Patra, Poonam Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In time-selective fading channel, the Alamouti orthogonality principle is lost due to the variation of channel from symbol-to-symbol in space–time block-coded orthogonal frequency division multiplexing (STBC-OFDM) system and causes co-channel interference (CCI) effects. To combat the CCI effects, various signal detection schemes have been proposed earlier by assuming that a priori channel state information (CSI) is known to the receiver. However, in practice, the CSI is unknown and therefore accurate estimation of channel is required for efficient signal detection. In this paper, by exploiting circulant properties of the channel frequency response (CFR) autocorrelation matrix [math], we propose an efficient low complexity linear-minimum-mean-square-error (LMMSE) estimator. This estimator applies an expectation–maximization (EM) iterative process to reduce the computational complexity significantly. Finally, we compare the proposed LMMSE-EM estimator with conventional least square (LS) and LMMSE estimator in terms of performance and computational complexity. The simulation results show that the proposed LMMSE-EM estimator achieves exactly the same performance as the optimal LMMSE estimator with much lower computational complexity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:26Z
      DOI: 10.1142/S0218126619502232
  • Memristor Based Planar Tunable RF Circuits
    • Authors: C. L. Palson, D. D. Krishna, B. R. Jose, J. Mathew, M. Ottavi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Memristors have been recently proposed as an alternative to incorporate switching along with traditional CMOS circuits. Adaptive impedance and frequency tuning are an essential and challenging aspect in communication system design. To enable both, a matching network based on switchable capacitors with fixed inductors is proposed in this paper where the switching is done by memristive switches. This paper analyzes the operation of memristors as a switch and a matching network based on memristors which adaptively tunes with impedance and frequency. With three capacitor banks of each 0.5 pF resolution and two fixed inductors, matching for antenna impedance ranging from 20 to 200[math]Ohms and for frequencies ranging from 0.9 to 3.2[math]GHz is reported. Thereafter, an adaptive planar band-pass filter is implemented on CMOS technology with two metal layers. This adaptive frequency tunable band-pass filter uses a [math] network with resonator tanks in both arms that operates at 2.45 GHz. It is tunable from 2.8[math]GHz to 7.625[math]GHz range. This tunability is achieved using tunable spiral inductor based on memristive switches. The proposed filter layout is implemented and simulated in ANSYS Designer. The initialization and the programming circuitry to enable adaptive switching of the memristive devices has to be addressed. Since RF memristive devices are not commercially available, circuit level simulations are done as a proof of concept to validate the expected results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:26Z
      DOI: 10.1142/S0218126619502256
  • Time Efficient Segmented Technique for Dynamic Programming Based
           Algorithms with FPGA Implementation
    • Authors: Talal Bonny, Ridhwan Al Debsi, Mohamed Basel Almourad
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although dynamic programming (DP) is an optimization approach used to solve a complex problem fast, the time required to solve it is still not efficient and grows polynomially with the size of the input. In this contribution, we improve the computation time of the dynamic programming based algorithms by proposing a novel technique, which is called “SDP: Segmented Dynamic programming”. SDP finds the best way of splitting the compared sequences into segments and then applies the dynamic programming algorithm to each segment individually. This will reduce the computation time dramatically. SDP may be applied to any dynamic programming based algorithm to improve its computation time. As case studies, we apply the SDP technique on two different dynamic programming based algorithms; “Needleman–Wunsch (NW)”, the widely used program for optimal sequence alignment, and the LCS algorithm, which finds the “Longest Common Subsequence” between two input strings. The results show that applying the SDP technique in conjunction with the DP based algorithms improves the computation time by up to 80% in comparison to the sole DP algorithms, but with small or ignorable degradation in comparing results. This degradation is controllable and it is based on the number of split segments as an input parameter. However, we compare our results with the well-known heuristic FASTA sequence alignment algorithm, “GGSEARCH”. We show that our results are much closer to the optimal results than the “GGSEARCH” algorithm. The results are valid independent from the sequences length and their level of similarity. To show the functionality of our technique on the hardware and to verify the results, we implement it on the Xilinx Zynq-7000 FPGA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:25Z
      DOI: 10.1142/S021812661950227X
  • A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity
    • Authors: R. Nagulapalli
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by [math]20[math]dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to [math] will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5[math]dB PSRR improvement and 7.5% improvement in sensitivity to [math]. The proposed solution consumes 180[math]nW power from 1[math]V power supply voltage and occupies 3300[math][math]m2 silicon area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:25Z
      DOI: 10.1142/S0218126619502268
  • Hierarchical Optimization of Electric Vehicle System Charging Plan Based
           on the Scheduling Priority
    • Authors: Feng Ni, Linfang Yan, Ke Wu, Mengxuan Shi, Jianyu Zhou, Xia chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Unregulated charging of a large number of electric vehicles (EVs) simultaneously may cause electricity shortages and price spikes in the power market. This paper deals with the optimization of EV charging strategy using the priority sequence. Firstly, the evaluation indices such as the schedulable interval ratio, the emergency probability and the battery losses are proposed. Then a comprehensive evaluation system for the EV scheduling priority is established by adopting the entropy weight method to incorporate multiple indices. Based on the scheduling priority obtained, a double-hierarchical optimal model is proposed, taking into account the constraints such as the demand of the EV owner. Its upper objective aims to minimize the sum of the square of deviation between the actual and the required schedulable capacity of EV aggregator over every interval. The lower one minimizes the sum of EV scheduling priority sequence over the scheduling interval. Case studies with 100 EVs show that the hierarchical optimization model can assist EV aggregator in making effective charging scheme. It is also observed that better flexibility for dispatching EVs can be achieved using multiple indices with weights.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:24Z
      DOI: 10.1142/S0218126619502219
  • A Compact CPW-Fed Dual-Band Planar Monopole Antenna for LTE/2.4-GHz/WiMAX,
           C-Band and HiperLAN/2 Applications
    • Authors: Ahmed Zakaria Manouare, Saida Ibnyaich, Abdelaziz EL Idrissi, Abdelilah Ghammaz
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present the design of a compact planar monopole antenna for dual-band wireless communication applications. The proposed antenna is based on a planar structure composed by a CPW feed line and a rectangular ring with a vertical strip. The designed antenna has a small overall size of [math][math]mm3. Dual-band characteristics can be obtained by adjusting the distance between the rectangular ring and the ground plane of the CPW feed line, as well as the dimensions of the rectangular ring and the length of the vertical strip. A prototype of the proposed antenna which was fabricated and measured to validate the design reveals that there is a good agreement between the simulation and the experiment. The measured result shows that the antenna has the impedance bandwidths of 610[math]MHz (2–2.61[math]GHz) and 2600[math]MHz (3.18–5.78[math]GHz) with a reflection coefficient less than [math]10[math]dB covering all the LTE 2300, 2.4-GHz band, WiMAX, C-band and HiperLAN/2 applications. In addition, the dual-band monopole antenna exhibits almost omnidirectional radiation patterns and an appreciable gain over the operating frequency bands. Details of the proposed antenna design and both simulated and experimental results are analyzed and discussed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-27T09:49:30Z
      DOI: 10.1142/S0218126619502207
  • Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area
           for SAR ADC
    • Authors: Shubin Liu, Haolin Han, Ruixue Ding
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-26T01:11:55Z
      DOI: 10.1142/S0218126619300101
  • An Active-C Current-Mode Universal First-Order Filter and Oscillator
    • Authors: D. Agrawal, S. Maheshwari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an electronically tunable current-mode first-order universal filter. The proposed circuit employs only a single Extra-X Current-Controlled Conveyor (EX-CCCII) and a single grounded capacitor, which is suitable for IC implementation. The circuit can realize three current transfer functions simultaneously, namely low-pass, high-pass and all-pass. The proposed circuit exhibits low-input and high-output impedance, which is suitable for cascading. The pole frequency of the filter can be electronically tuned, by varying the bias current of EX-CCCII. The nonidealities and parasitic effects on the circuit performance are investigated in detail. Also, the Monte Carlo analysis is done to show the effect of active and passive element mismatches on the pole frequency. An eight-phase current-mode sinusoidal oscillator and current-mode second-order filter are further realized using the proposed circuit. The functionality of the proposed circuits is verified through PSPICE simulations, using 0.25-[math]m TSMC CMOS technology parameters.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-26T01:11:55Z
      DOI: 10.1142/S0218126619502190
  • A New Floating Memristor Based on CBTA with Grounded Capacitors
    • Authors: Abdullah Yesil, Yunus Babacan, Fırat Kacar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-17T09:16:52Z
      DOI: 10.1142/S0218126619502177
  • A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body
    • Authors: Pratosh Kumar Pal, Rajendra Kumar Nagaria
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A low-voltage and low-power all-MOSFET voltage reference is presented having most of the transistors working in subthreshold region. The basic beta-multiplier with cascode transistor provides a supply-independent current utilized by the active load circuit to generate an output reference voltage using body biasing. The proposed circuit is simulated using standard SCL 180-nm CMOS technology for the supply voltage ranging from 0.75[math]V to 1.8[math]V. The simulation obtains an average output voltage reference of 450.4[math]mV for the given supply range at room temperature. The minimum power dissipation at room temperature is 54.37[math]nW. The temperature coefficient (TC) of 28.13[math]ppm/∘C is achieved having the temperature range of [math]10–87∘C for the minimum operating supply voltage. It has the PSRR values of [math]39.4[math]dB at 100[math]Hz and [math]12[math]dB at 1[math]MHz. Also, the active area of the proposed circuit is 0.014[math]mm2.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-17T09:16:51Z
      DOI: 10.1142/S0218126619502153
  • Design of Dual-Sampling and Adaptive Predictive PID Controller for Buck
           DC–DC Converters
    • Authors: Changyuan Chang, Jidong Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, based on the combination scheme of dual-sampling and adaptive predictive PID control, a digital controller for improving the transient performance of Buck DC–DC converters is designed. Due to the inherent loop delay in analog-to-digital (A/D) conversion, the calculation process of the digital controller and digital pulse width modulator (DPWM) of conventional digitally-controlled Buck DC–DC converters limits the system bandwidth and this makes the transient response lower. The designed digital controller can reduce the delay time in analog-to-digital converter (ADC), the digital controller and DPWM of digitally-controlled Buck DC–DC converters. Adaptive predictive control is used to eliminate the delay time of ADC and the digital controller, while dual-sampling scheme is used to reduce the delay time of DPWM in this paper. These are two new control schemes, and they show better performance in improving the transient response than other existing control schemes. Both simulation and experimental results demonstrate that the designed digital controller based on dual-sampling and adaptive predictive PID control is effective in improving the transient performance of Buck DC–DC converters. During experimental verification, for a load step between 0.5[math]A and 1.0[math]A, the fastest transient recovery time and the overshoot voltage are found to be 102[math][math]s and 120[math]mV, respectively. Compared with the conventional digital PID controller, the transient recovery time and the overshoot voltage of the digital controller designed in this paper are decreased by 40.0% and 27.3%, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-17T09:16:50Z
      DOI: 10.1142/S0218126619501950
  • Fast and Accurate System-Level Power Estimation Model for FPGA-Based
    • Authors: Abhishek N. Tripathi, Arvind Rajawat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present an efficient and fast system-level power estimation model for the FPGA-based designs. To estimate the dynamic power early, first time, LLVM IR code analysis is employed at the C-level designs and then the neural network-based estimation model is built from the information obtained from this high-level profiling. The model accuracy is validated through designs of heterogeneous domains from the CHStone and MachSuite benchmarks. An insignificant relative error of 0.21–3.6% is observed for the analyzed benchmark designs with the exceptional increase in the estimation speed by 63 times of magnitude as compared to the Xilinx Vivado Design Suite. Moreover, the model eliminates the need for synthesis-based exploration. In addition, the effectiveness of proposed approach is also verified through a comparison with the other reported works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-17T09:16:49Z
      DOI: 10.1142/S0218126619502189
  • Configurable Operational Amplifier Architectures Based on Oxide Resistive
    • Authors: Hassen Aziza, Christian Dufaza, Annie Perez, Said Hamdioui
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-11T03:59:38Z
      DOI: 10.1142/S0218126619502165
  • Probe Feed Multi-Element Multi-Segment Triangular Dielectric Resonator
           Antenna with RCS Analysis
    • Authors: Pinku Ranjan, Ravi Kumar Gangwar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of the paper is to propose a design and analysis of multi-element multi-segment triangular dielectric resonator antenna (MEMS TDRA) with Radar Cross-Section (RCS). The proposed antenna has been excited through coaxial probe feed. The coaxial probe feed excites TM[math] dominant mode fields within the TDR elements. A general guideline for wide bandwidth and high gain has been prepared for designing of MEMS TDRA. The model of the proposed MEMS TDRA has been studied through simulation (Ansoft HFSS software) and fabricated for measurement. The simulated antenna performance has good agreement with the measured one. The proposed MEMS TDRA performance has been compared with some similar type of previously published structure and found wider bandwidth and higher gain. The proposed MEMS TDRA provides monopole-like radiation pattern with nearly 39% bandwidth ([math] dB). The average gain of 6.0 dBi has been found over the entire bandwidth. The RCS analysis has been performed for monostatic and bistatic modes at different frequencies and angles. The proposed antenna is appropriate for WLAN and WiMAX applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-11T03:59:37Z
      DOI: 10.1142/S0218126619502086
  • A High-Precision Bandgap Voltage Reference with Automatic
           Curvature-Compensation Technique
    • Authors: Ze-kun Zhou, Hongming Yu, Yue Shi, Zhuo Wang, Bo Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A high-precision bandgap voltage reference (BGR) with a novel curvature-compensation scheme is proposed in this paper. The temperature coefficient (TC) can be automatically optimized with a built-in adaptive curvature-compensation technique, which is realized in a digitization control way. An exponential curvature-compensation method is first adopted to reduce the TC in a certain degree, especially in low temperature range. Then, the temperature drift of BGR in higher temperature range can be further minimized by dynamic zero-temperature-coefficient point tracking (ZTCPT) with temperature changes. With the help of proposed adaptive signal processing, the output voltage of BGR can approximately maintain zero TC in a wider temperature range. Verification results of the BGR proposed in this paper, which is implemented in 0.35-[math]m BiCMOS process, illustrate that the TC of 1.4[math]ppm/[math]C is realized under the power supply voltage of 3[math]V and the power supply rejection of the proposed circuit is [math][math]dB without any filter capacitor.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-11T03:59:36Z
      DOI: 10.1142/S0218126619502141
  • Amplifier-Aware Content-Based Precoder Design for Hierarchical Image
           Transmission over a Realistic MIMO-OFDM Channel
    • Authors: Hermann Sohtsinda, Clency Perrine, Smail Bachir, Claude Duvanaud, Christian Chatellier
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes the design of a precoder in MIMO systems dedicated to JPEG Wireless (JPWL) (ISO/IEC 15444-11) image transmission which jointly takes into account the channel noise and the nonlinear distortions due to the high power amplifier (HPA) used in the transmitter. MIMO-OFDM (Orthogonal Frequency Division Multiplexing) systems dedicated to image transmission rely only on the Channel State Information (CSI) and the image content to design their precoding solutions. However, the nonlinear behavior of the HPA used at the front-end is not taken into account when designing the current precoders. In order to ensure the QoS of the transmitted image, a large level back-off is usually applied to avoid the nonlinear distortions generated by the HPA. In addition, the Input Back-off (IBO) value is statically chosen and does not depend on the other parameters of the link such as the instantaneous MIMO channel status, the modulation order and the scalability of the JPWL content. This may reduce both the global energy efficiency and the transmission quality of the Radio-Frequency (RF) link. Therefore, this work proposes a new precoding scheme to allocate the total available power while dynamically adjusting the optimal power IBO value according to the HPA parameters, the instantaneous channel status and the image content to be transmitted. Numerical results using a commercial HPA model under the IEEE 802.11n standard show that the proposed power allocation algorithm improves the visual quality of the received JPWL images compared to the state-of-the-art over a realistic radio channel model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-10T02:22:24Z
      DOI: 10.1142/S0218126619502098
  • A Low Power and Low Current-Mismatch Charge Pump with Dynamic Current
    • Authors: Lianxi Liu, Shaopu Gao, Junchao Mu, Zhangming Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel low power charge pump (CP) that minimizes the mismatch between the charging and the discharging currents is proposed in this paper. The switching circuit with dynamic current compensation is used to reduce the power consumption of the proposed CP. In addition, precise current replication which makes use of the resistors and the low offset operational amplifiers (OTA) can enable a reduction in current mismatch caused by process mismatch. Meanwhile, the high output impedance can reduce the current mismatch caused by the channel length modulation effect. Based on the 0.18[math][math]m deep-Nwell CMOS process, the proposed CP can reduce the overall power consumption by 56% compared with the CP without current compensation, reduce the current mismatch caused by process mismatch to less than 0.9% and reduce the current mismatch caused by the channel length modulation effect to less than 0.01% over the output voltage ranging from 0.3 to 1.5[math]V with 1.8[math]V supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-10T02:22:24Z
      DOI: 10.1142/S021812661920007X
  • Boolean Difference Technique for Detecting All Missing Gate and Stuck-at
           Faults in Reversible Circuits
    • Authors: Joyati mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates. One example of reversible gate is Toffoli gate. A Toffoli gate (also known as [math]-CNOT) has two components — the control and the target. Initially, stuck-at fault and other fault models were used for modeling defects in quantum reversible circuits. Later, a new fault model known as missing gate fault model was introduced, which is more effective in capturing the errors in quantum reversible circuit. Boolean Difference is already a known technique to detect stuck-at faults in conventional CMOS circuit. In this paper, Boolean Difference method is applied to derive the test set for detecting each stuck-at fault and missing gate fault in a reversible circuit. Then an optimization algorithm is used to derive an optimal test set, which will detect all possible faults in a circuit. The method is valid also for other fault models.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-10T02:22:22Z
      DOI: 10.1142/S0218126619502128
  • A Group-Based Buffer Management for SSD
    • Authors: Yan Liu, Jilong Xu, Guoqi Xie, Zaimei Zhang, Keqin Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Random writes limit the application of SSDs significantly because of their poor latency and high garbage collection overhead. Traditional page-based and block-based buffer management algorithms cannot achieve both high buffer hit ratio and good destage sequentiality at the same time. In this paper, we propose a hybrid scheme called the group-based buffer management (GBBM). To improve buffer hit ratio and decrease write/erase counts, GBBM divides buffer space into Page Region and Group Region. The frequently accessed data pages are placed at the Page Region, while infrequently accessed random written data are grouped in the Group Region. GBBM has been evaluated extensively through simulations. The write counts of GBBM show an average decrease of 12.7% compared with page-level buffer scheme. Compared with hybrid buffer management such as CBM, GBBM decreases the average write/erase count by 14.3%/12.1%. The write hit ratio of GBBM shows a 4.5% improvement as compared with PAB. The proposed GBBM can significantly reduce the number of write operations while maintaining a relatively high buffer hit ratio.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-10T02:22:17Z
      DOI: 10.1142/S021812661950213X
  • Global Multiprocessor Scheduling with Job Level Priority Assignment
    • Authors: Tao Yang, Qingxu Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the field of real-time multiprocessor scheduling, researchers have found that global scheduling on average results in better resource utilization than partitioned scheduling, and is more robust in the presence of timing errors. In this paper, we present a global scheduling algorithm JPA with Job-level Priority Assignment for sporadic task systems that can be viewed as a generalization of both FPS and EDF. We also introduce JPA's efficient variant, which greatly reduces the runtime overhead comparing with JPA. As will be shown by the experiments, JPA indeed exhibits much better performance than the state-of-the-art multiprocessor scheduling/analysis techniques based on FPS and EDF.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-10T02:22:16Z
      DOI: 10.1142/S0218126619502104
  • An Optimized Approach to Pipelined Architecture for Fast 2D Normalized
    • Authors: R. E. Chaudhari, S. B. Dhok
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An optimized hardware architecture for fast normalized cross-correlation (NCC) is essential in real-time high-speed applications. Typical applications of NCC are in object localization, as one of the best motion estimators and as a similarity measure in the field of image processing. However, high computational cost is a significant drawback of NCC. To reduce computation time and hardware resource usages, this paper presents a feed-forward single-path architecture with parallel computation of numerator and denominator components of NCC. The cross-correlation of two signals is implemented in the frequency domain using pipelined architecture of 2D FFT with polyphase sequential subband decomposition technique. The FFT can be determined for any even length of signal when compared to the traditional method involving a power of two-signal length. The proposed pipelined architecture of NCC is more efficient in terms of computational complexity and memory requirement. This proposed architecture is implemented in Verilog HDL with fixed-point data type which helps to devise simple and efficient architecture, which gives excellent SQNR of more than 90 dB with 22-bit output word length. It can operate at the maximum clock frequency of 220.4[math]MHz, takes a total NCC time of 4.36[math][math]s and has a latency of 996 cycles, giving a throughput of 220 Msamples/s for a block size of [math] pixels using Virtex-7 FPGA. This pipelined architecture not only offers an attractive solution for different sizes of image block, but also improves the speed of the system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-10T02:22:14Z
      DOI: 10.1142/S0218126619502116
  • Novel Architecture for Low-Power CNTFET-Based Compressors
    • Authors: Morteza Dadashi Gavaber, Mehrdad Poorhosseini, Saadat Pourmozafari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Carbon nanotube field-effect transistors (CNTFETs) are excellent candidates for the replacement of traditional CMOS circuits. One of the most important modules in many arithmetic circuits is multiplier. Sometimes multipliers may occupy more area as well as consume high power which may cause speed reduction in the critical path. Compressors are important building blocks which are used in most multipliers. In this paper, a low-power architecture is proposed which can be used in compressor designs. The proposed architecture uses a low-power three-input XOR gate to reduce area, delay and power consumption. In order to evaluate the delay and power consumption of circuits, we have used four different types of compressors (3–2, 4–2, 5–2 and 7–2). These four designs were simulated using HSPICE simulation tool with 32-nm CMOS model based on 1-V and 1-GHz frequency operator. The results indicate that the proposed compressor architectures have less power–delay product (PDP) and power consumption in comparison with the existing proposed compressors.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-03T02:44:19Z
      DOI: 10.1142/S0218126619502074
  • Study of MEMS Touch-Mode Capacitive Pressure Sensor Utilizing Flexible SiC
           Circular Diaphragm: Robust Design, Theoretical Modeling, Numerical
           Simulation and Performance Comparison
    • Authors: Sumit Kumar Jindal, M. Aditya Varma, Deepali Thukral
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Copious research has been conducted on Capacitive Pressure Sensors over the decades with a focus on Silicon being the primary filming element. However, due to Silicon Carbide emerging as superior in harsh environmental conditions, the research is gravitating towards it for industrial applications. This work presents a new analytical model for a polycrystalline silicon carbide-based capacitive pressure sensor working in touch-mode operation. Carbide demonstrates properties like electrical stability, mechanical robustness and chemical inertness which puts it on the frontier of research. The mathematical model proposed is a simple yet powerful tool in manipulating design and sizing for fast analysis. It is quicker and bypasses the need for complex simulation software. The analysis is purely mathematical and hence the results are analyzed with MATLAB. The mathematical model developed is verified with a standard Finite Element Analysis (FEM) using COMSOL v5.2. The results of the mathematical analysis dovetail well with the FEM analysis and show a significant improvement in both the sensitivity and capacitance generated.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-12-03T02:44:18Z
      DOI: 10.1142/S0218126619502062
  • Synthesis Approach for Compact VDTA Quadrature Sine-Wave Oscillators with
           Orthogonal Control
    • Authors: Yong-An Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      From the nodal admittance matrix (NAM) expansion approach and 16 pathological patterns of the voltage differencing transconductance amplifier (VDTA), two different categories, namely sort A and sort B, of the quadrature sine-wave oscillators-employed VDTAs and grounded capacitors in the current mode are synthesized. In all, four quadrature sine-wave oscillators with two sets of quadrature current outputs are attained. Because canonic number is used for component quantity, the oscillators are appropriate to integrated circuit realization and also provide electronic, linear, and orthogonal adjustments between the oscillation criterion and frequency by means of tuning bias currents of the VDTAs. The paper-and-pencil and simulation analyses as well as experimental analysis have been carried out to check the utilized synthesis approach.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-28T09:03:55Z
      DOI: 10.1142/S0218126619502050
  • Analysis and Optimization of Voltage-Driven Double-Balanced Passive Mixer
           for MICS Band Receiver
    • Authors: Mouna Bettaieb, Ghazi Bouzid, Saif Benali, Hatem Trabelsi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents analysis of a 25% duty-cycle fully-differential double-balanced passive mixer dedicated to medical implantable devices. The proposed passive mixer is part of a medical implant communication service (MICS) receiver front-end operating at 402–405[math]MHz. By performing time-domain analysis, two LTI models have been developed to study the fully-differential double-balanced passive mixer: A simplified model and a complete model taking into account harmonic components. Both models account for the AC coupling capacitors at the mixer input and account for baseband voltage variation over one LO period. In this study it has been shown the ability of mixer input impedance matching by varying baseband resistor at the mixer output. The frequency of match can be controlled by varying the AC coupling capacitors and baseband capacitors. The performance of the proposed models was compared with that of the mixer and the results were very close. In particular, the results of simulations of the input impedance as a function of the baseband resistance and as a function of the IF frequency show the validity of the proposed models. The main parameters of the passive mixer such as input impedance, gain and noise figure (NF) were optimized taking into account the constraints of our application. The proposed mixer is designed to operate at LO frequency of 403.2[math]MHz. Transistors size is optimized to meet the receiver specifications. The mixer realizes a conversion gain of 0[math]dB and an NF of 4.8[math]dB. Linearity simulations show 25.2[math]dBm for IIP3 and 9.66[math]dBm for [math]. The mixer consumes 1.44[math]pW without LO circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-28T09:03:45Z
      DOI: 10.1142/S0218126619502049
  • Programming of Memristive Artificial Synaptic Crossbar Network Using PWM
    • Authors: P. Michael Preetam Raj, Arvind Subramaniam, Shashank Priya, Souri Banerjee, Souvik Kundu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Memristor resembles an artificial synapse and is considered to be basic electronic element for realizing neuromorphic circuits. In this work, a systematic investigation was conducted on memristor-based resistance-programming circuits to write analog data into a memristor utilizing pulse width modulation techniques. The high-frequency sinusoidal signal was utilized to read the data in the form of its electronic resistance. An optimum circuit configuration demonstrated multilevel stable resistive states, which are analogous to the connection weights in the human synapse. In order to modulate these memristive weights for representing the learning activities in human brain synapse, it was identified that the pulse width modulation technique is superior as compared to spike-timing-dependent plasticity. Further, the above analysis was utilized in training the memristor to update its resistive weights in consonance with its learning, analogous to that in a neural network. Further, the memristive crossbar architecture was utilized to implement a real-time application in Econometrics, where an array of memristors were utilized to learn and update the purchase trends of an [math] matrix of customers. The proposed circuits possess the advantages of high packing density, low power consumption and nonvolatility, and also pave the way for developing future neuromorphic circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-23T07:14:52Z
      DOI: 10.1142/S0218126619502013
  • ASIC and FPGA Comparative Study for IoT Lightweight Hardware Security
    • Authors: Nagham Samir, Abdelrahman Sobeih Hussein, Mohaned Khaled, Ahmed N. El-Zeiny, Mahetab Osama, Heba Yassin, Ali Abdelbaky, Omar Mahmoud, Ahmed Shawky, Hassan Mostafa
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Data security, privacy and authenticity are crucial in wireless data transmission. Low power consumption is the main requirement for any chip design targeting the Internet of Things (IoT) applications. In this research paper, a comparative study of eight authenticated encryption and decryption algorithms, selected from the “Competition for Authenticated Encryption: Security, Applicability and Robustness” (CAESAR), namely, ACORN, ASCON, CLOC, JOLTIK, MORUS, PRIMATEs, SCREAM and SILC, is presented. The FPGA and ASIC implementations of these eight algorithms are synthesized, placed and routed. Power, area, latency and throughput are measured for all algorithms. All results are analyzed to determine the most suitable algorithm for IoT applications. These results show that ACORN algorithm exhibits the lowest power consumption of the eight studied at the expense of lower throughput and higher latency. MORUS algorithm gives the highest throughput among the eight selected algorithms at the expense of large area utilization.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-23T07:14:51Z
      DOI: 10.1142/S0218126619300095
  • YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine
           Supporting Congestion-Aware Adaptive Routing Using FPGAs
    • Authors: Khyamling Parane, B. M. Prabhu Prasad, Basavaraj Talawar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [math] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [math] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-23T07:14:50Z
      DOI: 10.1142/S0218126619502025
  • Electrolytic Capacitorless AC/DC LED Driver
    • Authors: Changyuan Chang, Xiong Han, Menglin Wu, Dadi Zhao, Hongliang Xu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents electrolytic capacitorless AC/DC LED driver. It adopts Boost–Buck topology, through modulation of the conduction time [math] and the change of input current reference, to reduce the instantaneous input and output power difference, so a smaller film capacitor can be used instead of the electrolytic capacitor. Therefore, LED driver power life has been effectively improved. The Buck converter operates in the inductor current discontinuous conduction mode to achieve constant output current by controlling the peak current. The control IC is fabricated in TSMC 0.35-[math]m 5-V/650-V CMOS/LDMOS process, and verified in a 72-V/150-mA circuit prototype. The test results show that when the range of input voltage is 175–264 Vac, the efficiency of the system is 83%, the voltage linear regulation is [math]%, the load regulation is [math]%, and the electrolytic capacitor is replaced by 470-nF CBB capacitor under the condition that the power factor is above 0.7. Therefore, the design of the control chip in the LED driver has a very good application prospect.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-23T07:14:48Z
      DOI: 10.1142/S0218126619502001
  • Parloom: A New Low-Power Set-Associative Instruction Cache Architecture
           Utilizing Enhanced Counting Bloom Filter and Partial Tags
    • Authors: Sajjad Rostami-Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The cache system dissipates a significant amount of energy compared to the other memory components. This will be intensified if a cache is designed with a set-associative structure to improve the system performance because the parallel accesses to the entries of a set for tag comparisons lead to even more energy consumption. In this paper, a novel method is proposed as a combination of a counting Bloom filter and partial tags to mitigate the energy consumption of set-associative caches. This new hybrid method noticeably decreases the cache energy consumption especially in highly-associative instruction caches. In fact, it uses an enhanced counting Bloom filter to predict cache misses with a high accuracy as well as partial tags to decrease the overall cache size. This way, unnecessary tag comparisons can be prevented and therefore, the cache energy consumption is considerably reduced. Based on the simulation results, the proposed method provides the energy reduction from 22% to 31% for 4-way–32-way set-associative L1 caches bigger than 16[math]kB running the MiBench programs. The improvements are attained with a negligible system performance degradation compared to the traditional cache system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-16T06:19:26Z
      DOI: 10.1142/S0218126619502037
  • Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power
           Efficient Technique for VLSI Circuit Design
    • Authors: Anjali Sharma, Harsh Sohal, Harsimran Jit Kaur
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[math]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[math]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[math]nm technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-15T04:02:31Z
      DOI: 10.1142/S0218126619501974
  • A 3.5-GHz Class-F Power Amplifier with Current-Reused Topology in
           0.13-[math]m CMOS for 5G Application
    • Authors: Dan Li, Sichun Du
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a 3.5-GHz class-F Power Amplifier with current-reused topology in 0.13-[math]m CMOS for 5G application is presented. This proposed circuit has a two-stage structure by a current-reused topology driving to improve gain and the stability of PA. An output matching network is constructed by an open-circuited third harmonic resonator that can integrate the current and voltage waveform in the time domain adopted to improve the output power and reduce power consumption. The simulation results show that the proposed PA provides a 13[math]dBm output power with a PAE of 50.5% and a small signal gain of 32.5[math]dB that is higher than reported for a two-stage design in CMOS at the 3.5-GHz frequency, while the minimum output return loss (S[math]) is [math]14.4[math]dB with a minimum value of [math]24.67[math]dB. Many experiments are carried out to prove that the proposed PA has higher gain and higher efficiency compared to the traditional class-F power amplifier and is suitable for 5G short-range applications. Finally, the layout occupies a compact chip area of [math][math]mm2, including testing pads.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-15T04:02:24Z
      DOI: 10.1142/S0218126619501937
  • Synchronization Stability Analysis of Medical Cyber-Physical Cloud System
           Considering Multi-Closed-Loops
    • Authors: Li Liu, Guoqi Xie, Renfa Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Medical cyber-physical system (MCPS) is usually used in hospitals to provide continuous services (e.g., glycemic monitor and alarm) for patients. In this paper, we introduce cloud computing to integrate multiple MCPSs of hospitals to construct medical cyber-physical cloud system (MCPCS). Such complex MCPCS need stability analysis to guarantee collaboration among multiple MCPSs. We treat the MCPCS as a complex network, where each MCPS is considered as a node. Then, we introduce the Lyapunov stability theory for synchronization stability analysis of MCPCS by considering multi-closed-loops. For different network types, the dynamic equations of MCPSs were improved through introducing feedback in the multi-closed-loops. For the problem that different networks cause different delays, we select three networks to solve sufficient conditions for the synchronization stability of MCPCS. Experiments are performed to confirm the efficiency of sufficient conditions and the synchronization stability of MCPCS.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-15T04:02:17Z
      DOI: 10.1142/S0218126619501986
  • A Simple WiMAX and RFID Band-Notched UWB Bandpass Filter and Its
           Susceptibility Study
    • Authors: Lakhindar Murmu, Santasri Koley, Amit Bage, Sushrut Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An ultra-wideband (UWB) bandpass filter (BPF) with a fractional bandwidth (FBW) of about 110%, transmission zero at the high-frequency edge, and band notches at the worldwide interoperability for microwave access (WiMAX) and radio frequency identification (RFID) band is presented in this paper. The filter is based on single short-circuited stub, U-shaped defected ground structure (DGS) array, two U-shaped resonators and two stepped impedance resonators (SIRs). The filter is compact and exhibits a selective filtering characteristic equivalent to a three-pole Chebyshev filter. The design procedure has been described and verified by full-wave electromagnetic (EM) simulation and measurement. The proposed filter has low insertion loss, sharp rejection, and excellent in and out band performance. Due to its applications in WiMAX and RFID systems, the filter may be subjected to high EM radiation from the antenna and nearby sources. Therefore, susceptibility study of such a filter is very important. Hence, the susceptibility study of the band-notched UWB BPF has been carried out by subjecting the structure to an interference source.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-15T04:02:13Z
      DOI: 10.1142/S0218126619501962
  • Optimum Structure-Based Multi-level Inverter with Doubling Circuit
    • Authors: Saikat Majumdar, Bidyut Mahato, Kartick Chandra Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A single-phase cascaded generalized doubling circuit-based multi-level inverter configuration is presented that can generate maximum number of output voltage levels by distributing the total asymmetrical input DC link voltage among the cells using minimum number of power switches. A cell consists of [math] numbers of sub-cells each having two DC voltage sources connected in series along with a half-bridge circuit and a polarity reversal unit. Moreover, an optimum structure of novel proposed MLI is presented and well described in the paper. A laboratory prototype of proposed 15-level MLI is developed and the experimental results are found at par with the simulation results. The experimental results are captured for different modulation indices to show the effectiveness of the proposed MLI that can be used for Photovoltaic (PV) applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-15T04:02:09Z
      DOI: 10.1142/S0218126619501949
  • FPGA Virtualization Mechanism Based on Heterogeneous Zynq Platforms
    • Authors: Zhilei Chai, Wei Liu, Qin Wu, Qunfang He, Wenjie Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      FPGA (Field Programmable Gate Array) has the advantages of parallelism and reconfigurability, therefore, it is widely used in areas such as image processing, robotics and artificial intelligence. However, the development of FPGA currently involves too many hardware details, so it lacks extensibility for different platforms and flexibility for system level management and scheduling. In this paper, we propose an FPGA Virtualization Mechanism (FVM), which divides physical resources into pages (virtual resources). We use the technology of PR (Partial Reconfiguration) and the method of intermediate form to lift the extensibility and performance. We implement FVM in our platform VSC (Vary Super Computer System). Experiment results show that FVM can solve the problem of extensibility and flexibility, with high performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-08T02:43:39Z
      DOI: 10.1142/S0218126619501998
  • Lifetime Reliability Enhancement in Multiprocessor Systems Through a
           Fine-Grained System-Level Approach
    • Authors: Athena Abdi, Masoomeh Karami, Hamid R. Zarandi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a fine-grained scheduling approach to enhance lifetime reliability of multiprocessor systems is presented. Lifetime reliability is an important and emerging concern arising with advances in technology due to the increase in power density. As a result, temperature variation accelerates wear-out, leading to system failures. The antagonistic relation of lifetime reliability with other design parameters of multiprocessor systems, such as power consumption and temperature, makes its improvement more challenging. Lifetime reliability enhancement approaches are considered at different levels of abstractions and for various system components. Our proposed scheduling method extracts the precise low-level information of lifetime reliability from determined blocks of processing cores and utilizes them at system-level to study the system state criticality at a low-performance cost. Based on the online periodic monitoring, our proposed scheduling approach applies control actions to improve lifetime reliability of the system according to its effective parameters. To demonstrate the effectiveness of our proposed scheduling approach in improving lifetime reliability and compare it to the previous related research, several experiments are considered. To simulate the target multiprocessor system and the proposed approach, the Enhanced Super ESCalar (ESESC) simulator for computer architecture tool is utilized. The experimental results show that employing our proposed scheduling method improves lifetime reliability at about 54[math]. Moreover, it causes 14% and 12% enhancement in temperature and power consumption. Furthermore, we perform a Monte Carlo-based simulation to validate the proposed scheduling approach and generalize it to other applications at very low-performance overhead. Experimental results show that Monte Carlo simulation extremely decreases the execution time rather than ESESC which makes utilizing our scheduling approach reasonable in large applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-08T02:43:38Z
      DOI: 10.1142/S0218126619501913
  • Enhanced Parallel Application Scheduling Algorithm with Energy Consumption
           Constraint in Heterogeneous Distributed Systems
    • Authors: Jinghong Li, Guoqi Xie, Keqin Li, Zhuo Tang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Energy consumption has always been one of the main design problems in heterogeneous distributed systems, whether for large cluster computer systems or small handheld terminal devices. And as energy consumption explodes for complex performance, many efforts and work are focused on minimizing the schedule length of parallel applications that meet the energy consumption constraints currently. In prior studies, a pre-allocation method based on dynamic voltage and frequency scaling (DVFS) technology allocates unassigned tasks with minimal energy consumption. However, this approach does not necessarily result in minimal scheduling length. In this paper, we propose an enhanced scheduling algorithm, which allocates the same energy consumption for each task by selecting a relatively intermediate value among the unequal allocations. Based on the two real-world applications (Fast Fourier transform and Gaussian elimination) and the randomly generated parallel application, experiments show that the proposed algorithm not only achieves better scheduling length while meeting the energy consumption constraints, but also has better performance than the existing parallel algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-08T02:43:37Z
      DOI: 10.1142/S0218126619501901
  • A High Gain, 808[math]MHZ GBW Four-Stage OTA in 65[math]nm CMOS
    • Authors: Zhe Li, Rui Ma, Maliang Liu, Ruixue Ding, Zhangming Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath [math]-[math] compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65[math]nm 1.2[math]V CMOS process, achieving 808[math]MHz gain-bandwidth, 119[math]dB DC gain, 585[math]V/[math]s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2[math]V with power consumption of 2.17[math]mW and the layout area is 0.011[math]mm2.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-07T02:13:32Z
      DOI: 10.1142/S0218126619501925
  • Dual-Notched Monopole Antenna Using DGS for WLAN and Wi-MAX Applications
    • Authors: Arnab De, Bappadittya Roy, Anup Kumar Bhattacharjee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a wideband printed polygon-shaped monopole antenna has been designed using microstrip line feeding technique which provides dual-notch band characteristics (2.98–3.19[math]GHz) and (3.62–5.00[math]GHz) by the use of slots geometry in both the patch and the ground plane. The results of the antenna have been compared both with and without slots in both planes. The initial antenna without DGS and slots in the patch was made to work in the frequency range from 2.56–5.98[math]GHz having impedance bandwidth of about 80.09%. The proposed antenna can be made usable for multi-band applications such as WLAN (2.4/3.2/5.2/5.8[math]GHz) and Wi-MAX (3.5 and 5.5[math]GHz) applications providing fractional bandwidth (FBW) of 85.36% (2.33–5.80[math]GHz) and maximum peak gain of 5.65[math]dBi at 3.50[math]GHz. The value of return loss obtained is about 53.36[math]dB at 2.56[math]GHz. Prototype of the final antenna is fabricated and the results are verified with the simulated ones.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-02T07:35:33Z
      DOI: 10.1142/S0218126619501895
  • MASH DDSM with Negative Feedback
    • Authors: Yilong Liao, Xiangning Fan, Zaijun Hua
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) with negative feedback to acquire the maximum sequence length. The mathematical analysis shows that the sequence length is [math], which is not affected by the input values and initial conditions, where [math] is the smallest prime number above the quantization interval [math], and [math] is the order of the MASH DDSM. Moreover, the influence of the negative feedback on the input range is analyzed. Finally, the simulations and experiments are performed to verify the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-11-02T07:35:30Z
      DOI: 10.1142/S0218126619501883
  • An Efficient Privacy-Preserving Attribute-Based Encryption with Hidden
           Policy for Cloud Storage
    • Authors: Chanying Huang, Songjie Wei, Anmin Fu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cloud storage is one of the most widely-used storage services, because it can provide users with unlimited, scalable, low-cost and convenient resource services. When data is outsourced to cloud for storage, data security and access control are the two essential issues that need to be addressed. Attribute-based encryption (ABE) scheme can provide sufficient data security and fine-grained access control for cloud data. As more and more attention is drawn to privacy protection, privacy preservation becomes another urgent issue for cloud storage. In ABE, since the access policies are generally stored in clear text, it will lead to the disclosure of users’ privacy. Some works sacrifice computational efficiency, key length or ciphertext size for privacy concerns. To solve these problems, this paper proposes an efficient privacy-preserving attribute-based encryption scheme with hidden policy for outsourced data. Using the idea of Boolean equivalent transformation, the proposed scheme achieves fast encryption and privacy protection for both data owner and legitimate visitors. In addition, the proposed scheme can satisfy constant secret key length and reasonable size of ciphertext requirements. We also conduct theoretical security analysis, and carry out experiments to prove that the proposed scheme has good performance in terms of computation, communication and storage overheads.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-31T06:19:45Z
      DOI: 10.1142/S021812661950186X
  • Fully Integrable/Cascadable CM Universal Filter and CM Quadrature
           Oscillator Using VDCC and Only Grounded Passive Elements
    • Authors: Tajinder Singh Arora, Bhargavi Rohil, Soumya Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a current mode universal filter circuit, employing two active elements along with four grounded passive components only. The derived circuit realizes all five filtering responses, i.e., low pass (LP), band pass (BP), high pass (HP), band reject (BR) and all pass (AP), simultaneously from high-impedance ports along with the input being fed to low-impedance port, thus making it a fully cascadable filter. In addition, the designed circuit exhibits independent tunability of its quality factor. With the idea of making the proposed filter fully integrable, a resistor-less approach of the configuration has also been discussed. By making slight modifications in the filter configuration, a current mode single-resistance-controlled quadrature oscillator circuit has also been derived. The ideal, nonideal, sensitivity and parasitic analysis have been conducted for the designed configurations. The functionality of the proposed structures is verified by PSPICE simulations using 0.18[math][math]m CMOS technology. The designs have also been verified using PSPICE macro-model of the commercially available IC, i.e., OPA860.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-31T06:19:44Z
      DOI: 10.1142/S0218126619501810
  • Modified Q-Based Real Frequency Design of Narrowband Impedance Equalizer
           with Complex Terminations
    • Authors: Metin Şengül, Gökmen Yeşilyurt
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, real frequency design equations of narrowband impedance matching network with complex terminations are derived; which are used to design L, Pi and T type of networks. In the approach, there is no need to have termination models with component values, it is enough to have measurement values of termination impedances. A few examples are solved to exhibit the merits and application of the derived equations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-29T09:03:26Z
      DOI: 10.1142/S0218126619501834
  • An ENOB Evaluation Method for an Acquisition Channel
    • Authors: Xin Liu, Yan Liu, Zengshou Dong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Three-parameter and four-parameter sine-wave fitting algorithms are powerful tools for estimating the parameters of the excited single-tone sine-wave for ADC. In the dynamic performance testing processes of instruments, the angle frequency, amplitude, phase and dc component of the input sine-wave are all unknown, so the fitting procedure is nonlinear. This paper proposes and analyzes a test method based on iteration Interpolated Discrete Fourier Transform (IpDFT) and sine-wave fitting method for evaluating the effective number of bit (ENOB) of the acquisition channel. Mathematical expressions of the Least-square fitting residual error and the proposed ENOB evaluation based on iteration IpDFT method are derived. These expressions are then particularized for acquisition circuit output noise composed of single-tone and additive white noise. Simulation results show that the DFT-based golden section searching algorithm (DGSSA) is an effective algorithm under coherent and non-coherent sampling conditions. The accuracy of the derived expressions and estimated parameters are verified through both the computer simulations and experimental results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-29T09:03:25Z
      DOI: 10.1142/S0218126619501858
  • Synthesis of Fractional-Order Biquadratic Immittance Functions
    • Authors: Guishu Liang, Xiaoyan Huo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Passive network synthesis, as an important part of circuit and system theory, has been well developed in integer-order circuits. With the development of fractional-order calculus and fractional-order elements, the problem of using fractional-order passive networks to realize fractional-order immittance functions has drawn much attention. In this paper, the realization of a fractional-order biquadratic immittance function is considered. First, the form of a fractional-order biquadratic function and some theorems that could promote later research are introduced. Second, a detailed study for the realization of a fractional-order biquadratic immittance function is shown. Finally, through summarizing the realizability conditions of each network, we have obtained the scope of fractional biquadratic impedance functions that can be realized by this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-29T08:07:05Z
      DOI: 10.1142/S0218126619501871
  • A Full-Wave CMOS Rectifier with High-Speed Comparators for Implantable
           Medical Devices
    • Authors: Mahnaz Janipoor Deylamani, Fatemeh Abdi, Parviz Amiri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a CMOS full-wave rectifier with comparator-controlled switches for transmission of wireless power in implantable medical devices. It uses MOS transistors as low loss switches to provide high power conversion efficiency (PCE). The proposed fast comparator circuit, by controlling the switches in the rectifier, reduces the reverse leakage current in the negative cycle and increases the conduction time in the positive cycle so that more current flows into the output load and optimizes the rectifier power efficiency. The designed comparator does not require constant voltage source for its function and it is self-biased. The proposed rectifier is implemented using 0.18[math][math]m CMOS technology and provides 1.195[math]V output DC voltage with a 190[math][math] load resistance and AC input signal with the frequency of 13.56[math]MHz and peak-to-peak amplitude of 1.36[math]V. Under these conditions, PCE and voltage conversion efficiency (VCE) values are 85.5% and 88%, respectively. The peak PCE and VCE increase with a decrease in operation frequency and dimensions of transistors are optimized using multiple simulations for intended frequency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-29T08:07:05Z
      DOI: 10.1142/S0218126619501780
  • FLC and PWM SMC for KY Boost Converter
    • Authors: K. Ramash Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a design and implementation of fuzzy logic controller (FLC) plus PWM sliding mode controller (SMC) for 2nd order-d KY positive output voltage boost converter (KYPOVBC) operated in continuous inductor current mode (CICM). It is more suitable for steady power source in liquid crystal display (LCD), I-pad, CCTV camera, computer parts, light emitting diode (LED), renewable energy and industrial application. The 2nd order-d KYPOVBC always works in CICM and replica of synchronous rectification characteristics. The ON/OFF nature of the 2nd order-d KYPOVBC is nonlinear and their dynamic performance becomes poor. The classical linear controllers are noncapable of output voltage regulation of this converter during the high input supply voltage and load disparities. With the purpose of improving dynamic performance, an output voltage and inductor current regulation of the 2nd order-d KYPOVBC, a SMC plus FLC is designed. The state-space equations of the 2nd order-d KYPOVBC are arrived and then, SMC parameters are calculated. The FLC rules are framed according to the working nature of the 2nd order-d KYPOVBC without mathematical modeling, which is one of the major advantages of the FLC. The SMC acts as an inside loop of this converter to regulate the inductor current, whereas the FLC and proportional integral (PI) controllers act as an outside loop of the same converter for controlling the output voltage. The performance of the designed model is investigated at various operating regions by developing both the experimental and matrix laboratory (MATLAB)/simulation link (Simulink) models in comparison with the SMC plus PI controller. The results are presented to show the best performance of the designed model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-29T08:07:04Z
      DOI: 10.1142/S0218126619501846
  • Arbitrary Waveform Generators Using Current-Controlled Current Conveyor
           Transconductance Amplifier and Current Conveyor Analog Switches
    • Authors: Montree Kumngern, Thanat Nonthaputha, Fabian Khateb
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new amplitude modulation (AM), frequency modulation (FM), amplitude shift keying (ASK), frequency shift keying (FSK), phase shift keying (PSK) and quadrature amplitude modulation (QAM) waveform generators using current current-controlled conveyor transconductance amplifier (CCCTA) and current conveyor analog switches (CCASs). The CCCTA around with capacitors and resistors are used to generate high-frequency carrier which is worked as a quadrature oscillator. The oscillating frequency of oscillator can be controlled using the bias current of CCCTA, therefore FM and FSK waveforms can be obtained by applying information signal through the bias current of CCCTA. Unlike previous waveform generators, proposed circuit uses second generation current conveyor (CCII) to work as CCAS and AM, ASK, PSK and QAM waveforms can be obtained by putting information signals to control switches that realized using CCIIs. The proposed circuit has been simulated using 0.18[math][math]m CMOS [math]-well process from TSMC. The simulation results are used to confirm workability of the proposed circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-25T05:52:33Z
      DOI: 10.1142/S0218126619501792
  • Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for
           4 GHz–6.1 GHz Applications in 0.18 [math]m CMOS
    • Authors: Nitin Kumar, Manoj Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The differential ring voltage controlled oscillator (VCO) is one of the critical devices in wireless communication system having excellent stability, controllability and noise rejection ability. A novel design of delay cell is proposed for the four staged CMOS differential ring VCO with high output frequency, low power consumption and low phase noise. The differential ring VCO utilizes multiloop dual delay path topology to acquire both high output frequency and low phase noise. Results have been achieved in TSMC 0.18-[math]m CMOS process with a supply voltage ([math]) 1.8[math]V. The proposed design achieves an output frequency range of 4.029[math]GHz to 6.122[math]GHz and power of 4.475[math]mW is consumed with control voltage variation from 1[math]V to 2[math]V. The proposed VCO exhibits [math]89.7[math]dBc/Hz phase noise at 1[math]MHz offset frequency and the corresponding figure of merit (FoM) is [math]155.9[math]dBc/Hz. The design of differential ring VCO with novel delay stage has improved performance in terms of power consumption, output oscillation frequency and phase noise.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-25T05:52:33Z
      DOI: 10.1142/S0218126619501822
  • Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst
           Stuck-Open and Stuck-Closed Faults
    • Authors: Malay Kule, Hafizur Rahaman, Bhargab B. Bhattacharya
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We propose a technique for the analysis of manufacturing yield of nano-crossbar for the different values of defect percentage and crossbar-size. We provide an estimate of the minimum-size crossbar to be fabricated, wherein a defect-free crossbar of a given size can always be found with a guaranteed yield. Our technique is based on logical merging of two defective rows (or two columns) that emulate a defect-free row (or column). The proposed technique easily handles both the stuck-open and stuck-closed faults. Experimental results show that the proposed method provides higher defect-tolerance compared to that of previous techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-25T05:52:32Z
      DOI: 10.1142/S0218126619501809
  • Formal Modeling and Verifying the TTCAN Protocol from a Probabilistic
    • Authors: Xin Li, Jian Guo, Yongxin Zhao, Xiaoran Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The time-triggered CAN (TTCAN) protocol has been widely used in the automotive industry to fulfil the safety and real-time requirements of the application. As an extension of the standard CAN protocol, the TTCAN protocol aims to guarantee a safe and deterministic communication by introducing time-triggered messages with respect to a global synchronized time, which are scheduled in independent transmission windows within the system matrix. However, the new features bring more difficulties in designing and verifying the reliable applications in the TTCAN network. In this paper, we first present a formal probabilistic model of the TTCAN protocol with a consideration of its novel features. A TTCAN system consisting of three parts, i.e., a system matrix, an arbitration and some nodes, is modeled as discrete Markov chains model. Furthermore, five probabilistic properties are described and verified in the probabilistic model checker tool PRISM. Our work gives a quantitative analysis method for the given requirements, which facilitates the designers to a formal understanding of TTCAN protocol.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-24T02:52:37Z
      DOI: 10.1142/S0218126619501779
  • Improved Adaptive Wavelet Thresholding for Effective Speckle Noise
           Reduction in Low Contrast Medical Images
    • Authors: P. Sreelatha, M. Ezhilarasi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Informative images endure from poor contrast and noise during image acquisition. Significant information retrieval necessitates image contrast enhancement and removal of noise as a prerequisite before any further processing can be done. Dominant applications with low contrast images affected by speckle noise are medical ultrasound images. The objective of this work is to improve the effectiveness of the preprocessing stage in medical ultrasound images by enhancing the image while retaining its structural characteristics. For image enhancement, this work proposes to develop an automatic contrast enhancement technique using cumulative histogram equalization and gamma correction based on the image. For noise removal, this work proposes an algorithm Gamma Correction with Exponentially Adaptive Threshold (GCEAT) which suggests the use of GC for contrast enhancement along with a new wavelet-based adaptive soft thresholding technique for noise removal. The proposed GCEAT-based image de-noising is validated with other enhancement and noise removal techniques. Experimental results with low contrast synthetic and actual ultrasound images show that the suggested proposed system performs better than existing contrast enhancement techniques. Encouraging results were obtained with medical ultrasound images in terms of Peak-Signal to Noise Ratio (PSNR), Mean Square Error (MSE), Structural Similarity Index Measure (SSIM) and Average Intensity (AI).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-24T02:52:37Z
      DOI: 10.1142/S0218126619501767
  • A Novel Synchronous Current-Doubler Rectifier for LED Drivers Without
           Electrolytic Capacitors
    • Authors: Jianguang Ma, Xueye Wei, Liang Hu, Junhong Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High-brightness light-emitting diode (LED) lamps have attracted much attention because of their high efficiency, simple structure, energy conservation and environmental protection aspects, and long lifetime. Thus, an LED driver must have a long lifespan, high density, and compact space. However, conventional LED power supplies use an electrolytic capacitor as the storage capacitor in the holdup time, which has a short lifespan and occupies large space. In this paper, a novel synchronous current-doubler rectifier (SCDR) method is proposed as an LED driver. The reasonably designed circuit is used to control the output voltage ripple in the normal range without adding a complicated control circuit. The proposed topology is designed using few components, has no electrolytic capacitor, and has a low cost for high-output current LED driver applications. Circuit operating principles and detailed theoretical analysis are provided in this paper. A 200-W prototype has been established and tested, and the experimental results are presented to highlight the merits of the proposed circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-16T08:28:40Z
      DOI: 10.1142/S0218126619501755
  • Group Delay Equalization of Polynomial Recursive Digital Filters in
           Maximal Flat Sense
    • Authors: Negovan Stamenković, Nikola Stojanović, Goran Perinić
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The paper presents the development of an algorithm to obtain stable allpass filter, which acts as a group delay equalizer, with the aim to equalize group delay of the polynomial IIR filter in a maximal flat sense. The proposed method relies on a set of nonlinear equations, derived directly from the flatness conditions of the group delay response at the origin in the [math]-plane, with the order to obtain the unknown values of the allpass filter coefficients. The algorithm implemented in the MATLAB platform returns the coefficients of allpass filter. In the given example, first we construct a minimum phase polynomial IIR digital filter with a maximally flat magnitude at origin, next we augment the system with cascade connection of nonminimum allpass digital filter with order to equalize the group delay response of the whole filter in a maximally flat sense.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-16T08:28:38Z
      DOI: 10.1142/S0218126619501731
  • Design of a Low-Phase-Noise Ka-Band GaAs HBT VCO
    • Authors: Jincan Zhang, Min Liu, Liwen Zhang, Jinchan Wang, Bo Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the study of a Ka-band GaAs HBT VCO is reported with particular emphasis on achieving low-phase noise while using direct coupled varactor. A push–push cross-coupled VCO configuration is employed to achieve high oscillation frequency and low-phase noise. The measured oscillation bandwidth spans from 30.2 to 28.6[math]GHz with a tuning range of 1.6[math]GHz, while the phase noise at 1[math]MHz of frequency offset from the carrier at 29.3[math]GHz is [math][math]dBc/Hz. The VCO consumes 28.2[math]mW from 3[math]V supply and occupies an area of [math][math]mm. The FOM of the VCO achieves [math][math]dBc/Hz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-16T08:28:34Z
      DOI: 10.1142/S0218126619501743
  • An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New
           Segmented Structure
    • Authors: Mehdi Bandali, Alireza Hassanzadeh, Masoume Ghashghaie, Omid Hashemipour
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[math]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [math]-V supply voltage with the sample rate of 140[math]MS/s show SFDR [math] 64.37[math]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-12T04:13:11Z
      DOI: 10.1142/S021812661950172X
  • Power–Delay-Error-Efficient Approximate Adder for Error-Resilient
    • Authors: Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[math]18[math]J for 16-bit adder and 5.808E[math]18[math]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-11T01:50:25Z
      DOI: 10.1142/S0218126619501718
  • A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for
           Coherent Optical Receiver in 0.13-[math]m SiGe BiCMOS
    • Authors: Jiquan Li, Yingmei Chen, Pan Tang, Zhen Zhang, Hui Wang, Hao Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[math]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[math]m SiGe BiCMOS technology and it only occupies 1.05[math]mm[math][math][math]1.46[math]mm chip area. With a power consumption of 1.831[math]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[math]GS/s.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-10T01:16:35Z
      DOI: 10.1142/S0218126619501676
  • Design of High Efficiency Linear Power Amplifier with a Continuous
           Broadband Based on Two-Tone Signal Analysis
    • Authors: Chen Lu, Li Gun
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an innovative approach to achieve broadband linear power amplifier (PA) with a continuous broadband is presented. The proposed method mainly depends on the theory of control of intermodulation products and harmonics. This method results in a continuous sweet spots over a wide bandwidth. Based on the continuous sweet spots, a suboptimal solution is derived for improving the efficiency and linearity of broadband PAs. To verify the effectiveness of this method, one broadband PA operating over 4.5–5.5[math]GHz is developed and measured, it indicates that the peak output power of the PA is 35–57[math]dBm for a small signal input with a gain of 12[math]dB, and the peak drain efficiency (DE) of the PA is larger than 57% over the whole working band. However, when the PA is stimulated by a 5[math]MHz two-tone signal input, we observe that the DE keeps above 38% under the condition of the measured third-order intermodulation distortion (IMD3) is not larger than [math][math]dBc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-10T01:16:33Z
      DOI: 10.1142/S0218126619200068
  • Reliability Analysis of High Gain Integrated DC–DC Topologies for
           Xenon Lamp Applications
    • Authors: Divya Navamani, K. Vijayakumar, Jason Manoraj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Emerging switched-mode power supplies incorporated applications demand reliable, less volume and high efficient dc–dc converters. The persistent usage of the dc–dc converters in various applications makes their reliability a significant concern. Hence, this paper deals with a family of non-isolated high gain integrated dc–dc converter topologies derived from a quadratic converter. The reliability analysis is carried out using electronic equipment reliability handbook, MIL-HDBK-217F. For the first time, reliability prediction is done based on the working environment of the power electronic equipments. We developed the reliability prediction for the converters used in the lighting application such as automotive headlamp and aircraft landing lights. The mean time to failure for both the environment is calculated. The reliability comparison is carried out for the proposed topologies and the most reliable converter is chosen. Also, all the converter topologies are simulated using nL5 simulator to confirm their theoretical results. Finally, a laboratory prototype for 40 W with input voltage of 12 V is implemented for the most reliable topology to validate the steady-state analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-10T01:16:32Z
      DOI: 10.1142/S0218126619501688
  • Design and Analysis of a Broadband Current-Mode CMOS Direct-Conversion
           Receiver Frond-End Circuit
    • Authors: Xin Han Chen, Shuxiang Song, Mingcan Cen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A broadband (0.8–5[math]GHz) CMOS current-mode direct-conversion receiver has been integrated in a 0.18-[math]m CMOS process. The proposed receiver front-end features a broadband active-balun low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference, conversion gain and outstanding linearity. With the technique of noise and distortion cancellation which performs a better input impedance matching, we employ a broadband common-gate–common-source (CG–CS) LNTA and a current mirror to improve both gain and noise figure (NF) performance. Compared to the 50% duty-cycle switching stage, the 25% duty-cycle I–Q switching stage is implemented by using serial switches driven by 50% quadrature local oscillator (LO) signals separately, which improves the down-conversion gain by 3[math]dB and lowers the noise figure. The transimpedance amplifier employs the [math]-boosting technique to realize low input impedance and high transimpedance gain. The core circuit (RF and baseband signal path) consumes 26[math]mW, and the prototype receiver achieves approximately 33–34.5-dB conversion gain, 8.1–9.35-dB NF and 7.5–9.8-dBm IIP3 from 0.8[math]GHz to 5[math]GHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-10T01:16:31Z
      DOI: 10.1142/S021812661950169X
  • Design of a Tri-Band Doherty Amplifier Based on Generalized Impedance
    • Authors: Weimin Shi, Songbai He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces a methodology for implementing multi-band Doherty power amplifiers. Traditionally, a 90[math] impedance inverter line is required in Doherty architecture. In this contribution, a generalized impedance inverter line is utilized to construct multi-band Doherty power amplifiers. A tri-band Doherty power amplifier operating at 1.15, 1.85 and 2.55[math]GHz is designed to validate the proposed method. Measurement results show the fabricated Doherty power amplifier achieves 6[math]dB output back-off drain efficiencies of 62.3%, 49.3% and 50.5% at 1.15, 1.85 and 2.55[math]GHz, respectively. The peaking output power of the fabricated tri-band Doherty power amplifier is 43.2, 43.7 and 43.8[math]dBm with drain efficiencies of 64.5%, 62.2% and 64.5% at three working frequency points, respectively. Furthermore, when the designed Doherty power amplifier is driven by a 20[math]MHz wideband LTE signal with peak-to-average-power ratio of 6.4[math]dB, adjacent channel power ratios of [math]29.4 and [math]57.1[math]dBc are achieved before and after digital pre-distortion at 1.85[math]GHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-10T01:16:28Z
      DOI: 10.1142/S0218126619501706
  • Design and Implementation of Three-Winding Coupled Inductor and Switched
           Capacitor-Based DC–DC Converter Fed PV-TDVR
    • Authors: M. Kumar, S. Ramesh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a three-winding coupled inductor-based high-gain DC–DC converter fed transformerless dynamic voltage restorer (TDVR) to compensate the voltage sag, voltage swell and interruption in the single-phase power distribution network. The TDVR supported by the cascaded DC–DC boost converters offers high boosting gain. The cascaded connection of DC–DC converters reduces the efficiency due to the usage of more active and passive devices. The proposed PV-TDVR is designed to provide higher efficiency by reducing the number of power conversion stages with reduced numbers of active and passive components. The operating modes of the proposed PV-TDVR are presented in a comprehensive way. The MATrix LABoratory (MATLAB) simulation and 1-kV prototype model results are presented to analyze the performance of PV-TDVR in mitigating the voltage disturbances in the single-phase power distribution network.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-08T06:31:58Z
      DOI: 10.1142/S0218126619501585
  • Memristor Emulator Circuit Using Multiple-Output OTA and Its Experimental
    • Authors: Rajeev Kumar Ranjan, Pankaj Kumar Sharma, Sagar, Niranjan Raj, Bharti Kumari, Fabian Khateb
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A charge-controlled memristor emulator circuit based on one kind of active device [operational transconductance amplifier (OTA)] using CMOS technology is introduced in this paper. The proposed circuit can be configured in both incremental and decremental types by using a simple switch. The memristor behavior can be electronically tuned by adjusting the transconductance of the OTAs. By changing the value of the capacitor, the pinched hysteresis loop observed in the current versus voltage plane can be held at higher frequencies. The proposed emulator circuit functions well up to 500 kHz. The experiment has been performed using commercially available OTA ICs (CA3080). The experimental demonstration has been carried out for 10, 20 and 120[math]kHz. A simple high-pass filter is explained in both configurations to demonstrate the functionality of the proposed memristor emulator. The proposed circuit has been simulated in PSPICE using 0.5-[math]m CMOS parameter. The simulated and experimental results validate the theoretical proposition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-08T06:31:56Z
      DOI: 10.1142/S0218126619501664
  • A Start-up Assisted Fully Differential Folded Cascode Opamp
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, B. Yassine, S. Zourob, S. Raparthy, N. Yassine
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[math]dB, 250[math]MHz unity gain bandwidth amplifier has been developed in 65[math]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[math][math]A from a 1.2[math]V supply and occupies the 2184[math][math]m2 area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-08T06:31:56Z
      DOI: 10.1142/S0218126619501640
  • Formal Equivalence Checking Between System-Level and RTL Descriptions
           without Pre-Given Mapping Information
    • Authors: Jian Hu, Tun Li, Sikun Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-02T03:21:50Z
      DOI: 10.1142/S0218126619501639
  • A New Technique for Designing Low-Power High-Speed Domino Logic Circuits
           in FinFET Technology
    • Authors: Sandeep Garg, Tarun K. Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[math]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[math] higher compared to different existing techniques in FinFET SG mode and is 1.42–[math] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [math] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-02T03:21:50Z
      DOI: 10.1142/S0218126619501652
  • A Literature Review on Next Generation Graphene Interconnects
    • Authors: Nikita Patel, Yash Agrawal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-02T03:21:49Z
      DOI: 10.1142/S0218126619300083
  • Resistorless Frequency Locked On-Chip Oscillator with
           Proportional-to-Absolute Temperature References
    • Authors: Peiqing Han, Niansong Mei, Zhaofeng Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[math]m standard CMOS process with an active area of 0.072[math]mm2. The temperature coefficient of frequency is 48[math]ppm/[math]C at best and 82.5[math]ppm/[math]C on average over [math]–70[math]C and the frequency spread is 1.43% ([math]/[math] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[math]V to 1[math]V and the power consumption is 95[math]nW under the supply voltage of 0.65[math]V.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-02T03:21:48Z
      DOI: 10.1142/S0218126619501627
  • Two-Dimensional DOA Estimation for Planar Array Using a Successive
           Propagator Method
    • Authors: Weiyang Chen, Xiaofei Zhang, Chi Jiang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We consider the problem of two-dimensional (2D) direction of arrival (DOA) estimation for planar array, and propose a successive propagator method (PM)-based algorithm. The rotational invariance property of the propagator matrix is exploited to obtain the initial angle estimations, while the accurate estimates can be achieved through successive one-dimensional and local spectrum-peak searches. The proposed algorithm can obtain automatically paired 2D-DOA estimations, and it requires no eigenvalue decomposition of the covariance matrix of received data, which remarkably reduces the computational cost compared with traditional 2D-PM algorithm. In addition, the DOA estimation performance of the proposed algorithm is better than estimation of signal parameters via rotational invariance technique (ESPRIT) algorithm and PM algorithm, and is close to 2D-PM algorithm which requires 2D spectrum-peak search. Numerical simulations demonstrate the effectiveness and improvement of the proposed algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-01T03:45:07Z
      DOI: 10.1142/S0218126619501615
  • Energy Optimization Heuristics for Budget-Constrained Workflow in
           Heterogeneous Computing System
    • Authors: Junqiang Jiang, Wenbin Li, Li Pan, Bo Yang, Xin Peng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the rapid development of commercialized computation, the heterogeneous computing system (HCS) has evolved into a new method of service provisioning based on utility computing models, in which the users consume services and resources based on their quality of service requirements. In certain models using the pay-as-you-go concept, the users are charged for accessed services based on their usage. In addition, the commercialized HCS provider also assumes the responsibility to reduce the energy consumption to protect the environment. This paper considers a basic model known as directed acyclic graphs (DAG), which is designed for workflow applications, and investigates heuristics that allows the scheduling of various tasks of a workflow into the dynamic voltage and frequency scaling enabled HCS. The proposed approaches, which are Minimum-Cost-Up-to-Budget (MCUB) and Maximum-Cost-Down-to-Budget (MCDB), could not only satisfy budget constrains but could also optimize overall energy consumption. The approaches along with their variants are implemented and evaluated using four types of basic DAGs. From the experimental results, we conclude that MCDB outperforms MCUB in energy optimization and makespan criterion while meeting budget constraints faced by users.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-01T03:45:06Z
      DOI: 10.1142/S0218126619501597
  • Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail
           Dynamic Comparator with Reduced Kickback Noise Effect
    • Authors: Avaneesh K. Dubey, R. K. Nagaria
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[math]nm and 180[math]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[math]nm result shows that the comparator has the total delay as low as 104.3[math]ps and consumes only 0.288[math]fJ of energy per conversion from a 0.8[math]V supply. The mean value of input voltage error due to kickback noise is found as 306[math]nV.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-01T03:45:05Z
      DOI: 10.1142/S0218126619501573
  • The Classification of EEG Signals with Multi-Domain Fusion Based on D-S
           Evidence Theory
    • Authors: Rongxiang Ge, Jianzhong Hu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The classification of electroencephalogram (EEG) signals is a key technique of brain–computer interface (BCI) system. In view of the complexity of EEG signals and the low accuracy in EEG signals recognition, a motor imagery EEG signals classification method with multi-domain fusion based on Dempster–Shafer (D-S) evidence theory is presented in this paper. Firstly, time domain statistics (TDS), autoregressive (AR) model and discrete wavelet transform (DWT) are used to extract features from EEG signals, respectively, and three probabilistic output support vector machine (SVM) classification models are trained based on these three feature sets. Secondly, using the output of each SVM, we construct basic probability assignment (BPA) function and get fusion BPA through D-S evidence theory. Finally, determining the class of test samples based on decision rules. Four databases from BCI competition are employed to evaluate the proposed approach, and the highest classification accuracy reaches 92.83%. Results show that this method acquires higher accuracy and has strong individual adaptability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-10-01T03:45:04Z
      DOI: 10.1142/S0218126619501603
  • Parameter Space Exploration for Analog Circuit Design Using Enhanced Bee
           Colony Algorithm
    • Authors: Subhash Patel, Rajesh A Thakker
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, novel swarm optimization algorithm based on the Artificial Bee Colony (ABC) algorithm called Enhanced Artificial Bee Colony (EABC) algorithm is proposed for the design and optimization of the analog CMOS circuits. The new search strategies adopted improve overall performance of the proposed algorithm. The performance of EABC algorithm is compared with other competitive algorithms such as ABC, GABC (G-best Artificial Bee Colony Algorithm) and MABC (Modified Artificial Bee Colony Algorithm) by designing three CMOS circuits; Two-stage operational amplifier, low-voltage bulk driven OTA and second generation low-voltage current conveyor in 0.13 [math]m and 0.09[math][math]m CMOS technologies. The obtained results clearly indicate that the performance of EABC algorithm is better than other mentioned algorithms and it can be an effective approach for the automatic design of the analog CMOS circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-25T12:14:11Z
      DOI: 10.1142/S0218126619501536
  • All-Optical DFT Using TOAD-Based Cross-Bar Switches
    • Authors: Ashis Kumar Mandal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The discovery of ultra-high-speed all-optical switches in the very recent past based on semiconductor optical amplifier (SOA) especially in the interferometric configuration is very pronouncing due to their features like high repetition rate, low power consumption, fast switching time, noise and jitter tolerance, being easily integrable and operationally versatile, thereby bringing a revolution in all-optical information processing systems. In this work, an all-optical computing tool namely SOA-based [math] terahertz optical asymmetric demultiplexer (TOAD) is used because it can be employed to design more complex circuits and subsystems of enhanced combinational and sequential functionality. In this paper, (a) a switching network with its two switching actions and (b) an all-optical [math] cross-bar network architecture, i.e., a multistage cube network for [math] using TOAD-based [math] optical cross-bar switch for discrete Fourier transform (DFT), are proposed. Numerical simulation of this work is done with OptiSystem v7.0 to evaluate the performance of the proposed circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-25T12:14:11Z
      DOI: 10.1142/S0218126619501561
  • C-FDLA: Crow Search with Integrated Fractional Dragonfly Algorithm for
           Load Balancing in Cloud Computing Environments
    • Authors: C. Ashok Kumar, R. Vimala
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Cloud environment provides a shared pool of resources to various users all around the world. The cloud model has the physical machines and the virtual machines for processing the tasks from the users in a parallel manner. In certain situations, the user’s demand may be high, which leads to the overloading of the processing units, and this situation affects the performance of the cloud setup. Several works have introduced the load balancing strategy to balance the load of the cloud environment, but they lack in the ability to reduce the number of task migrations. This paper introduces the load balancing strategy by defining the optimization algorithm and the multi-objective model. This research introduces the Crow search with the integrated Fractional Dragonfly Algorithm (C-FDLA), for load balancing through the hybridization of the Crow Search Algorithm (CSA), Dragonfly Algorithm (DA) and the fractional calculus. Also, the paper uses the multi-objective model based on selection probabilities, the frequency scaling based capacity of the machine and the data length of the task. The performance of the proposed C-FDLA is analyzed under different cloud scenarios, and from the results, it is evident that the proposed work has achieved significant performance with the minimum load of 0.0913 and number of tasks reallocated as 11.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-25T12:14:10Z
      DOI: 10.1142/S0218126619501159
  • A Self-Powered P-SSHI Interface Circuit with Adaptive On-Resistance Active
           Diode for PEH
    • Authors: Lianxi Liu, Jiangwei Cheng, Junchao Mu, Chaojin Huang, Zhangming Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a two-stage synchronous rectifier interface circuit for piezoelectric energy harvesting (PEH) system. The proposed rectifier includes a first-stage negative voltage converter, a second-stage adaptive on-resistance active diode, and combines a precise switch-on-time controlled P-SSHI circuit. The traditional active two-stage synchronous rectifier has lower current detection accuracy and hardly achieves high efficiency rectification over a wide input current range. An adaptive on-resistance active diode (AOR active diode) is proposed to replace the traditional active diode to achieve higher current zero-crossing detection accuracy, improve the input current range and the output power of the rectifier. The proposed diode allows the rectifier to maintain high rectification efficiency over a wider input current range. Further, a parallel synchronized switch harvesting on inductor (P-SSHI) with precise switch-on-time controlled circuit is proposed to achieve higher voltage flipping efficiency and improve the power extraction capability of the rectifier. By using the AOR active diode and the P-SSHI with precise switch-on-time controlled circuit, a good performance improvement has been achieved for the proposed interface circuit. The design is fabricated in an SMIC 0.35[math][math]m standard CMOS technology with a die size of [math][math]mm2. The simulation results indicate that the proposed circuit achieves more than 80% power converting efficiency and its peak efficiency is 85%. The current zero-crossing detection accuracy of the proposed AOR active diode is less than 10[math][math]A. The proposed PEH interface circuit extracts up to 2.81 times more output power compared with a traditional rectifier. The voltage flipping efficiency of the P-SSHI circuit is up to 90%, which can effectively improve the power extraction capability of the rectifier. Moreover, the proposed circuit can be self-powered and cold started up.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-25T12:14:09Z
      DOI: 10.1142/S021812661950155X
  • Optimal Power Flow-Based Combined Economic and Emission Dispatch Problems
           Using Hybrid PSGWO Algorithm
    • Authors: C. R. Edwin Selva Rex, M. Marsaline Beno, J. Annrose
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new and efficient hybrid approach combining two meta-heuristic methods for solving economic and emission dispatch problems. We used particle swarm optimization (PSO)-based gray wolf optimization to solve this problem. Additionally, the nonlinear control parameter is employed to balance the global search and local search ability of the algorithm and improve the convergence speed of the algorithm. At the same time, the idea of PSO is introduced, which utilizes the best value of the individual and the best value of the wolf pack to update the position information of each gray wolf. This method preserves the best position information of the individual and avoids the algorithm falling into a local optimum. The optimal power flow (OPF)-based CEED problem is formulated with the combination of fuel cost, fuel emission with penalty function, real power loss and voltage deviation. The proposed approach is implemented in MATLAB working platform and tested by IEEE 30 bus system with different test cases. Moreover, the CEED problem-solving performance of PSGWO algorithm is examined by 3-unit, 6-unit and 40-unit test systems. Then, the obtained results are compared with conventional methods to highlight the benefits of the proposed algorithm in reducing the fuel cost, fuel emission, voltage deviation and power losses, respectively. The experimental results show that the proposed approach provides accurate solutions for all types of objective solutions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-24T05:53:05Z
      DOI: 10.1142/S0218126619501548
  • Stochastic Delay Characterization for Multicoupled RLC Interconnects Under
           Process Variations
    • Authors: Jin Sun, Xin Li, Zhichao Lian, Min Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The characterization of interconnect delay metrics in terms of process variations is an important but complicated task for statistical timing analysis in today’s integrated circuits (ICs). This paper presents a stochastic delay characterization framework for multicoupled interconnects in the presence of process variation. The proposed method starts with deriving the stochastic nodal equations for the RLC network that models multicoupled interconnects. By employing polynomial chaos (PC) expansion, a nonsampling-based stochastic prediction method, we further represent the voltage responses of network nodes as a series of orthogonal polynomials of random variables. During the expansion procedure, we use an adaptive approximation algorithm to reduce the number of required sampling points. We then use a stochastic collocation method to estimate the coefficients in the PC expansion model. With the voltage response determined as an expression of a multi-dimensional polynomial of random variables, the stochastic properties of the delay of multicoupled interconnects can be predicted. The proposed method not only takes into account the strong correlations among process variations, but also extracts an explicit delay representation for multicoupled interconnects in terms of process variations. Experimental results demonstrate that the delay characteristics predicted by the proposed method match well with the results by the brute-force Monte-Carlo method. Moreover, a significant speedup over the Monte-Carlo method has been achieved by the proposed delay characterization framework.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-21T02:21:08Z
      DOI: 10.1142/S0218126619501524
  • Construction of Higher-Dimensional Hyperchaotic Systems with a Maximum
           Number of Positive Lyapunov Exponents under Average Eigenvalue Criteria
    • Authors: Jianbin He, Simin Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Over the last 40 years, the design of [math]-dimensional hyperchaotic systems with a maximum number ([math]) of positive Lyapunov exponents has been an open problem for research. Nowadays it is not difficult to design [math]-dimensional hyperchaotic systems with less than ([math]) positive Lyapunov exponents, but it is still extremely difficult to design an [math]-dimensional hyperchaotic system with the maximum number ([math]) of positive Lyapunov exponents. This paper aims to resolve this challenging problem by developing a chaotification approach using average eigenvalue criteria. The approach consists of four steps: (i) a globally bounded controlled system is designed based on an asymptotically stable nominal system with a uniformly bounded controller; (ii) a closed-loop pole assignment technique is utilized to ensure that the numbers of eigenvalues with positive real parts of the controlled system be equal to ([math]) and ([math]), respectively, at two saddle-focus equilibrium points; (iii) the number of average eigenvalues with positive real parts is ensured to be equal to ([math]) for the controlled system over a given control period; (iv) the smallest value of the positive real parts of the average eigenvalues is ensured to be greater than a given threshold value. Finally, the paper is closed with some typical examples which illustrate the feasibility and performance of the proposed design methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-20T03:10:23Z
      DOI: 10.1142/S0218126619501512
  • A Markov Prediction-Based Privacy Protection Scheme for Continuous Query
    • Authors: Lei Zhang, Jing Li, Songtao Yang, Yi Liu, Xu Zhang, Yue Sun
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The query probability of a location which the user utilizes to request location-based service (LBS) can be used as background knowledge to infer the real location, and then the adversary may invade the privacy of this user. In order to cope with this type of attack, several algorithms had provided query probability anonymity for location privacy protection. However, these algorithms are all efficient just for snapshot query, and simply applying them in the continuous query may bring hazards. Especially that, continuous anonymous locations which provide query probability anonymity in continuous anonymity are incapable of being linked into anonymous trajectories, and then the adversary can identify the real trajectory as well as the real location of each query. In this paper, the query probability anonymity and anonymous locations linkable are considered simultaneously, then based on the Markov prediction, we provide an anonymous location prediction scheme. This scheme can cope with the shortage of the existing algorithms of query probability anonymity in continuous anonymity locations difficult to be linked, and provide query probability anonymity service for the whole process of continuous query, so this scheme can be used to resist the attack of both of statistical attack as well as the infer attack of the linkable. At last, in order to demonstrate the capability of privacy protection in continuous query and the efficiency of algorithm execution, this paper utilizes the security analysis and experimental evaluation to further confirm the performance, and then the process of mathematical proof as well as experimental results are shown.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-17T02:42:23Z
      DOI: 10.1142/S0218126619501470
  • Aging-Aware Task Scheduling for Mesh-Based Network-on-Chips Under Aging
    • Authors: Jinbin Tu, Tianhao Yang, Lu Yin, Shuangyu Xie, Ruitao Xu, Jin Sun
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aging effect induced by negative bias temperature instability (NBTI) is a universal issue existing in electronic equipments. NBTI aging effect can increase the path delay of network-on-chip (NoC) device, resulting in the decreased frequency of processor core and in turn its performance degradation. Under this circumstance, aging-aware task scheduling becomes a complex and challenging problem in advanced multicore systems. This paper presents an aging-aware scheduling method that incorporates NBTI aging effect into the task scheduling framework for mesh-based NoCs. The proposed method relies on a NBTI aging model to evaluate the degradation of core’s operating frequency to establish the task scheduling model under aging effect. Taking into account core performance degradation and the communication overheads among cores, we develop a meta-heuristic scheduling strategy based on particle swarm optimization algorithm to minimize the total execution time of all tasks. Experimental results show that the schedule obtained by the aging-aware algorithm has shorter completion time and higher throughput compared with the nonaging-aware case. On average, the makespan can be reduced by 13.55% and the throughput can be increased by 21.73% for a variety of benchmark applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-17T02:42:22Z
      DOI: 10.1142/S0218126619501469
  • Cellular Automata Based Test Design for Coherence Verification in 3D
    • Authors: Bidesh Chakraborty, Mamata Dalui, Biplab K. Sikdar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensures high speed cache memory access. Maintaining coherency of shared data in such caches is, however, very crucial and, therefore, demands that the reliability and accuracy of TSVs as well as the cache coherence controller (CC) are to be ensured. In the current work, we propose an elegant test solution for at-speed detection of stuck-at-faults in TSVs (offline test) as well as verification for the functioning of CC (online test). The proposed test structure is designed around the modular and cascadable structure of Cellular Automata (CA) to achieve a cost-effective realization of test and coherence verification in 3D caches with high degree of scalability. It ensures correct decisions in more than 71% cases even if the test hardware is subjected to single stuck-at-fault.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-07T08:20:16Z
      DOI: 10.1142/S0218126619501482
  • Makespan Minimization for Multiprocessor Real-Time Systems under Thermal
           and Timing Constraints
    • Authors: Jing Hua, Yingqiong Peng, Yilu Xu, Kun Cao, Jing Jia
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the continued scaling of the CMOS device, the exponential increase in power density has strikingly elevated the temperature of on-chip systems. In this paper, the problem of allocating and scheduling frame-based real-time applications is addressed to multiprocessors to minimize the makespan under the thermal and timing constraints. The proposed algorithms consist of offline and online components. The offline component assigns the applications accepted at static time to processors in a way that the finish time of processors are balanced. The online component firstly selects the processor with the highest allocation probability for each application accepted at runtime. The allocation probability is calculated by taking the processor workload and temperature profiles into consideration. The higher allocation probability of a processor shows the better performance with respect to makespan and temperature can be achieved by executing the application on this processor. Then, the operating frequencies of applications are determined by making the most of slack in order to reduce the peak temperature under the timing constraint. Extensive simulations were performed to validate the effectiveness of the proposed approach. Experimental results have shown that the static makespan of the proposed scheme is very close to the optimal schedule length within a small margin varying from 0.118[math]s to 0.249[math]s, and the dynamic makespan of the proposed scheme can be adapted to satisfy varying system design constraints. The peak temperature of the proposed algorithms can be up to [math] lower than that of the benchmarking schemes.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-07T08:20:15Z
      DOI: 10.1142/S0218126619501457
  • Efficient Lightweight Hardware Structures of Point Multiplication on
           Binary Edwards Curves for Elliptic Curve Cryptosystems
    • Authors: Bahram Rashidi, Mohammad Abedini
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of 5M + 4S + 2D and 5M + 4S + 1D for general and special cases of BECs, respectively, where M,S and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [math] and [math] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-07T08:20:15Z
      DOI: 10.1142/S0218126619501494
  • De-Speckling of Ultrasound Images Using Local Statistics-Based Trilateral
    • Authors: S. Jayanthi Sree, C. Vasanthanayaki
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Speckle noise in ultrasound images is a major hindrance for the automation of segmentation, detection, classification and measurements of region of interest, to assist clinician for diagnosing pathologies. Speckle noise occurs due to constructive and destructive interference of the echo signals reflected from the target and has a granular appearance. Various techniques have been devised for speckle reduction. Most of these techniques are based on adaptive filters, wavelet transform and anisotropic diffusion filters. In this paper, a new speckle reduction technique based on the trilateral filter and local statistics of the image has been developed. The local speckle content of the image influences the trilateral filtering. The trilateral filter is a robust edge preserving filter which considers the similarity of neighboring regions in terms of adjacency, intensity and edge details. Hence, the new method preserves the finer details of the ultrasound images in the process of filtering speckle noise. The proposed technique is validated using synthetic, simulated and real-time clinical ultrasound images. Comparison of the proposed technique with the existing speckle removal algorithms in terms of quality metrics such as MSE, PSNR, UQI, SSI, FoM has been made and best results are obtained for the proposed technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-07T08:20:14Z
      DOI: 10.1142/S0218126619501500
  • High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk
           Driven Flipped Voltage Follower Cell
    • Authors: Caffey, Rishikesh Pandey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[math]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[math]M[math], wide bandwidth of 239.245[math]MHz and low power dissipation of 104[math][math]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[math]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-07T03:47:04Z
      DOI: 10.1142/S0218126619501408
  • Realization of Resistorless and Electronically Tunable Inverse Filters
           Using VDTA
    • Authors: Praveen Kumar, Neeta Pandey, Sajal K. Paul
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents resistorless realization of inverse filters using voltage differencing transconductance amplifier (VDTA). First, four topologies are proposed which provide inverse low-pass, high-pass, band-pass, and band-reject responses. Subsequently, a unified inverse filter is also derived by incorporating two switches in the combination of proposed inverse low-pass and inverse band-pass topologies. This topology is capable of providing inverse low-pass, inverse high-pass, inverse band-pass, and inverse band-reject responses by appropriate switch settings. The proposed inverse filter structures are electronically tunable and use only grounded capacitors. The behavior of the proposed filters is also investigated for nonidealities. To verify the functionality of the proposed inverse filter circuits, SPICE simulation is carried out using 0.18-[math]m CMOS technology parameters from TSMC. The effect of deviation in the active and passive component values on angular frequency is tested through Monte Carlo simulation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-07T03:47:04Z
      DOI: 10.1142/S0218126619501433
  • Hierarchical Request-Size-Aware Flash Translation Layer Based on
           Page-Level Mapping
    • Authors: Dong Bin Yeo, Joon-Yong Paik, Tae-Sun Chung
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Owing to the increasing Internet population, there has been an explosion in the amount of digital data generated and also an increase in data complexity. This trend is called big data paradigm. As the Internet of Things (IoT) takes center stage, the growth of data will continue to increase. Therefore, the demand for mass storage devices that have high access speed is increasing. Industry has been paying attention to flash memories that can process large amounts of data at high speed. It will be a good alternative for storing and processing ever-increasing amounts of data because of low power consumption, high shock resistance, portability and fast access speed. However, the write speed is about 10–20 times slower than the read speed in flash memory. In addition, write operations are not allowed to be performed with in-place updates. Garbage collection mechanism is proposed in order to solve the problem incurred by the not-in-place update property of write operations. However, garbage collection mechanism unavoidably causes overhead of additional internal operations, which leads to performance degradation. In this paper, to prevent performance degradation caused by garbage collection, we propose a request-size-aware flash translation layer (RSaFTL) and a hierarchical request-size-aware flash translation layer (HiRSaFTL). They are designed based on page-level address translation. In RSaFTL and HiRSaFTL, page-sized data with high temporal locality cluster into a special area called active blocks by exploiting the property of realistic traces. As a result of the experiments, RSaFTL and HiRSaFTL reduce the number of pages migrated during garbage collections by up to 17.9% and 21.3%, respectively, compared with pure page-level flash transition layer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-06T07:28:22Z
      DOI: 10.1142/S0218126619501172
  • Thermal-Aware Partitioning and Encoding of Power-Gated FSM
    • Authors: Priyanka Choudhury, Kanchan Manna, Vivek Rai, Sambhu Nath Pradhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Miniaturization and the continued scaling of CMOS technology leads to the high-power dissipation and ever-increasing power densities. One of the major challenges for the designer at all design levels is the temperature management, particularly the local hot spots along with power dissipation. In this work, the controller circuits which are implemented as Finite State Machines (FSMs) are considered for their thermal-aware and power-aware realization. Using Genetic Algorithm (GA), both encoding and bipartitioning of the FSM circuit are implemented to get two subFSMs such that at a particular instant of time, one subFSM is active at a time, whereas the other one is power-gated. Again, thermal-aware realization (in terms of power-density) of this power-gated FSM is done. Therefore, the work concerns with the thermal-aware encoding and partitioning of FSM for its power-gated realization. Average temperature saving obtained in this approach for a set of benchmark circuits over previous works is more than 16%. After getting the final partitioned circuit which is optimized in terms of Area and power-density, thermal analysis of the sunFSMs is performed to get the absolute temperature. As thermal-aware design may increase the area, a suitable area-temperature trade-off is also presented in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-03T06:43:23Z
      DOI: 10.1142/S0218126619501445
  • A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End
           in 65[math]nm CMOS Technology
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, A. A. Tammam, N. Yassine, B. Yassine, M. Ben-Esmael
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a fully integrated front-end, low noise amplifier (LNA), dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input-referred noise of the LNA, without adding any additional power. The proposed technique implemented in 65[math]nm CMOS technology achieves 30 dB closed-loop voltage gain, 0.05[math]Hz lower cut-off frequency and 100 MHz 3-dB bandwidth. It operates at 1.2[math]V power supply and draws 1[math][math]A static current. The prototype described in this paper occupies 3300[math][math]m2 silicon area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-03T06:43:23Z
      DOI: 10.1142/S0218126619501378
  • Global Image Dehazing via Frequency Perception Filtering
    • Authors: Linli Xu, Jing Han, Tian Wang, Lianfa Bai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In outdoor scenes, haze limits the visibility of images, and degrades people’s judgement of the objects. In this paper, based on an assumption of human visual perception in frequency domain, a novel image haze removal filtering is proposed. Combining this assumption with the theory of frequency domain filtering, we first estimate the cut-off frequency to divide the frequency domain of the hazy image into three components — low-frequency domain, intermediate-frequency domain and high-frequency domain. Then, by introducing the weighting factors, the three components are recombined together. After the theoretical deduction of frequency domain, the establishment of the actual model and adjusting the cut-off frequency and weighting factors, we finally acquire a global and adaptive filtering. This filtering can restore the details and the contours of the images, which have less noise, and improve the visibility of the objects in hazy images. Moreover, our method is simple in structure and strongly applicable, and rarely affected by parameters. Our algorithm is stable and performs well in heavy fog and the scene changes.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-09-03T06:43:22Z
      DOI: 10.1142/S0218126619501421
  • Self-Crossing Memristive Pinched Hystereses in Autonomous Implicit Models
    • Authors: Wieslaw Marszalek
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper shows that autonomous implicit ODEs (based on planar lemniscates) are interesting models, yielding pinched self-crossing hystereses that are intrinsic features of all memristive elements in nanoscale electronics. Each model has a folded saddle that allows for an oscillating trajectory to traverse different sides of singularity. The models considered in this paper are autonomous and therefore different from typical input–state–output models considered thus far. The models preserve the usual properties of memristive elements. For example, the area enclosed by the pinched hystereses decreases with the increased frequency of oscillations. The same-time instant zero-crossing property is also satisfied provided that certain conditions are met. Another novel aspect of this paper is the fact that the autonomous models are based on various planar lemniscates (of Gerono, Devil and Bernoulli) which can be nonlinearly transformed to model pinched hystereses of various shapes. The proposed models are differentiable and the use of the sign and absolute value terms, typical in modeling of memristive elements, is avoided. Several simulation results are included and two simple analog circuits having the pinched hysteretic characteristics of mem-inductors and mem-capacitors are proposed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-31T09:13:12Z
      DOI: 10.1142/S0218126619501391
  • Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on
           Quantum-Dot Cellular Automata
    • Authors: Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng, Guangjun Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently reported quantum-dot cellular automata (QCA) exclusive-OR gate designs are usually made with the AND–OR–INVERTER method in which it is difficult to optimize the XOR gate. This paper presents a novel low-power exclusive-OR (XOR) gate which is mainly based on cell-level format. Compared with the previous XOR gates, the proposed XOR gate performs in a different manner. This XOR gate design is accomplished by the intercellular effects method. For better performance comparison with previous relevant works, 4-, 8-, 16- and 32-bit parity generators are implemented in this paper. The simulation results show that there is a reduction of 32.5% cell count and 21.5% area in comparison with the existing advanced 32-bit parity generator. Especially in the aspect of clock cycle, the proposed design reduces the delay by 50% compared to the previous design. For simulation analysis, QCADesigner tool is used to verify the correctness of the proposed design. QCApro tool is used to evaluate the power dissipation of this design.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-31T09:13:11Z
      DOI: 10.1142/S021812661950141X
  • A New Analysis Way of Three-Phase Switched Capacitor Converter
    • Authors: WangLok Do, Farzin Asadi, Kei Eguchi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The paper presents the theoretical analysis way of the switched capacitor converter (SCC). The main goal of this research is to suggest the analysis way of three-phase SCC. A common SCC operates by two phases; charging phase and discharging phase. Therefore, state-space averaging model or slow and fast switching limit (S-FSL) model has been suitable. Although the four-terminal equivalent model can cover all situation including three-phases cases, this model does not include the parameter of frequency and capacitance. Therefore, the four-terminal model has a weakness. In this situation, we selected the Fibonacci sequence SCC operated by three-phase as the target circuit, which topology has been proved to have higher efficiency, small size in the previous research. In the paper, we suggest the new analysis way of the three-phase SCC by combination of the four-terminal equivalent model and RC circuit model from each loop equation of the equivalent circuits of the SCC. By using the suggested way, it is possible to analyze the three-phase SCC, deriving the effect of the load, operation frequency and duty ratio variation. In order to verify the feasibility and the cogency of the suggested analysis way, comparative analysis is implemented by SPICE simulations. The error in the load regulation between the suggested way and the simulation result is negligible. Through this result, we establish the foundation of the analysis of the three-phase SCC.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-24T09:55:05Z
      DOI: 10.1142/S021812661950138X
  • Improved MB Cognitive Radio Spectrum Sensing Using Wavelet Spectrum
    • Authors: Ricardo Tadashi Kobayashi, Aislan Gabriel Hernandes, Mario Lemes Proença, Taufik Abrao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In cognitive radio (CR), the sensed aggregate bandwidth could be as large as several GHz. This is especially challenging if the bandwidths and central frequencies of the sensed signals are unknown and need to be estimated. This work discusses a new improved method for MB spectrum sensing (iMB-SS) based on edge detection and using Wavelet Spectrum Filtering. The proposed iMB-SS method uses a Welch power spectrum density (PSD) estimate and a multi-scale Wavelet approach to reveal the spectrum transition (edges), which is deployed to characterize the spectrum occupancy in CR scenarios where the operation frequencies of the primary users (PUs) are unknown. The focus of this work lies in improving the performance of the MB spectrum sensor, particularly by refining the spectral edge location and reducing misleading detection. A comprehensive analytical description and numerical analysis have been carried out by focusing on orthogonal-frequency-division-multiplexing (OFDM) signal applications in CR networks. Numerical results corroborate the effectiveness of the proposed iMB-SS approach. The simulated results for the multiple-PU’s OFDM-based transmission CR system demonstrate that the proposed iMB-SS method can achieve high performance even under low signal-to-noise ratio (SNR) regime, turning it out as an attractive choice for SS in the MB CR systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-24T09:55:04Z
      DOI: 10.1142/S0218126619501366
  • Grid Interconnection of Renewable Energy Sources Using Unified Power
           Quality Conditioner: A Fuzzy Logic-Based Approach
    • Authors: T. Vigneysh, N. Kumarappan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes distributed generation-integrated unified power quality conditioner (UPQC-DG) with adaptive fuzzy proportional–integral (AFPI) controller to improve the power quality (PQ) of a distribution network. In the proposed system, the DG units are integrated at dc-link of the UPQC to provide additional functionalities. The additional functionalities which are unique to the proposed system is to (i) export the available active power from renewable energy sources to the grid, (ii) compensate long term PQ problems, (iii) compensate voltage interruption. Additionally, the dc-link voltage of the system is controlled by using the proposed AFPI controller to effectively improve the dynamic performance of the system during disturbances. Unlike conventional PI controller, in the proposed controller, the gains are not fixed. It is dynamically adjusted by the fuzzy logic-based intelligent supervisory control system according to system operating conditions. The effectiveness of the proposed system is verified using extensive simulation studies and necessary results are compared with the existing literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-24T09:55:04Z
      DOI: 10.1142/S0218126619501354
  • Digital Estimation and Compensation of Analog Errors in
           Frequency-Interleaved ADCs
    • Authors: Jinpeng Song, Shulin Tian, Yu-Hen Hu, Peng Ye, Kuojun Yang, Lianping Guo, Wentao Wei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel digital compensation scheme for measuring, estimating and correcting linear weakly time-varying analog errors in frequency-interleaved analog-to-digital converters (FI-ADCs) is presented. This method features three important improvements over existing approaches: First, the Wigner–Ville distribution (WVD) is used to better estimate the nonstationary analog channel frequency response (ACFR) spectrum. Secondly, the estimated ACFR spectrum is approximated with a rational polynomial model using the [math]-norm metric. The corresponding [math]-norm minimization problem is solved using a primal-relaxed dual global optimization (PRD-GOP) method. Thirdly, the digital compensation circuitry is designed utilizing a preconditioned biconjugate gradient stabilized (BICGSTAB) algorithm that yields a computationally efficient solution. Numerical experimentations have been conducted and the outcomes validate the feasibility and superior performance of this proposed method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T07:07:29Z
      DOI: 10.1142/S0218126619501342
  • Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs
    • Authors: Alexander Barkalov, Larysa Titarenko, Sławomir Chmielewski
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T07:07:28Z
      DOI: 10.1142/S0218126619501317
  • Developing an Offline Persian Automatic Lip Reader as a New Human–Mobile
           Interaction Method in Android Smart Phones
    • Authors: Fatemeh Sadat Lesani, Faranak Fotouhi Ghazvini, Rouhollah Dianat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new method to communicate with mobile phones is introduced. A camera phone can track the user’s lip motions using the lip reading algorithms. They recognize the words and sentences to run the appropriate application automatically. However, two of the challenges when implementing these algorithms in mobile phones are the changing ambient’s light and the limited resources such as memory and CPU. In this research, two methods are introduced to solve these problems. An offline lip reading application is implemented for Android phones which tracks the user’s lips in the Persian language. The application recognizes Persian words using visual features extraction from the user’s lips. The significance of this paper lies in the fact that it reports one of the first systems ever developed for offline lip reading. The whole process takes place completely on the device without the support of a dedicated server for the execution of the algorithms. In addition, this research is one of the first studies conducted on Persian mobile lip reading systems. Finally, the application was tested by disabled people who suffer from hand disabilities. The application satisfied them more than other applications which use sound, touch or text as an interface.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T07:07:27Z
      DOI: 10.1142/S0218126619501329
  • An Efficient Clock Generation Algorithm for System-on-Chip Based on Least
           Common Multiple
    • Authors: Nesrine Toubaline, Mahdoum Ali, Djamel Bennouar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Current networks-on-chip (NoCs) may include many Intellectual Properties (IPs). As those IPs do not necessarily operate at the same clock frequency, a significant number of Phase Locked Loops (PLLs) are required. Since a PLL is very power consuming ([math], a PLL delivering a 6 GHz frequency consumes 11[math]mW), one needs to reduce the number of PLLs. To the best of our knowledge, only one work in literature tackled this problem. Since the interested problem is not polynomial in time, we developed heuristic-based methods and found that our work outperforms that which is described in the literature both in terms of number 30% and power consumption 25% of PLLs with less CPU time.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T01:12:43Z
      DOI: 10.1142/S0218126619501287
  • Design and Implementation of Stereoscopic Image Generation
    • Authors: Chi-Chou Kao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we proposed the design and implementation of a new stereoscopic image generation system. In the conventional system, the smoothness of depth map can reduce the incidence of image holes, but cause geometric distortions of the image depth. To solve the problems, the depth map is first refined to increase the accuracy of image depth and the quality of images. Next, we derive a hardware-oriented method for 3D warping and improve hole-filling procedures to enhance the performance of image. Finally, the circuit design is presented according to the proposed stereoscopic image generation system to achieve real-time applications. The experimental results demonstrate that the proposed system can improve by 10–27% when compared to existing methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T01:12:42Z
      DOI: 10.1142/S0218126619501330
  • Implementation of Face Recognition Algorithm on Field Programmable Gate
           Array (FPGA)
    • Authors: Tijana Šušteršič, Aleksandar Peulić
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The aim of this study is to implement an algorithm for face recognition, based on fast fourier transform (FFT), on the field programmable gate array (FPGA) chip. Implemented program included the initialization process of two single-IP-core ROM blocks, each with an image of a human face, which are sent to the real components of two-channel IP CoreFFT block. The result of classification could be displayed in the form of either a word “yes” or “no” on the seven-segment display or the information about the reference to the folder with the found match face. Due to the lack of memory on the chip, the results are discussed based on the results obtained by the simulation, whilst the implemented part of the system included displaying images on VGA monitor and result of the algorithm shown on seven-segment display or realized as a software solution in Matlab. The results show 79% accuracy and the advantage of presented system lies in the possibility of working with images in real time. The results obtained in this study can be a good starting point in the implementation of complex algorithms for face recognition using all the benefits that FPGAs offer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T01:12:42Z
      DOI: 10.1142/S0218126619501299
  • Design of a Hybrid Accumulator Architecture for Harvesting and Storing of
           Power in WSN using an Adaptive Power Organizing Algorithm
    • Authors: R. Senthilkumar, G. M. Tamilselvan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Converting the harnessed energy from the environment or other energy sources to electrical energy is referred to as energy harvesting. The need of energy harvesting in wireless sensor networks is an essential issue to be handled to allow adequacy of the innovation in a wide range of utilizations. The maximum energy should be harvested from the solar panels and it should be stored and managed effectively to power the nodes in the wireless network. For this purpose, a solution proposed in this paper utilizes a hybrid accumulator architecture that combines the advantages of an effectively controlled “battery and ultra-capacitor (UC)” where the power stream from a lithium ion (Li-ion) battery is combined with a UC for power upgrade and conveyance to the stack proficiently and using a new adaptive power organizing algorithm, management of power in the battery and capacitor can be performed. The proposed design is implemented in Simulink and the results show the effect of the hybrid design.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-21T01:12:40Z
      DOI: 10.1142/S0218126619501305
  • A Residue-to-Binary Converter with an Adjustable Structure for an Extended
           RNS Three-Moduli Set
    • Authors: Ahmad Hiasat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In earlier publications, many researchers have addressed the problem of residue-to-binary conversion for the popular moduli set [math], where [math] is a positive integer greater than 1. In this paper, we are proposing, potentially, the fastest converter ever for this moduli set with the least hardware requirements. Moreover, the paper revisits the extended three-moduli set [math], where [math] is a positive integer such that [math]. This paper proposes an efficient residue-to-binary converter with an adjustable structure. The proposed structure allows increasing the dynamic range at a cost of two gates per bit. When compared with a similar published work for the extended moduli set, the proposed extended converter showed significant reductions in area by 9.9–13.4%, in delay by 16.9–24.1% and in power consumption by 10.6–16.7%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-13T09:40:07Z
      DOI: 10.1142/S0218126619501263
  • Design of Broadband LNA Using Improved Self-Bias Architecture
    • Authors: Tian Qi, Songbai He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A broadband low-noise amplifier (LNA) using 0.13[math][math]m GaAs HEMT technology for Ku-band applications is presented in this paper. By introducing an improved self-bias architecture, the LNA is achieved with low noise figure (NF) and high power gain. Compared with traditional LNA, self-bias architecture can reduce DC supplies to single one, and the improved architecture proposed here also takes part in source matching to reduce the complexity matching networks for broadband applications. To verify, an LNA operating over 12–18-GHz bandwidth is fabricated. The measurement results, for all the 72 chips on the wafer, and their average values are in great accordance with the simulation results, with 25.5–27.5-dB power gain, 1.1–1.8-dB NF, 15–17.5-dBm output power at [math] and with a chip size of 2[math]mm[math][math][math]1.5[math]mm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-13T09:40:06Z
      DOI: 10.1142/S0218126619200056
  • A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback
    • Authors: Jianqun Ding, Lijun Huang, Xianwu Mi, Dajiang He, Shenghai Chen, Xiaoliang Peng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325[math]GHz and 2.435[math]GHz, and the phase noise is [math]128.2[math]dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535[math]mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198[math]dBc/Hz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-13T09:40:06Z
      DOI: 10.1142/S0218126619501251
  • Use of Distributed Semi-Supervised Clustering for Text Classification
    • Authors: Pei Li, Ze Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Text classification is an important way to handle and organize textual data. Among existing methods of text classification, semi-supervised clustering is a main-stream technique. In the era of ‘Big data’, the current semi-supervised clustering approaches for text classification generally do not apply for excessive costs in scalability and computing performance for massive text data. Aiming at this problem, this study proposes a scalable text classification algorithm for large-scale text collections, namely D-TESC by modifying a state-of-the-art semi-supervised clustering approach for text classification in a centralized fashion (TESC). D-TESC can process the textual data in a distributed manner to meet a great scalability. The experimental results indicate that (1) the D-TESC algorithm has a comparable classification quality with TESC, and (2) outperforms TESC by average 7.2 times by using eight CPU threads in terms of scalability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-13T09:40:06Z
      DOI: 10.1142/S0218126619501275
  • Fault Tolerant Control of EPS System with Sensor Fault
    • Authors: Manel Allous, Kais Mrabet, Nadia Zanzouri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Taking into account the sensors faults, modeling of electric power steering (EPS) behavior improves steering reliability. Such task becomes difficult considering the nonlinearity of EPS systems. Therefore, in order to ensure the good behavior stability of the EPS, it is important to validate such established models on a real system. Hence, a fault tolerant control (FTC) design is herein proposed by considering an occurring fault at the torsion bar. A Luenberger observer is used to estimate the torque sensor fault. The FTC is performed to compensate this sensor fault by using the inverse bond graph (BG) modeling. Our simulations reveal the importance of proposed control strategy to improve the EPS system performance but also to reduce the system complexity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-06T08:08:07Z
      DOI: 10.1142/S0218126619501160
  • Transfer Learning Based on Regularized Common Spatial Patterns Using
           Cosine Similarities of Spatial Filters for Motor-Imagery BCI
    • Authors: Yilu Xu, Qingguo Wei, Hua Zhang, Ronghua Hu, Jizhong Liu, Jing Hua, Fumin Guo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In motor-imagery brain–computer interface (BCI), transfer learning based on the framework of regularized common spatial patterns (RCSP) can make full use of the training data derived from other subjects to reduce calibration time for a new subject. Covariance matrices are commonly used to estimate the difference between subjects. However, the classification performances vary greatly depending on different assumptions of the distribution of covariance matrices. Therefore, to directly observe the variations of the target subject’s features after transferring, we neglect the distribution of covariance matrices and instead compare cosine similarities of spatial filters between the target subject and the composite subject whose data comes from the target subject and a source subject. Two RCSP algorithms based on cosine measure are proposed to use the samples of all source subjects and most useful source subjects, respectively. Experiments on one public data set from BCI competition show that our proposed approaches significantly improve the classification performances compared to the conventional CSP algorithm in almost every case, based on a small training set.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-06T08:08:07Z
      DOI: 10.1142/S0218126619501238
  • Design of Wireless Network on Chip with Priority-Based MAC
    • Authors: Yiming Ouyang, Yang Zhao, Kun Xing, Zhengfeng Huang, Huaguo Liang, Jianhua Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The wireless network on chip WiNoC introduces wireless links in the traditional network on chip (NoC), which reduces the network diameter and enables high-throughput, low-latency data communications. In addition, if wireless nodes can dynamically request data transmission, wireless bandwidth will be more effectively utilized. In order to implement a conflict-free, adaptive bandwidth allocation strategy, a priority-based dynamic media access control mechanism has been designed. In this work, a dynamic priority calculation method has been proposed based on the packets’ transmission time and the waiting time in the queue. Then, a priority calculating unit is designed to calculate the dynamic priority of the packet. Finally, the central control unit designed obtains the dynamic priority of the packets, and dynamically authorizes the use rights of the wireless medium according to the priority of the data packet. Simulation experiments show that the media access control mechanism proposed in this paper has significant improvements in throughput, delay, and power consumption performances compared with other mechanisms [S.Deb et al., Wireless NoC as interconnection backbone for multicore chips: promises and challenges, IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2012) 228–239].
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-06T08:08:06Z
      DOI: 10.1142/S021812661950124X
  • Novel Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2D
           Inverse DWT
    • Authors: Goran Savić, Vladimir Rajović
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel memory efficient hardware architecture for 5/3 lifting-based two-dimensional (2D) inverse discrete wavelet transform (IDWT). The proposed architecture processes multiple levels of composition simultaneously using only one one-dimensional (1D) 5/3 lifting-based inverse vertical filter and only one 1D 5/3 lifting-based inverse horizontal filter. In case of [math] levels of composition for [math] image, the proposed 5/3 2D IDWT architecture requires the total memory of size less than [math], which is lower memory size than memory size required in any other previously published architecture. In terms of total number of adders, total number of multipliers (shifters), total computing time and output latency, presented solution is comparable with other state-of-the-art solutions. Proposed hardware architecture is suitable for implementation in JPEG 2000 decoder, since default inverse filter for reversible transformation in JPEG 2000 standard is 5/3 IDWT filter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-03T09:51:58Z
      DOI: 10.1142/S0218126619501184
  • Nonlinear Dynamics of Three-Neurons-Based Hopfield Neural Networks (HNNs):
           Remerging Feigenbaum Trees, Coexisting Bifurcations and Multiple
    • Authors: Z. T. Njitacke, J. Kengne
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, the dynamics of a simplified model of three-neurons-based Hopfield neural networks (HNNs) is investigated. The simplified model is obtained by removing the synaptic weight connection of the third and second neuron in the original Hopfield networks introduced in Ref. 11. The investigations have shown that the simplified model possesses three equilibrium points among which origin of the systems coordinates. It is found that the origin is always unstable while the symmetric pair of fixed points with conditional stability has values depending on synaptic weight between the second and the first neuron that is used as bifurcation control parameter. Numerical simulations, carried out in terms of bifurcation diagrams, graph of Lyapunov exponents, phase portraits, Poincaré section, time series and frequency spectra are employed to highlight the complex dynamical behaviors exhibited by the model. The results indicate that the modified model of HNNs exhibits rich nonlinear dynamical behaviors including symmetry breaking, chaos, periodic window, antimonotonicity (i.e., concurrent creation and annihilation of periodic orbits) and coexisting self-excited attractors (e.g., coexistence of two, four and six disconnected periodic and chaotic attractors) which have not been reported in previous works focused on the dynamics of HNNs. Finally, PSpice simulations verify the results of theoretical analyses of the simplified model of three-neurons-based HNNs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-03T09:51:57Z
      DOI: 10.1142/S0218126619501214
  • Design and Evaluation of Band-Pass Matching Coupler for Narrow-Band DC
           Power Line Communications
    • Authors: Bingting Wang, Ziping Cao, Zhen Luan, Bo Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In power line communication (PLC), coupling transformers are usually required for coupling, band-pass filtering and impedance matching. However, coupling transformer design involves so many parameters that it is typically an imprecise and experimental procedure. In addition, the cost and size of transformers prevent them from being an economic and compact solution for PLC couplers. This paper first analyzes a simplified, distributed parameter model of the power line, which can be used to calculate power line impedance easily and accurately. Next, a low-cost, band-pass matching coupler with compact architecture is designed to replace the coupling transformer for direct current PLC (DC-PLC), which ensures impedance matching on the basis of an accurate power line impedance instead of using an average value. Finally, simulations as well as laboratory tests are conducted under 95–125[math]kHz (CENELEC B-band), which confirm the new coupler’s excellent band-pass filtering and impedance matching performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-03T09:51:56Z
      DOI: 10.1142/S0218126619501196
  • A Performance Conserving Approach for Reducing Memory Power Consumption in
           Multi-Core Systems
    • Authors: Juan Fang, Jiajia Lu, Mengxuan Wang, Hui Zhao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia and industry. In this paper, we first proposed a novel strategy called Dynamic Bank Partitioning (DBP), which allocates banks to different applications based on their memory access characteristics. DBP not only effectively eliminates the interference among applications, but also fully takes advantage of bank level parallelism. Secondly, to further reduce power consumption, we propose an adaptive method to dynamically select an optimal page policy for each bank according to the characteristics of memory accesses that each bank receives. Our experimental results show that our strategy not only improves the system performance but also reduces the memory power consumption at the same time. Our proposed scheme can reduce memory power consumption up to 21.2% (10% on average across all workloads) and improve the performance to some extent. In the case that workloads are built with mixed applications, our scheme reduces the power consumption by 14% on average and improves the performance up to 12.5% (3% on average).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-03T09:51:56Z
      DOI: 10.1142/S0218126619501135
  • A 0.55 V Bandgap Reference with a 59 ppm/[math]C Temperature
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, A. A. Tammam, P. Georgiou, F. J. Lidgey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[math]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[math]V, and generates a 286[math]mV reference voltage with a temperature coefficient of 59[math]ppm/[math]C. The circuit takes 413[math]nA current from 0.55[math]V supply and occupies 0.00986[math]mm2 of active area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-08-03T09:51:55Z
      DOI: 10.1142/S0218126619501202
  • An Optimized 2.4[math]GHz RF Energy Harvester for Energizing Low-Power
           Wireless Sensor Platforms
    • Authors: Chandra Shekhar, Shirshu Varma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The lifetime of battery-operated sensor platforms (i.e., sensor nodes) is a critical issue. The replacement of their batteries is quite a challenging task if these platforms are deployed for detecting events in inaccessible geographical areas (e.g., forest). This paper describes an optimized RF energy harvester/scavenger (consisting of an antenna, impedance matching circuit and rectifier) for energizing low-power sensor platforms (electronic systems). Few nonmatched rectifiers (using HSMS-285X Schottky diodes) are fabricated to characterize the input impedance for different sets of parameters. After characterization a proper impedance matching circuit is integrated for the maximum power transfer from antenna to rectifier. It is shown that a single stage of RF rectifier is enough to produce output voltage of 1.8[math]V. Very few realizations of RF energy harvester are reported in the literature under 2.4[math]GHz ISM band category. Furthermore, high-gain microstrip patch array antennas are fabricated to capture the maximum power from the surroundings. The maximum harvesting range of 0.92[math]m is obtained at 27[math]dBm transmitting power level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-31T05:48:09Z
      DOI: 10.1142/S0218126619501044
  • A Review of Recent Techniques in Mixed-Criticality Systems
    • Authors: Hongxia Chai, Gongxuan Zhang, Jin Sun, Ahmadreza Vajdi, Jing Hua, Junlong Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Unlike traditional embedded systems that almost have only one criticality level, many complex embedded systems nowadays are mixed-critical and are more and more widely used. There has been a lot of research on mixed-criticality (MC) systems. In this paper, we present a survey on the MC systems on these research. First, we discuss the exaltation of the schedulability of MC systems. As improving schedulability may lead to quality-of-service (QoS) reduction of MS systems. Therefore, we investigate the approaches to solve this problem. Improving QoS of MS systems may inevitably increase the energy consumption. Then, we introduce the researches that take the energy efficiency as a design requirement of MC systems. Few MC systems regard fault-tolerance as the design requirement, thus, we extensively investigate fault-tolerance of MC systems. In addition, we introduce some of the main applications for MC systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-30T08:00:34Z
      DOI: 10.1142/S0218126619300071
  • Design of 85 GHz High Power Gain SiGe Buffer with Transformer Matching
    • Authors: Guiheng Zhang, Wei Zhang, Jun Fu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An 85[math]GHz buffer with high power gain is shown in this paper. In order to obtain high power gain, two classic techniques to improve power gain are adopted. The first one is cascade structure of two power stages, and the other one is that each stage utilizes differential cascode structure. Meanwhile, the step-by-step pre-matching technique is applied to optimize the performance of buffer. The stability factor and output power are both improved with other critical design strategies, and a tradeoff is made between gain and efficiency. What’s more, single-ended transformer matching network (TMN) is applied to simplify matching method. The simplified matching method is easy to use with smith chart and works very well, then a modified transformer model is adopted to analyze and optimize the performance of TMN with iterations of impedance matching. After fabricated by 0.13[math][math]m SiGe BiCMOS technology, the buffer shows 18.5[math]dB power gain and 2[math]dBm output power of 1[math]dB gain compression point with 2.8[math]V supply voltage and 40[math]mA operating current, and the saturated output power is 6.33[math]dBm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-30T08:00:33Z
      DOI: 10.1142/S0218126619501147
  • A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable
    • Authors: Ali Nejati, Yasin Bastan, Parviz Amiri, Mohammad Hossein Maghami
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[math][math]m standard CMOS process, the circuit consumes [math]m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270[math]mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8[math]V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12[math]mW.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-27T03:12:30Z
      DOI: 10.1142/S0218126619200044
  • A High-Performance Skin Impedance Measurement Circuit for Biomedical
    • Authors: K. Hayatleh, S. Zourob, R. Nagulapalli, S. Barker, N. Yassine, P. Georgiou, F. J. Lidgey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[math]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[math]uW from 1.5[math]V power supply. The circuit occupies 0.01954[math]mm2 silicon area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-25T02:13:01Z
      DOI: 10.1142/S021812661950110X
  • Algorithms for Reconfiguring NoC-based Fault-Tolerant Multiprocessor
    • Authors: Jigang Wu, Yalan Wu, Guiyuan Jiang, Siew Kei Lam
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper investigates the techniques to construct high-quality target processor array (fault-free logical subarray) from a physical array with faulty processing elements (PEs), where a fixed number of spare PEs are pre-integrated that can be used to replace the faulty ones when necessary. A reconfiguration algorithm is successfully developed based on our proposed novel shifting operations that can efficiently select proper spare PEs to replace the faulty ones. Then, the initial target array is further refined by a carefully designed tabu search algorithm. We also consider the problem of constructing a fault-free subarray with given size, instead of the original size, which is often required in energy-efficient MPSoC design. We propose two efficient heuristic algorithms to construct target arrays of given sizes leveraging a sliding window on the physical array. Simulation results show that the improvements of the proposed algorithms over the state of the art are [math] and [math], in terms of congestion factor and distance factor, respectively, for the case that all faulty PEs can be replaced using the spare ones. For the case of finding [math] target array on [math] host array, the proposed heuristic algorithm saves the running time up to [math] while the solution quality keeps nearly unchanged, in comparison with the baseline algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-25T02:12:59Z
      DOI: 10.1142/S0218126619501111
  • A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM
    • Authors: Pritam Bhattacharjee, Alak Majumder
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[math]V at 6.6[math]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-23T03:34:09Z
      DOI: 10.1142/S0218126619501081
  • Three-Bit DMTL Phase Shifter for Phased Array Antennas
    • Authors: N. M. Mary Sindhuja, S. Kanthamani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      RF MEMS phase shifter is a device that is used to modify the transmission phase of RF signal and provide signal control. Phase shifters are high-value components used in phased array antenna architectures. In phased array antenna the phase shifter is used to provide reliable electronic beam steering. The proposed 3-bit distributed MEMS transmission line (DMTL) phase shifter is designed using elevated coplanar waveguide (ECPW) transmission line for the first time, which results in better return loss of [math]14.23[math]dB and an average insertion loss of [math]1.46[math]dB. This paper discusses the development of ECPW-based 3-bit DMTL phase shifter designed to operate at 15[math]GHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-23T03:34:09Z
      DOI: 10.1142/S0218126619501123
  • Design and Development of Dual Input DC–DC Converter for Hybrid
           Energy System
    • Authors: Hitendra Singh Thakur, Ram Narayan Patel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In hybridization of energy sources with distinct voltage–current characteristics, power electronic converter plays crucial role for efficient and reliable energy diversification. In this paper nonisolated dual input converter is proposed for integration and diversification of energy from two different sources with distinct voltage–current characteristics. The proposed dual input converter (DIC) is proficient for energy diversification from two sources individually and concurrently with series and parallel combination of connected sources. The proposed topology can be operated in buck, buck-boost and boost modes of operation. It offers compact design, higher degree of reliability in operation, simplicity in control and flexibility in selection of input source voltage magnitude. Comprehensive analysis of the proposed converter and detailed comparison with existing literature has also been presented. The proposed concept has been simulated in MATLAB SIMULINK and validated experimentally using dSPACE 1103 real time digital signal controller.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-23T03:34:08Z
      DOI: 10.1142/S0218126619501093
  • Experimental Verification of Pseudo-Differential Electronically
           Controllable Multifunction Filter Using Modified Current
           Differencing/Summing Units
    • Authors: Jan Jerabek, Jan Dvorak, Roman Sotner, Norbert Herencsar, Jaroslav Koton
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the synthesis and analysis of reconfigurable frequency filter with differential input and differential output terminals and its experimental verification. The inner structure of the filter has single-ended form, i.e., filter behaves as the so-called pseudo-differential circuit. Filtering function can be electronically reconfigured between low-pass (LP) and band-pass (BP) responses. Active elements of the filter are differential voltage buffer (DVB) as an input stage and modified current differencing unit (MCDU) together with modified current summing unit (MCSU) as the inner and also output stage. Each of the important parameters of the filter (angular pole frequency, quality factor and pass-band gain) is electronically controllable by parameters of these active elements used. Some of the parameters of the filter are controlled by two independent parameters, i.e., are dual-controlled, which enables the extended electronic controllability. The proposed topology operates in the voltage mode and both input nodes have high input impedance. Expected behavior of the filter is analyzed and verified by PSpice simulations using CMOS models of above-mentioned active elements. Moreover, features of the filter in both configurations were successfully verified also by experimental measurements using behavioral models of active elements.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-23T03:32:07Z
      DOI: 10.1142/S0218126619500981
  • Peak Temperature Minimization for Hard Real-Time Systems Using DVS and DPM
    • Authors: Mingchuan Zhou, Long Cheng, Manuel Dell’Antonio, Xiebing Wang, Zhenshan Bing, M. Ali Nasseri, Kai Huang, Alois Knoll
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the increasing power densities, managing the on-chip temperature has become an important design challenge, especially for hard real-time systems. This paper addresses the problem of minimizing the peak temperature under hard real-time constraints using a combination of dynamic voltage scaling and dynamic power management. We derive a closed-form formulation for the peak temperature and provide a genetic-algorithm-based approach to solve the problem. Our approach is evaluated with both simulations and real measurements with an Intel i5 processor. The evaluation results demonstrate the effectiveness of the proposed approach compared to related works in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-20T01:58:34Z
      DOI: 10.1142/S0218126619501020
  • Fully Electronically Tunable and Easily Cascadable Square/Triangular Wave
           Generator with Duty Cycle Adjustment
    • Authors: Bhartendu Chaturvedi, Atul Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel multiple-output dual-X current conveyor transconductance amplifier with buffer-based square/triangular wave generator is introduced in the paper. The proposed generator provides square wave in current mode and triangular wave in voltage mode. Outputs as square and triangular waves are available from terminals with appropriate impedance levels thereby making the proposed generator circuit easily cascadable in both current and voltage modes. The oscillation frequency and amplitude of output square wave are electronically and independently controllable. One more interesting feature of the proposed generator circuit is the adjustable duty cycle. The proposed circuit of square/triangular wave generator is verified through the HSPICE simulation results carried using 0.18[math][math]m CMOS technology. The simulation results show linear variation of duty cycle against external DC current over a range of 6.5–96%. The variation of square wave’s amplitude via bias current is found to be linear from 10[math][math]A to 80[math][math]A. Moreover, the proposed generator can operate very well up to 23.8[math]MHz with nonlinearity less than 5%. The proposed generator circuit is also experimentally verified.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-20T01:58:33Z
      DOI: 10.1142/S0218126619501056
  • An Efficient Match Search Approach Using Two-Dimensional Hash Function in
           Hardware-Based Dictionary Compression
    • Authors: Qian Dong, Bing Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The hardware-based dictionary compression is widely adopted for high speed requirement of real-time data processing. Hash function helps to manage large dictionary to improve compression ratio but is prone to collisions, so some phrases in match search result are not true matches. This paper presents a novel match search approach called dual chaining hash refining, which can improve the efficiency of match search. From the experimental results, our method showed obvious advantage in compression speed compared with other approach that utilizes single hash function described in the previous publications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-18T08:08:21Z
      DOI: 10.1142/S0218126619501068
  • Multispectral Palmprint Recognition: A Survey and Comparative Study
    • Authors: Yassir Aberni, Larbi Boubchir, Boubaker Daachi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multispectral palmprint recognition has been investigated for many problems and applications over the last decade. It has become one of the most well-known biometric recognition systems. Its success is due to the rich features that can be extracted and exploited from the multispectral images of palmprint captured within specific wavelength ranges across the electromagnetic spectrum. This paper provides an overview of recent state-of-the-art multispectral palmprint approaches for person recognition. The approaches surveyed are discussed by describing, in particular, their feature extraction, feature fusion, matching and decision algorithms. Finally, a comparative study to evaluate their performances for both verification and identification modes is addressed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-18T08:08:20Z
      DOI: 10.1142/S021812661950107X
  • Design of a Quad-Band Monopole Antenna with Independent Frequency Control
    • Authors: Wang Ren, Peng-Hong Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A coplanar waveguide (CPW)-fed I-shaped monopole antenna with independent frequency control characteristic is presented for simultaneously satisfying the global positioning system (GPS), wireless local area network (WLAN), and worldwide interoperability for microwave access (WiMAX) applications. It is printed on an FR4 substrate with a single-layered metallic structure and the overall dimensions are [math][math]mm3. The proposed antenna consists of an I-shaped monopole, a pair of split-ring resonators (SRRs), and a coplanar ground plane. The unique advantage of this study is that the four frequency bands are generated individually by different radiating elements. That is, each of them can be controlled independently with little interference from others, which brings added convenience to the antenna design, optimization and debugging processes. Simulated and measured results both demonstrate that it can cover the 1.575[math]GHz GPS (1.57–1.59[math]GHz); 2.4/5.2/5.8[math]GHz WLAN (2.4–2.485, 5.15–5.35 and 5.725–5.825[math]GHz) and 3.5/5.5[math]GHz WiMAX (3.40–3.60 and 5.25–5.85[math]GHz) applications with satisfactory radiation patterns and acceptable gains.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-16T09:12:53Z
      DOI: 10.1142/S0218126619501019
  • Image De-Hazing Via Gradient Optimized Adaptive Forward-Reverse Flow-Based
           Partial Differential Equation
    • Authors: U. A. Nnolim
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this study, we propose a modified partial differential equation (PDE)-based algorithm for image de-hazing. The algorithm possesses relatively low computational complexity and the core function of the PDE is easily amenable to hardware implementation. New contributions include the optimization and automated processing for dark and hazy images, avoiding manual parameter tuning. Additionally, the regularization parameter is computed adaptively from the binary mask of the input image. This is combined with a gradient-based metric for optimization to automatically determine stopping time of the algorithm for both types of images. The proposed scheme is fast and utilizes spatial or frequency domain filters to achieve illumination and reflectance component estimation without resorting to logarithms. Moreover, there is absence of halos in de-hazed images compared to previous work. Extensive experiments indicate that the proposed approach yields results comparable to or better than several works from the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-16T09:12:52Z
      DOI: 10.1142/S0218126619500993
  • Systematic Hysteresis Analysis for Dynamic Comparators
    • Authors: Leïla Khanfir, Jaouhar Mouïne
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized. In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18[math][math]m CMOS technology showing a maximum error of 8.6%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-16T09:12:52Z
      DOI: 10.1142/S0218126619501007
  • A Thermal Mitigation Algorithm Based on the Power Characteristics of
           Mobile Application Processors
    • Authors: Chang Min Eun, Hyun Hak Cho, Ok Hyun Jeong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern mobile devices suffer from severe power and thermal issues due to the adoption of high-frequency multi-core processors. However, methods of resolving the thermal problems in mobile environments are restricted due to their size, semiconductor process technology, and battery limitations. Mobile devices generally rely on a software framework called the Thermal Management Model (TMM). However, conventional TMMs suffer from inevitable performance degradation due to the thermal response. We propose a new Thermal Mitigation Algorithm (TMA) to optimize performance and thermal mitigation by considering the multi-core power curve of a mobile CPU which is experimentally derived using a typical smartphone and thus resolve this issue. Our proposed scheme aims to reduce thermal problems and enhance system performance by limiting the usage of power-inefficient frequencies when operating on a multi-core. We evaluate the proposed algorithm on a real system using a typical smartphone and conduct the performance measurement using the AnTuTu benchmark v4.5.1. In addition, we use the on-chip temperature sensors of CPU cores and a crystal oscillator embedded in the Application Processor (AP) to monitor the temperature of the mobile device. The result shows that our scheme, respectively reduce the average temperatures of CPU cores and a crystal oscillator by 6.61% and 5.02% while improving system performance by 3.24%. In conclusion, we reduce the thermal problems and enhance performance simultaneously using the proposed TMA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-16T09:12:52Z
      DOI: 10.1142/S0218126619501032
  • A Review of Cost and Makespan-Aware Workflow Scheduling in Clouds
    • Authors: Pingping Lu, Gongxuan Zhang, Zhaomeng Zhu, Xiumin Zhou, Jin Sun, Junlong Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Scientific workflow is a common model to organize large scientific computations. It borrows the concept of workflow in business activities to manage the complicated processes in scientific computing automatically or semi-automatically. The workflow scheduling, which maps tasks in workflows to parallel computing resources, has been extensively studied over years. In recent years, with the rise of cloud computing as a new large-scale distributed computing model, it is of great significance to study workflow scheduling problem in the cloud. Compared with traditional distributed computing platforms, cloud platforms have unique characteristics such as the self-service resource management model and the pay-as-you-go billing model. Therefore, the workflow scheduling in cloud needs to be reconsidered. When scheduling workflows in clouds, the monetary cost and the makespan of the workflow executions are concerned with both the cloud service providers (CSPs) and the customers. In this paper, we study a series of cost-and-time-aware workflow scheduling algorithms in cloud environments, which aims to provide researchers with a choice of appropriate cloud workflow scheduling approaches in various scenarios. We conducted a broad review of different cloud workflow scheduling algorithms and categorized them based on their optimization objectives and constraints. Also, we discuss the possible future research direction of the clouds workflow scheduling.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-13T02:03:34Z
      DOI: 10.1142/S021812661930006X
  • Improvement of Gray ROM-Based Encoder for Flash ADCs
    • Authors: Mohammad Soleimani, Siroos Toofan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-[math] thermometer codes to 2-of-[math] codes ([math]). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-[math] codes by the use of two-input AND and four-input merged AND–OR gates. In the second stage, 2-of-[math] codes are turned to [math] gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, [math] MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-[math]m CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30[math]ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50[math]mW and 13.90[math]mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-06T08:19:27Z
      DOI: 10.1142/S021812661950097X
  • A High Value, Linear and Tunable CMOS Pseudo-Resistor for Biomedical
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, P. Georgiou, F. J. Lidgey
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31[math]dB mid-band gain and a low-pass cutoff frequency of 0.85[math]Hz. The circuit operates from a 1[math]V supply and draws 950[math]nA current at room temperature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-06T08:19:26Z
      DOI: 10.1142/S0218126619500968
  • Analysis and Design of a New 10-Bit High Accuracy and Resolution TDC by
           Elimination of Offset Voltage and Parasitic Capacitors Effects
    • Authors: Mahdi Rezvanyvardom, Amin Mirzaei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18[math][math]m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-06T08:19:25Z
      DOI: 10.1142/S0218126619500956
  • Firefly Algorithm for Intelligent Context-Aware Sensor Deployment Problem
           in Wireless Sensor Network
    • Authors: Puri Vishal, A. Ramesh Babu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor networks (WSNs) provide acceptable low cost and efficient deployable solutions to execute the target tracking, checking and identification of substantial measures. The primary step necessary for WSN is to organize all the sensor nodes in their positions to build up an effective network. In the sensor deployment model, Target COVerage (TCOV) and Network CONnectivity (NCON) are the basic issues in WSNs that have obtained significant consideration in sensor deployment. This paper intends to develop an intelligent context awareness algorithm for sensor deployment process in WSN. Accordingly, the process is divided into two phases. In the first phase, the TCOV process is performed, whereas the second phase of the algorithm establishes NCON among the sensors. An objective model to meet both TCOV and NCON is formulated as a minimization problem. The problem is solved using FireFly (FF) optimization to determine the optimal locations for sensors. It leads to an intelligent sensor deployment model that can determine the optimal locations for the sensors in the WSN. Further, the proposed FF-TCOV and FF-NCON models are compared against the conventional algorithms, namely, genetic algorithm, particle swarm optimization, artificial bee colony, differential evolution and evolutionary algorithm-based TCOV and NCON models. The results achieved from the simulation show the improved performance of the proposed technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-07-04T08:22:18Z
      DOI: 10.1142/S0218126619500944
  • Novel Lossless Grounded and Floating Inductance Simulators Employing a
           Grounded Capacitor Based on CC-CFA
    • Authors: Amrita Singh, Manoj Kumar Jain, Subodh Wairya
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Simulation of inductors has been a very popular area of analog circuit research and the alternative choice for realizing inductor-based circuits in integrated circuits. In this paper, lossless, grounded and floating inductor topologies using current-controlled-current-feedback amplifier (CC-CFA) with single grounded capacitor are presented. The proposed topologies can be tuned electronically by changing the biasing current of the CC-CFA. Two topologies for grounded inductor simulator employ two CC-CFA and one grounded capacitor. One topology for floating inductor simulator employs three CC-CFA and one grounded capacitor. The performance of the grounded and floating inductor simulators are demonstrated on resonant circuits. The theoretical analysis is verified by PSPICE simulation results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-27T08:34:33Z
      DOI: 10.1142/S0218126619500932
  • A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs
    • Authors: Jing Li, Xin Ye, Jian Luo, Ning Ning, Qi Yu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd–even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with [math] samples and costs less hardware with 2.1[math]k gate counts.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-27T08:34:33Z
      DOI: 10.1142/S0218126619500920
  • Efficient Design of Quantum Circuits Using Nearest Neighbor Constraint in
           3D Architecture
    • Authors: Leniency Marbaniang, Kamalika Datta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Synthesis and optimization of quantum circuits have received significant attention from researchers in recent years. Developments in the physical realization of qubits in quantum computing have led to new physical constraints to be addressed. One of the most important constraints that is considered by many researchers is the nearest neighbor constraint which limits the interaction distance between qubits for quantum gate operations. Various works have been reported in the literature that deal with nearest neighbor compliance in multi-dimensional (mostly 1D and 2D) qubit arrangements. This is normally achieved by inserting SWAP gates in the gate netlist to bring the interacting qubits closer together. The main objective function to minimize here is the number of SWAP gates. The present paper proposes an efficient qubit placement strategy in a three-dimensional (3D) grid that considers not only qubit interactions but also the relative positions of the gates in the circuit. Experimental evaluation on a number of benchmark circuits show that the proposed method reduces the number of SWAP gates by 16.2% to 47.0% on the average as compared to recently published works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-25T03:25:30Z
      DOI: 10.1142/S0218126619500841
  • A Bandwidth Mismatch Optimization Technique in Time-Interleaved
           Analog-to-Digital Converters
    • Authors: Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[math]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-25T03:25:30Z
      DOI: 10.1142/S0218126619500907
  • Second Order Universal Filter Using Four Terminal Floating Nullor (FTFN)
    • Authors: Ashish Ranjan, Subrahmanyam Perumalla, Ravi Kumar, Vista John, Shantikumar Yumnam
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this research paper, a voltage mode second order universal filter using Four Terminal Floating Nullor (FTFN) is presented. The proposed design uses Three Input Single Output (TISO) for the realization of all filter responses namely Low Pass Filter (LPF), High Pass Filter (HPF), Band Pass Filter (BPF), Notch Filter (NF) and All Pass Filter (APF) by using proper input selection. The analog building block, FTFN is simply realized with two commercially available AD844 ICs. The proposed second order universal filter comes with a single FTFN block with four passive components in which no component matching is required for filter realization. The universal filter is well verified using PSPICE simulation. In addition, experimental verification for the second order APF has been performed that confirms the theoretical expectations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-25T03:25:28Z
      DOI: 10.1142/S0218126619500919
  • True Three-Valued Ternary Content Addressable Memory Cell Based On
           Ambipolar Carbon Nanotube Transistors
    • Authors: Daniel Hellkamp, Kundan Nepal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [math]- and [math]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar design can lead to a savings of up to 31% in terms of transistor count over a traditional design. We also explore issues related to matchline leakage, cell stability and design in the presence of metallic tubes.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-25T03:25:28Z
      DOI: 10.1142/S0218126619500853
  • An Exponential Jerk System: Circuit Realization, Fractional Order and Time
           Delayed Form with Dynamical Analysis and Its Engineering Application
    • Authors: Karthikeyan Rajagopal, Akif Akgul, Sajad Jafari, Anitha Karthikeyan, Ünal Çavuşoğlu, Sezgin Kacar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Simple dynamical systems are of interest always. In this paper, we propose a simple jerk system with one exponential nonlinearity. Dynamical properties of the proposed system are investigated. To show the practical realizability of the proposed system we implement the exponential jerk system using off the shelf components. Fractional order and time delays are considered as complex analysis patterns of nonlinear systems. We investigate the fractional order time delayed exponential jerk system. For numerical analysis we use the modified Adomian Decomposition Method. To show the engineering importance of the proposed system, we derive a pseudo random number generator based on it.Various test results are presented to show the randomness of the system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-25T03:25:27Z
      DOI: 10.1142/S0218126619500877
  • Simulation and Analysis of Novel Extendable Multilevel Inverter Topology
    • Authors: V. Thiyagarajan, P. Somasundaram, K. Ramash Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multilevel inverter (MLI) has become more popular in high power, high voltage industries owing to its high quality output voltage waveform. This paper proposes a novel single phase extendable type MLI topology. The term ‘extendable’ is included since the presented topology can be extended with maximum number of dc voltage sources to synthesize larger output levels. This topology can be operated in both symmetrical and asymmetrical conditions. The major advantages of the proposed inverter topology include minimum switching components, reduced gate driver circuits, less harmonic distortion and reduced switching losses. The comparative analysis based on the number of switches, dc voltage sources and conduction switches between the proposed topology and other existing topologies is presented in this paper. The comparison results show that the proposed inverter topology requires fewer components. The performance of the proposed MLI topology has been analyzed in both symmetrical and asymmetrical conditions. The simulation model is developed using MATLAB/SIMULINK software to verify the performance of the proposed inverter topology and also the feasibility of the presented topology during the symmetrical condition has been validated experimentally.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-21T07:48:15Z
      DOI: 10.1142/S0218126619500890
  • An Automated Security Approach of Video Steganography–Based LSB
           Using FPGA Implementation
    • Authors: Sa’ed Abed, Mohammed Al-Mutairi, Abdullah Al-Watyan, Omar Al-Mutairi, Wesam AlEnizy, Aisha Al-Noori
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Steganography has become one of the most significant techniques to conceal secret data in media files. This paper proposes a novel automated methodology of achieving two levels of security for videos, which comprise encryption and steganography techniques. The methodology enhances the security level of secret data without affecting the accuracy and capacity of the videos. In the first level, the secret data is encrypted based on Advanced Encryption Standard (AES) algorithm using Java language, which renders the data unreadable. In the second level, the encrypted data is concealed in the video frames (images) using FPGA hardware implementation that renders the data invisible. The steganographic technique used in this work is the least significant bit (LSB) method; a 1–1–0 LSB scheme is used to maintain significantly high frame imperceptibility. The video frames used as cover files are selected randomly by the randomization scheme developed in this work. The randomization method scatters the data throughout the video frames rendering the retrieval of the data in its original order, without a proper key, a challenging task. The experimental results of concealment of secret data in video frames are presented in this paper and compared with those of similar approaches. The performance in terms of area, power dissipation, and peak signal-to-noise ratio (PSNR) of the proposed method outperformed traditional approaches. Furthermore, it is demonstrated that the proposed method is capable of automatically embedding and extracting the secret data at two levels of security on video frames, with a 57.1[math]dB average PSNR.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-21T07:48:15Z
      DOI: 10.1142/S021812661950083X
  • Design and Implementation of New Topology for Nonisolated DC–DC
           Microconverter with Effective Clamping Circuit
    • Authors: M. Premkumar, T. R. Sumithira
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents nonisolated DC–DC converter which suits for solar photovoltaic (PV) applications. The DC–DC converter proposed in this paper utilizes coupled inductor, voltage boost capacitor and passive clamp circuit to achieve desired voltage gain and the passive clamp circuit will help the converter to accomplish high efficiency. To minimize the voltage spike/ringing across MOSFET drain-source and to recover the coupled inductor leakage energy, the RCD clamp circuit is used. The voltage lift capacitor along with the clamp circuit helps in increasing the voltage gain of the converter. The proposed converter offers low voltage stress on MOSFET and diode, low-coupled inductor turns ratio with low duty cycle. The converter is analyzed and simulated with PLECS standalone simulating environment for all aspects of the clamp circuit. The simulation results are compared with RCD and other clamping circuits to verify the performance of the proposed converter. The converter is also compared with active clamping to discuss the effectiveness of passive clamping circuit. To track the maximum power from the solar PV module, the conventional maximum power point tracking (MPPT) techniques are used. The prototype is designed and implemented for 150W and experimental results are verified.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-21T07:48:14Z
      DOI: 10.1142/S0218126619500828
  • Modeling and Analysis of the Nonideality of LO Pulse Overlap for
           Multi-Phase Passive Mixer First RF Frontend
    • Authors: Yongqian Du, Wei Hu, Guifang Li, Shibin Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multi-phase passive mixer (PM) first RF frontend has regained great concern for its satisfactory noise performance comparable to LNA-first frontend. Moreover, the re-configurable impedance, bi-directional signal transparency and bi-directional impedance translation performance enable a splendid application future for the multi-phase PM-first RF frontend. However, it still suffers from quite a few nonidealities, among which the adjacent Local Oscillator (LO) pulse overlap is the remaining nonideality lacking deep research, and how the LO pulse overlap decays the impedance matching and noise performance of multi-phase PM-first RF frontend remains unclear. In this work, an accurate model is, for the first time, established and analyzed to reveal how the LO pulse overlap decays the impedance matching and noise performance of multi-phase PM-first RF frontend. The analytical and simulation results demonstrate that the impedance matching will be drastically deteriorated because of LO overlap, and when LO pulse overlap exceeds 2% the impedance matching will be collapsed, while the noise figure (NF) is deteriorated by 3.1 dB when LO overlap ranges from 0% to 2%. Moreover, even a chocking inductor technique and a technique by introducing a synchronous phase-shifted signal have been proposed to suppress the LO overlap, the gain and noise performance can be deteriorated or the power and chip area cost are big. To address this question, a LO pulse overlap suppression technique is proposed furthermore by introducing an overlap safeguard factor (OLSF) in this work. The additional impedance smaller than 2[math][math] in the main signal path makes the OLSF scheme beneficial for noise and gain improvement, and the proposed OLSF scheme is power, area (0.04[math]mm[math] and cost efficient compared with existing LO overlap suppression techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-21T07:48:12Z
      DOI: 10.1142/S0218126619500865
  • Design of Eight Parallel 512-Point MDF FFT/IFFT Processor for WPAN
    • Authors: C. A. Arun, Prakasam Periasamy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a high-speed FFT algorithm for high data rate wireless personal area network applications. In a wireless personal area network, the FFT/IFFT block leads the major role. Computational requirements of FFT processors are a heavy burden in most real-time applications. From the previous work, it can be recognized that most of the FFT structures follow the divide and conquer algorithms, which improve the computational efficiency. In the proposed model, a new design of 512-point FFT/IFFT processor is derived by mixed approach for a Radix-26 algorithm, which has been presented and implemented using the Eight Parallel Multipath Delay Feedback (MDF) architecture. In this work, three distinct complex multiplication approaches are derived; from the analysis, a mixed approach has been proposed to reduce the multiplier complexity and also the equivalent normalized area. The proposed design is compiled and simulated with 90[math]nm CMOS technology optimized for a 1.2[math]V supply voltage. The proposed Mixed Radix-26 algorithm has been verified and validated using existing architectures. It has been found that the proposed mixed approach for Radix-26 algorithm reduces the normalized area by 8.603% compared with verified architectures. Also, the multiplier complexity is reduced by more than 33% using Canonical Signed Digit constant multiplier. The proposed architecture is suitable for applications like OFDM based WPAN applications at high data processing rates.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-21T07:48:11Z
      DOI: 10.1142/S0218126619500889
  • Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic
    • Authors: Yasir A. Shah, Khalid Javeed, Shoaib Azmat, Xiaojun Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime [math] is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye’s double and add (DAA) algorithm based on [math]-only common [math] (co-[math]) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47[math]ms at a maximum frequency of 327[math]MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and [math] metrics.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-21T07:48:10Z
      DOI: 10.1142/S0218126619500816
  • A Review on Self-Healing and Self-Organizing Techniques for Wireless
           Sensor Networks
    • Authors: Sergio Diaz, Diego Mendez, Rolf Kraemer
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We present the state-of-the-art related to self-organizing and self-healing techniques. On the one hand, self-organization is the nodes’ ability to construct a network topology without any human intervention and any previous topology knowledge. On the other hand, self-healing is the network’s ability to recover from failures by using hardware and software redundancies. By using both techniques, Wireless Sensor Networks (WSNs) can be deployed in unattended and harsh environments where on-site technical service is unfeasible. In the last few years, a large amount of work has been done in these two research areas, but these different techniques occur at different layers and with no general classification or effort to consolidate them. One of the contributions of this paper is the consolidation of the most significant and relevant mechanisms in these two areas, and additionally, we made an effort to organize and classify them. In this review, we explain in detail the two stages of self-organization, namely topology construction and management. Moreover, we present a comprehensive study of the four steps in a self-healing technique, namely, information collection, fault detection, fault classification and fault recovery. By introducing relevant work, comparative tables, and future trends, we provide the reader with a complete picture of the state-of-the-art. Another contribution is the proposal of a unified framework that employs self-organizing and self-healing mechanisms to achieve a fault-tolerant network.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-20T04:25:45Z
      DOI: 10.1142/S0218126619300058
  • New Time-Domain Approach for Digital Signal Processing: A Set of
           Experimental Measures for Systems with High Transmission Rates
    • Authors: Mauricio Silveira, Gustavo Varella Figueiredo, Robinson Gaudino Caputo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The essential purpose of this paper is to introduce to the current literature a new theoretical approach on how to implement the process of encoding data using a unique treatment with respect to the digital signal processing. Some relationships between a set of digital pulses and a special class of real polynomials allow us to identify the generation of a single pulse with an intrinsic dependence on the zero values of an arbitrary equation represented by a polynomial equation, where this direct match is established through an analytic operator. By using an ordinary field-programmable gate array architecture, it is possible to validate our theoretical approach, and we are presenting some experimental measurements, as well as one application on how to build a commercial data compressor for fiber optics. The algorithm here introduced presents an innovative technique, and its performance is faster per comparison. Furthermore, thanks to the math-to-time-domain transformations, it tends to overcome the current time required to process polynomial equations, which are involved in the data compression and data encryption systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:18Z
      DOI: 10.1142/S0218126619500725
  • Improvement on Image Edge Detection Using a Novel Variant of the Ant
           Colony System
    • Authors: Karima Benhamza, Hamid Seridi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an improved Ant Colony System algorithm applied to image edge detection is presented. During their movement on image, artificial ants establish pheromone graph which represents the image edge information. The ant movement is directed by the local variation of the image’s intensity values. To improve this method, supplementary behaviors are added to each ant in response to its local stimuli, i.e., the ant self-reproduces and directs its progenitors to an appropriate direction to explore more suitable areas. Moreover, it dies if it exceeds a specific iteration age and so the ineffective searches are eliminated. These additional behaviors allow diversifying the exploration performed by ants and also reinforcing the exploitation of these ants’ search experience. Proposed approach allows having more accurate and more complete edges. The performance is tested visually with various images and empirically with evaluation parameters.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:17Z
      DOI: 10.1142/S0218126619500804
  • Fast In-Memory Key–Value Cache System with RDMA
    • Authors: Wei Chen, Songping Yu, Zhiying Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The quick advances of Cloud and the advent of Fog computing impose more and more critical demand for computing and data transfer of low latency onto the underlying distributed computing infrastructure. Remote direct memory access (RDMA) technology has been widely applied for its low latency of remote data access. However, RDMA gives rise to a host of challenges in accelerating in-memory key–value stores, such as direct remote memory writes, making the remote system more vulnerable. This study presents an in-memory key–value system based on RDMA, named Craftscached, which enables: (1) buffering remote memory writes into a communication cache memory to eliminate direct remote memory writes to the data memory area; (2) dividing the communication cache memory into RDMA-writable and RDMA-readable memory zones to reduce the possibility of data corruption due to stray memory writes and caching data into an RDMA-readable memory zone to improve the remote memory read performance; and (3) adopting remote out-of-place direct memory write to achieve high performance of remote read and write. Experimental results in comparison with Memcached indicate that Craftscached provides a far better performance: (1) in the case of read-intensive workloads, the data access of Craftscached is about 7–43[math] and 18–72.4% better than those of TCP/IP-based and RDMA-based Memcached, respectively; (2) the memory utilization of small objects is more efficient with only about 3.8% memory compaction overhead.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:16Z
      DOI: 10.1142/S0218126619500749
  • A Multi-Objective-Driven Placement Technique for Digital Microfluidic
    • Authors: Chaowei Wan, Xiaodao Chen, Dongbo Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Microfluidic biochips are extensively utilized in biochemistry procedures due to their low cost, high precision and efficiency when compared to traditional laboratory procedures. Recent, computer-aided design (CAD) techniques enable a high performance in digital microfluidic biochip design. A key part in digital microfluidic biochip CAD design is the biochip placement procedure which determines the physical location for biological reactions during the physical design. For the biochip physical design, multiple objects need to be considered, such as the size of the chip and the total operation time. In this paper, a multi-objective optimization is proposed based on Markov decision processes (MDPs). The proposed method is evaluated on a set of standard biochip benchmarks. Compared to existing works, experimental results show that the total operation time, the capacity for routing and the chip size can be optimized simultaneously.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:16Z
      DOI: 10.1142/S0218126619500762
  • Low-Cost AES-128 Implementation for Edge Devices in IoT Applications
    • Authors: S. Shanthi Rekha, P. Saravanan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Internet of Things (IoT) is an ecosystem of connected edge devices that are accessible through the internet. Recent research focusses on adding more smartness and intelligence to these edge devices making them susceptible to various kinds of security threats. These edge devices rely on cryptographic techniques to encrypt the pre-processed data collected from the sensors deployed in the field. Since the edge devices are resource constrained, low-cost implementations of cryptographic algorithms are desirable. This work proposes a novel low-cost implementation of a versatile symmetric encryption algorithm namely Advanced Encryption Standard (AES) using time-multiplexed architectures for edge devices. The optimization is carried out in a four-fold manner on AES encryption/decryption hardware based on the resource sharing mechanism with a modified Substitution box achieving a maximum of 1.053[math]GHz operating frequency. The aim of this work is to develop an area-power efficient AES architecture with a reasonable throughput suitable for resource constrained applications. The proposed architectures are synthesized on a Virtex-6 FPGA board and the ASIC performance results are obtained using 180[math]nm SCL technology library. Implementation results of the proposed AES core integrated with an UART module are shown as a proof of concept.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:15Z
      DOI: 10.1142/S0218126619500622
  • Four-Input One-Output Voltage-Mode Universal Filter Using Simple OTAs
    • Authors: Montree Kumngern, Pichai Suksaibul, Fabian Khateb
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a new electronically tunable voltage-mode universal filter with four-input one-output employing six simple operational transconductance amplifiers (OTAs), two grounded capacitors and two MOS resistors. The use of grounded passive components is beneficial for integrated circuit implementation. The proposed filter can realize low-pass, band-pass, high-pass, band-stop and all-pass filtering functions without active and passive component-matching conditions and inverting-type input signals requirements. The natural frequency and quality factor can be tuned independently and electronically by adjusting the bias currents. The voltage-mode filter offers the features of high-input impedance and low active and passive sensitivities. The characteristics of the proposed universal filter are verified using PSPICE simulators through 0.35[math][math]m CMOS process. Experimental results are used to confirm the workability of proposed circuit through LM13600 commercially available OTAs. Also a digitally programmable filter is shown to confirm the advantage of multiple-input universal filter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:15Z
      DOI: 10.1142/S0218126619500786
  • A Variability-Aware Robust Design Methodology for Integrated Circuits by
           Geometric Programming
    • Authors: Yi Zhang, Junlong Zhou, Li Chen, Jin Sun
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Process variations have continuously posed significant challenges to the performance and yield of integrated circuits (ICs). The performance modeling and robust optimization method considering process variations has become an important research task in today’s IC design. Aiming at solving the problems of strong nonlinearity and high-dimensional problems in circuit design, this paper proposes a general robust optimization method for ICs by geometric programming. This method first employs regularization sparse models to model a specific performance metric as a posynomial function in terms of design parameters, in order to reduce parameter space dimensionality and to accurately capture the nonlinear relationship between performance perturbations and process variations. Based on the posynomial performance models, this method further uses an uncertainty set to represent the uncertainties of process variations, and formulates the problem of robust optimization under process variations as a general geometric programming model that can be efficiently solved. Experimental results demonstrate that, the proposed method not only enhances the accuracy and efficiency of circuit performance modeling, but also improves the performance yield significantly compared with traditional circuit design methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:14Z
      DOI: 10.1142/S0218126619500737
  • A Capacitor-Splitting Switching Scheme with Low Total Power Consumption
           for SAR ADCs
    • Authors: Hao Wang, Wenming Xie, Zhixin Chen, Sijing Cai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A low-power capacitor-splitting switching algorithm for successive approximation register (SAR) and analog-to-digital converters (ADCs) is proposed. To reduce the total power consumption, it does not require reset energy, which accounts for a large proportion. Besides, energy-efficient one-side double-level switching technique is also utilized from the forth bit cycle. Thus, the proposed switching algorithm requires 26.54 CV[math] total switching energy, 16.75% less over the tri-level one. Due to the capacitor-splitting structure, it also shows good linearity performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:14Z
      DOI: 10.1142/S0218126619200020
  • Biquadratic Digital Phase-Compensator Design with Stability-Margin
    • Authors: Tian-Bo Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a novel method for the design of a recursive second-order (biquadratic) all-pass phase compensator with controllable stability margin. The design idea stems from the generalized stability triangle (GST) derived by the author for the second-order biquadratic digital filter. Based on the GST, a parameter-transformation method is proposed on the transformations of the denominator coefficients of the transfer function of the biquadratic phase compensator. The transformations convert the original denominator coefficients to other new parameters, and any values of those new parameters can guarantee that the GST condition is always satisfied. Optimizing the new parameters yields a biquadratic phase compensator that definitely meets a prespecified stability margin. That is, a biquadratic all-pass phase compensator can be designed to have an arbitrarily specified stability margin. This in turn avoids the occurrence that a recursive phase compensator may become unstable in the practical applications. Thus, the resulting biquadratic phase compensator has robust stability, which is extremely important during the practical filtering operations. A design example is given to show the stability margin guarantee as well as the approximation accuracy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:14Z
      DOI: 10.1142/S0218126619500683
  • Low-Power FSM Synthesis Based on Automated Power and Clock Gating
    • Authors: Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work introduces a concept of integrating clock gating and power gating in finite state machines (FSMs) to reduce the overall power dissipation. The theory of the proposed power gating technique is to shut down the power supply during periods of inactivity of the FSM. The inactive period is identified by the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating on the other hand disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The proposed approach introduces the concept of gating into both the state logic (DGS) and output logic (DGO) in FSM separately and can be implemented in general to all FSMs. The control logic for gating automatically extracts information from the state description of the FSM. An efficient method of partitioning of the FSM is also proposed in this paper to effectively implement the gating techniques. The dual gating approach has been introduced in 10 standard benchmark FSM circuits for DGS technique and later extended to four FSMs for implementing “DGS[math][math][math]DGO.” Then the circuits are simulated and synthesized in CADENCE analog and digital design tools. Simulation results show a maximum power reduction of 62.17% in DGS technique and 73% total power savings after implementing “DGS[math][math][math]DGO.” The average area overhead in DGS technique is 12.9% whereas in DGS[math][math][math]DGO, the area increases by 22.6%. The area overhead and the delay tend to reduce as the size of the FSM increases.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:12Z
      DOI: 10.1142/S0218126619200032
  • An Efficient Partitioning Algorithm Based on Hypergraph for 3D
           Network-On-Chip Architecture Floorplanning
    • Authors: Junyan Tan, Chunhua Cai
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network-on-Chip (NoC) supplies a scalable and fast interconnect for the communication between the different IP cores in the System-on-Chip (SoC). With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate more and more components for the different signal processing tasks. Two dimensional Network-on-Chip (2D NoC) becomes a bottleneck for the development of the SoC architecture because of its limitation on the area of chip and the long latency. In this case, SoC research is forcing on the exploration of three dimensions (3D) technology for developing the next generation of large SoC which integrates three dimensional Network-on-Chip (3D NoC) for the communication architecture. 3D design technology resolves the vertical inter-layer connection issue by Through-Silicon Vias (TSVs). However, TSVs occupy significant silicon area which limits the inter-layer links of the 3D NoC. Therefore, the task partitioning on 3D NoC must be judicious in large SoC design. In this paper, we propose an efficient layer-aware partitioning algorithm based on hypergraph (named ELAP-NoC) for the task partitioning with TSV minimization for 3D NoC architecture floorplanning. ELAP-NoC contains divergence stage and convergence stage. ELAP-NoC supplies firstly a multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that ELAP-NoC performs a better capacity in the partitioning of the different numbers of cores which supplies the first step for the 3D NoC floorplanning.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:12Z
      DOI: 10.1142/S0218126619500750
  • Practical Reliability Analysis and Approximate Design of Arithmetic
    • Authors: Xingjian Xu, Tian Ban, Yuehua Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Critical constituent gates are first detected and graded based on their individual impact of an error in the outputs. This brings in the idea of practical reliability analysis metric. Then, the approximation of arithmetic circuits by random logic applied to least significant gates is introduced. The 74283 fast adder is used as an example to illustrate the feasibility of the proposed methods. Simulation results show the potential efficient application of the proposed reliability analysis metric and approximation method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:12Z
      DOI: 10.1142/S0218126619500774
  • Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority
    • Authors: Trailokya Nath sasamal, Ashutosh Kumar Singh, Umesh Ghanekar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[math][math]m2 and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:11Z
      DOI: 10.1142/S0218126619500798
  • Optimal Energy Management Strategy and Novel Control Approach for DPGSs
           Under Unbalanced Grid Faults
    • Authors: Rabeh Abbassi, Sahbi Marrouchi, Salem Saidi, Abdelkader Abbassi, Souad Chebbi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, the use of distributed power generation systems (DPGSs) based on renewable energy resources is increasingly being pursued as a supplement and a reliable alternative to the large traditional energy sources. For it, power-electronic interface technologies and control have also emerged as the most important key elements in the area of energy management and integrating DPGSs. The specification of a power-electronic interface is subject to several requirements that are related not only to the DPGS itself but also to its interactions with the power system especially where the utility grid is subject to events that can potentially lead to large-scale disturbances or even to its collapse if it operates near its capacity without fault margin. This study deals, first, with an optimized energy management strategy and, second, with a newly-conceived control strategy called symmetrical components control algorithm (SCCA) that was proposed for four-leg three-phase grid-connected voltage source inverter (VSI) used for DPGSs with wind–solar–battery sources. A mechanism of negative and zero sequences injection based on the control of ([math]) current coordinates has been introduced. The performance of entire control system, to enhance the unbalanced fault ride-through capability of DPGSs, has been evaluated by time domain simulations with MATLAB/Simulink. Advantages of the combined active–reactive control ensuring both current and voltage controls have been achieved compared to the majority of already published strategies. The distinct features of the proposed SCCA strategy prove that it allows to meet the requirements for grid interconnection and the new stricter standards with respect to power quality, safe running, and islanding protection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:11Z
      DOI: 10.1142/S0218126619500579
  • Virtual Verification and Validation of Automotive System
    • Authors: Mona Safar, Magdy A. El-Moursy, Mohamed Abdelsalam, Ayman Bakr, Keroles Khalil, Ashraf Salem
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-18T01:26:11Z
      DOI: 10.1142/S0218126619500713
  • A New Asymmetric and Cascaded Switched Diode Multilevel Inverter Topology
           for Reduced Switches, DC Source and Blocked Voltage on Switches
    • Authors: S. A. Ahamed Ibrahim, P. Anbalagan, M. A. Jagabar Sathik
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new asymmetric switched diode (ASD) multilevel inverter is presented for medium-voltage and high-power applications. The proposed converter consists of series connection basic unit with full-bridge inverter. In addition to this, a cascaded switched diode (CSD) structure is recommended to generate the higher number of voltage levels. Seven different algorithms are presented to determine the magnitudes of DC sources in CSD topology. To prove the advantages of proposed multilevel converter over recent multilevel converters in terms of blocking voltage, numbers of IGBTs and on-state switches are presented. To show the authority of the proposed multilevel inverter, it is simulated using MATLAB/Simulink and is experimentally tested using prototype model for 13-level inverter. Finally, various output voltage and current waveforms are shown to prove the dynamic behavior of proposed inverter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-06T03:04:35Z
      DOI: 10.1142/S0218126619500646
  • Dynamic Modeling and Optimal Control of a Wind Turbine with Doubly Fed
           Induction Generator Using Imperialist Competitive and Artificial Bee
           Colony Algorithms
    • Authors: Javad Salehi, Arman Amini Badr
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper addresses modeling, stability analysis and control of the doubly fed induction generator (DFIG) for wind turbines (WTs). In the present work, imperialist competitive and artificial bee colony algorithms are used for optimizing parameters of controllers of a WT with DFIG. Algorithms for optimizing the controllers’ parameters are described. Based on this, an eigenvalue-based objective function is utilized to optimize the parameters. To evaluate the optimized gains, simulations are performed on a single machine-infinite bus system, and the dynamic responses of system with parameters obtained from two optimization techniques are compared.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-06T03:04:34Z
      DOI: 10.1142/S0218126619500701
  • A Wideband Extended-Dynamic-Range Successive Detection Logarithmic
           Amplifier Based on 0.15 [math]m GaAs pHEMT Technology
    • Authors: Nader Javadifar, Massoud Dousti, Hassan Hajghassem
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper puts forward an extended-dynamic-range successive detection logarithmic amplifier (SDLA) for [math]-band (18–26.5[math]GHz) applications. A novel single-transistor power detection unit (PDU) is used instead of a conventional rectifier to effectively improve the dynamic range–bandwidth product of the amplifier. Circuit analysis and mathematical modeling are performed for the proposed PDU and the SDLA, respectively. Transistor level design is carried out for the whole circuit using 0.15[math][math]m GaAs pseudomorphic high electron mobility transistor (pHEMT) technology. The SDLA presents a wide dynamic range of 75[math]dB with a [math] 1.5[math]dB logarithmic error, over the entire band of interest, and consumes 340[math]mW from [math] 2.5[math]V and –0.8[math]V power supplies. All requirements are verified in post-layout simulation using ADS software. Thermal simulation and statistical yield analysis are performed to ensure the robustness of the proposed architecture.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-06T03:04:32Z
      DOI: 10.1142/S0218126619500695
  • A Digital–Controlled Soft-Start Circuit for Negative Output
           DC–DC Converter
    • Authors: Yan-Ming Li, Xiao-Li Xi, Hao Zhang, Zhong-Hui Chen, Jian Sun, Yang Luo, Hai-Qin Jin, Zan Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To suppress the inrush current and overshoot voltage generated at the start-up stage of Buck–Boost converter, a digital–controlled soft-start circuit based on digital-to-analog converter (DAC) control technology is proposed in this paper. The power consumption of the circuit is zero and the circuit is also keeps the characteristics of simple structure and high reliability. The circuit has been integrated into a Buck–Boost converter with negative voltage output by using the 0.18[math][math]m CDMOS high voltage process. The experimental results show that this circuit can effectively suppress the rush current, and the output voltage drops smoothly from 0 to the adjustment value, [math][math]V.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-04T05:52:09Z
      DOI: 10.1142/S0218126619500671
  • Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal
           Convex Faulty Region
    • Authors: Munshi Mostafijur Rahaman, Prasun Ghosal, Tuhin Subhra Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Reliability of a Network-on-Chip (NoC) relies vastly upon the efficiency of handling faults. Faults those lead to trouble during on-chip communication process are basically of two types namely soft and hard. Here, hard faults are considered. Hard faults may be caused due to failure of links, routers, or other processing units. These are mainly dealt with fault-tolerant routing algorithms or by employing redundant hardware. Multiple faulty nodes are being avoided by acquiring region-based approaches. Most of the fault-tolerant routing techniques are designed on homogeneous faulty regions where some active nodes also act as deactivated nodes to build the region homogeneous. On the other hand, adaptive routing on nonhomogeneous faulty regions increases load on its boundary and most of them does not assure deadlock freeness. This paper proposes a deadlock-free adaptive fault-tolerant NoC routing named F-Route-NoC-Mesh (FRNM) ignoring any virtual channel on orthogonal convex faulty regions. Contributions of this work focus on balancing network traffic by assuming a virtual faulty block boundary and routing packets through this virtual boundary. Destination does not exist within that virtual faulty block regions to reduce load on the boundary of orthogonal faulty regions. Thus, this work is aimed at acquiring proper incorporation of procedures being able to reach fault-tolerant degree, routing efficiency and performance enhancement. Using the proposed algorithm (FRNM), a fault block model-based approach is developed. Significant improvements of average latency (43.37% to 60.44%), average throughput (4.18% to 90.81%) and power consumption (5.93% to 33.28%) are achieved over the state-of-the-art by using a cycle accurate simulator.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-04T05:52:09Z
      DOI: 10.1142/S0218126619500555
  • Small-Signal Modeling of the LLC Half-Bridge Resonant Converter
    • Authors: Jianguang Ma, Xueye Wei, Liang Hu, Junhong Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a small-signal modeling method for building an LLC half-bridge resonant converter. In recent years, the LLC half-bridge resonant converter has attracted the attention of many researchers because of its high-power conversion efficiency and high-power density. Generally, the LLC half-bridge resonant converter consists of many passive components, including stray and parasitic elements, resulting in a high-order system. Because the fundamental harmonic approximation (FHA) method for an LLC resonant converter only considers the fundamental harmonic and neglects higher harmonics, it is not accurate and introduces large errors in a higher-order system. In this paper, according to the operation principle of the LLC half-bridge resonant converter, a small-signal model is established. Based on the small-signal model, the input-to-output and control-to-output transfer function is derived. The experimental result verified that the proposed model yields a high accuracy, thereby highlighting the usefulness and versatility of the proposed model over other existing models.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-04T05:52:09Z
      DOI: 10.1142/S0218126619500634
  • Electronically Tunable Third-Order Quadrature Oscillator Using VDTAs
    • Authors: Hua-Pin Chen, San-Fu Wang, Yu-Nan Chen, Qi-Geng Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This study proposes a new electronically tunable third-order quadrature oscillator using two multi-output voltage difference transconductance amplifiers (VDTAs) and three grounded capacitors. The proposed circuit provides three quadrature voltage outputs, two high-impedance quadrature current outputs, and one high-impedance current output with controllable amplitude. The proposed circuit can provide amplitude modulation/amplitude shift keying signals when the input bias current of the second VDTA is a modulating signal. The oscillation condition and oscillation frequency can be separately adjusted by the input bias currents of two multi-output VDTAs, and it is suitable for use on custom sensor networks. Experimental and H-Spice simulation results are given to confirm theoretical analyses.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-04T05:52:08Z
      DOI: 10.1142/S021812661950066X
  • DHC: A Distributed Hierarchical Clustering Algorithm for Large Datasets
    • Authors: Wei Zhang, Gongxuan Zhang, Xiaohui Chen, Yueqi Liu, Xiumin Zhou, Junlong Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Hierarchical clustering is a classical method to provide a hierarchical representation for the purpose of data analysis. However, in practical applications, it is difficult to deal with massive datasets due to their high computation complexity. To overcome this challenge, this paper presents a novel distributed storage and computation hierarchical clustering algorithm, which has a lower time complexity than the standard hierarchical clustering algorithms. Our proposed approach is suitable for hierarchical clustering on massive datasets, which has the following advantages. First, the algorithm is able to store massive dataset exceeding the main memory space by using distributed storage nodes. Second, the algorithm is able to efficiently process nearest neighbor searching along parallel lines by using distributed computation at each node. Extensive experiments are carried out to validate the effectiveness of the DHC algorithm. Experimental results demonstrate that the algorithm is 10 times faster than the standard hierarchical clustering algorithm, which is an effective and flexible distributed algorithm of hierarchical clustering for massive datasets.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-04T05:52:07Z
      DOI: 10.1142/S0218126619500658
  • Bifurcation Control and Complex Dynamics in Field-Oriented Control of a
    • Authors: W. Souhail, H. Khammari, M. F. Mimouni
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The general purpose of this paper is to develop new aspects of bifurcation structures in a 3D parametric space. Identification of generic bifurcation structures in former studies was based on the arrangement of bifurcation curves in the parameter plane. So by analogy to such studies, we define the bifurcation surface in 3D parameter space as the main feature of the said generic structures. The implementation of this idea is made on the permanent magnet synchronous machine (PMSM) whose speed is regulated with a field-oriented control (FOC). Sufficient conditions are given for the existence of three main bifurcations: limit point (LP), Hopf (H) and Bogdanov–Takens (BT). Starting from bifurcation curves traced in a parameter plane and changing a third parameter, a qualitative bifurcation surface is constructed in a 3D parametric space. This led to underline the increasing complexity of the bifurcation structures when dealing with more than two parameters. This study put into evidence not only the complex behavior of PMSM, but stands as a starting point for a new formalism on the bifurcation structures in a 3D parametric space.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-06-01T06:08:20Z
      DOI: 10.1142/S0218126619300046
  • Fast Transaction-Level Model for Direct Memory Access Controller
    • Authors: Mona Safar, Magdy A. El-Moursy, Ahmed Tarek, Ahmed Emad, Ahmed Hesham, Ashraf Salem, Mohsen Mahroos
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Transaction-Level Modeling (TLM) has been widely used in system-level design in the past few years. Simulation speed of Virtual Platforms (VPs) depends mainly on the transactions which are initiated by the Programmer’s View (PV) models of the VP devices. PV models are required to run at highest simulation speed. Data bus width as a hardware (HW) parameter should not reduce simulation speed of the modeled transactions. Furthermore, HW-related parameters should only be accounted for when considering timing of the models. A fast SystemC-TLM model is developed for the widely used ARM PrimeCell PL080 DMAC IP. The performance of the proposed model is validated against a developed RTL model for the same device. The effect of the transactions granularity on simulation speed is determined. Different programmed transfers are simulated and compared with open-source Quick Emulator (QEMU)-based models. The developed model is compared with the developed RTL, the open-source QEMU model, and the existing ARM Fast Model (AFM). It is shown that simulation time of the developed model is reduced by two orders of magnitude as compared to the other existing models.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-05-28T03:50:03Z
      DOI: 10.1142/S0218126619500592
  • Regression-Based Prediction for Task-Based Program Performance
    • Authors: Isil Oz, Muhammad Khurram Bhatti, Konstantin Popov, Mats Brorsson
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As multicore systems evolve by increasing the number of parallel execution units, parallel programming models have been released to exploit parallelism in the applications. Task-based programming model uses task abstractions to specify parallel tasks and schedules tasks onto processors at runtime. In order to increase the efficiency and get the highest performance, it is required to identify which runtime configuration is needed and how processor cores must be shared among tasks. Exploring design space for all possible scheduling and runtime options, especially for large input data, becomes infeasible and requires statistical modeling. Regression-based modeling determines the effects of multiple factors on a response variable, and makes predictions based on statistical analysis. In this work, we propose a regression-based modeling approach to predict the task-based program performance for different scheduling parameters with variable data size. We execute a set of task-based programs by varying the runtime parameters, and conduct a systematic measurement for influencing factors on execution time. Our approach uses executions with different configurations for a set of input data, and derives different regression models to predict execution time for larger input data. Our results show that regression models provide accurate predictions for validation inputs with mean error rate as low as 6.3%, and 14% on average among four task-based programs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-05-28T03:49:59Z
      DOI: 10.1142/S0218126619500609
  • A 3–14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless
           Applications in 90 nm CMOS
    • Authors: Vikram SINGH, Sandeep Kumar Arya, Manoj Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[math]GHz ultra-wideband (UWB) frequency range using 90[math]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[math]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[math]) less than [math]10.8[math]dB. The proposed LNA achieves an average S[math] of 15.9[math][math][math]0.7[math]dB with a maximum of 16.7[math]dB at 3.0[math]GHz and NF of 1.68–2.7[math]dB for 3.1–10.6[math]GHz UWB frequency range. It provides input reflection coefficient (S[math]) less than [math]10.2[math]dB, reverse isolation (S[math]) less than [math]75.8[math]dB and a NF of 1.68–4.0[math]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[math]dB compression point (P1dB) of [math]13[math]dBm and input third-order intercept point (IIP3) of [math]8[math]dBm at 6[math]GHz. It consumes 20.1[math]mW of power from a 1.2[math]V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-05-28T03:49:57Z
      DOI: 10.1142/S0218126619500567
  • Behavioral Modeling for Parallel- and Cascade-Connected dc–dc
    • Authors: Husan Ali, Xiancheng Zheng, Haider Zaman, Huamei Liu, Xiaohua Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Analysis of distributed energy systems (DESs) is more challenging, as multiple energy sources are connected with different loads through power electronics converters. Modeling and simulation become an essential step during the design stage, prior to actual implementation. These DESs comprised numerous converters in various configurations, e.g., parallel and cascade. This paper presents behavioral modeling technique for interconnected converters that can be used to predict dynamics of overall system. First models are developed for two converters in parallel and cascade configuration using direct approach (DA). The model derivation using DA becomes too complex for larger systems. A new transformation-based approach (TBA) is proposed, which, unlike DA, is simple and can easily be extended to model [math] interconnected converters. In this method, the measured [math]-parameter set is transformed to another domain, equivalent model is computed simply by the addition or multiplication of transformed [math]-parameters and then the equivalent model is transformed back to [math]-parameter set. The modeling techniques are implemented in Matlab/Simulink. The results from DA and TBA are compared, and their close agreement suggests that the new TBA can be used for the analysis of interconnected systems, comprised of multiple parallel and cascade converters.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-05-28T03:49:56Z
      DOI: 10.1142/S0218126619500580
  • Automated Generation of Synchronous Formal Models from SystemC
    • Authors: Hamoudi Kalla, David Berner, Jean-Pierre Talpin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      SystemC is one of the most popular electronic system-level design language and it is embraced by a growing community that seeks to move to a higher level of abstraction. It lacks however a standard way of integrating formal methods and formal verification techniques into a SystemC design flow. In this paper, we show how SystemC descriptions are automatically transformed into the formal synchronous language Signal, while conserving the original structure and enabling the application of formal verification techniques. Signal provides a simple semantics of concurrency and time, and allows verification with an existing theorem prover and model checker. The approach that we propose consists of two steps: the extraction of the structure and the transformation of the behavior. In the first step, SystemC model is analyzed and the structural information is extracted. In the second step, for each SystemC module, the corresponding Signal behavior is generated and filled into the already prepared Signal structure.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-05-28T03:49:51Z
      DOI: 10.1142/S0218126619500610
  • An On-Chip Digital Monostable Multivibrator using Inverter-based Delay
    • Authors: Meilin Wan, Yin Zhang, Ming Zhang, Haoshuang Gu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Monostable multivibrator or one-shot timer is widely used in signal processing. In this paper, a simple and useful way to realize retriggerable monostable multivibrator by using digital logic gates is presented. The basic circuit is composed of one D flip-flop, one NAND gate, one inverter (INV) and two inverter-based delay chains. The width of the output pulse is adjusted through tuning the delay of the inverter-based delay chain. The retriggerable characteristic is realized by resetting all the delayed signals when new triggering occurs in the current monostable period. The basic circuit is designed and fabricated on-chip using a 180[math]nm standard CMOS process with effective area less than 1200[math][math]m2. The retriggerable version is realized in a FPGA platform. Both simulated and measured results are in agreement with the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2018-05-28T03:49:50Z
      DOI: 10.1142/S0218126619200019
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