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  Subjects -> ELECTRONICS (Total: 207 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advanced Materials Technologies     Hybrid Journal   (Followers: 1)
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 8)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 9)
Advances in Electronics     Open Access   (Followers: 100)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 40)
Advancing Microelectronics     Hybrid Journal  
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 28)
Annals of Telecommunications     Hybrid Journal   (Followers: 8)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 16)
Australian Journal of Electrical and Electronics Engineering     Hybrid Journal  
Batteries     Open Access   (Followers: 9)
Batteries & Supercaps     Hybrid Journal   (Followers: 5)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 31)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 2)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 9)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 309)
ECTI Transactions on Computer and Information Technology (ECTI-CIT)     Open Access  
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 2)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 124)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 109)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 103)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elektronika ir Elektortechnika     Open Access   (Followers: 2)
Elkha : Jurnal Teknik Elektro     Open Access  
Emitor : Jurnal Teknik Elektro     Open Access   (Followers: 3)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage     Hybrid Journal   (Followers: 1)
Energy Storage Materials     Full-text available via subscription   (Followers: 4)
EPE Journal : European Power Electronics and Drives     Hybrid Journal  
EPJ Quantum Technology     Open Access   (Followers: 1)
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 9)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
IACR Transactions on Symmetric Cryptology     Open Access   (Followers: 1)
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 102)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 81)
IEEE Embedded Systems Letters     Hybrid Journal   (Followers: 57)
IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology     Hybrid Journal   (Followers: 3)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 52)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Letters on Electromagnetic Compatibility Practice and Applications     Hybrid Journal   (Followers: 4)
IEEE Magnetics Letters     Hybrid Journal   (Followers: 7)
IEEE Nanotechnology Magazine     Hybrid Journal   (Followers: 42)
IEEE Open Journal of Circuits and Systems     Open Access   (Followers: 3)
IEEE Open Journal of Industry Applications     Open Access   (Followers: 3)
IEEE Open Journal of the Industrial Electronics Society     Open Access   (Followers: 3)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 77)
IEEE Pulse     Hybrid Journal   (Followers: 5)
IEEE Reviews in Biomedical Engineering     Hybrid Journal   (Followers: 23)
IEEE Solid-State Circuits Letters     Hybrid Journal   (Followers: 3)
IEEE Solid-State Circuits Magazine     Hybrid Journal   (Followers: 13)
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 367)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 74)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 64)
IEEE Transactions on Autonomous Mental Development     Hybrid Journal   (Followers: 8)
IEEE Transactions on Biomedical Engineering     Hybrid Journal   (Followers: 39)
IEEE Transactions on Broadcasting     Hybrid Journal   (Followers: 13)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 26)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 46)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Geoscience and Remote Sensing     Hybrid Journal   (Followers: 227)
IEEE Transactions on Haptics     Hybrid Journal   (Followers: 5)
IEEE Transactions on Industrial Electronics     Hybrid Journal   (Followers: 75)
IEEE Transactions on Industry Applications     Hybrid Journal   (Followers: 40)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 27)
IEEE Transactions on Learning Technologies     Full-text available via subscription   (Followers: 12)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 80)
IEEE Transactions on Services Computing     Hybrid Journal   (Followers: 4)
IEEE Transactions on Signal and Information Processing over Networks     Hybrid Journal   (Followers: 13)
IEEE Transactions on Software Engineering     Hybrid Journal   (Followers: 79)
IEEE Women in Engineering Magazine     Hybrid Journal   (Followers: 11)
IEEE/OSA Journal of Optical Communications and Networking     Hybrid Journal   (Followers: 16)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 36)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 60)
IET Smart Grid     Open Access   (Followers: 1)
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 14)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 12)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 3)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 10)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 25)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 12)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 38)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 9)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronic Science and Technology     Open Access   (Followers: 1)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 4)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 189)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 10)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal   (Followers: 1)
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 3)
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 11)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 32)
Journal of Power Electronics     Hybrid Journal   (Followers: 2)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 27)
Journal of Signal and Information Processing     Open Access   (Followers: 8)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Microelectronics and Solid State Electronics     Open Access   (Followers: 28)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal   (Followers: 1)
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 2)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 11)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 6)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 57)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Solid State Electronics Letters     Open Access  
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Transactions on Cryptographic Hardware and Embedded Systems     Open Access   (Followers: 2)

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Similar Journals
Journal Cover
Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [119 journals]
  • NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed–Muller Network
           Synthesis Using Parallel Tabular Technique
    • Authors: Apangshu Das, Yallapragada C. Hareesh, Sambhu Nath Pradhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuristic algorithm named nondominated sorting genetic algorithm-II (NSGA-II) has been employed for selecting suitable input polarity of mixed polarity dual Reed–Muller (MPDRM) expansion function to reduce the power-density. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Without performance degradation, the proposed MPDRM approach shows more than 50% improvement in the area and power savings and around 6% peak temperature reduction for the MCNC benchmark circuits than that of earlier literature at the logic level. Algorithmic optimized circuit decompositions are implemented in physical design domain using CADENCE INNOVUS and HotSpot tool and silicon area, power consumption and absolute temperature are reported to validate the proposed technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-07-02T07:00:00Z
      DOI: 10.1142/S021812662020008X
       
  • Increasing Penetration of DERs in Smart Grid Framework: A State-of-the-Art
           Review on Challenges, Mitigation Techniques and Role of Smart Inverters
    • Authors: Sumeet Kumar Wankhede, Priyanka Paliwal, Mukesh K. Kirar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The world is witnessing a transformation from the conventional electrical grid into the smart grid. The smart grid can provide an effective solution to alarming problems associated with a conventional grid with increased reliability, efficiency, and sustainability. Integration of distributed energy resources (DERs) comprising of renewable energy sources (RESs) is a vital component of the smart grid. DERs not only can provide a viable solution for environmental concerns arising due to conventional fossil fuel-based plants, but can also contribute towards the system reliability. However, the integration of DERs is associated with several challenges.  Thus, the successful deployment of DERs in smart grid framework calls for a comprehensive analysis. This paper presents an exhaustive review of various challenges associated with increased penetration of DERs. An organized classification of various technical challenges along with their mitigation measures has been critically reviewed. Smart inverters equipped with advanced control structure are emerging as a potential solution to address these challenges effectively. Hence, a review of smart inverter along with its functional capabilities has also been discussed in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-07-02T07:00:00Z
      DOI: 10.1142/S0218126620300147
       
  • Novel Adaptive Controller for Buck Converter with High Resource Efficiency
           and Low Computational Complexity
    • Authors: Fatemeh Abdi, Parviz Amiri, Mohammad Hosien Refan, Manfred Reddig, Ralph Kennel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Power converters are used in a wide range of industrial processes. Computational complexity, tracking ability, and calculation accuracy are the main parameters that affect the switching performance of power converters. One of the major parts of switch-mode power converters is the controllers which are essential for proper operation. A new adaptive controller is proposed to reduce the computational complexity, the algorithm is presented based on Improved Variable Forgetting Factor (IVFF), Leading Dichotomous Coordinate Descent (DCD), and Exponentially-weighted Recursive Least Square (ERLS). The proposed method estimates the system coefficients with 98% accuracy. The settling time of the output voltage is 0.008[math]ms which is faster than other algorithms. According to Leading DCD, this structure needs no multiplier and divider blocks. VFF leads to the improvement of the tracking ability and convergence rate in the system variations. This structure can be implemented on any application that needs an optimal controller. The Vedic mathematics as a multiplier operation is used in the structure of the improved VFF for reducing the calculation delay and area. The error of the proposed method converges to zero with lower than 60 iterations. In other words, the proposed algorithm calculates the optimal coefficients with lower than 50 iterations and is faster than another algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-07-02T07:00:00Z
      DOI: 10.1142/S0218126620502308
       
  • One-Bit [math]-Encoded Stimulus Generation for On-Chip ADC Test
    • Authors: Shakeel Ahmad, Jerzy Dąbrowski
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an application of the [math] modulation technique to the on-chip dynamic test for analog-to-digital converters (ADCs). The required stimulus such as a single- or two-tone signal is encoded into one-bit [math] sequence, which is applied to an ADC under test through a driving buffer and a simple low-pass reconstruction filter. By a systematic approach, we select the order and type of a [math] modulator and develop a frequency plan suitable for the spectral measurement. In this way, we achieve a high dynamic range suitable for spectral harmonic and intermodulation distortion tests for ADCs. For high frequency measurements (up to the Nyquist frequency), we propose a novel low-pass/band-pass modulation scheme that allows to avoid harmful effects of the low-frequency quantization noise. Also we address the distortion components which originate from the buffer imperfections for a nonreturn-to-zero waveform representing the encoded stimulus. We show that the low-frequency distortion components can be cancelled by using a simple iterative predistortion technique supported by measurements with a DC-calibrated ADC. By correlation between low- and high-frequency components also the high frequency distortions can be largely reduced. The presented techniques are illustrated by simulation results of an ADC under test.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-07-02T07:00:00Z
      DOI: 10.1142/S021812662050245X
       
  • Social Recommendation Combining Trust Relationship and Distance Metric
           Factorization
    • Authors: Ming Ye, Yuanle Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The recommender system predicts user preferences by mining user historical behavior data. This paper proposes a social recommendation combining trust relationship and distance metric factorization. On the one hand, the recommender system has a cold start problem, which can be effectively alleviated by adding social relations. Simultaneously, to improve the problem of sparse trust matrix, we use the Jaccard similarity coefficient and the Dijkstra algorithm to reconstruct the trust matrix and explore the potential user trust relationship. On the other hand, the traditional matrix factorization algorithm is modeled by the user item potential factor dot product, however, it does not satisfy the triangle inequality property and affects the final recommender effect. The primary motivator behind our approach is to combine the best of both worlds, mitigate the inherent weaknesses of each paradigm. Combining the advantages of the two ideas, it has been demonstrated that our algorithm can enhance recommender performance and improve cold start in recommender systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-07-02T07:00:00Z
      DOI: 10.1142/S0218126620502497
       
  • Alleviation of Data Timing Channels in Normalized/Subnormal Floating Point
           Multiplier
    • Authors: Senthil Pitchai, VE. Jayanthi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Floating point (FP) multiplication goes down in the scientific application when it sustains the subnormal inputs either in the implementation of software or hardware. Any high-level language executes the FP instructions in the graphics processing unit (GPU) and floating-point unit (FPU) for supporting the normalized numbers alone. In FP multiplication, execution times for normalized and subnormal numbers are not equal. Execution time variations create unintentional delay and data timing channels (DTCs). A circuit is proposed for floating-point multiplication to minimize the unintentional delay for the holistic support of subnormal numbers. In this proposed four-path FP multiplication, the circuit produces the four types of output in four paths having different delays for all cases of input combination. These four paths are establishing the DTCs. A maximum delay path is taken into account to combine and equalize the four paths into a single output path. Two levels of the control circuit combine the four paths to a single path for reducing the DTC effect. To evaluate the performance after path equalization, the proposed FP multiplier is implemented in Stratix-IV and Cyclone-IV FPGAs with a delay of 57.25 and 82.82 ns, respectively. Here, eight pipeline stages reduce the delay and improve the operating speed of the entire circuit. Stage delay and operating speed for this FP multiplier in both FPGA implementations are 12.44 and 16.86[math]ns, and 153.19 and 116.78[math]MHz, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-07-02T07:00:00Z
      DOI: 10.1142/S0218126621200012
       
  • Device-Circuit Interaction and Performance Benchmarking of Tunnel
           Transistor-Based Ex-OR Gates for Energy Efficient Computing
    • Authors: Sadulla Shaik
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper explores the design and analysis of 20[math]nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300[math]mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300[math]mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20[math]nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100[math]mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126620502357
       
  • Power Efficient and High-Accuracy Approximate Multiplier with Error
           Correction
    • Authors: Zhixi Yang, Xianbin Li, Jun Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126620502412
       
  • Optimal Real Power Penetration to Solar PV-FED Double Boost Integrated
           Multilevel Converter with Improved Power Quality
    • Authors: B. N. Ch. V. Chakravarthi, G. V. Siva Krishna Rao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In grid-connected solar PV system, power quality gets affected seriously due to the variable real power penetration. The transformer is mandatory to integrate and isolate the solar PV and powered network. However, due to presence of this transformer, size and cost of the entire solar PV station get increased and it requires more space while supplying poor quality of power. In order to overcome this drawback, this paper proposes a double boost integrated multilevel inverter to inject the power into utility grid. In addition, the optimal control strategy is used to tap maximum power generation from solar PV and injected into grid with improved power quality. This paper presents an adaptive digital hysteresis current control approach to penetrate optimal power into grid. To validate the proposed work, the simulation results are carried out using PSCAD/EMDTC software. Furthermore, to confirm theoretical study and simulation study, the experimental test was performed and detailed results with validation were presented in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126620502564
       
  • Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth
           Applications
    • Authors: Sumalya Ghosh, Bishnu Prasad De, K. B. Maji, R. Kar, D. Mandal, A. K. Mal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[math]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[math][math]m CMOS process. The designed LNA shows a gain of 15.28[math]dB, NF of 0.376[math]dB, the power dissipation of 936[math][math]W and IIP3 of [math][math]dBm at 2.4[math]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[math]mW[math] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126620502618
       
  • Depth-Based Real-Time Gait Recognition
    • Authors: Adnan Ramakić, Diego Sušanj, Kristijan Lenac, Zlatko Bundalo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Each person describes unique patterns during gait cycles and this information can be extracted from live video stream and used for subject identification. In recent years, there has been a profusion of sensors that in addition to RGB video images also provide depth data in real-time. In this paper, a method to enhance the appearance-based gait recognition method by also integrating features extracted from depth data is proposed. Two approaches are proposed that integrate simple depth features in a way suitable for real-time processing. Unlike previously presented works which usually use a short range sensors like Microsoft Kinect, here, a long-range stereo camera in outdoor environment is used. The experimental results for the proposed approaches show that recognition rates are improved when compared to existing popular gait recognition methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126620502667
       
  • An Adaptive Multi-Mode PWM Control PSR Flyback Converter
    • Authors: Chang Chen, Lei Wang, Changyuan Chang, Xiong Han
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an adaptive multi-mode PWM control PSR flyback converter is proposed. In constant voltage (CV) mode, the converter adopts primary-side regulate (PSR) scheme to detect load information through the auxiliary winding, which reflects the load information on the voltage of [math]. The converter adjusts the switching frequency according to the voltage of [math] under different load conditions, realizing adaptive multi-mode PWM control to significantly improve light- load efficiency and thus the overall average efficiency. Besides, it does not give compromise to other system performance, such as audible noise, standby power consumption, and regulation. To verify the feasibility and performance of the proposed circuit, the converter has been designed and fabricated in HHGRACE_0.35[math][math]m BCD process and verified in a 5V/1A circuit prototype. The experimental results show that 25% load power efficiency of the proposed converter is 78.1%, which is improved by up to 3.4% compared to the conventional converter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126621500018
       
  • Automatic Question Answering System Based on Convolutional Neural Network
           and Its Application to Waste Collection System
    • Authors: Chuan Jiang, Qianmin Su, Lele Zhang, Bo Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As a typical cyber-physical-social system (CPSS), the waste collection system profoundly changes the current waste processing mode and greatly relieves the dilemma of waste disposal. However, the existing waste collection system does not provide the function that guides people to deliver the waste into the correct trash bin. In order to improve the efficiency of waste collection system, we propose an automatic question answering system based on convolutional neural network (CNN) to help people classify waste correctly. The construction process of automatic question answering system is divided into the following steps. We first construct a question answering dataset about waste classification, in which question answering pairs from the four waste categories (recyclable waste, harmful waste, dry waste, and wet waste) are included. After the dataset is constructed, we perform text preprocessing on the dataset, which includes denoising, Chinese word segmentation, and removing stop words. After text preprocessing, we use the Word2vec model as feature representation. Then, we construct a CNN and utilize the word embeddings as an input to train model. Finally, we deploy the trained model to the waste collection system, which can answer the question of waste classification that people ask. We also present a comparative analysis of the proposed method and traditional machine learning methods. The experiment shows that the proposed method has higher accuracy of waste classification than that of traditional machine learning methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-30T07:00:00Z
      DOI: 10.1142/S0218126621500134
       
  • An Improved Water Surface Images Segmentation Algorithm Based on the Otsu
           Method
    • Authors: Ning Li, Xin Lv, Shoukun Xu, Bo Li, Yuwan Gu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The one-dimensional Otsu method is an adaptive threshold method. It obtains the optimal threshold for image segmentation by the maximum between-class variance, without considering the minimum within-class variance. As the background of water surface image is mostly uniform, using this feature, the threshold selection tactics adopt the combination of the one-dimensional Otsu method and the uniformity measurement, proposes the threshold segmentation method based on uniformity measurement, and adopts the performance evaluation method based on GT image to compare the segmentation result. Experimental results demonstrate that effectiveness of the improved Otsu method is generally better than the traditional Otsu method, and the other four commonly used threshold segmentation methods for the water surface image, which improves the segmentation accuracy of such images and reduces the segmentation error rate. At the same time, as the water surface image is usually affected by light intensity, water ripple and other factors, this paper also adopts the relevant correction algorithm to further improve the segmentation accuracy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-23T07:00:00Z
      DOI: 10.1142/S0218126620502515
       
  • Comprehensive and Systematic Study on the Fault Tolerance Architectures in
           Cloud Computing
    • Authors: Vahid Mohammadian, Nima Jafari Navimipour, Mehdi Hosseinzadeh, Aso Darwesh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Providing dynamic resources is based on the virtualization features of the cloud environment. Cloud computing as an emerging technology uses a high availability of services at any time, in any place and independent of the hardware. However, fault tolerance is one of the main problems and challenges in cloud computing. This subject has an important effect on cloud computing, but, as far as we know, there is not a comprehensive and systematic study in this field. Accordingly, in this paper, the existing methods and mechanisms are discussed in different groups, such as proactive and reactive, types of fault detection, etc. Various fault tolerance techniques are provided and discussed. The advantages and disadvantages of these techniques are shown on the basis of the technology that they have used. Generally, the contributions of this research provide a summary of the available challenges associated with fault tolerance, a description of several important fault tolerance methods in the cloud computing and the key regions for the betterment of fault tolerance techniques in the future works. The advantages and disadvantages of the selected articles in each category are also highlighted and their significant challenges are discussed to provide the research lines for further studies.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-22T07:00:00Z
      DOI: 10.1142/S0218126620502400
       
  • Effective Data Storage and Dynamic Data Auditing Scheme for Providing
           Distributed Services in Federated Cloud
    • Authors: A. M. Sermakani, D. Paulraj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, many organizations and industries are using the cloud computing technologies for exchanging the resources and their confidential data. For this purpose, many cloud services are available and also provide the facility to categorize their users as private and public users for accessing their own data from private cloud and public cloud. The combination of these two clouds is called federated cloud which facilitates to allow both kinds of cloud users for accessing their own data on same cloud database. In this scenario, the authorization and authentication process is becoming complex task on cloud. For providing the facility to access their own data only from federated cloud, a new secured data storage and retrieval algorithm called AES and Triple-DES-based Secured Storage and Retrieval Algorithm (ATDSRA) are proposed for storing the private and public cloud user’s data securely on cloud database. Here, the TDES is used for encrypting the input data, data merging and aggregation methods were used for grouping the encrypted input data. Moreover, a new dynamic data auditing scheme called CRT-based Dynamic Data Auditing Algorithm (CRTDDA) is proposed for conducting the cloud data auditing over the federated cloud and also restricting the data access. The proposed new auditing mechanism that is able to protect the stored data from access violence. In addition, the standard Table64 is used for encryption and decryption processes. The experimental results of this work proves the efficiency of the proposed model in terms of security level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-22T07:00:00Z
      DOI: 10.1142/S021812662050259X
       
  • A Cap-less Voltage Spike Detection and Correction Circuit for Low Dropout
           Regulator
    • Authors: P. Manikandan, B. Bindu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents [math] and [math] and pull-down currents [math] and [math]. These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage [math]. The proposed circuit detects the output voltage via [math] and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180[math]nm technology and the simulation result shows that the LDO has good load transient response with 190[math]ns settling time and 170[math]mV voltage spike over 1[math]mA to 100[math]mA load current range.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-18T07:00:00Z
      DOI: 10.1142/S0218126620200091
       
  • Effective Algorithms for Scheduling Workflow Tasks on Mobile Clouds
    • Authors: Heng Li, Yaoqin Zhu, Meng Zhou, Yun Dong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In mobile cloud computing, the computing resources of mobile devices can be integrated to execute complicated applications, in order to tackle the problem of insufficient resources of mobile devices. Such applications are, in general, characterized as workflows. Scheduling workflow tasks on a mobile cloud system consisting of heterogeneous mobile devices is a NP-hard problem. In this paper, intelligent algorithms, e.g., particle swarm optimization (PSO) and simulated annealing (SA), are widely used to solve this problem. However, both PSO and SA suffer from the limitation of easily being trapped into local optima. Since these methods rely on their evolutionary mechanisms to explore new solutions in solution space, the search procedure converges once getting stuck in local optima. To address this limitation, in this paper, we propose two effective metaheuristic algorithms that incorporate the iterated local search (ILS) strategy into PSO and SA algorithms, respectively. In case that the intelligent algorithm converges to a local optimum, the proposed algorithms use a perturbation operator to explore new solutions and use the newly explored solutions to start a new round of evolution in the solution space. This procedure is iterated until no better solutions can be explored. Experimental results show that by incorporating the ILS strategy, our proposed algorithms outperform PSO and SA in reducing workflow makespans. In addition, the perturbation operator is beneficial for improving the effectiveness of scheduling algorithms in exploring high-quality scheduling solutions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-18T07:00:00Z
      DOI: 10.1142/S0218126620502552
       
  • Compensation of Non-linear Distortion Effects in MIMO-OFDM Systems Using
           Constant Envelope OFDM for 5G Applications
    • Authors: M. El Ghzaoui, A. Hmamou, J. Foshi, J. Mestoui
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Orthogonal frequency division multiplexing (OFDM) is a multicarrier transmission system that can achieve high data rate over wireless channels. At the same time, multiple input multiple output OFDM (MIMO-OFDM) in wireless communication systems has been exposed to offer significant improvement over wireless technology by providing transmit diversity. It has become a promising technique for high-performance 5G broadband wireless communications. However, the main problem associated with MIMO-OFDM is that its signal exhibits high peak-to-average power ratio (PAPR), which causes nonlinear distortion and consequently performance degradation. Besides, PAPR carries weaknesses such as an increase in power consumption of high power amplifier (HPA) and analog to digital converter (ADC). Thus, 5G base stations will push up power requirements because energy consumption grows with the number of transceiver elements. So, mobile operators must find the right compromise that, on the one hand, guarantees a certain level of performance to a data flow, and, on the other hand, the energy cost generated for the deployment of the network. For this, as part of the management of power consumption, we propose MIMO constant envelope OFDM (MIMO-CE-OFDM) technique. In this work, we used MIMO-CE-OFDM to mitigate the nonlinear effect of HPA and ADC. To perform practical simulations, we have used COST 2100 MIMO channel model. In this paper, a MIMO-CE-OFDM system has been presented and analyzed under COST 2100 channel model conditions. Simulation results are given to illustrate the performance of [math] MIMO-CE-OFDM in the presence of both HPA and ADC nonlinearity. This work shows that the effect of nonlinearity is shown to be negligible on MIMO-CE-OFDM signal.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-18T07:00:00Z
      DOI: 10.1142/S0218126620502576
       
  • Stability and Stabilization of Heterogeneous Switched Systems with
           Mode-Dependent Average Dwell Time via Homogeneous Polynomial Lyapunov
           Functions Approach
    • Authors: Shaohang Yu, Chengfu Wu, Liang Wang, Jia-Nan Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work researches the problem of searching for multiple homogeneous polynomial Lyapunov functions (HPLFs) for heterogeneous switched linear systems. First, a nonconvex optimization condition is constructed to study the stability property of heterogeneous switched systems, where each Lyapunov function candidate reduces dimension to their corresponding matrix eigenvalue. Based on the stability analysis condition, a controller-dependently multiple HPLFs condition is introduced to determine controllers and explores locally minimum mode-dependent average dwell time (LMMDADT). Additionally, the existing properties condition and solvable properties condition of controllers are given in the form of HPLFs. At last, a practical example and a contrast example are both presented to show feasibility of the proposed results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-18T07:00:00Z
      DOI: 10.1142/S0218126620502588
       
  • Low-Complexity MIMO MMSE Receiver with Performance Enhancement via
           Coordinate Interleaving
    • Authors: Serdar Özyurt, Mustafa Öztürk, Enver Çavuş
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multiple-input multiple-output (MIMO) Minimum mean-square error (MMSE) receivers are widely adopted in the latest communication standards and reducing the complexity of these receivers while preserving the error performance is highly desirable. In this work, we study the error performance and implementation complexity of MIMO MMSE receivers when combined with a coordinate interleaved signal space diversity (SSD) technique. Contrary to the well-known trade-off between the error performance and implementation complexity, the proposed system leads to a considerably simplified MIMO MMSE receiver with significant performance gains when compared to the original MIMO MMSE receiver. Unlike the standard MIMO MMSE receiver, the proposed coordinate interleaved technique induces a block diagonal transmit correlation matrix providing both performance enhancement and complexity reduction. The results show that the error performance can be improved more than 10[math]dB with up to 71% computational complexity reduction. The complexity comparison between the original and proposed approaches is also verified by means of field-programmable gate array (FPGA) implementation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-10T07:00:00Z
      DOI: 10.1142/S021812662050231X
       
  • Experimental Realization of Square/Triangular Wave Generator using
           Commercially Available ICs
    • Authors: Atul Kumar, Bhartendu Chaturvedi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper deals with the experimental realization of square/triangular wave generator using commercially available ICs. A prototype of extra-X second generation current conveyor and five passive components are used in the experimental setup. The proposed generator provides both square and triangular waveforms simultaneously in voltage-mode. The circuit enjoys the feature of independent controllability of oscillation frequency via grounded resistor/grounded capacitor. A range of oscillation frequency from 3[math]Hz to 250[math]Hz is easily achieved via variation in one of the grounded resistors for a fixed value of capacitor. Moreover, a range of oscillation frequency from 19.8[math]Hz to 19.2[math]kHz can be achieved through the variation in grounded capacitor. The experimental results show that the performance of the proposed generator is good at operating frequency as low as at 19.8 Hz and as high as 19.2[math]kHz. Therefore, the proposed circuit can operate well from extra-low-frequency range to very-low-frequency range. Furthermore, the maximum nonlinearity of oscillation frequency is found to be 4% only.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-06-02T07:00:00Z
      DOI: 10.1142/S0218126620502242
       
  • A Review on Design of Multiband Bandpass Filter Using Different DGS
           Structures to Enhance the Performance
    • Authors: Kapil Kumar, Amit Dixit, Pradyot Kala, Savita Yadav, Reena Pant
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we discussed about the work done by researchers for the enhancement of performance of a multiband BPF by introducing different defected ground structure (DGS) geometries. A DGS structure on a conventional inductively coupled band pass filter is used to miniaturize the resonator. By introducing a DGS on the transversal dimension of the CPW, it enhances filter performance. The DGS cell also transforms a single band to a multiband BPF by using this structure. The design technique of the filters with the DGS can be explained at very high frequencies in GHz ranges and give very accurate simulated and measured results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-28T07:00:00Z
      DOI: 10.1142/S0218126620300123
       
  • A Low-Cost Image Encryption Method to Prevent Model Stealing of Deep
           Neural Network
    • Authors: Wei Jiang, Zicheng Gong, Jinyu Zhan, Zhiyuan He, Weijia Pan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Model stealing attack may happen by stealing useful data transmitted from embedded end to server end for an artificial intelligent systems. In this paper, we are interested in preventing model stealing of neural network for resource-constrained systems. We propose an Image Encryption based on Class Activation Map (IECAM) to encrypt information before transmitting in embedded end. According to class activation map, IECAM chooses certain key areas of the image to be encrypted with the purpose of reducing the model stealing risk of neural network. With partly encrypted information, IECAM can greatly reduce the time overheads of encryption/decryption in both embedded and server ends, especially for big size images. The experimental results demonstrate that our method can significantly reduce time overheads of encryption/decryption and the risk of model stealing compared with traditional methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-28T07:00:00Z
      DOI: 10.1142/S0218126620502527
       
  • Generalized Hybrid Continuous Mode for Designing Broadband Power
           Amplifiers
    • Authors: Decheng Gan, Weimin Shi, Muhammad Furqan Haider
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      It has been widely validated that continuous working modes are powerful theories for designing broadband power amplifier (BPA). Theoretically, the conduction angle of all continuous-mode power amplifiers (PAs) is 180∘ (class-B-biased). However, in practice, these PAs are always biased in class-AB condition. Thus, continuous-mode PAs biased in class-AB condition should be researched. This paper generalizes the theory of hybrid continuous mode (HCM) for implementing broadband power amplifiers. The intrinsic drain current waveform of HCM biased above the pinch-off point (conduction angle is larger than 180∘) is first derived. Then, the impedance space of the generalized HCM (class-AB-biased) is explored and analyzed. The conclusion is that the generalized HCM possesses a shifted fundamental impedance space along with the enlargement of conduction angle. For validating the proposed theory, a broadband PA working over 1.6–3.0[math]GHz is implemented. Experimental results indicate that the designed BPA achieves a saturation power of 40.3–42.7[math]dBm and a drain efficiency of 64.3–74.4%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-21T07:00:00Z
      DOI: 10.1142/S0218126620502369
       
  • A New Secure and Efficient Approach for TRNG and Its Post-Processing
           Algorithms
    • Authors: Selman Yakut, Taner Tuncer, Ahmet Bedri Özer
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Random numbers are important parameters for the security of cryptographic applications. In this study, a secure and efficient generator is proposed to generate random numbers. The first part of the generator is a true random number generator that consists of chaotic systems implemented on FPGA. The second part of the generator is a post-processing algorithm used to overcome the problems that emerge from the generator or environmental factors. As the post-processing algorithm, Keccak, the latest standard of hash algorithm, was rearranged and used. Random numbers with the proposed approach meet the security requirements for cryptographic applications. Furthermore, the NIST 800-22 test suite and autocorrelation test are used to ensure the generated numbers have no statistical weakness. The successful test results demonstrate the security of the generated numbers. An important advantage of the proposed generator does not cause any data loss and perform 100% efficiency although data loss can be up to 70% in some post-processing algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-21T07:00:00Z
      DOI: 10.1142/S0218126620502448
       
  • A Novel Floating/Grounded Meminductor Emulator
    • Authors: Hasan Sozen, Ugur Cam
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Meminductor is a nonlinear two-terminal element with storage energy and memory ability. To date, meminductor element is not available commercially as memristor and memcapacitor are. Therefore, it is of great significance to implement a meminductor emulator for breadboard experiment. In this paper, a flux-controlled floating/grounded meminductor emulator without a memristor is presented. It is built with commercially available off-the-shelf electronic devices. It consists of single operational transconductance amplifier (OTA), single multiplier, two second-generation current conveyors (CCIIs), single current-feedback operational amplifier (CFOA) and single operational amplifier. Using OTA device introduces an additional control parameter besides frequency and amplitude values of applied voltage to control the area of pinched hysteresis loop of meminductor. Mathematical model of proposed emulator circuit is given to describe the behavior of meminductor circuit. The breadboard experiment is performed using CA3080, AD844, AD633J and LM741 for OTA, CCII–CFOA, multiplier and operational amplifier, respectively. Simulation and experimental test results are given to verify the theoretical analyses. Frequency-dependent pinched hysteresis loop is maintained up to 5 kHz. The presented meminductor emulator tends to work as ordinary inductor for higher frequencies.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-21T07:00:00Z
      DOI: 10.1142/S0218126620502473
       
  • Alphanumeric Pattern Recognition by Memristive Crossbar Circuit using
           Perceptron Learning Rule
    • Authors: Muhammad Khalid
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an alphanumeric pattern recognition approach based on memristive crossbar circuit using perceptron learning rule. The proposed approach incorporates a memristive crossbar-based learning and training circuit (TC) module (i.e., synaptic network) and an operational amplifier (op-amp)-based neuron. Alphanumeric patterns, such as alphabets (A–Z) and numerics (0–9), are applied on the TC module and it adjusts the synaptic weights using the perceptron learning rule. The TC module includes 16 inputs, which are interconnected to nine output neurons through memristors. The input and output patterns are represented through [math] and [math] matrix pixels, respectively. This proposed circuit has implemented all alphanumeric patterns, such as alphabets (A–Z) and numerics (0–9), successfully. However, only the pattern “A” is illustrated in detail for better understanding. SPICE simulation results supported by analytical calculations of pattern “A” are reported. The average power consumption for the proposed approach using memristor is 77.77% lower than the conventional MOSFET-based approach, apart from significant saving of silicon overhead in contrast to its counterpart approach.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-16T07:00:00Z
      DOI: 10.1142/S021812662050228X
       
  • A New Chaotic Jerk System with Double-Hump Nonlinearity
    • Authors: Debabrata Biswas
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we report a new third-order chaotic jerk system with double-hump (bimodal) nonlinearity. The bimodal nonlinearity is of basic interest in biology, physics, etc. The proposed jerk system is able to exhibit chaotic response with proper choice of parameters. Importantly, the chaotic response is also obtained from the system by tuning the nonlinearity preserving its bimodal form. We analytically obtain the symmetry, dissipativity and stability of the system and find the Hopf bifurcation condition for the emergence of oscillation. Numerical investigations are carried out and different dynamics emerging from the system are identified through the calculation of eigenvalue spectrum, two-parameter and single parameter bifurcation diagrams, Lyapunov exponent spectrum and Kaplan–Yorke dimension. We identify that the form of the nonlinearity may bring the system to chaotic regime. Effect of variation of parameters that controls the form of the nonlinearity is studied. Finally, we design the proposed system in an electronic hardware level experiment and study its behavior in the presence of noise, fluctuations, parameter mismatch, etc. The experimental results are in good analogy with that of the analytical and numerical ones.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-07T07:00:00Z
      DOI: 10.1142/S0218126620502321
       
  • Approximate Compressor-Based Multiplier Design Methodology for
           Error-Resilient Digital Signal Processing
    • Authors: Zhixi Yang, Xianbin Li, Jun Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[math]dB for image processing; similarly, with a decrease of 0.3[math]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-07T07:00:00Z
      DOI: 10.1142/S0218126620502333
       
  • Effective Real-Time Scheduling Optimization for Multi-Functional
           Mixed-Criticality Systems
    • Authors: Nan Gao, Weiqi Shi, Xin Peng, Jing Huang, Cheng Xu, Guoqi Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The heterogeneous distributed embedded systems integrated of multiple functions with different criticality levels are multi-functional mixed-criticality systems (MMCSs). The state-of-the-art work has studied the real-time scheduling in MMCS; however, it is not well designed in system switching mechanism and operation which may lead to missing the deadlines of high-criticality functions and redundant operation. In this study, we improve and optimize the problem by developing an algorithm called rearrangement-based scheduling for MMCS (RSM). The RSM algorithm optimizes the following two main aspects. The first aspect is optimizing system-criticality switching mechanisms, including system criticality changed up and down. The second aspect is the effective operation in system-criticality switching to reduce redundant operation. Experiments are performed, and results show that the RSM algorithm can achieve lower overall makespan and deadline miss ratios (DMRs) than the existing algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-06T07:00:00Z
      DOI: 10.1142/S0218126620502266
       
  • Low-Power Passive/Active UHF RFID Tag Transceiver with Frequency Locked
           On-chip Oscillator
    • Authors: Peiqing Han, Zhaofeng Zhang, Niansong Mei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A reconfigurable architecture is presented to be compatible with conventional passive operating mode and active mode for ultrahigh frequency (UHF) and radio-frequency identification (RFID) tag. The transceiver with frequency locked on-chip oscillator is proposed to increase the read range of RFID system and the lifetime of tag. The transceiver is fabricated in 0.18[math][math]m standard CMOS process with the active area of 0.246[math]mm2. For passive mode, the sensitivity of tag is [math][math]dBm. For the active mode, the sensitivity is [math][math]dBm only consuming 1.2[math][math]W under the supply voltage of 0.8[math]V. The output power is [math][math]dBm for active transmitting mode and the power consumption is 450[math][math]W under the supply voltage of 1[math]V.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-06T07:00:00Z
      DOI: 10.1142/S0218126620502345
       
  • Improved Whale Optimized MLP Neural Network-Based Learning Mechanism for
           Multiuser Detection in MIMO Communication System
    • Authors: R. Umamaheswari, M. Ramya Princess, P. Nirmal Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Direct-Sequence Code Division Multiple Access (DS-CDMA) is a digital method to spread spectrum modulation for digital signal transmission. We propose to detect signal in DS-CDMA communication using the learning mechanism. Initially, the user signals are spread using the respective pseudo-noise (PN) code where the input signal is multiplied with the code which is then modulated using the quadrature phase shift keying (QPSK) modulator. The modulated signal is then transmitted in a 3G/4G channel considering all types of fading. The transmitted signal is received by the antenna array which is performed by demodulation. We propose to adaptively assign the weights by employing Improved Whale Optimized Multi-Layer Perceptron Neural Network (IWMLP-NN)-based learning mechanism. To design IWMLP-NN, Improved Whale Optimization Algorithm is combined with multilayer perceptron neural network. This is used instead of the normal Multiple Signal Classification (MUSIC) and least mean squares (LMS)/root-mean-square (RMS) algorithms used in beam-forming networks. After assigning weight through IWMLP-NN-based learning mechanism, we de-spread to get the original user data. We have compared our proposed technique with the normal techniques with the help of plots of Bit Error Rate (BER) versus Signal-to-Noise Ratio (SNR). We use both the AWGN channel and fading channel for analysis. Experimental results prove that our proposed method achieves better BER performance results even with deep fading.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-05-06T07:00:00Z
      DOI: 10.1142/S0218126620502394
       
  • Energy-Efficient Scheduling Optimization for Parallel Applications on
           Heterogeneous Distributed Systems
    • Authors: Nan Gao, Cheng Xu, Xin Peng, Haibo Luo, Wufei Wu, Guoqi Xie
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Designing energy-efficient scheduling algorithms on heterogeneous distributed systems is increasingly becoming the focus of research. State-of-the-art works have studied scheduling by combining dynamic voltage and frequency scaling (DVFS) technology and turning off the appropriate processors to reduce dynamic and static energy consumptions. However, the methods for turning off processors are ineffective. In this study, we propose a novel method to assign priorities to processors for facilitating effective selection of turned-on processors to decrease static energy consumption. An energy-efficient scheduling algorithm based on bisection (ESAB) is proposed on this basis, and this algorithm directly turns on the most energy-efficient processors depending on the idea of bisection to reduce static energy consumption while dynamic energy consumption is decreased by using DVFS technology. Experiments are performed on fast Fourier transform, Gaussian elimination, and randomly generated parallel applications. Results show that our ESAB algorithm makes a better trade-off between reducing energy consumption and low computation time of task assignment (CTTA) than existing algorithms under different scale conditions, deadline constraints, and degrees of parallelism and heterogeneity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-25T07:00:00Z
      DOI: 10.1142/S0218126620502035
       
  • A [math]–4 V Input Common-Mode Range Bidirectional Current Shunt
           Monitor
    • Authors: S. Huang, Peijun Liu, Quanzhen Duan, Yuemin Ding, Zhen Meng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This study describes a novel bidirectional current shunt monitor (CSM) circuit operating at both positive and negative common-mode (CM) voltages. The proposed CSM circuit mainly consists of two comparators, three error amplifiers, several current-mirror transistors and a few resistors. One comparator is used to detect current flowing direction, and the other one is utilized to ensure good operation of CSM circuit with both positive and negative CM voltages. The proposed CSM circuit has been implemented in SMIC 0.18[math][math]m standard CMOS process and its performances have been verified by simulations. The simulated results show that the proposed CSM circuit, at a supply voltage of 5[math]V and with an input CM voltage range from [math] to 4[math]V, can sense a voltage difference of 4–40[math]mV and keep a constant scaled gain of 100[math]V/V. The gain error is less than 0.65% and the common-mode rejection ratio (CMRR) is higher than 130[math]dB at 1[math]kHz. Simulation results show that the output voltage of CSM circuit varies linearly with the CSM input sense voltage.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-25T07:00:00Z
      DOI: 10.1142/S0218126620502217
       
  • An Efficient Data Gathering Technique Using Optimal Minimum Coverage
           Spanning Tree Algorithm in WSN
    • Authors: C. Nandagopal, S. M. Ramesh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A WSN system incorporates a gateway that provides wireless connectivity back to the wired world and distributed nodes. Many existing schemes were utilized for the purpose of increasing the data gathering capacity of sensor nodes from source to sink node. But the existing schemes suffered from maximum distance problem of reaching the sink node. Hence, to overcome those issues, we propose an energy efficient data gathering technique in WSN. Initially, in this paper, the sensor nodes are clustered using LEACH protocol. After the clustering process, cluster heads (CHs) are selected. These selected CHs in all the clusters are used for transferring the messages to the mobile node for data gathering. Then, optimal data transmission path is selected with the help of Optimal Minimum Covering Spanning Tree (OMST) algorithm. The OMST algorithm enhances data gathering and reduces the duration for reaching the sink node via selection of polling points. For reducing time complexity in MST, an efficient optimization algorithm is used. For an optimization purpose, particle gene swarm (PGS) model is used. From the experimental results, the proposed method achieved better results than the existing method in terms of energy, overhead, delay, delivery ratio, NLT and throughput.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-25T07:00:00Z
      DOI: 10.1142/S0218126620502254
       
  • Minimization of Common-Mode Voltage of Three-Phase Five-Level NPC Inverter
           Using 3D Space Vector Modulation
    • Authors: Palanisamy Ramasamy, Vijayakumar Krishnasamy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a three-dimensional Space Vector Modulation (3D SVM) is implemented for minimization of Common-Mode Voltage (CMV) of five-level Neutral Point Clamped (NPC) inverter. The 3D SVM control includes all merits of 2D SVM and provides better control compared to other PWM strategies. The switching state vectors are selected based on the nearest vector Switching State Vector (NSV); it selects the switching vectors which are having the minimum CMV level. It leads to minimization of the bearing voltage and protection of the drive from the damage; also this system reduces the total harmonic distortion. The switching time is calculated by reference vector identification with large and small subcubes tracking and prisms tracking in 3D cubic region. The CMV level with 3D SVM scheme is compared with other PWM methods. The simulation and hardware results are verified using Matlab Simulink and FPGA processor.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-25T07:00:00Z
      DOI: 10.1142/S0218126620502291
       
  • Switched Capacitor-Coupled Inductor DC–DC Converter for Grid-Connected
           PV System using LFCSO-Based Adaptive Neuro-Fuzzy Inference System
    • Authors: J. K. Mohan Kumar, H. Abdul Rauf, R. Umamaheswari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the Levy flight-based chicken swarm optimization (LFCSO) is proposed to follow the highest power of grid-joined photovoltaic (PV) framework. To analyze the grid-associated PV framework, the characteristics of current, power, voltage, and irradiance are determined. Because of the low yield voltage of the source PV, a big advance up converter with big productivity is required when the source PV is associated with the matrix power. A tale great advance up converter dependent on the exchanged capacitor and inductor is illustrated in this paper. The LFCSO algorithm with the adaptive neuro-fuzzy inference system is used to generate the control pulses of the transformer-coupled inductor DC–DC converter-less switched capacitor. While using the switched capacitor-coupled inductor, the voltage addition is expanded in the DC–DC converter and the power of PV is maximized. Here, the normal CSO algorithm is updated with the help of Levy flight functions to generate optimal results. To get the accurate optimal results, the output of the proposed LFCSO algorithm is given as the input of the ANFIS technique. After that, the optimal results are generated and they provide the pulses for the system. The working guideline is analyzed and the voltage addition is derived with the utilization of the proposed technique. From that point forward, it predicts the exact maximum power of the converter according to its inputs. Under the variety of solar irradiance and partial shading conditions (PSCs), the PV system is tested and its characteristics are analyzed in different time instants. The proposed LFCSO with ANFIS method is actualized in Simulink/MATLABstage, and the tracking executing is examined with a traditional method such as genetic algorithm (GA), perturb and observe (P&O) technique–neuro-fuzzy controller (NFC) and fuzzy logic controller (FLC) technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-20T07:00:00Z
      DOI: 10.1142/S0218126620502011
       
  • QCA-Based RAM Design Using a Resilient Reversible Gate with Improved
           Performance
    • Authors: Rupali Singh, Devendra Kumar Sharma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Reversible logic and Quantum dot cellular automata are the prospective pillars of quantum computing. These paradigms can potentially reduce the size and power of the future chips while simultaneously maintaining the high speed. RAM cell is a crucial component of computing devices. Design of a RAM cell using a blend of reversible logic and QCA technology will surpass the limitations of conventional RAM structure. This motivates us to explore the design of a RAM cell using reversible logic in QCA framework. The performance of a reversible circuit can be improved by utilizing a resilient reversible gate. This paper presents the design of QCA-based reversible RAM cell using an efficient, fault-tolerant and low power reversible gate. Initially, a novel reversible gate is proposed and implemented in QCA. The QCA layout of the proposed reversible gate is designed using a unique multiplexer circuit. Further, a comprehensive analysis of the gate is carried out for standard Boolean functions, cost function and power dissipation and it has been found that the proposed gate is 75.43% more cost-effective and 58.54% more energy-efficient than the existing reversible gates. To prove the inherent testability of the proposed gate, its rigorous testing is carried out against various faults and the proposed gate is found to be 69.2% fault-tolerant. For all the performance parameters, the proposed gate has performed considerably better than the existing ones. Furthermore, the proposed gate is explicitly used for designing reversible D latch and RAM cell, which are crucial modules of sequential logic circuits. The proposed latch is 45.4% more cost effective than the formerly reported D latch. The design of QCA-based RAM cell using reversible logic is novel and not reported earlier in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-20T07:00:00Z
      DOI: 10.1142/S0218126620502096
       
  • A Positive Feedback-Based Op-Amp Gain Enhancement Technique for
           High-Precision Applications
    • Authors: Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[math]nm CMOS technology. It results in 81[math]dB voltage gain, which is 21[math]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[math]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[math]V supply. The circuit draws a total static current of 295[math][math]A and occupies 5000[math][math]m2 of silicon area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-20T07:00:00Z
      DOI: 10.1142/S0218126620502205
       
  • A Novel Topology for Bidirectional Converter with High Buck Boost Gain
    • Authors: S. Saravanan, K. Karunanithi, S. Pragaspathy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In non-isolated bidirectional DC-DC converters (NIBIDC), voltage output of buck/boost mode is incongruous at lower and higher end due to the existing gain. In this paper, a novel NIBIDC is designed in such a way that it enhances the gain in both buck and boost mode of operation. The proposed NIBIDC is employed with four power switches (MOSFET) with an anti-parallel diode embodied, four inductors and three capacitors used as passive elements. The current flow in parallel connected inductor improves the circuit competence. Voltage gain of NIBIDC in buck operation is lower than conventional cascaded bidirectional buck/boost converter (CCBBC) whereas the voltage gain is higher than CCBBC in boost mode. The switching stress is same while the efficiency of NIBIDC is more than CCBBC. The topology structure of the NIBIDC is simple and easy to control. The performance analysis under steady-state condition of the novel converter is carried out and a detailed comparison with CCBBC is done in connection to switching stress, converter efficiency and duty ratios to output power, etc. The operation details for proposed NIBIDC in both mode is verified/validated by experimenting with 20[math]V input for different duty ratios in charging and discharging state of a battery and the results infer to be identical with theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-20T07:00:00Z
      DOI: 10.1142/S0218126620502229
       
  • Switched-Capacitor Common-Mode Feedback-Based Fully Differential
           Operational Amplifiers and its Usage in Implementation of Integrators
    • Authors: Joydeep Basu, Pradip Mandal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      For stabilizing the common-mode output voltage of fully differential operational amplifiers, switched-capacitor (SC) type of common-mode feedback (CMFB) is a familiar technique. This is appropriate for implementing high-gain wide-swing low-power op-amps due to its benefits of minimum power consumption, superior linearity across a large amplifier output swing range, and improved feedback loop stability in comparison to continuous-time CMFB. However, the usage of SC-CMFB requires careful attention to some realistic aspects, details of many of which are available in literature. Nonetheless, its adverse effect on the op-amp’s differential-mode gain has not been investigated much. The explanation for this effect is the SC-CMFB-induced equivalent resistive loading, and this is particularly significant in amplifiers like folded cascode which are intended to provide a high gain. This issue of drop in op-amp dc gain because of SC-CMFB, and the consequence on the realization of continuous-time and discrete-time forms of integrators utilizing such amplifiers is the topic of discussion in this paper. Relevant analytical derivations and circuit simulations at the transistor level are provided. A couple of design guidelines and circuit topologies for minimizing the loading-induced gain reduction are also presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-20T07:00:00Z
      DOI: 10.1142/S0218126620502230
       
  • Edge Detection Based on Fuzzy Logic and Hybrid Types of Shannon Entropy
    • Authors: Mourad Moussa, Hazar El Ouni, Ali Douik
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Edge is basically the symbol and reflection of partial image discreteness. It is one of the most commonly used operations in image processing and pattern recognition, it contains a wealth of internal information leading to strong interpretation of image. Resisting against noise, illumination and extracting appropriate features from an image is a great challenge in many computer vision applications. Indeed this topic participates to reduce the handled information and focuses on those related to existing objects. Efficient and accurate edge detection will lead to increase in the performance of many computer vision applications, including image segmentation, object-based image coding and image retrieval. Contour detection contributes to locate pixel sets which correspond to sudden intensities variation, these unstable properties of the given image commonly suggest to important events on going in the scene. In this paper, we present in the first time a novel and robust method for edge detection based on joint and conditional entropy when we highlight a Shannon theory, the second part of this paper is dedicated to decision making of edge pixels membership by intelligent method based on fuzzy logic tool.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-20T07:00:00Z
      DOI: 10.1142/S0218126620502278
       
  • Optimal Placement and Sizing of TCSC for Improving the Voltage and
           Economic Indices of System with Stochastic Load Model
    • Authors: Saman Ghaedi, Behrouz Tousi, Maysam Abbasi, Masoud Alilou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an efficient method is proposed for optimal allocation and sizing of Thyristor Controlled Series Compensator (TCSC) to improve the technical and economic indices of a power network with deterministic and stochastic load models. First, the compensator allocation is done in the transmission system with the deterministic load model. After calculating the technical and economic indices of the network in the presence of a deterministic load model, the proposed method is applied to the system with a stochastic load model. The two-point estimation method is used for simulating the stochastic conditions. The indices of voltage deviation and economics of the system are optimized for selecting the optimal location and size of TCSCs. The economic index comprises loss cost, cost of the produced active power of generators and also the costs of installation, operation and maintenance of TCSCs. The multi-objective particle swarm optimization (MOPSO) is utilized to optimize the objective functions. After the multi-objective optimization, the fuzzy decision method is employed to extract one of the Pareto-optimal solutions as the best compromise one. For evaluating the proposed method, comprehensive simulations have been performed on the IEEE 39-bus network by using MATLAB/Matpower software. The simulation results clearly prove the remarkable performance of the proposed method in improving the technical and economic indices of the system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-16T07:00:00Z
      DOI: 10.1142/S0218126620502175
       
  • A New Methodology for Implementing the Data Distribution Service on Top of
           Gigabit Ethernet for Automotive Applications
    • Authors: Manel Takrouni, Azer Hasnaoui, Ikbel Mejri, Salem Hasnaoui
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Today’s vehicles have become increasingly complex, as consumers demand more features and better quality in their cars. Most of these new features require additional electronic control units (ECU) and software control, constantly pushing back the limits of existing architectures and design methodologies. Indeed, modern automobiles have a larger number of critical time functions distributed and running simultaneously on each ECU. Data Distribution Service (DDS) is a publish/subscribe middleware specified by the international consortium Object Management Group (OMG), which makes the information available in real time, while offering a rich range of quality of service (QoS) policies. In this paper, we propose a new methodology to integrate DDS in automotive application. We evaluate the performance of our new design by testing the fulfillment of real time QoS requirements. We also compare the performance of the vehicle application when using FlexRay and Ethernet networks. Computations prove that the use of DDS over Gigabit Ethernet (GBE) is promising in the automotive field.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-12T07:00:00Z
      DOI: 10.1142/S0218126620502102
       
  • Energy-Efficient Clusterhead Selection Scheme in Heterogeneous Wireless
           Sensor Network
    • Authors: Piyush Rawat, Siddhartha Chauhan, Rahul Priyadarshi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The applications of wireless sensor network (WSN) are growing very rapidly, so utilizing the energy in an efficient manner is a challenging task as the battery life of nodes in WSN is very limited. For enhancing the lifetime of the network, various clustering protocols have been proposed earlier. In this paper, a clustering protocol named Energy Efficient Clusterhead Selection Scheme (ECSS) is proposed. The proposed ECSS protocol focusses on selecting an energy-efficient cluster head (CH), which helps in enhancing the overall lifetime and performance of the network. The proposed ECSS protocol uses the energy levels of nodes for the CH selection process. The proposed protocol is designed for the heterogeneous environment and it aims in minimizing the energy usage in the network and thereby improving the lifespan of the network. To measure the performance of the proposed ECSS protocol, the comparison is performed with the various existing protocols using MATLAB simulator. The results of simulation show that the proposed ECSS protocol has enhanced the network lifespan, throughput, and energy usage of the network as contrasted to the existing protocols.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-11T07:00:00Z
      DOI: 10.1142/S0218126620502047
       
  • Automation Software for Semiconductor Research Laboratories: Electrical
           Parameter Calculation Program (SeCLaS-PC)
    • Authors: A. Akkaya, E. Ayyıldız
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We prepared a simple program for basic electrical measurements and parameter extraction from these measurements of metal–semiconductor (MS) contacts. In this paper, we introduce a basic electrical parameter calculation software (SeCLaS-PC) for semiconductor laboratories from the temperature-dependent/independent current–voltage ([math]–[math]), capacitance– voltage ([math]–[math]) and capacitance–frequency ([math]–[math]) measurement results. SeCLaS-PC program was developed using Keysight VEE Pro (Visual Engineering Environment) software and the program has a user-friendly graphical interface. More than 50 device parameters can be easily obtained, using different methods, from the [math]–[math], temperature-dependent [math]–[math] and temperature-dependent [math]–[math] measurement results for one device, with our SeCLaS-PC program.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-11T07:00:00Z
      DOI: 10.1142/S0218126620502151
       
  • Enhancing the Lifetime of a Phase Change Memory with Bit-Flip Reversal
    • Authors: Bhukya Krishna Priya, N. Ramasubramanian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Phase Change Memory (PCM) has evolved as a promising alternative over Dynamic Random Access Memory (DRAM) in terms of cell density and leakage power. While non-volatility is a desirable feature, it gives rise to the possibility of the data being present even after the power is switched off. To secure the data, encryption is normally done by using the standard Advanced Encryption Standard (AES) algorithm. Encrypting the data results in huge number of bit-flips, which reduces the lifetime of a PCM. The proposed method increases the lifetime of PCM by reducing the number of bit-flips occurred due to the encryption of modified words only and leaving the unmodified words as they are. The generated encrypted text, which is written by using the bit-flips reversal method, reduces the number of cells involved in writing by approximately 25%. This method is implemented by using Gem5 simulator and is evaluated with splash2 benchmark suite. It is observed that the proposed method improves the lifetime of a PCM memory by 15% without consuming extra power.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-11T07:00:00Z
      DOI: 10.1142/S0218126620502199
       
  • Impedance Source-based Multilevel Inverter: A State-of-the-Art Review
    • Authors: Jammy Ramesh Rahul, Chinmay Kumar Das, Kirubakaran Annamalai, Veeramraju Tirumala Somasekhar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Impedance source-based multilevel inverters are becoming popular for emerging power generation technologies such as fuel cells, photovoltaic, and wind turbines. It is one of the most promising power electronic interfaces for single stage DC/AC conversion with inherent buck-boost capability. Therefore, in this paper, an extensive review of emerging impedance source-based multilevel inverter (Z-MLI) topologies is presented. These topologies are developed by the combination of impedance source network and multilevel inverter (MLI) with the merits of high voltage gain, enhanced reliability due to shoot-through immunity, improved input voltage regulation, reduced filter size, and better quality of supply. Most of the recent Z-MLI topologies are based on quasi-Z-source network which operates with continuous input current. In order to identify a suitable topology, an exhaustive comparison is made with various configurations of Z-MLIs in terms of component count, boost gain, switching stress, and control complexity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-04T08:00:00Z
      DOI: 10.1142/S0218126620300111
       
  • Full Error Detection and Correction Method Applied on Pipelined Structure
           Using Two Approaches
    • Authors: Mehmed Dug, Stefan Weidling, Egor Sogomonyan, Dejan Jokic, Milos Krstic
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-04T08:00:00Z
      DOI: 10.1142/S0218126620502187
       
  • Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller
           with Predictive Input Voltage
    • Authors: R. Thangam, S. P. Joy Vasantha Rani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the design of a fuzzy rule-based MDPSM controlled buck converter is analyzed. Power factor improvement and harmonic minimization for the buck converter connected through the variable load with a fuzzy rule are discussed and simulated. The MDPSM controlled converter is supplied with 230[math]V and reaches 15[math]V as output. The converter output, always connected with nonlinear loads, causes less power factor with more harmonics and gives less power quality. Active PFC with a fuzzy-based voltage controlled power factor controller is designed to reduce total harmonics and to raise the power factor value equal to unity. The fuzzy-based MDPSM controller was designed using MATLAB Simulink. Controller output waveforms are examined and analyzed with other controller performances. The converter is rated with 2[math]mA, 0.5[math]mH and 212[math][math]F values with output power 48[math]W. The converter is tested for different resistive loads and inductive loads.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-03T08:00:00Z
      DOI: 10.1142/S0218126620502072
       
  • Comparison and Optimization of Various Coated Ceramic Insulator Artificial
           Coastal Thermal Power Plant Pollution
    • Authors: T. Mariprasath, S. Asokan, M. Ravindaran
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In power system, the post-insulator is a critical apparatus which carries the conductor and also provides isolation between the conductors as well as ground. Besides, it offers mechanical support. However, extreme weather and pollution cause post-insulator flashover, which results in interruption of power supply and revenue loss. Therefore, post-insulator’s pollution flashover study is necessary. The pollution flashover voltage (FOV) is directly related to dominating metrological circumstance and how this pollution severity on the surface of insulator. Mostly, anti-pollution flashover coating is deliberated to be one of the most effective means to prevent and reduce pollution flashover. This paper investigates and compares the application of Epoxy Resin and Room Temperature Vulcanize (RTV) Silicone Rubber for enhancing the performance of ceramic outdoor (near coastal thermal plant area) insulator to defeat the effect of environmental pollution. At first, a real-time pollution performance has been carried out in controlled laboratory setup. It shows that the withstand ability of post-insulator has been 25% with Silicone Rubber coating. Subsequently, Artificial Neural Network (ANN) has been used to predict the FOV of post-insulator under wet and dry condition. It shows that critical FOV has enriched with anti-reflection coating rate. After that, post-insulator has been modeled by COMSOL multiphysics software, which is used for estimating field distribution on post-insulator. From the modeling, we found that anti-reflection coated post-insulator surface has low electrical stress than that of others.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-03T08:00:00Z
      DOI: 10.1142/S0218126620501996
       
  • Distributed Finite-Time Coordinated Attitude Tracking Control for Multiple
           Spacecraft with Actuator Saturation
    • Authors: Zhi Gao, Zhihao Zhu, Yu Guo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      For multi-spacecraft with actuator saturation, inertia uncertainties and external disturbances, a distributed finite-time coordinated attitude tracking control problem for the spacecraft with the communication topology containing fewer information paths is investigated. Aiming at reducing the communication path, a class of distributed finite-time state observers is designed. To speed up the convergence rate of the multiple spacecraft system, a fast nonsingular terminal sliding mode function is proposed. Moreover, an adaptive control term is proposed to suppress the impact of the external state-dependent disturbances and unknown time-varying inertia uncertainties. Further considering the actuator saturation owing to its physical limitations, a saturation function is designed. With the distributed finite-time observers, the fast nonsingular terminal sliding mode function, the adaptive update law and the saturation function, a distributed finite-time coordinated attitude tracking saturation controller is designed. Using the proposed controller, the follower can synchronize with the common leader with time-varying trajectory in finite time. Simulation results demonstrate the effectiveness of the designed controller.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-03T08:00:00Z
      DOI: 10.1142/S0218126620502126
       
  • Implementation of High Performance Hierarchy-Based Parallel Signed
           Multiplier for Cryptosystems
    • Authors: S. Elango, P. Sampath
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[math]nm, 90[math]nm and 45[math]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [math] and [math] signed arithmetic modules are implemented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-03T08:00:00Z
      DOI: 10.1142/S021812662050214X
       
  • Novel Approach to Analyze Crosstalk for a Multi-Line Bus System at 32-nm
           Technology
    • Authors: Ch. Praveen Kumar, E. Sreenivasa Rao, P. Chandra Sekhar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100[math][math]m and 1,000[math][math]m interconnect lengths, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-03-03T08:00:00Z
      DOI: 10.1142/S0218126620502163
       
  • EA-MAC: A QoS Aware Emergency Adaptive MAC Protocol for Intelligent
           Scheduling of Packets in Smart Emergency Monitoring Applications
    • Authors: Asokan Jayaram, Sanjoy Deb
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The evolution of the wireless sensor network (WSN) in recent years has reached its greatest heights and applications are increasing day by day, one such application is Smart Emergency Monitoring Systems (SMESs) which is in vision of implementation in every urban and rural areas. The implementation of WSN architecture in the Smart Monitoring Systems needs an intelligent scheduling mechanism that efficiently handles the high traffic load as well as the emergency traffic load without sacrificing the energy efficiency of the network. However, the traditional scheduling algorithms such as First Come First Served (FCFS), Round Robin, and Shortest Job First (SJF) cannot meet the requirements of high traffic load in SMESs. To address these shortcomings, this paper presents Emergency Adaptive Medium Access Control protocol (EA-MAC), a fuzzy priority scheduling based Quality-of-service (QoS)-aware medium access control (MAC) protocol for hierarchical WSNs. EA-MAC protocol employs the most powerful fuzzy logics to schedule the sensor nodes with both normal and emergency traffic load without any data congestion, and packet loss and maintaining the better QoS which is considered to be more important in SMESs applications. Moreover, a novel rank-based clustering mechanism in EA-MAC protocol prolongs the network lifetime by minimizing the distance between the Cluster Head (CH) and the Base Station (BS). Both analytical and simulation models demonstrate the superiority of the EA-MAC protocol in terms of energy consumption, transmission delay and data throughput when compared with the existing Time Division Multiple Access (TDMA) based MAC protocols such as LEACH protocol and Cluster Head Election Mechanism-Based On Fuzzy Logic (CHEF) protocol.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-28T08:00:00Z
      DOI: 10.1142/S0218126620502059
       
  • Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS
           Transistors with Memristor for Low Power Applications
    • Authors: V. Keerthy Rai, R. Sakthivel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Neural networks are mimetic with biological neuron which are employed on digital computers. These networks are designed with CMOS technology using 0.45[math][math]m in cadence virtuoso. The scaling of CMOS limits parameters like power consumption, area and parallelism. To overcome the limitations, a nanoscale, nonvolatile Memristor device is used to design the synapses. The proposed network is designed for neuron synapse networks implemented with a memristor device. This network is compared with neuron linked with CMOS synapse. The proposed network has low power consumption, high spike frequency, and low delay value. The spike frequency of Memristor synapse increases by 65.51% when compared with the existing CMOS synapse and power consumption is reduced to 52.79%. The delay is reduced to 0.294[math][math]s. The simulation results are carried using Specter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S021812662050187X
       
  • High Gain Single Switch DC-DC Converter Based on Switched Capacitor Cells
    • Authors: G. Indira Kishore, Ramesh Kumar Tripathi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With photovoltaic or fuel cell as a source, the high voltage required at DC bus as input for inverter can be obtained by high gain DC-DC converters. This can be achieved by implementing switched capacitor (SC) cells. Switched capacitors have the ability to produce high static gain and at the same time, they limit the voltage stress across the components. This paper proposes a high static gain, single switch DC converter based on the SC cells to develop high gain. These cells not only boost the voltage gain but also reduce the voltage stress at the active components. This converter also features a single active switch, low input ripple current through the inductor, absence of snubber circuit as the proposed converter does not assist the voltage spike across the active switch. The proposed converter allows high switching frequency and therefore results in a smaller size. The voltage gain can be increased further by adding the switched cells. In this paper, the operation in CCM, DCM, and design of components for the proposed converter is discussed. The MATLAB/SIMLINK and hardware-based studies for the proposed converters have been discussed to validate the specified features.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S0218126620501881
       
  • A Phase Self-Correction Method for Bias Temperature Drift Suppression of
           MEMS Gyroscopes
    • Authors: Tao Yin, Yueshan Lin, Haigang Yang, Huanming Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Phase error of the demodulation clock in the Coriolis vibratory gyroscope system allows the quadrature errors to leak into the sense channel and causes significant bias and temperature drift at the rate output. A phase self-correction method to suppress the temperature drift of the bias in gyroscopes is proposed. Through sweeping the demodulation clock phase and simultaneously monitoring the mechanical quadrature error output in gyroscopes, the optimal demodulation clock phase with minimum relatively phase shift is determined. Thus the bias influenced by the temperature and surroundings can be calibrated on-chip at start-up or when the environment changes drastically without the requirement of the complicated instruments. The proposed approach is validated by a silicon MEMS gyroscope with the natural frequency of 2.8[math]kHz, which shows nearly 22 times improvement in the temperature sensitivity of the system bias, from 550[math]mdeg/s/∘C down to 24.7[math]mdeg/s/∘C.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S0218126620501984
       
  • Accurate Calculation of Unreliability of CMOS Logic Cells and Circuits
    • Authors: Azam Beg
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern decananometer-sized MOS transistors tend to exhibit high rates of failure, underscoring the need for accurately estimating the unreliabilities of circuits built from such transistors. This paper presents a methodology for unreliability calculation that extends from individual transistors to complete logic circuits. As a logic cell’s or logic circuit’s unreliability is highly dependent on its transistors’ drain–source and gate–source voltages, SPICE simulations are used to determine the voltages for the individual transistors. The voltage measurements are then utilized by the mathematical equations to predict the unreliabilities with high accuracy. A scalable framework based on the proposed methodology has been successfully implemented. The framework has been validated using ISCAS85 benchmark circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S0218126620502023
       
  • Design of a Stable Low Power 11-T Static Random Access Memory Cell
    • Authors: Ashish Sachdeva, V. K. Tomar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [math] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [math] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S0218126620502060
       
  • A Low Cost MST-FSM Obfuscation Method for Hardware IP Protection
    • Authors: Yuejun Zhang, Zhao Pan, Pengjun Wang, Xiaowei Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Effective resistance to intellectual property (IP) piracy, overproduction and reverse engineering are becoming more and more necessary in the integrated circuit (IC) supply chain. To protect the hardware, the obfuscation methodology hides the original function by adding a large number of redundant states. However, existing hardware obfuscation approaches have hardware overhead and efficiency of obfuscation limitations. This paper proposed a novel methodology for IP security using the minimum spanning tree finite state machine (MST-FSM) obfuscation. In the minimum spanning tree (MST) algorithm, the Hamming distance defines the cost of obfuscated states. The Kruskal algorithm optimizes the connection relationship of obfuscated states by computing the Hamming distance of the MST-FSM. The proposed MST-FSM is automatically generated and embedded in the hardware IP with the self-building program. Finally, the MST-FSM is applied on the itc99 benchmark circuits and encryption standard IP cores. Compared with other state-of-the-arts, the obfuscation potency is improved by 3.57%, and the average hardware cost is decreased by about 6.01%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S0218126620502084
       
  • SCRN: A Complex Network Reconstruction Method Based on Multiple Time
           Series
    • Authors: Chao Meng, Xue Song Jiang, Xiu Mei Wei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Complex network reconfiguration has always been an important task in complex network research. Simple and effective complex network reconstruction methods can promote the understanding of the operation of complex systems in the real world. There are many complex systems, such as stock systems, social systems and thermal power systems. These systems generally produce correlated time series of data. Discovering the relationships among these multivariate time series is the focus of this research. This paper proposes a Spearman coefficient reconstruction network (SCRN) method based on the Spearman correlation coefficient. In the SCRN method, we select entities in the real world as the nodes of the network and determine connection weights of the network edges by calculating the Spearman correlation coefficients among nodes. In this paper, we selected a stock system and boiler equipment in a thermal power generation system to construct two complex network models. For the stock network model, we used the classic Girvan–Newman (GN) algorithm for community discovery to determine whether the proposed network topology is reasonable. For the boiler network model, we built a predictive model based on an support vector regression (SVR) model in machine learning, and we verified the rationality of the boiler model by predicting the amount of boiler steam.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-26T08:00:00Z
      DOI: 10.1142/S0218126620502138
       
  • Ultra-Fast DC Charger with Improved Power Quality and Optimal Algorithmic
           Approach to Enable V2G and G2V
    • Authors: Bekkam Krishna, D. Anusha, V. Karthikeyan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In existing electric vehicle (EV) charger topology, due to the presence of line frequency transformer and bidirectional DC-DC/AC converters, the circuit complexity in the structure gets increased in EV charger; thereby, it results bigger in size for high capacity. Moreover, due to rectification mode, it consumes the power with poor power quality. To overcome these drawbacks, this paper proposes a single input-dual port (SIDP) isolated bidirectional DC-DC converter (IBDC) to achieve ultra-fast EV charging of the battery. Also, to improve the power quality, a novel DC-link-fed PFC control strategy is proposed in this paper. Moreover, enabling grid to vehicle (G2V) and vehicle to grid (V2G) operation at bidirectional way depends on the situation such as state of charge (SOC) levels, off-peak and peak hours and user-defined data, which have been implemented using optimal algorithmic approach (OAA). The closed-loop control strategies are implemented to transfer the power at an accurate range using PWM plus phase-shifting approach. Moreover, it has the advantages of smaller in size due to the presence of medium frequency transformer and power quality gets improved without any additional converter stage. Finally, to validate the proposed operation, the results are observed under various case studies and conditional input from the customer and presented in this paper. Furthermore, the experimental results have been presented to validate the operation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-24T08:00:00Z
      DOI: 10.1142/S0218126620501972
       
  • Extracting a Credible Hint of Response Time to Scale Resources in Elastic
           Clusters
    • Authors: Cheng Hu, Yuhui Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In elastic clusters, the service resources (or called “resources” for short) can be dynamically scaled, thus providing opportunities to cut down the energy cost of redundant resources. Generally, taking into account the Quality of Service (QoS) of clusters, resources are carefully scaled according to specific hints which are some features of system status. However, when the Service Quality Requirement (SQR) is referred to the response time of requests, some widely used features cannot well reflect the status of the QoS. Consequently, the QoS cannot be well maintained, and the energy-saving efficiency is unsatisfactory. In this paper, we indicate that under such SQR, the outstanding hint for resource scaling is the response time of requests. Accordingly, we propose a resource scaling method which scales resources leveraging an elaborate Hint of Response time (HR). More specifically, HR is credible to foresee future QoS, and our method extracts HR by tracking and making analysis on the waiting requests in each server. Moreover, when resource scaling operation is performed, our method can estimate how many resources are suitable for current workloads with a good accuracy. Thereby, our method can timely and directly scale resources to the suitable amount, thus can significantly reduce the time delay of re-matching resources. Finally, our method can significantly promote cluster performance on both the QoS and the energy-saving efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-24T08:00:00Z
      DOI: 10.1142/S0218126620502114
       
  • An Efficient Prediction Framework for Multi-parametric Yield Based on
           Uncertainty of Performance-Relevant Structure
    • Authors: Xin Li, Haifei Yuan, Dongming Li, Zhi Fang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the aggressive shrinking of integrated circuit (IC) fabrication technology, variability in design parameters leads to significant yield loss. Therefore, efficient parametric yield prediction has been a critical task for today’s ICs, especially when multiple performances are considered simultaneously. However, most of the previous yield prediction works have failed to take into account uncertainty of performance-relevant structures. Neglecting the uncertainty effects will tend to result in predictive accuracy loss. To avoid the issue, this paper proposes a multi-parametric yield prediction framework based on the uncertainty of performance-relevant structures. In the proposed framework, saddle point estimation and mixed copula function are applied to maintain the uncertainty-relevant structures among performance metrics and predict the multi-parametric yield accurately. First, the framework constructs a general statistical model for performance metrics to illustrate the uncertainty of performance-relevant structures. The general model is explicitly expressed in terms of underlying process, voltage, and temperature (PVT) parameters. Then, based on the general performance model and taking total leakage current and gate delay for example, their marginal distributions are estimated by assuming the PVT parameters as normal random variables. Finally, a mixed copula-based yield prediction method is suggested to solve the uncertainty-relevant structure problem. Experimental results demonstrate that the proposed yield prediction framework is capable of predicting multi-parametric yield under arbitrary performance-relevant structures. Compared to Monte Carlo (MC) analysis, the relative errors of yield prediction are less than 5%, which means the framework has good accuracy and efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-21T08:00:00Z
      DOI: 10.1142/S021812662050173X
       
  • A Novel Scale Insensitive KCF Tracker Based on HOG and Color Features
    • Authors: Zhichao Lian, Changju Feng, Zhonggeng Liu, Chanying Huang, Chunshan Xu, Jin Sun
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Kernelized Correlation Filters (KCF) for visual tracking have received much attention due to their fast speed and outstanding performances in real scenarios. However, the KCF sometimes still fails to track the targets with different scales, and it may drift because the target response is fixed and the original histogram of orientation gradient (HOG) features cannot represent the targets well. In this paper, we propose a novel fast tracker, which is based on KCF and insensitive to scale changes by learning two independent correlation filters (CFs) where one filter is designed for position estimation and the other is for scale estimation. In addition, it can adaptively change the target response and multiple features are integrated to improve the performance for our tracker. Finally, we employ an adaptive high confidence filters updating scheme to avoid errors. Evaluated on the popular OTB50 and OTB100 datasets, our proposed trackers show superior performances in terms of efficiency and accuracy compared to the existing methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S0218126620501832
       
  • A Flexible High-Level Fusion for an Accurate Human Action Recognition
           System
    • Authors: Amel Ben Mahjoub, Mohamed Atri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Action recognition is a very effective method of computer vision areas. In the last few years, there has been a growing interest in Deep learning networks as the Long Short–Term Memory (LSTM) architectures due to their efficiency in long-term time sequence processing. In the light of these recent events in deep neural networks, there is now considerable concern about the development of an accurate action recognition approach with low complexity. This paper aims to introduce a method for learning depth activity videos based on the LSTM and the classification fusion. The first step consists in extracting compact depth video features. We start with the calculation of Depth Motion Maps (DMM) from each sequence. Then we encode and concatenate contour and texture DMM characteristics using the histogram-of-oriented-gradient and local-binary-patterns descriptors. The second step is the depth video classification based on the naive Bayes fusion approach. Training three classifiers, which are the collaborative representation classifier, the kernel-based extreme learning machine and the LSTM, is done separately to get classification scores. Finally, we fuse the classification score outputs of all classifiers with the naive Bayesian method to get a final predicted label. Our proposed method achieves a significant improvement in the recognition rate compared to previous work that has used Kinect v2 and UTD-MHAD human action datasets.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S021812662050190X
       
  • Improved Ternary Reversible Logic Synthesis Using Group Theoretic Approach
    • Authors: P. Mercy Nesa Rani, Kamalika Datta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Quantum computation relies on exploiting quantum mechanical phenomena, and has received significant attention in recent years. Higher-dimensional quantum systems increase the density of encoded information per computing element (e.g., qutrit for three-level system), resulting in less resource overhead. For instance, 63% reduction in the number of qutrits is possible for ternary quantum systems as compared to the corresponding binary systems. The proposed work exploits this fact to synthesize ternary reversible circuits employing a cycle-based technique. The method starts from the ternary reversible specification of a given function in the form of a permutation. The permutation cycles are factored into simpler three-cycles and two-cycles, which are then mapped to ternary reversible gates. Different gate libraries are used to synthesize three-cycles and two-cycles, respectively. A gate decomposition approach is also proposed to synthesize a quantum gate netlist in terms of elementary ternary quantum gates, viz. Muthukrishnan–Stroud gate and shift gate. Synthesis results on benchmark functions indicate that the proposed method results in 27% and 6% improvements in quantum cost and gate count, respectively, over existing works in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S0218126620501923
       
  • A Novel Four Switch Infinite Level Inverter
    • Authors: K. T. Ajmal, K. Muhammedali Shafeeque, B. Jayanand
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel Four Switch Infinite Level Inverter (FSILI) is proposed in this paper. In conventional multilevel inverters, as the number of levels increases the output voltage becomes more sinusoidal. Unlike conventional multilevel topologies, the output voltage level in the proposed topology depends upon the switching frequency. Since the switching frequency is very high, the output voltage level approaches infinity, thus the name Infinite Level Inverter. Proposed topology requires only one inductor and capacitor reducing the size, weight and thus cost of the overall system. Inherent buck operation is happening in the proposed topology with a sine varying duty ratio PWM control. Steady-state analysis and design of the inverter are carried out. The proposed topology is simulated using Matlab/Simulink to evaluate the theoretical analysis and operation. A hardware prototype is also developed to validate the operation of proposed FSILI.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S0218126620501935
       
  • Minimizing Energy of Heterogeneous Computing Systems by Task Scheduling
           Approach,
    • Authors: Junke Li, Junwei Li, Mingjiang Li, Guanyu Wang, Jincheng Zhou, Yu Lu, Deguang Li, Yanhui Huang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      As an important component of computer system, GPU has been used more widely in the system under the support of general computing. In addition to focusing on its performance, the issues of its energy consumption and environmental problem have gradually attracted the concerns of researchers, computer architects, and developers. Current researches only consider single-task scheduling for saving energy, lacking the focus on energy saving from scheduling the overall tasks. In view of the shortcomings of current researches, we propose a METS (Minimizing Execution Time Slot) approach to reduce energy by rationally allocating the tasks across GPUs. It first collects the number of tasks and the corresponding estimated performance information. Next, it decides whether to turn the problem into a 0–1 knapsack problem or to use FIFO method based on the number of tasks. Then, we conduct our experiment on typical platform to verify our proposed approach. The experimental results show that METS can save on average 8.43% of energy when compared with the existing approaches. This shows that the proposed METS method is effective, reasonable and feasible.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S0218126620501947
       
  • A Universal Method for Designing Multi-Digit Ternary to Binary Converter
           Using CNTFET
    • Authors: Maryam Shahangian, Seied Ali Hosseini, Reza Faghih Mirzaee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Ternary logic can reduce the number of interconnections, chip area and power dissipation. In addition, one of the important features of carbon nanotube field effect transistors (CNTFETs) is the capability of adjusting threshold voltage. As a result, the design complexity of ternary circuits can be decreased. The structure of a mixed radix system which is based on multi-valued and binary logic is more appropriate compared to only multiple-valued logic (MVL). Therefore, ternary-to-binary and binary-to-ternary converters are the essential components for the ternary signaling on the bus and the binary logic processing circuits. It is also important for the creation of compatibility between the binary and ternary logic. This study is about a multi-digit binary-to-ternary converter by using CNTFET. At first, the algorithm used for the multi-digit conversion from ternary to binary logic is addressed in this paper. Then, the paper proposes a block diagram suitable for designing the multi-digit ternary-to-binary converter. Some new gates including One-Active Gate and Two-Active Gate, as well as two types of binary half-and full-adders, are designed for the purpose of implementing the proposed block diagram. This is done by adjusting the proper threshold voltage for CNTFETs. The proposed algorithm can also be applied to any desired number of bits. The proper operation and high efficiency of the proposed converter are confirmed by HSPICE simulation results and 32[math]nm CNTFET technology from the Stanford University.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S0218126620501960
       
  • Novel Implementation Approach with Enhanced Memory Access Performance of
           MGS Algorithm for VLIW Architecture
    • Authors: Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modified Gram–Schmidt (MGS) algorithm is one of the most-known forms of QR decomposition (QRD) algorithms. It has been used in many signal and image processing applications to solve least square problem and linear equations or to invert matrices. However, QRD is well-thought-out as a computationally expensive technique, and its sequential implementation fails to meet the requirements of many real-time applications. In this paper, we suggest a new parallel version of MGS algorithm that uses VLIW (Very Long Instruction Word) resources in an efficient way to get more performance. The presented parallel MGS is based on compact VLIW kernels that have been designed for each algorithm step taking into account architectural and algorithmic constraints. Based on instruction scheduling and software pipelining techniques, the proposed kernels exploit efficiently data, instruction and loop levels parallelism. Additionally, cache memory properties were used efficiently to enhance parallel memory access and to avoid cache misses. The robustness, accuracy and rapidity of the introduced parallel MGS implementation on VLIW enhance significantly the performance of systems under severe rea-time and low power constraints. Experimental results show great improvements over the optimized vendor QRD implementation and the state of art.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-19T08:00:00Z
      DOI: 10.1142/S021812662050200X
       
  • Hardware Design of a Kind of Grid Multi-Scroll Chaotic System Based on a
           MSP430F169 Chip
    • Authors: Wei Xu, Ning Cao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Based on only MSP430F169 chip, a digital chaotic generator for a grid-like JERK chaotic system is designed, from which grid-like [math] chaotic attractors are generated. By analyzing the nonlinear functions of the gird-like chaotic system, the saddle focal balance points are respectively extended in [math],[math] direction. According to the hardware requirements of MSP430F169 chip, using Euler algorithm to discretize the chaotic system, the values of 36 saddle focal balance points need to be recalculated. The numerical values of the focal balance points which are involving iterative operations are given by the proposed comparative piece-wise method, their analysis and numerical simulations are also performed. The software and hardware design ideas are given for implementation, the experiment results are verification of the feasibility of the scheme.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-11T08:00:00Z
      DOI: 10.1142/S0218126620501893
       
  • An Efficient Method for Selecting the Optimal Features using Evolutionary
           Algorithms for Epilepsy Diagnosis
    • Authors: S. Afrakhteh, M. R. Mosavi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      One of the important parameters in the brain–computer interface (BCI) system is speed. Therefore, it is always desirable to design a high-speed system that has an acceptable performance, simultaneously. The main idea of this paper is the use of evolutionary algorithms (EAs) to select the optimal features for epilepsy diagnosis by processing the electroencephalogram (EEG) signals. The lesser the number of features is, the higher will be the usefulness of accuracy of the system to us. Therefore, here, using EAs, some of the features that are redundant in the data and do not contain a lot of information and only increase the complexity of the system are eliminated and the best features are chosen. We select this choice by EAs. Running the feature selection step is after the feature extraction step. In fact, the features were extracted using the common spatial pattern (CSP) algorithm, and then the optimal features were selected from the extracted feature set. This can save a lot of system complexity and reduce system execution time considerably. Finally, at the diagnostic stage, these selected features are given to a simple neural network (NN). The results showed that when the combination of EA and CSP is used, the precision of the system is much higher than when the CSP method is only used, although it contributes significantly to the complexity of the system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-11T08:00:00Z
      DOI: 10.1142/S0218126620501959
       
  • A Compact CPW Fed Wideband Slot Antenna for Wireless Communications
    • Authors: Amrita Gorai, Bappadittya Roy, G. K. Mahanti
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A compact circularly polarized CPW-fed slot antenna is proposed here. The antenna consists of a pentagonal patch within an asymmetrical slot with a single coplanar waveguide feed. The proposed antenna is excited with CPW feed mechanism and investigated experimentally. The structure is fabricated on FR4 epoxy substrate with a permittivity of 4.4. The impedance bandwidth of 10[math]GHz (4[math]GHz to 14[math]GHz) and the axial ratio bandwidth of 1.2[math]GHz with the corresponding fractional bandwidth of 113%. The simulation results fulfil the bandwidth requirements of IEEE 802.11a (5.15–5.35[math]GHz/5.47–5.725[math]GHz) for wireless applications. In terms of bandwidth, compactness and circular polarization comparable results between simulated and measured results clearly show the validity of the proposed structure.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-06T08:00:00Z
      DOI: 10.1142/S0218126620501844
       
  • A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D
           Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic
    • Authors: Anirban Chakraborty, Ayan Banerjee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Dedicated hardware for “Discrete Wavelet Transform” (DWT) is at high demand for real-time imaging operations in any standalone electronic devices, as DWT is being extensively utilized for most of the transform-domain imagery applications. Various DWT algorithms exist in the literature facilitating its software implementations which are generally unsuitable for real-time imaging in any stand-alone devices due to their power intensiveness and huge computation time. In this paper, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. Our proposed architecture, which mingles the advantages of convolutional and lifting DWT while discarding their notable disadvantages, is made area and memory efficient by exploiting “Distributed Arithmetic’ (DA) in our own ingenious way. Almost 90% reduction in the memory size than other notable architectures is reported. In our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, “mode”. With the introduction of DA, pipelining and parallelism are easily incorporated into our proposed 1D/2D DWT architectures. The area requirement and critical path delay are reduced to almost 38.3% and 50% than that of the latest remarkable designs. The performance of the proposed VLSI architecture also excels in real-time applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-05T08:00:00Z
      DOI: 10.1142/S0218126620501510
       
  • Middle-Order Vehicle-Based Clustering Model for Reducing Packet Loss in
           Vehicular Ad-hoc Networks
    • Authors: S. David, P. T. Vanathi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Vehicular Ad-hoc NETworks (VANETs) are typically termed as a wireless ad-hoc network that contains extreme node mobility and also the network carries a great significance in various traffic-oriented commercial applications and safety services. Due to its high mobility, routing in VANET has been a challenging work and also proving a higher rate of packet delivery ratio with reduced packet loss has been more important to be considered in route formations. With that note, this paper contributes to developing a clustering model called Middle-Order Vehicle-based Clustering (MOVC) model for managing the frequent topological change and high vehicle mobility, and efficiently handling the typical road traffic scenario. Moreover, the algorithm is intended to maintain the cluster to be constant for managing the vehicles in effective ways and also to provide uninterrupted communication between the vehicles. An algorithm for Effective Cluster Head Election (ECHE) is also derived in this paper for proficiently handling the frequency variation on the highways. Further, the model is simulated and evaluated on the basis of various metrics of VANET routing, specifically packet loss, packet delivery ratio, network lifetime and throughput. The results show that the proposed mechanism outperforms the results of existing models.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-05T08:00:00Z
      DOI: 10.1142/S0218126620501807
       
  • FPGA-Based ROI Encoding for HEVC Video Bitrate Reduction
    • Authors: Zhilei Chai, Shen Li, Qunfang He, Mingsong Chen, Wenjie Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos ([math]), and the bitrate is reduced by 10% on average with stable video quality.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-05T08:00:00Z
      DOI: 10.1142/S0218126620501820
       
  • Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene
           Nanoribbon (MLGNR) in On-Chip Interconnects
    • Authors: Himanshu Sharma, Karmjit Singh Sandha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[math]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[math]nm) for variable global lengths (500–2000[math][math]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-05T08:00:00Z
      DOI: 10.1142/S0218126620501856
       
  • Design of DQPSK Demodulator for Implantable Biomedical Devices
    • Authors: Vaibhav Garg, Kavindra Kandpal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Implantable biomedical devices (IBDs) play a vital role in today’s healthcare industry. Such applications demand high data rate, low power and small-sized demodulators. This work presents a simple small-sized low-power architecture for differential quadrature phase shift keying (DQPSK) demodulator for these devices. The proposed circuitry is designed in UMC 90-nm CMOS technology and occupies a layout area of 0.015 mm2. It is operated at 1-V supply voltage with a power consumption of 405[math][math]W. The carrier frequency is 10[math]MHz and the obtained data rate is 20[math]Mbps. Hence it exhibits a high data-rate-to-carrier-frequency (DRCF) ratio of 200% making it ideal for IBDs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-04T08:00:00Z
      DOI: 10.1142/S0218126620200078
       
  • Efficient Diminished-1 Modulo (2[math]) Adder Using Parallel Prefix Adder
    • Authors: Subodh Kumar Singhal, B. K. Mohanty, Sujit Kumar Patel, Gaurav Saxena
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Parallel prefix adder (PPA) is the core component of diminished-1 modulo (2[math]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo (2[math]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo (2[math]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-02-04T08:00:00Z
      DOI: 10.1142/S0218126620501868
       
  • General Method to Design Reversible Universal [math]-Bit Up/Down Counters
    • Authors: Zeinab Kalantari, Mohammad Eshghi, Majid Mohammadi, Somayeh Jassbi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [math]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([math], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-30T08:00:00Z
      DOI: 10.1142/S0218126620501650
       
  • A Symmetrical Multilevel Inverter Topology with Minimal Switch Count and
           Total Harmonic Distortion
    • Authors: Kavali Janardhan, Arvind Mittal, Amit Ojha
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A multilevel inverter (MLI) with reduced number of power devices, especially for the higher output levels, is presented in this paper. The generalized topology for ([math]) level MLI is developed with symmetrical isolated dc sources and ([math]) number of switches. A five-level MLI is developed with five power switches and then by adding each one additional switch two more levels are added in the output voltage waveform. With the help of lookup table, the working principle of the proposed five-level MLI topology is explained. Sinusoidal pulse width modulation–phase disposition control technique has been used to get a minimal total harmonic distortion (THD). The proposed MLI topology is simulated on the MATLAB platform. The laboratory prototype is developed for five-level MLI, and the experimental results obtained validate the simulation studies. The dSPACE 1104 is used for generating gate pulses in case of experimentation. The output voltage and current THDs obtained are 9.20% and 4.60%, respectively; the harmonics are mitigated more with five-level inverter. The proposed topology is compared with the cascaded H-bridge multilevel inverter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-30T08:00:00Z
      DOI: 10.1142/S0218126620501741
       
  • High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads
    • Authors: P. Manikandan, B. Bindu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The proposed LDO does not require an external capacitor making it suitable for System-on-Chip (SoC) applications. The low-frequency PSR of the LDO varies with load current as the transconductance and output conductance of the power transistor depend on the load current. The proposed LDO is capable of maintaining a constant and high PSR for varying loads by using an adaptive network. The NMOS pass transistor in the adaptive network tracks the power-supply noise through the power transistor and bypasses this noise current through it to the ground. This helps to avoid the flow of this noise current through the load and thus the circuit can achieve high and constant PSR for varying loads. The LDO with adaptive network achieves very high power-supply rejections of [math][math]dB at low frequencies and [math][math]dB at 1[math]MHz, for a load current of 4[math]mA. This LDO is implemented in 0.18-[math]m CMOS technology and consumes 1.35-mW quiescent power over the range of 1–10[math]mA of the load current.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-30T08:00:00Z
      DOI: 10.1142/S0218126620501789
       
  • An Electronically Adjustable Waveform Generator
    • Authors: İbrahim Ethem Saçu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel electronically adjustable square/triangular waveform generator has been introduced in this paper. The proposed circuit employs one active element, the multi-output current-controlled current conveyor transconductance amplifier, and one passive component grounded capacitor only. The resistorless realization of the presented generator provides a good advantage in terms of integrated circuit fabrication. In the offered circuit, the frequency and amplitude of the output square wave are electronically tunable by means of relevant bias currents. Additionally, the upper and lower threshold levels are electronically controllable by the respective bias current. On the contrary, electronically adjusting of the duty cycle of output waveform is possible via the external DC current. The generator circuit is simulated with TSMC 0.18[math][math]m technology parameters and SPICE. Moreover, the introduced circuit is implemented by using commercially available active devices and thus it is also verified experimentally.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-30T08:00:00Z
      DOI: 10.1142/S0218126620501911
       
  • Design of Pentacene-based Organic Field-Effect Transistor for
           Low-Frequency Operational Transconductance Amplifier
    • Authors: Cross T. Asha Wise, G. R. Suresh, M. Palanivelen, S. Saraswathi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Mounting electronics circuits on a plastic flexible substrate are pertinent for biosensing applications due to their resilient nature, minimal processing conditions, lightweight and low cost. Organic Field-Effect Transistors (OFET)-based amplifier for flexible biosensors have been proposed in this paper. To design flexible biosensing circuits, Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Polycyclic Hydrocarbon is a suitable choice. It is a big challenge to build an organic circuit using graphene electrode due to its poor performance of [math]-type OFET, therefore it is advisable to use Pentacene as [math]- and [math]-type Organic semiconductors. Pentacene being one among the foremost totally investigated conjugated organic molecules with a high application potential because the hole mobility in OFETs goes up to 0.2[math]cm2/(Vs), which exceeds that of amorphous silicon. In biosignal process, the first and most important step is to amplify the biosignal for further processing. Operational Transconductance Amplifier (OTA) plays an essential role in biological signal measuring instruments like EEG, ECG, EMG modules which measure the heart, muscle and brain activities. The OTA designed using this OFET is adaptable for flexible sensor circuits and also it derives the transconductance of 67 which is similar to silicon OTA. The amplifier designed here gives unit gain of 42[math]dB with a frequency of 195[math]Hz which is suitable for low-frequency biosignal processing applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-24T08:00:00Z
      DOI: 10.1142/S0218126620501819
       
  • A 4-Stage Pipelined Architecture for Point Multiplication of Binary Huff
           Curves
    • Authors: Muhammad Rashid, Malik Imran, Atif Raza Jafri, Zahid Mehmood
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work has proposed a 4-stage pipelined architecture to achieve an optimized throughput over area ratio for point multiplication (PM) computation in binary huff curves (BHC) cryptography. The original mathematical formulation of BHC is revisited with an objective to reduce the required area. Consequently, a simplified formulation of BHC is obtained with 43% reduction in the hardware resources. As far as the throughput is concerned, it is improved first by reducing the critical path and second by minimizing the number of clock cycles (CCs) required to compute one PM. The critical path is reduced through the placement of pipeline registers, whereas the number of required CCs are minimized through an efficient scheduling of computations. These two factors i.e., the area reduction and throughput optimizations, have resulted in maximizing the throughput over area ratio. The proposed pipelined architecture is implemented over [math] field, using standard NIST curve parameters. The architecture is modeled in Verilog and synthesized using Xilinx (ISE 14.7) design tool on Virtex 7 FPGA. The implementation results show that 17% improvement in clock frequency, 13% reduction in the time required to compute one PM and 2.6% improvement in throughput/area are achieved when compared with the most recent state of the art solutions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-22T08:00:00Z
      DOI: 10.1142/S0218126620501790
       
  • Development of a Hardware Circuit for Real-Time Acquisition of Brain
           Activity Using NI myDAQ
    • Authors: Oinam Robita Chanu, R. Kalpana, B. Soorya, R. Santhosh, V. Karthik Raj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Electroencephalography (EEG) is the recording of electrical activity of the brain. The 10–20 system is the standard electrode location method used to acquire EEG data, which uses 21 electrodes to record the electrical activity of the brain. Patient preparation and correct electrode placement are important to obtain reliable outputs. The current 10–20 system consumes greater time for patient preparation and also causes discomfort due to a higher number of electrodes being used or wearing an uncomfortable cap. This paper focuses on reducing the number of electrodes, thus reducing patient discomfort as well as preparation time. Advancement in the field of hardware and software processing has led to the utilization of brain waves for communication between human and the computer. This work deals with EEG-based Brain–Machine Interface (BMI) intended for designing a portable single-channel EEG signal acquisition system. EEG signal was acquired using the data acquisition module [National Instruments (NI) myDAQ] and the signal was viewed in the NI Laboratory Virtual Instrument Engineering Workbench (LabVIEW) environment. It was observed that the peak-to-peak amplitude of alpha, beta and theta waves changes in accordance with the activity the subjects performed. Thus, the developed instrument was tested on 10 different subjects to acquire the alpha, beta and theta waves by performing different activities. From the results, it can be concluded that the developed system can be used for studying a person’s brain waves (alpha, beta and theta) based on the activity performed by the subject with a limited number of electrodes.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-21T08:00:00Z
      DOI: 10.1142/S0218126620501704
       
  • Performance Investigation of FinFET-Based MO-CCII and its Applications:
           Resistor-Less Multi-Function Bi-Quadratic Filter and Balanced Modulator
    • Authors: Mohd Yasir, Mohammad Samar Ansari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an optimal design of a high-performance multi-output second-generation current conveyor (MO-CCII) based on 20[math]nm Fin-Shaped Field Effect Transistor (FinFETs). Proposed MO-CCII has very low port X impedance and very high port Y impedance. The performance of the CCII has been thoroughly investigated in terms of DC, AC and transient characteristics of terminal voltages and branch currents and frequency response of port impedances. CCII shows the excellent high-frequency response of voltage as well as current transfer gains. The 3[math]dB BW of voltage and current transfer gains are 11.2[math]GHz and 11[math]GHz, respectively. CCII provides excellent performance over its CMOS counterpart. Also, a resistor-less multi-function bi-quadratic filter is proposed. The filter depends on two CCIIs, a capacitor and does not require any resistors. It has three inputs and one output and realizes low-pass, high-pass and band-pass filters from a similar setup. FinFETs in the linear region are utilized as variable resistor to control filter properties. Nevertheless, the proposed filter has two floating capacitors which can be effortlessly realized in these days’ integrated circuit advancements. Also, a balanced modulator is proposed utilizing the proposed FinFET-based CCII and FinFET transistors only. Balanced modulator’s frequency of operation obtained is in GHz range.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-21T08:00:00Z
      DOI: 10.1142/S0218126620501753
       
  • Synthesis of Monitoring Rules with STL
    • Authors: Sertac Kagan Aydin, Ebru Aydin Gol
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Online monitoring is essential to enhance the reliability for various systems including cyber-physical systems and Web services. During online monitoring, the system traces are checked against monitoring rules in real time to detect deviations from normal behaviors. In general, the rules are defined as boundary conditions by the experts of the monitored system. This work studies the problem of synthesizing online monitoring rules in the form of temporal logic formulas in an automated way. The monitoring rules are described as past-time signal temporal logic (ptSTL) formulas and an algorithm to synthesize such formulas from a given set of labeled system traces is proposed. The algorithm searches the formula space using genetic algorithms and produces the best formula representing a monitoring rule. In addition, online STL monitoring algorithm is improved to efficiently compute a quantitative valuation for piecewise-constant signals from ptSTL formulas, thus, to reduce the overhead of the real-time computation. The effectiveness of the results is shown on two illustrative examples inspired from online monitoring of Web services.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-21T08:00:00Z
      DOI: 10.1142/S0218126620501777
       
  • Design and Optimization of Dual-Band Energy-Efficient OOK UWB Transmitter
           Via PSO Algorithm
    • Authors: Dalenda Ben Issa, Mounir Samet
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A CMOS ON–OFF-keying 3–10.6-GHz transmitter with low power consumption and low complexity used to Impulse Radio Ultra-Wide Band (IR-UWB) communication system is presented in this work. This architecture is designed and optimized via particle swarm optimization (PSO) algorithm. The IR-UWB transmitter is adapted to generate a high bandwidth frequency and it has a band switching capability. It consists of a switching inductance–capacitance voltage-controlled oscillator (LC_VCO), a pulse generator circuit, an injection-locked frequency divider (ILFD) circuit, a buffer and an antenna. The VCO is switched ON/OFF by the pulse signal produced by a generator circuit which is realized through synchronizing the received data by a clock signal. The used technique for transmitting a discontinuous signal is based on a complementary switch-mode ON–OFF LC_VCO, whose main advantage is to reduce power consumption. In this work, a best agreement between the results of the optimization technique and those of the simulation is obtained. The simulated results illustrate a signal of pulse width of 2.5 ns and a pulse repetition rate (PRR) of 200 MHz. The output spectra are centered at 4-GHz and 8-GHz frequencies with 1,332-MHz and 1,350-MHz bandwidths, respectively. The peak-to-peak amplitude of a UWB signal output is 154[math]mV. The IR-UWB transmitter power consumption is 11.4[math]mW which corresponds to the consumption energy of 28.5 pJ/pulse @ 200[math]MHz. The power spectral densities (PSDs) of the output signals of both circuits viz. ON–OFF LC_VCO and ILFD are less than [math][math]dBm/MHz, which agreed well with the Federal Communication Commission (FCC) regulation. The transmitter design is well implemented using a TSMC 0.18-[math]m CMOS process technology in an Advanced Design System (ADS).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-15T08:00:00Z
      DOI: 10.1142/S0218126620300093
       
  • Machine Learning Techniques for Assisted Reproductive Technology: A Review
    • Authors: K. Ranjini, A. Suruliandi, S. P. Raja
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Infertility is becoming a public health issue in almost all countries. Assisted Reproductive Technology (ART) is considered as a method of last resort for treating infertility. The treatment of ART is highly expensive and painful, and also the probability of success is low since the success is affected by a large number of variables. Researchers are now trying to identify patterns comprising significant variables, their impact on success, and the interdependence of different variables to enumerate the status of the patient and to support the doctors and biologists to prescribe treatment to improve the probability of success of ART. Machine learning technique is a tool that is used by various researchers in the field of ART to identify the interlink between the variables. The objective of this review paper is to find the appliance of machine learning techniques in ART and to find further enrichment needed for future research. From the literature, it is found that some research works were done using machine learning techniques to predict ART outcome. On analyzing the reviews qualitatively and quantitatively, it is understood that various classifiers are used for ART outcome prediction but they are trained using limited amount of static data collected from fertility centers. The exact prediction of ART outcome may be improved by training the classifier with large amount of dynamic data. But building such a classifier is difficult by the already existing techniques. This may be made possible by introducing Big Data Analytics in ART.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-15T08:00:00Z
      DOI: 10.1142/S021812662030010X
       
  • An Ultra-Low-Power Five-Input Majority Gate in Quantum-Dot Cellular
           Automata
    • Authors: Feifei Deng, Guangjun Xie, Shaowei Wang, Xin Cheng, Yongqiang Zhang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[math], 11.09% at 1[math] and 12.66% at 1.5[math] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-15T08:00:00Z
      DOI: 10.1142/S0218126620501765
       
  • Logic Design Using Modules and Nonlinear Integer Programming
    • Authors: C. Pavlatos, A. C. Dimopoulos, G. Papakonstantinou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Using logic gates is the traditional way of designing logic circuits. However, in many cases, the use of modules is advantageous as the module is considered a uniform structure composed of multiple gates. In this paper, a nonlinear approach is proposed for designing logic circuits for use as modules multiplexers (MUXs) or Reed–Muller universal blocks (RMs). The experimental results show that the method gives better results compared to other methods available in the literature. The main advantages of the method are that it guarantees minimality and it can also handle Boolean functions for incompletely specified functions. The method is general enough and can be used for any kind of modules.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-14T08:00:00Z
      DOI: 10.1142/S0218126620501649
       
  • Perspective and Opportunities of Modulo 2[math] Multipliers in Residue
           Number System: A Review
    • Authors: Raj Kumar, Ritesh Kumar Jaiswal, Ram Awadh Mishra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo 2[math] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo 2[math] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo 2[math] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-13T08:00:00Z
      DOI: 10.1142/S0218126620300081
       
  • Embedded System Implementation of Shunt Active Power Filter with Direct
           Compensation Component Generation Using Linear Operational Amplifiers
    • Authors: S. Kumaresan, H. Habeebullah Sait
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the principles, the design, the methodology of low cost implementation and the results of implementation of a shunt active power filter (SAPF) in the embedded system environment are presented. The system for which the SAPF is considered has a combination of linear reactive load and a three-phase-fed diode bridge rectifier that drives an RL load. The generation of the compensating signal or the reference signal is based upon the direct calculations implemented using the linear operational amplifiers. Further, the generation of the pulse width modulation (PWM) pulses is much similar to the conventional sinusoidal PWM but implemented in the embedded system platform. In this work, the built-in PWM and ADC sections of the microcontroller PIC 16F877A have been utilized for generating the PWM pulses without the requirement of an explicit carrier signal. The proposed method has been validated in MATLAB SIMULINK environment and also by an experimental prototype.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-10T08:00:00Z
      DOI: 10.1142/S0218126620501662
       
  • Design of a Ku-band MMIC LNA with a Simple T-type Input Matching Network
    • Authors: Tian Qi, Songbai He, Cheng Zhong, Zhitao Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the design of a wideband monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) fabricated in 0.13-[math]m GaAs pHEMT process is presented. A simple T-type input matching network (IMN) and a source feedback structure are employed to achieve low noise figure (NF). The MMIC LNA, which operates across 12–18[math]GHz, can be used for satellite applications. Experimental results show an NF around 1.5[math]dB in 12–17.5[math]GHz and a minimum NF of 1.21[math]dB at 16.5[math]GHz. In addition, a flat small-signal gain of [math][math]dB is achieved at 13.5–17.5[math]GHz. The input return loss is lower than [math] dB at 12–14.5[math]GHz and the output return loss is lower than [math] dB at 12–17[math]GHz. The power consumed is lower than 0.3[math]W and the [math] (1-dB compression point) output power is around 13[math]dBm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-06T08:00:00Z
      DOI: 10.1142/S0218126620200066
       
  • A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage
           Microbolometer Readout Architecture
    • Authors: Mehmet Ali Gülden, Ertan Zencir, Enver Çavuş
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[math]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2020-01-06T08:00:00Z
      DOI: 10.1142/S0218126620501698
       
 
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