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  Subjects -> ELECTRONICS (Total: 184 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 6)
Advances in Electronics     Open Access   (Followers: 79)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 318)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 267)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 106)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 93)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 195)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 67)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 20)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 70)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 25)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 25)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 3)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 169)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 29)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 19)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 54)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [119 journals]
  • Simulation and Analysis of Novel Extendable Multilevel Inverter Topology
    • Authors: V. Thiyagarajan, P. Somasundaram, K. Ramash Kumar
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      Multilevel inverter (MLI) has become more popular in high power, high voltage industries owing to its high quality output voltage waveform. This paper proposes a novel single phase extendable type MLI topology. The term ‘extendable’ is included since the presented topology can be extended with maximum number of dc voltage sources to synthesize larger output levels. This topology can be operated in both symmetrical and asymmetrical conditions. The major advantages of the proposed inverter topology include minimum switching components, reduced gate driver circuits, less harmonic distortion and reduced switching losses. The comparative analysis based on the number of switches, dc voltage sources and conduction switches between the proposed topology and other existing topologies is presented in this paper. The comparison results show that the proposed inverter topology requires fewer components. The performance of the proposed MLI topology has been analyzed in both symmetrical and asymmetrical conditions. The simulation model is developed using MATLAB/SIMULINK software to verify the performance of the proposed inverter topology and also the feasibility of the presented topology during the symmetrical condition has been validated experimentally.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:03:46Z
      DOI: 10.1142/S0218126619500890
       
  • An Efficient Match Search Approach Using Two-Dimensional Hash Function in
           Hardware-Based Dictionary Compression
    • Authors: Qian Dong, Bing Li
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      The hardware-based dictionary compression is widely adopted for high speed requirement of real-time data processing. Hash function helps to manage large dictionary to improve compression ratio but is prone to collisions, so some phrases in match search result are not true matches. This paper presents a novel match search approach called dual chaining hash refining, which can improve the efficiency of match search. From the experimental results, our method showed obvious advantage in compression speed compared with other approach that utilizes single hash function described in the previous publications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:03:40Z
      DOI: 10.1142/S0218126619501068
       
  • An Optimized 2.4[math]GHz RF Energy Harvester for Energizing Low-Power
           Wireless Sensor Platforms
    • Authors: Chandra Shekhar, Shirshu Varma
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      The lifetime of battery-operated sensor platforms (i.e., sensor nodes) is a critical issue. The replacement of their batteries is quite a challenging task if these platforms are deployed for detecting events in inaccessible geographical areas (e.g., forest). This paper describes an optimized RF energy harvester/scavenger (consisting of an antenna, impedance matching circuit and rectifier) for energizing low-power sensor platforms (electronic systems). Few nonmatched rectifiers (using HSMS-285X Schottky diodes) are fabricated to characterize the input impedance for different sets of parameters. After characterization a proper impedance matching circuit is integrated for the maximum power transfer from antenna to rectifier. It is shown that a single stage of RF rectifier is enough to produce output voltage of 1.8[math]V. Very few realizations of RF energy harvester are reported in the literature under 2.4[math]GHz ISM band category. Furthermore, high-gain microstrip patch array antennas are fabricated to capture the maximum power from the surroundings. The maximum harvesting range of 0.92[math]m is obtained at 27[math]dBm transmitting power level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:03:33Z
      DOI: 10.1142/S0218126619501044
       
  • Peak Temperature Minimization for Hard Real-Time Systems Using DVS and DPM
    • Authors: Mingchuan Zhou, Long Cheng, Manuel Dell’Antonio, Xiebing Wang, Zhenshan Bing, M. Ali Nasseri, Kai Huang, Alois Knoll
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      With the increasing power densities, managing the on-chip temperature has become an important design challenge, especially for hard real-time systems. This paper addresses the problem of minimizing the peak temperature under hard real-time constraints using a combination of dynamic voltage scaling and dynamic power management. We derive a closed-form formulation for the peak temperature and provide a genetic-algorithm-based approach to solve the problem. Our approach is evaluated with both simulations and real measurements with an Intel i5 processor. The evaluation results demonstrate the effectiveness of the proposed approach compared to related works in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:03:26Z
      DOI: 10.1142/S0218126619501020
       
  • Improvement of Gray ROM-Based Encoder for Flash ADCs
    • Authors: Mohammad Soleimani, Siroos Toofan
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-[math] thermometer codes to 2-of-[math] codes ([math]). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-[math] codes by the use of two-input AND and four-input merged AND–OR gates. In the second stage, 2-of-[math] codes are turned to [math] gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, [math] MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-[math]m CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30[math]ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50[math]mW and 13.90[math]mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:03:17Z
      DOI: 10.1142/S021812661950097X
       
  • A High Value, Linear and Tunable CMOS Pseudo-Resistor for Biomedical
           Applications
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, P. Georgiou, F. J. Lidgey
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31[math]dB mid-band gain and a low-pass cutoff frequency of 0.85[math]Hz. The circuit operates from a 1[math]V supply and draws 950[math]nA current at room temperature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:03:07Z
      DOI: 10.1142/S0218126619500968
       
  • Design of a Quad-Band Monopole Antenna with Independent Frequency Control
    • Authors: Wang Ren, Peng-Hong Wang
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      A coplanar waveguide (CPW)-fed I-shaped monopole antenna with independent frequency control characteristic is presented for simultaneously satisfying the global positioning system (GPS), wireless local area network (WLAN), and worldwide interoperability for microwave access (WiMAX) applications. It is printed on an FR4 substrate with a single-layered metallic structure and the overall dimensions are [math][math]mm3. The proposed antenna consists of an I-shaped monopole, a pair of split-ring resonators (SRRs), and a coplanar ground plane. The unique advantage of this study is that the four frequency bands are generated individually by different radiating elements. That is, each of them can be controlled independently with little interference from others, which brings added convenience to the antenna design, optimization and debugging processes. Simulated and measured results both demonstrate that it can cover the 1.575[math]GHz GPS (1.57–1.59[math]GHz); 2.4/5.2/5.8[math]GHz WLAN (2.4–2.485, 5.15–5.35 and 5.725–5.825[math]GHz) and 3.5/5.5[math]GHz WiMAX (3.40–3.60 and 5.25–5.85[math]GHz) applications with satisfactory radiation patterns and acceptable gains.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:58Z
      DOI: 10.1142/S0218126619501019
       
  • A Bandwidth Mismatch Optimization Technique in Time-Interleaved
           Analog-to-Digital Converters
    • Authors: Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[math]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:51Z
      DOI: 10.1142/S0218126619500907
       
  • Experimental Verification of Pseudo-Differential Electronically
           Controllable Multifunction Filter Using Modified Current
           Differencing/Summing Units
    • Authors: Jan Jerabek, Jan Dvorak, Roman Sotner, Norbert Herencsar, Jaroslav Koton
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      This paper presents the synthesis and analysis of reconfigurable frequency filter with differential input and differential output terminals and its experimental verification. The inner structure of the filter has single-ended form, i.e., filter behaves as the so-called pseudo-differential circuit. Filtering function can be electronically reconfigured between low-pass (LP) and band-pass (BP) responses. Active elements of the filter are differential voltage buffer (DVB) as an input stage and modified current differencing unit (MCDU) together with modified current summing unit (MCSU) as the inner and also output stage. Each of the important parameters of the filter (angular pole frequency, quality factor and pass-band gain) is electronically controllable by parameters of these active elements used. Some of the parameters of the filter are controlled by two independent parameters, i.e., are dual-controlled, which enables the extended electronic controllability. The proposed topology operates in the voltage mode and both input nodes have high input impedance. Expected behavior of the filter is analyzed and verified by PSpice simulations using CMOS models of above-mentioned active elements. Moreover, features of the filter in both configurations were successfully verified also by experimental measurements using behavioral models of active elements.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:39Z
      DOI: 10.1142/S0218126619500981
       
  • A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs
    • Authors: Jing Li, Xin Ye, Jian Luo, Ning Ning, Qi Yu
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd–even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with [math] samples and costs less hardware with 2.1[math]k gate counts.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:30Z
      DOI: 10.1142/S0218126619500920
       
  • Firefly Algorithm for Intelligent Context-Aware Sensor Deployment Problem
           in Wireless Sensor Network
    • Authors: Puri Vishal, A. Ramesh Babu
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      Wireless sensor networks (WSNs) provide acceptable low cost and efficient deployable solutions to execute the target tracking, checking and identification of substantial measures. The primary step necessary for WSN is to organize all the sensor nodes in their positions to build up an effective network. In the sensor deployment model, Target COVerage (TCOV) and Network CONnectivity (NCON) are the basic issues in WSNs that have obtained significant consideration in sensor deployment. This paper intends to develop an intelligent context awareness algorithm for sensor deployment process in WSN. Accordingly, the process is divided into two phases. In the first phase, the TCOV process is performed, whereas the second phase of the algorithm establishes NCON among the sensors. An objective model to meet both TCOV and NCON is formulated as a minimization problem. The problem is solved using FireFly (FF) optimization to determine the optimal locations for sensors. It leads to an intelligent sensor deployment model that can determine the optimal locations for the sensors in the WSN. Further, the proposed FF-TCOV and FF-NCON models are compared against the conventional algorithms, namely, genetic algorithm, particle swarm optimization, artificial bee colony, differential evolution and evolutionary algorithm-based TCOV and NCON models. The results achieved from the simulation show the improved performance of the proposed technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:24Z
      DOI: 10.1142/S0218126619500944
       
  • A Review of Cost and Makespan-Aware Workflow Scheduling in Clouds
    • Authors: Pingping Lu, Gongxuan Zhang, Zhaomeng Zhu, Xiumin Zhou, Jin Sun, Junlong Zhou
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      Scientific workflow is a common model to organize large scientific computations. It borrows the concept of workflow in business activities to manage the complicated processes in scientific computing automatically or semi-automatically. The workflow scheduling, which maps tasks in workflows to parallel computing resources, has been extensively studied over years. In recent years, with the rise of cloud computing as a new large-scale distributed computing model, it is of great significance to study workflow scheduling problem in the cloud. Compared with traditional distributed computing platforms, cloud platforms have unique characteristics such as the self-service resource management model and the pay-as-you-go billing model. Therefore, the workflow scheduling in cloud needs to be reconsidered. When scheduling workflows in clouds, the monetary cost and the makespan of the workflow executions are concerned with both the cloud service providers (CSPs) and the customers. In this paper, we study a series of cost-and-time-aware workflow scheduling algorithms in cloud environments, which aims to provide researchers with a choice of appropriate cloud workflow scheduling approaches in various scenarios. We conducted a broad review of different cloud workflow scheduling algorithms and categorized them based on their optimization objectives and constraints. Also, we discuss the possible future research direction of the clouds workflow scheduling.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:17Z
      DOI: 10.1142/S021812661930006X
       
  • Fully Electronically Tunable and Easily Cascadable Square/Triangular Wave
           Generator with Duty Cycle Adjustment
    • Authors: Bhartendu Chaturvedi, Atul Kumar
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      A novel multiple-output dual-X current conveyor transconductance amplifier with buffer-based square/triangular wave generator is introduced in the paper. The proposed generator provides square wave in current mode and triangular wave in voltage mode. Outputs as square and triangular waves are available from terminals with appropriate impedance levels thereby making the proposed generator circuit easily cascadable in both current and voltage modes. The oscillation frequency and amplitude of output square wave are electronically and independently controllable. One more interesting feature of the proposed generator circuit is the adjustable duty cycle. The proposed circuit of square/triangular wave generator is verified through the HSPICE simulation results carried using 0.18[math][math]m CMOS technology. The simulation results show linear variation of duty cycle against external DC current over a range of 6.5–96%. The variation of square wave’s amplitude via bias current is found to be linear from 10[math][math]A to 80[math][math]A. Moreover, the proposed generator can operate very well up to 23.8[math]MHz with nonlinearity less than 5%. The proposed generator circuit is also experimentally verified.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:11Z
      DOI: 10.1142/S0218126619501056
       
  • A Thermal Mitigation Algorithm Based on the Power Characteristics of
           Mobile Application Processors
    • Authors: Chang Min Eun, Hyun Hak Cho, Ok Hyun Jeong
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      Modern mobile devices suffer from severe power and thermal issues due to the adoption of high-frequency multi-core processors. However, methods of resolving the thermal problems in mobile environments are restricted due to their size, semiconductor process technology, and battery limitations. Mobile devices generally rely on a software framework called the Thermal Management Model (TMM). However, conventional TMMs suffer from inevitable performance degradation due to the thermal response. We propose a new Thermal Mitigation Algorithm (TMA) to optimize performance and thermal mitigation by considering the multi-core power curve of a mobile CPU which is experimentally derived using a typical smartphone and thus resolve this issue. Our proposed scheme aims to reduce thermal problems and enhance system performance by limiting the usage of power-inefficient frequencies when operating on a multi-core. We evaluate the proposed algorithm on a real system using a typical smartphone and conduct the performance measurement using the AnTuTu benchmark v4.5.1. In addition, we use the on-chip temperature sensors of CPU cores and a crystal oscillator embedded in the Application Processor (AP) to monitor the temperature of the mobile device. The result shows that our scheme, respectively reduce the average temperatures of CPU cores and a crystal oscillator by 6.61% and 5.02% while improving system performance by 3.24%. In conclusion, we reduce the thermal problems and enhance performance simultaneously using the proposed TMA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:02:04Z
      DOI: 10.1142/S0218126619501032
       
  • Analysis and Design of a New 10-Bit High Accuracy and Resolution TDC by
           Elimination of Offset Voltage and Parasitic Capacitors Effects
    • Authors: Mahdi Rezvanyvardom, Amin Mirzaei
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18[math][math]m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:01:55Z
      DOI: 10.1142/S0218126619500956
       
  • Systematic Hysteresis Analysis for Dynamic Comparators
    • Authors: Leïla Khanfir, Jaouhar Mouïne
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized. In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18[math][math]m CMOS technology showing a maximum error of 8.6%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:01:44Z
      DOI: 10.1142/S0218126619501007
       
  • Second Order Universal Filter Using Four Terminal Floating Nullor (FTFN)
    • Authors: Ashish Ranjan, Subrahmanyam Perumalla, Ravi Kumar, Vista John, Shantikumar Yumnam
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      In this research paper, a voltage mode second order universal filter using Four Terminal Floating Nullor (FTFN) is presented. The proposed design uses Three Input Single Output (TISO) for the realization of all filter responses namely Low Pass Filter (LPF), High Pass Filter (HPF), Band Pass Filter (BPF), Notch Filter (NF) and All Pass Filter (APF) by using proper input selection. The analog building block, FTFN is simply realized with two commercially available AD844 ICs. The proposed second order universal filter comes with a single FTFN block with four passive components in which no component matching is required for filter realization. The universal filter is well verified using PSPICE simulation. In addition, experimental verification for the second order APF has been performed that confirms the theoretical expectations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:01:37Z
      DOI: 10.1142/S0218126619500919
       
  • Image De-Hazing Via Gradient Optimized Adaptive Forward-Reverse Flow-Based
           Partial Differential Equation
    • Authors: U. A. Nnolim
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      In this study, we propose a modified partial differential equation (PDE)-based algorithm for image de-hazing. The algorithm possesses relatively low computational complexity and the core function of the PDE is easily amenable to hardware implementation. New contributions include the optimization and automated processing for dark and hazy images, avoiding manual parameter tuning. Additionally, the regularization parameter is computed adaptively from the binary mask of the input image. This is combined with a gradient-based metric for optimization to automatically determine stopping time of the algorithm for both types of images. The proposed scheme is fast and utilizes spatial or frequency domain filters to achieve illumination and reflectance component estimation without resorting to logarithms. Moreover, there is absence of halos in de-hazed images compared to previous work. Extensive experiments indicate that the proposed approach yields results comparable to or better than several works from the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:01:30Z
      DOI: 10.1142/S0218126619500993
       
  • Novel Lossless Grounded and Floating Inductance Simulators Employing a
           Grounded Capacitor Based on CC-CFA
    • Authors: Amrita Singh, Manoj Kumar Jain, Subodh Wairya
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 06, 15 June 2019.
      Simulation of inductors has been a very popular area of analog circuit research and the alternative choice for realizing inductor-based circuits in integrated circuits. In this paper, lossless, grounded and floating inductor topologies using current-controlled-current-feedback amplifier (CC-CFA) with single grounded capacitor are presented. The proposed topologies can be tuned electronically by changing the biasing current of the CC-CFA. Two topologies for grounded inductor simulator employ two CC-CFA and one grounded capacitor. One topology for floating inductor simulator employs three CC-CFA and one grounded capacitor. The performance of the grounded and floating inductor simulators are demonstrated on resonant circuits. The theoretical analysis is verified by PSPICE simulation results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-12T10:01:23Z
      DOI: 10.1142/S0218126619500932
       
  • Special Issue on Design, Technology, and Test of Integrated Circuits and
           Systems
    • Authors: Alberto Bosio, Mario Barbareschi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.

      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-10T09:06:28Z
      DOI: 10.1142/S0218126619020018
       
  • An Enhanced Evolutionary Technique for the Generation of Compact
           Reconfigurable Scan-Network Tests
    • Authors: Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behavior, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Post-processing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploration.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-06T08:04:03Z
      DOI: 10.1142/S0218126619400073
       
  • Implementation of Modified Field-Oriented Control Scheme for Improving the
           Fault Ride Through Ability of BDFIG System
    • Authors: Maheswari Muthusamy, A. K. Parvathy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper devises a design named brushless doubly fed induction generator (BDFIG) with a fault ride-through enhancement that employs upgraded field-oriented control (FOC) scheme. The DFIG is most suitable for wind energy conversion system (WECS) because it has an amicable establishment, economical operation and promising characteristics. A WECS based on two BDFIGs connected electrically in parallel and mechanically in series, excited by a three-phase inverter and controlled as variable speed, is described. For enhancing power quality and power flow capability, static compensator (STATCOM) has been incorporated in the proposed configuration. The comparative analysis on performance has been carried out with the existing proportional-integral (PI) controller and self-tuning fuzzy logic controller (STFLC) for the proposed configuration under varying wind speed. In this paper, the fuzzy controller is designed to adapt PI parameters Kp and Ki, in order to reduce at least some inherent characteristics (overshoot, response time, etc.) of the error between the reference and system response. The digital simulation results claim that the FLC-based controller can offer an attractive and feasible control for the proposed WECS integrating two BDFIGs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-30T08:49:53Z
      DOI: 10.1142/S0218126620500401
       
  • Toward a Unified Performance Metric for Benchmarking Steganography Systems
    • Authors: Tamer Rabie, Mohammed Baziyad, Talal Bonny, Raouf Fareh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent advances in network speeds for exchanging multimedia data over insecure networks has resulted in an increased interest in steganography techniques. These techniques are usually evaluated based on their performance in three attributes; namely, capacity, imperceptibility, and robustness. Each of these attributes has its own measurement metric. Hence, comparing two different steganography schemes based on these individual metric tools becomes inconsistent. In this paper, a novel measurement metric tool is introduced for benchmarking steganography schemes. This new tool, named the “Combined Capacity-Quality-Robustness Effectiveness” (CCQRE) metric, combines the three opposing attributes of a steganography system into one conglomerate performance measure. Comparative results demonstrate the effectiveness of the proposed CCQRE metric for benchmarking various steganography schemes based on the researcher’s interest in capacity, imperceptibility, or robustness.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:39Z
      DOI: 10.1142/S0218126620500425
       
  • An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit
           Asynchronous SAR Quantizer for Medical Applications
    • Authors: Sahel Javahernia, Esmaeil Najafi Aghdam, Pooya Torkzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [math] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[math][math]m CMOS technology achieves 95.98[math]dB peak signal-to-noise and distortion (SNDR) for 10[math]KHz signal bandwidth and dissipates 44[math][math]w while its FOM is obtained about 43 fJ/conv.-step.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:38Z
      DOI: 10.1142/S0218126620500565
       
  • Termination Transformation Theorem for Microwave Power Transfer Networks
    • Authors: Ramazan Kopru
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Termination transformation theorem (TTT) proposed in this work transforms a doubly complex terminated microwave power transfer network (PTN) to an equivalent doubly resistively terminated termination transformed network (TTN) which is essentially a filter network. In this work, the transducer power gain (TPG) formula, Tgen, based on S and transmission (ABCD) parameters for the PTN have been restudied from the classical literature. Then, a new TPG formula, Tgen1, based on the newly proposed TTT has been derived using the transformed TTN network. To be able to show the validity of the proposed TTT, the newly derived TPG formula Tgen1 and the classical TPG formula Tgen have been computed within the scope of an example PTN design. The theorem has been proved mathematically, and experimentally as well with the aid of a Matlab code. The performance plots yielded from the Matlab code have clearly shown that both TPG formulae, i.e., Tgen and Tgen1, are in complete agreement with each other. In that sense, the proposed TTT might be considered as an alternative and helpful technique to be used in microwave engineering.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:37Z
      DOI: 10.1142/S0218126620500437
       
  • Design and Analysis of Inset Fed Wide-Band Rectenna with Defected Ground
           Structure
    • Authors: Asmita Rajawat, P. K. Singhal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The design proposed and fabricated in this paper is a slotted wide-band rectenna with the inclusion of Defected Ground Structure (DGS) which can harvest RF energy in the frequency range of 5.336–6.194[math]GHz with a center frequency of 5.8[math]GHz. For the development of antenna, FR4 substrate having a dielectric permittivity of 4.3 has been adopted. Two parallel slots on the patch are incorporated on either side of the feed line to obtain the wide-band structure. Dumbbell-shaped DGS is also incorporated exactly underneath the feed line to increase the gain of the antenna. HSMS-285C Schottky diode has been used for the implementation of the rectifier circuit and a Greinacher voltage doubler has been chosen. ADS design software has been used for rectifier simulation and CST has been used for the designing of the antenna. Current behavior on the patch can be investigated to explore the wide-band mechanism. The antenna operates in the frequency range of 5.336–6.194[math]GHz and with VSWR less than 2, which corresponds to 16.07% impedance bandwidth. The antenna achieves a gain of 6.189[math]dB and a directivity of 8.776[math]dBi. The conversion efficiency of the rectifier was optimized to 75% at 5.8[math]GHz. The proposed design gave an output of 3.2[math]V which can be used under numerous energy harvesting and wireless power transmission applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:36Z
      DOI: 10.1142/S0218126620500474
       
  • Novel Monopole Microstrip Antennas for GPS, WiMAX and WLAN Applications
    • Authors: Biplab Bag, Priyabrata Biswas, Sushanta Biswas, Partha Pratim Sarkar, Dibyendu Ghoshal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, two novel low-profile monopole antennas are presented for simultaneous operation in GPS (Global Positioning System), WLAN (Wireless Local Area Network) and WiMAX (Worldwide Interoperability for Microwave Access) applications. The antennas constitute of a T-shaped microstrip feed line and directly coupled strips to generate multiple bands. The proposed antennas are printed on one side of a low-cost FR4 epoxy substrate and partial ground plane (metal plane is etched partially) are fabricated on the other side of the substrate. The overall dimension of antenna is [math][math]mm3. Measured results show that the antenna1 (quad band) covers the four distinct operating bands of 320[math]MHz (2.17–2.49[math]GHz), 190[math]MHz (3.31–3.50[math]GHz), 270[math]MHz (5.18–5.45[math]GHz) and 700[math]MHz (5.5–6.20[math]GHz). Antenna2 (penta band) covers the frequency bands of 1.29–1.98[math]GHz (center frequency 1.61[math]GHz), 2.78–2.91[math]GHz (center frequency 2.83[math]GHz), 3.59–3.94[math]GHz (center frequency 3.75[math]GHz), 5.15–5.33[math]GHz (center frequency 5.24[math]GHz) and 5.39–6.06[math]GHz (center frequency 5.56[math]GHz). The detail antenna design and parametric analyses are discussed in steps. The characteristic of radiation pattern and gain are measured. The measured and simulated results are in good agreement. The antennas are designed using a simulation software HFSS v.15.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:11:00Z
      DOI: 10.1142/S0218126620500504
       
  • New Voltage-Mode Sinusoidal Oscillators Using VDIBAs
    • Authors: San-Fu Wang, Hua-Pin Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents two new voltage-mode sinusoidal oscillators based on voltage differencing inverting buffered amplifier (VDIBA). The first proposed circuit exhibits independent and electronic control of oscillation condition by using the bias current of the VDIBA. The proposed configuration contains only single VDIBA, two grounded capacitors and two resistors, which are the least number of active components and the minimum number of passive components necessary for realizing voltage-mode oscillator topology. The second proposed circuit exhibits independent and electronic control on the condition of oscillation without affecting the oscillation frequency by adjusting the separate bias currents of the VDIBAs. The proposed configuration contains two VDIBAs, two grounded capacitors and one resistor, which can provide four quadrature voltage outputs simultaneously. Both proposed circuits enjoy only two grounded capacitors, which are suitable for monolithic integration. HSpice simulations and experimental results are included to confirm the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:11:00Z
      DOI: 10.1142/S0218126620500528
       
  • Simple Double-Scroll Chaotic Circuit Based on Meminductor
    • Authors: D. D. Zhai, F. Q. Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Meminductor has attracted more and more attention as the new memory element. In this paper, a new generic meminductor model is proposed and analyzed. Its emulator is designed and its pinched hysteresis loop is presented. Based on the established meminductor and using a traditional capacitor and resistor, a new simple chaotic circuit presenting double-scroll chaotic attractors is proposed and its dynamical behaviors including phase portrait, Lyapunov exponents, Poincare mapping, power spectrum, bifurcation and the sensibility of initial value are analyzed. Meanwhile, it has been found that hidden attractors and transient chaotic phenomena under different initial value. Finally, the hardware circuit for the proposed simple double-scroll chaotic system is constructed and some experimental results are presented for validating the correctness of the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:58Z
      DOI: 10.1142/S0218126620500486
       
  • FPGA Implementation of the Generalized Parallel Two-Box Model-based
           Digital Predistorter for Wireless Transmitters
    • Authors: Ahmad Rahati Belabad, Soheil Shahrooz, Saeed Sharifian, Seyed Ahmad Motamedi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the FPGA implementation of the generalized parallel two-box (GPTB) model is proposed. The blocks such as multipliers, complex magnitude calculator, and magnitude powers calculator have been utilized to implement the GPTB model. In the implementation of the proposed model, a total of 30 complex multipliers, 56 noncomplex multipliers and 56 adders were used. The GPTB DPD model has been implemented by using System Generator and Vivado software. The FPGA with a part number of xc7vx690t-3 from Xilinx has been employed to implement the model. The simulation results demonstrate the correctness of the implemented model in Vivado. Also, the verification of the GPTB model is accomplished by means of the simulation of the transmitter excited by QAM signals in the ADS software. The measure of an adjacent channel power ratio (ACPR) decreased by about 16[math]dB as a result of the simulation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:57Z
      DOI: 10.1142/S0218126620500541
       
  • A High-Data-Rate Area-Efficient Uni-Pulse Harmonic Modulation Transmitter
           for Implantable Neural Recording Microsystems
    • Authors: Mohammad Zinaty, Parviz Amiri, Mohammad Hossein Maghami
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new data transmission method, named Uni-Pulse Harmonic Modulation (PHM), is presented and its concept is mathematically analyzed using the relations of inductive links. In this type of modulation, the Uni-Pulse passing through the primary coil generates an oscillation in the secondary coil, corresponding to its positive edge, and its negative edge is able to damp this oscillation. The Uni-Pulse passing the primary coil gives the opportunity to use a half-bridge driver instead of full-bridge driver and hence the chip area is desirably reduced. For implementing the proposed modulation technique, two half-bridge driver circuits are suggested that are controlled by series of transistors and transmission gates occupying 900[math][math]m2 and 737.87[math][math]m2 of chip area, respectively. Another merit of the proposed transmitters, besides their occupying low chip area, is that they can transmit data at the rate of 40[math]MHz, while the received frequency is set at 66.6[math]MHz. Therefore, the high amount of 60% is obtained for the data rate to carrier frequency ratio. Designed in a standard 0.18-[math]m CMOS process, the proposed circuits operate at 1.8[math]V supply voltages with consuming almost 400[math]pj energy for transmitting each data bit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:57Z
      DOI: 10.1142/S0218126620200017
       
  • A Scaler Design for the RNS Three-Moduli Set [math] Based on Mixed-Radix
           Conversion
    • Authors: Ahmad Hiasat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Adopting the moduli set [math] for different DSP applications instead of the traditional moduli set [math] has the advantage of excluding modulus [math]. A multiply-and-accumulate modulo [math] unit is more demanding than a modulo [math] unit, which signifies the importance of this adoption. This paper introduces a new design for a scaling unit “Scaler”, that deals with the arithmetic-friendly residue number system (RNS) moduli set [math]. The scaling factor is the power-of-two moduli [math]. The scaling algorithm is based on the mixed-radix conversion (MRC) technique, which converts RNS-based representation into a weighted representation. The proposed approach is compared with other functionally-identical or functionally-similar scalers that perform scaling for the same moduli set under consideration or for the moduli set [math]. The comparison is carried using theoretical unit-gate approach and experimental VLSI layout approach. The proposed scaler is shown to be more area and power-efficient than recently published competitive works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:56Z
      DOI: 10.1142/S0218126620500413
       
  • A Statistical Test Generation Based on Mutation Analysis for Improving the
           Hardware Trojan Detection
    • Authors: Yanjiang Liu, Yiqiang Zhao, Jiaji He, Ruishan Xin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:56Z
      DOI: 10.1142/S0218126620500498
       
  • Integrated Passive Devices and Switching Circuit Design for a 3D DC/DC
           Converter up to 60 V
    • Authors: Sergio Saponara, Gabriele Ciarpi, Tobias Erlbacher, Gudrun Rattmann
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work presents the design and test of a switched-cap 3D DC/DC converter able to work up to 60[math]V. The switches and the control circuits are integrated single-chip in a high-voltage (HV) MOS technology, and the passive devices are stacked on top of the chip. As an innovation versus the state-of-the-art, the work first presents the design of integrated passive devices, based on through silicon vias (TSV) MOS-compatible technology, which are suitable for switching converter applications up to 60[math]V. Then, the implementation and experimental characterization of the switched-cap 3D DC/DC is proposed, with the silicon TSV capacitors stacked on top of the 0.35[math][math]m HV-MOS die. Compared with the state-of-the-art, the proposed 3D DC/DC converter is a compact circuit, able to directly regulate a wide input voltage range (from 6[math]V to 60[math]V) to a 5[math]V, 2[math]W output. Hence, it is suitable to supply low-power loads, such as control units and/or sensors, directly from the 48[math]V power line available in hybrid vehicles or telecom and networking systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:55Z
      DOI: 10.1142/S0218126620500395
       
  • Multimodal Wireless Sensor Networks for Monitoring Applications: A Review
    • Authors: Juan Aranda, Diego Mendez, Henry Carrillo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor networks (WSNs) are a widely used solution for monitoring-oriented applications (e.g., water quality on watersheds, pollution monitoring in cities). These kinds of applications are characterized by the necessity of two data-reporting modes: time-driven and event-driven. The former is used mainly for continually supervising an area and the latter for event detection and tracking. By switching between both modes, a WSN can improve its energy efficiency and event-reporting latency, compared to single data-reporting schemes. We refer to those WSNs, where both data-reporting modes are required simultaneously, as multimodal wireless sensor networks (M2WSNs). In this paper, we present, from an energy-efficiency perspective, a review of switching mechanisms for M2WSNs. Besides, we explore two sophisticated techniques required in M2WSNs for further energy saving and event-reporting latency reduction purposes: duty-cycling and wake-up radio. We highlight future directions concerning switching and network management techniques for M2WSNs. To our knowledge, this review is first of its kind.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:21Z
      DOI: 10.1142/S0218126620300032
       
  • Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using
           Nanoscale Hierarchical Implementation Model
    • Authors: Theodoros Simopoulos, George Ph. Alexiou, Themistoklis Haniotakis
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, we extend the implementation guidelines of the WDSRAM — Write Driver SRAM — through the definition of a hierarchical implementation model which is applied on the material layout memory design level. This model can be used in order to create WDSRAMs of any size, maintaining the memory’s write function speed-up against the typical SRAM implementation model. The post-layout simulation results are presented in comparison with the corresponding results of the typical SRAM and confirm that the WDSRAM write function speed-up is maintained against the typical SRAM when the memory size increases. A brief background knowledge on the WDSRAM function is also provided.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:21Z
      DOI: 10.1142/S0218126619400085
       
  • Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells
           Comprising D- and E-Mode HEMTs
    • Authors: Aleš Chvála, Lukáš Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Šatka, Michal Blaho, Dagmar Gregušová, Ján Kuzmík
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents monolithic integrated InAlN/GaN NAND and NOR logic cells comprising depletion-mode, enhancement-mode and dual-gate enhancement-mode high electron mobility transistors (HEMTs). The designed NAND and NOR logic cells consist of the depletion-mode and enhancement-mode HEMT transistors integrated onto a single die. InAlN/GaN-based NAND and NOR logic cells with good static and dynamic performance are demonstrated for the first time. Calibrated static and dynamic electrophysical models are proposed for 2D device simulations in Sentaurus Device environment. Sentaurus Device mixed-mode setup interconnects the transistors to NAND and NOR logic circuits which allows analysis and characterization of the devices as a complex system. Circuit models of depletion-mode, enhancement-mode and dual-gate HEMTs are designed and calibrated by experimental results and 2D device simulations. The proposed models exhibit highly accurate results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:20Z
      DOI: 10.1142/S0218126619400097
       
  • Fault Tolerant Control for Wind Turbine System Based on Model Reference
           Adaptive Control and Particle Swarm Optimization Algorithm
    • Authors: Yassine Fadili, Ismail Boumhidi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper tackles the problem of Fault Tolerant Control (FTC) for Wind Turbine System. Motivated by the Model Reference Adaptive Control (MRAC) and the Particle Swarm Optimization Algorithm (PSOA), the main contribution of this work is to provide online tuning for the wind turbine controller. In order to achieve the required system performances, even during components and/or system faults, our proposed strategy takes care of an adaptive controller in which the desired performance is expressed in terms of a reference model. The controller parameter adjustments are made using the stability theory that involves the gradient function and the Lyapunov function. Moreover, the minimization of the fitness function of PSOA allows convergence of the proposed MRAC to an optimal point, owing to redistribution of the control signals when a failure or noise occurs. The simulation results have shown good performance than some existing approaches in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:20Z
      DOI: 10.1142/S0218126620500371
       
  • Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier
           with Reduced Power Dissipation
    • Authors: Mohammad Moradinezhad Maryan, Seyed Javad Azhari, Mehdi Ayat, Reza Rezaei Siahrood
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[math][math]m TSMC (level-49) CMOS technology. Simulation results with [math]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [math][math]dB bandwidth (BW) is 903[math]MHz, the total harmonic distortion (THD) is 0.3% (at 1[math]MHz), and the maximum and static power consumption are [math]W and [math]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [math][math]dB BW as 657[math]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-10T09:16:33Z
      DOI: 10.1142/S0218126620500383
       
  • RF/Microwave Power Amplifiers: The Development Route and State-of-the-Art
    • Authors: Xuguang Li, Haipeng Fu, Kaixue Ma, Shoukui Zhu, Qianfu Cheng, Jianguo Ma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent decades have seen significant progresses in the field of power amplifiers (PAs). In order to present the evolution of the field, this paper shows the development trends of the PA research based on the statistical analysis from 1970 to 2017. The brief history of radio frequency (RF)/microwave PAs and a comprehensive review on the evolution of RF/microwave PAs are presented. The state-of-the-art PAs thus far based on the statistical analysis in terms of the figure of merit (FoM) of RF/microwave PAs have been discussed in this paper. A quantitative relationship of trade-off of PA performance metrics is proposed, and the potential room for improvement of the performance of the PAs is also revealed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:48Z
      DOI: 10.1142/S0218126620300044
       
  • Classification of EEG Signals Based on Filter Bank and Sparse
           Representation in Motor Imagery Brain-Computer Interfaces
    • Authors: Jin Wang, Qingguo Wei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To improve the classification performance of motor imagery (MI) based brain-computer interfaces (BCIs), a new signal processing algorithm for classifying electroencephalogram (EEG) signals by combining filter bank and sparse representation is proposed. The broadband EEG signals of 8–30[math]Hz are segmented into 10 sub-band signals using a filter bank. EEG signals in each sub-band are spatially filtered by common spatial pattern (CSP). Fisher score combined with grid search is used for selecting the optimal sub-band, the band power of which is employed for designing a dictionary matrix. A testing signal can be sparsely represented as a linear combination of some columns of the dictionary. The sparse coefficients are estimated by [math] norm optimization, and the residuals of sparse coefficients are exploited for classification. The proposed classification algorithm was applied to two BCI datasets and compared with two traditional broadband CSP-based algorithms. The results showed that the proposed algorithm provided superior classification accuracies, which were better than those yielded by traditional algorithms, verifying the efficacy of the present algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:48Z
      DOI: 10.1142/S0218126620500346
       
  • An S-Band CMOS 6-Bit Vector-Sum Phase Shifter with Low RMS Phase Error
           Using Frequency-to-Voltage Converter Feedforward Loop
    • Authors: Mostafa Nobakht Sarkezeh, Aminghasem Safarian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2–4[math]GHz) applications. The designed phase shifter in 180[math]nm CMOS technology achieves an RMS phase error in the range of 0.607–1.18∘ with [math][math]dBm input signal over 2–4[math]GHz frequency band. With lower input signal of [math][math]dBm, the RMS phase error is 0.621–1.34∘ for 2–4[math]GHz input frequency. The proposed phase shifter shows an RMS amplitude error less than 0.41[math]dB over 2–4[math]GHz frequency. The 1-dB compression point ([math]) of the proposed phase shifter is [math][math]dBm. The proposed wideband phase shifter draws 32 mA from 1.8 supply voltage. It occupies an active area of only 0.025[math]mm2, due to active design without any inductor.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:47Z
      DOI: 10.1142/S021812662050036X
       
  • 1/[math] (Close-in) Phase Noise Reduction by Tail Transistor Flicker Noise
           Suppression Technique
    • Authors: Jalil Mazloum, Samad Sheikhaei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel circuit method is proposed to reduce 1/[math] (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/[math] output phase noise is reduced by 5.7[math]dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18[math][math]m CMOS technology with 1.8[math]V supply and 3.6[math]mW power consumption. Post-layout simulations predict a phase noise of [math][math]dBc/Hz for the proposed oscillator at 100[math]KHz offset from 3.1[math]GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6[math]dBc/Hz at 100[math]KHz and 1[math]MHz offsets, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:47Z
      DOI: 10.1142/S0218126620500358
       
  • In-Network Distributed Least-Mean-Square Identification of Nonlinear
           Systems Using Volterra–Laguerre Model
    • Authors: Saurav Gupta, Sachin N. Kapgate, Ajit Kumar Sahoo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      It is of great importance to model the behavior of nonlinear systems in a distributed fashion using wireless sensor networks (WSNs) because of their computation and energy-efficient data processing. However, least squares methods have been previously employed to estimate the parameters of Volterra model for modeling nonlinear systems. Still, it is more convenient and advantageous to use in-network distributed identification strategy for real-time modeling and control. In this context, a black-box model with generalized structure and remarkable modeling ability called Volterra–Laguerre model is considered in which distributed signal processing is employed to identify the nonlinear systems in a distributed manner. The model cost function is expressed as a separable constrained minimization problem which is decomposed into augmented Lagrangian form to facilitate the distributed optimization. Then, alternating direction method of multipliers is employed to estimate the optimal parameters of the model. Convergence of the algorithm is guaranteed by providing its mean stability analysis. Simulation results for a nonlinear system are obtained under the noisy environment. These results are plotted against the results of noncooperative and centralized methods, demonstrating the effectiveness and superior performance of the proposed algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:41Z
      DOI: 10.1142/S0218126620500309
       
  • A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network
    • Authors: Peng Guo, Hong Ma, Ruizhi Chen, Donglin Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although the convolutional neural network (CNN) has exhibited outstanding performance in various applications, the deployment of CNN on embedded and mobile devices is limited by the massive computations and memory footprint. To address these challenges, Courbariaux and co-workers put forward binarized neural network (BNN) which quantizes both the weights and activations to [math]1. From the perspective of hardware, BNN can greatly simplify the computation and reduce the storage. In this work, we first present the algorithm optimizations to further binarize the first layer and the padding bits of BNN; then we propose a fully binarized CNN accelerator. With the Shuffle–Compute structure and the memory-aware computation schedule scheme, the proposed design can boost the performance for feature maps of different sizes and make full use of the memory bandwidth. To evaluate our design, we implement the accelerator on the Zynq ZC702 board, and the experiments on the SVHN and CIFAR-10 datasets show the state-of-the-art performance efficiency and resource efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:41Z
      DOI: 10.1142/S0218126619400048
       
  • An Experimental Study of Metastability-Induced Glitching Behavior
    • Authors: Thomas Polzer, Florian Huemer, Andreas Steininger
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [math] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:41Z
      DOI: 10.1142/S0218126619400061
       
  • Advances in Concurrent Computing for Digital Stochastic Measurement
           Simulation
    • Authors: Nebojsa Pjevalica, Velibor Pjevalica, Nenad Petrovic
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces a concurrent computing technique for the acceleration of digital stochastic measurement simulations. The digital stochastic measurement presents an advanced methodology based on the specific parallel hardware structure, utilized for an orthogonal transformation calculus/decomposition. Methodology is analyzed in detail, starting from the very basic idea, toward recent references, covering main research directions and trends. An oversampling nature of the evaluated digital stochastic measurement, along with demanding arithmetic requirements, implies exhausting simulation complexity. As a test case, several typical power grid signals were harmonically analyzed through a discrete Fourier transformation based on the proposed methodology. A harmonic decomposition was simulated with several levels of computing concurrency. Through all the simulated scenarios main success criterion was model accuracy, while the parameter used for selection of the optimal simulation computing technique was the overall calculus speed. Final results exposed thread pool computing technique as an optimal simulation platform.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:40Z
      DOI: 10.1142/S0218126620500334
       
  • A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at
           Board Level
    • Authors: Hassan Ebrahimi, Hans G. Kerkhoff
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The reliability of board-level data communications intensively depends on the reliability of interconnections on a board. One of the most challenging interconnections reliability threats is intermittent resistive faults (IRFs). Detecting such faults is a major challenge. The main reason is the random behavior of these faults. They may occur randomly in time, duration and amplitude. The occurrence rate can vary from a few nanoseconds to months. This paper investigates IRF detection at the board level by introducing a new digital in situ IRF monitor. Hardware-based fault injection has been used to validate the proposed IRF monitor. As case studies, two widely used on-board transmission protocols namely the Universal Asynchronous Receiver Transmitter (UART) and the Serial Peripheral Interface bus (SPI), have been used. In addition, one fault management framework, based on the IJTAG standard, has been implemented to collect and characterize information from the monitors. The experimental results show that the proposed monitor is effective in detecting IRFs at the board level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-27T01:30:37Z
      DOI: 10.1142/S0218126619400036
       
  • A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems
    • Authors: Lukáš Kohútka, Lukáš Nagy, Viera Stopjaková
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-27T01:30:36Z
      DOI: 10.1142/S021812661940005X
       
  • Design, Fabrication and Measurement of a Novel Compact Triband CPW-Fed
           Planar Monopole Antenna Using Multi-type Slots for Wireless Communication
           Applications
    • Authors: Ahmed Zakaria Manouare, Saida Ibnyaich, Divitha Seetharamdoo, Abdelaziz EL Idrissi, Abdelilah Ghammaz
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel compact coplanar waveguide (CPW)-fed planar monopole antenna with triple-band operation is presented for simultaneously satisfying the LTE 2600, WiMAX, WLAN and X-band applications. It is printed on a single-layered FR4 substrate. In this paper, the proposed antenna, which occupies a small volume of [math][math]mm3 including the ground plane, is simply composed of a CPW-fed monopole with U-, L- and T-shaped slots. By carefully selecting the lengths and positions of both L-shaped and U-shaped slots, a good dual notched band characteristic at center-rejected frequencies of 3.10[math]GHz and 4.50[math]GHz can be achieved, respectively. The T-shaped slot is etched on the radiating element to excite a resonant frequency in the 7[math]GHz band. Then, to prove the validation of the typical design, a prototype model is fabricated and measured. The experimental result shows that the three frequency bands of 2.31–2.80[math]GHz (490[math]MHz), 3.37–3.84[math]GHz (470[math]MHz) and 5.04–7.94[math]GHz (2900[math]MHz) can successfully cover the desired bandwidths of LTE2600/WiMAX (3.50/5.50[math]GHz)/WLAN (5.20/5.80[math]GHz) and the X-band communication systems (7.1-GHz operation). The principal applications of the X-band are radar, aircraft, spacecraft and mobile or satellite communication system. Nearly omnidirectional and bidirectional radiation patterns of the triband antenna are observed in both H- and E-planes, respectively. In addition, a reasonable gain over the operating bands has been obtained. Indeed, the good agreements between simulation and measurement results have validated the proposed structure, confirming its potential for multiband wireless communication services.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-25T02:27:15Z
      DOI: 10.1142/S0218126620500322
       
  • Design of Robust Quantizers for Low-Bit Analog-to-Digital Converters for
           Gaussian Source
    • Authors: Milan R. Dinčić, Zoran H. Perić, Dragan B. Denić, Zoran Stamenković
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper considers the design of robust logarithmic [math]-law companding quantizers for the use in analog-to-digital converters (ADCs) in communication system receivers. The quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. Furthermore, linearization of the logarithmic [math]-law companding function is performed to simplify hardware implementation of the quantizers. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness — they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic [math]-law companding quantizers there is no need for using automatic gain control (AGC), which reduces the implementation complexity and increases the speed of the ADCs due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power. The proposed low-bit ADCs can be used in MIMO and 5G massive MIMO systems, where due to very high operating frequencies and a large number of receiving channels (and consequently a large number of ADCs), the reduction of ADC complexity and energy consumption becomes a significant goal.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-25T02:27:14Z
      DOI: 10.1142/S0218126619400024
       
  • Realization Approach for Sinusoidal Signal Generation and Circuit with
           Easy Control
    • Authors: S. Maheshwari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new approach for realizing sinusoidal signal with quadrature property is proposed, which employs simple analog building blocks and facilitates easy tuning of the oscillation frequency, through a gain factor. The proposed approach is used for realizing a novel quadrature oscillator circuit, which requires three current feedback operational amplifiers and passive components. The proposed circuit provides outputs at low impedance terminals, and benefits from easy control over the frequency of oscillation (FO), which depends on resistive ratio, rather than absolute resistor values. The frequency control is also independent of the condition of oscillation (CO). The nonideal effects and the parasitic studies are presented. The verification of the proposed realization scheme for quadrature oscillators and the new circuit is carried out through both simulation studies and experimental results, using the commercially available chips.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-25T02:27:13Z
      DOI: 10.1142/S0218126620500310
       
  • Modeling Analysis and Diagnosis of Analog Circuits in [math]-Domain
    • Authors: Michał Tadeusiewicz, Marek Ossowski
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The paper is dedicated to the linear time-invariant analog electronic circuits. It deals with the problem of modeling of the circuits in the [math]-domain. The model put forward in this paper enables solving different issues with the analysis of linear dynamic circuits. The model’s usefulness to fault diagnosis is emphasized in the paper, especially its application to multiple soft fault diagnosis of linear circuits. To make such diagnosis possible, the node equations with unknown node voltages and the diagnosed parameters are used. The set of actual values of the verified parameters is achieved by solving an appropriate system of algebraic nonlinear equations associated to the node equations. It can be determined using the Newton algorithm with adaptive choice of damping parameter. The diagnosis method is adjusted to real conditions by considering the deviations of the healthy parameters inside their tolerance scopes. Two real-life electronic circuits are considered to illustrate the method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:17Z
      DOI: 10.1142/S0218126620500280
       
  • Accurate Detection of ECG Signals in ECG Monitoring Systems by Eliminating
           the Motion Artifacts and Improving the Signal Quality Using SSG Filter
           with DBE
    • Authors: Mahesh B. Dembrani, K. B. Khanchandani, Anita Zurani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The automatic recognition of QRS complexes in an Electrocardiography (ECG) signal is a critical step in any programmed ECG signal investigation, particularly when the ECG signal taken from the pregnant women additionally contains the signal of the fetus and some motion artifact signals. Separation of ECG signals of mother and fetus and investigation of the cardiac disorders of the mother are demanding tasks, since only one single device is utilized and it gets a blend of different heart beats. In order to resolve such problems we propose a design of new reconfigurable Subtractive Savitzky–Golay (SSG) filter with Digital Processor Back-end (DBE) in this paper. The separation of signals is done using Independent Component Analysis (ICA) algorithm and then the motion artifacts are removed from the extracted mother’s signal. The combinational use of SSG filter and DBE enhances the signal quality and helps in detecting the QRS complex from the ECG signal particularly the R peak accurately. The experimental results of ECG signal analysis show the importance of our proposed method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:15Z
      DOI: 10.1142/S0218126620500243
       
  • Resource and Performance Tradeoff for Task Scheduling of Parallel
           Reconfigurable Architectures
    • Authors: Chi-Chou Kao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a resource/performance tradeoff algorithm for task scheduling of parallel reconfigurable architectures. First, it uses unlimited resources to generate an optimal scheduling algorithm. Then, a relaxation algorithm is applied to satisfy the number of resources under increasing minimum performance. To demonstrate the performance of the proposed algorithm, we not only compare the existing methods with standard benchmarks but also implement on physical systems. The experimental results show that the proposed algorithms satisfy the requirements of the systems with limited resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:12Z
      DOI: 10.1142/S0218126620500292
       
  • A Hardware–Software Co-Design Framework for Real-Time Video
           Stabilization
    • Authors: Hassan Javed, Muhammad Bilal, Shahid Masud
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Live digital video is a valuable source of information in security, broadcast and industrial quality control applications. Motion jitter due to camera and platform instability is a common artefact found in captured video which renders it less effective for subsequent computer vision tasks such as detection and tracking of objects, background modeling, mosaicking, etc. The process of algorithmically compensating for the motion jitter is hence a mandatory pre-processing step in many applications. This process, called video stabilization, requires estimation of global motion from consecutive video frames and is constrainted by additional challenges such as preservation of intentional motion and native frame resolution. The problem is exacerbated in the presence of local motion of foreground objects and requires robust compensation of the same. As such achieving real-time performance for this computationally intensive operation is a difficult task for embedded processors with limited computational and memory resources. In this work, development of an optimized hardware–software co-design framework for video stabilization has been investigated. Efficient video stabilization depends on the identification of key points in the frame which in turn requires dense feature calculation at the pixel level. This task has been identified to be most suitable for offloading the pipelined hardware implemented in the FPGA fabric due to the involvement of complex memory and computation operations. Subsequent tasks to be performed for the overall stabilization algorithm utilize these sparse key points and have been found to be efficiently handled in the software. The proposed Hardware–Software (HW–SW) co-design framework has been implemented on Zedboard FPGA platform which houses Xilinx Zynq SOC equipped with ARM A9 processor. The proposed implementation scheme can process real-time video stream input at 28 frames per second and is at least twice faster than the corresponding software-only approach. Two different hardware accelerator designs have been implemented using different high-level synthesis tools using rapid prototyping principle and consume less than 50% of logic resources available on the host FPGA while being at least 30% faster than contemporary designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:12Z
      DOI: 10.1142/S0218126620500279
       
  • Limited Effect of Noise Injection on Synchronization of Crystal
           Oscillators
    • Authors: Kazuyoshi Ishimura, Isao T. Tokuda
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Experimental study on noise-induced synchronization of crystal oscillators is presented. Two types of circuits were constructed: one consists of two Pierce oscillators that were isolated from each other and received a common noise input, while the other is based on a single Pierce oscillator that received a same sequence of noise signal repeatedly. Due to frequency detuning between the two Pierce oscillators, the first circuit showed no clear sign of noise-induced synchronization. The second circuit, on the other hand, generated coherent waveforms between different trials of the same noise injection. The waveform coherence was, however, broken immediately after the noise injection was terminated. Stronger perturbation such as the voltage resetting was finally shown to be effective to induce phase shifts, leading to phase synchronization of the Pierce oscillator. Our study presents a guideline for utilizing noise to synchronize clocks of multiple CPU systems, distributed sensor networks, and other engineering devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-18T01:42:29Z
      DOI: 10.1142/S0218126620500267
       
  • A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs
    • Authors: Xin Li, Cheng Huang, Desheng Ding, Jianhui Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-18T01:42:29Z
      DOI: 10.1142/S0218126620300020
       
  • Attribute-Based Collusion Resistance in Group-Based Cloud Data Sharing
           using LKH Model
    • Authors: N. Rajkumar, E. Kannan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Utilizing cloud computing, users can avail a compelling and effective approach for information sharing between collective individuals in the cloud with the facility of less administration cost and little maintenance. Security in cloud computing refers to procedures, standards and processes created to provide assurance for security of information in the cloud environment. In this paper, we project a secure data sharing method in cloud for dynamic members by producing keys for users using Logic Key Hierarchy (LKH) model, i.e., a tree-based key generation technique. We have generated this key using reverse hashing and one way hash-based technique so that no exiled user can predict the new key and new users cannot predict the old keys of the network group. From numerous experiments, this work is proved to be the best in maintaining forward secrecy, backward secrecy and group compromise attacks and consumes less computation cost compared to any other hash-based key generation techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-12T03:06:24Z
      DOI: 10.1142/S0218126620300019
       
  • A High Precision Output Impedance Calibration Technique for SST
           Transmitter
    • Authors: Xu Bai, Jianzhong Zhao, Yumei Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a high precision output impedance calibration technique for source-series terminated (SST) transmitter. Unlike the conventional impedance calibration technique using a digital method, the proposed impedance calibration employs the analog method to implement the impedance calibration. Therefore, there is no trade-off between area overhead and precision of calibration. The proposed analog impedance calibration circuit has three analog impedance control loops, namely, pull-up loop, pull-down loop and shunt-loop. Each loop is composed of a high gain amplifier and a slice-based unit. To reduce the hardware, the shunt loop utilized a slice unit replication design to achieve the shunt-slice calibration. These loops send output voltage to the SST transmitter when they reached stability. Fabricated in 55[math]nm CMOS technology, the power consumption of the calibration circuit is 1.35[math]mW and the total area is 61[math][math]m*83.1[math][math]m, which consumes 6.3% of the total power consumed by the transmitter and occupies 25% of the total area occupied by the complete transmitter. The post-layout simulation result shows that the maximum impedance calibration error of the three loops is less than 0.02%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-11T08:17:37Z
      DOI: 10.1142/S0218126620500255
       
  • Normally Bypassed Cascaded Sources Multilevel Inverter with RGA
           Optimization for Reduced Output Distortion and Formulaic Passive Filter
           Design
    • Authors: G. Chitrakala, N. Stalin, V. Mohan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-11T08:17:37Z
      DOI: 10.1142/S021812662050019X
       
  • Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic
           Structures
    • Authors: B. P. Bhuvana, V. S. Kanchana Bhaaskaran
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the adiabatic logic called 2[math]–[math]–2[math], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[math]–[math]–2[math] adiabatic logic is capable of operating through a wide range of frequency from 100[math]MHz to 1[math]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[math]–[math]–2[math] against the [math] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[math]–[math]–2[math] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[math]–[math]2[math] over [math] and PFAL designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:54Z
      DOI: 10.1142/S0218126620500164
       
  • A Multiband, Spectrally-Efficient Impulse Radio Transmitter Design with
           Low-Complexity CMOS Pulse Generator for IEEE 802.15.4a Application
    • Authors: Hanen Saoudi, Hamadi Ghariani, Mongi Lahiani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel multiband impulse radio ultra-wideband (MB-IR-UWB) transmitter with an energy-efficient and low-complexity pulse generator design technique compliant with the IEEE 802.15.4a standard is investigated in this paper. This transmitter is made up of a new differential narrow triangular pulse generator, a new multiband voltage-controlled oscillator (VCO), an active mixer and a variable-gain power amplifier (PA). It operates at 14 UWB bands and generates an output signal with the duration of 3[math]ns, more than 500[math]MHz of channel bandwidth and more than 20[math]dB of sidelobe suppression, while achieving an average energy efficiency of 51.36 pJ/pulse from 1.4-V supply. Improving spectral flexibility and worldwide compliance is the major contribution brought by this paper to make this circuit as a multifunction wireless device well suited for low-cost, low-power multiband applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:54Z
      DOI: 10.1142/S0218126620500206
       
  • Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications
    • Authors: Imen GHORBEL, Fayrouz Haddad, Wenceslas Rahajandraibe, Mourad Loulou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[math][math]m CMOS process. Measurements present an ultra-low power consumption of only 262[math][math]W drawn from 1[math]V supply voltage. The measured frequency tuning range is about 10% between 2.179[math]GHz and 2.409[math]GHz. The post-layout simulation presents a phase noise (PN) of [math][math]dBc/Hz, while the measured PN is [math][math]dBc/Hz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:53Z
      DOI: 10.1142/S0218126619501226
       
  • Operation, Control and Verification of Seven-Level Quasi-Z-Source-Based
           [math]-Type Inverter
    • Authors: Ramesh Rahul Jammy, Kirubakaran Annamalai, Chinmay Kumar Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel seven-level Quasi-Z-Source-based [math]-type inverter (7L[math]qZST[math]) is proposed. The proposed inverter is an upgrade of Quasi-Z-source (qZs) network and seven-level [math]-type inverter. The 7L qZST[math] comprises of three qZs-based impedance networks, two bidirectional switches and an [math]-bridge inverter. It owns the advantages of reduced switch count, improved output voltage gain, enhanced reliability and better quality of output voltage and current. The performance of the proposed topology is tested for two different pulse width modulation techniques based on shoot-through control. The first technique offers simple control and operated at a fixed shoot-through duty cycle for realizing output voltage level. The second technique facilitates independent control of each qZs network dc-link voltage and they can be operated at different shoot through duty cycle which overcomes the limitation of first technique with better quality in output voltage. The detailed operation of the proposed topology and control schemes have been elaborated for different switching states for each output voltage level generation. Extensive simulation and experimentation are performed for both the switching schemes to verify their performance under steady state and dynamic conditions. Furthermore, a brief comparison is constructed to highlight the merits of the proposed inverter with conventional topologies.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:52Z
      DOI: 10.1142/S0218126620500231
       
  • A Novel Salp Swarm Optimization MPP Tracking Algorithm for the Solar
           Photovoltaic Systems under Partial Shading Conditions
    • Authors: S. Krishnan, K. Sathiyasekar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To extract the maximum solar power from the photovoltaic (PV) panel/array with the high conversion efficiency under partial shading condition (PSC), this paper discusses a new and an efficient maximum power point (MPP) tracking algorithm. The proposed algorithm is based on the bio-inspired salp swarm optimization (SSO), and the algorithm forecasts the global MPP (GMPP) with the fast convergence to GMPP and high tracking efficiency. The SSO algorithm thus reduces the computational burden as encountered in whale optimization algorithm (WOA), and gray wolf optimization (GWO) algorithm discussed in the various literatures. The modeling and simulation of the proposed SSO algorithm are done with the help of Matlab/Simulink software to validate the effectiveness to locate the MPP during PSCs. The simulation results prove that the proposed SSO algorithm exhibits a high PV power output with the tracking efficiency of more than 95% at the faster convergence rate to GMPP. The SSO algorithm is experimentally verified on the conventional boost converter under different shading conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:51Z
      DOI: 10.1142/S0218126620500176
       
  • Evolved Fuzzy NN Control for Discrete-Time Nonlinear Systems
    • Authors: Tim Chen, A. Babanin, Assim Muhammad, B. Chapron, C. Y. J. Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To guarantee the asymptotic stability of discrete-time nonlinear systems, this paper proposes an Evolved Bat Algorithm (EBA) fuzzy neural network (NN) controller. In the evolved fuzzy NN modeling, an NN model and linear differential inclusion (LDI) representation are established for arbitrary nonlinear dynamics. This representation is constructed by the use of sector nonlinearity to convert a nonlinear model to the multiple rule base of the linear model, and a new sufficiency condition to guarantee asymptotic stability in the Lyapunov function is implemented in terms of linear matrix inequalities. The proposed method is an enhancement of existing methods which produces good results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:48Z
      DOI: 10.1142/S0218126620500152
       
  • A Low-Power Clock Generator with a Wide Frequency Tuning Range and Low
           Temperature Variation: Analysis and Design
    • Authors: Ziba Fazel, MaryamSadat Shokrekhodaei, Mojtaba Atarodi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180[math]nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about [math][math]dBc/Hz at 10[math]MHz offset frequency. Frequency changes less than [math] in the temperature range of [math]C–[math]C. The clock generator consumes 0.657[math]mW of power. Results show improvement in comparison to the previous works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:49Z
      DOI: 10.1142/S0218126620500127
       
  • Distributed Coordinated Attitude Regulation Control for Multiple
           Spacecraft with Time-varying Uncertainties
    • Authors: Zhihao Zhu, Yu Guo, Zhi Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      For multiple spacecrafts under the communication topology containing a spanning tree with the leader as the root, we investigate a distributed coordinated attitude regulation control problem of the spacecraft with unknown time-varying uncertainties and state-dependent disturbances. Aiming at solving the practical problem that the information of the leader may be only available to a subset of the followers, a novel class of distributed finite-time leaders’ state observer for each follower is proposed. Meanwhile, a new self-adjustment matrix is designed to reduce the overshoot of the system. In addition, an adaptive compensation term is designed to reject the impact of the time-varying inertia uncertainties and external state-dependent and state-independent disturbances. On the basis of the distributed finite-time observer, the self-adjustment matrix and the adaptive law, two distributed coordinated attitude regulation control laws are designed. With the first controller, the coordinated attitude regulation system is stable asymptotically, and with the second controller, the system is bounded stable. Both distributed coordinated attitude regulation controllers can guarantee that the follower spacecraft can track a common time-varying trajectory of the leader. Numerical simulation examples validate the effectiveness of the proposed controllers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:46Z
      DOI: 10.1142/S0218126620500188
       
  • A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR
           Filter Implementation Using Hardware–Software Co-Design
    • Authors: C. Ranjith, S. P. Joy Vasantha Rani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:44Z
      DOI: 10.1142/S0218126620500140
       
  • Prediction of Pareto Dominance Using an Attribute Tendency Model for
           Expensive Multi-Objective Optimization
    • Authors: Wenbin li, Junqiang Jiang, Xi Chen, Guanqi Guo, Jianjun He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a novel surrogate-assisted multi-objective evolutionary algorithm, MOEA-ATCM, to solve expensive or black-box multi-objective problems with small evaluation budgets. The proposed approach encompasses a state-of-the-art MOEA based on a nondominated sorting genetic algorithm assisted by multi-fidelity optimization methods. A high-fidelity attribute tendency (AT) surrogate model was used to construct a linear decision space by introducing the knowledge of the objective space. A coarse model (CM) based on the AT model and correlation analyses of the objective functions and decision attributes were used to predict the Pareto dominance for candidates in the new decision space constructed by the AT model. Two major roles of MOEA-ATCM were identified: (1) the development of a new multi-fidelity surrogate-model-based method to predict Pareto dominance in a decision space that was then applied to MOEA, which does not need to dynamically update surrogate models in the optimization process and (2) the development of a Pareto dominance prediction method to obtain good nondominated solutions of expensive or black box problems with relatively few objective function evaluations. The advantages of MOEA-ATCM were verified by mathematical benchmark problems and a real-world multi-objective parameter optimization problem.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:36Z
      DOI: 10.1142/S0218126620500218
       
  • Object Detection Using Multiview CCA-Based Graph Spectral Learning
    • Authors: Peng Guo, Guoqi Xie, Renfa Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent years have witnessed a surge of interest in semi-supervised learning-based object detection. Object detection is usually accomplished by classification methods. Different from conventional methods, those usually adopt a single feature view or concatenate multiple features into a long feature vector, multiview graph spectral learning can attain simultaneously object classification and weight learning of multiview. However, most existing multiview graph spectral learning (GSL) methods are only concerned with the complementarities between multiple views but not with correlation information. Accurately representing image objects is difficult because there are multiple views simultaneously for an image object. Thus, we offer a GSL method based on multiview canonical correlation analysis (GSL-MCCA). The method adds MCCA regularization term to a graph learning framework. To enable MCCA to reveal the nonlinear correlation information hidden in multiview data, manifold local structure information is incorporated into MCCA. Thus, GSL-MCCA can lead to simultaneous selection of relevant features and learning transformation. Experimental evaluations based on Corel and VOC datasets suggest the effectiveness of GSL-MCCA in object detection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:34Z
      DOI: 10.1142/S021812662050022X
       
  • Research on the Linear Acceleration Sensor Signal Acquisition Technology
           Based on the High-Order Anti-Aliasing Cauer Filter
    • Authors: Zhuo Hou, Sanmin Shen, Yong Ye, Jiahao Deng, Yuting Liu, Qing Meng, Zuodong Duan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A linear acceleration sensor integrated into an inertial measurement unit and its signal processing technology are presented in this paper. Based on the characteristics of the acceleration sensor, before analog-to-digital conversion, a design method for optimizing and conditioning the output signal in levels of frequency with the high-order anti-aliasing Cauer filter is proposed. Compared with the previously published papers, here we not only focus on the anti-aliasing filtering effect under a single channel, but also pay more attention to the anti-aliasing filtering effect with more data to the same type of channels with the same cut-off frequency and different types of channels with different cut-off frequencies. Similar to other kinds of filters, this paper points out that the high-order anti-aliasing Cauer filter also has its inherent delay characteristic. And this paper also reveals the qualitative relationship between frequency and time delay in different testing environments by using various delay test data. Compared with the previously published papers, through the simple solution processing with the true attitude data, this paper further estimates the error of simple attitude signal processing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-26T02:58:31Z
      DOI: 10.1142/S0218126620500085
       
  • Divide and Compact — Stochastic Space Compaction for
           Faster-than-at-Speed Test
    • Authors: Alexander Sprenger, Sybille Hellebrand
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([math]-values). These [math]-values impede the test response compaction. In addition, the number and distribution of the [math]-values vary with the clock frequency, and thus a very flexible [math]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [math]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [math]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [math]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [math]-reduction and fault efficiency can be adapted to user-defined goals.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-18T03:38:53Z
      DOI: 10.1142/S0218126619400012
       
  • Analysis, Control and FPGA Implementation of a Fractional-Order Modified
           Shinriki Circuit
    • Authors: Karthikeyan Rajagopal, Fahimeh Nazarimehr, Laarem Guessas, Anitha Karthikeyan, Ashokkumar Srinivasan, Sajad Jafari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we introduce a novel integer-order memristor-modified Shinriki circuit (MMSC). We investigate the dynamic properties of the MMSC system and the existence of chaos is proved with positive largest Lyapunov exponent. Bifurcation plots are derived to analyze the parameter dependence of the MMSC system. The fractional-order model of the MMSC system (FOMMSC) is derived and the bifurcation analysis of the FOMMSC system with the fractional orders is carried out. Fractional-order adaptive sliding-mode controllers (FOASMCs) and genetically optimized PID controllers are designed to synchronize identical FOMMSC systems with unknown parameters. Numerical simulations are conducted to validate the theoretical results. FPGA implementation of the FOASMC controllers is presented to show that the proposed control algorithm is hardware realizable. MMSC has trigonometric functions which make the system more complex and the optimization and synchronization of such systems in the integer order itself are harder, so the paper does the same in fractional order. The proposed system is a memristive circuit which can show special features such as multistability, hyperchaos, and multiscroll attractor. Such a system with these features is very rare in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-15T01:31:23Z
      DOI: 10.1142/S0218126619502323
       
  • A Physics-Based Analytical Model for MgZnO/ZnO HEMT
    • Authors: Yogesh Kumar Verma, Varun Mishra, Santosh Kumar Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a physics-based compact model is developed for novel MgZnO/ZnO high-electron-mobility transistor (HEMT). Poisson’s equation coupled with 1D Schrödinger equation is solved self-consistently in the triangular quantum well to derive an expression of two-dimensional electron gas (2DEG) density with respect to gate voltage at the heterointerface of barrier (MgZnO) and buffer (ZnO) layers. A compact mathematical framework has been devised further for the first time for ZnO-based HEMT to the best of our knowledge using the expression of 2DEG density to compute surface potential, gate charge, gate current, gate capacitance, current–voltage characteristics, output conductance, transconductance and cut-off frequency with respect to gate voltage and along with the drain–source output resistance [math].
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-15T01:31:22Z
      DOI: 10.1142/S0218126620500097
       
  • Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC
           Converter for Implantable Devices
    • Authors: Najmeh Cheraghi Shirazi, Abumoslem Jannesari, Pooya Torkzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[math]mV and 20[math]MHz clock frequency for 1[math]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[math]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[math][math]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[math]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [math][math][math]m for TBCCCP, [math][math][math]m for ITBCCCP2 and [math][math][math]m for ITBCCCP4.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-13T06:31:07Z
      DOI: 10.1142/S0218126620500139
       
  • Analysis, Design and Control of an Integrated Three-Level Buck Converter
           under DCM Operation
    • Authors: Wen-Ming Zheng, Wen-Liang Zeng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A three-level buck (TLB) converter has the characteristics of higher voltage conversion efficiency, lower inductor current ripples, output voltage ripples and voltage stresses on switches when compared with the buck converters in continuous conduction mode (CCM). With a TLB converter integrated on a chip, we cannot avoid its discontinuous conduction mode (DCM) operation due to a smaller inductance and load variation. In this paper, we’ll present and discuss the analysis, design and control of a TLB converter under DCM operation, implemented in a 65[math]nm CMOS process. Transistor level simulation results show that when the TLB converter operates at 100[math]MHz with a 5[math]nH on-chip inductor, a 10[math]nF output capacitor and a 10[math]nF flying capacitor, it can achieve an output conversion range of 0.7–1.2[math]V from a 2.4[math]V input supply, with a peak efficiency of 81.5%@120[math]mW. The output load transient response is 100[math]mV with 101[math]ns for undershoot, and 86[math]mV with 110[math]ns for overshoot when [math]–100[math]mA. The maximum output voltage ripple is less than 19[math]mV.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-13T06:31:06Z
      DOI: 10.1142/S0218126620500115
       
  • Deep Convolutional Neural Network with Optical Flow for Facial
           Micro-Expression Recognition
    • Authors: Qiuyu Li, Jun Yu, Toru Kurihara, Haiyan Zhang, Shu Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Micro-expression is a kind of brief facial movements which could not be controlled by the nervous system. Micro-expression indicates that a person is hiding his true emotion consciously. Micro-expression recognition has various potential applications in public security and clinical medicine. Researches are focused on the automatic micro-expression recognition, because it is hard to recognize the micro-expression by people themselves. This research proposed a novel algorithm for automatic micro-expression recognition which combined a deep multi-task convolutional network for detecting the facial landmarks and a fused deep convolutional network for estimating the optical flow features of the micro-expression. First, the deep multi-task convolutional network is employed to detect facial landmarks with the manifold-related tasks for dividing the facial region. Furthermore, a fused convolutional network is applied for extracting the optical flow features from the facial regions which contain the muscle changes when the micro-expression appears. Because each video clip has many frames, the original optical flow features of the whole video clip will have high number of dimensions and redundant information. This research revises the optical flow features for reducing the redundant dimensions. Finally, a revised optical flow feature is applied for refining the information of the features and a support vector machine classifier is adopted for recognizing the micro-expression. The main contribution of work is combining the deep multi-task learning neural network and the fusion optical flow network for micro-expression recognition and revising the optical flow features for reducing the redundant dimensions. The results of experiments on two spontaneous micro-expression databases prove that our method achieved competitive performance in micro-expression recognition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:22Z
      DOI: 10.1142/S0218126620500061
       
  • Third-Kind Chebyshev Wavelet Method for the Solution of Fractional Order
           Riccati Differential Equations
    • Authors: Sadiye Nergis Tural-Polat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we derive the numerical solutions of the various fractional-order Riccati type differential equations using the third-kind Chebyshev wavelet operational matrix of fractional order integration (C3WOMFI) method. The operational matrix of fractional order integration method converts the fractional differential equations to a system of algebraic equations. The third-kind Chebyshev wavelet method provides sparse coefficient matrices, therefore the computational load involved for this method is not as severe and also the resulting method is faster. The numerical solutions agree with the exact solutions for non-fractional orders, and also the solutions for the fractional orders approach those of the integer orders as the fractional order coefficient [math] approaches to 1.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:21Z
      DOI: 10.1142/S0218126619502475
       
  • A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic
           Asynchronous Pipeline Design
    • Authors: Mansi Jhamb, Vinod Kumar Khera, Piyush Pant, Hinduja Pudi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:21Z
      DOI: 10.1142/S0218126619502347
       
  • An Efficient Load Forecasting in Predictive Control Strategy Using Hybrid
           Neural Network
    • Authors: Shweta Sengar, Xiaodong Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Load forecasting is a difficult task, because the load series is complex and exhibits several levels of seasonality. The load at a given hour is dependent not only on the load at the previous day, but also on the load at the same hour on the previous day and previous week, and because there are many important exogenous variables that must be considered. Most of the researches were simultaneously concentrated on the number of input variables to be considered for the load forecasting problem. In this paper, we concentrate on optimizing the load demand using forecasting of the weather conditions, water consumption, and electrical load. Here, the neural network (NN) power load forecasting model clubbed with Levy-flight from cuckoo search algorithm is proposed, i.e., called hybrid neural network (HNN), and named as LF-HNN, where the Levy-flight is used to automatically select the appropriate spread parameter value for the NN power load forecasting model. The results from the simulation work have demonstrated the value of the LF-HNN approach successfully selected the appropriate operating mode to achieve optimization of the overall energy efficiency of the system using all available energy resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:20Z
      DOI: 10.1142/S0218126620500103
       
  • A 21-Level Bipolar Single-Phase Modular Multilevel Inverter
    • Authors: Sidharth Sabyasachi, Vijay B. Borghate, Santosh Kumar Maddugari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a module for single-phase multilevel inverter topology. The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge. This results in reduction in filter cost and size. The module can be cascaded for high voltage applications. The same arrangement of voltage source magnitudes in first module is maintained in the remaining cascaded modules. The proposed topology is suitable for the applications like electric vehicle and emergency services like residences and hospitality industries, etc. A set of comparisons between the proposed and recently published topologies are provided to differentiate between them. The topology is simulated and verified in MATLAB/SIMULINK. A hardware prototype is developed in the laboratory for experimental confirmation with various conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:20Z
      DOI: 10.1142/S0218126620500048
       
  • New Hardware Architecture for Self-Organizing Map Used for Color Vector
           Quantization
    • Authors: Khaled Ben Khalifa, Ahmed Ghazi Blaiech, Mehdi Abadi, Mohamed Hedi Bedoui
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [math] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:19Z
      DOI: 10.1142/S0218126620500024
       
  • An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future
           3D Chip-Multiprocessors
    • Authors: Arghavan Asad, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy, Farah Mohammadi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:19Z
      DOI: 10.1142/S0218126619502244
       
  • Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate
           the Reconfiguration Overheads in Reconfigurable Systems
    • Authors: I. Hariharan, M. Kannan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:18Z
      DOI: 10.1142/S0218126619502463
       
  • A Lion’s Pride Inspired Algorithm for VLSI Floorplanning
    • Authors: Lalin L Laudis, N Ramadass
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:17Z
      DOI: 10.1142/S0218126620500036
       
  • A Memetic Algorithm-Based Design Space Exploration for Datapath Resource
           Allocation During High-Level Synthesis
    • Authors: Shathanaa Rajmohan, N. Ramasubramanian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      System designers have started adopting high-level synthesis (HLS) for architectural design because of the higher levels of abstraction offered. The HLS tools provide multiple design choices with tradeoff among different design parameters. Design Space Exploration (DSE) involves optimizing the synthesis options to achieve best tradeoffs among the metrics of interest. With the aim of exploring the design space in a feasible amount of time, we present a novel automated DSE approach. In particular, meeting the constraints presented by different parameters of interest is modeled as a multi-objective problem and solved using Memetic algorithm. The effectiveness of different variations of the Memetic algorithm in solving the DSE problem is studied and a Firefly algorithm-based solution is proposed with a novel probabilistic local search mechanism. The proposed approach is compared with existing solutions and the results prove that the proposed approach outperforms both existing solutions and other variations of Memetic algorithms in terms of convergence time and quality of results. In addition to that, a case study has been included to demonstrate the applicability of the approach. Results show that the proposed approach achieves a 33% improvement in cost, [math] improvement in speed and [math] improvement in hypervolume.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:17Z
      DOI: 10.1142/S0218126620500012
       
  • A New CPFSK Demodulation Approach for Software Defined Radio
    • Authors: Kayol Soares Mayer, Candice Müller, Fernando Cesar Comparsi de Castro, Maria Cristina Felippetto de Castro
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [math], which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes [math], [math] and [math], respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T07:33:56Z
      DOI: 10.1142/S0218126619502438
       
  • RDMKE: Applying Reuse Distance Analysis to Multiple GPU Kernel Executions
    • Authors: Mohsen Kiani, Amir Rajabzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern GPUs can execute multiple kernels concurrently to keep the hardware resources busy and to boost the overall performance. This approach is called simultaneous multiple kernel execution (MKE). MKE is a promising approach for improving GPU hardware utilization. Although modern GPUs allow MKE, the effects of different MKE scenarios have not adequately studied by the researchers. Since cache memories have significant effects on the overall GPU performance, the effects of MKE on cache performance should be investigated properly. The present study proposes a framework, called RDMKE (short for Reuse Distance-based profiling in MKEs), to provide a method for analyzing GPU cache memory performance in MKE scenarios. The raw memory access information of a kernel is first extracted and then RDMKE enforces a proper ordering to the memory accesses so that it represents a given MKE scenario. Afterward, RDMKE employs reuse distance analysis (RDA) to generate cache-related performance metrics, including hit ratios, transaction counts, cache sets and Miss Status Holding Register reservation fails. In addition, RDMKE provides the user with the RD profiles as a useful locality metric. The simulation results of single kernel executions show a fair correlation between the generated results by RDMKE and GPU performance counters. Further, the simulation results of 28 two-kernel executions indicate that RDMKE can properly capture the nonlinear cache behaviors in MKE scenarios.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-31T08:20:39Z
      DOI: 10.1142/S0218126619502451
       
  • Determination of Worst-Case Data Using an Adaptive Surrogate Model for
           Real-Time System
    • Authors: Muhammad Rashid, Syed Abdul Baqi Shah, Muhammad Arif, Muhammad Kashif
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The estimation of worst-case execution time (WCET) is a critical activity in the analysis of real-time systems. Evolutionary algorithms are frequently employed for the determination of worst-case data, used in the estimation of WCET. However, in order to employ an evolutionary algorithm, several executions of the application program are required, either on the target hardware or using its simulator. Multiple executions of the application program consume a huge amount of time. In order to reduce the huge execution time, this paper proposes the use of an adaptive surrogate model. The initial training of surrogate model is performed with a cycle-accurate simulator. The initially trained model is then used to assist the evolutionary algorithm by predicting the execution time of an application program. However, contrary to the direct training approach, the surrogate model in this paper is updated (adapted) during the evolution process. The adaptive training of a surrogate model increases its prediction accuracy and reduces the overall time. The validity of proposed methodology is illustrated with multiple sorting algorithms, extensively used in real-time systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:28Z
      DOI: 10.1142/S021812662050005X
       
  • 2.4 GHz Real-Time Prototyping Tool for OFDM Channel Estimation using USRP2
           and LabVIEW
    • Authors: Kerem Küçük
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless local area networks (WLANs) are currently playing an important role in serving the indoor traffic demand. Therefore, there is a need for software-defined radio platforms (SDRs) that can enable the solutions used in these systems to be tested in real environments as well as simulated results. In this paper, we present the SDR-based wireless receiver platform for determining the real-time WLANs performance and provide the comparison of the different channel estimation methods for IEEE 802.11g based on orthogonal frequency division multiplexing (OFDM) operations. The implementation of the receiver comprises the universal software radio peripheral and National Instruments LabVIEW. To determine the real-time receiver tool performance, we emphasized necessary signal processing techniques and different channel estimation methods with varying experimental parameters in real wireless environments. Experimental results report that the SDR-based receiver tool with the LabVIEW in real-time provides the throughput of the OFDM wireless network. The captured throughput performance concerning frame error rate by the receiver is also scrutinized with different channel estimation methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:26Z
      DOI: 10.1142/S0218126619502360
       
  • An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant
           Arithmetic
    • Authors: Ahmad Towhidy, Reza omidi, Karim Mohammadi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:21Z
      DOI: 10.1142/S021812661950244X
       
  • Analysis and FPGA Implementation of Zero-Forcing Receive Beamforming with
           Signal Space Diversity under Different Interleaving Techniques
    • Authors: Mustafa Anıl Reşat, Adem Çiçek, Serdar Özyurt, Enver Çavuş
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We combine multiple-input multiple-output zero-forcing receive beamforming (ZFRBF) with time and spatial component interleaved signal space diversity (SSD) and analyze the system’s error performance and implementation complexity. A transreceiver system with two transmit and [math] ([math]) receive antennas is considered where the number of simultaneous substreams equals two. The error performance of the proposed scheme with binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) modulations is studied. Under the time component interleaved SSD case, we derive an exact average bit error probability expression for BPSK and a tight approximation on the average symbol error probability for QPSK. The signal constellation rotation angles are accordingly computed. Using a similar approach, the signal constellation rotation angles are also determined for the scenario of spatial component interleaved SSD. It is demonstrated that the performance of the original ZFRBF model can be improved significantly by utilizing SSD especially with the time interleaving method. Another contribution to the literature is to study hardware complexity of the proposed scheme on FPGA. It is shown that while achieving considerable performance gain, SSD introduces only an insignificant increase to the system complexity without any extra bandwidth or time slot usage.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:20Z
      DOI: 10.1142/S0218126620500073
       
  • A Miniaturized High-Gain (MHG) Ultra-Wideband Unidirectional Monopole
           Antenna for UWB Applications
    • Authors: J. Vijayalakshmi, G. Murugesan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A miniaturized high-gain (MHG) ultra-wideband (UWB) unidirectional monopole antenna with defected ground structure (DGS) is designed for ultra-wideband applications. The MHG antenna is printed on the FR4 substrate material with an overall size of 26.6-mm [math] 29.3-mm [math] 1.6-mm, which operates over the UWB frequency range and achieves the bandwidth between 3.1[math]GHz and 10.6[math]GHz. This high-gain unidirectional antenna exhibits a peak gain of 7.20[math]dB with an efficiency of 95%. The compact antenna is a simple overlay design of circular and rectangular patches with the partial ground plane exhibiting high gain and better directivity. The overlay patch antenna acts as the radiator for wider bandwidth compared to the fundamental design of patch antenna and is matched to an SMA connector via 50[math][math] microstrip feed line. These simulated results are presented using HFSS software package. The designed antennas are fabricated and validated by using Agilent Vector Analyzer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-29T09:21:53Z
      DOI: 10.1142/S021812661950230X
       
  • Chaotic Oscillator Based on Fractional Order Memcapacitor
    • Authors: Akif Akgul
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Many literatures have discussed fractional order memristor and memcapacitor-based chaotic oscillators but the entire oscillator model is considered to be of fractional order. My interest is to propose a nonlinear oscillator with considering only the memcapacitor element of fractional order. Hence, I propose a fractional order memcapacitor (FMC)-based novel chaotic oscillator. The complete mathematical model for the proposed oscillator is derived and presented in this paper. The dimensionless state equations are then analyzed by using the equilibrium points and their stability, Eigen values, Kaplan–Yorke dimensions and Lyapunov exponents. To understand the complete dynamical behavior, bifurcation graphs are obtained and presented. Finally, the proposed fractional memcapacitor oscillator is implemented by using the shelf components.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:42Z
      DOI: 10.1142/S0218126619502396
       
  • AFBV: A High-Performance Network Flow Classification Method for
           Multi-Dimensional Fields and FPGA Implementation
    • Authors: Ling Zheng, Zhiliang Qiu, Weina Wang, Weitao Pan, Shiyong Sun, Ya Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[math]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:40Z
      DOI: 10.1142/S0218126619502372
       
  • Automatic Test Pattern Generation Through Boolean Satisfiability for
           Testing Bridging Faults
    • Authors: Hossein Mokhtarnia, Shahram Etemadi Borujeni, Mohammad Saeed Ehsani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:39Z
      DOI: 10.1142/S0218126619502402
       
  • Study and Design of Single and Double Layer Square Patch Antennas for UWB
           Applications
    • Authors: Soufian Lakrit, Hassan Ammor, Soufiane Matah, Jaouad Terhzaz, Abdelouahd Tribak
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the design of Single and Double Layer microstrip patch antennas for ultra-wideband applications. This structure consists of a square patch with a partial ground plane, fed by a 50[math][math] microstrip line. This antenna is designed for a system to detect malignant tumors by microwave imaging. Prototypes of the two antennas are fabricated and tested with a network analyzer. The proposed antenna can achieve an ultra-wide bandwidth with VSWR[math]2 from 3.82[math]GHz to 11.72[math]GHz for single layer antenna and from 3.2[math]GHz to 10.95[math]GHz for double layer antenna, with stable and bi-directional radiation pattern. The gain is good and has a peak value of 6.5[math]dBi. The simulation of this antenna has been performed using Ansoft High Frequency Structure Simulator (HFSS) and Computer Simulation Technology-Microwave Studio (CST).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:38Z
      DOI: 10.1142/S0218126619502335
       
  • Distributed Amplifier Based on Monolayer Graphene Field Effect Transistor
    • Authors: Ali Safari, Massoud Dousti, Mohammad Bagher Tavakoli
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the ultra-high carrier mobility and ultralow resistivity of Graphene channel, a Graphene field effect transistor (GFET) is an interesting candidate for future RF and microwave electronics. In this paper, the introduction and review of existing compact circuit-level model of GFETs are presented. A compact GFET model based on drift-diffusion transport theory is then implemented in Verilog-A for RF/microwave circuit analysis. Finally, the GFET model is used to design a GFET-based distributed amplifier (DA) using advanced design system (ADS) tools. The simulation results demonstrate a gain of 8[math]dB, an input/output return loss less than [math]10[math]dB, [math]3[math]dB bandwidth from DC up to 5[math]GHz and a dissipation of about 60.45[math]mW for a 1.5[math]V power supply. The main performance characteristics of the distributed amplifier are compared with 0.18[math][math]m CMOS technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:04Z
      DOI: 10.1142/S0218126619502311
       
  • Compact, Programmable, Two-Stage Configuration for Implantable
           Biopotential Recording Amplifiers
    • Authors: Mohammad Hossein Maghami, Amir Masoud Sodagar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper [math]3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-[math]m technology, and consumes 0.022[math]mm2 and 0.27[math]mm2 of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8[math]V, power consumption of the proposed amplifier is 36.7[math][math]W with the simulated input-referred noise of 4[math][math] over 1[math]Hz–10[math]kHz for each channel. The amplifier also provides an output swing of 0.95 Vpp with a total harmonic distortion of [math]50[math]dB at the frequency of 1[math]kHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:03Z
      DOI: 10.1142/S0218126619200093
       
  • Efficient PSoC Implementation of Modular Multiplication and Exponentiation
           Based on Serial-Parallel Combination
    • Authors: M. Issad, B. Boudraa, M. Anane, A. M. Bellemou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than the input data length. The design must be scalable to support different security levels. The implementation achieves optimums execution time and HW resources number. In order to satisfy these constraints, Montgomery Power Ladder (MPL) and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution times. The application for 1024-bits data length shows that the MMM run in 6.24[math][math]s and requires 647 slices. The ME is executed in 6.75[math]ms using 2881 slices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:01Z
      DOI: 10.1142/S0218126619502293
       
  • Wide Tuning Range Varactorless Tunable Active Inductor-Based Voltage
           Controlled Oscillator for Wireless Applications
    • Authors: Omar Faruqe, Md Tawfiq Amin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90[math]nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46[math]GHz for the tuning voltage of 0.3–1.5[math]V. It consumes a low dc power ranging from 2.44[math]mW to 4.79[math]mW for the specified tuning range. The variation of phase noise ranges from [math][math]dBc/Hz to [math][math]dBc/Hz at 1[math]MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of [math][math]dBc/Hz with a differential output power of 1.8[math]dBm at tuning voltage of 0.7[math]V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:01Z
      DOI: 10.1142/S0218126619502426
       
  • Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection
    • Authors: Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High data rates and error-rate performance approaching close to theoretical limits are key trends for evolving digital wireless communication applications. To address the first requirement, multiple-input multiple-output (MIMO) techniques are adopted in emergent wireless communication standards and applications. On the other hand, turbo concept is used to alleviate the destructive effects of the channel and ensure error-rate performance close to theoretical limits. At the receiver side, the incorporation of MIMO techniques and turbo processing leads to increased complexity that has a severe impact on computation speed, power consumption and implementation area. Because of its increased complexity, the detector is considered critical among all receiver components. Low-complexity algorithms are developed at the cost of decreased performance. Minimum mean-squared error (MMSE) solution with iterative detection and decoding shows an acceptable tradeoff. In this paper, the complexity of the MMSE algorithm in turbo detection context is investigated thoroughly. Algorithmic computations are surveyed to extract the characteristics of all involved parameters. Consequently, several decompositions are applied leading to enhanced performance and to a significant reduction of utilized computations. The complexity of the algorithm is evaluated in terms of real-valued operations. The proposed decompositions save an average of [math] and [math] of required operations for 2 [math] 2 and 4 [math] 4 MIMO systems, respectively. In addition, the hardware implementation designed applying the devised simplifications and decompositions outperforms available state-of-the-art implementations in terms of maximum operating frequency, execution time, and performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:00Z
      DOI: 10.1142/S0218126619502281
       
  • A Transformation Methodology of Normal Nonlinear Resistors/Conductors to
           Inverses
    • Authors: C. Sánchez-López, V. H. Carbajal-Gómez, M. A. Carrasco-Aguilar, F. E. Morales-López
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work proposes a simple transformation methodology of normal nonlinear resistors/conductors to their inverted topologies in their floating and grounded versions (NNR/C). It is demonstrated that inverted topologies can also be configured as incremental or decremental nonlinear resistors/conductors. The main fingerprints of an NNR/C are holding up after the transformation and it is demonstrated that an inverse nonlinear resistor/conductor becomes a linear resistor/conductor when the operating frequency of the signal source decreases, inverse behavior in comparison with one memristor. Illustrative examples are given for floating and grounded nonlinear resistors and in both configurations. HSPICE simulation results are provided confirming the theory. Moreover, the normal and inverses resistors can be reconfigured in order to be used in future applications such as programmable analog circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:59Z
      DOI: 10.1142/S0218126619300113
       
  • An Electronically Controllable Voltage-Mode MOSFET-Only Single-Input
           Dual-Output Filter
    • Authors: Abdullah Yesil, Deniz Ozenli, Emre Arslan, Fırat Kacar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new design of voltage mode (VM), single-input dual-output MOSFET-only filter which has electronic tunability property is presented without using passive circuit elements like resistors and capacitors. The filter topology is able to realize low-pass (LP) and band-pass (BP) filter functions with using the same circuit configuration. The proposed filter is laid-out in the Cadence environment using 0.18-[math]m TSMC CMOS technology parameters. The layout area is only 344.4[math][math]m2 and the power consumption is about 170[math][math]W. Furthermore, variations in the center frequency of the BP filter are presented performing Monte Carlo (MC) analysis to reinforce the filter results. Also, the noise performance of the proposed filter is investigated and it is shown that the theoretical and simulation results are in very good agreement.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:59Z
      DOI: 10.1142/S0218126619502220
       
  • Dynamic Energy Reduction in TCAM Match-Line Sensing Using Charge-Sharing
           and Positive Feedback
    • Authors: Syed Iftekhar Ali, Safayat Bin Hakim
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180[math]nm 1.8[math]V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:57Z
      DOI: 10.1142/S0218126619502384
       
  • Ultra-Wideband Bandpass Filter Based on a Multi-Stub Loaded Loop Resonator
    • Authors: Xiaodong Xie, Zhizhan Yang, Mingxing Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A multi-stub loaded loop resonator (MSLLR) is proposed in this paper, which exhibits five main resonant modes of interest. Then, an ultra-wideband (UWB) bandpass filter is developed on it. Through direct source/load coupling, two transmission zeros can be created at both sides of the passband of the filter, which improves its frequency selectivity. The measured results of the fabricated filter show that its bandwidth can cover the UWB frequency range and the return loss in the passband is greater than 12.9[math]dB. Frequency selectivity is improved due to two transmission zeros at both sides of the passband. Group delay variation is less than 0.48[math]ns in the passband, which is relatively flat.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:56Z
      DOI: 10.1142/S0218126619200081
       
  • A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field
           Effect Transistor Including the Capacitive Effects
    • Authors: Sudipta Bardhan, Manodipan Sahoo, Hafizur Rahaman
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ([math]), transconductance ([math]), gate to drain capacitance ([math]) and gate to source capacitance ([math]) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than [math] NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:55Z
      DOI: 10.1142/S0218126619502414
       
  • A Novel Dual-Band Concurrent Asymmetric Doherty Power Amplifier for
           Wireless Communications
    • Authors: Shaban Rezaei Borjlu, Massoud Dousti
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a different dual-band asymmetric Doherty power amplifier (ADPA) with a novel dual-band bandpass filter (DBBPF) with quad-section stepped impedance resonators (SIRs) is presented. This specific DBBPF rejects the annoying frequencies of the second and third harmonics in the dual-band and contributes considerably to performance improvement of ADPA. This structure is confirmed with the design, simulation, implementation and testing of a 10 W GaN-based ADPA for global system for mobile communications (GSM) and worldwide interoperability for microwave access (WiMAX) applications at 1.84 and 3.5[math]GHz, respectively. In the measurement results, the ADPA defines a drain efficiency (DE) of 63.7% with an output power of 35[math]dBm and power gain is 14.2[math]dB, and a DE of 47.5% with an output power of 34.5[math]dBm and power gain is 10.4[math]dB at the 9[math]dB output power back-off (OBO) from the saturated output power in the two frequency bands. Linearity effects, applying 10[math]MHz 16 QAM signal and a 5[math]MHz WiMAX signal, display an adjacent channel leakage ratio of [math] and [math][math]dBc with the average output power of 36.8/36[math]dBm at 1.84/3.5[math]GHz, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:54Z
      DOI: 10.1142/S0218126619502359
       
  • A Novel LMMSE-EM Channel Estimator for High Mobility STBC-OFDM System
    • Authors: Jyoti Prasanna Patra, Poonam Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In time-selective fading channel, the Alamouti orthogonality principle is lost due to the variation of channel from symbol-to-symbol in space–time block-coded orthogonal frequency division multiplexing (STBC-OFDM) system and causes co-channel interference (CCI) effects. To combat the CCI effects, various signal detection schemes have been proposed earlier by assuming that a priori channel state information (CSI) is known to the receiver. However, in practice, the CSI is unknown and therefore accurate estimation of channel is required for efficient signal detection. In this paper, by exploiting circulant properties of the channel frequency response (CFR) autocorrelation matrix [math], we propose an efficient low complexity linear-minimum-mean-square-error (LMMSE) estimator. This estimator applies an expectation–maximization (EM) iterative process to reduce the computational complexity significantly. Finally, we compare the proposed LMMSE-EM estimator with conventional least square (LS) and LMMSE estimator in terms of performance and computational complexity. The simulation results show that the proposed LMMSE-EM estimator achieves exactly the same performance as the optimal LMMSE estimator with much lower computational complexity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:26Z
      DOI: 10.1142/S0218126619502232
       
  • Memristor Based Planar Tunable RF Circuits
    • Authors: C. L. Palson, D. D. Krishna, B. R. Jose, J. Mathew, M. Ottavi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Memristors have been recently proposed as an alternative to incorporate switching along with traditional CMOS circuits. Adaptive impedance and frequency tuning are an essential and challenging aspect in communication system design. To enable both, a matching network based on switchable capacitors with fixed inductors is proposed in this paper where the switching is done by memristive switches. This paper analyzes the operation of memristors as a switch and a matching network based on memristors which adaptively tunes with impedance and frequency. With three capacitor banks of each 0.5 pF resolution and two fixed inductors, matching for antenna impedance ranging from 20 to 200[math]Ohms and for frequencies ranging from 0.9 to 3.2[math]GHz is reported. Thereafter, an adaptive planar band-pass filter is implemented on CMOS technology with two metal layers. This adaptive frequency tunable band-pass filter uses a [math] network with resonator tanks in both arms that operates at 2.45 GHz. It is tunable from 2.8[math]GHz to 7.625[math]GHz range. This tunability is achieved using tunable spiral inductor based on memristive switches. The proposed filter layout is implemented and simulated in ANSYS Designer. The initialization and the programming circuitry to enable adaptive switching of the memristive devices has to be addressed. Since RF memristive devices are not commercially available, circuit level simulations are done as a proof of concept to validate the expected results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:26Z
      DOI: 10.1142/S0218126619502256
       
  • Time Efficient Segmented Technique for Dynamic Programming Based
           Algorithms with FPGA Implementation
    • Authors: Talal Bonny, Ridhwan Al Debsi, Mohamed Basel Almourad
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although dynamic programming (DP) is an optimization approach used to solve a complex problem fast, the time required to solve it is still not efficient and grows polynomially with the size of the input. In this contribution, we improve the computation time of the dynamic programming based algorithms by proposing a novel technique, which is called “SDP: Segmented Dynamic programming”. SDP finds the best way of splitting the compared sequences into segments and then applies the dynamic programming algorithm to each segment individually. This will reduce the computation time dramatically. SDP may be applied to any dynamic programming based algorithm to improve its computation time. As case studies, we apply the SDP technique on two different dynamic programming based algorithms; “Needleman–Wunsch (NW)”, the widely used program for optimal sequence alignment, and the LCS algorithm, which finds the “Longest Common Subsequence” between two input strings. The results show that applying the SDP technique in conjunction with the DP based algorithms improves the computation time by up to 80% in comparison to the sole DP algorithms, but with small or ignorable degradation in comparing results. This degradation is controllable and it is based on the number of split segments as an input parameter. However, we compare our results with the well-known heuristic FASTA sequence alignment algorithm, “GGSEARCH”. We show that our results are much closer to the optimal results than the “GGSEARCH” algorithm. The results are valid independent from the sequences length and their level of similarity. To show the functionality of our technique on the hardware and to verify the results, we implement it on the Xilinx Zynq-7000 FPGA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:25Z
      DOI: 10.1142/S021812661950227X
       
  • A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity
    • Authors: R. Nagulapalli
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by [math]20[math]dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to [math] will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5[math]dB PSRR improvement and 7.5% improvement in sensitivity to [math]. The proposed solution consumes 180[math]nW power from 1[math]V power supply voltage and occupies 3300[math][math]m2 silicon area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:25Z
      DOI: 10.1142/S0218126619502268
       
  • Hierarchical Optimization of Electric Vehicle System Charging Plan Based
           on the Scheduling Priority
    • Authors: Feng Ni, Linfang Yan, Ke Wu, Mengxuan Shi, Jianyu Zhou, Xia chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Unregulated charging of a large number of electric vehicles (EVs) simultaneously may cause electricity shortages and price spikes in the power market. This paper deals with the optimization of EV charging strategy using the priority sequence. Firstly, the evaluation indices such as the schedulable interval ratio, the emergency probability and the battery losses are proposed. Then a comprehensive evaluation system for the EV scheduling priority is established by adopting the entropy weight method to incorporate multiple indices. Based on the scheduling priority obtained, a double-hierarchical optimal model is proposed, taking into account the constraints such as the demand of the EV owner. Its upper objective aims to minimize the sum of the square of deviation between the actual and the required schedulable capacity of EV aggregator over every interval. The lower one minimizes the sum of EV scheduling priority sequence over the scheduling interval. Case studies with 100 EVs show that the hierarchical optimization model can assist EV aggregator in making effective charging scheme. It is also observed that better flexibility for dispatching EVs can be achieved using multiple indices with weights.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:24Z
      DOI: 10.1142/S0218126619502219
       
 
 
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