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  Subjects -> ELECTRONICS (Total: 187 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 7)
Advances in Electronics     Open Access   (Followers: 90)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Power Electronics     Open Access   (Followers: 38)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 337)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 26)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 14)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 30)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 20)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 38)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 13)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 9)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 295)
ECTI Transactions on Computer and Information Technology (ECTI-CIT)     Open Access  
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access  
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 117)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 97)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 100)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 55)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access   (Followers: 1)
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 207)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 99)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 80)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 49)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 72)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 71)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 58)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 26)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 42)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 78)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access  
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 55)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 70)
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 35)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 11)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 3)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 10)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 25)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 11)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 32)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 9)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 3)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 175)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 10)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 3)
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 11)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 29)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Microelectronics and Solid State Electronics     Open Access   (Followers: 27)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 41)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal   (Followers: 1)
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 9)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 2)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 56)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 78)
Solid State Electronics Letters     Open Access  
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Transactions on Electrical and Electronic Materials     Hybrid Journal  
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Ural Radio Engineering Journal     Open Access  
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
Journal of Circuits, Systems, and Computers
Journal Prestige (SJR): 0.172
Citation Impact (citeScore): 1
Number of Followers: 4  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0218-1266 - ISSN (Online) 1793-6454
Published by World Scientific Homepage  [119 journals]
  • A Start-up Assisted Fully Differential Folded Cascode Opamp
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, B. Yassine, S. Zourob, S. Raparthy, N. Yassine
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[math]dB, 250[math]MHz unity gain bandwidth amplifier has been developed in 65[math]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[math][math]A from a 1.2[math]V supply and occupies the 2184[math][math]m2 area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:11:08Z
      DOI: 10.1142/S0218126619501640
       
  • Two-Dimensional DOA Estimation for Planar Array Using a Successive
           Propagator Method
    • Authors: Weiyang Chen, Xiaofei Zhang, Chi Jiang
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      We consider the problem of two-dimensional (2D) direction of arrival (DOA) estimation for planar array, and propose a successive propagator method (PM)-based algorithm. The rotational invariance property of the propagator matrix is exploited to obtain the initial angle estimations, while the accurate estimates can be achieved through successive one-dimensional and local spectrum-peak searches. The proposed algorithm can obtain automatically paired 2D-DOA estimations, and it requires no eigenvalue decomposition of the covariance matrix of received data, which remarkably reduces the computational cost compared with traditional 2D-PM algorithm. In addition, the DOA estimation performance of the proposed algorithm is better than estimation of signal parameters via rotational invariance technique (ESPRIT) algorithm and PM algorithm, and is close to 2D-PM algorithm which requires 2D spectrum-peak search. Numerical simulations demonstrate the effectiveness and improvement of the proposed algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:10:54Z
      DOI: 10.1142/S0218126619501615
       
  • Formal Modeling and Verifying the TTCAN Protocol from a Probabilistic
           Perspective
    • Authors: Xin Li, Jian Guo, Yongxin Zhao, Xiaoran Zhu
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      The time-triggered CAN (TTCAN) protocol has been widely used in the automotive industry to fulfil the safety and real-time requirements of the application. As an extension of the standard CAN protocol, the TTCAN protocol aims to guarantee a safe and deterministic communication by introducing time-triggered messages with respect to a global synchronized time, which are scheduled in independent transmission windows within the system matrix. However, the new features bring more difficulties in designing and verifying the reliable applications in the TTCAN network. In this paper, we first present a formal probabilistic model of the TTCAN protocol with a consideration of its novel features. A TTCAN system consisting of three parts, i.e., a system matrix, an arbitration and some nodes, is modeled as discrete Markov chains model. Furthermore, five probabilistic properties are described and verified in the probabilistic model checker tool PRISM. Our work gives a quantitative analysis method for the given requirements, which facilitates the designers to a formal understanding of TTCAN protocol.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:10:41Z
      DOI: 10.1142/S0218126619501779
       
  • A Novel Synchronous Current-Doubler Rectifier for LED Drivers Without
           Electrolytic Capacitors
    • Authors: Jianguang Ma, Xueye Wei, Liang Hu, Junhong Zhang
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      High-brightness light-emitting diode (LED) lamps have attracted much attention because of their high efficiency, simple structure, energy conservation and environmental protection aspects, and long lifetime. Thus, an LED driver must have a long lifespan, high density, and compact space. However, conventional LED power supplies use an electrolytic capacitor as the storage capacitor in the holdup time, which has a short lifespan and occupies large space. In this paper, a novel synchronous current-doubler rectifier (SCDR) method is proposed as an LED driver. The reasonably designed circuit is used to control the output voltage ripple in the normal range without adding a complicated control circuit. The proposed topology is designed using few components, has no electrolytic capacitor, and has a low cost for high-output current LED driver applications. Circuit operating principles and detailed theoretical analysis are provided in this paper. A 200-W prototype has been established and tested, and the experimental results are presented to highlight the merits of the proposed circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:10:30Z
      DOI: 10.1142/S0218126619501755
       
  • Design of High Efficiency Linear Power Amplifier with a Continuous
           Broadband Based on Two-Tone Signal Analysis
    • Authors: Lu Chen, Gun Li
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      In this paper, an innovative approach to achieve broadband linear power amplifier (PA) with a continuous broadband is presented. The proposed method mainly depends on the theory of control of intermodulation products and harmonics. This method results in a continuous sweet spots over a wide bandwidth. Based on the continuous sweet spots, a suboptimal solution is derived for improving the efficiency and linearity of broadband PAs. To verify the effectiveness of this method, one broadband PA operating over 4.5–5.5[math]GHz is developed and measured, it indicates that the peak output power of the PA is 35–57[math]dBm for a small signal input with a gain of 12[math]dB, and the peak drain efficiency (DE) of the PA is larger than 57% over the whole working band. However, when the PA is stimulated by a 5[math]MHz two-tone signal input, we observe that the DE keeps above 38% under the condition of the measured third-order intermodulation distortion (IMD3) is not larger than [math][math]dBc.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:10:20Z
      DOI: 10.1142/S0218126619200068
       
  • A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for
           Coherent Optical Receiver in 0.13-[math]m SiGe BiCMOS
    • Authors: Jiquan Li, Yingmei Chen, Pan Tang, Zhen Zhang, Hui Wang, Hao Huang
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[math]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[math]m SiGe BiCMOS technology and it only occupies 1.05[math]mm[math][math][math]1.46[math]mm chip area. With a power consumption of 1.831[math]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[math]GS/s.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:10:05Z
      DOI: 10.1142/S0218126619501676
       
  • Group Delay Equalization of Polynomial Recursive Digital Filters in
           Maximal Flat Sense
    • Authors: Negovan Stamenković, Nikola Stojanović, Goran Perinić
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      The paper presents the development of an algorithm to obtain stable allpass filter, which acts as a group delay equalizer, with the aim to equalize group delay of the polynomial IIR filter in a maximal flat sense. The proposed method relies on a set of nonlinear equations, derived directly from the flatness conditions of the group delay response at the origin in the [math]-plane, with the order to obtain the unknown values of the allpass filter coefficients. The algorithm implemented in the MATLAB platform returns the coefficients of allpass filter. In the given example, first we construct a minimum phase polynomial IIR digital filter with a maximally flat magnitude at origin, next we augment the system with cascade connection of nonminimum allpass digital filter with order to equalize the group delay response of the whole filter in a maximally flat sense.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:09:50Z
      DOI: 10.1142/S0218126619501731
       
  • A New Technique for Designing Low-Power High-Speed Domino Logic Circuits
           in FinFET Technology
    • Authors: Sandeep Garg, Tarun K. Gupta
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[math]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[math] higher compared to different existing techniques in FinFET SG mode and is 1.42–[math] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [math] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:09:37Z
      DOI: 10.1142/S0218126619501652
       
  • Power–Delay-Error-Efficient Approximate Adder for Error-Resilient
           Applications
    • Authors: Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[math]18[math]J for 16-bit adder and 5.808E[math]18[math]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:09:23Z
      DOI: 10.1142/S0218126619501718
       
  • An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New
           Segmented Structure
    • Authors: Mehdi Bandali, Alireza Hassanzadeh, Masoume Ghashghaie, Omid Hashemipour
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[math]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [math]-V supply voltage with the sample rate of 140[math]MS/s show SFDR [math] 64.37[math]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:09:08Z
      DOI: 10.1142/S021812661950172X
       
  • Formal Equivalence Checking Between System-Level and RTL Descriptions
           without Pre-Given Mapping Information
    • Authors: Jian Hu, Tun Li, Sikun Li
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:08:56Z
      DOI: 10.1142/S0218126619501639
       
  • The Classification of EEG Signals with Multi-Domain Fusion Based on D-S
           Evidence Theory
    • Authors: Rongxiang Ge, Jianzhong Hu
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      The classification of electroencephalogram (EEG) signals is a key technique of brain–computer interface (BCI) system. In view of the complexity of EEG signals and the low accuracy in EEG signals recognition, a motor imagery EEG signals classification method with multi-domain fusion based on Dempster–Shafer (D-S) evidence theory is presented in this paper. Firstly, time domain statistics (TDS), autoregressive (AR) model and discrete wavelet transform (DWT) are used to extract features from EEG signals, respectively, and three probabilistic output support vector machine (SVM) classification models are trained based on these three feature sets. Secondly, using the output of each SVM, we construct basic probability assignment (BPA) function and get fusion BPA through D-S evidence theory. Finally, determining the class of test samples based on decision rules. Four databases from BCI competition are employed to evaluate the proposed approach, and the highest classification accuracy reaches 92.83%. Results show that this method acquires higher accuracy and has strong individual adaptability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:08:41Z
      DOI: 10.1142/S0218126619501603
       
  • Improved Adaptive Wavelet Thresholding for Effective Speckle Noise
           Reduction in Low Contrast Medical Images
    • Authors: P. Sreelatha, M. Ezhilarasi
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      Informative images endure from poor contrast and noise during image acquisition. Significant information retrieval necessitates image contrast enhancement and removal of noise as a prerequisite before any further processing can be done. Dominant applications with low contrast images affected by speckle noise are medical ultrasound images. The objective of this work is to improve the effectiveness of the preprocessing stage in medical ultrasound images by enhancing the image while retaining its structural characteristics. For image enhancement, this work proposes to develop an automatic contrast enhancement technique using cumulative histogram equalization and gamma correction based on the image. For noise removal, this work proposes an algorithm Gamma Correction with Exponentially Adaptive Threshold (GCEAT) which suggests the use of GC for contrast enhancement along with a new wavelet-based adaptive soft thresholding technique for noise removal. The proposed GCEAT-based image de-noising is validated with other enhancement and noise removal techniques. Experimental results with low contrast synthetic and actual ultrasound images show that the suggested proposed system performs better than existing contrast enhancement techniques. Encouraging results were obtained with medical ultrasound images in terms of Peak-Signal to Noise Ratio (PSNR), Mean Square Error (MSE), Structural Similarity Index Measure (SSIM) and Average Intensity (AI).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:08:26Z
      DOI: 10.1142/S0218126619501767
       
  • Reliability Analysis of High Gain Integrated DC–DC Topologies for
           Xenon Lamp Applications
    • Authors: Divya Navamani, K. Vijayakumar, Jason Manoraj
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      Emerging switched-mode power supplies incorporated applications demand reliable, less volume and high efficient dc–dc converters. The persistent usage of the dc–dc converters in various applications makes their reliability a significant concern. Hence, this paper deals with a family of non-isolated high gain integrated dc–dc converter topologies derived from a quadratic converter. The reliability analysis is carried out using electronic equipment reliability handbook, MIL-HDBK-217F. For the first time, reliability prediction is done based on the working environment of the power electronic equipments. We developed the reliability prediction for the converters used in the lighting application such as automotive headlamp and aircraft landing lights. The mean time to failure for both the environment is calculated. The reliability comparison is carried out for the proposed topologies and the most reliable converter is chosen. Also, all the converter topologies are simulated using nL5 simulator to confirm their theoretical results. Finally, a laboratory prototype for 40 W with input voltage of 12 V is implemented for the most reliable topology to validate the steady-state analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:08:10Z
      DOI: 10.1142/S0218126619501688
       
  • Design of a Low-Phase-Noise Ka-Band GaAs HBT VCO
    • Authors: Jincan Zhang, Min Liu, Liwen Zhang, Jinchan Wang, Bo Liu
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      In this paper, the study of a Ka-band GaAs HBT VCO is reported with particular emphasis on achieving low-phase noise while using direct coupled varactor. A push–push cross-coupled VCO configuration is employed to achieve high oscillation frequency and low-phase noise. The measured oscillation bandwidth spans from 30.2 to 28.6[math]GHz with a tuning range of 1.6[math]GHz, while the phase noise at 1[math]MHz of frequency offset from the carrier at 29.3[math]GHz is [math][math]dBc/Hz. The VCO consumes 28.2[math]mW from 3[math]V supply and occupies an area of [math][math]mm. The FOM of the VCO achieves [math][math]dBc/Hz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:07:55Z
      DOI: 10.1142/S0218126619501743
       
  • Design and Analysis of a Broadband Current-Mode CMOS Direct-Conversion
           Receiver Frond-End Circuit
    • Authors: Xin Han Chen, Shuxiang Song, Mingcan Cen
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      A broadband (0.8–5[math]GHz) CMOS current-mode direct-conversion receiver has been integrated in a 0.18-[math]m CMOS process. The proposed receiver front-end features a broadband active-balun low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference, conversion gain and outstanding linearity. With the technique of noise and distortion cancellation which performs a better input impedance matching, we employ a broadband common-gate–common-source (CG–CS) LNTA and a current mirror to improve both gain and noise figure (NF) performance. Compared to the 50% duty-cycle switching stage, the 25% duty-cycle I–Q switching stage is implemented by using serial switches driven by 50% quadrature local oscillator (LO) signals separately, which improves the down-conversion gain by 3[math]dB and lowers the noise figure. The transimpedance amplifier employs the [math]-boosting technique to realize low input impedance and high transimpedance gain. The core circuit (RF and baseband signal path) consumes 26[math]mW, and the prototype receiver achieves approximately 33–34.5-dB conversion gain, 8.1–9.35-dB NF and 7.5–9.8-dBm IIP3 from 0.8[math]GHz to 5[math]GHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:07:34Z
      DOI: 10.1142/S021812661950169X
       
  • Memristor Emulator Circuit Using Multiple-Output OTA and Its Experimental
           Results
    • Authors: Rajeev Kumar Ranjan, Pankaj Kumar Sharma, Sagar, Niranjan Raj, Bharti Kumari, Fabian Khateb
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      A charge-controlled memristor emulator circuit based on one kind of active device [operational transconductance amplifier (OTA)] using CMOS technology is introduced in this paper. The proposed circuit can be configured in both incremental and decremental types by using a simple switch. The memristor behavior can be electronically tuned by adjusting the transconductance of the OTAs. By changing the value of the capacitor, the pinched hysteresis loop observed in the current versus voltage plane can be held at higher frequencies. The proposed emulator circuit functions well up to 500 kHz. The experiment has been performed using commercially available OTA ICs (CA3080). The experimental demonstration has been carried out for 10, 20 and 120[math]kHz. A simple high-pass filter is explained in both configurations to demonstrate the functionality of the proposed memristor emulator. The proposed circuit has been simulated in PSPICE using 0.5-[math]m CMOS parameter. The simulated and experimental results validate the theoretical proposition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:07:20Z
      DOI: 10.1142/S0218126619501664
       
  • Design of a Tri-Band Doherty Amplifier Based on Generalized Impedance
           Inverter
    • Authors: Weimin Shi, Songbai He
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      This paper introduces a methodology for implementing multi-band Doherty power amplifiers. Traditionally, a 90∘ impedance inverter line is required in Doherty architecture. In this contribution, a generalized impedance inverter line is utilized to construct multi-band Doherty power amplifiers. A tri-band Doherty power amplifier operating at 1.15, 1.85 and 2.55[math]GHz is designed to validate the proposed method. Measurement results show the fabricated Doherty power amplifier achieves 6[math]dB output back-off drain efficiencies of 62.3%, 49.3% and 50.5% at 1.15, 1.85 and 2.55[math]GHz, respectively. The peaking output power of the fabricated tri-band Doherty power amplifier is 43.2, 43.7 and 43.8[math]dBm with drain efficiencies of 64.5%, 62.2% and 64.5% at three working frequency points, respectively. Furthermore, when the designed Doherty power amplifier is driven by a 20[math]MHz wideband LTE signal with peak-to-average-power ratio of 6.4[math]dB, adjacent channel power ratios of [math]29.4 and [math]57.1[math]dBc are achieved before and after digital pre-distortion at 1.85[math]GHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:07:05Z
      DOI: 10.1142/S0218126619501706
       
  • Resistorless Frequency Locked On-Chip Oscillator with
           Proportional-to-Absolute Temperature References
    • Authors: Peiqing Han, Niansong Mei, Zhaofeng Zhang
      Abstract: Journal of Circuits, Systems and Computers, Volume 28, Issue 10, September 2019.
      A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[math]m standard CMOS process with an active area of 0.072[math]mm2. The temperature coefficient of frequency is 48[math]ppm/∘C at best and 82.5[math]ppm/∘C on average over [math]–70∘C and the frequency spread is 1.43% ([math]/[math] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[math]V to 1[math]V and the power consumption is 95[math]nW under the supply voltage of 0.65[math]V.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-26T07:06:55Z
      DOI: 10.1142/S0218126619501627
       
  • Efficient and Robust Approach for Heartbeat Detection of ECG Signal
    • Authors: Anas Fouad Ahmed, Mohammed Abdulmunem Ahmed, Hussain Mustafa Bierk
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces an efficient and robust method for heartbeat detection based on the calculated angles between the successive samples of electrocardiogram (ECG) signal. The proposed approach involves three stages: filtering, computing the angles of the signal and thresholding. The suggested method is applied to two different types of ECG databases (QTDB and MIT-BIH). The results were compared with the other algorithms suggested in previous works. The proposed approach outperformed the other algorithms, in spite of its simplicity and their fast calculations. These features make it applicable in real-time ECG diagnostics systems. The suggested method was implemented in real-time using a low cost ECG acquisition system and it shows excellent performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-18T08:43:41Z
      DOI: 10.1142/S0218126620501339
       
  • Implementation of Efficient Intra- and Inter-Zone Routing for Extending
           Network Consistency in Wireless Sensor Networks
    • Authors: A. Prasanth, S. Pavalarajan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor network (WSN) consists of a large amount of limited battery-powered sensor nodes. In general, energy consumption will be a significant concern for WSN owing to irreplaceable battery constraints of sensor nodes. The zone formation approach could be an adequate data aggregation technique which efficiently minimizes the energy consumption by categorizing sensor nodes into zones. However, the main constraints like zone head (ZH) selection, frequent change of ZH, and multi-hop communication from ZH to the sink have a direct impact on the network consistency of WSN. In this paper, a novel efficient intra- and inter-zone routing scheme has been proposed in order to prolong the network consistency of WSN. In the proposed scheme, the hybrid algorithm is established in which harmony search algorithm incorporates with modified moth flame optimization algorithm. This hybrid algorithm provides the appropriate ZH selection for intra-zone routing that reduces the frequent change of ZH in the network. Furthermore, the path balancing in inter-zone routing is acquired through multi-criteria-based optimal path routing algorithm. The performance results confirm that the proposed scheme enhances the network consistency compared with an existing scheme.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-10T03:57:04Z
      DOI: 10.1142/S0218126620501297
       
  • A 2.3 mW Multi-Frequency Clock Generator with [math]137 dBc/Hz Phase Noise
           VCO in 180 nm Digital CMOS Technology
    • Authors: Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[math]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[math]nm CMOS process with supply voltage of 1.8[math]V. The phase noise of VCO is [math][math]dBc/Hz at an offset frequency of 100[math]MHz. The reference clock of 25[math]MHz synthesizes the output clock of 1.6[math]GHz with rms jitter of 0.642[math]ps.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-10T03:57:03Z
      DOI: 10.1142/S0218126620501303
       
  • Cascaded Dense-UNet for Image Super-Resolution
    • Authors: Huaijuan Zang, Leilei Zhu, Zhenglong Ding, Xinke Li, Shu Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recently, deep convolutional neural networks (CNNs) have achieved great success in single image super-resolution (SISR). Especially, dense skip connections and residual learning structures promote better performance. While most existing deep CNN-based networks exploit the interpolation of upsampled original images, or do transposed convolution in the reconstruction stage, which do not fully employ the hierarchical features of the networks for final reconstruction. In this paper, we present a novel cascaded Dense-UNet (CDU) structure to take full advantage of all hierarchical features for SISR. In each Dense-UNet block (DUB), many short, dense skip pathways can facilitate the flow of information and integrate the different receptive fields. A series of DUBs are concatenated to acquire high-resolution features and capture complementary contextual information. Upsampling operators are in DUBs. Furthermore, residual learning is introduced to our network, which can fuse shallow features from low resolution (LR) image and deep features from cascaded DUBs to further boost super-resolution (SR) reconstruction results. The proposed method is evaluated quantitatively and qualitatively on four benchmark datasets, our network achieves comparable performance to state-of-the-art super-resolution approaches and obtains pleasant visualization results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-09T08:11:29Z
      DOI: 10.1142/S0218126620501212
       
  • Design and Analysis of Power Efficient TG Based Dual Edge Triggered
           Flip-Flops with Stacking Technique
    • Authors: Neethu Anna Sabu, K. Batri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[math]nm CMOS technology with a power supply of 1[math]V at 500[math]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-09T08:11:29Z
      DOI: 10.1142/S0218126620501236
       
  • An Efficient Interface Circuit for Miniature Piezoelectric Energy
           Harvesting with P-SSHC
    • Authors: Lianxi Liu, Yu Shang, Jiangwei Cheng, Zhangming Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A miniature and high-efficiency interface circuit based on parallel synchronous switch harvesting on capacitors (P-SSHC) for piezoelectric energy harvesting (PEH) is proposed in this paper. This interface circuit consists of a two-stage synchronous rectifier and the P-SSHC circuit. The two-stage synchronous rectifier, composed of a negative voltage converter (NVC) and an active diode (AD), achieves higher efficiency compared with the full-bridge rectifier (FBR). In addition, the two-stage synchronous rectifier detects the zero-crossing moment of the input current; therefore, an extra current zero-crossing detection circuit is eliminated, which simplifies the structure of the interface circuit, reduces power consumption and improves peak converting efficiency. The P-SSHC circuit aims to improve the power extraction capability of the rectifier. The P-SSHC achieves considerable voltage flipping efficiency with very small volume compared to the parallel synchronized switch harvesting on inductor (P-SSHI), which is more suitable for volume sensitive applications. The proposed interface circuit is designed in SMIC 0.35[math][math]m CMOS process. Simulation results show that it achieves a [math] output power improvement compared with FBR for the case of a 3.4[math]V open-circuit voltage, the voltage flipping efficiency is as high as 83.6% and the peak power converting efficiency is up to 91.5%. The overall volume of the capacitors used in this paper is only 0.6[math]mm3, which is much smaller than the inductor used by conventional P-SSHI interface circuit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-09T08:11:28Z
      DOI: 10.1142/S0218126620200042
       
  • Application of the Computer Capacity to the Analysis of Processors
           Evolution
    • Authors: Boris Ryabko, Anton Rakitskiy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The concept of the so-called computer capacity was proposed in 2012 and applied for analysis of processors of different kinds. Here, we analyze the evolution of processors using the computer capacity as the main tool of analysis. It is shown that during the transition “from old to new” the manufacturers change the parameters that affect the computer capacity. It allows us to predict the values of parameters of following processors. Intel processors are used as the main example due to their high popularity and the accessibility of detailed description of all the technical characteristics.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-09T08:11:28Z
      DOI: 10.1142/S0218126620501273
       
  • A Temperature-Stable Low-Power Wide-Range CMOS Voltage Controlled
           Oscillator Design for Biomedical Applications
    • Authors: Zied Sakka, Nadia Gargouri, Mounir Samet
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a low power temperature compensated CMOS ring oscillator for biomedical applications across a wide temperature range. The proposed circuit deploys an IPTAT (inversely proportional to absolute temperature) bias current by generating an adaptive control voltage in each stage of the oscillator to compensate the overall oscillator’s temperature coefficient (TC). Simulations using TSMC 0.18[math][math]m CMOS technology show that this configuration can achieve a frequency variation less than 0.25%, leading to an average frequency drift of 20.83[math]ppm/∘C. Monte Carlo simulations have also been performed and demonstrate a 3[math] deviation of about 2.15%. The power dissipated by the proposed circuit is only 8.48[math]mW at 25∘C.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-09T08:11:27Z
      DOI: 10.1142/S0218126620501285
       
  • Covert Electromagnetic Nanoscale Communication System in the Terahertz
           Channel
    • Authors: Areeb Ahmed, Ferit Acar Savaci
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, an electromagnetic nano random communication system (EM-nRCS) has been proposed which ensures covert communication in the terahertz (THz) band. In the proposed system, the skewed alpha-stable noise shift keying method has been used to transmit random noise signals (RNSs) from the nano-transmitter (NT) by utilizing single-walled/carbon nanotubes-based true random number generator (SWCNTs-TRNG) and a graphene-based nano-antenna. A line-of-sight THz transparency window between 0.1[math]THz and 0.5[math]THz in the THz channel with spreading loss, molecular absorption loss and molecular absorption noise has been considered. Due to the broadband nature of the RNSs, the proposed EM-nRCS provides efficient transmission by overcoming the high path loss and intense channel noise arising from random fluctuations in the THz band. Non-coherent nano-receiver (NR) consisting of the modified extreme value method (MEVM) estimator has been proposed to extract the hidden binary information in the received RNSs. The bit error rate performance shows that the proposed EM-nRCS ensures high performance and covertness for future EM nanoscale communication devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-09T08:11:26Z
      DOI: 10.1142/S0218126620501261
       
  • A Novel Constant Power Management Controller for Hybrid PV-Battery System
    • Authors: V. S. N. Narasimha Raju, M. Premalatha, D. V. Siva Krishna Rao K
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In grid-connected applications, the photovoltaic (PV)-based power generation is getting more attention these days due to several factors like pollution-free, single investment plant, etc. However, it has the drawback of interruption in power generation, which makes it undesirable to power system. In order to overcome this drawback, a constant power is supplied to the grid by integrating energy storage system like battery and/or ultra-capacitor with solar PV. This paper proposes a grid-connected PV-battery-based hybrid power system to deliver a constant power to the grid. Modeling and simulation of solar PV-battery-based hybrid system have been developed and the constant power management controller (CPMC) is ensured to inject constant power at the change in environmental conditions. The simulation result shows the performance of proposed control algorithm to PV-battery-based hybrid system is validated.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-02T07:26:28Z
      DOI: 10.1142/S0218126620501194
       
  • FPGA-Based Pipelined Architecture for Real-Time Estimation of Sensitivity
           Maps Using Pre-Scan Method in Parallel MRI
    • Authors: Tooba Khan, Muhammad Faisal Siddiqui, Hammad Omer
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Parallel MRI (pMRI) is a widely used technique for increasing the MRI acquisition speed, by using multiple receiver coils with spatially discriminated sensitivities. Sensitivity encoding (SENSE) is a parallel MRI technique used for reconstructing the aliasing free images from the under-sampled MRI data using the spatial information obtained from multiple receiver coils. Precise receiver coil sensitivity estimation is critical for the correct image reconstruction from the under-sampled data in SENSE. Pre-scan method is a quick and conventionally used method for correct estimation of the receiver coil sensitivities, to be used in SENSE. In this work, an application-specific hardware implemented on FPGA (Field Programmable Gate Array) for real-time sensitivity maps estimation using the pre-scan method is proposed. The proposed architecture has the potential to be installed on the receiver coil data acquisition system, which would provide sensitivity maps for image reconstruction, without moving the raw data to the MRI workstation. Parallelism is utilized in the proposed pipelined architecture to make it even faster. From the experimental results, it is shown that the proposed architecture estimates the sensitivity maps in only 1.466[math]ms for eight receiver coils. Furthermore, high mean SNR (30[math][math]dB), low root-mean-square-error ([math]) and low artifact power ([math]) are achieved for the under-sampled human head, cardiac and phantom data sets (acceleration factor = 2), reconstructed with SENSE algorithm utilizing the sensitivity maps estimated by the proposed architecture.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-09-02T07:26:27Z
      DOI: 10.1142/S021812662050125X
       
  • Detection and Classification of High Impedance Fault in Power Distribution
           System using Hybrid Technique
    • Authors: N. Narasimhulu, D. V. Ashok Kumar, M. Vijaya Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a hybrid strategy is introduced for detecting and classifying the High Impedance Fault in Power Distribution System. For hybridization, Gravitational Search Algorithm is combined with Artificial Neural Network to crease the classification performance. The ANN is utilized to characterize the blame signal from the reference signal and the execution is enhanced in view of the GSA calculation. The yield of the proposed method is recognized and arranged whether it is HIF fault or no-fault. At first, the ordinary practices of the appropriation framework are assessed. After that, the deficiencies are connected and the signals are measured. At that point, these are given to the contribution of the enhanced ANN procedure, which gives the dataset to breaking down the framework exhibitions. Finally, the proposed strategy is implemented in the MATLAB/Simulink model and its execution is assessed and compared with other conventional techniques like DWT-ANFIS, DWT-RBFFN, MWT-ANFIS, and MWT-FLC based GA. From the experimental results, it shows that the proposed method achieved better performance than existing methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-26T08:24:08Z
      DOI: 10.1142/S0218126620501182
       
  • Design of the Baseband Physical Layer of NarrowBand IoT LTE Uplink Digital
           Transmitter
    • Authors: Basma H. Mohamed, Ahmed Taha, Ahmed Shawky, Essraa Ahmed, Ali Mohamed, Manar Mohsen, Rodina Samy, Amr ELHosiny, Ahmed Ibrahim, Hassan Mostafa
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With the new age of technology and the release of the Internet of Things (IoT) revolution, there is a need to connect a wide range of devices with varying throughput and performance requirements. In this paper, a digital transmitter of NarrowBand Internet of Things (NB-IoT) is proposed targeting very low power and delay-insensitive IoT applications with low throughput requirements. NB-IoT is a new cellular technology introduced by 3GPP in release 13 to provide wide-area coverage for the IoT. The low-cost receivers for such devices should have very low complexity, consume low power and hence run for several years. In this paper, the implementation of the data path chain of digital uplink transmitter is presented. The standard specifications are studied carefully to determine the required design parameters for each block. And the design is synthesized in UMC 130-nm technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-26T08:24:08Z
      DOI: 10.1142/S021812662050111X
       
  • Convolutional Neural Network for Sparse Reconstruction of MR Images
           Interposed with Gaussian Noise
    • Authors: M. V. R. Manimala, C. Dhanunjaya Naidu, M. N. Giri Prasad
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Compressive Sensing (CS) reconstructs high-quality images from very few measurements, which are far below Nyquist rate. CS proves to be very useful for acquiring high dimensional image sets like Magnetic Resonance Imaging (MRI). However, the efficiency of MR image reconstruction is affected due to slow acquisition of voluminous k-space data. To improve the quality of reconstructed image and increase the speed of the reconstruction, a novel algorithm namely Adaptive Sparse Reconstruction using Convolution Neural Network AsrCNN has been, proposed for MR Images. AsrCNN employs a CNN, which consists of four convolutional layers and one fully connected layer. The proposed algorithm reconstructs MR images with immense quality, as it is trained over a large dataset with adaptive gradient optimization. The training set consists of [math] image patches, which is used to create the dictionary by adaptively updating the weights. Subsequently, the dictionary is employed for recovery of sparse MR images corrupted with Gaussian noise. Patch-based approach in AsrCNN enables MR images of varied sizes to be processed without resizing. Experimental results for AsrCNN show an improvement of 1–5 dB in PSNR over previous state-of-art algorithms. Training has been done on GPU using Convolutional Architecture for Fast Feature Embedding (CAFFE) framework as it reduces significant amount of time in reconstructing images.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-26T08:24:07Z
      DOI: 10.1142/S0218126620501169
       
  • A Novel Asymmetrical Reduced Switch Nine-Level Inverter
    • Authors: Madan Kumar Das, Akanksha Sinha, Kartick Chandra Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel asymmetrical nine-level inverter topology using only six switches along with its generalized structure are presented in this paper. The proposed reduced switch multilevel inverter topology makes use of a lower total standing voltage for a required output voltage as compared to the existing ones. One of the major advantages of the proposed multilevel inverter over other existing topologies is that, the circuit can be extended to a higher-level inverter, by cascading a few proposed inverter modules and can also be extended to the three-phase structure very easily, thereby making the inverter structure simple. In addition to this, the proposed inverter module does not require any additional H-bridge circuit to obtain the negative voltage levels for AC voltage, resulting in reduced voltage stress on the switches. This paper also incorporates an effective technique to determine the total standing voltage as well as the switching and conduction losses of the inverter. The MATLAB/Simulink based proposed nine-level as well as an 81-level inverters are modeled and the simulation results are presented. An experimental prototype of nine-level inverter using six switches is developed and tested to validate the simulation results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-21T03:07:38Z
      DOI: 10.1142/S0218126620501170
       
  • A VGA Linearity Improvement Technique for ECG Analog Front-End in
           65[math]nm CMOS
    • Authors: Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a 65[math]nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100[math]mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15[math]dB reduction in the harmonic distortion for 20[math]mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108[math][math]m2 silicon area and consumes 0.43 [math]A from a 1.2[math]V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-21T03:07:38Z
      DOI: 10.1142/S0218126620501133
       
  • The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power
           Circuit Designs
    • Authors: Haiyan Ni, Jianping Hu, Xuqiang Zhang, Haotian Zhu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a method of optimizing dual-threshold independent-gate FinFET devices is discussed, and the optimal circuit design is carried out by using these optimized devices. Dual-threshold independent-gate FinFETs include low threshold devices and high threshold devices. The low threshold device is equivalent to two merging parallel short-gate devices and high threshold device is equivalent to two merging series SG devices. We optimize the device mainly by selecting the appropriate gate work function, gate oxide thickness, silicon body thickness and so on. Our optimization is based on the Berkeley BSIMIMG model and verified by TCAD tool. Based on these optimized devices, we designed the compact basic logic gates and two new compact D-type flip-flops. Additionally, we developed a circuit synthesis method based on Binary Decision Diagram (BDD) and the optimized compact basic logic gates. Hspice simulations show that the circuits using the proposed dual-threshold IG FinFETs have better performance than the circuits directly using the short-gate devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-21T03:07:37Z
      DOI: 10.1142/S0218126620501145
       
  • A Low-Loss and High-Isolation Transformer-Based mm-Wave SPDT with
           Integrated Fan-out Wafer Level Packaging
    • Authors: Xing Quan, Jiang Luo, Guodong Su, Kai Jing, Jinsong Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40[math]nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34[math]dB and the IL is less than 2.2[math]dB at 24–31[math]GHz. The isolations are better than 27[math]dB between two double-throw ports and better than 20[math]dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220[math][math] (with PADs) and its return losses are better than [math]9[math]dB at 24–31[math]GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-16T09:56:14Z
      DOI: 10.1142/S0218126620501157
       
  • Design Guidelines for MEMS Optical Accelerometer based on Dependence of
           Sensitivities on Diaphragm Dimensions
    • Authors: Sumit Kumar Jindal, Srishti Priya, S. Kshipra Prasadh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work deals in specifying the design considerations while constructing a Micro Electro Mechanical Systems (MEMS) optical accelerometer working on capacitive sensing technique. Sensitivity is one of the most demanded characteristics of any sensor. The sensor considered is a MEMS capacitive accelerometer in which both displacement and capacitance are the primary sensing characteristics. This differential capacitive accelerometer causes change in displacement due to applied acceleration and further produces change in capacitance. So, the main focus in this work is to improve or select the suitable diaphragm dimensions of the differential capacitor in order to get optimal capacitive and displacement sensitivity. This is done for an Optical MEMS (MOEMS) based sensor where slight change has a large-scale impact. The electrical signal is converted to optical by adding an Optical Interferometer. Mach–Zehnder Interferometer (MZI) is used to carry out the intensity modulation which also gives protection in inflammable surroundings. This makes the system suitable for working in high temperature regions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-16T09:56:14Z
      DOI: 10.1142/S0218126620501078
       
  • The Evolution of Integrated CMOS Power Amplifiers for Next Generation
           Mobile Wireless Transceivers
    • Authors: Selvakumar Mariappan, Jagadheswaran Rajendran, Harikrishnan Ramiah, Norlaili Mohd Noh, Asrulnizam Abd Manaf
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless communication standard continues to evolve in order to fulfill the demand for high data rate operation. This leads to the exertion on the design of radio frequency power amplifier (RFPA) which consumes high DC power in order to support linear transmission of high data rate signal. Hence, operating the PA with low DC power consumption without trading-off the linearity is vital in order to achieve the goal of achieving fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the evolution of CMOS PA toward achieving a fully integrated transceiver solution is discussed through the review of multifarious CMOS PA design. This is categorized into the review of efficiency enhancement designs followed by linearity enhancement designs of the CMOS PA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-16T09:56:13Z
      DOI: 10.1142/S021812662030007X
       
  • A Hybrid Multi-Agent-Based BFPSO Algorithm for Optimization of Benchmark
           Functions
    • Authors: Renuka Kamdar, Priyanka Paliwal, Yogendra Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The goal to provide faster and optimal solution to complex and high-dimensional problem is pushing the technical envelope related to new algorithms. While many approaches use centralized strategies, the concept of multi-agent systems (MASS) is creating a new option related to distributed analyses for the optimization problems. A novel learning algorithm for solving the global numerical optimization problems is proposed. The proposed learning algorithm integrates the multi-agent system and the hybrid butterfly–particle swarm optimization (BFPSO) algorithm. Thus it is named as multi-agent-based BFPSO (MABFPSO). In order to obtain the optimal solution quickly, each agent competes and cooperates with its neighbors and it can also learn by using its knowledge. Making use of these agent–agent interactions and sensitivity and probability mechanism of BFPSO, MABFPSO realizes the purpose of optimizing the value of objective function. The designed MABFPSO algorithm is tested on specific benchmark functions. Simulations of the proposed algorithm have been performed for the optimization of functions of 2, 20 and 30 dimensions. The comparative simulation results with conventional PSO approaches demonstrate that the proposed algorithm is a potential candidate for optimization of both low-and high-dimensional functions. The optimization strategy is general and can be used to solve other power system optimization problems as well.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-16T09:56:13Z
      DOI: 10.1142/S0218126620501121
       
  • A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise
           Randomization for Multi-Bit DACs
    • Authors: Di Li, Chunlong Fei, Qidong Zhang, Yani Li, Yintang Yang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[math]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[math]mm2, and dissipated a power of 28.8[math]mW from a 1.8-V power supply at a sampling rate of 320[math]MHz. The measured spurious-free dynamic range (SFDR) was 94[math]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[math]dB at [math]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[math]pJ/conv.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-13T02:41:12Z
      DOI: 10.1142/S021812662050108X
       
  • A New Capacitance Multiplier Structure with High Multiplication Factor for
           Ultra-Low-Frequency Filter in Biomedical Applications
    • Authors: Yan Li, Yong Liang Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel capacitance multiplier is proposed to implement an ultra-low-frequency filter for physiological signal processing in biomedical applications. With the proposed multiplier, a simple first-order low-pass filter achieves a [math]3-dB frequency of 33.4[math]μHz with a 1-pF capacitance and a 20[math]k[math] resistance. This corresponds to a multiplication factor of as large as [math]. By changing the controlling terminal, the [math]3-dB frequency can be tuned in a wide range of 33.4[math]μHz–6.3[math]kHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-13T02:41:12Z
      DOI: 10.1142/S0218126620501091
       
  • A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for
           Low-Power Application
    • Authors: Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32[math]mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-13T02:41:11Z
      DOI: 10.1142/S0218126620501108
       
  • Development and Application of a Coupling Method for Well Pattern and
           Production Optimization in Unconventional Reservoirs
    • Authors: Yukun Chen, Hui Zhao, Qi Zhang, Yuhui Zhou, Hui Wang, Sheng Lei, Shujian Xie, Lingfei Xu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Numerous optimization variables cause the optimization of large-scale field development challenging, which can be overcome by constraining wells to be within patterns and optimizing the parameters relevant to the pattern type and geometry. In this study, a new method incorporating well pattern optimization and production optimization for unconventional reservoirs is presented. By defining a quantitative well pattern description approach, we develop the geometric transformation parameters to quantify well pattern operations (e.g., rotation, shear, especially translation) to change the geometric shape of well patterns including five-spot, inverse seven-spot and inverse nine-spot well pattern. In contrast, a variety of optimization algorithms can be applied to accomplish the optimization of well pattern problems but the computational cost is large for many algorithms. Therefore, we also propose a general upscaling stochastic approximation algorithm (GUSA), which is an improved approximate perturbation gradient algorithm, to realize the combination of well pattern optimization and production optimization simultaneously. It is proved that both the gradient formulation of SPSA algorithm and EnOpt algorithm are the special form of the general approximate perturbation gradient. Afterwards, the synthetic cases (homogeneous and heterogeneous models) and actual unconventional field cases are discussed based on the three mentioned well pattern types. The detailed optimization results show that the presented coupling method can achieve the optimization by transforming well pattern geometry, reducing the total number of wells and adjusting the field injection rate, which is proved to be effective. In sum, this coupling method provides an efficient optimization procedure combing the well pattern optimization and production optimization for practical field development.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-05T07:24:42Z
      DOI: 10.1142/S0218126620501054
       
  • Blind Joint DOA and Polarization Estimation for Polarization-Sensitive
           Coprime Arrays Via Reduced-Dimensional Root Finding Approach
    • Authors: Jinqing Shen, Xiaofei Zhang, Yi He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we investigate the problem of blind joint multi-parameter estimation for polarization-sensitive coprime linear arrays (PS-CLAs). We propose a reduced-dimensional polynomial root finding approach, which first utilizes the relation between the two subarrays to reconstruct the spectrum function and then converts three-dimensional (3D) total spectral search (TSS) to one-dimensional (1D) TSS. Furthermore, 1D polynomial root finding technique is employed to obtain the ambiguous direction of arrival (DOA) estimates, for further saving the computational cost. Finally, the true DOA estimates can be obtained based on the arrangements with coprime property, and subsequently the polarization parameters can be estimated through pairing. In addition, the matching error of false targets can be avoided due to the relation between the two subarrays. The proposed approach only requires about 0.01% computational complexity of the 1D TSS method to achieve the same estimation performance and behaves better in resolution. Simulations are provided to validate the superiority of the proposed approach.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-05T07:24:41Z
      DOI: 10.1142/S0218126620501042
       
  • A Modified Two-Step ANN Ensemble Approach to Improve Generalization and
           its Application in Fractal Antenna Design
    • Authors: Balwinder S. Dhaliwal, Gaganpreet Kaur, Navreet Saini, Shyam Sundar Pattnaik, Simranjit Kaur Josan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, a fractal antenna with rectangular base shape has been designed for 5.2[math]GHz resonant frequency. Recently, ANN modeling of fractal antenna parameters have shown to be an effective approach for its design optimization. But the selection of ANN ensemble members and their output aggregation are two important issues for efficient operation of ANN ensembles. A novel two-step method based on output sensitivity of ANN and genetic algorithm optimization of ensemble members has been proposed in this paper for addressing the above two issues. The proposed approach, which is a modified form of existing technique, has been first validated by applying it over six benchmark functions and compared with existing approach for improved performance. Further, the proposed approach has been used to develop an ANN ensemble for design optimization of fractal antenna at 5.2[math]GHz resonant frequency. The selected antenna geometry has been experimentally verified and has shown significant miniaturization of 48.34% as compared to conventional rectangular micro-strip antenna.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-08-05T07:24:41Z
      DOI: 10.1142/S0218126620501066
       
  • A Review of Geological Applications of High-Spatial-Resolution Remote
           Sensing Data
    • Authors: Chunming Wu, Xiao Li, Weitao Chen, Xianju Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Geologists employ high-spatial-resolution (HR) remote sensing (RS) data for many diverse applications as they effectively reflect detailed geological information, enabling high-quality and efficient geological surveys. Applications of HR RS data to geological and related fields have grown recently. HR optical remote sensing data are widely used in geological hazard assessment, seismic monitoring, mineral exploitation, glacier monitoring, and mineral information extraction due to high accuracy and clear object features. By reviewing these applications, we can better understand the results of previous studies and more effectively use the latest data and methods to efficiently extract key geological information. Compared with optical satellite images, synthetic-aperture radar (SAR) images are stereoscopic and exhibit clear relief, strong performance, and good detection of terrain, landforms, and other information. SAR images have been applied to seismic mechanism research, volcanic monitoring, topographic deformation, and fault analysis. Furthermore, a multi-standard maturity analysis of the geological applications of HR images reveals that optical remote sensing data are superior to radar data for mining, geological disaster, lithologic, and volcanic applications, but inferior for earthquake, glacial, and fault applications. Therefore, it is necessary for geological remote sensing research to be truly multi-disciplinary or inter-disciplinary, ensuring more detailed and efficient surveys through cross-linking with other disciplines. Moreover, the recent application of deep learning technology to remote sensing data extraction has improved the capabilities of automatic processing and data analysis with HR images.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-30T10:14:35Z
      DOI: 10.1142/S0218126620300068
       
  • A New Tune-Dependent Multiple-Gated Transistor Linearization Technique
    • Authors: Farzan Rezaei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new multiple-gated transistor (MGTR) linearization technique is presented. To simultaneously keep linearity and tuning capability of proposed operational transconductance amplifier (OTA), the auxiliary transistors which are employed for [math] cancellation of differential pair (DP) stage are body-driven through a tune-dependent voltage. By this way, the third-order nonlinearity of DP is reduced for a wide range of transconductance values from 5.1 to 35.6[math][math]A/V. The OTA works with 1.2[math]V supply voltage and its power consumption changes between 137.4 and 156[math][math]W at the entire tuning range. For [math][math][math]A/V ([math][math]V) and for 0.6[math][math] input voltage, the simulation results show 6[math]dB reduction in the total harmonic distortion (THD) of proposed OTA when the MGTR linearization technique is used and 15[math]dB reduction when the tune-dependent body driving is also utilized. The proposed OTA is employed in a third-order low-pass Butterworth filter which is tunable from 2 to 18[math]MHz. The in-band IIP3 of filter is 16.9 and 12.4[math]dBm, respectively, for 2 and 18[math]MHz cutoff frequencies while the two-tone input voltage is applied at 1[math]MHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-29T08:21:23Z
      DOI: 10.1142/S0218126620501030
       
  • Multi-Objective Local Pollination-Based Gray Wolf Optimizer for Task
           Scheduling Heterogeneous Cloud Environment
    • Authors: M. Gokuldhev, G. Singaravel, N. R. Ram Mohan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The rebel of global networked resource is Cloud computing and it shared the data to the users easily. With the widespread availability of network technologies, the user requests increase day by day. Nowadays, the foremost complication in Cloud technology is task scheduling. The cargo position and arrangement of the tasks are the two important parameters in the Cloud domain, which can provide the Quality of Service (QoS). In this paper, we formulated the optimal minimization of makespan and energy consumption in task scheduling using Local Pollination-based Gray Wolf Optimizer (LPGWO) algorithm. In the hybrid concept, Gray Wolf Optimizer (GWO) algorithm and Flower Pollination Algorithm (FPA) are combined and used. In the presence of GWO, the best searching factor is used to increase the convergence speed and FPA is used to distribute the data to the next packet of candidate solution using local pollination concept. Chaotic mapping and OBL are used to provide a suitable initial candidate for task solutions. Therefore, the experiments delivered better task scheduling results in low and high heterogeneities of physical machines. Ultimately, the comparison with the simulation results had shown the minimum convergence speed of makespan and energy consumption.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-29T08:21:22Z
      DOI: 10.1142/S0218126620501005
       
  • Geometry-Based Crosstalk Reduction in CNT Interconnects
    • Authors: P. Uma Sathyakam, P. S. Mallick, Paridhi Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-22T03:47:51Z
      DOI: 10.1142/S0218126620500942
       
  • A Method for Human Gait Recognition from Video Streams Using Silhouette,
           Height and Step Length
    • Authors: Adnan Ramakić, Zlatko Bundalo, Dušanka Bundalo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes and presents one way for people recognition from video streams. People recognition can be realized using various biometric features, behavioral or physiological, and methods based on that features. This work proposes and describes an algorithm for people recognition from video streams that is composed of two modules, module for dataset creation and module for recognition. Module for dataset creation involves creation of various types of person images and parameters. Module for recognition includes multiple comparisons of the images and different parameters comparison. These parameters are average height and average step length of a person during a gait cycle. For experimental purposes, a dataset for 15 persons in gait is created using a long-range stereo camera in outdoor environment. The algorithm has high accuracy in people recognition and easily can be upgraded with additional steps and modules, so it is suitable for use in various applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-22T03:47:51Z
      DOI: 10.1142/S0218126620501017
       
  • An Application-Level Method of Arbitrary Synchronization Failure Detection
           in TTEthernet Networks
    • Authors: Xue Qian Tang, Qiao Li, Guangshan Lu, Huagang Xiong, Feng He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Precise distributed clock synchronization is important for Time-Triggered Ethernet (TTEthernet) in which fail-arbitrary synchronization failure cannot be treated by existed protocols unless every synchronization node is equipped with a dedicated clock monitoring. A novel method was presented to detect arbitrary synchronization failure by some application-level routines which make distributed decisions mainly by monitoring the protocol control frames (PCFs). An arbitrary failure node can be exactly detected and located by the routine resided on each of the Compression Masters based on the concerned accusation messages sent from Synchronization Masters or Synchronization Clients. The proposed method can make up the weak points on the detection of the arbitrary failure node of the existed fault-tolerant synchronization mechanism and enhance the synchronization node to resist the arbitrary failure for TTEthernet. By our SAL-based model checking, this method had been formally verified to have a fail-arbitrary detection capacity even in a standard integration configuration. Simulations imply that the quality of the whole clock synchronization is effectively improved after the failure node has been isolated.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-22T03:47:50Z
      DOI: 10.1142/S0218126620501029
       
  • Augmented Reality-Based Simulation of Some Basic Electrical Circuits Which
           Requires Oscilloscope for Analysis without Hardware
    • Authors: Mehmet Özüaǧ, İsmail Cantürk, Lale Özyilmaz
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This study aims to contribute to the electronics education through the use of Augmented Reality (AR) technology, and thus, limit the dependency on a physical environment and the equipment required for the experiments performed in electronics education. In this regard, an Augmented Reality-based mobile application (ARElectronicLab) has been designed to provide a technology–reality blended experience of electronic circuits in real physical life. This AR-based mobile application has been used to create simulations of diode clipper circuit and inverting operational amplifier circuit. The mobile application operates with a marker in real life and enables monitoring of 3D simulations of electronic components through a touch screen. Hence, the application offers a real-like experience and brings an innovative and enriching perspective into the electronics education.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-18T04:17:24Z
      DOI: 10.1142/S0218126620500966
       
  • In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling
           System on an FPGA
    • Authors: Minh Tung Dam, Van Toan Nguyen, Jeong-Gun Lee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a timing error predictor (TEP) for adaptive frequency scaling (AFS) is proposed on a field-programmable gate array (FPGA). The use of TEP-based AFS can minimize large timing margin which is added to a clock cycle time for tolerating process, voltage, and temperature (PVT) variations. On an FPGA, in general, the typical dynamic frequency scaling has used the feature of dynamic frequency synthesis (DFS) in a digital clock manager (DCM). However, it has a long locking time. Moreover, during the DCM reconfiguration for generating a new frequency, the lock signal of the DCM can be lost and it leads to possible glitches or spikes at the output. In this work, a variable-length ring oscillator (VLRO), which employs a high-speed carry chain in an FPGA, is proposed to replace the DCM for changing the frequency within one clock cycle without introducing any glitches. Furthermore, an in-situ TEP, which detects timing errors, is combined with VLRO to further reduce the timing margin of a target system. Our proposed in-situ TEP-based AFS scheme is applied to a [math]-bit multiplier and implemented on a Spartan-6 FPGA device (XFC6SLX45). The functional correctness of the TEP is verified under various DC supply voltages and operating frequencies. The experimental results show that the proposed TEP-based AFS system switches the clock frequency correctly within two clock cycles and improves circuit performance up to [math] the nominal operating condition by minimizing the timing margin.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-18T04:17:24Z
      DOI: 10.1142/S021812662050098X
       
  • A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP
           Reduction Circuitry
    • Authors: Chua-Chin Wang, Zong-You Hou, Deng-Shian Wang, Chia-Lung Hsieh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[math] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-18T04:17:24Z
      DOI: 10.1142/S0218126620500954
       
  • Design of a Bio-Inspired Embryonic Cellular Array Based on Bus Structure
    • Authors: Tao Wang, Jinyan Cai, Yafeng Meng, Meng Lv, Zexi Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      There are some shortcomings, such as huge hardware resource consumption, functional differentiation is difficult and limited fault detection coverage, when embryonic cellular array (ECA) is used to design large-scale circuit. In this paper, the structure characteristics and communication method of multicellular organism are analyzed briefly, and a new bio-inspired ECA based on bus structure (BECA) is proposed, besides that the corresponding self-repairing strategy is designed. First, the functional decomposition has been applied in BECA, which uses bus structure to realize internal communication. BECA consists of bus and electronic tissues (ET), which can be used to realize large-scale circuit. C17 circuit in ISCAS85 circuit library is chosen as experiment subject, and experiment simulation results indicate that BECA based on bus structure is suitable for large-scale circuit, and the faults occurred in ET can be repaired effectively. In order to research BECA from the mathematical point of view, the reliability evaluation model of BECA is established, which is based on [math]-out-of-[math] system reliability model. In addition, the hardware resource consumption model of BECA is established by analyzing the number of metal oxide semiconductor (MOS) transistors that ECA consumed. Based on BECA reliability and hardware resource consumption evaluation model, comparative experiment is studied, and the results indicate that the proposed ECA can improve the reliability of circuit and reduce hardware resource consumption effectively. Therefore, the BECA presented will play an important role in designing large-scale digital circuit with self-repairing ability.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-18T04:17:23Z
      DOI: 10.1142/S0218126620500991
       
  • Combinational Counters: A Low Overhead Approach to Address DPA Attacks
    • Authors: Ghobad Zarrinchian, Morteza Saheb Zamani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Differential Power Analysis (DPA) attacks are known as viable and practical techniques to break the security of cryptographic algorithms. In this type of attack, an adversary extracts the encryption key based on the correlation of consumed power of the hardware running encryption algorithms to the processed data. To address DPA attacks in the hardware layer, various techniques have been proposed thus far. However, current techniques generally impose high performance overhead. Especially, the power overhead is a serious issue which may limit the applicability of current techniques in power-constrained applications. In this paper, combinational counters are explored as a way to address the DPA attacks. By randomizing the consumed power in each clock cycle of the circuit operation, these counters can enhance the resistance of the cryptographic cores against DPA attacks with low power overhead as well as zero timing overhead. Experimental results for an AES S-Box module in 45[math]nm technology reveal that the proposed technique is capable of achieving higher level of security in comparison to two other approaches while preserving the power and performance overhead at a same or lower level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-17T08:24:28Z
      DOI: 10.1142/S0218126620500978
       
  • A Three-Stage Fuzzy-Logic-Based Handover Necessity Estimation and Target
           Network Selection Scheme for Next Generation Heterogeneous Networks
    • Authors: Meenakshi Subramani, Vinoth Babu Kumaravelu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The network performance is an imperative factor for the customers to select a mobile network operator (MNO). The customers demand seamless mobility and services with minimal packet loss and ultra-low latency from the subscribed MNO. Device-to-Device (D2D) communication is one of the key enabling solutions of fifth generation (5G), which has the potential to enhance throughput, latency, packet loss rate (PLR) performances of the network. 5G is expected to support high mobility and smaller range heterogeneous cells. This leads to frequent handovers. The unessential handovers may cause wastage of network resources. The improper network selection may prompt extreme quality degradation. In this work, a three-stage fuzzy-logic-based handover necessity estimation and target selection scheme is proposed for general heterogeneous networks. The simulation results prove that PLR, number of handovers executed and throughput performances of the proposed scheme are superior than the conventional and fuzzy-based multi-attribute decision-making (MADM) schemes. Even though this scheme is demonstrated for D2D application, it can be extended for any heterogeneous network scenarios.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-15T03:31:54Z
      DOI: 10.1142/S0218126620500929
       
  • Reduction of Power Electronic Devices in a Single-Phase Generalized
           Multilevel Inverter
    • Authors: Bidyut Mahato, Saikat Majumdar, Kartick Chandra Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Multilevel inverters (MLIs) emerged as a boon to the industries due to the fact that it fulfils different industrial aspects such as reduced electromagnetic interference, lower maintenance, less installation area and reduced harmonic content. MLI generates a staircase output voltage with suitable combination of power devices and DC voltage sources. In this work, a generalized cascaded MLI is proposed that employs only a half-bridge converter rather than the full H-bridge converter for the polarity-reversal (on which the maximum DC link voltage appears) and thereby also reduces the required number of power switches. Five different types of algorithm in the proposed configuration have been studied and the most optimal algorithm is further elaborated and implemented. A specimen 7-level inverter of the proposed configuration is modeled in MATLAB/Simulink and is further implemented in the laboratory using the controller DS1103. The experimental results for different modulation indices are further amalgamated and verified with the simulation results. Nevertheless, a comparative assessment of different performance-related parameters of the proposed topology along with the generalized expressions is carried out and are also compared with some of the recently published MLI topologies.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-09T07:00:12Z
      DOI: 10.1142/S0218126620500930
       
  • Kernel Fuzzy Clustering with Output Layer Self-Connection Recurrent Neural
           Networks for Software Cost Estimation
    • Authors: V. Resmi, S. Vijayalakshmi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In the current world, the software cost estimation problem has been resolved using various newly developed methods. Significantly, the software cost estimation problems can be dealt with effectively with the recently grown recurrent neural network (RNN) than the other newly developed methods. In this paper, an improved approach is proposed to software cost estimation using Output layer self-connection recurrent neural networks (OLSRNN) with kernel fuzzy c-means clustering (KFCM). The proposed OLSRNN method follows the basics of traditional RNN models for integrating self-connections to the output layer; thereby, the output temporal dependencies are better captured. Also, the performance of neural networks is improved using the kernel fuzzy clustering algorithm to enhance software estimation results. Ultimately, five publicly available software cost estimation datasets are adapted to verify the efficacy of the proposed KFCM-OLSRNN method using the validation metrics such as MdMRE, PRED (0.25) and MMRE. The experimental results proved the efficiency of the proposed method for solving the software cost estimation problem.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-05T09:02:03Z
      DOI: 10.1142/S0218126620500917
       
  • Decomposition-Based New Space Vector Modulation Algorithm for Three-Level
           Inverter with Various ADSVPWM Strategies
    • Authors: A. Suresh Kumar, K. Sri Gowri, M. Vijaya Kumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The three-level inverter is extensively preferred in medium-voltage industrial applications over the conventional inverter due to its benefits. The performance of inverter is better when the space vector modulation (SVM) approach is preferred. However, the implementation of conventional SVM approach is more complex. In this paper, a decomposition-based new SVM algorithm for three-level inverter is proposed to reduce computational complexity and implementation time using a low-cost digital controller. Initially, the performance of the proposed SVM algorithm is studied through MATLAB simulation using the conventional switching sequence 0127. Further enhancing the performance, the proposed algorithm is implemented with various advanced discontinuous SVPWM strategies using the advanced switching sequences of 1012–2721 and 0121–7212. The no-load motor current THD and switching loss analysis for ADSVPWM and conventional SVPWM strategies at different modulation indices are presented is this paper for a comparison point of view. The no load motor current THD results obtained through simulation are validated experimentally by implementing the proposed algorithm on real-time interface tool through dSPACE, which is used to control constant V/F-controlled three-level inverter-fed induction motor. Further to show the effectiveness of the proposed technique, the experimental investigation is done on induction motor at loaded condition and the results are presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-05T09:02:02Z
      DOI: 10.1142/S0218126620500905
       
  • Shunt Active Power Filter with Solar Photovoltaic System for Long-Term
           Harmonic Mitigation
    • Authors: P. Suresh, G. Vijayakumar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a shunt Active Power Filter (APF), supported by Solar Photovoltaic (SPV) system for a grid-connected application that improves power quality. The reference signal for the shunt APF is obtained from the adaptive Proportional Integrative Derivatives (PID), based on an algorithm of Least Mean Eighth (LME) with Unit Vector Template (UVT). The LME algorithm distinguishes the basic weight sections from load currents and estimates the three phase reference source current. These reference currents are used to generate a gate signal for the shunt APF. The DC-link voltage regulator is used to keep the constant DC-link voltage of the shunt APF with an APID controller. To reduce present distortions of electric power distribution systems, a design of a suitable controller is conducted using an intelligent computational technique for predicting the right reference signals. The SPV scheme is designed to obtain the highest energy output from the SPV panel with the maximum power point tracking algorithm (MPPT) scheme and is connected to the power grid. For long-term harmonic mitigation, the SPV system continuously maintains the DC-link of the shunt APF. Mathematically, the presented current reference signal generation scheme is examined and digital simulation outcomes are displayed under distinct steady and dynamic state conditions. Lastly, the complete scheme is validated by using the hardware prototype.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-02T01:53:10Z
      DOI: 10.1142/S0218126620500814
       
  • Feature Extraction Acceleration to Stabilize Execution Time for Real-Time
           Applications in Low-Cost Embedded Systems
    • Authors: Taek Kyu Kim
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Extracted features are widely used for image processing. Many research endeavors have been undertaken to extract significant features of fast moving images. Appropriate algorithm processing is necessary to extract features and provide features to the other modules in real time with low-cost embedded systems. The features from accelerated segment test (FAST) algorithm is renowned for feature extraction. FAST is composed of simple arithmetic operators. In this study, FAST is employed to implement the hardware accelerator in a field-programmable gate array for small embedded systems. Meanwhile, the threshold value in FAST affects the number of extracted features and the execution time. The precarious execution time makes it difficult for the system to schedule the timing of system functions and thus degrades the performance. An appropriate method is necessary to stabilize the execution time. A dynamic threshold controller in a FAST hardware accelerator is thus proposed to enable a stable execution time. A proportional integral controller composed of an adder, subtractor, and shifter is applied for low design implementation costs. The proposed approach occupies 2,263 slice flip-flops, 3,498 look-up tables, and 17 block RAMs in a Xilinx Virtex 5 FX field-programmable gate array. It requires 3.87 ms for continuous [math] images from the KITTI benchmark.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-07-02T01:53:08Z
      DOI: 10.1142/S0218126620200030
       
  • 2-GHz 2[math]VDD 28-nm CMOS Digital Output Buffer with Slew Rate
           Auto-Adjustment Against Process and Voltage Variations
    • Authors: Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U-Fat Chio, Wei Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A 2[math]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[math]GHz given 1.8/1.05[math]V supply voltage, namely, VDD or 2[math]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-27T08:20:14Z
      DOI: 10.1142/S0218126620500887
       
  • WBAT Job Scheduler: A Multi-Objective Approach for Job Scheduling Problem
           on Cloud Computing
    • Authors: B. Hariharan, D. Paul Raj
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The main objective of the proposed methodology is multi-objective job scheduling using hybridization of whale and BAT optimization algorithm (WBAT) which is used to change existing solution and to adopt a new good solution based on the objective function. The scheduling function in the proposed job scheduling strategy first creates a set of jobs and cloud node to generate the population by assigning jobs to cloud node randomly and evaluate the fitness function which minimizes the makespan and maximizes the quality of jobs. Second, the function uses iterations to regenerate populations based on WBAT behavior to produce the best job schedule that gives minimum makespan and good quality of jobs. The experimental results show that the performance of the proposed methods is better than the other methods of job scheduling problems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-27T08:20:13Z
      DOI: 10.1142/S0218126620500899
       
  • Design of Low-Power SoC for Wearable Healthcare Device
    • Authors: Ji Kwang Kim, Jung Hwan Oh, Gwan Beom Hwang, Oh Seong Gwon, Seung Eun Lee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In wearable devices, power consumption is a serious issue since wearable devices must maintain the power-on state at any time. In healthcare system, a variety of signal processing operations occupy a large portion of overall workload because it has periodic and heavy computational workloads. In this paper, we propose a low-power System on Chip (SoC) architecture for wearable healthcare devices. In order to reduce power consumption of processor, we design a hardware accelerator that handles signal processing and provides computation offloading. Furthermore, to minimize the area and maximize the performance of the accelerator, we optimize the operation bit-width by analyzing the frequency response. The low-power healthcare SoC was fabricated with 0.11[math][math]m CMOS process. Finally, we measured the power consumption of our chip and verified the applicability of the digital filter accelerator, which reduces the energy consumption for embedded processor.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-26T09:40:21Z
      DOI: 10.1142/S0218126620500851
       
  • An Ultra-Low Power Consumption High-Linearity Switching Scheme for SAR ADC
    • Authors: Yushi Chen, Yiqi Zhuang, Hualian Tang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-25T10:07:11Z
      DOI: 10.1142/S0218126620500863
       
  • Low-Energy Switching Method Based on Asymmetric Binary Search Algorithm
           for SAR ADCs
    • Authors: Weiyue Qu, Jinqiang Zhao, Zhaofeng Zhang, Niansong Mei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An area-efficient and low-energy switching method for the successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. Unlike most switching methods, the proposed switching method resolves the first three bits by using asymmetric binary search algorithm. Benefiting from the novel reference voltages – [math], [math](1/4[math]), ground, this proposed switching method achieves 87.5% area reduction and 98.71% energy reduction over the conventional method. Furthermore, it also achieves good linearity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-21T06:58:47Z
      DOI: 10.1142/S0218126620500875
       
  • Fractional-Order Dual-Slope Integral Fast Analog-to-Digital Converter with
           High Sensitivity
    • Authors: Bo Yu, Yi-Fei Pu, Qiu-Yan He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The dual-slope integral analog-to-digital converter is widely used in low-speed, high-precision measurement owing to its high precision and strong resistance on crosstalk interference. To meet the requirements of higher accuracy and faster measurement, the integral sensitivity and conversion speed of the dual-slope integral analog-to-digital converter must be improved. Therefore, based on fractional-order calculus, we propose a fractional-order dual-slope integral analog-to-digital converter. First, constant-current charging curves were provided to explain the source of the idea of the fractional-order dual-slope integral analog-to-digital converter. Then, the working principle of the fractional-order dual-slope integral analog-to-digital converter is described in detail. The calculation formula of analog-to-digital conversion is derived and analyzed. Moreover, the relationship of the voltage-measurement error with the operation-order error of the fractor and the reference voltage error is theoretically derived. Furthermore, we theoretically analyze the resistance of the proposed analog-to-digital converter to crosstalk interference, as well as the requirements for the first fractional integral time when crosstalk interference is suppressed. Specifically, we prove that the proposed analog-to-digital converter has a higher sensitivity and conversion speed than the classical converter, and we provide a quantitative calculation formula.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-17T06:06:00Z
      DOI: 10.1142/S0218126620500838
       
  • A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and
           Low-Noise Dynamic Comparator Technique
    • Authors: Daiguo Xu, Hequan Jiang, Dongbin Fu, Xiaoquan Yu, Shiliu Xu, Jun Yuan, Rongbin Hu, Can Zhu, Jianan Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[math]mW from 1[math]V power supply with a SNDR [math][math]dB and SFDR [math][math]dB. The proposed ADC core occupies an active area of 0.021[math]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-14T06:10:15Z
      DOI: 10.1142/S021812662050084X
       
  • High Stable and Low Power 8T CNTFET SRAM Cell
    • Authors: M. Elangovan, K. Gunavathi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [math], [math]) and Dual chiral value (NCNTFET with [math], [math] and PCNTFET [math], [math]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[math]nm CNTFET model in HSPICE simulation tool.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-14T06:10:14Z
      DOI: 10.1142/S0218126620500802
       
  • A Dynamic Channel Reservation Strategy Based on Priorities of
           Multi-Traffic and Multi-User in LEO Satellite Networks
    • Authors: Juan Wang, Lijuan Sun, Jian Zhou, Chong Han
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In Low Earth Orbit (LEO) satellite networks, it is a challenge to allocate the limited resources to meet the needs of different calls. In this paper, a dynamic channel reservation strategy based on priorities of multi-traffic and multi-user in LEO satellite networks is proposed. The dynamic admission threshold reserved for different calls is the key of this strategy. Firstly, the traffic prediction model based on LEO satellite mobility is established. Then the channel allocation model is built on the Markov process. Finally, the reserved admission thresholds are dynamically changed according to the predicted traffic. And the calculation of the admission thresholds is solved by the genetic algorithm. The simulation results show that the proposed strategy not only meets the needs of calls of different type traffic and different level users, but also improves the overall quality of service in LEO satellite networks.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-14T06:10:13Z
      DOI: 10.1142/S0218126620500826
       
  • Special Issue on Design, Technology, and Test of Integrated Circuits and
           Systems
    • Authors: Alberto Bosio, Mario Barbareschi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.

      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-10T09:06:28Z
      DOI: 10.1142/S0218126619020018
       
  • Reversible Circuits Synthesis from Functional Decision Diagrams by using
           Node Dependency Matrices
    • Authors: Suzana Stojković, Radomir Stanković, Claudio Moraga, Milena Stanković
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Decision diagrams are a data structure suitable for reversible circuit synthesis. Functional decision diagrams (FDDs) are particularly convenient in synthesis with Toffoli gates, since the functional expressions for decomposition rules used in them are similar to the functional expressions of Toffoli gates. The main drawback of reversible circuit synthesis based on decision diagrams is the usually large number of ancilla lines. This paper presents two methods for the reduction of the number of ancilla lines in reversible circuits derived from FDDs by selecting the order of implementation of nodes. In the first method, nodes are implemented by levels, starting from the bottom level to the top. The method uses appropriately defined level dependency matrices for choosing the optimal order of implementation of nodes at the same level. In this way, the optimization is performed level by level. The second method uses a diagram dependency matrix expressing mutual dependencies among all the nodes in the diagram. This method is computationally more demanding than the first method, but the reductions of both the number of lines and the Quantum cost of the circuits are larger.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-10T07:07:56Z
      DOI: 10.1142/S0218126620500796
       
  • On the Diminished-1 Modulo 2[math] Addition and Subtraction
    • Authors: Constantinos Efstathiou, Kiamal Pekmestzi, Nikolaos Moshopoulos
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, the design of the diminished-1 modulo [math] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [math] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-06T10:36:22Z
      DOI: 10.1142/S0218126620300056
       
  • A 5.8 GHz Low-Power Energy Harvester for RF Wireless Power Transfer
           Systems
    • Authors: Mariem Kanoun, David Cordeau, Jean-Marie Paillot, Hassene Mnif, Mourad Loulou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the design and implementation of an RF energy harvester system at 5.8[math]GHz for low-power wireless transmission applications. The potential application of the proposed system is to wirelessly power sensor nodes. First, a design methodology of the rectifier based on a theoretical approach is presented. The simulation results show an excellent correlation with the theoretical ones, proving the accuracy of the proposed design methodology. A prototype is fabricated and the simulation results are validated by the measurements. Then, the rectenna is combined to a commercial power management circuit and a load which emulates the behavior of a sensor. The power management circuit boosts and regulates the output DC voltage as well as stores the collected energy into a capacitor. Finally, the complete system is experimentally tested and excellent performances are demonstrated. The efficiency of the RF energy harvester is 24% at [math]10[math]dBm input power and 47% at [math]5[math]dBm input power which are the highest reported measured efficiencies at this frequency and at those power levels. The complete rectenna system is able to harvest 4.62[math]mJ in 40 s and 192[math]s for [math]6[math]dBm and [math]10[math]dBm input power, respectively allowing us to power wirelessly low-power electronic devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-06T10:36:21Z
      DOI: 10.1142/S0218126620500760
       
  • A High Throughput and Pipelined Implementation of the LUKS on FPGA
    • Authors: Xiaochao Li, Kongcheng Wu, Qi Zhang, Shaoyu Lin, Yihui Chen, Shen Yuong Wong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The Linux Unified Key Setup (LUKS) is the standard key management scheme for the full disk encryption solution implemented in Linux-based operating systems. It is composed of PBKDF2, an anti-forensic splitter, and a cipher. In this paper, a new FPGA-based high-throughput and pipelined implementation of LUKS is presented. We design a four-stage pipelined SHA-1 module without the multiplexers between piecewise function and a total eight-stage pipelined PBKDF2 by reusing two hash results. Besides, we implement ST box-based AES decipher with BRAM resources, which improves the performance and leaves most of the slice resources to PBKDF2 architecture. By using the above techniques, we instantiate a high throughput LUKS co-processor in a Xilinx Zynq 7030 FPGA. Compared to the previous work of implementation of LUKS PBKDF2 with AES on FPGA, our design shows better improvement of the speed and efficiency by 16 times and 8 times, respectively. Our speed of LUKS key recovery is even faster than Nvidia GPU GTX480.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-06T10:36:21Z
      DOI: 10.1142/S0218126620500759
       
  • Minimum Component All Pass Filters Using a New Versatile Active Element
    • Authors: Mohammad Faseehuddin, Jahariah Sampe, Sadia Shireen, Sawal Hamid Md Ali
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35[math][math]m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-04T07:33:41Z
      DOI: 10.1142/S0218126620500784
       
  • 2.2–4.6-GHz Active Quasi-Circulator with [math] 24-dB
           Transmit–Receive Isolation
    • Authors: Najam Muhammad Amin, Lianfeng Shen, Danish Kaleem, Zhi-Gong Wang, Keping Wang, Faisal Siddiqui, Rana Saeed, Haroon Rasheed, Burhan Ahmed
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-[math]m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of [math] dB between transmitter-to-antenna ports ([math]) and of [math] dB between antenna-to-receiver ports ([math]), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ([math]) is better than 24 dB with a maximum value of 29.5[math]dB @ 3.6[math]GHz. The power dissipation of the proposed AQC is 40[math]mW and it covers an active chip area of 0.677[math]mm2.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-06-04T07:33:40Z
      DOI: 10.1142/S0218126620500772
       
  • Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator
           on Flexible Hardware for a Flash ADC
    • Authors: Ashima Gupta, Anil Singh, Alpana Agarwal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180[math]nm CMOS technology with 1.8[math]V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43[math]dB, 25.2[math]dB and 30.1[math]dB, respectively at 33.20[math]MHz input frequency and 200[math]MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14[math]mW. The calculated value of DNL and INL is [math] LSB and [math] LSB respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-30T02:45:34Z
      DOI: 10.1142/S0218126620500735
       
  • SPV-Based UPQC with Modified Power Angle Control Scheme for the
           Enhancement of Power Quality
    • Authors: A. Gowrishankar, M. Ramasamy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Unified Power Quality Conditioner (UPQC) with a modified Power Angle Control (PAC) scheme is presented for effective interconnection of renewable energy system into the grid. The UPQC consists of both shunt and series Active Power Filters (APFs). The shunt and series APF is one of the most effective custom power devices, which provides compensation for current and voltage-based disturbances, respectively. The shunt APF supplies active power to the load from the Distributed Generation (DG) in addition to reactive power demand supplied by it. Because of this functionality, the Volt–Ampere (VA) burden increases along with the rating of the shunt inverter. The PAC scheme aims to effective utilization of series and shunt APFs through sharing of reactive power to reduce VA burden on shunt APF. The PAC scheme is based on Synchronous Reference Frame (SRF) theory, which has simple computations, is robust and uses existing measurements of Solar Photovoltaic (SPV)-integrated UPQC. The performance of the proposed SPV-integrated UPQC is verified with the manifestation of nonlinear loads and reactive burdens with the SPV power generating system. The dynamic performance of the PV-UPQC is verified under the grid disturbances such as voltage sag, swell, varying load and change in solar irradiation. The effectiveness of the proposed control scheme is evaluated through the digital simulation and hardware experimental prototype model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-30T02:45:34Z
      DOI: 10.1142/S0218126620500644
       
  • Scalable Anomaly Detection for Large-Scale Heterogeneous Data in Cloud
           Using Optimal Elliptic Curve Cryptography and Gaussian Kernel Fuzzy
           [math]-Means Clustering
    • Authors: P. Santhosh Kumar, Latha Parthiban, V. Jegatheeswari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In most systems, a smart functionality is enabled through an essential vital service such as detecting anomalies from complex, large-scale and dynamic data. However, ensuring the privacy and security for the cloud data is the most crucial and challenging task in the present world. Moreover, it is important to safeguard the security of sensitive data and its privacy from unauthorized parties who are trying to access the data. Therefore, to accomplish this task, several encryption, decryption and key generation mechanisms were introduced in the existing works for privacy preserving in cloud platform. But, there still remain open issues such as increased communication overhead, reduced security and increased time consumption. Also, these existing works followed the symmetric key cryptographic mechanism for privacy preservation of data; hence, a single secret key is shared by several users for accessing the original data. Due to this fact, a high security risk arises and it allows unauthorized parties to access the data. Thus, this work introduces a cloud-based privacy preserving model for offering a scalable and reliable anomaly detection service for sensor data through holding the benefits of cloud resources. Also, this paper aims to impose a newly developed Elliptic Curve Cryptography-based Collective Decision Optimization (ECDO) approach over the proposed framework for improving the privacy and security of the data. Furthermore, to perform the data clustering computation we used the Gaussian kernel fuzzy [math]-means clustering (GKFCM) algorithm within the cloud platform, especially for data partitioning and to classify the anomalies. Thus, the computational difficulties are limited by adopting this suitable privacy preserving model which collaborates a private server and a set of public servers through a cloud data center. Moreover, on encrypted data the granular anomaly detection operations are performed by the virtual nodes executed over public servers. Experimental validation was performed on four datasets resulting from Intel Labs publicly available sensor data. The experimental outcomes demonstrate the ability of the proposed framework in providing high anomaly detection accuracy without any degradation in data privacy.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-27T06:55:57Z
      DOI: 10.1142/S0218126620500747
       
  • A Communication Model Framework for Electric Transmission Line Monitoring
           Using Artificial Bee Colony Algorithm
    • Authors: C. Jeyanthi, H. Habeebullah Sait, K. Chandrasekaran, C. Christopher Columbus
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The natural calamity and physical malfunction in the overhead transmission line cause bad impact on the networks such as mechanical failures, power losses, reduction of line capacity, and voltage drop. These adverse impacts can be reduced by implementing proper monitoring systems. Wireless sensor network is an apt mechanism to monitor the overhead transmission network because of its physical configuration. This paper portrays the communication between wireless sensor networks and central data processing station. Cellular communication can directly transmit information through an assisted cellular module (CM) based on the probability of cellular coverage. In this paper, one of the modern optimization techniques, i.e., artificial bee colony algorithm, is used to study the problem of CM placement of cellular communication. By using this algorithm, the optimal number and location of the CMs for a test system varied from 10 to 100 are determined. A novel optimal link path scheme is proposed to check the condition of the required quality of services of both cellular/ZigBee users. The attained results show that the methodology is best suited to acquire low cost solution for the cellular module placement problem.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-23T08:49:10Z
      DOI: 10.1142/S0218126620500632
       
  • A Multi-Layer Self-Healing Algorithm for WSNs
    • Authors: Sergio Diaz, Diego Mendez, Rolf Kraemer
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The implementation of Wireless Sensor Networks (WSNs) is a challenging task due to their intrinsic characteristics, e.g., energy limitations and unreliable wireless links. Considering this, we have developed the Disjoint path And Clustering Algorithm (DACA) that combines topology control and self-healing mechanisms to increase the network lifetime with minimum loss of coverage. Initially, DACA constructs a tree that includes all nodes of the network by using the Collection Tree Protocol (CTP). This tree is an initial communication backbone through which DACA centralizes the information. Then, DACA builds a set of spatial clusters using Kmeans and selects the Cluster Heads (CHs) using Particle Swarm Optimization (PSO) and a multi-objective optimization (MOO) function. Subsequently, DACA reconstructs the tree using only the CHs. In this way, DACA reduces the number of active nodes in the network and saves energy. Finally, DACA finds disjoint paths on the reconstructed tree by executing the N-to-1 multipath discovery protocol. By doing so, the network can overcome communications failures with a low control message overhead. The simulations on Castalia show that DACA considerably extends the network lifetime by having a set of inactive nodes and disjoint paths that support the communication when active nodes die. Besides, DACA still maintains a good coverage of the area of interest despite the inactive nodes. Additionally, we evaluate the shape of the tree (i.e., the average number of hops) and the risk of connection loss of the network.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:17:01Z
      DOI: 10.1142/S021812662050070X
       
  • An Elephant Herding Optimization Algorithm-Based Static Switched Filter
           Compensation Scheme for Power Quality Improvement in Smart Grid
    • Authors: S. Mani Kuchibhatla, D. Padmavathi, R. Srinivasa Rao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Power quality (PQ) issue is referred to as any problem that exposes in the voltage and current or in frequency value that causes a malfunction of protection devices or maloperation of the system. The improvement of the PQ is important at the load side when the production processes get more complicated and require a bigger liability level. An Elephant Herding Optimization (EHO) algorithm is presented for improving the PQ and reducing the harmonic distortion using the Static Switched Filter Compensation (SSFC) in Photovoltaic (PV) interconnected wind energy conversion system (WECS). The novelty of the proposed system is enhancing the performance of the grid-connected hybrid energy system such as stabilizing the voltage, reducing the power loss and mitigating the harmonic distortion using the SSFC. Here, the proposed controller is used to optimize the control pulses for SSFC. The SSFC and voltage-source converters with smart dynamic controllers are emerging as stabilization and power filtering equipment to improve the PQ. The proposed method has implemented in MATLAB/Simulink platform and their performances are evaluated and contrasted with the existing technologies such as Bat algorithm (BA) and Firefly algorithm (FA) techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:17:00Z
      DOI: 10.1142/S0218126620500668
       
  • Enhanced Buck-Boost dc–dc Converter with Positive Output Voltage
    • Authors: Hossein Ajdar Faeghi Bonab, Mohamad Reza Banaei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new transformerless buck-boost converter is presented. The voltage gain of the converter is higher than the classic boost converter, classic buck-boost converter, CUK and SEPIC converters. The proposed converter advantage is buck-boost capability. The proposed converter topology is simple; therefore, the converter control is simple. The converter has one main switch. Hence, the switch with low switching and conduction losses can be used. The stress of the main switch is low; therefore, switch with low on-state resistance can be selected. The principles of the converter and mathematic analyses are presented. The validity of the accuracy of calculations is verified by the experimental results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:17:00Z
      DOI: 10.1142/S0218126620500723
       
  • A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability
    • Authors: S. R. Mansore, R. S. Gamad, D. K. Mishra
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[math]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[math] and 1.06[math] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[math]V. Write static noise margin (WSNM) of the proposed design is 1.65[math], 1.71[math] and 1.77[math] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[math] and 0.81[math] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[math] lesser read power as compared to PPN10T cell at 0.4[math]V. Leakage power of the proposed cell is 0.35[math] of C6T cell at 0.4[math]V. Proposed 11T cell occupies 1.65[math] larger area as compared to that of conventional 6T.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:16:59Z
      DOI: 10.1142/S021812662050067X
       
  • Designing a New Scalable Autoconfiguration Protocol with Optimal Header
           Selection for Large Scale MANETs
    • Authors: Rajula Angelin Samuel, D. Shalini Punithavathani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Autoconfiguration in mobile ad hoc network (MANET) is a challenging task to be accomplished in hostile environment. Moreover, a mobile node in MANET is usually configured with a unique IP address for providing better communication and to connect it with an IP network. Essentially, the nodes in wired networks are autoconfigured using a commonly known Dynamic Host Configuration Protocol (DHCP) server. However, MANET exhibits the intrinsic characteristics (i.e., distributed, dynamic and multi-hop) in nature; hence, it is hard to adopt DHCP server for autoconfiguration of nodes in MANET without applying significant modifications in auto-configuration scheme. This paper proposes an efficient IPV6 Duplicate address Elimination Autoconfiguration protocol for MANETs (IDEAM) which comprises the member and the cluster head (CH) nodes organized in a hierarchical fashion. Further, the proposed protocol considers the global connectivity exhibiting reduced communication overhead among the nodes. Initially, our proposed auto-configuration protocol encourages the Duplicate Address Detection (DAD) operation by selecting a controller node from the prefixed group members using a joining node in the network. In other words, the DAD operation is performed perfectly by a selected controller node on behalf of the new joining node. Thus, our proposed protocol becomes more effective and behaves better in the minimization of overhead by considerably eliminating the DAD messages broadcast in the network. Also, we imposed a new Flower pollination based gray wolf optimization (FPGWO) algorithm for selecting an optimal header among the group members by considering various node parameters (i.e., node location, resources and node density) to avoid unnecessary broadcasting of additional weight messages about each node in the network. The simulation results proved the efficiency of our proposed protocol in terms of scalability and in the minimization of overhead. Also, an effectual method provided by our proposed approach enhances the activity of marginal nodes over the group for healing the network that degrades its performance followed by the splitting and merging operation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:16:57Z
      DOI: 10.1142/S0218126620500681
       
  • Design of Current Differencing Transconductance Amplifier using a Novel
           Approach of Transconductance Boosting for High Frequency Applications
    • Authors: Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces a novel approach of transconductance boosting for current differencing transconductance amplifier (CDTA). Generally, the variation in the transconductance is achieved by changing the bias current and/or by increasing the aspect ratios of differential pair MOSFETs. These techniques of transconductance variations suffer from several serious drawbacks which include higher power dissipation, limited range of transconductance gain and lower input/output swing. The proposed approach of transconductance boosting overcomes these drawbacks at certain extent and also provides a high value of transconductance gain with acceptable range of bandwidth and power dissipation. It includes two different techniques to make it more effective for transconductance boosting. In the first technique, common source amplifiers have been used between gate and source terminals of the differential pair MOSFETs whereas in the second technique the concept of partial positive feedback is utilized. Using this approach, a new structure of CDTA namely cross-coupled common source current differencing transconductance amplifier I (CCCS-CDTA I) is proposed. To further improve the transconductance gain of CCCS-CDTA I, another structure CCCS-CDTA II is also proposed, in which the differential pair MOSFETs are replaced by two networks of “n” parallel MOSFETs having same aspect ratios. The proposed CCCS-CDTAs are simulated in Mentor Graphics Eldo simulator using TSMC 0.18[math][math]m process parameters. To confirm the performance of CCCS-CDTA II, physical layout and post-layout simulation results have been presented using Mentor Graphics Calibre tool. The advantages of proposed CCCS-CDTAs have also been discussed by realizing KHN filters and oscillators.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:16:56Z
      DOI: 10.1142/S0218126620500656
       
  • Quantum Ternary Multiplication Gate (QTMG): Toward Quantum Ternary
           Multiplier and a New Realization for Ternary Toffoli Gate
    • Authors: Asma Taheri Monfared, Majid Haghparast
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:16:56Z
      DOI: 10.1142/S0218126620500711
       
  • Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based
           Methodology
    • Authors: Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3[math][math][math]to 9[math][math][math]speedups.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:16:55Z
      DOI: 10.1142/S0218126620500577
       
  • Design and Realization of Current-Fed Single-Input Dual-Output
           Soft-Switched Resonant Converter
    • Authors: Naresh Kumar Reddi, M. R. Ramteke, H. M. Suryawanshi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new single-input dual-output [SIDO] soft-switched resonant full-bridge converter, which has asymmetrical structures for the isolated multiple outputs. The proposed structure is capable of supplying different loads having dissimilar voltage-current characteristics and independent of each other. This converter features wide range of zero current switching (ZCS) turn-off and automatic load-voltage regulation. In automatic load-voltage regulation, converter maintains constant voltage without the need of change in frequency or duty ratio during load change. First, the modes of converter operation are explained and then design of key parameters have been outlined. A laboratory prototype for 380[math]V, 500[math]W as main output and 24[math]V, 50[math]W as auxiliary output for an input voltage range of 40–50[math]V was built-up and tested. Experimental results confirm the viability of voltage regulation, ZCS and power efficiency of the proposed converter.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-16T07:16:54Z
      DOI: 10.1142/S0218126620500693
       
  • A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger
    • Authors: Yasin Bastan, Parviz amiri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[math]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[math][math]m CMOS process. The proposed circuit occupies only [math][math][math]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[math]mV and consumes only 6.64[math]nW power.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-13T02:31:55Z
      DOI: 10.1142/S0218126620200029
       
  • Wideband Input Matching CMOS Low-Noise Amplifier with Noise and Distortion
           Cancellation
    • Authors: Asieh Parhizkar Tarighat, Mostafa Yargholi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a wideband low-noise amplifier (LNA) is designed based on the resistive feedback topology with a TSMC 0.18[math][math]m standard RF CMOS process. Bandwidth expansion is provided by the second-order Chebyshev filter. The noise figure (NF) increases at high frequency because of the source parasitic capacitors of the cascode transistor; so, noise cancelling technique is applied to the cascode transistor of the proposed LNA. Bias conditions and sizes of the transistors are optimized to cancel the nonlinear transconductance ([math]). With this modified technique, low noise figure, high linearity and improved input and output matching can be attained for 3.1–10.6[math]GHz frequency band. Post-layout simulation result of the proposed LNA shows the maximum power gain of 17[math]dB at 5.5[math]GHz frequency, NF of lower than 4.5[math]dB over the whole band of 3.1–10.6[math]GHz, maximum IIP2 of [math]28[math]dBm and IIP3 of [math]7.5[math]dBm, while dissipating 9[math]mW (with buffer) from a 1.8 V supply voltage. It occupies [math]m silicon die area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-13T02:31:54Z
      DOI: 10.1142/S0218126620500590
       
  • A Hybrid-Countermeasure based Fault-Resistant AES Implementation
    • Authors: Noura Benhadjyoussef, Mouna Karmani, Mohsen Machhout, Belgacem Hamdi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-10T03:25:01Z
      DOI: 10.1142/S0218126620500449
       
  • A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal
           Blood Cell Levels
    • Authors: R. Nagulapalli, K. Hayatleh, S. Barker, A. A. Tammam, F. J. Lidgey, N. Yassine
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter-Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65-nm CMOS technology and post-layout simulations show 15.25-aF sensitivity. The total circuit occupies 2,184-[math]m2 silicon area and consumes 216[math][math]A from a 1-V power supply.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-10T03:25:01Z
      DOI: 10.1142/S0218126620500619
       
  • A New and Generalized MLI with Overall Lesser Power Electronic Devices
    • Authors: Bidyut Mahato, Saikat Majumdar, Kartick Chandra Jana
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Reduction in the overall power devices such as power semi-conductor switches, gate drivers with the associated circuits and DC voltage sources reduces the size, cost, complexity in addition with enhancing the overall performance of the inverter. This paper presents a new and generalized multilevel inverter topology with reduced number of power components. To identify the significance of proposed inverter, the generalized formulae for all the parameters are calculated and a comprehensive comparison of different performance parameters are presented in tabular as well as in graphical form. Multicarrier pulse width modulation strategy is adopted for generating the switching pulses. Simulation of the proposed MLI topology for the 9-level and 17-level inverter have been performed in MATLAB/Simulink and the corresponding experimental results are incorporated for one unit and two units, respectively, experiments are carried out at RL load. Nevertheless, level per switch Ratio (L/S) is introduced and compared with some of the new discussed MLI topologies. Moreover, the switching and the conduction losses of the inverter are also calculated and incorporated in this paper.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-10T03:25:00Z
      DOI: 10.1142/S0218126620500589
       
  • Adaptive Fuzzy-Based IRFOC of Speed Sensorless Six-Phase Induction Motor
           Drive System
    • Authors: Zakaria Elbarbary, Mohammad Fazle Azeem, Haitham Z. Azazi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent times, instead of three-phase induction motors (IM), multi-phase motors have been used in several applications, due to numerous advantages that they offer. Elimination of mechanical position or speed sensors allures for adjustable speed drives of IM. It leads to cost reduction, lesser maintenance and increased reliability of the motor drive. To eliminate the speed sensor, the rotor speed is estimated from measured stator currents and voltages at motor terminals. This paper proposes a scheme based on speed estimation method using Model Reference Adaptive System (MRAS) in conjunction with Adaptive Fuzzy Knowledge Based Controller (AFKBC) to improve the performance of a sensorless Indirect Rotor Field Oriented Control (IRFOC) of six-phase IM drive. AFKBC allows to operate at various operating conditions. A fitness function is defined for Queen Bee-based Genetic Algorithm (QBGA) to tune the scaling factor of AFKBC which improves the transient and steady state performances. The performance of the proposed scheme is evaluated by simulation on Matlab/Simulink package. The results of the proposed scheme are compared with conventional PI-based speed controller of the drive system. The proposed controller scheme improves the performance of the drive system at various operating conditions. The estimated speed algorithm gives good correlation between estimated and actual motor speed. The simulation results also illustrate that proposed scheme is robust and suitable for high performances six-phase IM drive.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-10T03:24:59Z
      DOI: 10.1142/S0218126620500620
       
  • Design of Wide Bandwidth, High-CMRR Voltage and Transadmittance-Mode
           Instrumentation Amplifier Using a Single CBTA
    • Authors: Mehmet Sagbas, Umut Engin Ayten
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, a high-performance voltage and current output instrumentation amplifier circuit is proposed. The proposed circuit also has voltage-mode (VM) and transadmittance-mode (TAM) outputs at a time. It employs a single current backward transconductance amplifier (CBTA) and a grounded resistor. It has the advantage of having low input and high output impedances which makes it easy for cascadability. The presented circuit has electronically tunable property due to the bias current of the CBTA. The validity of the proposed circuit is demonstrated by PSPICE simulations using a 0.18[math][math]m CMOS process with [math][math]V supply voltage. Simulation results show that the proposed circuit has a high common mode rejection ratio (CMRR), wide bandwidth, low offset and high gain properties.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-10T03:24:59Z
      DOI: 10.1142/S0218126620500607
       
  • An Enhanced Evolutionary Technique for the Generation of Compact
           Reconfigurable Scan-Network Tests
    • Authors: Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Nowadays, many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behavior, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Post-processing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploration.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-05-06T08:04:03Z
      DOI: 10.1142/S0218126619400073
       
  • Run-Time Deep Learning Enhanced Fast Coding Unit Decision for High
           Efficiency Video Coding
    • Authors: Xin Li, Na Gong
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The state-of-the-art high efficiency video coding (HEVC/H.265) adopts the hierarchical quadtree-structured coding unit (CU) to enhance the coding efficiency. However, the computational complexity significantly increases because of the exhaustive rate-distortion (RD) optimization process to obtain the optimal coding tree unit (CTU) partition. In this paper, we propose a fast CU size decision algorithm to reduce the heavy computational burden in the encoding process. In order to achieve this, the CU splitting process is modeled as a three-stage binary classification problem according to the CU size from [math], [math] to [math]. In each CU partition stage, a deep learning approach is applied. Appropriate and efficient features for training the deep learning models are extracted from spatial and pixel domains to eliminate the dependency on video content as well as on encoding configurations. Furthermore, the deep learning framework is built as a third-party library and embedded into the HEVC simulator to speed up the process. The experiment results show the proposed algorithm can achieve significant complexity reduction and it can reduce the encoding time by 49.65%(Low Delay) and 48.81% (Random Access) on average compared with the traditional HEVC encoders with a negligible degradation (2.78% loss in BDBR, 0.145[math]dB loss in BDPSNR for Low Delay, and 2.68% loss in BDBR, 0.128[math]dB loss in BDPSNR for Random Access) in the coding efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-30T08:49:53Z
      DOI: 10.1142/S0218126620500462
       
  • Implementation of Modified Field-Oriented Control Scheme for Improving the
           Fault Ride Through Ability of BDFIG System
    • Authors: Maheswari Muthusamy, A. K. Parvathy
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper devises a design named brushless doubly fed induction generator (BDFIG) with a fault ride-through enhancement that employs upgraded field-oriented control (FOC) scheme. The DFIG is most suitable for wind energy conversion system (WECS) because it has an amicable establishment, economical operation and promising characteristics. A WECS based on two BDFIGs connected electrically in parallel and mechanically in series, excited by a three-phase inverter and controlled as variable speed, is described. For enhancing power quality and power flow capability, static compensator (STATCOM) has been incorporated in the proposed configuration. The comparative analysis on performance has been carried out with the existing proportional-integral (PI) controller and self-tuning fuzzy logic controller (STFLC) for the proposed configuration under varying wind speed. In this paper, the fuzzy controller is designed to adapt PI parameters Kp and Ki, in order to reduce at least some inherent characteristics (overshoot, response time, etc.) of the error between the reference and system response. The digital simulation results claim that the FLC-based controller can offer an attractive and feasible control for the proposed WECS integrating two BDFIGs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-30T08:49:53Z
      DOI: 10.1142/S0218126620500401
       
  • Toward a Unified Performance Metric for Benchmarking Steganography Systems
    • Authors: Tamer Rabie, Mohammed Baziyad, Talal Bonny, Raouf Fareh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent advances in network speeds for exchanging multimedia data over insecure networks has resulted in an increased interest in steganography techniques. These techniques are usually evaluated based on their performance in three attributes; namely, capacity, imperceptibility, and robustness. Each of these attributes has its own measurement metric. Hence, comparing two different steganography schemes based on these individual metric tools becomes inconsistent. In this paper, a novel measurement metric tool is introduced for benchmarking steganography schemes. This new tool, named the “Combined Capacity-Quality-Robustness Effectiveness” (CCQRE) metric, combines the three opposing attributes of a steganography system into one conglomerate performance measure. Comparative results demonstrate the effectiveness of the proposed CCQRE metric for benchmarking various steganography schemes based on the researcher’s interest in capacity, imperceptibility, or robustness.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:39Z
      DOI: 10.1142/S0218126620500425
       
  • SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support
    • Authors: Petr Fišer, Ivo Háleček, Jan Schmidt, Václav Šimek
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one or enumerate all optimum implementations, while the allowed target gate types and gates costs can be arbitrarily specified. Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable of performing two or more different intended functions, depending on instantaneous conditions in the target operating environment. In this paper we propose the first method ever, generating provably size-optimal polymorphic circuits. Scalability and feasibility of the method are documented by providing experimental results for all NPN-equivalence classes of four-input functions implemented in AND–Inverter and AND–XOR–Inverter logics without polymorphic behavior support being used and for all pairs of NPN–equivalence classes of three-input functions for polymorphic circuits. Finally, several smaller benchmark circuits were synthesized optimally, both in standard and polymorphic logics.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:38Z
      DOI: 10.1142/S0218126619400103
       
  • An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit
           Asynchronous SAR Quantizer for Medical Applications
    • Authors: Sahel Javahernia, Esmaeil Najafi Aghdam, Pooya Torkzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [math] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[math][math]m CMOS technology achieves 95.98[math]dB peak signal-to-noise and distortion (SNDR) for 10[math]KHz signal bandwidth and dissipates 44[math][math]w while its FOM is obtained about 43 fJ/conv.-step.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:38Z
      DOI: 10.1142/S0218126620500565
       
  • Termination Transformation Theorem for Microwave Power Transfer Networks
    • Authors: Ramazan Kopru
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Termination transformation theorem (TTT) proposed in this work transforms a doubly complex terminated microwave power transfer network (PTN) to an equivalent doubly resistively terminated termination transformed network (TTN) which is essentially a filter network. In this work, the transducer power gain (TPG) formula, Tgen, based on S and transmission (ABCD) parameters for the PTN have been restudied from the classical literature. Then, a new TPG formula, Tgen1, based on the newly proposed TTT has been derived using the transformed TTN network. To be able to show the validity of the proposed TTT, the newly derived TPG formula Tgen1 and the classical TPG formula Tgen have been computed within the scope of an example PTN design. The theorem has been proved mathematically, and experimentally as well with the aid of a Matlab code. The performance plots yielded from the Matlab code have clearly shown that both TPG formulae, i.e., Tgen and Tgen1, are in complete agreement with each other. In that sense, the proposed TTT might be considered as an alternative and helpful technique to be used in microwave engineering.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:37Z
      DOI: 10.1142/S0218126620500437
       
  • Emulating the Statistical Properties of Indoor Power Line Colored
           Background Noise for Development of a Power Line Noise Simulator
    • Authors: Rubi Baishya, Banty tiru, Utpal Sarma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper deals with the development of a realistic power line channel simulator wherein power line communication devices can be tested before implementation to meet the massive need of data transfer. The statistics of the noise follow the experimentally observed in different sites, namely the time-varying non-white power spectral densities (PSDs) of the background noise and a target non Gaussian amplitude distribution. The procedure based on the inverse cumulative distribution function method of generation of random numbers and iteratively updating a target spectrum necessitates knowledge of a maximum of 17 parameters for successful implementation and has been validated for three sites in the low-frequency ([math]500[math]kHz) and high-frequency (1–30[math]MHz) bands. The average percentage errors in prediction of the mean of the channel capacity (CC) are 12.68% and 10.66% in the two bands, respectively. The minimum correlations of the distribution of BER of OFDM in a channel corrupted by the simulated and observed noises are is 0.883 and 0.801 in the two bands which are high compared to 0.422 and 0.355, respectively, when the requirement of a target amplitude distribution is neglected. With low-frequency noise emulated by a data acquisition card, an average percentage error of 11.82% in the CC and a correlation of 0.867 (against 0.498) in BER are obtained. The noise thus generated can be used as a testbed for system testing, instead of the conventional static models (additive white Gaussian noise or with time-invariant colored PSD), leading to better optimization of the implemented devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:36Z
      DOI: 10.1142/S0218126620500553
       
  • Design and Analysis of Inset Fed Wide-Band Rectenna with Defected Ground
           Structure
    • Authors: Asmita Rajawat, P. K. Singhal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The design proposed and fabricated in this paper is a slotted wide-band rectenna with the inclusion of Defected Ground Structure (DGS) which can harvest RF energy in the frequency range of 5.336–6.194[math]GHz with a center frequency of 5.8[math]GHz. For the development of antenna, FR4 substrate having a dielectric permittivity of 4.3 has been adopted. Two parallel slots on the patch are incorporated on either side of the feed line to obtain the wide-band structure. Dumbbell-shaped DGS is also incorporated exactly underneath the feed line to increase the gain of the antenna. HSMS-285C Schottky diode has been used for the implementation of the rectifier circuit and a Greinacher voltage doubler has been chosen. ADS design software has been used for rectifier simulation and CST has been used for the designing of the antenna. Current behavior on the patch can be investigated to explore the wide-band mechanism. The antenna operates in the frequency range of 5.336–6.194[math]GHz and with VSWR less than 2, which corresponds to 16.07% impedance bandwidth. The antenna achieves a gain of 6.189[math]dB and a directivity of 8.776[math]dBi. The conversion efficiency of the rectifier was optimized to 75% at 5.8[math]GHz. The proposed design gave an output of 3.2[math]V which can be used under numerous energy harvesting and wireless power transmission applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:36Z
      DOI: 10.1142/S0218126620500474
       
  • An Efficient and High-Speed Implementation of QRD-MGS Algorithm for STAP
           Application Based on Floating Point FPGAs
    • Authors: Narjes Hasanikhah, Siavash Amin-Nejad, Ghafar Darvish, M. R. Moniri
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a [math] matrix with vector size of 17 takes 7.86[math][math]s with the maximum clock frequency of 282[math]MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-26T02:06:35Z
      DOI: 10.1142/S0218126620500450
       
  • SeRA: Self-Repairing Architecture for Dark Silicon Era
    • Authors: Harini Sriraman, Pattabiraman Venkatasubbu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The lifetime reliability of processors has become a major design constraint in the dark silicon era. Processor reliability issues are mainly due to design defects and aging. Unlike design defects, however, aging faults gradually accumulate over time. Many methods have recently been proposed to monitor the performance degradation of circuits. In this study, an architectural solution that extends the circuit-level age monitoring to processor stages is proposed for monitoring performance degradation. When degradation of a stage quantified as delay of half of the reference clock occurs, a self-repairing mechanism is triggered. This mechanism configures an field programmable gate array (FPGA), which takes over the functions of the degraded unit. The proposed self-repairing mechanism is applied to the stages of the processor data-path. This method (SeRA) has lesser area overhead compared with the state-of-art solutions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:11:00Z
      DOI: 10.1142/S021812662050053X
       
  • Novel Monopole Microstrip Antennas for GPS, WiMAX and WLAN Applications
    • Authors: Biplab Bag, Priyabrata Biswas, Sushanta Biswas, Partha Pratim Sarkar, Dibyendu Ghoshal
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, two novel low-profile monopole antennas are presented for simultaneous operation in GPS (Global Positioning System), WLAN (Wireless Local Area Network) and WiMAX (Worldwide Interoperability for Microwave Access) applications. The antennas constitute of a T-shaped microstrip feed line and directly coupled strips to generate multiple bands. The proposed antennas are printed on one side of a low-cost FR4 epoxy substrate and partial ground plane (metal plane is etched partially) are fabricated on the other side of the substrate. The overall dimension of antenna is [math][math]mm3. Measured results show that the antenna1 (quad band) covers the four distinct operating bands of 320[math]MHz (2.17–2.49[math]GHz), 190[math]MHz (3.31–3.50[math]GHz), 270[math]MHz (5.18–5.45[math]GHz) and 700[math]MHz (5.5–6.20[math]GHz). Antenna2 (penta band) covers the frequency bands of 1.29–1.98[math]GHz (center frequency 1.61[math]GHz), 2.78–2.91[math]GHz (center frequency 2.83[math]GHz), 3.59–3.94[math]GHz (center frequency 3.75[math]GHz), 5.15–5.33[math]GHz (center frequency 5.24[math]GHz) and 5.39–6.06[math]GHz (center frequency 5.56[math]GHz). The detail antenna design and parametric analyses are discussed in steps. The characteristic of radiation pattern and gain are measured. The measured and simulated results are in good agreement. The antennas are designed using a simulation software HFSS v.15.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:11:00Z
      DOI: 10.1142/S0218126620500504
       
  • New Voltage-Mode Sinusoidal Oscillators Using VDIBAs
    • Authors: San-Fu Wang, Hua-Pin Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents two new voltage-mode sinusoidal oscillators based on voltage differencing inverting buffered amplifier (VDIBA). The first proposed circuit exhibits independent and electronic control of oscillation condition by using the bias current of the VDIBA. The proposed configuration contains only single VDIBA, two grounded capacitors and two resistors, which are the least number of active components and the minimum number of passive components necessary for realizing voltage-mode oscillator topology. The second proposed circuit exhibits independent and electronic control on the condition of oscillation without affecting the oscillation frequency by adjusting the separate bias currents of the VDIBAs. The proposed configuration contains two VDIBAs, two grounded capacitors and one resistor, which can provide four quadrature voltage outputs simultaneously. Both proposed circuits enjoy only two grounded capacitors, which are suitable for monolithic integration. HSpice simulations and experimental results are included to confirm the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:11:00Z
      DOI: 10.1142/S0218126620500528
       
  • Simple Double-Scroll Chaotic Circuit Based on Meminductor
    • Authors: D. D. Zhai, F. Q. Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Meminductor has attracted more and more attention as the new memory element. In this paper, a new generic meminductor model is proposed and analyzed. Its emulator is designed and its pinched hysteresis loop is presented. Based on the established meminductor and using a traditional capacitor and resistor, a new simple chaotic circuit presenting double-scroll chaotic attractors is proposed and its dynamical behaviors including phase portrait, Lyapunov exponents, Poincare mapping, power spectrum, bifurcation and the sensibility of initial value are analyzed. Meanwhile, it has been found that hidden attractors and transient chaotic phenomena under different initial value. Finally, the hardware circuit for the proposed simple double-scroll chaotic system is constructed and some experimental results are presented for validating the correctness of the theoretical analysis.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:58Z
      DOI: 10.1142/S0218126620500486
       
  • Texture Entropy-Based Classification for Iris Recognition Systems
    • Authors: Veljko Papic, Jelena Krmar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In recent years, iris recognition is one of the most widely used techniques for person identification. Automatic iris identification implies a comparison of query iris image with iris entries in a large database to determine the identity of the person. In this paper, we propose a straightforward and effective algorithm for the classification of irises into several categories according to the iris texture characteristics. The goal of the classification is to identify and retrieve a smaller subset of the large database and to narrow down the search space. In this way, the response time of the iris recognition system could be significantly improved. We analyzed several cases for dividing the whole database (we used UPOL, CASIA, and UBIRIS databases) into up to eight subsets and calculated the time savings. The simulation results illustrate the potential of the proposed classification method for large-scale iris databases.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:57Z
      DOI: 10.1142/S0218126620500516
       
  • FPGA Implementation of the Generalized Parallel Two-Box Model-based
           Digital Predistorter for Wireless Transmitters
    • Authors: Ahmad Rahati Belabad, Soheil Shahrooz, Saeed Sharifian, Seyed Ahmad Motamedi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, the FPGA implementation of the generalized parallel two-box (GPTB) model is proposed. The blocks such as multipliers, complex magnitude calculator, and magnitude powers calculator have been utilized to implement the GPTB model. In the implementation of the proposed model, a total of 30 complex multipliers, 56 noncomplex multipliers and 56 adders were used. The GPTB DPD model has been implemented by using System Generator and Vivado software. The FPGA with a part number of xc7vx690t-3 from Xilinx has been employed to implement the model. The simulation results demonstrate the correctness of the implemented model in Vivado. Also, the verification of the GPTB model is accomplished by means of the simulation of the transmitter excited by QAM signals in the ADS software. The measure of an adjacent channel power ratio (ACPR) decreased by about 16[math]dB as a result of the simulation.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:57Z
      DOI: 10.1142/S0218126620500541
       
  • A High-Data-Rate Area-Efficient Uni-Pulse Harmonic Modulation Transmitter
           for Implantable Neural Recording Microsystems
    • Authors: Mohammad Zinaty, Parviz Amiri, Mohammad Hossein Maghami
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a new data transmission method, named Uni-Pulse Harmonic Modulation (PHM), is presented and its concept is mathematically analyzed using the relations of inductive links. In this type of modulation, the Uni-Pulse passing through the primary coil generates an oscillation in the secondary coil, corresponding to its positive edge, and its negative edge is able to damp this oscillation. The Uni-Pulse passing the primary coil gives the opportunity to use a half-bridge driver instead of full-bridge driver and hence the chip area is desirably reduced. For implementing the proposed modulation technique, two half-bridge driver circuits are suggested that are controlled by series of transistors and transmission gates occupying 900[math][math]m2 and 737.87[math][math]m2 of chip area, respectively. Another merit of the proposed transmitters, besides their occupying low chip area, is that they can transmit data at the rate of 40[math]MHz, while the received frequency is set at 66.6[math]MHz. Therefore, the high amount of 60% is obtained for the data rate to carrier frequency ratio. Designed in a standard 0.18-[math]m CMOS process, the proposed circuits operate at 1.8[math]V supply voltages with consuming almost 400[math]pj energy for transmitting each data bit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:57Z
      DOI: 10.1142/S0218126620200017
       
  • A Scaler Design for the RNS Three-Moduli Set [math] Based on Mixed-Radix
           Conversion
    • Authors: Ahmad Hiasat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Adopting the moduli set [math] for different DSP applications instead of the traditional moduli set [math] has the advantage of excluding modulus [math]. A multiply-and-accumulate modulo [math] unit is more demanding than a modulo [math] unit, which signifies the importance of this adoption. This paper introduces a new design for a scaling unit “Scaler”, that deals with the arithmetic-friendly residue number system (RNS) moduli set [math]. The scaling factor is the power-of-two moduli [math]. The scaling algorithm is based on the mixed-radix conversion (MRC) technique, which converts RNS-based representation into a weighted representation. The proposed approach is compared with other functionally-identical or functionally-similar scalers that perform scaling for the same moduli set under consideration or for the moduli set [math]. The comparison is carried using theoretical unit-gate approach and experimental VLSI layout approach. The proposed scaler is shown to be more area and power-efficient than recently published competitive works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:56Z
      DOI: 10.1142/S0218126620500413
       
  • A Statistical Test Generation Based on Mutation Analysis for Improving the
           Hardware Trojan Detection
    • Authors: Yanjiang Liu, Yiqiang Zhao, Jiaji He, Ruishan Xin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:56Z
      DOI: 10.1142/S0218126620500498
       
  • Integrated Passive Devices and Switching Circuit Design for a 3D DC/DC
           Converter up to 60 V
    • Authors: Sergio Saponara, Gabriele Ciarpi, Tobias Erlbacher, Gudrun Rattmann
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work presents the design and test of a switched-cap 3D DC/DC converter able to work up to 60[math]V. The switches and the control circuits are integrated single-chip in a high-voltage (HV) MOS technology, and the passive devices are stacked on top of the chip. As an innovation versus the state-of-the-art, the work first presents the design of integrated passive devices, based on through silicon vias (TSV) MOS-compatible technology, which are suitable for switching converter applications up to 60[math]V. Then, the implementation and experimental characterization of the switched-cap 3D DC/DC is proposed, with the silicon TSV capacitors stacked on top of the 0.35[math][math]m HV-MOS die. Compared with the state-of-the-art, the proposed 3D DC/DC converter is a compact circuit, able to directly regulate a wide input voltage range (from 6[math]V to 60[math]V) to a 5[math]V, 2[math]W output. Hence, it is suitable to supply low-power loads, such as control units and/or sensors, directly from the 48[math]V power line available in hybrid vehicles or telecom and networking systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-22T06:10:55Z
      DOI: 10.1142/S0218126620500395
       
  • Multimodal Wireless Sensor Networks for Monitoring Applications: A Review
    • Authors: Juan Aranda, Diego Mendez, Henry Carrillo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless sensor networks (WSNs) are a widely used solution for monitoring-oriented applications (e.g., water quality on watersheds, pollution monitoring in cities). These kinds of applications are characterized by the necessity of two data-reporting modes: time-driven and event-driven. The former is used mainly for continually supervising an area and the latter for event detection and tracking. By switching between both modes, a WSN can improve its energy efficiency and event-reporting latency, compared to single data-reporting schemes. We refer to those WSNs, where both data-reporting modes are required simultaneously, as multimodal wireless sensor networks (M2WSNs). In this paper, we present, from an energy-efficiency perspective, a review of switching mechanisms for M2WSNs. Besides, we explore two sophisticated techniques required in M2WSNs for further energy saving and event-reporting latency reduction purposes: duty-cycling and wake-up radio. We highlight future directions concerning switching and network management techniques for M2WSNs. To our knowledge, this review is first of its kind.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:21Z
      DOI: 10.1142/S0218126620300032
       
  • Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using
           Nanoscale Hierarchical Implementation Model
    • Authors: Theodoros Simopoulos, George Ph. Alexiou, Themistoklis Haniotakis
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, we extend the implementation guidelines of the WDSRAM — Write Driver SRAM — through the definition of a hierarchical implementation model which is applied on the material layout memory design level. This model can be used in order to create WDSRAMs of any size, maintaining the memory’s write function speed-up against the typical SRAM implementation model. The post-layout simulation results are presented in comparison with the corresponding results of the typical SRAM and confirm that the WDSRAM write function speed-up is maintained against the typical SRAM when the memory size increases. A brief background knowledge on the WDSRAM function is also provided.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:21Z
      DOI: 10.1142/S0218126619400085
       
  • Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells
           Comprising D- and E-Mode HEMTs
    • Authors: Aleš Chvála, Lukáš Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Šatka, Michal Blaho, Dagmar Gregušová, Ján Kuzmík
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents monolithic integrated InAlN/GaN NAND and NOR logic cells comprising depletion-mode, enhancement-mode and dual-gate enhancement-mode high electron mobility transistors (HEMTs). The designed NAND and NOR logic cells consist of the depletion-mode and enhancement-mode HEMT transistors integrated onto a single die. InAlN/GaN-based NAND and NOR logic cells with good static and dynamic performance are demonstrated for the first time. Calibrated static and dynamic electrophysical models are proposed for 2D device simulations in Sentaurus Device environment. Sentaurus Device mixed-mode setup interconnects the transistors to NAND and NOR logic circuits which allows analysis and characterization of the devices as a complex system. Circuit models of depletion-mode, enhancement-mode and dual-gate HEMTs are designed and calibrated by experimental results and 2D device simulations. The proposed models exhibit highly accurate results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:20Z
      DOI: 10.1142/S0218126619400097
       
  • Fault Tolerant Control for Wind Turbine System Based on Model Reference
           Adaptive Control and Particle Swarm Optimization Algorithm
    • Authors: Yassine Fadili, Ismail Boumhidi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper tackles the problem of Fault Tolerant Control (FTC) for Wind Turbine System. Motivated by the Model Reference Adaptive Control (MRAC) and the Particle Swarm Optimization Algorithm (PSOA), the main contribution of this work is to provide online tuning for the wind turbine controller. In order to achieve the required system performances, even during components and/or system faults, our proposed strategy takes care of an adaptive controller in which the desired performance is expressed in terms of a reference model. The controller parameter adjustments are made using the stability theory that involves the gradient function and the Lyapunov function. Moreover, the minimization of the fitness function of PSOA allows convergence of the proposed MRAC to an optimal point, owing to redistribution of the control signals when a failure or noise occurs. The simulation results have shown good performance than some existing approaches in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-11T08:54:20Z
      DOI: 10.1142/S0218126620500371
       
  • Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier
           with Reduced Power Dissipation
    • Authors: Mohammad Moradinezhad Maryan, Seyed Javad Azhari, Mehdi Ayat, Reza Rezaei Siahrood
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[math][math]m TSMC (level-49) CMOS technology. Simulation results with [math]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [math][math]dB bandwidth (BW) is 903[math]MHz, the total harmonic distortion (THD) is 0.3% (at 1[math]MHz), and the maximum and static power consumption are [math]W and [math]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [math][math]dB BW as 657[math]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-10T09:16:33Z
      DOI: 10.1142/S0218126620500383
       
  • RF/Microwave Power Amplifiers: The Development Route and State-of-the-Art
    • Authors: Xuguang Li, Haipeng Fu, Kaixue Ma, Shoukui Zhu, Qianfu Cheng, Jianguo Ma
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent decades have seen significant progresses in the field of power amplifiers (PAs). In order to present the evolution of the field, this paper shows the development trends of the PA research based on the statistical analysis from 1970 to 2017. The brief history of radio frequency (RF)/microwave PAs and a comprehensive review on the evolution of RF/microwave PAs are presented. The state-of-the-art PAs thus far based on the statistical analysis in terms of the figure of merit (FoM) of RF/microwave PAs have been discussed in this paper. A quantitative relationship of trade-off of PA performance metrics is proposed, and the potential room for improvement of the performance of the PAs is also revealed.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:48Z
      DOI: 10.1142/S0218126620300044
       
  • Classification of EEG Signals Based on Filter Bank and Sparse
           Representation in Motor Imagery Brain-Computer Interfaces
    • Authors: Jin Wang, Qingguo Wei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To improve the classification performance of motor imagery (MI) based brain-computer interfaces (BCIs), a new signal processing algorithm for classifying electroencephalogram (EEG) signals by combining filter bank and sparse representation is proposed. The broadband EEG signals of 8–30[math]Hz are segmented into 10 sub-band signals using a filter bank. EEG signals in each sub-band are spatially filtered by common spatial pattern (CSP). Fisher score combined with grid search is used for selecting the optimal sub-band, the band power of which is employed for designing a dictionary matrix. A testing signal can be sparsely represented as a linear combination of some columns of the dictionary. The sparse coefficients are estimated by [math] norm optimization, and the residuals of sparse coefficients are exploited for classification. The proposed classification algorithm was applied to two BCI datasets and compared with two traditional broadband CSP-based algorithms. The results showed that the proposed algorithm provided superior classification accuracies, which were better than those yielded by traditional algorithms, verifying the efficacy of the present algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:48Z
      DOI: 10.1142/S0218126620500346
       
  • An S-Band CMOS 6-Bit Vector-Sum Phase Shifter with Low RMS Phase Error
           Using Frequency-to-Voltage Converter Feedforward Loop
    • Authors: Mostafa Nobakht Sarkezeh, Aminghasem Safarian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2–4[math]GHz) applications. The designed phase shifter in 180[math]nm CMOS technology achieves an RMS phase error in the range of 0.607–1.18∘ with [math][math]dBm input signal over 2–4[math]GHz frequency band. With lower input signal of [math][math]dBm, the RMS phase error is 0.621–1.34∘ for 2–4[math]GHz input frequency. The proposed phase shifter shows an RMS amplitude error less than 0.41[math]dB over 2–4[math]GHz frequency. The 1-dB compression point ([math]) of the proposed phase shifter is [math][math]dBm. The proposed wideband phase shifter draws 32 mA from 1.8 supply voltage. It occupies an active area of only 0.025[math]mm2, due to active design without any inductor.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:47Z
      DOI: 10.1142/S021812662050036X
       
  • 1/[math] (Close-in) Phase Noise Reduction by Tail Transistor Flicker Noise
           Suppression Technique
    • Authors: Jalil Mazloum, Samad Sheikhaei
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel circuit method is proposed to reduce 1/[math] (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/[math] output phase noise is reduced by 5.7[math]dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18[math][math]m CMOS technology with 1.8[math]V supply and 3.6[math]mW power consumption. Post-layout simulations predict a phase noise of [math][math]dBc/Hz for the proposed oscillator at 100[math]KHz offset from 3.1[math]GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6[math]dBc/Hz at 100[math]KHz and 1[math]MHz offsets, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-08T09:04:47Z
      DOI: 10.1142/S0218126620500358
       
  • In-Network Distributed Least-Mean-Square Identification of Nonlinear
           Systems Using Volterra–Laguerre Model
    • Authors: Saurav Gupta, Sachin N. Kapgate, Ajit Kumar Sahoo
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      It is of great importance to model the behavior of nonlinear systems in a distributed fashion using wireless sensor networks (WSNs) because of their computation and energy-efficient data processing. However, least squares methods have been previously employed to estimate the parameters of Volterra model for modeling nonlinear systems. Still, it is more convenient and advantageous to use in-network distributed identification strategy for real-time modeling and control. In this context, a black-box model with generalized structure and remarkable modeling ability called Volterra–Laguerre model is considered in which distributed signal processing is employed to identify the nonlinear systems in a distributed manner. The model cost function is expressed as a separable constrained minimization problem which is decomposed into augmented Lagrangian form to facilitate the distributed optimization. Then, alternating direction method of multipliers is employed to estimate the optimal parameters of the model. Convergence of the algorithm is guaranteed by providing its mean stability analysis. Simulation results for a nonlinear system are obtained under the noisy environment. These results are plotted against the results of noncooperative and centralized methods, demonstrating the effectiveness and superior performance of the proposed algorithm.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:41Z
      DOI: 10.1142/S0218126620500309
       
  • A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network
    • Authors: Peng Guo, Hong Ma, Ruizhi Chen, Donglin Wang
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although the convolutional neural network (CNN) has exhibited outstanding performance in various applications, the deployment of CNN on embedded and mobile devices is limited by the massive computations and memory footprint. To address these challenges, Courbariaux and co-workers put forward binarized neural network (BNN) which quantizes both the weights and activations to [math]1. From the perspective of hardware, BNN can greatly simplify the computation and reduce the storage. In this work, we first present the algorithm optimizations to further binarize the first layer and the padding bits of BNN; then we propose a fully binarized CNN accelerator. With the Shuffle–Compute structure and the memory-aware computation schedule scheme, the proposed design can boost the performance for feature maps of different sizes and make full use of the memory bandwidth. To evaluate our design, we implement the accelerator on the Zynq ZC702 board, and the experiments on the SVHN and CIFAR-10 datasets show the state-of-the-art performance efficiency and resource efficiency.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:41Z
      DOI: 10.1142/S0218126619400048
       
  • An Experimental Study of Metastability-Induced Glitching Behavior
    • Authors: Thomas Polzer, Florian Huemer, Andreas Steininger
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [math] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:41Z
      DOI: 10.1142/S0218126619400061
       
  • Advances in Concurrent Computing for Digital Stochastic Measurement
           Simulation
    • Authors: Nebojsa Pjevalica, Velibor Pjevalica, Nenad Petrovic
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper introduces a concurrent computing technique for the acceleration of digital stochastic measurement simulations. The digital stochastic measurement presents an advanced methodology based on the specific parallel hardware structure, utilized for an orthogonal transformation calculus/decomposition. Methodology is analyzed in detail, starting from the very basic idea, toward recent references, covering main research directions and trends. An oversampling nature of the evaluated digital stochastic measurement, along with demanding arithmetic requirements, implies exhausting simulation complexity. As a test case, several typical power grid signals were harmonically analyzed through a discrete Fourier transformation based on the proposed methodology. A harmonic decomposition was simulated with several levels of computing concurrency. Through all the simulated scenarios main success criterion was model accuracy, while the parameter used for selection of the optimal simulation computing technique was the overall calculus speed. Final results exposed thread pool computing technique as an optimal simulation platform.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-04-02T08:47:40Z
      DOI: 10.1142/S0218126620500334
       
  • A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at
           Board Level
    • Authors: Hassan Ebrahimi, Hans G. Kerkhoff
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The reliability of board-level data communications intensively depends on the reliability of interconnections on a board. One of the most challenging interconnections reliability threats is intermittent resistive faults (IRFs). Detecting such faults is a major challenge. The main reason is the random behavior of these faults. They may occur randomly in time, duration and amplitude. The occurrence rate can vary from a few nanoseconds to months. This paper investigates IRF detection at the board level by introducing a new digital in situ IRF monitor. Hardware-based fault injection has been used to validate the proposed IRF monitor. As case studies, two widely used on-board transmission protocols namely the Universal Asynchronous Receiver Transmitter (UART) and the Serial Peripheral Interface bus (SPI), have been used. In addition, one fault management framework, based on the IJTAG standard, has been implemented to collect and characterize information from the monitors. The experimental results show that the proposed monitor is effective in detecting IRFs at the board level.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-27T01:30:37Z
      DOI: 10.1142/S0218126619400036
       
  • A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems
    • Authors: Lukáš Kohútka, Lukáš Nagy, Viera Stopjaková
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-27T01:30:36Z
      DOI: 10.1142/S021812661940005X
       
  • Design, Fabrication and Measurement of a Novel Compact Triband CPW-Fed
           Planar Monopole Antenna Using Multi-type Slots for Wireless Communication
           Applications
    • Authors: Ahmed Zakaria Manouare, Saida Ibnyaich, Divitha Seetharamdoo, Abdelaziz EL Idrissi, Abdelilah Ghammaz
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel compact coplanar waveguide (CPW)-fed planar monopole antenna with triple-band operation is presented for simultaneously satisfying the LTE 2600, WiMAX, WLAN and X-band applications. It is printed on a single-layered FR4 substrate. In this paper, the proposed antenna, which occupies a small volume of [math][math]mm3 including the ground plane, is simply composed of a CPW-fed monopole with U-, L- and T-shaped slots. By carefully selecting the lengths and positions of both L-shaped and U-shaped slots, a good dual notched band characteristic at center-rejected frequencies of 3.10[math]GHz and 4.50[math]GHz can be achieved, respectively. The T-shaped slot is etched on the radiating element to excite a resonant frequency in the 7[math]GHz band. Then, to prove the validation of the typical design, a prototype model is fabricated and measured. The experimental result shows that the three frequency bands of 2.31–2.80[math]GHz (490[math]MHz), 3.37–3.84[math]GHz (470[math]MHz) and 5.04–7.94[math]GHz (2900[math]MHz) can successfully cover the desired bandwidths of LTE2600/WiMAX (3.50/5.50[math]GHz)/WLAN (5.20/5.80[math]GHz) and the X-band communication systems (7.1-GHz operation). The principal applications of the X-band are radar, aircraft, spacecraft and mobile or satellite communication system. Nearly omnidirectional and bidirectional radiation patterns of the triband antenna are observed in both H- and E-planes, respectively. In addition, a reasonable gain over the operating bands has been obtained. Indeed, the good agreements between simulation and measurement results have validated the proposed structure, confirming its potential for multiband wireless communication services.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-25T02:27:15Z
      DOI: 10.1142/S0218126620500322
       
  • Design of Robust Quantizers for Low-Bit Analog-to-Digital Converters for
           Gaussian Source
    • Authors: Milan R. Dinčić, Zoran H. Perić, Dragan B. Denić, Zoran Stamenković
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper considers the design of robust logarithmic [math]-law companding quantizers for the use in analog-to-digital converters (ADCs) in communication system receivers. The quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. Furthermore, linearization of the logarithmic [math]-law companding function is performed to simplify hardware implementation of the quantizers. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness — they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic [math]-law companding quantizers there is no need for using automatic gain control (AGC), which reduces the implementation complexity and increases the speed of the ADCs due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power. The proposed low-bit ADCs can be used in MIMO and 5G massive MIMO systems, where due to very high operating frequencies and a large number of receiving channels (and consequently a large number of ADCs), the reduction of ADC complexity and energy consumption becomes a significant goal.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-25T02:27:14Z
      DOI: 10.1142/S0218126619400024
       
  • Realization Approach for Sinusoidal Signal Generation and Circuit with
           Easy Control
    • Authors: S. Maheshwari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new approach for realizing sinusoidal signal with quadrature property is proposed, which employs simple analog building blocks and facilitates easy tuning of the oscillation frequency, through a gain factor. The proposed approach is used for realizing a novel quadrature oscillator circuit, which requires three current feedback operational amplifiers and passive components. The proposed circuit provides outputs at low impedance terminals, and benefits from easy control over the frequency of oscillation (FO), which depends on resistive ratio, rather than absolute resistor values. The frequency control is also independent of the condition of oscillation (CO). The nonideal effects and the parasitic studies are presented. The verification of the proposed realization scheme for quadrature oscillators and the new circuit is carried out through both simulation studies and experimental results, using the commercially available chips.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-25T02:27:13Z
      DOI: 10.1142/S0218126620500310
       
  • Modeling Analysis and Diagnosis of Analog Circuits in [math]-Domain
    • Authors: Michał Tadeusiewicz, Marek Ossowski
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The paper is dedicated to the linear time-invariant analog electronic circuits. It deals with the problem of modeling of the circuits in the [math]-domain. The model put forward in this paper enables solving different issues with the analysis of linear dynamic circuits. The model’s usefulness to fault diagnosis is emphasized in the paper, especially its application to multiple soft fault diagnosis of linear circuits. To make such diagnosis possible, the node equations with unknown node voltages and the diagnosed parameters are used. The set of actual values of the verified parameters is achieved by solving an appropriate system of algebraic nonlinear equations associated to the node equations. It can be determined using the Newton algorithm with adaptive choice of damping parameter. The diagnosis method is adjusted to real conditions by considering the deviations of the healthy parameters inside their tolerance scopes. Two real-life electronic circuits are considered to illustrate the method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:17Z
      DOI: 10.1142/S0218126620500280
       
  • Accurate Detection of ECG Signals in ECG Monitoring Systems by Eliminating
           the Motion Artifacts and Improving the Signal Quality Using SSG Filter
           with DBE
    • Authors: Mahesh B. Dembrani, K. B. Khanchandani, Anita Zurani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The automatic recognition of QRS complexes in an Electrocardiography (ECG) signal is a critical step in any programmed ECG signal investigation, particularly when the ECG signal taken from the pregnant women additionally contains the signal of the fetus and some motion artifact signals. Separation of ECG signals of mother and fetus and investigation of the cardiac disorders of the mother are demanding tasks, since only one single device is utilized and it gets a blend of different heart beats. In order to resolve such problems we propose a design of new reconfigurable Subtractive Savitzky–Golay (SSG) filter with Digital Processor Back-end (DBE) in this paper. The separation of signals is done using Independent Component Analysis (ICA) algorithm and then the motion artifacts are removed from the extracted mother’s signal. The combinational use of SSG filter and DBE enhances the signal quality and helps in detecting the QRS complex from the ECG signal particularly the R peak accurately. The experimental results of ECG signal analysis show the importance of our proposed method.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:15Z
      DOI: 10.1142/S0218126620500243
       
  • Resource and Performance Tradeoff for Task Scheduling of Parallel
           Reconfigurable Architectures
    • Authors: Chi-Chou Kao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we propose a resource/performance tradeoff algorithm for task scheduling of parallel reconfigurable architectures. First, it uses unlimited resources to generate an optimal scheduling algorithm. Then, a relaxation algorithm is applied to satisfy the number of resources under increasing minimum performance. To demonstrate the performance of the proposed algorithm, we not only compare the existing methods with standard benchmarks but also implement on physical systems. The experimental results show that the proposed algorithms satisfy the requirements of the systems with limited resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:12Z
      DOI: 10.1142/S0218126620500292
       
  • A Hardware–Software Co-Design Framework for Real-Time Video
           Stabilization
    • Authors: Hassan Javed, Muhammad Bilal, Shahid Masud
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Live digital video is a valuable source of information in security, broadcast and industrial quality control applications. Motion jitter due to camera and platform instability is a common artefact found in captured video which renders it less effective for subsequent computer vision tasks such as detection and tracking of objects, background modeling, mosaicking, etc. The process of algorithmically compensating for the motion jitter is hence a mandatory pre-processing step in many applications. This process, called video stabilization, requires estimation of global motion from consecutive video frames and is constrainted by additional challenges such as preservation of intentional motion and native frame resolution. The problem is exacerbated in the presence of local motion of foreground objects and requires robust compensation of the same. As such achieving real-time performance for this computationally intensive operation is a difficult task for embedded processors with limited computational and memory resources. In this work, development of an optimized hardware–software co-design framework for video stabilization has been investigated. Efficient video stabilization depends on the identification of key points in the frame which in turn requires dense feature calculation at the pixel level. This task has been identified to be most suitable for offloading the pipelined hardware implemented in the FPGA fabric due to the involvement of complex memory and computation operations. Subsequent tasks to be performed for the overall stabilization algorithm utilize these sparse key points and have been found to be efficiently handled in the software. The proposed Hardware–Software (HW–SW) co-design framework has been implemented on Zedboard FPGA platform which houses Xilinx Zynq SOC equipped with ARM A9 processor. The proposed implementation scheme can process real-time video stream input at 28 frames per second and is at least twice faster than the corresponding software-only approach. Two different hardware accelerator designs have been implemented using different high-level synthesis tools using rapid prototyping principle and consume less than 50% of logic resources available on the host FPGA while being at least 30% faster than contemporary designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-20T09:16:12Z
      DOI: 10.1142/S0218126620500279
       
  • Limited Effect of Noise Injection on Synchronization of Crystal
           Oscillators
    • Authors: Kazuyoshi Ishimura, Isao T. Tokuda
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Experimental study on noise-induced synchronization of crystal oscillators is presented. Two types of circuits were constructed: one consists of two Pierce oscillators that were isolated from each other and received a common noise input, while the other is based on a single Pierce oscillator that received a same sequence of noise signal repeatedly. Due to frequency detuning between the two Pierce oscillators, the first circuit showed no clear sign of noise-induced synchronization. The second circuit, on the other hand, generated coherent waveforms between different trials of the same noise injection. The waveform coherence was, however, broken immediately after the noise injection was terminated. Stronger perturbation such as the voltage resetting was finally shown to be effective to induce phase shifts, leading to phase synchronization of the Pierce oscillator. Our study presents a guideline for utilizing noise to synchronize clocks of multiple CPU systems, distributed sensor networks, and other engineering devices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-18T01:42:29Z
      DOI: 10.1142/S0218126620500267
       
  • A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs
    • Authors: Xin Li, Cheng Huang, Desheng Ding, Jianhui Wu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-18T01:42:29Z
      DOI: 10.1142/S0218126620300020
       
  • Attribute-Based Collusion Resistance in Group-Based Cloud Data Sharing
           using LKH Model
    • Authors: N. Rajkumar, E. Kannan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Utilizing cloud computing, users can avail a compelling and effective approach for information sharing between collective individuals in the cloud with the facility of less administration cost and little maintenance. Security in cloud computing refers to procedures, standards and processes created to provide assurance for security of information in the cloud environment. In this paper, we project a secure data sharing method in cloud for dynamic members by producing keys for users using Logic Key Hierarchy (LKH) model, i.e., a tree-based key generation technique. We have generated this key using reverse hashing and one way hash-based technique so that no exiled user can predict the new key and new users cannot predict the old keys of the network group. From numerous experiments, this work is proved to be the best in maintaining forward secrecy, backward secrecy and group compromise attacks and consumes less computation cost compared to any other hash-based key generation techniques.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-12T03:06:24Z
      DOI: 10.1142/S0218126620300019
       
  • A High Precision Output Impedance Calibration Technique for SST
           Transmitter
    • Authors: Xu Bai, Jianzhong Zhao, Yumei Zhou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a high precision output impedance calibration technique for source-series terminated (SST) transmitter. Unlike the conventional impedance calibration technique using a digital method, the proposed impedance calibration employs the analog method to implement the impedance calibration. Therefore, there is no trade-off between area overhead and precision of calibration. The proposed analog impedance calibration circuit has three analog impedance control loops, namely, pull-up loop, pull-down loop and shunt-loop. Each loop is composed of a high gain amplifier and a slice-based unit. To reduce the hardware, the shunt loop utilized a slice unit replication design to achieve the shunt-slice calibration. These loops send output voltage to the SST transmitter when they reached stability. Fabricated in 55[math]nm CMOS technology, the power consumption of the calibration circuit is 1.35[math]mW and the total area is 61[math][math]m*83.1[math][math]m, which consumes 6.3% of the total power consumed by the transmitter and occupies 25% of the total area occupied by the complete transmitter. The post-layout simulation result shows that the maximum impedance calibration error of the three loops is less than 0.02%.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-11T08:17:37Z
      DOI: 10.1142/S0218126620500255
       
  • Normally Bypassed Cascaded Sources Multilevel Inverter with RGA
           Optimization for Reduced Output Distortion and Formulaic Passive Filter
           Design
    • Authors: G. Chitrakala, N. Stalin, V. Mohan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-11T08:17:37Z
      DOI: 10.1142/S021812662050019X
       
  • Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic
           Structures
    • Authors: B. P. Bhuvana, V. S. Kanchana Bhaaskaran
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the adiabatic logic called 2[math]–[math]–2[math], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[math]–[math]–2[math] adiabatic logic is capable of operating through a wide range of frequency from 100[math]MHz to 1[math]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[math]–[math]–2[math] against the [math] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[math]–[math]–2[math] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[math]–[math]2[math] over [math] and PFAL designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:54Z
      DOI: 10.1142/S0218126620500164
       
  • A Multiband, Spectrally-Efficient Impulse Radio Transmitter Design with
           Low-Complexity CMOS Pulse Generator for IEEE 802.15.4a Application
    • Authors: Hanen Saoudi, Hamadi Ghariani, Mongi Lahiani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A novel multiband impulse radio ultra-wideband (MB-IR-UWB) transmitter with an energy-efficient and low-complexity pulse generator design technique compliant with the IEEE 802.15.4a standard is investigated in this paper. This transmitter is made up of a new differential narrow triangular pulse generator, a new multiband voltage-controlled oscillator (VCO), an active mixer and a variable-gain power amplifier (PA). It operates at 14 UWB bands and generates an output signal with the duration of 3[math]ns, more than 500[math]MHz of channel bandwidth and more than 20[math]dB of sidelobe suppression, while achieving an average energy efficiency of 51.36 pJ/pulse from 1.4-V supply. Improving spectral flexibility and worldwide compliance is the major contribution brought by this paper to make this circuit as a multifunction wireless device well suited for low-cost, low-power multiband applications.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:54Z
      DOI: 10.1142/S0218126620500206
       
  • Operation, Control and Verification of Seven-Level Quasi-Z-Source-Based
           [math]-Type Inverter
    • Authors: Ramesh Rahul Jammy, Kirubakaran Annamalai, Chinmay Kumar Das
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a novel seven-level Quasi-Z-Source-based [math]-type inverter (7L[math]qZST[math]) is proposed. The proposed inverter is an upgrade of Quasi-Z-source (qZs) network and seven-level [math]-type inverter. The 7L qZST[math] comprises of three qZs-based impedance networks, two bidirectional switches and an [math]-bridge inverter. It owns the advantages of reduced switch count, improved output voltage gain, enhanced reliability and better quality of output voltage and current. The performance of the proposed topology is tested for two different pulse width modulation techniques based on shoot-through control. The first technique offers simple control and operated at a fixed shoot-through duty cycle for realizing output voltage level. The second technique facilitates independent control of each qZs network dc-link voltage and they can be operated at different shoot through duty cycle which overcomes the limitation of first technique with better quality in output voltage. The detailed operation of the proposed topology and control schemes have been elaborated for different switching states for each output voltage level generation. Extensive simulation and experimentation are performed for both the switching schemes to verify their performance under steady state and dynamic conditions. Furthermore, a brief comparison is constructed to highlight the merits of the proposed inverter with conventional topologies.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:52Z
      DOI: 10.1142/S0218126620500231
       
  • A Novel Salp Swarm Optimization MPP Tracking Algorithm for the Solar
           Photovoltaic Systems under Partial Shading Conditions
    • Authors: S. Krishnan, K. Sathiyasekar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To extract the maximum solar power from the photovoltaic (PV) panel/array with the high conversion efficiency under partial shading condition (PSC), this paper discusses a new and an efficient maximum power point (MPP) tracking algorithm. The proposed algorithm is based on the bio-inspired salp swarm optimization (SSO), and the algorithm forecasts the global MPP (GMPP) with the fast convergence to GMPP and high tracking efficiency. The SSO algorithm thus reduces the computational burden as encountered in whale optimization algorithm (WOA), and gray wolf optimization (GWO) algorithm discussed in the various literatures. The modeling and simulation of the proposed SSO algorithm are done with the help of Matlab/Simulink software to validate the effectiveness to locate the MPP during PSCs. The simulation results prove that the proposed SSO algorithm exhibits a high PV power output with the tracking efficiency of more than 95% at the faster convergence rate to GMPP. The SSO algorithm is experimentally verified on the conventional boost converter under different shading conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:51Z
      DOI: 10.1142/S0218126620500176
       
  • Evolved Fuzzy NN Control for Discrete-Time Nonlinear Systems
    • Authors: Tim Chen, A. Babanin, Assim Muhammad, B. Chapron, C. Y. J. Chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      To guarantee the asymptotic stability of discrete-time nonlinear systems, this paper proposes an Evolved Bat Algorithm (EBA) fuzzy neural network (NN) controller. In the evolved fuzzy NN modeling, an NN model and linear differential inclusion (LDI) representation are established for arbitrary nonlinear dynamics. This representation is constructed by the use of sector nonlinearity to convert a nonlinear model to the multiple rule base of the linear model, and a new sufficiency condition to guarantee asymptotic stability in the Lyapunov function is implemented in terms of linear matrix inequalities. The proposed method is an enhancement of existing methods which produces good results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-03-04T04:20:48Z
      DOI: 10.1142/S0218126620500152
       
  • A Low-Power Clock Generator with a Wide Frequency Tuning Range and Low
           Temperature Variation: Analysis and Design
    • Authors: Ziba Fazel, MaryamSadat Shokrekhodaei, Mojtaba Atarodi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180[math]nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about [math][math]dBc/Hz at 10[math]MHz offset frequency. Frequency changes less than [math] in the temperature range of [math]C–[math]C. The clock generator consumes 0.657[math]mW of power. Results show improvement in comparison to the previous works.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:49Z
      DOI: 10.1142/S0218126620500127
       
  • Distributed Coordinated Attitude Regulation Control for Multiple
           Spacecraft with Time-varying Uncertainties
    • Authors: Zhihao Zhu, Yu Guo, Zhi Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      For multiple spacecrafts under the communication topology containing a spanning tree with the leader as the root, we investigate a distributed coordinated attitude regulation control problem of the spacecraft with unknown time-varying uncertainties and state-dependent disturbances. Aiming at solving the practical problem that the information of the leader may be only available to a subset of the followers, a novel class of distributed finite-time leaders’ state observer for each follower is proposed. Meanwhile, a new self-adjustment matrix is designed to reduce the overshoot of the system. In addition, an adaptive compensation term is designed to reject the impact of the time-varying inertia uncertainties and external state-dependent and state-independent disturbances. On the basis of the distributed finite-time observer, the self-adjustment matrix and the adaptive law, two distributed coordinated attitude regulation control laws are designed. With the first controller, the coordinated attitude regulation system is stable asymptotically, and with the second controller, the system is bounded stable. Both distributed coordinated attitude regulation controllers can guarantee that the follower spacecraft can track a common time-varying trajectory of the leader. Numerical simulation examples validate the effectiveness of the proposed controllers.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:46Z
      DOI: 10.1142/S0218126620500188
       
  • A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR
           Filter Implementation Using Hardware–Software Co-Design
    • Authors: C. Ranjith, S. P. Joy Vasantha Rani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:44Z
      DOI: 10.1142/S0218126620500140
       
  • Prediction of Pareto Dominance Using an Attribute Tendency Model for
           Expensive Multi-Objective Optimization
    • Authors: Wenbin li, Junqiang Jiang, Xi Chen, Guanqi Guo, Jianjun He
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a novel surrogate-assisted multi-objective evolutionary algorithm, MOEA-ATCM, to solve expensive or black-box multi-objective problems with small evaluation budgets. The proposed approach encompasses a state-of-the-art MOEA based on a nondominated sorting genetic algorithm assisted by multi-fidelity optimization methods. A high-fidelity attribute tendency (AT) surrogate model was used to construct a linear decision space by introducing the knowledge of the objective space. A coarse model (CM) based on the AT model and correlation analyses of the objective functions and decision attributes were used to predict the Pareto dominance for candidates in the new decision space constructed by the AT model. Two major roles of MOEA-ATCM were identified: (1) the development of a new multi-fidelity surrogate-model-based method to predict Pareto dominance in a decision space that was then applied to MOEA, which does not need to dynamically update surrogate models in the optimization process and (2) the development of a Pareto dominance prediction method to obtain good nondominated solutions of expensive or black box problems with relatively few objective function evaluations. The advantages of MOEA-ATCM were verified by mathematical benchmark problems and a real-world multi-objective parameter optimization problem.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:36Z
      DOI: 10.1142/S0218126620500218
       
  • Object Detection Using Multiview CCA-Based Graph Spectral Learning
    • Authors: Peng Guo, Guoqi Xie, Renfa Li
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Recent years have witnessed a surge of interest in semi-supervised learning-based object detection. Object detection is usually accomplished by classification methods. Different from conventional methods, those usually adopt a single feature view or concatenate multiple features into a long feature vector, multiview graph spectral learning can attain simultaneously object classification and weight learning of multiview. However, most existing multiview graph spectral learning (GSL) methods are only concerned with the complementarities between multiple views but not with correlation information. Accurately representing image objects is difficult because there are multiple views simultaneously for an image object. Thus, we offer a GSL method based on multiview canonical correlation analysis (GSL-MCCA). The method adds MCCA regularization term to a graph learning framework. To enable MCCA to reveal the nonlinear correlation information hidden in multiview data, manifold local structure information is incorporated into MCCA. Thus, GSL-MCCA can lead to simultaneous selection of relevant features and learning transformation. Experimental evaluations based on Corel and VOC datasets suggest the effectiveness of GSL-MCCA in object detection.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-28T08:02:34Z
      DOI: 10.1142/S021812662050022X
       
  • Research on the Linear Acceleration Sensor Signal Acquisition Technology
           Based on the High-Order Anti-Aliasing Cauer Filter
    • Authors: Zhuo Hou, Sanmin Shen, Yong Ye, Jiahao Deng, Yuting Liu, Qing Meng, Zuodong Duan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A linear acceleration sensor integrated into an inertial measurement unit and its signal processing technology are presented in this paper. Based on the characteristics of the acceleration sensor, before analog-to-digital conversion, a design method for optimizing and conditioning the output signal in levels of frequency with the high-order anti-aliasing Cauer filter is proposed. Compared with the previously published papers, here we not only focus on the anti-aliasing filtering effect under a single channel, but also pay more attention to the anti-aliasing filtering effect with more data to the same type of channels with the same cut-off frequency and different types of channels with different cut-off frequencies. Similar to other kinds of filters, this paper points out that the high-order anti-aliasing Cauer filter also has its inherent delay characteristic. And this paper also reveals the qualitative relationship between frequency and time delay in different testing environments by using various delay test data. Compared with the previously published papers, through the simple solution processing with the true attitude data, this paper further estimates the error of simple attitude signal processing.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-26T02:58:31Z
      DOI: 10.1142/S0218126620500085
       
  • Divide and Compact — Stochastic Space Compaction for
           Faster-than-at-Speed Test
    • Authors: Alexander Sprenger, Sybille Hellebrand
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([math]-values). These [math]-values impede the test response compaction. In addition, the number and distribution of the [math]-values vary with the clock frequency, and thus a very flexible [math]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [math]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [math]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [math]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [math]-reduction and fault efficiency can be adapted to user-defined goals.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-18T03:38:53Z
      DOI: 10.1142/S0218126619400012
       
  • Analysis, Control and FPGA Implementation of a Fractional-Order Modified
           Shinriki Circuit
    • Authors: Karthikeyan Rajagopal, Fahimeh Nazarimehr, Laarem Guessas, Anitha Karthikeyan, Ashokkumar Srinivasan, Sajad Jafari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we introduce a novel integer-order memristor-modified Shinriki circuit (MMSC). We investigate the dynamic properties of the MMSC system and the existence of chaos is proved with positive largest Lyapunov exponent. Bifurcation plots are derived to analyze the parameter dependence of the MMSC system. The fractional-order model of the MMSC system (FOMMSC) is derived and the bifurcation analysis of the FOMMSC system with the fractional orders is carried out. Fractional-order adaptive sliding-mode controllers (FOASMCs) and genetically optimized PID controllers are designed to synchronize identical FOMMSC systems with unknown parameters. Numerical simulations are conducted to validate the theoretical results. FPGA implementation of the FOASMC controllers is presented to show that the proposed control algorithm is hardware realizable. MMSC has trigonometric functions which make the system more complex and the optimization and synchronization of such systems in the integer order itself are harder, so the paper does the same in fractional order. The proposed system is a memristive circuit which can show special features such as multistability, hyperchaos, and multiscroll attractor. Such a system with these features is very rare in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-15T01:31:23Z
      DOI: 10.1142/S0218126619502323
       
  • A Physics-Based Analytical Model for MgZnO/ZnO HEMT
    • Authors: Yogesh Kumar Verma, Varun Mishra, Santosh Kumar Gupta
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a physics-based compact model is developed for novel MgZnO/ZnO high-electron-mobility transistor (HEMT). Poisson’s equation coupled with 1D Schrödinger equation is solved self-consistently in the triangular quantum well to derive an expression of two-dimensional electron gas (2DEG) density with respect to gate voltage at the heterointerface of barrier (MgZnO) and buffer (ZnO) layers. A compact mathematical framework has been devised further for the first time for ZnO-based HEMT to the best of our knowledge using the expression of 2DEG density to compute surface potential, gate charge, gate current, gate capacitance, current–voltage characteristics, output conductance, transconductance and cut-off frequency with respect to gate voltage and along with the drain–source output resistance [math].
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-15T01:31:22Z
      DOI: 10.1142/S0218126620500097
       
  • Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC
           Converter for Implantable Devices
    • Authors: Najmeh Cheraghi Shirazi, Abumoslem Jannesari, Pooya Torkzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[math]mV and 20[math]MHz clock frequency for 1[math]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[math]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[math][math]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[math]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [math][math][math]m for TBCCCP, [math][math][math]m for ITBCCCP2 and [math][math][math]m for ITBCCCP4.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-13T06:31:07Z
      DOI: 10.1142/S0218126620500139
       
  • Analysis, Design and Control of an Integrated Three-Level Buck Converter
           under DCM Operation
    • Authors: Wen-Ming Zheng, Wen-Liang Zeng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A three-level buck (TLB) converter has the characteristics of higher voltage conversion efficiency, lower inductor current ripples, output voltage ripples and voltage stresses on switches when compared with the buck converters in continuous conduction mode (CCM). With a TLB converter integrated on a chip, we cannot avoid its discontinuous conduction mode (DCM) operation due to a smaller inductance and load variation. In this paper, we’ll present and discuss the analysis, design and control of a TLB converter under DCM operation, implemented in a 65[math]nm CMOS process. Transistor level simulation results show that when the TLB converter operates at 100[math]MHz with a 5[math]nH on-chip inductor, a 10[math]nF output capacitor and a 10[math]nF flying capacitor, it can achieve an output conversion range of 0.7–1.2[math]V from a 2.4[math]V input supply, with a peak efficiency of 81.5%@120[math]mW. The output load transient response is 100[math]mV with 101[math]ns for undershoot, and 86[math]mV with 110[math]ns for overshoot when [math]–100[math]mA. The maximum output voltage ripple is less than 19[math]mV.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-13T06:31:06Z
      DOI: 10.1142/S0218126620500115
       
  • Deep Convolutional Neural Network with Optical Flow for Facial
           Micro-Expression Recognition
    • Authors: Qiuyu Li, Jun Yu, Toru Kurihara, Haiyan Zhang, Shu Zhan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Micro-expression is a kind of brief facial movements which could not be controlled by the nervous system. Micro-expression indicates that a person is hiding his true emotion consciously. Micro-expression recognition has various potential applications in public security and clinical medicine. Researches are focused on the automatic micro-expression recognition, because it is hard to recognize the micro-expression by people themselves. This research proposed a novel algorithm for automatic micro-expression recognition which combined a deep multi-task convolutional network for detecting the facial landmarks and a fused deep convolutional network for estimating the optical flow features of the micro-expression. First, the deep multi-task convolutional network is employed to detect facial landmarks with the manifold-related tasks for dividing the facial region. Furthermore, a fused convolutional network is applied for extracting the optical flow features from the facial regions which contain the muscle changes when the micro-expression appears. Because each video clip has many frames, the original optical flow features of the whole video clip will have high number of dimensions and redundant information. This research revises the optical flow features for reducing the redundant dimensions. Finally, a revised optical flow feature is applied for refining the information of the features and a support vector machine classifier is adopted for recognizing the micro-expression. The main contribution of work is combining the deep multi-task learning neural network and the fusion optical flow network for micro-expression recognition and revising the optical flow features for reducing the redundant dimensions. The results of experiments on two spontaneous micro-expression databases prove that our method achieved competitive performance in micro-expression recognition.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:22Z
      DOI: 10.1142/S0218126620500061
       
  • Third-Kind Chebyshev Wavelet Method for the Solution of Fractional Order
           Riccati Differential Equations
    • Authors: Sadiye Nergis Tural-Polat
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we derive the numerical solutions of the various fractional-order Riccati type differential equations using the third-kind Chebyshev wavelet operational matrix of fractional order integration (C3WOMFI) method. The operational matrix of fractional order integration method converts the fractional differential equations to a system of algebraic equations. The third-kind Chebyshev wavelet method provides sparse coefficient matrices, therefore the computational load involved for this method is not as severe and also the resulting method is faster. The numerical solutions agree with the exact solutions for non-fractional orders, and also the solutions for the fractional orders approach those of the integer orders as the fractional order coefficient [math] approaches to 1.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:21Z
      DOI: 10.1142/S0218126619502475
       
  • A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic
           Asynchronous Pipeline Design
    • Authors: Mansi Jhamb, Vinod Kumar Khera, Piyush Pant, Hinduja Pudi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:21Z
      DOI: 10.1142/S0218126619502347
       
  • An Efficient Load Forecasting in Predictive Control Strategy Using Hybrid
           Neural Network
    • Authors: Shweta Sengar, Xiaodong Liu
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Load forecasting is a difficult task, because the load series is complex and exhibits several levels of seasonality. The load at a given hour is dependent not only on the load at the previous day, but also on the load at the same hour on the previous day and previous week, and because there are many important exogenous variables that must be considered. Most of the researches were simultaneously concentrated on the number of input variables to be considered for the load forecasting problem. In this paper, we concentrate on optimizing the load demand using forecasting of the weather conditions, water consumption, and electrical load. Here, the neural network (NN) power load forecasting model clubbed with Levy-flight from cuckoo search algorithm is proposed, i.e., called hybrid neural network (HNN), and named as LF-HNN, where the Levy-flight is used to automatically select the appropriate spread parameter value for the NN power load forecasting model. The results from the simulation work have demonstrated the value of the LF-HNN approach successfully selected the appropriate operating mode to achieve optimization of the overall energy efficiency of the system using all available energy resources.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:20Z
      DOI: 10.1142/S0218126620500103
       
  • A 21-Level Bipolar Single-Phase Modular Multilevel Inverter
    • Authors: Sidharth Sabyasachi, Vijay B. Borghate, Santosh Kumar Maddugari
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a module for single-phase multilevel inverter topology. The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge. This results in reduction in filter cost and size. The module can be cascaded for high voltage applications. The same arrangement of voltage source magnitudes in first module is maintained in the remaining cascaded modules. The proposed topology is suitable for the applications like electric vehicle and emergency services like residences and hospitality industries, etc. A set of comparisons between the proposed and recently published topologies are provided to differentiate between them. The topology is simulated and verified in MATLAB/SIMULINK. A hardware prototype is developed in the laboratory for experimental confirmation with various conditions.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:20Z
      DOI: 10.1142/S0218126620500048
       
  • New Hardware Architecture for Self-Organizing Map Used for Color Vector
           Quantization
    • Authors: Khaled Ben Khalifa, Ahmed Ghazi Blaiech, Mehdi Abadi, Mohamed Hedi Bedoui
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [math] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:19Z
      DOI: 10.1142/S0218126620500024
       
  • An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future
           3D Chip-Multiprocessors
    • Authors: Arghavan Asad, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy, Farah Mohammadi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:19Z
      DOI: 10.1142/S0218126619502244
       
  • Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate
           the Reconfiguration Overheads in Reconfigurable Systems
    • Authors: I. Hariharan, M. Kannan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:18Z
      DOI: 10.1142/S0218126619502463
       
  • A Lion’s Pride Inspired Algorithm for VLSI Floorplanning
    • Authors: Lalin L Laudis, N Ramadass
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:17Z
      DOI: 10.1142/S0218126620500036
       
  • A Memetic Algorithm-Based Design Space Exploration for Datapath Resource
           Allocation During High-Level Synthesis
    • Authors: Shathanaa Rajmohan, N. Ramasubramanian
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      System designers have started adopting high-level synthesis (HLS) for architectural design because of the higher levels of abstraction offered. The HLS tools provide multiple design choices with tradeoff among different design parameters. Design Space Exploration (DSE) involves optimizing the synthesis options to achieve best tradeoffs among the metrics of interest. With the aim of exploring the design space in a feasible amount of time, we present a novel automated DSE approach. In particular, meeting the constraints presented by different parameters of interest is modeled as a multi-objective problem and solved using Memetic algorithm. The effectiveness of different variations of the Memetic algorithm in solving the DSE problem is studied and a Firefly algorithm-based solution is proposed with a novel probabilistic local search mechanism. The proposed approach is compared with existing solutions and the results prove that the proposed approach outperforms both existing solutions and other variations of Memetic algorithms in terms of convergence time and quality of results. In addition to that, a case study has been included to demonstrate the applicability of the approach. Results show that the proposed approach achieves a 33% improvement in cost, [math] improvement in speed and [math] improvement in hypervolume.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T08:21:17Z
      DOI: 10.1142/S0218126620500012
       
  • A New CPFSK Demodulation Approach for Software Defined Radio
    • Authors: Kayol Soares Mayer, Candice Müller, Fernando Cesar Comparsi de Castro, Maria Cristina Felippetto de Castro
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [math], which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes [math], [math] and [math], respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-02-08T07:33:56Z
      DOI: 10.1142/S0218126619502438
       
  • RDMKE: Applying Reuse Distance Analysis to Multiple GPU Kernel Executions
    • Authors: Mohsen Kiani, Amir Rajabzadeh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Modern GPUs can execute multiple kernels concurrently to keep the hardware resources busy and to boost the overall performance. This approach is called simultaneous multiple kernel execution (MKE). MKE is a promising approach for improving GPU hardware utilization. Although modern GPUs allow MKE, the effects of different MKE scenarios have not adequately studied by the researchers. Since cache memories have significant effects on the overall GPU performance, the effects of MKE on cache performance should be investigated properly. The present study proposes a framework, called RDMKE (short for Reuse Distance-based profiling in MKEs), to provide a method for analyzing GPU cache memory performance in MKE scenarios. The raw memory access information of a kernel is first extracted and then RDMKE enforces a proper ordering to the memory accesses so that it represents a given MKE scenario. Afterward, RDMKE employs reuse distance analysis (RDA) to generate cache-related performance metrics, including hit ratios, transaction counts, cache sets and Miss Status Holding Register reservation fails. In addition, RDMKE provides the user with the RD profiles as a useful locality metric. The simulation results of single kernel executions show a fair correlation between the generated results by RDMKE and GPU performance counters. Further, the simulation results of 28 two-kernel executions indicate that RDMKE can properly capture the nonlinear cache behaviors in MKE scenarios.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-31T08:20:39Z
      DOI: 10.1142/S0218126619502451
       
  • Determination of Worst-Case Data Using an Adaptive Surrogate Model for
           Real-Time System
    • Authors: Muhammad Rashid, Syed Abdul Baqi Shah, Muhammad Arif, Muhammad Kashif
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The estimation of worst-case execution time (WCET) is a critical activity in the analysis of real-time systems. Evolutionary algorithms are frequently employed for the determination of worst-case data, used in the estimation of WCET. However, in order to employ an evolutionary algorithm, several executions of the application program are required, either on the target hardware or using its simulator. Multiple executions of the application program consume a huge amount of time. In order to reduce the huge execution time, this paper proposes the use of an adaptive surrogate model. The initial training of surrogate model is performed with a cycle-accurate simulator. The initially trained model is then used to assist the evolutionary algorithm by predicting the execution time of an application program. However, contrary to the direct training approach, the surrogate model in this paper is updated (adapted) during the evolution process. The adaptive training of a surrogate model increases its prediction accuracy and reduces the overall time. The validity of proposed methodology is illustrated with multiple sorting algorithms, extensively used in real-time systems.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:28Z
      DOI: 10.1142/S021812662050005X
       
  • 2.4 GHz Real-Time Prototyping Tool for OFDM Channel Estimation using USRP2
           and LabVIEW
    • Authors: Kerem Küçük
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Wireless local area networks (WLANs) are currently playing an important role in serving the indoor traffic demand. Therefore, there is a need for software-defined radio platforms (SDRs) that can enable the solutions used in these systems to be tested in real environments as well as simulated results. In this paper, we present the SDR-based wireless receiver platform for determining the real-time WLANs performance and provide the comparison of the different channel estimation methods for IEEE 802.11g based on orthogonal frequency division multiplexing (OFDM) operations. The implementation of the receiver comprises the universal software radio peripheral and National Instruments LabVIEW. To determine the real-time receiver tool performance, we emphasized necessary signal processing techniques and different channel estimation methods with varying experimental parameters in real wireless environments. Experimental results report that the SDR-based receiver tool with the LabVIEW in real-time provides the throughput of the OFDM wireless network. The captured throughput performance concerning frame error rate by the receiver is also scrutinized with different channel estimation methods.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:26Z
      DOI: 10.1142/S0218126619502360
       
  • An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant
           Arithmetic
    • Authors: Ahmad Towhidy, Reza omidi, Karim Mohammadi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:21Z
      DOI: 10.1142/S021812661950244X
       
  • Analysis and FPGA Implementation of Zero-Forcing Receive Beamforming with
           Signal Space Diversity under Different Interleaving Techniques
    • Authors: Mustafa Anıl Reşat, Adem Çiçek, Serdar Özyurt, Enver Çavuş
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      We combine multiple-input multiple-output zero-forcing receive beamforming (ZFRBF) with time and spatial component interleaved signal space diversity (SSD) and analyze the system’s error performance and implementation complexity. A transreceiver system with two transmit and [math] ([math]) receive antennas is considered where the number of simultaneous substreams equals two. The error performance of the proposed scheme with binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) modulations is studied. Under the time component interleaved SSD case, we derive an exact average bit error probability expression for BPSK and a tight approximation on the average symbol error probability for QPSK. The signal constellation rotation angles are accordingly computed. Using a similar approach, the signal constellation rotation angles are also determined for the scenario of spatial component interleaved SSD. It is demonstrated that the performance of the original ZFRBF model can be improved significantly by utilizing SSD especially with the time interleaving method. Another contribution to the literature is to study hardware complexity of the proposed scheme on FPGA. It is shown that while achieving considerable performance gain, SSD introduces only an insignificant increase to the system complexity without any extra bandwidth or time slot usage.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-30T09:49:20Z
      DOI: 10.1142/S0218126620500073
       
  • A Miniaturized High-Gain (MHG) Ultra-Wideband Unidirectional Monopole
           Antenna for UWB Applications
    • Authors: J. Vijayalakshmi, G. Murugesan
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A miniaturized high-gain (MHG) ultra-wideband (UWB) unidirectional monopole antenna with defected ground structure (DGS) is designed for ultra-wideband applications. The MHG antenna is printed on the FR4 substrate material with an overall size of 26.6-mm [math] 29.3-mm [math] 1.6-mm, which operates over the UWB frequency range and achieves the bandwidth between 3.1[math]GHz and 10.6[math]GHz. This high-gain unidirectional antenna exhibits a peak gain of 7.20[math]dB with an efficiency of 95%. The compact antenna is a simple overlay design of circular and rectangular patches with the partial ground plane exhibiting high gain and better directivity. The overlay patch antenna acts as the radiator for wider bandwidth compared to the fundamental design of patch antenna and is matched to an SMA connector via 50[math][math] microstrip feed line. These simulated results are presented using HFSS software package. The designed antennas are fabricated and validated by using Agilent Vector Analyzer.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-29T09:21:53Z
      DOI: 10.1142/S021812661950230X
       
  • Chaotic Oscillator Based on Fractional Order Memcapacitor
    • Authors: Akif Akgul
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Many literatures have discussed fractional order memristor and memcapacitor-based chaotic oscillators but the entire oscillator model is considered to be of fractional order. My interest is to propose a nonlinear oscillator with considering only the memcapacitor element of fractional order. Hence, I propose a fractional order memcapacitor (FMC)-based novel chaotic oscillator. The complete mathematical model for the proposed oscillator is derived and presented in this paper. The dimensionless state equations are then analyzed by using the equilibrium points and their stability, Eigen values, Kaplan–Yorke dimensions and Lyapunov exponents. To understand the complete dynamical behavior, bifurcation graphs are obtained and presented. Finally, the proposed fractional memcapacitor oscillator is implemented by using the shelf components.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:42Z
      DOI: 10.1142/S0218126619502396
       
  • AFBV: A High-Performance Network Flow Classification Method for
           Multi-Dimensional Fields and FPGA Implementation
    • Authors: Ling Zheng, Zhiliang Qiu, Weina Wang, Weitao Pan, Shiyong Sun, Ya Gao
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[math]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:40Z
      DOI: 10.1142/S0218126619502372
       
  • Automatic Test Pattern Generation Through Boolean Satisfiability for
           Testing Bridging Faults
    • Authors: Hossein Mokhtarnia, Shahram Etemadi Borujeni, Mohammad Saeed Ehsani
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:39Z
      DOI: 10.1142/S0218126619502402
       
  • Study and Design of Single and Double Layer Square Patch Antennas for UWB
           Applications
    • Authors: Soufian Lakrit, Hassan Ammor, Soufiane Matah, Jaouad Terhzaz, Abdelouahd Tribak
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents the design of Single and Double Layer microstrip patch antennas for ultra-wideband applications. This structure consists of a square patch with a partial ground plane, fed by a 50[math][math] microstrip line. This antenna is designed for a system to detect malignant tumors by microwave imaging. Prototypes of the two antennas are fabricated and tested with a network analyzer. The proposed antenna can achieve an ultra-wide bandwidth with VSWR[math]2 from 3.82[math]GHz to 11.72[math]GHz for single layer antenna and from 3.2[math]GHz to 10.95[math]GHz for double layer antenna, with stable and bi-directional radiation pattern. The gain is good and has a peak value of 6.5[math]dBi. The simulation of this antenna has been performed using Ansoft High Frequency Structure Simulator (HFSS) and Computer Simulation Technology-Microwave Studio (CST).
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-23T06:24:38Z
      DOI: 10.1142/S0218126619502335
       
  • Distributed Amplifier Based on Monolayer Graphene Field Effect Transistor
    • Authors: Ali Safari, Massoud Dousti, Mohammad Bagher Tavakoli
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Due to the ultra-high carrier mobility and ultralow resistivity of Graphene channel, a Graphene field effect transistor (GFET) is an interesting candidate for future RF and microwave electronics. In this paper, the introduction and review of existing compact circuit-level model of GFETs are presented. A compact GFET model based on drift-diffusion transport theory is then implemented in Verilog-A for RF/microwave circuit analysis. Finally, the GFET model is used to design a GFET-based distributed amplifier (DA) using advanced design system (ADS) tools. The simulation results demonstrate a gain of 8[math]dB, an input/output return loss less than [math]10[math]dB, [math]3[math]dB bandwidth from DC up to 5[math]GHz and a dissipation of about 60.45[math]mW for a 1.5[math]V power supply. The main performance characteristics of the distributed amplifier are compared with 0.18[math][math]m CMOS technology.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:04Z
      DOI: 10.1142/S0218126619502311
       
  • Compact, Programmable, Two-Stage Configuration for Implantable
           Biopotential Recording Amplifiers
    • Authors: Mohammad Hossein Maghami, Amir Masoud Sodagar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper proposes an area-efficient CMOS amplifier for neural recording applications. The proposed neural amplifier takes advantage of indirect negative feedback to realize a rather low upper [math]3-dB cutoff frequency. As a result, the capacitance needed to realize the cutoff frequency is so small that can be easily implemented on-chip. Moreover, the proposed circuit also employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. Designed based on a two-stage configuration, the amplifier provides tunable lower cutoff frequency and digitally-programmable upper cutoff frequency and voltage gain. The circuit is designed in a 0.18-[math]m technology, and consumes 0.022[math]mm2 and 0.27[math]mm2 of chip areas for single- and eight-channel designs, respectively. Operated with a supply voltage of 1.8[math]V, power consumption of the proposed amplifier is 36.7[math][math]W with the simulated input-referred noise of 4[math][math] over 1[math]Hz–10[math]kHz for each channel. The amplifier also provides an output swing of 0.95 Vpp with a total harmonic distortion of [math]50[math]dB at the frequency of 1[math]kHz.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:03Z
      DOI: 10.1142/S0218126619200093
       
  • Efficient PSoC Implementation of Modular Multiplication and Exponentiation
           Based on Serial-Parallel Combination
    • Authors: M. Issad, B. Boudraa, M. Anane, A. M. Bellemou
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than the input data length. The design must be scalable to support different security levels. The implementation achieves optimums execution time and HW resources number. In order to satisfy these constraints, Montgomery Power Ladder (MPL) and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution times. The application for 1024-bits data length shows that the MMM run in 6.24[math][math]s and requires 647 slices. The ME is executed in 6.75[math]ms using 2881 slices.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:01Z
      DOI: 10.1142/S0218126619502293
       
  • Wide Tuning Range Varactorless Tunable Active Inductor-Based Voltage
           Controlled Oscillator for Wireless Applications
    • Authors: Omar Faruqe, Md Tawfiq Amin
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90[math]nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46[math]GHz for the tuning voltage of 0.3–1.5[math]V. It consumes a low dc power ranging from 2.44[math]mW to 4.79[math]mW for the specified tuning range. The variation of phase noise ranges from [math][math]dBc/Hz to [math][math]dBc/Hz at 1[math]MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of [math][math]dBc/Hz with a differential output power of 1.8[math]dBm at tuning voltage of 0.7[math]V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:01Z
      DOI: 10.1142/S0218126619502426
       
  • Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection
    • Authors: Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      High data rates and error-rate performance approaching close to theoretical limits are key trends for evolving digital wireless communication applications. To address the first requirement, multiple-input multiple-output (MIMO) techniques are adopted in emergent wireless communication standards and applications. On the other hand, turbo concept is used to alleviate the destructive effects of the channel and ensure error-rate performance close to theoretical limits. At the receiver side, the incorporation of MIMO techniques and turbo processing leads to increased complexity that has a severe impact on computation speed, power consumption and implementation area. Because of its increased complexity, the detector is considered critical among all receiver components. Low-complexity algorithms are developed at the cost of decreased performance. Minimum mean-squared error (MMSE) solution with iterative detection and decoding shows an acceptable tradeoff. In this paper, the complexity of the MMSE algorithm in turbo detection context is investigated thoroughly. Algorithmic computations are surveyed to extract the characteristics of all involved parameters. Consequently, several decompositions are applied leading to enhanced performance and to a significant reduction of utilized computations. The complexity of the algorithm is evaluated in terms of real-valued operations. The proposed decompositions save an average of [math] and [math] of required operations for 2 [math] 2 and 4 [math] 4 MIMO systems, respectively. In addition, the hardware implementation designed applying the devised simplifications and decompositions outperforms available state-of-the-art implementations in terms of maximum operating frequency, execution time, and performance.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:58:00Z
      DOI: 10.1142/S0218126619502281
       
  • A Transformation Methodology of Normal Nonlinear Resistors/Conductors to
           Inverses
    • Authors: C. Sánchez-López, V. H. Carbajal-Gómez, M. A. Carrasco-Aguilar, F. E. Morales-López
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      This work proposes a simple transformation methodology of normal nonlinear resistors/conductors to their inverted topologies in their floating and grounded versions (NNR/C). It is demonstrated that inverted topologies can also be configured as incremental or decremental nonlinear resistors/conductors. The main fingerprints of an NNR/C are holding up after the transformation and it is demonstrated that an inverse nonlinear resistor/conductor becomes a linear resistor/conductor when the operating frequency of the signal source decreases, inverse behavior in comparison with one memristor. Illustrative examples are given for floating and grounded nonlinear resistors and in both configurations. HSPICE simulation results are provided confirming the theory. Moreover, the normal and inverses resistors can be reconfigured in order to be used in future applications such as programmable analog circuits.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:59Z
      DOI: 10.1142/S0218126619300113
       
  • An Electronically Controllable Voltage-Mode MOSFET-Only Single-Input
           Dual-Output Filter
    • Authors: Abdullah Yesil, Deniz Ozenli, Emre Arslan, Fırat Kacar
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A new design of voltage mode (VM), single-input dual-output MOSFET-only filter which has electronic tunability property is presented without using passive circuit elements like resistors and capacitors. The filter topology is able to realize low-pass (LP) and band-pass (BP) filter functions with using the same circuit configuration. The proposed filter is laid-out in the Cadence environment using 0.18-[math]m TSMC CMOS technology parameters. The layout area is only 344.4[math][math]m2 and the power consumption is about 170[math][math]W. Furthermore, variations in the center frequency of the BP filter are presented performing Monte Carlo (MC) analysis to reinforce the filter results. Also, the noise performance of the proposed filter is investigated and it is shown that the theoretical and simulation results are in very good agreement.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:59Z
      DOI: 10.1142/S0218126619502220
       
  • Dynamic Energy Reduction in TCAM Match-Line Sensing Using Charge-Sharing
           and Positive Feedback
    • Authors: Syed Iftekhar Ali, Safayat Bin Hakim
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Network routers use ternary content addressable memory (TCAM) for high-speed table look-up. A match-line (ML) sensing scheme for TCAM combining charge-sharing and positive feedback is presented. The objective is to simplify the ML sense amplifier (MLSA) of existing charge-sharing scheme while reducing ML energy consumption during look-up. The look-up has been performed in two steps. In the first step, a segment of each TCAM word is compared with the search key to detect large percentage of the mismatched words. The detected mismatched words are deactivated in the second step to reduce energy consumption. In the second step, the charge stored in a matched ML first segment is shared with second ML segment. Use of positive feedback in this step makes the MLSA circuit simple. Post-layout simulations implemented using 180[math]nm 1.8[math]V CMOS logic have been performed. In addition to lower scheme complexity and 16.5% reduction in circuit area, the proposed scheme provides dynamic energy saving up to 5.5% and peak power reduction of 52% compared to existing state-of-the-art charge-sharing technique.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:57Z
      DOI: 10.1142/S0218126619502384
       
  • Ultra-Wideband Bandpass Filter Based on a Multi-Stub Loaded Loop Resonator
    • Authors: Xiaodong Xie, Zhizhan Yang, Mingxing Deng
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      A multi-stub loaded loop resonator (MSLLR) is proposed in this paper, which exhibits five main resonant modes of interest. Then, an ultra-wideband (UWB) bandpass filter is developed on it. Through direct source/load coupling, two transmission zeros can be created at both sides of the passband of the filter, which improves its frequency selectivity. The measured results of the fabricated filter show that its bandwidth can cover the UWB frequency range and the return loss in the passband is greater than 12.9[math]dB. Frequency selectivity is improved due to two transmission zeros at both sides of the passband. Group delay variation is less than 0.48[math]ns in the passband, which is relatively flat.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:56Z
      DOI: 10.1142/S0218126619200081
       
  • A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field
           Effect Transistor Including the Capacitive Effects
    • Authors: Sudipta Bardhan, Manodipan Sahoo, Hafizur Rahaman
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ([math]), transconductance ([math]), gate to drain capacitance ([math]) and gate to source capacitance ([math]) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than [math] NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:55Z
      DOI: 10.1142/S0218126619502414
       
  • A Novel Dual-Band Concurrent Asymmetric Doherty Power Amplifier for
           Wireless Communications
    • Authors: Shaban Rezaei Borjlu, Massoud Dousti
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In this paper, a different dual-band asymmetric Doherty power amplifier (ADPA) with a novel dual-band bandpass filter (DBBPF) with quad-section stepped impedance resonators (SIRs) is presented. This specific DBBPF rejects the annoying frequencies of the second and third harmonics in the dual-band and contributes considerably to performance improvement of ADPA. This structure is confirmed with the design, simulation, implementation and testing of a 10 W GaN-based ADPA for global system for mobile communications (GSM) and worldwide interoperability for microwave access (WiMAX) applications at 1.84 and 3.5[math]GHz, respectively. In the measurement results, the ADPA defines a drain efficiency (DE) of 63.7% with an output power of 35[math]dBm and power gain is 14.2[math]dB, and a DE of 47.5% with an output power of 34.5[math]dBm and power gain is 10.4[math]dB at the 9[math]dB output power back-off (OBO) from the saturated output power in the two frequency bands. Linearity effects, applying 10[math]MHz 16 QAM signal and a 5[math]MHz WiMAX signal, display an adjacent channel leakage ratio of [math] and [math][math]dBc with the average output power of 36.8/36[math]dBm at 1.84/3.5[math]GHz, respectively.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-15T05:57:54Z
      DOI: 10.1142/S0218126619502359
       
  • A Novel LMMSE-EM Channel Estimator for High Mobility STBC-OFDM System
    • Authors: Jyoti Prasanna Patra, Poonam Singh
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      In time-selective fading channel, the Alamouti orthogonality principle is lost due to the variation of channel from symbol-to-symbol in space–time block-coded orthogonal frequency division multiplexing (STBC-OFDM) system and causes co-channel interference (CCI) effects. To combat the CCI effects, various signal detection schemes have been proposed earlier by assuming that a priori channel state information (CSI) is known to the receiver. However, in practice, the CSI is unknown and therefore accurate estimation of channel is required for efficient signal detection. In this paper, by exploiting circulant properties of the channel frequency response (CFR) autocorrelation matrix [math], we propose an efficient low complexity linear-minimum-mean-square-error (LMMSE) estimator. This estimator applies an expectation–maximization (EM) iterative process to reduce the computational complexity significantly. Finally, we compare the proposed LMMSE-EM estimator with conventional least square (LS) and LMMSE estimator in terms of performance and computational complexity. The simulation results show that the proposed LMMSE-EM estimator achieves exactly the same performance as the optimal LMMSE estimator with much lower computational complexity.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:26Z
      DOI: 10.1142/S0218126619502232
       
  • Memristor Based Planar Tunable RF Circuits
    • Authors: C. L. Palson, D. D. Krishna, B. R. Jose, J. Mathew, M. Ottavi
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Memristors have been recently proposed as an alternative to incorporate switching along with traditional CMOS circuits. Adaptive impedance and frequency tuning are an essential and challenging aspect in communication system design. To enable both, a matching network based on switchable capacitors with fixed inductors is proposed in this paper where the switching is done by memristive switches. This paper analyzes the operation of memristors as a switch and a matching network based on memristors which adaptively tunes with impedance and frequency. With three capacitor banks of each 0.5 pF resolution and two fixed inductors, matching for antenna impedance ranging from 20 to 200[math]Ohms and for frequencies ranging from 0.9 to 3.2[math]GHz is reported. Thereafter, an adaptive planar band-pass filter is implemented on CMOS technology with two metal layers. This adaptive frequency tunable band-pass filter uses a [math] network with resonator tanks in both arms that operates at 2.45 GHz. It is tunable from 2.8[math]GHz to 7.625[math]GHz range. This tunability is achieved using tunable spiral inductor based on memristive switches. The proposed filter layout is implemented and simulated in ANSYS Designer. The initialization and the programming circuitry to enable adaptive switching of the memristive devices has to be addressed. Since RF memristive devices are not commercially available, circuit level simulations are done as a proof of concept to validate the expected results.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:26Z
      DOI: 10.1142/S0218126619502256
       
  • Time Efficient Segmented Technique for Dynamic Programming Based
           Algorithms with FPGA Implementation
    • Authors: Talal Bonny, Ridhwan Al Debsi, Mohamed Basel Almourad
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Although dynamic programming (DP) is an optimization approach used to solve a complex problem fast, the time required to solve it is still not efficient and grows polynomially with the size of the input. In this contribution, we improve the computation time of the dynamic programming based algorithms by proposing a novel technique, which is called “SDP: Segmented Dynamic programming”. SDP finds the best way of splitting the compared sequences into segments and then applies the dynamic programming algorithm to each segment individually. This will reduce the computation time dramatically. SDP may be applied to any dynamic programming based algorithm to improve its computation time. As case studies, we apply the SDP technique on two different dynamic programming based algorithms; “Needleman–Wunsch (NW)”, the widely used program for optimal sequence alignment, and the LCS algorithm, which finds the “Longest Common Subsequence” between two input strings. The results show that applying the SDP technique in conjunction with the DP based algorithms improves the computation time by up to 80% in comparison to the sole DP algorithms, but with small or ignorable degradation in comparing results. This degradation is controllable and it is based on the number of split segments as an input parameter. However, we compare our results with the well-known heuristic FASTA sequence alignment algorithm, “GGSEARCH”. We show that our results are much closer to the optimal results than the “GGSEARCH” algorithm. The results are valid independent from the sequences length and their level of similarity. To show the functionality of our technique on the hardware and to verify the results, we implement it on the Xilinx Zynq-7000 FPGA.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:25Z
      DOI: 10.1142/S021812661950227X
       
  • A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity
    • Authors: R. Nagulapalli
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by [math]20[math]dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to [math] will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5[math]dB PSRR improvement and 7.5% improvement in sensitivity to [math]. The proposed solution consumes 180[math]nW power from 1[math]V power supply voltage and occupies 3300[math][math]m2 silicon area.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:25Z
      DOI: 10.1142/S0218126619502268
       
  • Hierarchical Optimization of Electric Vehicle System Charging Plan Based
           on the Scheduling Priority
    • Authors: Feng Ni, Linfang Yan, Ke Wu, Mengxuan Shi, Jianyu Zhou, Xia chen
      Abstract: Journal of Circuits, Systems and Computers, Ahead of Print.
      Unregulated charging of a large number of electric vehicles (EVs) simultaneously may cause electricity shortages and price spikes in the power market. This paper deals with the optimization of EV charging strategy using the priority sequence. Firstly, the evaluation indices such as the schedulable interval ratio, the emergency probability and the battery losses are proposed. Then a comprehensive evaluation system for the EV scheduling priority is established by adopting the entropy weight method to incorporate multiple indices. Based on the scheduling priority obtained, a double-hierarchical optimal model is proposed, taking into account the constraints such as the demand of the EV owner. Its upper objective aims to minimize the sum of the square of deviation between the actual and the required schedulable capacity of EV aggregator over every interval. The lower one minimizes the sum of EV scheduling priority sequence over the scheduling interval. Case studies with 100 EVs show that the hierarchical optimization model can assist EV aggregator in making effective charging scheme. It is also observed that better flexibility for dispatching EVs can be achieved using multiple indices with weights.
      Citation: Journal of Circuits, Systems and Computers
      PubDate: 2019-01-11T09:20:24Z
      DOI: 10.1142/S0218126619502219
       
 
 
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