A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z  

        1 2 | Last   [Sort by number of followers]   [Restore default list]

  Subjects -> ELECTRONICS (Total: 202 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advanced Materials Technologies     Hybrid Journal  
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 9)
Advances in Electronics     Open Access   (Followers: 99)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Power Electronics     Open Access   (Followers: 39)
Advancing Microelectronics     Hybrid Journal  
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 28)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 15)
Australian Journal of Electrical and Electronics Engineering     Hybrid Journal  
Batteries     Open Access   (Followers: 9)
Batteries & Supercaps     Hybrid Journal   (Followers: 4)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 31)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 2)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 9)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 304)
ECTI Transactions on Computer and Information Technology (ECTI-CIT)     Open Access  
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 2)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 123)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 108)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 103)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage     Hybrid Journal   (Followers: 1)
Energy Storage Materials     Full-text available via subscription   (Followers: 4)
EPE Journal : European Power Electronics and Drives     Hybrid Journal  
EPJ Quantum Technology     Open Access   (Followers: 1)
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 100)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 81)
IEEE Embedded Systems Letters     Hybrid Journal   (Followers: 56)
IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology     Hybrid Journal   (Followers: 2)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 52)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Letters on Electromagnetic Compatibility Practice and Applications     Hybrid Journal   (Followers: 3)
IEEE Magnetics Letters     Hybrid Journal   (Followers: 7)
IEEE Nanotechnology Magazine     Hybrid Journal   (Followers: 42)
IEEE Open Journal of Circuits and Systems     Open Access   (Followers: 2)
IEEE Open Journal of Industry Applications     Open Access   (Followers: 2)
IEEE Open Journal of the Industrial Electronics Society     Open Access   (Followers: 2)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 77)
IEEE Pulse     Hybrid Journal   (Followers: 5)
IEEE Reviews in Biomedical Engineering     Hybrid Journal   (Followers: 22)
IEEE Solid-State Circuits Letters     Hybrid Journal   (Followers: 2)
IEEE Solid-State Circuits Magazine     Hybrid Journal   (Followers: 13)
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 363)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 74)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 59)
IEEE Transactions on Autonomous Mental Development     Hybrid Journal   (Followers: 8)
IEEE Transactions on Biomedical Engineering     Hybrid Journal   (Followers: 38)
IEEE Transactions on Broadcasting     Hybrid Journal   (Followers: 13)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 26)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 45)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Geoscience and Remote Sensing     Hybrid Journal   (Followers: 221)
IEEE Transactions on Haptics     Hybrid Journal   (Followers: 4)
IEEE Transactions on Industrial Electronics     Hybrid Journal   (Followers: 76)
IEEE Transactions on Industry Applications     Hybrid Journal   (Followers: 40)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Learning Technologies     Full-text available via subscription   (Followers: 12)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 79)
IEEE Transactions on Services Computing     Hybrid Journal   (Followers: 4)
IEEE Transactions on Signal and Information Processing over Networks     Hybrid Journal   (Followers: 14)
IEEE Transactions on Software Engineering     Hybrid Journal   (Followers: 79)
IEEE Women in Engineering Magazine     Hybrid Journal   (Followers: 11)
IEEE/OSA Journal of Optical Communications and Networking     Hybrid Journal   (Followers: 16)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 59)
IET Smart Grid     Open Access   (Followers: 1)
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 12)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 3)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 10)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 25)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 12)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 37)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 9)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronic Science and Technology     Open Access   (Followers: 1)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 3)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 182)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 10)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal   (Followers: 1)
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 3)
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 11)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 31)
Journal of Power Electronics     Hybrid Journal   (Followers: 1)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Microelectronics and Solid State Electronics     Open Access   (Followers: 28)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal   (Followers: 1)
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 9)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 2)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 4)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 11)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 6)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 56)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Solid State Electronics Letters     Open Access  
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Transactions on Electrical and Electronic Materials     Hybrid Journal   (Followers: 1)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 7)
Ural Radio Engineering Journal     Open Access   (Followers: 1)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)

        1 2 | Last   [Sort by number of followers]   [Restore default list]

Similar Journals
Journal Cover
Journal of Low Power Electronics and Applications
Journal Prestige (SJR): 0.222
Citation Impact (citeScore): 1
Number of Followers: 10  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2079-9268
Published by MDPI Homepage  [222 journals]
  • JLPEA, Vol. 10, Pages 2: Temperature Compensation Circuit for ISFET Sensor

    • Authors: Ahmed Gaddour, Wael Dghais, Belgacem Hamdi, Mounir Ben Ali
      First page: 2
      Abstract: PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of diseases or susceptibility, wound healing, cellular internalization, etc. The ion-sensitive field effect transistor (ISFET) is capable of pH measurements. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. However, the extracted data from the sensor have been affected by the variation of the temperature. This paper presents a new integrated circuit that can enhance the immunity of ion-sensitive field effect transistors (ISFET) against the temperature. To achieve this purpose, the considered ISFET macro model is analyzed and validated with experimental data. Moreover, we investigate the temperature dependency on the voltage-current (I-V). Accordingly, an improved conditioning circuit is designed in order to reduce the temperature sensitivity on the measured pH values of the ISFET sensor. The numerical validation results show that the developed solution accurately compensates the temperature variation on the measured pH values at low power consumption.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-01-04
      DOI: 10.3390/jlpea10010002
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 3: Threshold Voltage Degradation for n-Channel
           4H-SiC Power MOSFETs

    • Authors: Esteban Guevara, Victor Herrera-Pérez, Cristian Rocha, Katherine Guerrero
      First page: 3
      Abstract: In this study, threshold voltage instability on commercial silicon carbide (SiC) power metal oxide semiconductor field electric transistor MOSFETs was evaluated using devices manufactured from two different manufacturers. The characterization process included PBTI (positive bias temperature instability) and pulsed IV measurements of devices to determine electrical parameters’ degradations. This work proposes an experimental procedure to characterize silicon carbide (SiC) power MOSFETs following two characterization methods: (1) Using the one spot drop down (OSDD) measurement technique to assess the threshold voltage explains temperature dependence when used on devices while they are subjected to high temperatures and different gate voltage stresses. (2) Measurement data processing to obtain hysteresis characteristics variation and the damage effect over threshold voltage. Finally, based on the results, it was concluded that trapping charge does not cause damage on commercial devices due to reduced value of recovery voltage, when a negative small voltage is applied over a long stress time. The motivation of this research was to estimate the impact and importance of the bias temperature instability for the application fields of SiC power n-MOSFETs. The importance of this study lies in the identification of the aforementioned behavior where SiC power n-MOSFETs work together with complementary MOS (CMOS) circuits.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-01-08
      DOI: 10.3390/jlpea10010003
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 4: Acknowledgement to Reviewers of Journal of Low
           Power Electronics and Applications in 2019

    • Authors: Journal Of Low Power Electronics And Applications Editorial Office; Journal Of Low Power Electronics And Applications Editorial Office
      First page: 4
      Abstract: The editorial team greatly appreciates the reviewers who have dedicated their considerable time and expertise to the journal’s rigorous editorial process over the past 12 months, regardless of whether the papers are finally published or not [...]
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-01-23
      DOI: 10.3390/jlpea10010004
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 5: High-Efficiency Switched-Capacitor DC-DC
           Converter with Three Decades of Load Current Range Using Adaptively-Biased

    • Authors: Anurag Veerabathini, Paul M. Furth
      First page: 5
      Abstract: A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the range of 12 μ A to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to <72 mV over the entire load current range.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-02-20
      DOI: 10.3390/jlpea10010005
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 6: An Acoustic Vehicle Detector and Classifier Using
           a Reconfigurable Analog/Mixed-Signal Platform

    • Authors: Swagat Bhattacharyya, Steven Andryzcik, David W. Graham
      First page: 6
      Abstract: The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a node architecture with low power consumption and in-the-field reconfigurability is evaluated in the context of an acoustic vehicle detection and classification (hereafter “AVDC”) scenario. The proposed architecture utilizes an always-on field-programmable analog array (FPAA) as a low-power event detector to selectively wake a microcontroller unit (MCU) when a significant event is detected. When awoken, the MCU verifies the vehicle class asserted by the FPAA and transmits the relevant information. The AVDC system is trained by solving a classification problem using a lexicographic, nonlinear programming algorithm. On a testing dataset comprising of data from ten cars, ten trucks, and 40 s of wind noise, the AVDC system has a detection accuracy of 100%, a classification accuracy of 95%, and no false alarms. The mean power draw of the FPAA is 43 μ W and the mean power consumption of the MCU and radio during its validation and wireless transmission process is 40.9 mW. Overall, this paper demonstrates that the utilization of an FPAA-based signal preprocessor can greatly improve the flexibility and power consumption of wireless sensor nodes.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-02-20
      DOI: 10.3390/jlpea10010006
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 7: Logic-in-Memory Computation: Is It Worth it'
           A Binary Neural Network Case Study

    • Authors: Andrea Coluccio, Marco Vacca, Giovanna Turvani
      First page: 7
      Abstract: Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is possible to obtain a local computation without the need to fetch data from the main memory. Although this concept introduces a lot of advantages from a theoretical point of view, its implementation could introduce an increasing complexity overhead of the memory itself, leading to a more sophisticated design flow. As a case study, Binary Neural Networks (BNNs) have been chosen. BNNs binarize both weights and inputs, transforming multiply-and-accumulate into a simpler bitwise logical operation while maintaining high accuracy, making them well-suited for a LiM implementation. In this paper, we present two circuits implementing a BNN model in CMOS technology. The first one, called Out-Of-Memory (OOM) architecture, is implemented following a standard Von Neumann structure. The same architecture was redesigned to adapt the critical part of the algorithm for a modified memory, which is also capable of executing logic calculations. By comparing both OOM and LiM architectures we aim to evaluate if Logic-in-Memory paradigm is worth it. The results highlight that LiM architectures have a clear advantage over Von Neumann architectures, allowing a reduction in energy consumption while increasing the overall speed of the circuit.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-02-22
      DOI: 10.3390/jlpea10010007
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 8: Body Bias Optimization for Real-Time Systems

    • Authors: Carlos C. Cortes Torres, Ryota Yasudo, Hideharu Amano
      First page: 8
      Abstract: The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional energy models cannot deal with the overhead of adjusting the BB voltage; thus, the models are not accurate. This paper presents a more accurate model for calculating energy overhead using an analytical double exponential expression for dynamic BB scaling and an optimization method based on nonlinear programming with consideration of the real-chip parameter constraints. The use of the proposed model resulted in an energy reduction of about 32% at lower frequencies in comparison with the conventional model. Moreover, the energy overhead was reduced to approximately 14% of the total energy consumption. This methodology provides a framework and design guidelines for real-time systems and computer-aided design.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-02-22
      DOI: 10.3390/jlpea10010008
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 9: AxCEM: Designing Approximate Comparator-Enabled

    • Authors: Samar Ghabraei, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
      First page: 9
      Abstract: Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often suggests employing approximate computing to improve the energy-efficiency, performance, and area of floating-point multipliers. Prior work has shown that employing hardware-oriented approximation for computing the mantissa product may result in significant system energy reduction at the cost of an acceptable computational error. This article examines the design of an approximate comparator used for preforming mantissa products in the floating-point multipliers. First, we illustrate the use of exact comparators for enhancing power, area, and delay of floating-point multipliers. Then, we explore the design space of approximate comparators for designing efficient approximate comparator-enabled multipliers (AxCEM). Our simulation results indicate that the proposed architecture can achieve a 66% reduction in power dissipation, another 66% reduction in die-area, and a 71% decrease in delay. As compared with the state-of-the-art approximate floating-point multipliers, the accuracy loss in DNN applications due to the proposed AxCEM is less than 0.06%.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-03-01
      DOI: 10.3390/jlpea10010009
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 10, Pages 10: Efficacy of Topology Scaling for Temperature and
           Latency Constrained Embedded ConvNets

    • Authors: Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera
      First page: 10
      Abstract: Embedded Convolutional Neural Networks (ConvNets) are driving the evolution of ubiquitous systems that can sense and understand the environment autonomously. Due to their high complexity, aggressive compression is needed to meet the specifications of portable end-nodes. A variety of algorithmic optimizations are available today, from custom quantization and filter pruning to modular topology scaling, which enable fine-tuning of the hyperparameters and the right balance between quality, performance and resource usage. Nonetheless, the implementation of systems capable of sustaining continuous inference over a long period is still a primary source of concern since the limited thermal design power of general-purpose embedded CPUs prevents execution at maximum speed. Neglecting this aspect may result in substantial mismatches and the violation of the design constraints. The objective of this work was to assess topology scaling as a design knob to control the performance and the thermal stability of inference engines for image classification. To this aim, we built a characterization framework to inspect both the functional (accuracy) and non-functional (latency and temperature) metrics of two ConvNet models, MobileNet and MnasNet, ported onto a commercial low-power CPU, the ARM Cortex-A15. Our investigation reveals that different latency constraints can be met even under continuous inference, yet with a severe accuracy penalty forced by thermal constraints. Moreover, we empirically demonstrate that thermal behavior does not benefit from topology scaling as the on-chip temperature still reaches critical values affecting reliability and user satisfaction.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2020-03-13
      DOI: 10.3390/jlpea10010010
      Issue No: Vol. 10, No. 1 (2020)
  • JLPEA, Vol. 9, Pages 29: TCAD Simulation and Analysis of Selective Buried
           Oxide MOSFET Dynamic Power

    • Authors: Rana Mahmoud, Narayanan Madathumpadical, Hasan Al-Nashash
      First page: 29
      Abstract: Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-09-22
      DOI: 10.3390/jlpea9040029
      Issue No: Vol. 9, No. 4 (2019)
  • JLPEA, Vol. 9, Pages 30: Energy-Performance Scalability Analysis of a
           Novel Quasi-Stochastic Computing Approach

    • Authors: Prashanthi Metku, Ramu Seva, Minsu Choi
      First page: 30
      Abstract: Stochastic computing (SC) is an emerging low-cost computation paradigm for efficient approximation. It processes data in forms of probabilities and offers excellent progressive accuracy. Since SC’s accuracy heavily depends on the stochastic bitstream length, generating acceptable approximate results while minimizing the bitstream length is one of the major challenges in SC, as energy consumption tends to linearly increase with bitstream length. To address this issue, a novel energy-performance scalable approach based on quasi-stochastic number generators is proposed and validated in this work. Compared to conventional approaches, the proposed methodology utilizes a novel algorithm to estimate the computation time based on the accuracy. The proposed methodology is tested and verified on a stochastic edge detection circuit to showcase its viability. Results prove that the proposed approach offers a 12–60% reduction in execution time and a 12–78% decrease in the energy consumption relative to the conventional counterpart. This excellent scalability between energy and performance could be potentially beneficial to certain application domains such as image processing and machine learning, where power and time-efficient approximation is desired.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-11-15
      DOI: 10.3390/jlpea9040030
      Issue No: Vol. 9, No. 4 (2019)
  • JLPEA, Vol. 9, Pages 20: Ultrasound Sensor-Based Wireless Power Transfer
           for Low-Power Medical Devices

    • Authors: Mustafa F. Mahmood, Saleem Latteef Mohammed, Sadik Kamel Gharghan
      First page: 20
      Abstract: Ultrasonic power transfer (UPT) is a promising method for wireless power transfer technology for low-power medical applications. Most portable or wearable medical devices are battery-powered. Batteries cannot be used for a long time and require periodic charging or replacement. UPT is a candidate technology for solving this problem. In this work, a 40-KHz ultrasound transducer was used to design a new prototype for supplying power to a wearable heart rate sensor for medical application. The implemented system consists of a power unit and heart rate measurement unit. The power unit includes an ultrasonic transmitter and receiver, rectifier, boost converter and super-capacitors. The heart rate measurement unit comprises measurement and monitoring circuits. UPT-based transfer power and efficiency were achieved using 1-, 4- and 8-Farad (F) super-capacitors. At 4 F, the system achieved 69.4% transfer efficiency and 0.318 mW power at 4 cm. In addition, 97% heart rate measurement accuracy was achieved relative to the benchmark device. The heart rate measurements were validated with statistical analysis. Our results show that this work outperforms previous works in terms of transfer power and efficiency with a 4-cm gap between the ultrasound transmitter and receiver.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-07-02
      DOI: 10.3390/jlpea9030020
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 21: Design and Analysis of SEU Hardened Latch for Low
           Power and High Speed Applications

    • Authors: Satheesh Kumar S, Kumaravel S
      First page: 21
      Abstract: Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-07-02
      DOI: 10.3390/jlpea9030021
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 22: FFC NMR Relaxometer with Magnetic Flux Density

    • Authors: António Roque, Duarte M. Sousa, Pedro Sebastião, Elmano Margato, Gil Marques
      First page: 22
      Abstract: This paper describes an innovative solution for the power supply of a fast field cycling (FFC) nuclear magnetic resonance (NMR) spectrometer considering its low power consumption, portability and low cost. In FFC cores, the magnetic flux density must be controlled in order to perform magnetic flux density cycles with short transients, while maintaining the magnetic flux density levels with high accuracy and homogeneity. Typical solutions in the FFC NMR literature use current control to get the required magnetic flux density cycles, which correspond to an indirect magnetic flux density control. The main feature of this new relaxometer is the direct control of the magnetic flux density instead of the magnet current, in contrast with other equipment available in the market. This feature is a great progress because it improves the performance. With this solution it is possible to compensate magnetic field disturbances and parasitic magnetic fields guaranteeing, among other possibilities, a field control below the earth magnetic field. Experimental results validating the developed solution and illustrating the real operation of this type of equipment are shown.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-07-13
      DOI: 10.3390/jlpea9030022
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 23: A New Approach for Optimizing Management of a
           Real Time Solar Charger Using the Firebase Platform Under Android

    • Authors: Mohamed Redha Rezoug, Rachid Chenni, Djamel Taibi
      First page: 23
      Abstract: With the continuous growth of energy consumption, the rationalization of energy has become a priority. The photovoltaic energy sector remains a major occupation for researchers in the field of production optimization or storage methods. The concept developed in this work is a mixed optimization approach for energy management during battery charging with a duty cycle. A selective collaborative algorithm intervenes to choose and use the appropriate results of the few techniques to optimize the charging time of a battery and estimate its state of charge by using the minimum possible tools. This is done using a collective database that is accessible in real time. It also effectively allows the synchronization of information between several customers. This approach is performed on a mobile application on android, through a Google Firebase platform that allows us to secure collaborative access between multiple customers and use the results of the calculations of some algorithms. It gives us the values obtained by the various sensors in real time to accelerate the charging speed of the battery. The validation of this approach led us to practice a few scenarios using an Arduino board to show that this approach has a better performance.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-07-16
      DOI: 10.3390/jlpea9030023
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 24: Memristor-Based Loop Filter Design for Phase
           Locked Loop

    • Authors: Naheem Olakunle Adesina, Ashok Srivastava
      First page: 24
      Abstract: The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-07-29
      DOI: 10.3390/jlpea9030024
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 25: Reconfigurable Analog Preprocessing for Efficient
           Asynchronous Analog-to-Digital Conversion

    • Authors: Brandon M. Kelly, Alexander T. DiLello, David W. Graham
      First page: 25
      Abstract: Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-08-12
      DOI: 10.3390/jlpea9030025
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 26: CMOS Inverter as Analog Circuit: An Overview

    • Authors: Woorham Bae
      First page: 26
      Abstract: Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-08-20
      DOI: 10.3390/jlpea9030026
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 27: Synchronous Counter Design Using Novel Level
           Sensitive T-FF in QCA Technology

    • Authors: Majeed, Alkaldy, bin Zainal, Bin MD Nor
      First page: 27
      Abstract: The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-09-05
      DOI: 10.3390/jlpea9030027
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 28: Multiple-Output DC-DC Converters with a Reduced
           Number of Active and Passive Components

    • Authors: Mert Turhan, Juan C. Castellanos, Marcel A. M. Hendrix, Jorge L. Duarte, Elena A. Lomonova
      First page: 28
      Abstract: Multiple-output converters have been widely used where individual outputs are required. Compared with conventional separate converters, the advantage of multiple outputs is to have a lower number of active and passive components. In this paper, first, a pulse-width-modulation (PWM)-pulse-frequency-modulation (PFM) method is used for two-output converters that have only one coil and one active switch. Secondly, three-output converter topologies are proposed where the third output is controlled by phase delay (PD). These converters need only two coils and two active switches to regulate three outputs. How to obtain PD at different switching frequencies is discussed next, and a PWM-PFM-PD controlled five-output buck converter is presented. The proposed solution uses only two active switches and two magnetic cores to adjust five-output voltages independently. A modeling and digital control method are proposed in order to regulate the five output voltages. A prototype circuit with independent 15 V/1.5 A, 12 V/1.5 A, 5 V/0.8 A, −5 V/0.6 A and 3.3 V/0.45 A outputs is assembled to validate the analysis, and it was proved that it regulates the output voltages at different loads.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-09-18
      DOI: 10.3390/jlpea9030028
      Issue No: Vol. 9, No. 3 (2019)
  • JLPEA, Vol. 9, Pages 13: Improving the Performance of Turbo-Coded Systems
           under Suzuki Fading Channels

    • Authors: Ali J. Al-Askery, Ali Al-Naji, Mohammed Sameer Alsabah
      First page: 13
      Abstract: In this paper, the performance of coded systems is considered in the presence of Suzuki fading channels, which is a combination of both short-fading and long-fading channels. The problem in manipulating a Suzuki fading model is the complicated integration involved in the evaluation of the Suzuki probability density function (PDF). In this paper, we calculated noise PDF after the zero-forcing equalizer (ZFE) at the receiver end with several approaches. In addition, we used the derived PDF to calculate the log-likelihood ratios (LLRs) for turbo-coded systems, and results were compared to Gaussian distribution-based LLRs. The results showed a 2 dB improvement in performance compared to traditional LLRs at 10 − 6 of the bit error rate (BER) with no added complexity. Simulations were obtained utilizing the Matlab program, and results showed good improvement in the performance of the turbo-coded system with the proposed LLRs compared to Gaussian-based LLRs.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-03-29
      DOI: 10.3390/jlpea9020013
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 14: PEDOT: PSS Thermoelectric Generators Printed on
           Paper Substrates

    • Authors: Henrik Andersson, Pavol Šuly, Göran Thungström, Magnus Engholm, Renyun Zhang, Jan Mašlík, Håkan Olin
      First page: 14
      Abstract: Flexible electronics is a field gathering a growing interest among researchers and companies with widely varying applications, such as organic light emitting diodes, transistors as well as many different sensors. If the circuit should be portable or off-grid, the power sources available are batteries, supercapacitors or some type of power generator. Thermoelectric generators produce electrical energy by the diffusion of charge carriers in response to heat flux caused by a temperature gradient between junctions of dissimilar materials. As wearables, flexible electronics and intelligent packaging applications increase, there is a need for low-cost, recyclable and printable power sources. For such applications, printed thermoelectric generators (TEGs) are an interesting power source, which can also be combined with printable energy storage, such as supercapacitors. Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate), or PEDOT:PSS, is a conductive polymer that has gathered interest as a thermoelectric material. Plastic substrates are commonly used for printed electronics, but an interesting and emerging alternative is to use paper. In this article, a printed thermoelectric generator consisting of PEDOT:PSS and silver inks was printed on two common types of paper substrates, which could be used to power electronic circuits on paper.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-03-30
      DOI: 10.3390/jlpea9020014
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 15: Voltage-Controlled Magnetic Anisotropy MeRAM
           Bit-Cell over Event Transient Effects

    • Authors: Nilson Maciel, Elaine C. Marques, Lirida Naviner, Hao Cai, Jun Yang
      First page: 15
      Abstract: Magnetic tunnel junction (MTJ) with a voltage-controlled magnetic anisotropy (VCMA) effect has been introduced to achieve robust non-volatile writing control with an electric field or a switching voltage. However, continuous technology scaling down makes circuits more susceptible to temporary faults. The reliability of VCMA-MTJ-based magnetoelectric random access memory (MeRAM) can be impacted by environmental disturbances because a radiation strike on the access transistor could introduce write and read failures in 1T-1MTJ MeRAM bit-cells. In this work, Single-Event Transient (SET) effects on a VCMA-MTJ-based MeRAM in 28 nm FDSOI CMOS technology are investigated. Results show the minimum SET charge Q c required to reach the access transistor associated with the striking time that can lead to an unsuccessful switch, that is, an error in the writing process (write failure). The synchronism between the fluctuations of the magnetic field in the MTJ free layer and the moment of the write pulse is also analyzed in terms of SET robustness. Moreover, results show that the minimum Q c value can vary more than 100 % depending on the magnetic state of the MTJ and the width of the access transistor. In addition, the most critical time against the SET occurrence may be before or after the write pulse depending on the magnetic state of the MTJ.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-04-05
      DOI: 10.3390/jlpea9020015
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 16: Novel Approaches for Efficient Delay-Insensitive

    • Authors: Florian Huemer, Andreas Steininger
      First page: 16
      Abstract: The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive communication channels according to the protocols (return-to-zero versus non-return-to-zero) and with respect to the codes (constant-weight versus systematic), with each solution having its specific pros and cons. From a higher abstraction, however, these protocols and codes represent corner cases of a more comprehensive solution space, and an exploration of this space promises to yield interesting new approaches. This is exactly what we do in this paper. More specifically, we present a novel coding scheme that combines the benefits of constant-weight codes, namely simple completion detection, with those of systematic codes, namely zero-effort decoding. We elaborate an approach for composing efficient “Partially Systematic Constant Weight” codes for a given data word length. In addition, we explore cost-efficient and orphan-free implementations of completion detectors for both, as well as suitable encoders and decoders. With respect to the protocols, we investigate the use of multiple spacers in return-to-zero protocols. We show that having a choice between multiple spacers can be beneficial with respect to energy efficiency. Alternatively, the freedom to choose one of multiple spacers can be leveraged to transfer information, thus turning the original return-to-zero protocol into a (very basic version of a) non-return-to-zero protocol. Again, this intermediate solution can combine benefits from both extremes. For all proposed solutions we provide quantitative comparisons that cover the whole relevant design space. In particular, we derive coding efficiency, power efficiency, as well as area effort for pipelined and non-pipelined communication channels. This not only gives evidence for the benefits and limitations of the presented novel schemes—our hope is that this paper can serve as a reference for designers seeking an optimized delay-insensitive code/protocol/implementation for their specific application.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-04-06
      DOI: 10.3390/jlpea9020016
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 17: Implementing Adaptive Voltage Over-Scaling:
           Algorithmic Noise Tolerance vs. Approximate Error Detection

    • Authors: Roberto Giorgio Rizzo, Andrea Calimera
      First page: 17
      Abstract: Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-04-21
      DOI: 10.3390/jlpea9020017
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 18: Aggressive Exclusion of Scan Flip-Flops from
           Compression Architecture for Better Coverage and Reduced TDV: A Hybrid

    • Authors: Pralhadrao V. Shantagiri, Rohit Kapur
      First page: 18
      Abstract: Scan-based structural testing methods have seen numerous inventions in scan compression techniques to reduce TDV (test data volume) and TAT (test application time). Compression techniques lead to test coverage (TC) loss and test patterns count (TPC) inflation when higher compression ratio is targeted. This happens because of the correlation issues introduced by these techniques. To overcome this issue, we propose a new hybrid scan compression technique, the aggressive exclusion (AE) of scan cells from compression for increasing overall TC and reduce TPC. This is achieved by excluding scan cells which contribute to 12% to 43% of overall care bits from compression architecture, placing them in multiple scan chains with dedicated scan-data-in and scan-data-out ports. The selection of scan cells to be excluded from the compression technique is done based on a detailed analysis of the last 95% of the patterns from a pattern set to reduce correlations. Results show improvements in TC of up to 1.33%, and reductions in TPC of up to 77.13%.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-05-29
      DOI: 10.3390/jlpea9020018
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 19: ILP Based Power-Aware Test Time Reduction Using
           On-Chip Clocking in NoC Based SoC

    • Authors: Harikrishna Parmar, Usha Mehta
      First page: 19
      Abstract: Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-06-17
      DOI: 10.3390/jlpea9020019
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 1: Modularity for Paralleling Different Rated Power
           Supplies Using Multi-Phase Switching Methods

    • Authors: Ping-Hui Lee, Yi-Te Chiang, Fan-Ren Chang
      First page: 1
      Abstract: This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can reduce power dissipation. The control module includes switches and a micro-programmed controlled unit that realizes the modularity by using multi-phase switching methods. The proposed module was studied, and experiments of two rated power supplies (60 and 45 W) were conducted to verify the studied results.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-16
      DOI: 10.3390/jlpea9010001
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 2: Acknowledgement to Reviewers of Journal of Low
           Power Electronics and Applications in 2018

    • Authors: Journal of Low Power Electronics; Applications Editorial Office
      First page: 2
      Abstract: Rigorous peer-review is the corner-stone of high-quality academic publishing [...]
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-16
      DOI: 10.3390/jlpea9010002
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 3: A New Multi-Bit Flip-Flop Merging Mechanism for
           Power Consumption Reduction in the Physical Implementation Stage of ICs

    • Authors: Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri, Nabil Hmina
      First page: 3
      Abstract: Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-21
      DOI: 10.3390/jlpea9010003
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 4: Analog Architecture Complexity Theory Empowering
           Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems

    • Authors: Jennifer Hasler
      First page: 4
      Abstract: This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-21
      DOI: 10.3390/jlpea9010004
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 5: Power and Area Efficient Clock Stretching and
           Critical Path Reshaping for Error Resilience

    • Authors: Mini Jayakrishnan, Alan Chang, Tony Tae-Hyoung Kim
      First page: 5
      Abstract: Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-21
      DOI: 10.3390/jlpea9010005
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 6: High Level Current Modeling for Shaping
           Electromagnetic Emissions in Micropipeline Circuits

    • Authors: Sophie Germain, Sylvain Engels, Laurent Fesquet
      First page: 6
      Abstract: In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net determining the activation instants of the different micropipeline stages and an asymmetric Laplace distribution modeling the current peaks of the activated stages. The design flow exploits this current estimation for shaping the electromagnetic emissions by setting the controller delays of the micropipeline circuits. The delay adjustment is performed by a genetic algorithm, which iterates until the electromagnetic emissions match the targeted spectral mask. In order to evaluate the technique, an Advanced Encryption Standard (AES) circuit has been designed. We first observed that the obtained current curve fits well with a gate simulation. Then, after shaping the electromagnetic emissions, the simulation shows that the spectrum fits within the spectral mask.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-29
      DOI: 10.3390/jlpea9010006
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 7: DoS Attack Detection and Path Collision
           Localization in NoC-Based MPSoC Architectures

    • Authors: Cesar Giovanni Chaves, Siavoosh Payandeh Azad, Thomas Hollstein, Johanna Sepúlveda
      First page: 7
      Abstract: Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-05
      DOI: 10.3390/jlpea9010007
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 8: A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst
           Asynchronous Wake-Up Controller in FDSOI 28 nm

    • Authors: Jean-Frédéric Christmann, Florent Berthier, David Coriat, Ivan Miro-Panades, Eric Guthmuller, Sébastien Thuries, Yvain Thonnart, Adam Makosiej, Olivier Debicki, Frédéric Heitzmann, Alexandre Valentian, Pascal Vivet, Edith Beigné
      First page: 8
      Abstract: Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-14
      DOI: 10.3390/jlpea9010008
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 9: A Fresh View on the Microarchitectural Design of
           FPGA-Based RISC CPUs in the IoT Era

    • Authors: Giovanni Scotti, Davide Zoni
      First page: 9
      Abstract: The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-19
      DOI: 10.3390/jlpea9010009
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 10: Analytical Performance of the Threshold Voltage
           and Subthreshold Swing of CSDG MOSFET

    • Authors: Uchechukwu A. Maduagwu, Viranjay M. Srivastava
      First page: 10
      Abstract: In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-26
      DOI: 10.3390/jlpea9010010
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 11: Tolerating Permanent Faults in the Input Port of
           the Network on Chip Router

    • Authors: Hala J. Mohammed, Wameedh N. Flayyih, Fakhrul Z. Rokhani
      First page: 11
      Abstract: Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-27
      DOI: 10.3390/jlpea9010011
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 12: Experimental Evaluation of SAFEPOWER Architecture
           for Safe and Power-Efficient Mixed-Criticality Systems

    • Authors: Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Mikel Azkarate-Askasua, Peio Onaindia, Tomaso Poggi, Nera González Romero, Elena Quesada Gonzalez, Timmy Sundström, Salvador Peiró Frasquet, Patricia Balbastre, Tage Mohammadat, Johnny Öberg, Yosab Bebawy, Roman Obermaisser, Adele Maleki, Alina Lenz, Duncan Graham
      First page: 12
      Abstract: With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-03-11
      DOI: 10.3390/jlpea9010012
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 10, Pages 1: Energy-Efficient Architecture for CNNs Inference
           on Heterogeneous FPGA

    • Authors: Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
      First page: 1
      Abstract: Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-12-24
      DOI: 10.3390/jlpea10010001
      Issue No: Vol. 10, No. 1 (2019)
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Email: journaltocs@hw.ac.uk
Tel: +00 44 (0)131 4513762

Your IP address:
Home (Search)
About JournalTOCs
News (blog, publications)
JournalTOCs on Twitter   JournalTOCs on Facebook

JournalTOCs © 2009-