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  Subjects -> ELECTRONICS (Total: 179 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 78)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 315)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 269)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 105)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 92)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 191)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 66)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 71)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 24)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access  
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 168)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Journal of Low Power Electronics and Applications
Journal Prestige (SJR): 0.222
Citation Impact (citeScore): 1
Number of Followers: 9  

  This is an Open Access Journal Open Access journal
ISSN (Print) 2079-9268
Published by MDPI Homepage  [215 journals]
  • JLPEA, Vol. 9, Pages 13: Improving the Performance of Turbo-Coded Systems
           under Suzuki Fading Channels

    • Authors: Ali J. Al-Askery, Ali Al-Naji, Mohammed Sameer Alsabah
      First page: 13
      Abstract: In this paper, the performance of coded systems is considered in the presence of Suzuki fading channels, which is a combination of both short-fading and long-fading channels. The problem in manipulating a Suzuki fading model is the complicated integration involved in the evaluation of the Suzuki probability density function (PDF). In this paper, we calculated noise PDF after the zero-forcing equalizer (ZFE) at the receiver end with several approaches. In addition, we used the derived PDF to calculate the log-likelihood ratios (LLRs) for turbo-coded systems, and results were compared to Gaussian distribution-based LLRs. The results showed a 2 dB improvement in performance compared to traditional LLRs at 10 - 6 of the bit error rate (BER) with no added complexity. Simulations were obtained utilizing the Matlab program, and results showed good improvement in the performance of the turbo-coded system with the proposed LLRs compared to Gaussian-based LLRs.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-03-29
      DOI: 10.3390/jlpea9020013
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 14: PEDOT: PSS Thermoelectric Generators Printed on
           Paper Substrates

    • Authors: Henrik Andersson, Pavol Šuly, Göran Thungström, Magnus Engholm, Renyun Zhang, Jan Mašlík, Håkan Olin
      First page: 14
      Abstract: Flexible electronics is a field gathering a growing interest among researchers and companies with widely varying applications, such as organic light emitting diodes, transistors as well as many different sensors. If the circuit should be portable or off-grid, the power sources available are batteries, supercapacitors or some type of power generator. Thermoelectric generators produce electrical energy by the diffusion of charge carriers in response to heat flux caused by a temperature gradient between junctions of dissimilar materials. As wearables, flexible electronics and intelligent packaging applications increase, there is a need for low-cost, recyclable and printable power sources. For such applications, printed thermoelectric generators (TEGs) are an interesting power source, which can also be combined with printable energy storage, such as supercapacitors. Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate), or PEDOT:PSS, is a conductive polymer that has gathered interest as a thermoelectric material. Plastic substrates are commonly used for printed electronics, but an interesting and emerging alternative is to use paper. In this article, a printed thermoelectric generator consisting of PEDOT:PSS and silver inks was printed on two common types of paper substrates, which could be used to power electronic circuits on paper.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-03-30
      DOI: 10.3390/jlpea9020014
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 15: Voltage-Controlled Magnetic Anisotropy MeRAM
           Bit-Cell over Event Transient Effects

    • Authors: Nilson Maciel, Elaine C. Marques, Lirida Naviner, Hao Cai, Jun Yang
      First page: 15
      Abstract: Magnetic tunnel junction (MTJ) with a voltage-controlled magnetic anisotropy (VCMA) effect has been introduced to achieve robust non-volatile writing control with an electric field or a switching voltage. However, continuous technology scaling down makes circuits more susceptible to temporary faults. The reliability of VCMA-MTJ-based magnetoelectric random access memory (MeRAM) can be impacted by environmental disturbances because a radiation strike on the access transistor could introduce write and read failures in 1T-1MTJ MeRAM bit-cells. In this work, Single-Event Transient (SET) effects on a VCMA-MTJ-based MeRAM in 28 nm FDSOI CMOS technology are investigated. Results show the minimum SET charge Q c required to reach the access transistor associated with the striking time that can lead to an unsuccessful switch, that is, an error in the writing process (write failure). The synchronism between the fluctuations of the magnetic field in the MTJ free layer and the moment of the write pulse is also analyzed in terms of SET robustness. Moreover, results show that the minimum Q c value can vary more than 100 % depending on the magnetic state of the MTJ and the width of the access transistor. In addition, the most critical time against the SET occurrence may be before or after the write pulse depending on the magnetic state of the MTJ.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-04-05
      DOI: 10.3390/jlpea9020015
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 16: Novel Approaches for Efficient Delay-Insensitive

    • Authors: Florian Huemer, Andreas Steininger
      First page: 16
      Abstract: The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive communication channels according to the protocols (return-to-zero versus non-return-to-zero) and with respect to the codes (constant-weight versus systematic), with each solution having its specific pros and cons. From a higher abstraction, however, these protocols and codes represent corner cases of a more comprehensive solution space, and an exploration of this space promises to yield interesting new approaches. This is exactly what we do in this paper. More specifically, we present a novel coding scheme that combines the benefits of constant-weight codes, namely simple completion detection, with those of systematic codes, namely zero-effort decoding. We elaborate an approach for composing efficient “Partially Systematic Constant Weight” codes for a given data word length. In addition, we explore cost-efficient and orphan-free implementations of completion detectors for both, as well as suitable encoders and decoders. With respect to the protocols, we investigate the use of multiple spacers in return-to-zero protocols. We show that having a choice between multiple spacers can be beneficial with respect to energy efficiency. Alternatively, the freedom to choose one of multiple spacers can be leveraged to transfer information, thus turning the original return-to-zero protocol into a (very basic version of a) non-return-to-zero protocol. Again, this intermediate solution can combine benefits from both extremes. For all proposed solutions we provide quantitative comparisons that cover the whole relevant design space. In particular, we derive coding efficiency, power efficiency, as well as area effort for pipelined and non-pipelined communication channels. This not only gives evidence for the benefits and limitations of the presented novel schemes—our hope is that this paper can serve as a reference for designers seeking an optimized delay-insensitive code/protocol/implementation for their specific application.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-04-06
      DOI: 10.3390/jlpea9020016
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 17: Implementing Adaptive Voltage Over-Scaling:
           Algorithmic Noise Tolerance vs. Approximate Error Detection

    • Authors: Roberto Giorgio Rizzo, Andrea Calimera
      First page: 17
      Abstract: Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-04-21
      DOI: 10.3390/jlpea9020017
      Issue No: Vol. 9, No. 2 (2019)
  • JLPEA, Vol. 9, Pages 1: Modularity for Paralleling Different Rated Power
           Supplies Using Multi-Phase Switching Methods

    • Authors: Ping-Hui Lee, Yi-Te Chiang, Fan-Ren Chang
      First page: 1
      Abstract: This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can reduce power dissipation. The control module includes switches and a micro-programmed controlled unit that realizes the modularity by using multi-phase switching methods. The proposed module was studied, and experiments of two rated power supplies (60 and 45 W) were conducted to verify the studied results.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-16
      DOI: 10.3390/jlpea9010001
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 2: Acknowledgement to Reviewers of Journal of Low
           Power Electronics and Applications in 2018

    • Authors: Journal of Low Power Electronics; Applications Editorial Office
      First page: 2
      Abstract: Rigorous peer-review is the corner-stone of high-quality academic publishing [...]
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-16
      DOI: 10.3390/jlpea9010002
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 3: A New Multi-Bit Flip-Flop Merging Mechanism for
           Power Consumption Reduction in the Physical Implementation Stage of ICs

    • Authors: Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri, Nabil Hmina
      First page: 3
      Abstract: Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-21
      DOI: 10.3390/jlpea9010003
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 4: Analog Architecture Complexity Theory Empowering
           Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems

    • Authors: Jennifer Hasler
      First page: 4
      Abstract: This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-21
      DOI: 10.3390/jlpea9010004
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 5: Power and Area Efficient Clock Stretching and
           Critical Path Reshaping for Error Resilience

    • Authors: Mini Jayakrishnan, Alan Chang, Tony Tae-Hyoung Kim
      First page: 5
      Abstract: Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-21
      DOI: 10.3390/jlpea9010005
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 6: High Level Current Modeling for Shaping
           Electromagnetic Emissions in Micropipeline Circuits

    • Authors: Germain, Engels, Fesquet
      First page: 6
      Abstract: In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net determining the activation instants of the different micropipeline stages and an asymmetric Laplace distribution modeling the current peaks of the activated stages. The design flow exploits this current estimation for shaping the electromagnetic emissions by setting the controller delays of the micropipeline circuits. The delay adjustment is performed by a genetic algorithm, which iterates until the electromagnetic emissions match the targeted spectral mask. In order to evaluate the technique, an Advanced Encryption Standard (AES) circuit has been designed. We first observed that the obtained current curve fits well with a gate simulation. Then, after shaping the electromagnetic emissions, the simulation shows that the spectrum fits within the spectral mask.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-01-29
      DOI: 10.3390/jlpea9010006
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 7: DoS Attack Detection and Path Collision
           Localization in NoC-Based MPSoC Architectures

    • Authors: Cesar Chaves, Siavoosh Azad, Thomas Hollstein, Johanna Sepúlveda
      First page: 7
      Abstract: Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-05
      DOI: 10.3390/jlpea9010007
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 8: A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst
           Asynchronous Wake-Up Controller in FDSOI 28 nm

    • Authors: Jean-Frédéric Christmann, Florent Berthier, David Coriat, Ivan Miro-Panades, Eric Guthmuller, Sébastien Thuries, Yvain Thonnart, Adam Makosiej, Olivier Debicki, Frédéric Heitzmann, Alexandre Valentian, Pascal Vivet, Edith Beigné
      First page: 8
      Abstract: Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-14
      DOI: 10.3390/jlpea9010008
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 9: A Fresh View on the Microarchitectural Design of
           FPGA-Based RISC CPUs in the IoT Era

    • Authors: Giovanni Scotti, Davide Zoni
      First page: 9
      Abstract: The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-19
      DOI: 10.3390/jlpea9010009
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 10: Analytical Performance of the Threshold Voltage
           and Subthreshold Swing of CSDG MOSFET

    • Authors: Uchechukwu A. Maduagwu, Viranjay M. Srivastava
      First page: 10
      Abstract: In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-26
      DOI: 10.3390/jlpea9010010
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 11: Tolerating Permanent Faults in the Input Port of
           the Network on Chip Router

    • Authors: Hala J. Mohammed, Wameedh N. Flayyih, Fakhrul Z. Rokhani
      First page: 11
      Abstract: Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-02-27
      DOI: 10.3390/jlpea9010011
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 9, Pages 12: Experimental Evaluation of SAFEPOWER Architecture
           for Safe and Power-Efficient Mixed-Criticality Systems

    • Authors: Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Mikel Azkarate-Askasua, Peio Onaindia, Tomaso Poggi, Nera González Romero, Elena Quesada Gonzalez, Timmy Sundström, Salvador Peiró Frasquet, Patricia Balbastre, Tage Mohammadat, Johnny Öberg, Yosab Bebawy, Roman Obermaisser, Adele Maleki, Alina Lenz, Duncan Graham
      First page: 12
      Abstract: With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2019-03-11
      DOI: 10.3390/jlpea9010012
      Issue No: Vol. 9, No. 1 (2019)
  • JLPEA, Vol. 8, Pages 33: An Improved CMOS Design of Op-Amp Comparator with
           Gain Boosting Technique for Data Converter Circuits

    • Authors: Anil Khatak, Manoj Kumar, Sanjeev Dhull
      First page: 33
      Abstract: A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-09-25
      DOI: 10.3390/jlpea8040033
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 34: Towards Neuromorphic Learning Machines Using
           Emerging Memory Devices with Brain-Like Energy Efficiency

    • Authors: Vishal Saxena, Xinyu Wu, Ira Srivastava, Kehan Zhu
      First page: 34
      Abstract: The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-02
      DOI: 10.3390/jlpea8040034
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 35: Path Planning for Highly Automated Driving on
           Embedded GPUs

    • Authors: Jörg Fickenscher, Sandra Schmidt, Frank Hannig, Mohamed Bouzouraa, Jürgen Teich
      First page: 35
      Abstract: The sector of autonomous driving gains more and more importance for the car makers. A key enabler of such systems is the planning of the path the vehicle should take, but it can be very computationally burdensome finding a good one. Here, new architectures in ECU are required, such as GPU, because standard processors struggle to provide enough computing power. In this work, we present a novel parallelization of a path planning algorithm. We show how many paths can be reasonably planned under real-time requirements and how they can be rated. As an evaluation platform, an Nvidia Jetson board equipped with a Tegra K1 SoC was used, whose GPU is also employed in the zFAS ECU of the AUDI AG.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-02
      DOI: 10.3390/jlpea8040035
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 36: An Experimental Characterization for Injection
           Quantity of a High-pressure Injector in GDI Engines

    • Authors: Wen-Chang Tsai, Tung-Sheng Zhan
      First page: 36
      Abstract: The high-pressure (HP) injector is a highly dynamic component requiring careful voltage and pressure input modulation to achieve the required fuel injection quantities of gasoline direct injection (GDI) engines. Accurate fuel injection curves are a key influence for this technology, and therefore, will require an accurate estimation of fuel flow rate to be realized. In order to be driven to rapid response with respect to solenoid valve coils, HP injectors typically require to be designed to be capable of rapid response in GDI engines. In this paper, the design and analysis of the proposed injector drive circuit are presented. Next, the effects of total pulse width, injector supply voltage, fuel system pressure, and pulse width modulation (PWM) operation on fuel injection quantities of an HP injector are measured for achieving robust performance and stability in the presence of bounded errors of the GDI injectors due to total pulse width, injector’s supply voltage, fuel pressure and PWM operation. Additionally, the fuel injection quantities of the HP injector are measured by tuning the parameters of the injector drive circuit with the PWM operation. These are defined as the fuel injection curves. Finally, experimental results are provided for verification of the proposed injector drive circuit.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-03
      DOI: 10.3390/jlpea8040036
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 37: Physical Simulations of High Speed and Low Power
           NanoMagnet Logic Circuits

    • Authors: Giovanna Turvani, Laura D’Alessandro, Marco Vacca
      First page: 37
      Abstract: Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-08
      DOI: 10.3390/jlpea8040037
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 38: MB-CNN: Memristive Binary Convolutional Neural
           Networks for Embedded Mobile Devices

    • Authors: Arjun Pal Chowdhury, Pranav Kulkarni, Mahdi Nazm Bojnordi
      First page: 38
      Abstract: Applications of neural networks have gained significant importance in embedded mobile devices and Internet of Things (IoT) nodes. In particular, convolutional neural networks have emerged as one of the most powerful techniques in computer vision, speech recognition, and AI applications that can improve the mobile user experience. However, satisfying all power and performance requirements of such low power devices is a significant challenge. Recent work has shown that binarizing a neural network can significantly improve the memory requirements of mobile devices at the cost of minor loss in accuracy. This paper proposes MB-CNN, a memristive accelerator for binary convolutional neural networks that perform XNOR convolution in-situ novel 2R memristive data blocks to improve power, performance, and memory requirements of embedded mobile devices. The proposed accelerator achieves at least 13.26 × , 5.91 × , and 3.18 × improvements in the system energy efficiency (computed by energy × delay) over the state-of-the-art software, GPU, and PIM architectures, respectively. The solution architecture which integrates CPU, GPU and MB-CNN outperforms every other configuration in terms of system energy and execution time.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-13
      DOI: 10.3390/jlpea8040038
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 39: Ray Tracing Modeling of Electromagnetic
           Propagation for On-Chip Wireless Optical Communications

    • Authors: Franco Fuschini, Marina Barbiroli, Marco Zoli, Gaetano Bellanca, Giovanna Calò, Paolo Bassi, Vincenzo Petruzzelli
      First page: 39
      Abstract: Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-17
      DOI: 10.3390/jlpea8040039
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 40: Editorial for the Special Issue on “Quantum-Dot
           Cellular Automata (QCA) and Low Power Application”

    • Authors: Stefania Perri
      First page: 40
      Abstract: Challenges created by the trend of increasingly reducing the size of transistors have made necessary innovative technologies to limit undesirable impacts on the performance speed and power consumption of future designs. [...]
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-23
      DOI: 10.3390/jlpea8040040
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 41: A Novel Approach to Design SRAM Cells for Low
           Leakage and Improved Stability

    • Authors: Tripti Tripathi, Durg Singh Chauhan, Sanjay Kumar Singh
      First page: 41
      Abstract: The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-24
      DOI: 10.3390/jlpea8040041
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 42: A 0.7 V, Ultra-Wideband Common Gate LNA with
           Feedback Body Bias Topology for Wireless Applications

    • Authors: Vikram Singh, Sandeep K. Arya, Manoj Kumar
      First page: 42
      Abstract: An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-10-26
      DOI: 10.3390/jlpea8040042
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 43: Low-Cost Low-Power Acceleration of a Microwave
           Imaging Algorithm for Brain Stroke Monitoring

    • Authors: Imran Sarwar, Giovanna Turvani, Mario R. Casu, Jorge A. Tobon, Francesca Vipiana, Rosa Scapaticci, Lorenzo Crocco
      First page: 43
      Abstract: Microwave imaging can effectively image the evolution of a hemorrhagic stroke thanks to the dielectric contrast between the blood and the surrounding brain tissues. To keep low both the form factor and the power consumption in a bedside device, we propose implementing a microwave imaging algorithm for stroke monitoring in a programmable system-on-chip, in which a simple ARM-based CPU offloads to an FPGA the heavy part of the computation. Compared to a full-software implementation in the ARM CPU, we obtain a 5× speed increase with hardware acceleration without loss in accuracy and precision.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-01
      DOI: 10.3390/jlpea8040043
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 44: A Recent Progress of Spintronics Devices for
           Integrated Circuit Applications

    • Authors: Tetsuo Endoh, Hiroaki Honjo
      First page: 44
      Abstract: Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit torque (SOT), and electric field (E-field) effect on magnetic anisotropy. The NV memories using STT have been studied and developed most actively and are about to enter into the market by major semiconductor foundry companies. On the other hand, a development of the NV memories using other writing schemes are now underway. In this review article, first, the recent advancement of the spintronics device using STT and the NV memories using them are reviewed. Next, spintronics devices using the other two writing schemes (SOT and E-field) are briefly reviewed, including issues to be addressed for the NV memories application.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-13
      DOI: 10.3390/jlpea8040044
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 45: Including Liquid Metal into Porous Elastomeric
           Films for Flexible and Enzyme-Free Glucose Fuel Cells: A Preliminary

    • Authors: Denis Desmaële, Francesco La Malfa, Francesco Rizzi, Antonio Qualtieri, Massimo De Vittorio
      First page: 45
      Abstract: This communication introduces a new flexible elastomeric composite film, which can directly convert the chemical energy of glucose into electricity. The fabrication process is simple, and no specific equipment is required. Notably, the liquid metal Galinstan is exploited with a two-fold objective: (i) Galinstan particles are mixed with polydimethylsiloxane to obtain a highly conductive porous thick film scaffold; (ii) the presence of Galinstan in the composite film enables the direct growth of highly catalytic gold structures. As a first proof of concept, we demonstrate that when immersed in a 20 mM glucose solution, a 5 mm-long, 5 mm-wide and 2 mm-thick sample can generate a volumetric power density up to 3.6 mW·cm − 3 at 7 mA·cm − 3 and 0.51 V without using any enzymes.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-22
      DOI: 10.3390/jlpea8040045
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 46: Low-Complexity Loeffler DCT Approximations for
           Image and Video Coding

    • Authors: Diego F. G. Coelho, Renato J.  Cintra, Fábio M. Bayer, Sunera Kulasekera, Arjuna  Madanayake, Paulo  Martinez, Thiago L. T.  Silveira, Raíza S.  Oliveira, Vassil S. Dimitrov
      First page: 46
      Abstract: This paper introduced a matrix parametrization method based on the Loeffler discrete cosine transform (DCT) algorithm. As a result, a new class of 8-point DCT approximations was proposed, capable of unifying the mathematical formalism of several 8-point DCT approximations archived in the literature. Pareto-efficient DCT approximations are obtained through multicriteria optimization, where computational complexity, proximity, and coding performance are considered. Efficient approximations and their scaled 16- and 32-point versions are embedded into image and video encoders, including a JPEG-like codec and H.264/AVC and H.265/HEVC standards. Results are compared to the unmodified standard codecs. Efficient approximations are mapped and implemented on a Xilinx VLX240T FPGA and evaluated for area, speed, and power consumption.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-22
      DOI: 10.3390/jlpea8040046
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 47: Enabling Energy-Efficient Physical Computing
           through Analog Abstraction and IP Reuse

    • Authors: Jennifer Hasler, Aishwarya Natarajan, Sihwan Kim
      First page: 47
      Abstract: This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. ion is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. ion of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-24
      DOI: 10.3390/jlpea8040047
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 48: Towards Energy-Efficient and Secure Computing

    • Authors: Zhiming Zhang, Qiaoyan Yu
      First page: 48
      Abstract: Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives or mechanisms to ensure computing systems’ resilience against various security threats on hardware. This work also uses examples to discuss practical methods for securing the hardware for computing systems to achieve energy efficiency.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-27
      DOI: 10.3390/jlpea8040048
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 49: Enhancing Reliability of Tactical MANETs by
           Improving Routing Decisions

    • Authors: Salman M. Al-Shehri, Pavel Loskot
      First page: 49
      Abstract: Mobile ad-hoc networks (MANETs) have been primarily designed to enhance tactical communications in a battlefield. They provide dynamic connectivity without requiring any pre-existing infrastructure. Their multi-hop capabilities can improve radio coverage significantly. The nature of tactical MANET operations requires more specialized routing protocols compared to the ones which are used in commercial MANET. Routing decisions in MANETs are usually conditioned on signal-to-interference-plus-noise ratio (SINR) measurements. In order to improve routing decisions for use in highly dynamic tactical MANETs, this paper proposes to combine two different metrics to achieve reliable multicast in multi-hop ad hoc networks. The resulting protocol combining received signal strength (RSS) with SINR to make routing decisions is referred to as Link Quality Aware Ad-hoc On-Demand Distance Vector (LQA-AODV) routing. The proposed routing protocol can quickly adapt to dynamic changes in network topology and link quality variations often encountered in tactical field operations. Using computer simulations, the performance of proposed protocol is shown to outperform other widely used reactive routing protocols assuming several performance metrics.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-11-28
      DOI: 10.3390/jlpea8040049
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 50: Design and Evaluation of an Electrical

    • Authors: Vinicius Sirtoli, Kaue Morcelles, John Gomez, Pedro Bertemes-Filho
      First page: 50
      Abstract: Electrical Bioimpedance Spectroscopy (EIS) is a technique used to assess passive electrical properties of biological materials. EIS detects physiological and pathological conditions in animal tissues. Recently, the introduction of broadband excitation signals has reduced the measuring time for application techniques such as Electrical Bioimpedance Myography. Therefore, this work is aimed at proposing a prototype by using discrete interval binary sequences (DIBS), which is based on a system that holds a current source, impedance acquisition system, microcontroller and graphical user interface. Measurements between 5 Ω to 5 kΩ had impedance acquisition and phase angle errors of aproximately 2% and were lower than 3 degrees, respectively. Based on a proposed circuit, bioimpedance of the chest muscle (Pectoralis Major) was measured during isotonic exercise (push-up). As a result, our analyses have detected tiredness and fatigue. We have explored and proposed new parameters which assess such conditions, as both the maximum magnitude and tiredness coefficient. These parameters decrease exponentially with consecutive push-ups and were convergent in the majority of the sixteen days of measurement.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-12-15
      DOI: 10.3390/jlpea8040050
      Issue No: Vol. 8, No. 4 (2018)
  • JLPEA, Vol. 8, Pages 22: A Survey of Low Voltage and Low Power Amplifier

    • Authors: Anna Richelli, Luigi Colalongo, Zsolt Kovacs-Vajna, Giacomo Calvetti, Davide Ferrari, Marco Finanzini, Simone Pinetti, Enrico Prevosti, Jacopo Savoldelli, Stefano Scarlassara
      First page: 22
      Abstract: Reducing voltage supply is one of the most effective way to reduce the power consumption, but, on the other hand it is a challenging choice for the analog designers. In this paper, different topologies, well-suited for low voltage and ultra-low voltage supply, are depicted, investigated, designed in the same standard 180 nm technology and compared, highlighting the benefits and the possible applications.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-23
      DOI: 10.3390/jlpea8030022
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 23: Efficient 3D-TLM Modeling and Simulation for the
           Thermal Management of Microwave AlGaN/GaN HEMT Used in High Power
           Amplifiers SSPA

    • Authors: Karim Belkacemi, Rachida Hocine
      First page: 23
      Abstract: A three-dimensional thermal simulation investigation for the thermal management of GaN-on-SiC monolithic microwave integrated circuits (MMICs) of consisting multi-fingers (HEMTs) is presented. The purpose of this work is to demonstrate the utility and efficiency of the three-dimensional Transmission Line Matrix method (3D-TLM) in a thermal analysis of high power AlGaN/GaN heterostructures single gate and multi-fingers HEMT SSPA (solid state power amplifiers). The self-heating effects induce thermal cross-talk between individual fingers in multi-finger AlGaN/GaN that affect device performance and reliability. Gate-finger temperature differences only arise after a transient state, due to the beginning of thermal crosstalk which is attributed to the finite rate of heat diffusion between gate fingers. The TLM method accounts for the real geometrical structure and the non-linear thermal conductivities of GaN and SiC in order to improve the realistic calculations accuracy heat dissipation and thermal behavior of the device. In addition, two types of heat sources located on the top of GaN layer are considered in thermal simulations: Nano-scale hotspot as a pulsed wave heat source under gate and micro-scale hotspot as a continuous wave heat source, between gate and drain. Heat diffusion however, occurs not only between individual gate fingers (inter-finger) in a multi-finger HEMT, but also within each gate finger (intra-finger). To compare results, a Micro-Raman Spectroscopy experience is conducted to obtain a detailed and accurate temperature distribution. Good agreement between the microscopic spectral measurement and TLM simulation results is observed by accepting an error less than 2.2% relative to a maximum temperature. Results show that the 3D-TLM method is suitable for understanding heat management in particular for microwave devices AlGaN/GaN HEMTs SSPA amplifier. TLM method helps to select and locates the expected hot spots and to highlight the need of thermal study pre-design in order to minimize the system-level thermal dissipation and lead therefore to higher reliability.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-23
      DOI: 10.3390/jlpea8030023
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 24: Effectiveness of Molecules for Quantum Cellular
           Automata as Computing Devices

    • Authors: Yuri Ardesi, Azzurra Pulimeno, Mariagrazia Graziano, Fabrizio Riente, Gianluca Piccinini
      First page: 24
      Abstract: Notwithstanding the increasing interest in Molecular Quantum-Dot Cellular Automata (MQCA) as emerging devices for computation, a characterization of their behavior from an electronic standpoint is not well-stated. Devices are typically analyzed with quantum physics-based approaches which are far from the electronic engineering world and make it difficult to design, simulate and fabricate molecular devices. In this work, we define new figures of merits to characterize the molecules, which are based on the post-processing of results obtained from ab initio simulations. We define the Aggregated Charge (AC), the electric-field generated at the receiver molecule (EFGR), the Vin–Vout and Vin–AC transcharacteristics (VVT and VACT), the Vout maps (VOM) and the MQCA cell working zones (CWZ). These quantities are compatible with an electronic engineering point of view and can be used to analyze the capability of molecules to propagate information. We apply and verify the methodology to three molecules already proposed in the literature for MQCA and we state to which extent these molecules can be effective for computation. The adopted methodology provides the quantitative characterization of the molecules necessary for digital designers, to design digital circuits, and for technologists, to the future fabrication of MQCA devices.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-07-28
      DOI: 10.3390/jlpea8030024
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 25: Multi-Vdd Design for Content Addressable Memories
           (CAM): A Power-Delay Optimization Analysis

    • Authors: Siddhartha Joshi, Dawei Li, Seda Ogrenci-Memik, Grzegorz Deptuch, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran
      First page: 25
      Abstract: In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-07-30
      DOI: 10.3390/jlpea8030025
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 26: Energy Efficiency Due to a Common Global
           Timebase—Synchronizing FlexRay to 802.1AS Networks as a Foundation

    • Authors: Paul Milbredt, Efim Schick, Michael Hübner
      First page: 26
      Abstract: Modern automotive control applications require a holistic time-sensitive development. Nowadays, this is achieved by technologies specifically designed for the automotive domain, like FlexRay, which offer a fault-tolerant time synchronization mechanism built into the protocol. Currently, the automotive industry adopts the Ethernet within the car, not only for embedding consumer electronics, but also as a fast and reliable backbone for control applications. Still, low-cost but highly reliable sensors connected over the traditional Controller Area Network (CAN) deliver data needed for autonomous driving. To fusion the data efficiently among all, a common timebase is required. The alternative would be oversampling, which uses more time and energy, e.g., at least double the perception rates of sensors. Ethernet and CAN do require the latter by default. Hence, a global synchronization mechanism eases tremendously the design of a low power automotive network and is the foundation of a transparent global clock. In this article, we present the first step: Synchronizing legacy FlexRay networks to the upcoming Ethernet backbone, which will contain a precise clock over the generalized Precision Time Protocol (gPTP) defined in IEEE 802.1AS. FlexRay then could still drive its strengths with deterministic transmission behavior and possibly also serve as a redundant technology for fail-operational system design.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-08-17
      DOI: 10.3390/jlpea8030026
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 27: A 0.5 V 68 nW ECG Monitoring Analog Front-End for
           Arrhythmia Diagnosis

    • Authors: Avish Kosari, Jacob Breiholz, NingXi Liu, Benton H. Calhoun, David D. Wentzloff
      First page: 27
      Abstract: This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-08-17
      DOI: 10.3390/jlpea8030027
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 28: Exploiting Read/Write Asymmetry to Achieve
           Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold

    • Authors: Yunfei Gu, Dengxue Yan, Vaibhav Verma, Pai Wang, Mircea R. Stan, Xuan Zhang
      First page: 28
      Abstract: Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-08-24
      DOI: 10.3390/jlpea8030028
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 29: An Improved Proposed Single Phase Transformerless
           Inverter with Leakage Current Elimination and Reactive Power Capability
           for PV Systems Application

    • Authors: Fahad Almasoudi, Mohammad Matin
      First page: 29
      Abstract: Single-phase transformerless inverters are broadly studied in literature for residential-scale PV applications due to their great advantages in reducing system weight, cost and elevating system efficiency. The design of transformerless inverters is based on the galvanic isolation method to eliminate the generation of leakage current. Unfortunately, the use of the galvanic isolation method alone cannot achieve constant common mode voltage (CMV). Therefore, a complete elimination of leakage current cannot be achieved. In addition, modulation techniques of single-phase transformerless inverters are designed for the application of the unity power factor. Indeed, next-generation PV systems are required to support reactive power to enable connectivity to the utility grid. In this paper, a proposed single-phase transformerless inverter is modified with the clamping method to achieve constant CMV during all inverter operating modes. Furthermore, the modulation technique is modified by creating a new current path in the negative power region. As a result, a bidirectional current path is created in the negative power region to achieve reactive power generation. The simulation results show that the CMV is completely clamped at half the DC link voltage and the leakage current is almost completely eliminated. Furthermore, a reactive power generation is achieved with the modified modulation techniques. Additionally, the total harmonic distortion (THD) of the grid current with the conventional and a modified modulation technique is analyzed. The efficiency of the system is enhanced by using wide-bandgap (WBG) switching devices such as SiC MOSFET. It is observed that the efficiency of the system decreased with reactive power generation due to the bidirectional current path, which leads to increasing conduction losses.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-09-06
      DOI: 10.3390/jlpea8030029
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 30: Exponentially Adiabatic Switching in Quantum-Dot
           Cellular Automata

    • Authors: Subhash S. Pidaparthi, Craig S. Lent
      First page: 30
      Abstract: We calculate the excess energy transferred into two-dot and three-dot quantum dot cellular automata systems during switching events. This is the energy that must eventually be dissipated as heat. The adiabaticity of a switching event is quantified using the adiabaticity parameter of Landau and Zener. For the logically reversible operations of WRITE or ERASE WITH COPY, the excess energy transferred to the system decreases exponentially with increasing adiabaticity. For the logically irreversible operation of ERASE WITHOUT COPY, considerable energy is transferred and so must be dissipated, in accordance with the Landauer Principle. The exponential decrease in energy dissipation with adiabaticity (e.g., switching time) distinguishes adiabatic quantum switching from the usual linear improvement in classical systems.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-09-07
      DOI: 10.3390/jlpea8030030
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 31: Clock Topologies for Molecular Quantum-Dot
           Cellular Automata

    • Authors: Enrique Blair, Craig Lent
      First page: 31
      Abstract: Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few mobile charges. Device switching occurs through quantum mechanical inter-dot charge tunneling, and devices are interconnected via the electrostatic field. QCA devices are implemented using arrays of QCA cells. A molecular implementation of QCA may support THz-scale clocking or better at room temperature. Molecular QCA may be clocked using an applied electric field, known as a clocking field. A time-varying clocking field may be established using an array of conductors. The clocking field determines the flow of data and calculations. Various arrangements of clocking conductors are laid out, and the resulting electric field is simulated. It is shown that that control of molecular QCA can enable feedback loops, memories, planar circuit crossings, and versatile circuit grids that support feedback and memory, as well as data flow in any of the ordinal grid directions. Logic, interconnect and memory now become indistinguishable, and the von Neumann bottleneck is avoided.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-09-08
      DOI: 10.3390/jlpea8030031
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 32: Waxberry-Like Nanosphere Li4Mn5O12 as High
           Performance Electrode Materials for Supercapacitors

    • Authors: Peiyuan Ji, Yi Xi, Chengshuang Zhang, Chuanshen Wang, Chenguo Hu, Yuzhu Guan, Dazhi Zhang
      First page: 32
      Abstract: Porous materials have superior electrochemical performance owing to its their structure, which could increase the specific and contact area with the electrode. The spinel Li4Mn5O12 has a three-dimensional tunnel structure for a better diffusion path, which has the advantage of lithium ion insertion and extraction in the framework. However, multi-space spherical materials with single morphologies are rarely studied. In this work, waxberry-like and raspberry-like nanospheres for Li4Mn5O12 have been fabricated by the wet chemistry and solid-state methods for the first time. The diameter of a single waxberry- and raspberry-like nanosphere is about 1 μm and 600 nm, respectively. The specific capacitance of Li4Mn5O12 was 535 mF cm−2 and 147.25 F g−1 at the scan rate of 2 mV s−1, and the energy density was 110.7 Wh kg−1, remaining at 70% after 5000th charge-discharge cycles. Compared with raspberry-like nanosphere Li4Mn5O12, the waxberry-like nanoporous spinel Li4Mn5O12 shows the better electrochemical performance and stability; furthermore, these electrochemical performances have been improved greatly compared to the previous studies. All these results indicate that the waxberry-like nanoporous spinel Li4Mn5O12 could provide a potential application in high performance supercapacitors.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-09-11
      DOI: 10.3390/jlpea8030032
      Issue No: Vol. 8, No. 3 (2018)
  • JLPEA, Vol. 8, Pages 9: Opportunistic Design Margining for Area and Power
           Efficient Processor Pipelines in Real Time Applications

    • Authors: Mini Jayakrishnan, Alan Chang, Tony Kim
      First page: 9
      Abstract: The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-03-21
      DOI: 10.3390/jlpea8020009
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 10: An Ultra-Low Power 28 nm FD-SOI Low Noise
           Amplifier Based on Channel Aware Receiver System Analysis

    • Authors: Jennifer Zaini-Desevedavy, Frédéric Hameau, Thierry Taris, Dominique Morche, Patrick Audebert
      First page: 10
      Abstract: This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-04-16
      DOI: 10.3390/jlpea8020010
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 11: Correction: Alateeq, A. et al. Performance of the
           Soft-Charging Operation in Series of Step-Up Power Switched-Capacitor
           Converters. J. Low Power Electron. Appl. 2018, 8, 8

    • Authors: Ayoob Alateeq, Yasser Almalaq, Mohammad Matin
      First page: 11
      Abstract: After publication of the research paper [1] (, a confusion of the charge flow direction in Section 2 makes some analysis unclear and confusing [...]
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-04-19
      DOI: 10.3390/jlpea8020011
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 12: Review of Analog-To-Digital Conversion
           Characteristics and Design Considerations for the Creation of
           Power-Efficient Hybrid Data Converters

    • Authors: Seyed Alireza Zahrai, Marvin Onabajo
      First page: 12
      Abstract: This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-04-30
      DOI: 10.3390/jlpea8020012
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 13: Performance and Power Analysis of HPC Workloads
           on Heterogeneous Multi-Node Clusters

    • Authors: Filippo Mantovani, Enrico Calore
      First page: 13
      Abstract: Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance to be able to correlate performance and power figures within the same profiling and analysis tools. For this reason, we present a performance and energy-efficiency study aimed at demonstrating how a single tool can be used to collect most of the relevant metrics. In particular, we show how the same analysis techniques can be applicable on different architectures, analyzing the same HPC application on a high-end and a low-power cluster. The former cluster embeds Intel Haswell CPUs and NVIDIA K80 GPUs, while the latter is made up of NVIDIA Jetson TX1 boards, each hosting an Arm Cortex-A57 CPU and an NVIDIA Tegra X1 Maxwell GPU.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-05-04
      DOI: 10.3390/jlpea8020013
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 14: 0.45 v and 18 μA/MHz MCU SOC with Advanced
           Adaptive Dynamic Voltage Control (ADVC)

    • Authors: Uzi Zangi, Neil Feldman, Tzach Hadas, Noga Dayag, Joseph Shor, Alexander Fish
      First page: 14
      Abstract: An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K–80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45–1.1 V volts with a direct battery connection for an input voltage of 1.6–3.6 V. Measurement results show that the peak energy efficiency is 18μW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3–5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-05-09
      DOI: 10.3390/jlpea8020014
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 15: Optimization of Finite-Differencing Kernels for
           Numerical Relativity Applications

    • Authors: Roberto Alfieri, Sebastiano Bernuzzi, Albino Perego, David Radice
      First page: 15
      Abstract: A simple optimization strategy for the computation of 3D finite-differencing kernels on many-cores architectures is proposed. The 3D finite-differencing computation is split direction-by-direction and exploits two level of parallelism: in-core vectorization and multi-threads shared-memory parallelization. The main application of this method is to accelerate the high-order stencil computations in numerical relativity codes. Our proposed method provides substantial speedup in computations involving tensor contractions and 3D stencil calculations on different processor microarchitectures, including Intel Knight Landing.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-05-25
      DOI: 10.3390/jlpea8020015
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 16: A Sub-50 µm2, Voltage-Scalable,
           Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip
           Thermal Monitoring

    • Authors: Seongjong Kim, Mingoo Seok
      First page: 16
      Abstract: This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The sensor also exhibits high accuracy and voltage-scalability down to 0.4 V, allowing the sensor to be used in dynamic voltage frequency scaling systems without requiring extra power distribution or regulation. The compact footprint and voltage scalability enables our proposed sensor to be implemented in a digital standard-cell format, allowing aggressive sensor placement very close to target hotspots in digital blocks. The proposed sensor frontend prototyped in a 65 nm CMOS technology has a footprint of 30.1 µm2, 3σ-error of ±1.1 °C across 0 to 100 °C after one temperature point calibration, marking a significant improvement over existing sensors designed for dynamic thermal management in VLSI systems.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-05-30
      DOI: 10.3390/jlpea8020016
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 17: Security Implications for Ultra-Low Power
           Configurable SoC FPAA Embedded Systems

    • Authors: Jennifer Hasler, Sahil Shah
      First page: 17
      Abstract: We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for embedded IoT devices. These techniques offer computational capability to address network security concerns. This paper begins the discussion of security opportunities for, and issues using, FPAA devices for small embedded IoT platforms. These FPAAs enable devices often utilized for low-power context aware computation. Embedded FPAA devices have both positive Security attributes, as well as potential vulnerabilities. FPAA devices can be part of the resulting secure computation, such as implementing unique functions. FPAA devices can be used investigate security of analog/mixed signal capabilities. The paper concludes with summarizing key improvements for secure ultra-low power embedded FPAA devices.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-05
      DOI: 10.3390/jlpea8020017
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 18: Software and DVFS Tuning for Performance and
           Energy-Efficiency on Intel KNL Processors

    • Authors: Enrico Calore, Alessandro Gabbana, Sebastiano Fabio Schifano, Raffaele Tripiccione
      First page: 18
      Abstract: Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short). We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM) and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS) technique.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-11
      DOI: 10.3390/jlpea8020018
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 19: A Low-Power Voltage Reference Cell with a 1.5 V

    • Authors: Mir Mohammad Navidi, David W. Graham
      First page: 19
      Abstract: A low-power voltage reference cell for system-on-a-chip applications is presented in this paper. The proposed cell uses a combination of standard transistors and thick-oxide transistors to generate a voltage above 1 V. A design procedure is also presented for minimizing the temperature coefficient (TC) of the reference voltage. This circuit was fabricated in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. It generates a 1.52 V output with a TC of 42 ppm/∘C from −70 ∘C to 85 ∘C while consuming only 1.11 μW.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-14
      DOI: 10.3390/jlpea8020019
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 20: Physical, Electrical, and Reliability
           Considerations for Copper BEOL Layout Design Rules

    • Authors: Eitan N. Shauly
      First page: 20
      Abstract: The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 μm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-14
      DOI: 10.3390/jlpea8020020
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 21: A Top-Down Approach to Building Battery-Less
           Self-Powered Systems for the Internet-of-Things

    • Authors: Farah B. Yahya, Christopher J. Lukas, Benton H. Calhoun
      First page: 21
      Abstract: This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design choices that optimize the system and improve its reliability. We look into how to use these features to build the digital sub-system by determining the blocks to implement, the digital architecture, the clock rate of the system, the memory capacity, and the low power states. We also review how these features impact the choice of energy harvesting power management units.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-06-15
      DOI: 10.3390/jlpea8020021
      Issue No: Vol. 8, No. 2 (2018)
  • JLPEA, Vol. 8, Pages 1: SoC-Based Edge Computing Gateway in the Context of
           the Internet of Multimedia Things: Experimental Platform

    • Authors: Maher Jridi, Thibault Chapel, Victor Dorez, Guénolé Le Bougeant, Antoine Le Botlan
      First page: 1
      Abstract: This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-01-12
      DOI: 10.3390/jlpea8010001
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 2: A Bond Graph Approach for the Modeling and
           Simulation of a Buck Converter

    • Authors: Rached Zrafi, Sami Ghedira, Kamel Besbes
      First page: 2
      Abstract: This paper deals with the modeling of bond graph buck converter systems. The bond graph formalism, which represents a heterogeneous formalism for physical modeling, is used to design a sub-model of a power MOSFET and PiN diode switchers. These bond graph models are based on the device’s electrical elements. The application of these models to a bond graph buck converter permit us to obtain an invariant causal structure when the switch devices change state. This paper shows the usefulness of the bond graph device’s modeling to simulate an implicit bond graph buck converter.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-01-25
      DOI: 10.3390/jlpea8010002
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 3: Design of a Programmable Passive SoC for
           Biomedical Applications Using RFID ISO 15693/NFC5 Interface

    • Authors: Mayukh Bhattacharyya, Waldemar Gruenwald, Dirk Jansen, Leonhard Reindl, Jasmin Aghassi-Hagmann
      First page: 3
      Abstract: Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD).
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-01-31
      DOI: 10.3390/jlpea8010003
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 4: Acknowledgement to Reviewers of Journal of Low
           Power Electronics and Applications in 2017

    • Authors: Journal of Low Power Electronics; Applications Editorial Office
      First page: 4
      Abstract: Peer review is an essential part in the publication process, ensuring that Journal of Low Power Electronics and Applications maintains high quality standards for its published papers [...]
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-01-31
      DOI: 10.3390/jlpea8010004
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 5: The Advances, Challenges and Future Possibilities
           of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    • Authors: Amlan Ganguly, M. Ahmed, Rounak Singh Narde, Abhishek Vashist, Md Shamim, Naseef Mansoor, Tanmay Shinde, Suryanarayanan Subramaniam, Sagar Saxena, Jayanti Venkataraman, Mark Indovina
      First page: 5
      Abstract: With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-02-28
      DOI: 10.3390/jlpea8010005
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 6: Multiple Input Energy Harvesting Systems for
           Autonomous IoT End-Nodes

    • Authors: Johan Estrada-López, Amr Abuellil, Zizhen Zeng, Edgar Sánchez-Sinencio
      First page: 6
      Abstract: The Internet-of-Things (IoT) paradigm is under constant development and is being enabled by the latest research work from both industrial and academic communities. Among the many contributions in such diverse areas as sensor manufacturing, network protocols, and wireless communications, energy harvesting techniques stand out as a key enabling technology for the realization of batteryless IoT end-node systems. In this paper, we give an overview of the recent developments in circuit design for ultra-low power management units (PMUs), focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. The paper starts by discussing a general structure for IoT end-nodes and the main characteristics of PMUs for energy harvesting. Then, an overview is given of different published works for multisource power harvesting, observing their main advantages and disadvantages and comparing their performance. Finally, some open areas of research in multisource harvesting are observed and relevant conclusions are given.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-03-03
      DOI: 10.3390/jlpea8010006
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 7: An Efficient Connected Component Labeling
           Architecture for Embedded Systems

    • Authors: Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
      First page: 7
      Abstract: Connected component analysis is one of the most fundamental steps used in several image processing systems. This technique allows for distinguishing and detecting different objects in images by assigning a unique label to all pixels that refer to the same object. Most of the previous published algorithms have been designed for implementation by software. However, due to the large number of memory accesses and compare, lookup, and control operations when executed on a general-purpose processor, they do not satisfy the speed performance required by the next generation high performance computer vision systems. In this paper, we present the design of a new Connected Component Labeling hardware architecture suitable for high performance heterogeneous image processing of embedded designs. When implemented on a Zynq All Programmable-System on Chip (AP-SOC) 7045 chip, the proposed design allows a throughput rate higher of 220 Mpixels/s to be reached using less than 18,000 LUTs and 5000 FFs, dissipating about 620 μJ.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-03-06
      DOI: 10.3390/jlpea8010007
      Issue No: Vol. 8, No. 1 (2018)
  • JLPEA, Vol. 8, Pages 8: A Performance of the Soft-Charging Operation in
           Series of Step-Up Power Switched-Capacitor Converters

    • Authors: Ayoob Alateeq, Yasser Almalaq, Mohammad Matin
      First page: 8
      Abstract: Due to their high power density and appropriateness for small circuits integration, switched-capacitor (SC) converters have gotten more interests. Applying the soft-charging technique effectively eliminates the current transient that results in a higher power density and a higher fundamental efficiency. Achieving the complete soft-charging operation is impossible by using the conventional control diagram for any SC converter topology. In this paper, we proposed a split-phase control to achieve the complete soft-charging operation in a power switched-capacitor (PSC) converter. The proposed control diagram was designed for a 1-to-4 PSC converter (two-level of the PSC converter). The implemented split-phase diagram successfully controls eight switches to exhibit eight modes of operation. In addition to the current transient elimination, the complete soft-charging allows us to reduce capacitor sizes. However, reducing capacitor size negatively increases the output voltage ripple; hence, an output LC filter is needed. The complete soft-charging achievement accomplishes a 96% efficiency due to the lower output impedance and the dead time switching. LT-Spice software has been used to verify the proposed control and the results were compared with hard-charging and incomplete soft-charging operations.
      Citation: Journal of Low Power Electronics and Applications
      PubDate: 2018-03-12
      DOI: 10.3390/jlpea8010008
      Issue No: Vol. 8, No. 1 (2018)
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