Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Mohammad Motamedi;Felix Portillo;Mahya Saffarpour;Daniel Fong;Soheil Ghiasi;
Pages: 1 - 4 Abstract: Modern convolutional neural networks (CNNs) in computer vision are trained on a large number of images from numerous categories to form rich discriminative feature extractors. Inference using such models on resource-constrained Internet-of-Things (IoT) platforms poses a challenge and an opportunity. Having limited computation, storage, and energy budgets, most IoT platforms are not capable of hosting such compute intensive models. However, typical IoT applications demand detection of a relatively small number of categories, albeit the specific categories of interest may change at runtime as the context evolves dynamically. In this letter, we take advantage of the opportunity to address the challenge. Specifically, we develop a novel transformation to the architecture of a given CNN, so that the majority of the inference workload is allocated to class-specific disjoint branches, which can be dynamically executed or skipped, based on the context, to fulfill the application requirements. Experiments demonstrate that our approach preserves the classification accuracy for the classes of interest, while proportionally decreasing the model complexity and inference workload. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Stefano Cherubin;Daniele Cattaneo;Michele Chiari;Antonio Di Bello;Giovanni Agosta;
Pages: 5 - 8 Abstract: While many approximate computing methods are quite application-dependent, reducing the size of the data representation used in the computation has a more general applicability. We present a tuning assistant for floating to fixed point optimization (TAFFO), an LLVM-based framework designed to assist programmers in the precision tuning of software. We discuss the framework architecture and we provide guidelines to effectively tradeoff precision to improve the time-to-solution. We evaluate our framework on a well-known approximate computing benchmark suite, AxBench, achieving a speedup on 5 out of 6 benchmarks (up to 366%) with only a limited loss in precision ( PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Nick Iliev;Alberto Gianelli;Amit Ranjan Trivedi;
Pages: 9 - 12 Abstract: This letter discusses a novel low-power digital CMOS architecture for speaker identification (SI) by combining $k$ -means clustering with Gaussian mixture model (GMM) scoring. We show that $k$ -means clustering at the front-end reduces the dimensionality of speech features to minimize downstream processing without affecting SI accuracy. Implementation of cluster generator is discussed with novel distance computing and online centroid update datapaths to minimize overhead of the clustering layer (CL). The integrated design achieves $6times $ lower energy than the conventional for SI among ten speakers. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Wenjie Fu;Ming Ling;Wei Wang;Longxing Shi;
Pages: 13 - 16 Abstract: Multicore power, area, and timing (McPAT) is one of the popular system-level simulators that can evaluate power either in design space explorations (DSEs) or in run-time applications. However, when estimating the dynamic power of a processor, the inputs of McPAT are microarchitecture statistics captured from cycle-accurate simulations, which usually are unacceptably time-consuming. In this letter, we propose an accelerated McPAT power simulator (AMPS) without any cycle-accurate simulations. The statistics are analytically modeled using micro-architecture independent characteristics of the application (MICA) that extracted from the trace profiling. AMPS is verified under the SPEC2006 benchmark suite. The average error of power evaluation using AMPS is 4.96% relative to that based on the simulation statistics from gem5. Meanwhile, the evaluation time can be sped up by 9.76 times compared with the approach of accurate simulation inputs. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Davide Zoni;Luca Cremona;William Fornaciari;
Pages: 17 - 20 Abstract: Considering the energy-cap problem in battery-powered devices, dynamic voltage and frequency scaling, and power gating represent the de-facto state-of-the-art actuators. However, the limited margin available to reduce the operating voltage, the impossibility to massively integrate such actuators on-chip together with their actuation latency force a revision of such design methodologies. We present an all-digital architecture and a design methodology that can effectively manage the energy-cap problem for CPUs and accelerators. Two quality metrics are put forward to capture the performance loss and the energy budget violations. We employed a vector processor supporting four hardware threads as representative usecase. Results show an average performance loss and energy cap violations limited to 2.9% and 3.8%, respectively. Compared with solutions employing the dynamic frequency scaling actuator, our all-digital architecture improves the energy-cap violations by $3times $ while maintaining a similar performance loss. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Shasha Guo;Lei Wang;Baozi Chen;Qiang Dou;
Pages: 21 - 24 Abstract: Spiking neural networks (SNNs) have been shown to be accurate, fast, and efficient in classical machine vision tasks, such as object recognition or detection. It is typical to convert a pretrained deep neural network into an SNN since training SNN is not easy. The max-pooling (MP) function is widely adopted in most state-of-the-art deep neural networks. To maintain the accuracy of the SNN obtained through conversion, this function is an important element to be implemented. However, it is difficult due to the dynamic characteristics of spikes. As far as we know, existing solutions adopt additional technologies except the spiking neuron model to implement MP or approximate MP, which introduce overhead of memory storage and computation. In this letter, we propose a novel method that utilizes only the spiking neuron model to approximate MP. Our method does not incur any overhead. We validate our method with three datasets and six networks including three oxford visual geometry group-like networks. And the experimental results show that the performance (accuracy and convergence rate) of our method is as good as or even better than that of the existing method. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Jaeheon Kwak;Jinkyu Lee;
Pages: 25 - 28 Abstract: As different batteries exhibit their own advantages and disadvantages, a single-type battery system for a mobile embedded system (such as smartphones and tablet PC) cannot overcome the inherent limitations of its target battery. For example, although the lithium cobalt oxide (LCO) battery is the most popular battery for mobile embedded systems due to its high energy density, mobile embedded systems equipped with LCO batteries suffer from rapid capacity degradation. In this letter, we target heterogeneous batteries in a mobile embedded system and propose a method for minimizing the capacity degradation of the batteries. To this end, we first analyze factors that affect capacity degradation, and choose dominant factors that are controllable in a mobile embedded system. We then build a battery degradation model considering the factors, and finally develop a battery scheduling algorithm that minimizes capacity degradation using the degradation model. Our evaluation with real experiments and simulations demonstrates the effectiveness of the proposed algorithm in minimizing capacity degradation. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Authors:
Mohsen Ansari;Mostafa Pasandideh;Javad Saber-Latibari;Alireza Ejlali;
Pages: 29 - 32 Abstract: Due to the system-level power constraints, it is encountered that not all cores in a multicore chip can be simultaneously powered-on at the highest voltage/frequency levels. Also, in the future technology nodes, reliability issues due to the susceptibility of systems to transient faults should be considered in multicore platforms. Therefore, two major objectives in designing multicore embedded systems are low energy/power consumption and high reliability. This letter presents an energy management system that optimizes the energy consumption such that it satisfies reliability target and meets timing, thermal design power (TDP) and thermal safe power (TSP) constraints. Toward the TDP/TSP-constrained energy-reliability optimization, the proposed method schedules periodic real-time applications on different types of cores with voltage/frequency variations for heterogeneous multicore embedded systems. Experiments show that our proposed system provides up to 38.19% (in average by 29.66%) energy saving and up to 54.73% peak power reduction (in average by 24.55%) under different reliability targets and TDP/TSP constraints when compared to the state-of-the-art techniques. PubDate:
March 2020
Issue No:Vol. 12, No. 1 (2020)
Hybrid journal (It can contain Open Access articles)
