Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Abstract: These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Claudio Rubattu;Francesca Palumbo;Carlo Sau;Rubén Salvador;Jocelyn Sérot;Karol Desnos;Luigi Raffo;Maxime Pelcat;
Pages: 69 - 72 Abstract: Domain-specific acceleration is now a must for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow (DF) models of computation with coarse-grained reconfiguration (CGR) architectures can be particularly handful. In this letter we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on DF and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving design space exploration when compared with state-of-the-art high-level synthesis. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Hamed Zandevakili;Ali Mahani;
Pages: 73 - 76 Abstract: Fault tolerance is one of the main issues of electronic devices especially for controlling and monitoring of the operations in extreme environments. In this letter, a new memristor-based hybrid approach has been proposed, which combines attractive features of the both static and dynamic methods to introduce a new concurrent reconfigurable structure. The simulation results show that the proposed structure tolerates transient and permanent faults during the run-time with minimum delay, power consumption, and area overhead in comparison to the related works. The proposed work also reaches to minimum silicon protection factor with zero pause time during fault recovery phase. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Federico Reghenzani;Giuseppe Massari;William Fornaciari;
Pages: 77 - 80 Abstract: Measurement-based probabilistic timing analysis, a probabilistic real-time computing method, is based on the extreme value theory (EVT), a statistical theory applied to worst-case execution time (WCET) analysis on real-time embedded systems. The output of the EVT theory is a statistical distribution, in the form of generalized extreme value distribution or generalized Pareto distribution. Their cumulative distribution function can asymptotically assume one of the three possible forms: 1) light; 2) exponential; or 3) heavy tail. Recently, several works proposed to upper-bound the light-tail distributions with their exponential version. In this letter, we show that this assumption is valid only under certain conditions and that it is often misinterpreted. This leads to unsafe estimations of the WCET, which cannot be accepted in applications targeting safety critical embedded systems. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Yang Song;Bill Lin;
Pages: 81 - 84 Abstract: Mesh-based networks-on-chips (NoCs) are increasingly used for on-chip communications in embedded multicore processors. O1TURN is a well-known oblivious routing algorithm for mesh-based NoCs that has been shown to be worst-case throughput optimal for even network radices, but not for odd radices. More recently, another oblivious routing algorithm called U2TURN has been shown to be worst-case throughput optimal for both odd and even radices. This is accomplished by load-balancing among 2-turn paths in XYX or YXY routing, including nonminimal paths. Besides being worst-case throughput optimal, U2TURN achieves higher throughput than O1TURN under adversarial traffic. However, for random traffic, where the traffic is inherently load-balanced, O1TURN achieves lower network latency since it only considers minimal paths. In this letter, we propose a hybrid oblivious routing algorithm called uniform-minimal-first (UMF) routing. UMF works by exploiting any inherent load-balancing characteristics of the traffic pattern to reduce packet latency, but it retains the throughput optimality of U2TURN for both odd and even radices, and it achieves the performance of U2TURN under adversarial traffic. UMF is very inexpensive to implement as it just requires incrementing two small counters, but only for the head flit when a node injects a new packet (not for any pass-through traffic). These simple updates can be performed one cycle ahead of packet injection to avoid slowing down any router pipeline stage. Despite its simplicity, UMF outperforms U2TURN by 23.7% under random traffic and O1TURN by 12.6% under adversarial traffic. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Aditya Pradeep;Vishal Mohanty;Adarsh Muthuveeru Subramaniam;Chester Rebeiro;
Pages: 85 - 88 Abstract: Composite fields are used for implementing the advanced encryption standard (AES) SBox when compact and side-channel resistant constructions are required. The prior art has investigated efficient implementations of such SBoxes for application specific integrated circuit (ASIC) platforms. On field programmable gate arrays (FPGAs); however, due to the considerably different structure compared with ASICs, these implementations perform poorly. In this letter, we revisit composite field AES SBox implementations for FPGAs. We show how design choices and optimizations can be made to better suit the granular look-up tables that are present in modern FPGAs. We investigate 2880 SBox constructions and show that about half of them are better than the state-of-the-art composite field implementation. Our best SBox implementation is 18% smaller compared with the state-of-the-art implementation on an FPGA. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Hassan Mahmood;Zahid Ullah;Omer Mujahid;Inayat Ullah;Abdul Hafeez;
Pages: 89 - 92 Abstract: This letter proposes a novel approach to design a ternary content-addressable memory (TCAM) on a field-programmable gate array (FPGA). The proposed architecture uses slice registers (SRs) for storage instead of lookup tables and static random-access memory, and a control signal in place of a memory element to accommodate a don’t care state. The proposed architecture is implemented on Xilinx Virtex-6 FPGA. Compared with the latest prior work, the proposed TCAM reduces the number of SRs by 50.04% while not compromising on throughput. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Gereon Führ;Seyit Halil Hamurcu;Diego Pala;Thomas Grass;Rainer Leupers;Gerd Ascheid;Juan Fernando Eusse;
Pages: 93 - 96 Abstract: Field-programmable gate arrays (FPGAs) are known to increase performance and energy efficiency of parallel applications. Integrated on multiprocessor systems-on-chip, they can be used as accelerators in addition to the multicore processor. However, state-of-the-art high-level synthesis tools require an intensive manual effort to make effective use of all available FPGA resources. This letter proposes an automatic hardware/software partitioning software tool which optimizes for different design goals, such as performance and power. A given source code is analyzed and all necessary decisions and annotations are performed without the need for designer interaction. Further, abstract but accurate power models for FPGA and processor enable power or energy driven optimization. The tool flow is tested against representative benchmarks on the Xilinx Zynq UltraScale+. On average, an energy reduction of 71 % is possible compared to a nonpartitioned, sequential execution. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Authors:
Jing Yan;Xuyang Tian;Xiaoyuan Luo;Xinping Guan;
Pages: 97 - 100 Abstract: Most applications of underwater acoustic sensor networks (UASNs) rely on reliable location information. In this letter, we present an embedded communication system for underwater asynchronous localization. An asynchronous localization protocol is developed and encoded for the actual implementation on an embedded communication system. Particularly, the embedded communication system is composed of four transducers, one control center and four acoustic modems. In order to reduce the effect of multipath interference, the direct-sequence spread-spectrum (DSSS) technology is applied to the design of modem. Meanwhile, the iterative least squares method is implemented to estimate the position. Finally, experimental results are given to verify the effectiveness of the proposed system. It is demonstrated that the influences of asynchronous clock can be well eliminated. PubDate:
Sept. 2019
Issue No:Vol. 11, No. 3 (2019)
Hybrid journal (It can contain Open Access articles)
