Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Shanshan Wang;Chenglong Xiao;Wanjun Liu;
Pages: 1 - 4 Abstract: Automatic generation of custom instructions is the key to the extensible processors. The generation of custom instructions includes two crucial steps: 1) custom instruction enumeration and 2) custom instruction selection. This letter focuses on the custom instruction enumeration step. Enumerating all custom instruction candidates satisfying architectural constraints from an application graph is a computationally difficult problem. Considering the high complexity of the custom instruction enumeration, we propose a simple but efficient parallel search method based on multidepth graph partitioning for enumerating custom instructions. Experimental results show that the proposed method can give near-linear speedup and outperforms the latest parallel methods. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Sidharta Andalam;Daniel Jun Xian Ng;Arvind Easwaran;Karthikeyan Thangamariappan;
Pages: 5 - 8 Abstract: As the industrial cyber-infrastructure become increasingly important to realize the objectives of Industry 4.0, the consequence of disruption due to internal or external faults become increasingly severe. Thus there is a need for a resilient infrastructure. In this letter, we propose a contract-based methodology where components across layers of the cyber-infrastructure are associated with contracts and a light-weight resilience manager. This allows the system to detect faults (contract violation monitored using observers) and react (change contracts dynamically) effectively. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Mohammad Motamedi;Daniel Fong;Soheil Ghiasi;
Pages: 9 - 12 Abstract: Convolutional neural networks (CNNs) exhibit remarkable performance in various machine learning tasks. As sensor-equipped Internet of Things devices permeate into every aspect of modern life, the ability to execute CNN inference, a computationally intensive application, on resource constrained devices has become increasingly important. In this context, we present Cappuccino, a framework for synthesis of efficient inference software targeting mobile system-on-chips (SoCs). We propose techniques for efficient parallelization of CNN inference targeting mobile SoCs, and explore the underlying tradeoffs. Experiments with different CNNs on three mobile devices demonstrate the effectiveness of our approach. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Niels Reijers;Joshua Ellul;Chi-Sheng Shih;
Pages: 13 - 16 Abstract: A large number of virtual machines (VMs) have been developed for sensor nodes. Many are based on Java, although implementations based on Python and.Net also exist. Some aspects of the java virtual machine, such as the simple yet sufficiently expressive instruction set, work well on a sensor node. However, Java was developed for more powerful devices, which results in certain functionality not being ideal for resource constrained devices. While writing VM implementations and programmes to run on sensor node devices over the past decade, we encountered a number of situations where this mismatch between standard languages and the specifics of sensor node programming limited the practical use of current VMs. In this letter, we describe what we consider to be the most pressing issues and discuss how these may be resolved in future VMs. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Sedigheh Asyaban;Mehdi Kargahi;
Pages: 17 - 20 Abstract: This letter considers dual-criticality systems having periodic tasks with offsets scheduled by a given fixed-priority scheduler. We are interested to formally derive some feasibility interval for such systems. We prove that such an interval exists and that it is bounded by the size of four hyperperiods plus the largest task offset. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Yuteng Zhou;Yecheng Lyu;Xinming Huang;
Pages: 21 - 24 Abstract: As a fundamental feature of intelligent vehicles, vision-based road detection must be executed on a real-time embedded platform with high accuracy. Road detection is often applied in conjunction with lane detection to determine the drivable regions. Although some existing research based on large deep learning models achieved high accuracy using the road detection dataset, they often did not consider the low power requirement of a typical embedded system. In this letter, an ultralow-power hardware accelerator for road detection is proposed. By adopting a top-down convolutional neural network (CNN) structure, a small CNN, namely RoadNet, is trained that can achieve near state-of-the-art detection accuracy. Furthermore, each CNN layer is trimmed to be computationally identical and every processing element in the architecture is fully utilized. When implemented using 32-nm process technology, the proposed hardware accelerator requires the chip area of 0.45 mm2 and the power consumption of only 80 mW, which results in an equivalent power efficiency of about 300 GOP/s/W. The RoadNet chip is capable of processing 241 frames/s at 1080P image resolution. It stands out as an ultralow-power hardware accelerator in an embedded system for road detection. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Emanuele Lattanzi;Valerio Freschi;
Pages: 25 - 28 Abstract: Energy harvesting is increasingly considered a key technology for the design of autonomous embedded systems. However, the design, deployment, and validation of systems exploiting the energy scavenged from the environment to sustain their operativeness poses considerable research challenges, especially in a networked context. Emulation is regarded as an achievable option to allow reproducible and accurate experimental conditions. However, when the emulation is carried out by means of an embedded low-power device, the tradeoff between accuracy and tight time requirements has to be carefully taken into account in order to avoid performance degradation. We introduce a novel approach that aims at improving the reactiveness of a hardware–software embedded emulator thanks to the introduction of a hardware compensation circuit. The proposed system allows an efficient run-time correction of the emulated voltage to be supplied to the load, thus improving the response time of the emulator with respect to the software-based compensation. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Authors:
Kalyan Baital;Amlan Chakrabarti;
Pages: 29 - 32 Abstract: The shift from homogeneous multicore to heterogeneous multicore introduces challenges in scheduling the tasks to the appropriate cores maintaining the time deadline. This letter studies the existing scheduling schemes in a heterogeneous multicore system and finds an approach to enhance the homogeneous system model to heterogeneous scheduling architecture. The proposed model increases the overall system utilization by accommodating almost all the tasks (low power task and high power task) into appropriate cores (big high power and small low power). It further enhances the system performance by allocating rejected jobs from small cores into the big cores through a dispatcher. PubDate:
March 2019
Issue No:Vol. 11, No. 1 (2019)
Hybrid journal (It can contain Open Access articles)
