Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Biswadip Maity;Majid Shoushtari;Amir M. Rahmani;Nikil Dutt;
Pages: 33 - 36 Abstract: Memory approximation enables trading off quality/accuracy for performance or energy gains. Traditionally, application programmers are burdened with the difficult task of setting memory approximation knobs to achieve the desired quality of service (QoS). Our self-adaptive approach for memory approximation eases the programmer's burden: simply specify the desired quality as a goal, with the system deploying a formal control-theoretic approach to tune the memory approximation knobs and deliver a guaranteed QoS. We model quality configuration tracking as a formal quality control problem, and outline a system identification technique that captures memory approximation effects with variations in application input and system architecture. Preliminary results show that we can alleviate the programmer's burden of manual knob tuning for on-chip memory approximation. When compared with a manual calibration scheme we achieve 3× improvement in average settling time and up to 5× improvement in best case settling time. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Kazuo Sakiyama;Tatsuya Fujii;Kohei Matsuda;Noriyuki Miura;
Pages: 37 - 40 Abstract: Fault-injection attacks against cryptographic devices have been studied in great detail. As a countermeasure to such attacks, the flush code eraser (FCE) has been proposed. The FCE realizes a new attack reaction in which sensitive data in a cryptographic device are quickly invalidated by redistributing the electrons in the circuits. In this letter, we discuss the abilities of the FCE by evaluating the data invalidation period with experiments using a test chip. As a result, the invalidation period is estimated to be approximately 80 ps, which enhances the security of the cryptographic device and also prevents the possibility of the future attacks. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Andrew J. Sonta;Rishee K. Jain;
Pages: 41 - 44 Abstract: Understanding the underlying structure of building occupant dynamics is crucial to improving the effectiveness and energy efficiency of commercial buildings, as occupants fundamentally drive building design and operation. In current practice, we largely account for occupant behavior in the design and management of buildings through rudimentary schedules of presence or absence. However, the increasing availability of embedded sensors-such as plug load sensors-offers an opportunity not only to monitor occupants' activity patterns but also to use these patterns to gain insight into the network structure of occupants. In this letter, we present a statistical methodology for inferring this network, which comprises social, spatial, and organizational ties among occupants. We apply our method to a 7-person office environment in Northern California, and we compare the inferred networks to ground truth social, spatial, and organizational networks obtained through validated survey questions. We demonstrate that this approach offers insights into the complex nature of occupant dynamics, which can ultimately serve as inputs into building design strategies that minimize energy consumption and improve occupant well-being. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Kaoru Saso;Yuko Hara-Azumi;
Pages: 45 - 49 Abstract: As interest in architectural designs for “Internet of Things (IoT) edge computing” is growing, conflicting requirements between energy-efficiency and design-productivity are becoming remarkably crucial. Owing to the increasing diversity of IoT applications, the domain-oriented designs of processors should be reassessed. By focusing on one application domain that is control-intensive and mainly operates “light” computations, we examine issues of current processor designs, present simple and energy-efficient processors, and justify the design strategies that we employed. Our evaluation shows the effectiveness of our processors, in terms of circuit area and energy-efficiency, over ARM Cortex-M0, and reveals important findings in architectural designs for severely constrained IoT edge computing. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Yongsoo Joo;Dongjoo Seo;Dongyun Shin;Sung-Soo Lim;
Pages: 50 - 53 Abstract: As the size of mobile applications grows rapidly, the importance of application loading performance is increasingly emphasized in mobile devices. However, current operating systems rely on demand paging to load the working set of applications into memory, which typically generates small size input/outputs (I/Os) that are not handled well by mobile flash storage devices. We propose an aggressive merging scheme, which consists of an explicit application loading method and a series of optimization techniques: I/O reordering, I/O merging, and I/O padding. The key idea behind our scheme is to enlarge I/O size for application loading to increase the effective storage throughput. Experiments show that our scheme effectively increases the average I/O size by $5.6times $ , leading to 30% reduction of working set loading time. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Milad Afzalan;Farrokh Jazizadeh;
Pages: 54 - 57 Abstract: Power utilities leverage demand response (DR) events to effectively reduce the peak load at critical times with excessive power demand. DR programs are generally categorized as manual or automated from the automation perspective. The opportunities for automated DR in the residential sector have emerged with the integration of smart and connected loads. For example, smart appliances with deferrable loads can be scheduled to shift their load without consumers’ direct involvement, given that many consumers might not engage sufficiently to participate in the manual DR. However, it has been shown that unjustified load shifting from many consumers in peak times could result in high off-peak demand. Therefore, it is essential for utilities to identify and target consumers for participation according to efficacy criteria. To address this issue, in this letter, we propose a data-driven method for the selection of consumers according to their potential for demand reduction in a DR program. The proposed method characterizes the frequency, consistency, and the peak time usage of deferrable loads across several subsequent days. By measuring the impact on peak-load shaving, we evaluated our approach on a subset of electricity dataset from the Pecan Street Dataport. The findings demonstrate the efficacy of the proposed method in selecting consumers with deferrable loads based on their potential for demand reduction in the future events. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Abhishek N. Tripathi;Arvind Rajawat;
Pages: 58 - 61 Abstract: The demand of early estimation of the power of semiconductor devices has risen due to technology scaling, growing complexity, and faster time to market. In this letter, we present the early power estimation model for field programmable gate array-based designs. We perform the profiling at C-level using low-level virtual machine intermediate representation and then training of the neural network from the profiling information to create the estimation model. The model accuracy is validated from the CHStone, MachSuite, and Rosetta-master benchmark applications. An insignificant relative error of 0.21% to 5.12% is observed for the analyzed benchmark designs with the exceptional increase in estimation speed by 87 times of magnitude as compared to the Xilinx Vivado Design Suite. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Paolo Meloni;Daniela Loi;Gianfranco Deriu;Marco Carreras;Francesco Conti;Alessandro Capotondi;Davide Rossi;
Pages: 62 - 65 Abstract: The NEURAghe architecture has proved to be a powerful accelerator for deep convolutional neural networks running on heterogeneous architectures based on Xilinx Zynq-7000 all programmable system-on-chips. NEURAghe exploits the processing system and the programmable logic available in these devices to improve performance through parallelism, and to widen the scope of use-cases that can be supported. In this letter, we extend the NEURAghe template-based architecture to guarantee design-time scalability to multiprocessor SoCs with vastly different cost, size, and power envelope, such as Xilinx's Z-7007s, Z-7020, and Z-7045. The proposed architecture achieves state-of-the-art performance and cost effectiveness in all the analyzed configurations, reaching up to 335 GOps/s on the Z-7045. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Authors:
Rafael Stahl;Daniel Mueller-Gritschneder;Ulf Schlichtmann;
Pages: 66 - 69 Abstract: The Internet of Things (IoT) connects many tiny low-cost devices, so-called IoT nodes. Designers need to implement smart functionality with highly limited resources in terms of design effort, available on-chip memory, and computation power. This letter proposes a new method to reduce memory size, performance, and development effort for the device drivers. The driver behavior is developed with a new $C$ -like domain-specific language. Through register layout optimization targeting to combine accesses it achieves to reduce run time by 52% and code size by 22% for two RISC-V PULPino device drivers. PubDate:
June 2020
Issue No:Vol. 12, No. 2 (2020)
Hybrid journal (It can contain Open Access articles)
