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  Subjects -> ELECTRONICS (Total: 179 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Biosensors and Bioelectronics     Open Access   (Followers: 7)
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 5)
Advances in Electronics     Open Access   (Followers: 78)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Microelectronic Engineering     Open Access   (Followers: 13)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 313)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 266)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 105)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 92)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 189)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 66)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 19)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 71)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 24)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 5)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 12)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nano Devices, Sensors and Systems     Open Access   (Followers: 12)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 24)
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access  
Journal of Field Robotics     Hybrid Journal   (Followers: 2)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 167)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 28)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 18)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 53)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
Solid-State Electronics
Journal Prestige (SJR): 0.492
Citation Impact (citeScore): 2
Number of Followers: 9  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0038-1101
Published by Elsevier Homepage  [3158 journals]
  • TCAD Models of the Ballistic Mobility in the Source-to-Drain Tunneling
           Regime
    • Abstract: Publication date: Available online 6 April 2019Source: Solid-State ElectronicsAuthor(s): A. Schenk, P. Aguirre TCAD models of the ballistic mobility are developed where the mean ballistic velocity is not a fitting parameter, but a function of either the quasi-Fermi potential or the density. In the first case, a local version can be derived which is more robust when used together with a model for source-to-drain tunneling. The second form conserves the thermionic ballistic current and better matches the on-currents of short-channel FETs obtained from a quantum-transport solver, in particular at low source-drain bias. It requires the iterative extraction of the top-of-the-barrier density. This is the only non-local remnant of the hydrodynamic term in the balance equation for the mean velocity which is discarded in all commercial 2D/3D device simulators. The ballistic mobility, used with the Matthiessen rule, substitutes for this term and prevents that the drift-diffusion current diverges in the limit of zero gate length. The numerical integration of the models with the TCAD simulator S-Device is set out, and simulated transfer characteristics of In0.53Ga0.47As double-gate ultra-thin-body FETs with gate lengths ranging from 7 nm to 40 nm are compared with the corresponding quantum-transport results. It is shown that under conditions of dominant source-to-drain tunneling, the concepts of local quasi-Fermi potential and mean ballistic velocity break down. Suggestions for non-local modifications of both the mobility and tunneling models are given that would allow to use the same setup for all gate voltages from deep sub-threshold to deep inversion.
       
  • Compact modeling of the subthreshold characteristics of junctionless
           double-gate FETs including the source/drain extension regions
    • Abstract: Publication date: Available online 27 March 2019Source: Solid-State ElectronicsAuthor(s): Min Soo Bae, Ilgu Yun With the gate length shrinking to a few tens of nanometers, junctionless double-gate field-effect transistors (JL DG FETs) have become widely studied. In the subthreshold region, the electrical characteristics of JL DG FETs are sensitive to device parameters such as channel length, channel thickness, oxide thickness, doping concentration, and whether there are source/drain (S/D) extension regions or not. Therefore, it is essential for device engineers to develop compact models to run circuit simulations. In this paper, a compact JL DG FET model including S/D extension regions in the subthreshold region is proposed. Based on the superposition of the 1D Poisson equation and the 2D Laplace equation, the potential model is developed with and without S/D extension regions. Moreover, the subthreshold current, subthreshold slope, threshold voltage, and the drain induced barrier lowering are extracted without numerical iteration. The modeling results were verified with an ATLAS TCAD simulator and compared with a conventional undoped DG FET. We showed that the JL DG FET using the proposed compact model has better short-channel characteristics than the undoped DG FET with S/D extension regions, and we recommend that the doping concentration in the JL DG FET should be lighter for better subthreshold characteristics.
       
  • 2D and 3D TCAD Simulation of III-V Channel FETs at the End of Scaling
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): P. Aguirre, M. Rau, A. Schenk Quantum drift diffusion corrections, models for the one- and two-dimensional density of states, a non-local model for source-to-drain tunneling, and a simple ballistic mobility model are jointly used to simulate IDVGS-characteristics of scaled III-V-channel nFETs. The sub-threshold swing of double-gate ultra-thin-body and gate-all-around nanowire geometries are extracted for different gate lengths, and the semi-classical results are compared with those from the quantum transport simulator QTx. The low-dimensional density of states in combination with the ballistic mobility yields an overall good agreement with the QTx transfer curves after the onset of inversion and decreases ION by two orders of magnitude in comparison to the simulation with a large diffusive mobility. It is shown that source-to-drain tunneling sets a limit to scaling at a gate length of about 10 nm due to the degradation of the sub-threshold swing. Simulating this effect with a low-dimensional density of states reveals inconsistencies. They are attributed to the tunneling model, which had been derived for a three-dimensional electron gas.
       
  • Investigation of Thin Gate-Stack Z2-FET Devices as
           Capacitor-less Memory Cells
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): S. Navarro, C. Marquez, K.H. Lee, C. Navarro, M. Parihar, H. Park, P. Galy, M. Bawedin, Y.T. Kim, S. Cristoloveanu, F. Gamiz Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FDSOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z2-FET cells are observed.
       
  • Impact of contact and channel resistance on the frequency-dependent
           capacitance and conductance of pseudo-MOSFET
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): S. Sato, G. Ghibaudo, L. Benea, I. Ionica, Y. Omura, S. Cristoloveanu This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified.
       
  • Characterization of the Interface-Driven 1st Reset Operation in HfO2-based
           1T1R RRAM Devices
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): Eduardo Pérez, Mamathamba Kalishettyhalli Mahadevaiah, Cristian Zambelli, Piero Olivo, Christian Wenger In this work, the increase on the filament conductivity during the 1st Reset operation, by using the incremental step pulse with verify algorithm, is investigated in HfO2-based 1T1R RRAM devices. A new approach is proposed in order to explain the increase of conductivity by highlighting the crucial roles played by both metal-oxide interfaces. The top metal-oxide interface (HfO2-x/TixOy) plays a role in the forming operation by creating a strong gradient of oxygen vacancies in the hafnium oxide layer. The bottom metal-oxide interface (TixOyNz/HfO2-x) also creates oxygen vacancies, which strengthen the conductive filament tip near to this interface at the beginning of the 1st Reset, leading to the reported conductivity increase. After the 1st Reset operation the conductive filament stabilizes at the bottom interface suppressing this behavior in the subsequent reset operations. By modifying the programming parameters and the temperature, it was confirmed a constant current increase of about 9 μA during the 1st Reset regardless the operation conditions imposed.
       
  • Analog neuromorphic computing using programmable resistor arrays
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): Paul M. Solomon Digital logic technology has been extraordinarily successful and has been fueled by incredible gains in integration density and performance achieved over the years following Moore’s law. This has led to societal changes where more and more everyday functions are aided by smart devices following the path to artificial intelligence. However, in the field of deep machine learning, even this technology falls short, partly because device scaling gains are no longer easy to come by, but also due to intractable energy costs of computation. Deep learning, using labeled data, can be mapped onto artificial neural networks, arrays where the inputs and outputs are connected by programmable weights, and which can perform pattern recognition functions. The learning process consists of finding the optimum weights however this learning process is very slow for large problems. Exploiting the fact that weights do not need to be determined with high precision, as long as they can be updated precisely, the device community has recognized that analog computation approaches, using physical arrays of memristor (programmable resistor) type devices could offer significant speedup and power advantages compared to pure digital, or pure software approaches. On the other hand, the history of analog computation is not reassuring since the rule has been that more capable digital devices invariably supplant analog function. In this paper I will discuss the opportunities and limitations of using analog techniques to accelerate the learning process in resistive neural networks.
       
  • An Algorithm to Design Floating Field Rings in SiC and Si Power Diodes and
           MOSFETs
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): M.G. Jaikumar, K Akshay, Shreepad Karmalkar Prior work on Silicon Carbide (SiC) power devices has been silent on the exact procedure to be employed for designing the Floating Field Rings (FFRs) meant for raising avalanche breakdown voltage of these devices. On the other hand, prior procedures for designing FFRs in Si devices do not work for kV range breakdown associated with SiC devices, and employ 10’s of μm long rings. We propose a systematic procedure for deriving the number and spacing of the FFRs of any ring length required for achieving an arbitrary breakdown voltage. The procedure can be adapted to implement any one of the ring spacing strategies, namely - constant, decreasing or increasing as one moves outward from the main junction. The procedure is demonstrated for the linearly increasing ring spacing case using TCAD simulations, considering 1.7−5.5 kV 4H-Silicon Carbide devices and a 700 V Si device reported in literature. The FFR structures resulting from our procedure are found to have a total length which is 24.5-75 % of that published in literature, and breakdown voltage which is more than 92% of the plane parallel value.
       
  • Lumped-Parameter Equivalent Circuit Modeling of Solar Cells with S-Shaped
           I-V Characteristics
    • Abstract: Publication date: Available online 25 March 2019Source: Solid-State ElectronicsAuthor(s): Fei Yu, Gongyi Huang, Wei Lin, Chuanzhong Xu, Wanling Deng, Xiaoyu Ma, Junkai Huang In this paper, we propose a method to analytically solve some types of DC lumped-parameter equivalent circuit models for solar cells with S-shaped I-V characteristics measured under illumination. Based on the models proposed previously by other authors, we present the set of equations describing solar cell’s terminal current and voltage, derive the analytical solutions of I-V characteristics, and give discussions about the effects from the model parameters on solar cells’ I-V characteristics. The comparisons between the proposed solutions and the least square method results illustrate that the solution calculation scheme is not only both accurate and efficient, but also valid in the whole operation regime of solar cells especially for the S-shaped kink in the first quadrant. Finally, the solutions are validated by the reconstructed experimental data to demonstrate that they can be adopted in the practical applications of solar cells. As a result, the feature of the proposed solutions can decrease computation complexity, ease the extraction process of the solar cells’ model fitting parameters, and increase simulation accuracy.
       
  • Effects of Mole Fraction Variations and Scaling on Total Variability in
           InGaAs MOSFETs
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Nicolò Zagni, Francesco Maria Puglisi, Paolo Pavan, Giovanni Verzellesi Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate- Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, VT,lin, VT,sat, on-current, ION, leakage current, IOFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced VT variability, it increases the total VT,lin variability as well as that for ION and IOFF.
       
  • Improved performance of fully-recessed normally-off LPCVD SiN/GaN MISFET
           using N2O plasma pretreatment
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Mengjun Li, Jinyan Wang, Hongyue Wang, Qirui Cao, Jingqian Liu, Chengyu Huang An effective and simple approach for gate-recessed normally-off GaN-based MISFETs is proposed to suppress the high temperature induced degradation during low pressure chemical vapour deposition (LPCVD) in gate-recessed normally off GaN-based MISFET. After a N2O plasma treatment on GaN channel prior to LPCVD SiN, the LPCVD SiN/GaN MISFET exhibits a maximum drain current of 607mA/mm, 3 times higher than that without N2O plasma pretreatment, a threshold voltage of +1.2V at ID=0.1mA/mm, off-state hard-breakdown voltage of 1348V with LGD=20μm, and gate leakage current below 15nA/mm in the whole gate swing to +20V. The interface states characterization in MISFETs show that about 3 times lower interface trap density was achieved in MISFET with N2O plasma pretreatment compared to that in SiNx/GaN transistor without such surface treatment.
       
  • Effect of Degree of Strain Relaxation on Polarization Charges of
           GaN/InGaN/GaN Hexagonal and Triangular Nanowire Solar Cells
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): S.R. Routray, T.R. Lenka The innovative contribution of this paper is to derive polarization charges in hexagonal and triangular GaN/InGaN/GaN core/shell/shell nanowire solar cells considering effect of degree of strain relaxation (R) and appropriate stiffness coefficients. The crystal orientation angle, φ and non-linear effect of spontaneous polarization are tailored with strain calculations for a better precision of polarization charges in nanowire type devices. The article also formulated the effect of polarization charges while InGaN layers are grown above or below GaN layer in both types of nanowires depending on the lattice expansion or compression. The model accounts an innovative concept of polarization charges distribution with respect to growth of crystal orientation and strain relaxation. It is observed that nanowire solar cell with triangular geometry could be good enough for efficient generation of power as compared to hexagonal nanowire solar cell. This concept of one triangular nanowire solar cell exhibits an efficiency of 3.18% with 90.34% fill factor under 1 Sun AM1.5 illumination with 20% ‘In’ composition.
       
  • The 25th Korean Conference on Semiconductors
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Jung-Hee Lee, Tae Joo Park, Kyung Rok Kim, Yongwoo Kwon
       
  • Near-field scanning microwave microscope platform based on a coaxial
           cavity resonator for the characterization of semiconductor structures
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Bendehiba Abadlia Bagdad, Carmen Lozano, Francisco Gamiz A Near-Field Scanning Microwave Microscope (NSMM) for the characterization of semiconductor structures has been designed, simulated and fabricated. The present NSMM system is based on a home-made coaxial-cavity resonator which is fed by a Keysight N5242A PNA-X Network Analyzer. The inner conductor of the coaxial resonator is connected to a sharpened tungsten tip, which was fabricated by an electrochemical process. The reflection and transmission coefficients S11, S21, the resonance frequency fr and the quality factor Q of the resonant cavity are measured as the semiconductor structure is scanned by the sharpened probe tip while the sample-tip distance is kept constant in the near-field region. The interaction between the probe tip and the sample under test provides variations of these parameters which are related to the topographical and dielectric properties of a very small region of the material under the probe tip. Thus, a 2D image of the evolution of the S11, S21, fr and Q parameters on the surface of the device under test is obtained. This image can be related to space changes in the topography, dielectric properties and composition of the semiconductor structure.
       
  • Feasibility of plasmonic circuits for on-chip interconnects
    • Abstract: Publication date: Available online 22 March 2019Source: Solid-State ElectronicsAuthor(s): M. Fukuda, Y. Tonooka, T. Inoue, M. Ota Feasibility of fabricating plasmonic circuits by complementary metal-oxide-semiconductor (CMOS) compatible processes is presented, and the circuit performances are numerically and experimentally discussed from the viewpoint of operating speed and energy loss. The transmission speed of plasmonic signals, which is governed by the dispersion of circuits, is calculated to be about two orders of magnitude higher than that of electric signals. The energy loss per single transmitted-bit is estimated using shot-noise limits, and it is clarified that plasmonic signals are superior to electric ones if the transmitted distance is set to an area within a few hundred micrometers. Based on these results and the experimental results of each plasmonic components, the feasibility of plasmonic circuits are demonstrated. In addition, the feasibility of the functional expansion of plasmonic circuits, such as wavelength-division-multiplexing networks, is discussed using experimental values of plasmonic components fabricated by CMOS-compatible processes. These plasmonic circuits and networks can be merged into silicon integrated circuits on a silicon substrate using CMOS compatible processes.
       
  • A new method for characterization of gate overlap capacitances and
           effective channel size in MOSFETs
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Daniel Tomaszewski, Grzegorz Głuszko, Krzysztof Kucharski, Jolanta Malesińska Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices.
       
  • This special issue is devoted to selected papers presented at the
           EuroSOI-ULIS2018 international conference, held in Granada, Spain on 19-21
           March 2018
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Francisco Gamiz, Luca Donetti, Carlos Sampedro
       
  • 28 nm FDSOI Analog and RF Figures of Merit at N2 Cryogenic
           Temperatures
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): B. Kazemi Esfeh, N. Planes, M. Haond, J.-P. Raskin, D. Flandre, V. Kilchytska This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).
       
  • GDNMOS and GDBIMOS devices for high voltage ESD protection in thin film
           advanced FD-SOI technology
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Louise De Conti, Thomas Bedecarrats, Sorin Cristoloveanu, Maud Vinet, Philippe Galy GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28nm node ultra-thin film UTBB FD-SOI high-k metal gate CMOS technology. The anode current and voltage were measured and simulated for a high number of variants with different connectivity conditions on the terminals. The devices are reconfigurable and promising for high voltage ESD protection applications.
       
  • Comparison of Memory Effect with Voltage or Current Charging Pulse Bias in
           MIS Structures Based on Codoped Si-NCs Embedded in SiO2 or HfOx
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Andrzej Mazurak, Robert Mroczyński Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Comparison between results for HfOx and SiO2 gate dielectric layers is shown and discussed. Presented findings are promising for possible applications of Si-NCs in memory structures.
       
  • Characterization and Modeling of 28-nm FDSOI CMOS Technology down to
           Cryogenic Temperatures
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Arnout Beckers, Farzan Jazaeri, Heorhii Bohuslavskyi, Louis Hutin, Silvano De Franceschi, Christian Enz This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.
       
  • TFET Inverter Static and Transient Performances in Presence of Traps and
           Localized Strain
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): E. Gnani, M. Visciarelli, A. Gnudi, S. Reggiani, G. Baccarani This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different IOFF values, namely 100,nA/μm and 10,pA/μm to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for IOFF=10,pA/μm.
       
  • A thorough study of Si nanowire FETs with 3D Multi-Subband Ensemble Monte
           Carlo simulations
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): L. Donetti, C. Sampedro, F.G. Ruiz, A. Godoy, F. Gamiz We thoroughly compare the DC electrical behavior of n-MOS transistors based on Si nanowires with 〈100〉 and 〈110〉 channel orientations by means of Multi-Subband Ensemble Monte Carlo simulations. We find that the drain current depends on the nanowire diameter and it is slightly, but consistently, larger for 〈100〉 than for 〈110〉 nanowires. The observed differences in mobility, velocity and spatial charge distribution are interpreted in terms of the effective masses and populations of the different Si conduction band valleys, whose six-fold degeneracy is lifted by quantum confinement in narrow nanowires. Finally, we study the scaling behavior for channel lengths down to 8nm, concluding that the differences observed between orientations are minimal.
       
  • Impact of threshold voltage extraction methods on semiconductor device
           variability
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): G. Espiñeira, D. Nagy, A. García-Loureiro, N. Seoane, G. Indalecio This paper presents a study of the impact that several widely used threshold voltage (VT) extraction methods have on semiconductor device variability studies. The second derivative (SD), linear extrapolation (LE) and third derivative (TD) extraction techniques have been compared to the standard method used in variability, the constant current criteria (CC). To estimate the influence of these methods on the results, an ensemble of 10.7 nm gate length Si FinFETs affected by RD variability have been simulated. We have shown that variability estimators like the σVT,〈VT〉 and the VT shift, are heavily affected by the selected extraction methodology, with up to 30% differences in the standard deviation. We have demonstrated that being aware of which VT extraction technique has been used in a variability analysis is crucial to properly interpret the results as they may be heavily method-dependent.
       
  • Analytical Modeling of Capacitances in Tunnel–FETs Including the Effect
           of Schottky Barrier Contacts
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Atieh Farokhnejad, Mike Schwarz, Fabian Horst, Benjamín Iñíguez, François Lime, Alexander Kloes In this paper, a charge–based analytical model for intrinsic capacitances in tunnel field–effect transistors (TFETs) is presented. The model is derived for a Si Double–Gate (DG) n–TFET whose flexibility is applicable to single–gate or p–type TFETs as well. The model is verified comparing with the TCAD simulations as well as measurements data.Considering the capacitances of fabricated Si planar p–TFETs on Ultrathin Body, some deviations between TCAD simulations, compact model and measurements are observed. Here the effect of Schottky barriers at NiSi2 contacts are analyzed and a theory for the reason associated deviations and the unexpected behavior of intrinsic capacitances is evolved. Furthermore, a technique to include this effect in the aforementioned model is also presented.
       
  • Electrostatic Coupling and Identification of Single-Defects in GaN/AlGaN
           Fin-MIS-HEMTs
    • Abstract: Publication date: Available online 20 March 2019Source: Solid-State ElectronicsAuthor(s): A. Grill, B. Stampfer, Ki-Sik Im, J.-H. Lee, C. Ostermaier, H. Ceric, M. Waltl, T. Grasser Charge trapping effects are considered as one of the most severe reliability issues in gallium nitride (GaN)/aluminium gallium nitride (AlGaN) metal-insulator-semiconductor HEMTs (MISHEMTs). Thus, the identification of the origin and the physical properties of active defects is one of the key factors to improve the stability of GaN technology. In this work, we suggest two neighboring nitrogen vacancies as the origin of correlated random telegraph noise (RTN) emissions in a GaN/AlGaN fin-MISHEMT. We determine the magnitude of electrostatic coupling between these two defects by using three different approaches and verify the results by simulating the RTN emissions of a similar system using a Hidden Markov Model (HMM).
       
  • Evaluation of an InAs HEMT with Source-Connected Field Plate for
           High-Speed and Low-Power Logic Applications
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Jing Neng Yao, Yueh Chin Lin, Min Song Lin, Ting Jui Huang, Heng Tung Hsu, Simon M. Sze, Edward Y. Chang In this study, we have presented a source-connected field plate (SCFP) InAs high electron mobility transistor (HEMT) and evaluated its potential for using in high-speed and low-power logic applications. The fabricated device demonstrated good electrical characteristics including low subthreshold swing (SS) of 76 mV/decade, drain induced barrier lowering (DIBL) of 44 mV/V, ION /IOFF ratio of 2.4 × 104, an off-state gate leakage current of less than 5×10-6 A/mm and a Gm,max of 1100 mS/mm at VDS= 0.5V. When increasing the drain-source bias (VDS) to 1.0 V, the Gm,max increased to 1750 mS/mm with a cut-off frequency of 113 GHz. These results revealed that the fabrication of source-connected field plate InAs HEMTs achieved excellent device performance for high-speed and low-power logic applications.
       
  • Experimental analysis and improvement of the DC method for self-heating
           estimation
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): C.A.B. Mori, P.G.D. Agopian, J.A. Martino This paper reports an improved method for estimating the thermal resistance of a MOSFET device using the inverse of the transistor efficiency as a function of the power applied to the transistor’s channel. This method was deduced considering that the main effect of the self-heating is on the carriers’ mobility, where the temperature dependency, vertical/lateral field degradation and saturation velocity were taken into account. After performing the analytical considerations, the method was validated through numerical simulations to verify if its results were compatible with other traditional pulsed-like method for the thermal resistance extraction. This improved method was applied experimentally to attest its robustness. The advantages of this method are the use of DC measurements only and differences smaller than 10 K in the estimation of the absolute channel temperature due to the self-heating effect compared to a traditional pulsed-like method for the UTBB SOI studied in this work.
       
  • Transient Negative Capacitance and Charge Trapping in FDSOI MOSFETs with
           Ferroelectric HfYOX
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Qinghua Han, Paulus Aleksa, Thomas Carl Ulrich Tromm, Juergen Schubert, Siegfried Mantl, Qing-Tai Zhao Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.
       
  • A Smart Noise- and RTN-Removal Method for Parameter Extraction of CMOS
           Aging Compact Models
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Javier Diaz-Fortuny, Javier Martin-Martinez, Rosana Rodriguez, Rafael Castro-Lopez, Elisenda Roca, Francisco V. Fernandez, Montserrat Nafria In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.
       
  • Ferroelectric properties of SOS and SOI pseudo-MOSFETs with
           HfO2 interlayers
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): V.P. Popov, V.A. Antonov, M.A. Ilnitsky, I.E. Tyschenko, V.I. Vdovin, A.V. Miakonkikh, K.V. Rudenko The formation of a multi-crystalline HfO2 film, containing the ferroelectric phase OII (Pmn21) after a high-temperature annealing at 1100°C, was experimentally observed by HREM for the first time in silicon-on-sapphire (SOS) structures obtained by direct bonding and a hydrogen transfer of silicon layer on Si or C-sapphire substrates, respectively. PEALD HfO2 interlayers with the thickness of 20 nm were deposited on silicon before bonding to reduce the defects and magnitude of their charge at the SOS and silicon-on-insulator (SOI) interfaces. SOS pseudo-MOS transistors demonstrate standard drain-gate characteristics with the same charge carrier mobility as in bulk silicon and a small positive fixed charge (≤1.2x1012 cm-2). Moreover, a stable ferroelectric hysteresis with ΔVG ∼700 V observed only in SOS FETs is promising for the embedded memory formation and it extends the functionality of logic circuits. It was concluded that the OII phase is stabilized mainly by a high compressive stress and it is responsible for the hysteresis in the case of SOS pseudo-MOSFETs opposite to the SOI-structure.
       
  • Low temperature influence on performance and transport of Ω-Gate p-type
           SiGe-on-Insulator Nanowire MOSFETs
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.
       
  • New prospects on high on-current and steep subthreshold slope for
           innovative Tunnel FET architectures
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): C. Diaz Llorente, J-P Colinge, S. Martinie, S. Cristoloveanu, J. Wan, C. Le Royer, G. Ghibaudo, M. Vinet We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm-3) thin layer at the bottom for extremely small body thickness (TSi < 7 nm), increases ION even for small gate lengths (LG < 100 nm). The implementation of an embedded tip in the source enhances the maximum electric field at the source/channel junction, but the impact on the performance is limited because the tunneling area is not increased. Therefore, this architecture provides a performance similar to a standard TFET. TCAD simulations using SiGe with different germanium concentrations (30% and 50%) and pure germanium, instead of silicon, show an increase of the interband tunneling current when using an ultrahigh dopant concentration thin boron layer for small gate lengths (LG < 50 nm). The reduction of the tunneling current using a relatively thick channel (11 nm – 7 nm) can be compensated by using a higher germanium concentration to reduce the energy bandgap. However, this will increase the density of defects causing a TAT tunneling instead of interband tunneling, jeopardizing the possibility of achieving a subthreshold swing below 60 mV/dec.
       
  • Current and Shot Noise at Spin-dependent Hopping through Junctions with
           Ferromagnetic Contacts
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Viktor Sverdlov, Siegfried Selberherr Upcoming mass production of energy efficient spin-transfer torque magnetoresistive random access memory will revolutionize microelectronics by introducing non-volatility not only in memory but also in logic. The pressing issue is to boost the sensing margin by improving the tunneling magnetoresistance ratio. We demonstrate that spin-dependent trap-assisted tunneling in magnetic tunnel junctions can increase the tunneling magnetoresistance ratio. The impact of spin decoherence and relaxation on the current and shot noise at trap-assisted hopping is investigated in both normal contact-trap-ferromagnet and ferromagnet-trap-ferromagnet systems. In addition, our approach resolves a controversy between the two theoretical approaches to spin-dependent trap-assisted tunneling available in literature.
       
  • Investigation of built-in Bipolar Junction Transistor in FD-SOI BIMOS
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Thomas Bédécarrats, Philippe Galy, Claire Fenouillet-Béranger, Sorin Cristoloveanu The built-in bipolar junction transistor (BJT) of a BIMOS fabricated in 28nm ultra-thin body and BOX (UTBB) fully-depleted silicon-on-insulator (FD-SOI) high-k metal gate technology is investigated in common-emitter mode and in built-in metal-oxide-semi-conductor field effect transistor (MOSFET) off-state. In the weak VBE regime, field-effects dominate, generating a negative base current and making the current gain β0 meaningless. For VBE high enough, the BJT works normally but with a very low gain below 1.
       
  • Compact Modeling of Triple Gate Junctionless Mosfets for Accurate Circuit
           Design in a Wide Temperature Range
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Marcelo Antonio Pavanello, Antonio Cerdeira, Rodrigo Trevisoli Doria, Thales Augusto Ribeiro, Fernando Ávila-Herrera, Magali Estrada This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
       
  • Doping profile extraction in thin SOI films: application to A2RAM
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, G. Ghibaudo, J.-Ch. Barbe We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the operation and performance of A2RAM capacitorless memory cell. Assessed with TCAD simulation and simple extraction model adapted from bulk devices, this technique is validated with experimental data.
       
  • Quantum Modeling of Threshold Voltage in Ge Dual Material Gate (DMG)
           FinFET
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Rajesh Saha, Brinda Bhowmick, Srimanta Baishya An analytical model for threshold voltage of Ge dual material gate (DMG) FinFET by self consistently solving 3D Poisson’s and 2D Schrödinger’s equation is developed. The model includes the quantum effects as well. The potential distribution in the channel region is developed by solving 3D Poisson’s equation. The expression for wave function and quantized energy levels are derived by solving 2D Schrödinger’s equation. The model for inversion charge is derived by using the expression of quantized energy levels. The threshold voltage model is derived by equating inversion charge with the threshold charge estimated from TCAD simulator. The proposed models are validated with a numerical simulator for a wide range of geometrical parameter and drain bias values.
       
  • A Flexible Characterization Methodology of RRAM: Application to the
           Modeling of the Conductivity Changes as Synaptic Weight Updates
    • Abstract: Publication date: Available online 18 March 2019Source: Solid-State ElectronicsAuthor(s): M. Pedro, J. Martin-Martinez, R. Rodriguez, M.B. Gonzalez, F. Campabadal, M. Nafria In this work, an automatic and flexible measurement setup, which allows a massive electrical characterization of single RRAM devices with pulsed voltages, is presented. The evaluation of the G-V maps under single-pulse test-schemes is introduced as an example of application of the proposed methodology, in particular for neuromorphic engineering, where the fine analog control of the synaptic device conductivity state is required, by inducing small changes in each learning iteration. To describe the obtained data, a time-independent compact model for memristive devices is used. The fitting parameters statistical distributions are further studied.
       
  • Full Capacitance Model, Considering the Specifics of Amorphous Oxide
           Semiconductor thin film Transistors Structures
    • Abstract: Publication date: Available online 15 March 2019Source: Solid-State ElectronicsAuthor(s): A. Cerdeira, M. Estrada, Y. Hernandez-Barrios, I. Hernandez, B. Iñiguez A full capacitance model for Amorphous Oxide Semiconductor Thin Film Transistors (AOSTFTs), considering the effect of the drain contact overlap in bottom gate passivated structures is presented. It is shown that this drain overlap, on top of the passivation layer, serves as a second gate with an applied voltage equal to VDS. When VDS>VT the semiconductor-passivation (S-P) interface will be in accumulation and the behavior of the different capacitance is affected. An expression to represent this effect is included in the present model. The overlap capacitance between gate and drain/source, as well as the effect of reducing the channel capacitance as the drain is increased, are also considered by the model. The calculated capacitance is a function of the threshold voltage, (VT), the mobility and saturation parameters (γa ,αs), and the sharpness of the knee region m, which are extracted using the Unified Model and Extraction Method (UMEM) for AOSTFTs. Results are compared with simulated and experimental data.
       
  • Comparison of source/drain electrodes in Thin-film Transistors based on
           room temperature deposited Zinc Nitride films
    • Abstract: Publication date: Available online 14 March 2019Source: Solid-State ElectronicsAuthor(s): Miguel A. Dominguez, Jose Luis Pau, Abdu Orduña-Diaz, Andres Redondo-Cubero In this work, the comparison of source/drain electrodes in thin film transistors (TFTs) based on room temperature deposited Zinc Nitride (Zn3N2) films is presented. Aluminum and aluminum doped zinc oxide (AZO) films are used as electrodes. Both devices exhibit an on/off-current ratio of 104 and a subthreshold slope close to 1 V/Dec. The extracted field-effect mobility was 4.5 cm2/Vs and 1 cm2/Vs for TFTs using aluminum and AZO, respectively. Better electrical characteristics are achieved with aluminum electrodes. However, AZO electrodes made possible the fabrication of fully transparent Zn3N2 TFTs, reported for first time in this work.
       
  • Preface to FTM-2018 special issue
    • Abstract: Publication date: Available online 14 March 2019Source: Solid-State ElectronicsAuthor(s): S. Luryi, J.M. Xu, A. Zaslavsky
       
  • Synaptic Device Using a Floating Fin-Body MOSFET With Memory Functionality
           for Neural Network
    • Abstract: Publication date: Available online 14 March 2019Source: Solid-State ElectronicsAuthor(s): Sung Yun Woo, Kyu-Bong Choi, Suhwan Lim, Sung-Tae Lee, Chul-Heung Kim, Won-Mook Kang, Dongseok Kwon, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee We fabricate a floating fin-body MOSFET with charge trap layer on p-type (100) Si wafer and investigate the characteristics of the fabricated device as a synaptic device. To implement the long-term potentiation (LTP) and long-term depression (LTD), the change in conductance of the proposed device is investigated by adjusting the amount of charge in charge trap layer. A pair of synaptic device with these LTP and LTD is suggested to express the synaptic weight update in a multi-layer neural network. In addition, we show suitable weight-updating method using the proposed devices for implementing multi-layer neural networks. A 3-layer perceptron network consisted of 784 input, 200 hidden, and 10 output neurons was simulated using the conductance response of the proposed devices. In pattern recognition for 28×28 MNIST handwritten patterns, high learning performance with a classification accuracy of 95.74% is obtained when the unidirectional weight update method (B) is used.
       
  • Investigation on dependency mechanism of inverter voltage gain on current
           level of photo stressed depletion mode thin-film transistors
    • Abstract: Publication date: Available online 14 March 2019Source: Solid-State ElectronicsAuthor(s): Byeong Hyeon Lee, Sangsig Kim, Sang Yeol Lee The dependency of the inverter voltage gain on the current level (ILevel) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode ILevel. To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode ILevel. As the photo stress time increased, the D-mode ILevel increased, and the voltage gains were degraded as a result. This was mainly because the ILevel of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode ILevel, a high voltage gain of 9.85 was obtained at VDD = 3 V. It is important to note that the S.S value of the E-mode and the ILevel of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors.
       
  • Effect of a pentacene anode buffer on the performance of small-molecule
           organic solar cells
    • Abstract: Publication date: Available online 14 March 2019Source: Solid-State ElectronicsAuthor(s): Kazuhiro Hanya, Yukio Onaru, Kenji Harafuji The effect of a thin pentacene anode buffer layer on the performance of small-molecule organic solar cells (OSCs) was experimentally investigated primarily from morphological and crystallographic viewpoints. The OSC had a structure of indium-tin oxide (ITO, anode)/pentacene (anode buffer)/copper phthalocyanine (CuPc, donor)/fullerene (acceptor)/bathocuproine (cathode buffer)/Ag (cathode). The thin pentacene layer provided an enhanced initial device performance, that is, an increase of 5–29% in the short-circuit current density, resulting in an increase of 10–43% in the power conversion efficiency ηp. Atomic force microscopy showed that the roughness of the pentacene surface was large and that this roughness was increased and transferred to the overlaid CuPc surface. X-ray diffraction and near-edge X-ray absorption fine structure spectroscopy analyses showed that the standing-up CuPc crystallite orientation became randomized as the pentacene thickness was increased. The pentacene layer did not bring about the lying-down configuration of CuPc film molecules with respect to the substrate surface. The origin of the increase in ηp was the increase in the area between the donor–acceptor interface with enhanced roughness, which brought about an increase in the number of carriers generated at the interface. The reduction of energy barrier height for hole extraction from CuPc to ITO was also a possible reason for the increase in ηp.Graphical abstractGraphical abstract for this article
       
  • Electronic structure, magnetoexcitons and valley polarized electron gas in
           2D crystals
    • Abstract: Publication date: Available online 12 March 2019Source: Solid-State ElectronicsAuthor(s): L. Szulakowska, M. Bieniek, P. Hawrylak We describe here recent work on the electronic properties, magnetoexcitons and valley polarised electron gas in 2D crystals. Among 2D crystals, monolayer MoS2 has attracted significant attention as a direct-gap 2D semiconductor analogue of graphene. The crystal structure of monolayer MoS2 breaks inversion symmetry and results in K valley selection rules allowing to address individual valleys optically. Additionally, the band nesting near Q points is responsible for enhancing the optical response of MoS2.We show that at low energies the electronic structure of MoS2 is well approximated by the massive Dirac Fermion model. We focus on the effect of magnetic field on optical properties of MoS2. We discuss the Landau level structure of massive Dirac fermions in the two non-equivalent valleys and resulting valley Zeeman splitting. The effects of electron-electron interaction on the valley Zeeman splitting and on the magneto-exciton spectrum are described. We show the changes in the absorption spectrum as the self-energy, electron-hole exchange and correlation effects are included. Finally, we describe the valley-polarised electron gas in WS2 and its optical signature in finite magnetic fields.
       
  • SnO2 nanoparticles/TiO2 nanofibers heterostructures: in situ fabrication
           and enhanced gas sensing performance
    • Abstract: Publication date: Available online 11 March 2019Source: Solid-State ElectronicsAuthor(s): Kunquan Chen, Shijian Chen, Mingyu Pi, Dingke Zhang A facile electrospinning technique followed with calcinations in air has been accepted as a straight forward protocol for the research and development of SnO2/TiO2 heterostructures which are composed of SnO2 nanoparticles and TiO2 nanofibers. Characterizations of the nanocomposites by series of testing techniques indicate that the SnO2 nanoparticles were prepared and uniformly anchored on the surface of TiO2 nanofibers. Gas sensors were fabricated to investigate the gas-sensing behaviors of SnO2/TiO2 nanocomposites. Comparing with pure SnO2 nanoparticles and TiO2 nanofibers, SnO2/TiO2 nanocomposites exhibited better gas-sensing performance. The SnO2/TiO2 heterojunctional composites with the mass ratio of 1.5:1 presented an optimum operating temperature of 240 ℃. The maximum gas response relative to 100 ppm ethanol is 9.58, which is about 2.8 and 2.3 times higher, respectively, than pure TiO2 nanofibers and SnO2 nanoparticles. Meanwhile, the gas sensors prepared with SnO2/TiO2 nanocomposites also had shorter response and recovery time and long term stability. The enhanced sensing properties could be ascribed to the formation of heterojunction and the synergetic effect of SnO2 and TiO2 together with its unique nanoparticle attached fibrous architectures.
       
  • Influence of BEOL process on poly-Si grain boundary traps passivation in
           3D NAND flash memory
    • Abstract: Publication date: Available online 9 March 2019Source: Solid-State ElectronicsAuthor(s): Yuexin Zhao, Jun Liu, Ziqun Hua, Lei Jin, Zongliang Huo In this work, the influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash is investigated. Two hydrogenation methods in final passivation process are compared and hydrogen in passivation layer is found to be more effective for poly-Si grain boundary traps (GBT) passivation, according to device characteristics. Interlayer used as copper cap layer can also act as potential hydrogen diffusion source as well as final passivation layer. Besides, different interlayer films in BEOL process are found to be critical to cell device characteristics. It is considered that BEOL film stacks can influence poly-Si GBT density and cell device characteristics during subsequent hydrogen passivation process.
       
  • Wide Band Gap Semiconductor Technology: State-of-the-Art
    • Abstract: Publication date: Available online 6 March 2019Source: Solid-State ElectronicsAuthor(s): Michael Shur Applications of the wide band gap (WBG) semiconductors, such as GaN, AlGaN, and InGaN, range from lighting and ultraviolet (UV) technology to high power, radiation hard, high temperature, terahertz (THz) and sub-THz electronics and pyroelectronics. Wurtzite (hexagonal) symmetry makes these materials to be quite different from conventional cubic semiconductors. Spontaneous and piezoelectric polarization associated with the wurtzite crystal structure induces two-dimensional electron gases at AlGaN/GaN, AlInN/GaN, and AlGaN/InGaN interfaces with sheet concentrations 10 to 20 times higher than those in Si CMOS. A high current carrying capability and a high breakdown field make these materials perfect for high power applications. Adjusting the energy gaps of AlxGa1-xN and of InxGa1-xN by varying the molar fraction changes the wavelength of light they emit or absorb and enables light and UV emitters, solar cells, and photodetectors operating from THz and infrared to deep UV range. Blue, green, and white LEDs using InGaN revolutionized smart solid-state lighting. AlGaN UV LEDs are used for water purification, fighting antibiotic resistant bacteria and viruses, and dramatically increasing produce storage time. InN, ZnO, and BN have potential to compete with the AlN/GaN family. Diamond has re-emerged not only as a substrate for a record heat removal but also as a viable THz detector material. The WBG technology has many difficult problems to solve. High dislocation density in the WBG materials leads to a low efficiency of deep AlGaN UV LEDs and reliability problems of high power devices. Non-uniformities of the electric field distribution cause a premature breakdown. Using ultrathin WBG quantum well layers and nanowires and exploring radically new physics-based device designs might alleviate or even solve these problems.
       
  • Nanoelectronics with proximitized materials
    • Abstract: Publication date: Available online 5 March 2019Source: Solid-State ElectronicsAuthor(s): Igor Žutić, Alex Matos-Abiague, Benedikt Scharf, Tong Zhou, Hanan Dery, Kirill Belashchenko While materials design for many device applications usually relies on adding impurities, recent advances in scaling-down heterostructures with improved interfacial properties offer a different way to transform a large class of materials. A given material can be drastically changed by inheriting properties leaking from its neighboring regions, such as magnetism, superconductivity, or spin-orbit coupling. While these proximity effects often have a short range and are considered negligible, the situation is qualitatively different in atomically thin and two-dimensional materials where the extent of proximity effects can exceed their thickness. Consequently, proximitized materials have a potential to display novel properties and device opportunities, absent in any of the constituent region of the considered heterostructures. Such proximitized materials could provide platforms for a wide range of emerging applications: from seamless integration of memory and logic, to fault-tolerant topologically protected quantum computing.
       
  • NanoElectronics Roadmap for Europe:From Nanodevices and Innovative
           Materials to System Integration
    • Abstract: Publication date: Available online 5 March 2019Source: Solid-State ElectronicsAuthor(s): J. Ahopelto, G. Ardila, L. Baldi, F. Balestra, D. Belot, G. Fagas, S. De Gendt, D. Demarchi, M. Fernandez-Bolaños, D. Holden, A.M. Ionescu, G. Meneghesso, A. Mocuta, M. Pfeffer, R.M. Popp, E. Sangiorgi, C.M. Sotomayor Torres The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to mapping the future of European Nanoelectronics. NEREID’s objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. The roadmap will also identify promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, as well as identification of potential bottlenecks along the innovation (value) chain. Industry applications include Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing. The NEREID roadmap covers Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview of the roadmap’s structure and content.
       
  • Sub-Terahertz Testing of Millimeter Wave Monolithic and Very Large Scale
           Integrated Circuits
    • Abstract: Publication date: Available online 5 March 2019Source: Solid-State ElectronicsAuthor(s): M. Shur, S. Rudin, G. Rupper, M. Reed, J. Suarez Comprehensive Testing of Microwave Monolithic Integrated Circuits (MMICs) and Very Large Scale Integrated (VLSI) circuits is a problem of growing sophistication and importance. A commensurate problem involves the increasing relevance of hardware security, with rapidly increasing dependence of U.S. industry on imported electronics. Non-destructive, unobtrusive testing techniques are especially useful but hard to implement. In this paper, we report on using THz scanning of MMICs and VLSI circuits for testing, identification, and validation by measuring the circuit response at the pins. This technique could also be used to evaluate the reliability and lifetime of integrated circuits. This technique was demonstrated using a working and damaged MMIC with just a few transistors. For larger-scale circuits, this technique can be combined with machine learning for establishing the evolving database of the responses processed by an artificial-intelligence algorithm.
       
  • Low voltage operation of GaN vertical nanowire MOSFET
    • Abstract: Publication date: Available online 5 March 2019Source: Solid-State ElectronicsAuthor(s): D.-H. Son, J.-H. Lee, J.-G. Kim, K.-S. Im, J.-H. Lee
       
  • Possible Observation of Berry Phase in Aharonov Bohm rings of InGaAs
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): A. Aharony, O. Entin-Wohlman, L.H. Tzarfati, R. Hevroni, M. Karpovski, V. Shelukhin, V. Umansky, A. Palevski Three different methods of experimental mesoscopic physics, namely, weak antilocalization effects, universal conductance fluctuations, and Aharonov-Bohm oscillations, have been used to extract the electron phase-coherence scattering rate in two-dimensional gas of InGaAs/AlInAs heterostructures. The Aharonov-Bohm oscillations reveal strong beating effects, indicating the existence of two similar periodicities of the flux dependencies. As suggested by certain theoretical models, such a behavior might be expected from the so-called Berry phase acquired by electrons with different spin orientations in the presence of strong spin-orbit coupling and Zeeman splitting. In our paper we deduce the experimental values of the dephasing length and try to compare the observed beating pattern with possible scenarios for the appearance of the Berry phase.
       
  • Resonant amplification via Er-doped clad Si photonic molecules: towards
           compact low-loss/high-Q Si photonic devices
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): P.F. Jarschel, N.C. Frateschi Silicon photonics routers and band-pass filters employing ring resonators are usually constrained by a trade-off between quality factors and insertion loss, which is even more pronounced in compact designs. Device real estate is another factor to be considered for compactness and cost reduction. We propose an approach to simultaneously reduce insertion losses and increase the quality factor in such devices, while minimizing footprint. This approach consists in replacing the standard SiO2 top cladding of Si devices by erbium-doped Al2O3 films with a single post-processing step. Experimental results confirm the effectiveness of the method, where 1 dB output power increase is observed for a single ring device, in addition to an increase of 5% in the Q factor. In some cases of structures comprised of multiple coupled resonators, i.e., photonic molecules, the observed value of power increase is as high as 2.6 dB, with a Q factor increase of 25% and loss reduction of 3 dB.
       
  • Challenges for high performance and very low power operation at the end of
           the Roadmap
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Francis Balestra Future Nanoelectronic devices faces substantial challenges, in particular increased power consumption, saturation of performance, large variability and reliability limitation. In this respect, novel materials and innovative device architectures will be needed for Nanoscale FETs.This paper presents some promising solutions for the end of the roadmap with Multigate Nanodevices, Nanowires, Tunnel transistors, Ferroelectric FET, and Hybrid Nanocomponents using Phase Change materials or nanofilament. Other alternative materials, as ultra-thin films, 2D and 1D nanostructures, Heterostructures using strained or III-V materials, will also allow to boost these advanced nanotransistors.
       
  • The concept of electrostatic doping and related devices
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Sorin Cristoloveanu, Kyung Hwa Lee, Hyungjin Park, Mukta Singh Parihar Electrostatic doping aims at replacing donor/acceptor dopant species with free electron/hole charges induced by the gates in ultrathin MOS structures. Highly doped N+/P+ terminals and virtual P-N junctions can be emulated in undoped layers prompting innovative reconfigurable devices with enriched functionality. The distinct merit is that the carrier concentration and polarity (i.e., electrostatic doping) are tunable via the gate bias. After presenting the fundamentals, we review the family of electrostatically-doped devices fabricated with emerging or mature technologies (nanowires, nanotubes, 2D materials, FD-SOI). The multiple facets of the Hocus Pocus diode are discussed by underlining the difference with classical physical diodes. Electrostatic doping gave rise to a number of band-modulation devices with outstanding memory and sharp-switching capability. The concept, intrinsic mechanisms and typical applications are described in detail.
       
  • Epitaxy of Si-Ge-Sn-based heterostructures for CMOS-integratable light
           emitters
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Nils von den Driesch, Daniela Stange, Denis Rainko, Uwe Breuer, Giovanni Capellini, Jean-Michel Hartmann, Hans Sigg, Siegfried Mantl, Detlev Grützmacher, Dan Buca The recent rise of GeSn-based optically pumped lasers have multiplied the efforts to fabricate a fully CMOS compatible and group IV-based light emitter. Their integration with Si-based electronics may yield heavily reduced power consumption in integrated circuits and pave the way towards new sensing or medical applications. Here, we discuss the epitaxy of group IV GeSn and SiGeSn semiconductors and show their suitability for light emitting applications. Double and multi quantum well heterostructures are evaluated, whereby the latter enables an inherently easier control over the formation of deleterious misfit defects. Consequently, microdisk lasers fabricated from those show greatly enhanced light emission and reduced lasing thresholds. The use of in-situ p-i-n doping schemes allow the formation of light emitting diodes, resulting in electrically-enabled light emission already at room temperature.
       
  • Monitoring large-scale power distribution grids
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): D. Gavrilov, M. Gouzman, S. Luryi Power grids are distributed over vast geographical areas and have sophisticated multilayered architecture. The structure of the grid distribution layer is often poorly documented and sometimes unknown, presenting additional challenges to the development of systems for automated monitoring of power delivery to consumers.The proposed system performs the simultaneous functions of estimating the power grid topology (map) and monitoring of the grid operation. The core of the system is the distributed network of sensors installed at the branching points of electrical conductors. The sensors periodically measure the RMS current in the conductor, and the phase shift between current and voltage. Localization and time synchronization of sensors are performed using GPS modules. The sensors communicate over the powerline conductor. Transformers block communication signals, separating the network into clusters. The maps of the grid segments are reconstructed for each network cluster and then combined into the full grid map. The map is used for real-time monitoring of inconsistencies in the grid behavior to detect conductor breakage, powerline overload and possibly electricity theft. The autonomous sensors are inductively powered; auxiliary solar cells are installed as backup power source.
       
  • Plasmonic Modulation and Demodulation Structure for the Future Optical WDM
           Devices in Communication System
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Vitaly Sukharenko, Roger Dorsinville, Djafar Mynbaev Optical communications is the linchpin of modern communications delivering vast majority of the online traffic worldwide at the terabit-per-second rate. However, an exponential growth of this traffic requires proper increase in transmission rate, which, in turn, puts more pressure on finding new technological solutions to meet these demands. A possible direction of this search is application of plasmonics. Plasmonics has the potential to combine the best properties of both electronic and photonic worlds leading to the development of new units of optical systems in nanoscale footprints. Application of plasmonics in optical communications would lead to integration of plasmonic circuitry with digital electronics, which in turn would open new opportunities in research applications and lay the foundation for the next generation digital technology. This paper is the attempt to make one more step in this direction. Specifically, we propose the structure for plasmonic field modulation and demodulation under two conditions: (1) The work is done for narrow-band coupling conditions and (2) graphene is used as an intermediate layer between the conductor and the cover to increase the coupling efficiency at the 1550-nm wavelength. The results include a unique description of the plasmonic coupling and resonance peak for the proposed structure and analysis of the enhancement in modulation performance caused by the insertion of the graphene layer in the plasmonic structure. The possible applications of the proposed structure are also considered.
       
  • Two-pulse Sub-ns Switching Scheme for Advanced Spin-Orbit Torque MRAM
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Viktor Sverdlov, Alexander Makarov, Siegfried Selberherr The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor (CMOS) devices. However, a rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to slow down this trend is to introduce non-volatility in circuits. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential to achieve these goals. To further reduce the energy consumption, it is essential to replace SRAM in modern hierarchical multi-level processor memory structures with a non-volatile memory technology. The spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by relatively high switching currents and the need of an external magnetic field for deterministic switching of perpendicularly magnetized layers. The switching by means of two orthogonal current pulses allows achieving deterministic sub-500ps and magnetic field-free switching in perpendicularly magnetized rectangular structures. Complementing the two-pulse switching scheme with weak perpendicular interface-induced magnetic anisotropy reduces the switching current significantly for achieving sub-500ps switching in in-plane structures.
       
  • Characteristics of vertically stacked graphene-layer infrared
           photodetectors
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): M. Ryzhii, T. Otsuji, V.E. Karasik, V. Leiman, M.S. Shur, V. Ryzhii, V. Mitin We evaluate the characteristics of the vertically stacked graphene-layer infrared photodetector (VS-GLIP). Each period of the stack (which constitutes the GLIP) consists of a GL (serving as a photosensitive element with a floating potential) sandwiched between barrier layers made of the van der Waals materials, and highly conducting emitter and collector contact n-GLs. The operation of VS-GLIPs is associated with the interband photoexcitation of electrons from the GLs (direct or followed by the tunneling), injection of the electrons from the emitter layer and the collection of both the photoexcited and injected electrons by the collector layer. At a small probability of the electron capture into the floating GLs, each GLIP section exhibits an elevated photoconductive gain. Due to the vertical multi-GLIP structure the absorption efficiency can be close to unity. Due to this and because the photocurrents produced by each GLIP in the stack are summarized, the VS-GLIP can exhibit elevated detector responsivity and detectivity, in particular, exceeding those of the GLIPs.
       
  • Signatures of induced superconductivity in AlOx-capped
           topological heterostructures
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Peter Schüffelgen, Daniel Rosenbach, Yuan Pang, Jörn Kampmeier, Martina Luysberg, Lidia Kibkalo, Gregor Mussler, Dick Veldhuis, Alexander Brinkman, Li Lu, Thomas Schäpers, Detlev Grützmacher In order to access exotic Dirac and Majorana states in (Bi,Sb)-based topological insulators (TIs), the physical surface of those crystals should not be exposed to air. 2-3nm of in situ deposited Al on top of pristine TI thin films immediately oxidizes after taking the sample to ambient conditions. The native AlOx provides a favorable hard capping, which preserves the topological surface states during ex situ device fabrication. Here, we present a process on how to construct superconductor – topological insulator – superconductor (S-TI-S) junctions from in situ capped thin films comprised of 15nm Sb2Te3 on top of6nm Bi2Te3. The thicknesses of the Sb2Te3 and the Bi2Te3 layer allow us to precisely tune the Fermi level of the upper surface of the Sb2Te3 layer. The challenge is to provide a transparent interface between Sb2Te3 and the superconductive Nb, while assuring an AlOx-capped weak link in between two closely separated Nb electrodes. Low temperature experiments on our junctions provide evidence for charge transport mediated by coherent Andreev states. Magnetic field dependent measurements yielded Fraunhofer-like patterns, whose periodicities are in good agreement with the effective areas of the respective junctions. Transmission electron micrographs of the narrowest junction confirm a crystalline and capped weak link. Our results provide the first reported signatures of induced superconductivity in S-TI-S junctions, which are capped by native AlOx. The presented process allows for accessing S-TI hybrid devices via magnetic flux, while assuring in situ conserved weak links. This makes as-prepared junctions a promising platform for proposed flux-controllable Majorana devices.
       
  • Room Temperature Yellow InGaAlP Quantum Dot Laser
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): N.N. Ledentsov, V.A. Shchukin, Yu.M. Shernyakov, M.M. Kulagina, A.S. Payusov, N. Yu. Gordeev, M.V. Maximov, A.E. Zhukov, L.Ya. Karachinsky, T. Denneulin, N. Cherkashin We report simulation of the conduction band alignment in tensile–strained GaP–enriched barrier structures and experimental results on injection lasing in the green–orange spectral range (558–605 nm) in (AlxGa1–x)0.5In0.5P–GaAs diodes containing such barriers. The wafers were grown by metal–organic vapor phase epitaxy side–by–side on (811)A, (211)A and (322)A GaAs substrates, which surface orientations were strongly tilted towards the [111]A direction with respect to the (100) plane. Four sheets of GaP–rich quantum barrier insertions were applied to suppress the leakage of non–equilibrium electrons from the gain medium. Two types of the gain medium were applied. In one case 4–fold stacked tensile–strained (In,Ga)P insertions were used. Experimental data shows that self–organized vertically–correlated quantum dots (QDs) are formed on (211)A– and (322)A–oriented substrates, while corrugated quantum wires are formed on the (811)A surface. In the other case a short–period superlattice (SPSL) composed of 16–fold stacked quasi–lattice–matched 1.4 nm–thick In0.5Ga0.5P layers separated by 4 nm–thick (Al0.6Ga0.4)0.5In0.5P layers was applied. Laser diodes with 4–fold stacked QDs having a threshold current densities of ∼7–10 kA/cm2 at room temperature were realized for both (211)A and (322)A surface orientations at cavity lengths of ∼1 mm. Emission wavelength at room temperature was ∼599–603 nm. Threshold current density for the stimulated emission was as low as ∼1 kA/cm2. For (811)A–grown structures no room temperature lasing was observed. SPSL structures demonstrated lasing only at low temperatures
       
  • Exploiting topological matter for Majorana physics and devices
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): Peter Schüffelgen, Tobias Schmitt, Michael Schleenvoigt, Daniel Rosenbach, Pujitha Perla, Abdur R. Jalil, Gregor Mussler, Mihail Lepsa, Thomas Schäpers, Detlev Grützmacher Quantum computing promises to solve problems, which are impossible for classical computers. Among the different schemes of how to design a quantum computer, one particularly exotic version has raised a lot of attention lately. Although so-called topological quantum computing is a rather young concept, it promises to reduce the required overhead of physical quantum bits per logical quantum bit by a factor of 100 to 1000, due to an intrinsic protection against certain quantum errors. Once the fundamental mechanism – braiding of Majorana zero modes – is demonstrated, the topological scheme could become the most promising in terms of scalability. Currently, scientists around the globe try to exploit different materials to build first topological prototypes. This article offers a short introduction to the topological concept and also aims to review the latest developments and efforts in this rapidly evolving field. In addition to this, it discusses different platforms for experimental realization of topological protected devices. One particularly promising platform might evolve when in-situ fabrication techniques are applied to magnetically doped topological insulators. As a result, it should become possible to fabricate high fidelity Majorana devices for quantum computational tasks in a scalable fashion.
       
  • Quantum Dot 850 nm VCSELs with extreme high temperature stability
           operating at bit rates up to 25 Gbit/s at 150°C
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): N. Ledentsov, M. Agustin, V.A. Shchukin, J.-R. Kropp, N.N. Ledentsov, Ł. Chorchos, J.P. Turkiewicz, Z. Khan, C.-L. Cheng, J.W. Shi, N. Cherkashin
       
  • When will we have a quantum computer'
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): M.I. Dyakonov
       
  • Lithography for now and the future
    • Abstract: Publication date: Available online 4 March 2019Source: Solid-State ElectronicsAuthor(s): M.A. van de Kerkhof, J.P.H. Benschop, V.Y. Banine
       
  • Improvement of Sensing Margin and Reset Switching Fail of RRAM
    • Abstract: Publication date: Available online 28 February 2019Source: Solid-State ElectronicsAuthor(s): Woo Young Park, Wonki Ju, Young Seok Ko, Soo Gil Kim, Tae Jung Ha, Jae Yeon Lee, Yong Taek Park, Kyung Wan Kim, Jong Chul Lee, Jong Ho Lee, Joo Young Moon, Bo Mi Lee, Byung Gu Gyun, Byoung-Ki Lee, Jin Kook Kim To develop a high voltage read margin (△Vrd), a deep reset engineering and defect engineering are proposed. To realize the defect engineering, the amount of oxygen vacancy of resistor was controlled by optimizing the material of reservoir (RSV) and switching oxide. And we have investigated the barrier height modulation, which was formed by the Ru bottom electrode (BE) having high-work-function, to demonstrate the concept of deep reset engineering by reducing the set current (Iset) of HfO2 resistor (1R) to the turn-on current (Ith) of selector device (1S). Also, we have identified the causes of negative set fail through the chemical analysis of HfO2/BE TiN interface to improve the reset switching fail. Unstable TiON and TiOx chemical species, which present in the interface of HfO2/BE TiN, takes oxygen from the resistor HfO2 and thus creates the parasitic defects (or filament), which was injected from BE TiN. To improve the negative set fail of RRAM, we have proposed the O3 surface treatment of BE TiN and the BE Ru with superior oxidation resistance. By using a deep reset engineering, we successfully increased the △Vrd of 1 S1R by more than 0.5 V. We also demonstrated that Ru BE and the O3 surface treatment of BE TiN improved the reset window and the negative set.
       
  • Effect of beveled mesa angle on the leakage performance of 4H-SiC
           Avalanche Photodiodes
    • Abstract: Publication date: Available online 28 February 2019Source: Solid-State ElectronicsAuthor(s): Eugene Chong, Young Jin Koh, Dong-Hoon Lee, In-Ho Bae, Jong-Seon Kim, Young-Su Jeong, Jin Young Ryu, Jeong-Yoon Lee, Min-Jae Kang, Jin-Ho Park, Kyeong-Keun Choi We report on the effect of the beveled mesa angle on the performance of 4H-SiC avalanche photodiodes (APDs) with various active areas between 100 and 500 µm. The mesa structure was beveled with a smaller slope angle by using a photoresist reflow technique to suppress edge breakdown. Some beveled mesa APDs with a small angle of 10.5° were studied using high-resolution transmission electron microscopy and an electrical and optical measurement system compared with APDs with large slope angles of 28.5°. The study results show that a small-slope beveled mesa APD shows more uniform dark current level in the linear region, regardless of the active area with a sharp breakdown, and a lower dark count rate than the larger slope-angle APD.
       
  • High Concentration Phosphorus Doping in Ge for CMOS-Integrated Laser
           Applications
    • Abstract: Publication date: Available online 20 February 2019Source: Solid-State ElectronicsAuthor(s): Chan-Hyuck Park, Motoki Yako, Kazumi Wada, Yasuhiko Ishikawa, Donghwan Ahn Germanium is promising material for the laser that can be monolithically integrated on Si complementary metal-oxide-semiconductor platform and has emission wavelength of 1550 nm for optical interconnect. To obtain significant optical gain, it is necessary to achieve high n-type doping concentration level, while avoiding the damage to Ge crystalline quality. In this paper, we report an ex-situ phosphorus diffusion doping of Ge film, based on low-temperature phosphosilicate glass (PSG) pre-deposition process such as spin-on-glass and sub-atmospheric chemical vapor deposition (SACVD) methods. Closely related to optical gain properties of Ge for Ge-on-Si laser application, the photoluminescence characteristics of Ge epitaxial film after P diffusion doping were investigated. Especially, SACVD-processed PSG deposited directly on Ge film without any Si capping layer successfully led to high phosphorus doping concentration of ∼ 1019 cm-3 deep inside Ge and dramatically enhanced photoluminescence intensity by more than 10 times compared to intrinsic Ge film. By using the SACVD-PSG based P doping process, we developed an inverted-rib Ge waveguide structure for more effective optical gain. In the inverted-rib Ge structure, the mode will be positioned upward and stay relatively away from the Ge-Si interface where many dislocations are located and, as a result, we can expect less optical loss due to scattering and the overall higher mode gain. As a very promising preliminary result, from optical-pumping of the inverted-rib Ge, a threshold-like behavior starting at 18 kW/cm2 and amplified spontaneous emission around 1570 nm were demonstrated.
       
  • On the C-V characteristics of nanoscale strained Gate-All-Around Si/SiGe
           MOSFETs
    • Abstract: Publication date: Available online 20 February 2019Source: Solid-State ElectronicsAuthor(s): Amrita Kumari, Subindu Kumar, Tarun Kumar Sharma, Mukul K. Das Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the mainstream research topics of the current era in the field of semiconductor devices since they are the most efficient architectures among all multiple-gate (MG) devices. Incorporating strain in GAA device can boost the device performance significantly. As such, strained-Si (S-Si) GAA MOSFETs can have vast technological importance in future high performance logic technologies. Due to imperfections in the fabrication process, the cross-section of a GAA device may deviate from its ideal circular nature, giving rise to an elliptical structure. Capacitance-Voltage (C-V) characteristics is an important tool for characterizing such devices. For the first time, we analytically model the quasi-static C-V characteristics of elliptical S-Si GAA MOSFETs for various operating regions. We have incorporated quantum mechanical effects (QMEs) which cannot be neglected in devices having ultra-nanometre dimensions. Computations were carried out to investigate the effects of device dimensions, interface trap charges, doping concentration, germanium mole fraction and stress on the C-V characteristics of S-Si GAA MOSFETs. The possibilities for enhancing the device performance by using high-k dielectrics have also been investigated.
       
  • Synaptic Behaviors of HfO2 ReRAM by Pulse Frequency Modulation
    • Abstract: Publication date: Available online 19 February 2019Source: Solid-State ElectronicsAuthor(s): Dong Keun Lee, Min-Hwi Kim, Tae-Hyeon Kim, Suhyun Bang, Yeon-Joon Choi, Sungjun Kim, Seongjae Cho, Byung-Gook Park A resistive switching random-access memory (ReRAM) device with TiN/HfO2/SiO2/p+-Si stack is analyzed for synaptic behavior. Fabricated RRAM device stack consists of heavily doped p-type silicon bottom electrode (BE), HfO2 as a switching layer, SiO2 as a tunneling barrier layer and TiN as a top electrode (TE). The RRAM cell successfully shows I-V curves including SET and RESET operations in DC sweep mode. By inserting a SiO2 tunneling barrier layer, gradual switching characteristics are obtained by pulse operation. By optimizing the pulse scheme applied to the device, biological synaptic plasticity of long-term potentiation and depression is demonstrated. Finally, spike rate-dependent plasticity (SRDP) learning rule is realized by applying pulses with different frequencies to both terminals of the ReRAM device.
       
  • Silicon-based high-integration reconfigurable dipole with SPiN
    • Abstract: Publication date: Available online 16 February 2019Source: Solid-State ElectronicsAuthor(s): Han Su, Huiyong Hu, Pedram Mousavi, Heming Zhang, Bin Wang, Yuanhao Miao To improve the integration of reconfigurable antenna systems, a novel high-integration solid state plasma reconfigurable dipole antenna based on surface PiN (SPiN) diodes was presented in this paper. Silicon-based SPiN diodes were the basic building blocks of plasma channel, and carrier concentration within the intrinsic region achieved a relatively high level (exceeding 1018 cm-3). In this paper, parameters of the plasma region have been extensively discussed, and several optimized band stop filters were also introduced to replace the conventional capacitor and inductor. This method greatly improved the integration of antenna system to meet the requirements of modern communications. The resonant frequencies at 2.43 GHz and 2.53 GHz have been achieved by turning on or off different sections of the dipole. The Voltage Standing Wave Ratio (VSWR) of the antenna was 1.03 and 1.34, respectively. Other parameters of this antenna were also investigated in this paper. Experimental results confirm the usefulness of the SPiN diodes within solid state plasma antenna and other semiconductor fields.
       
  • Mobility extraction for short channel UTBB-FDSOI MOSFETs under back bias
           using an accurate inversion charge density model
    • Abstract: Publication date: Available online 5 February 2019Source: Solid-State ElectronicsAuthor(s): L. Trojman, L-Å Ragnarsson, N. Collaert In this work we measure the inversion charge density for short UTBB-FDSOI MOSFET (down to 45nm) using an accurate method for the extraction of the parasitic components which take into account the effect of the back bias. Based on these results, we propose a modification of the inversion charge density model that uses the simplified Lambert function in order to include the back bias effect. This model is then validated with the experimental data for different gate length (from 185nm to 45nm). It is shown that this inversion charge model is valid for the mobility extraction and give very good assessment of the mobility if we know only the IV-characteristic, the threshold voltage (with back bias effect) and the inversion charge capacitance. Finally, this method is used to extract the mobility for short channel devices (down to 40nm) and it is found that the short channel mobility suffers from degradation even for large back bias. For the shortest device, it is demonstrated that the main source of mobility degradation is caused by oxide charges and interface states located near the S/D extensions and then it is deduced that the mobility reduction for large back bias is related to neutral defect from Si-crystal close to the channel edge.
       
  • Experimental validation of the surface state distribution model in the
           Suzuki theory to qualify the thin film surface materials
    • Abstract: Publication date: Available online 5 February 2019Source: Solid-State ElectronicsAuthor(s): L. Pichon, K. Yang, A-C. Salaün The relevance of the theoretical Suzuki’s model of surface state density to determine the surface states distribution at the active layer/silicon dioxide interfaces is carried out in polycrystalline silicon thin film transistors (TFTs) issued from two different crystallization technologies of the active layer: furnace solid phase crystallized (FSPC) and laser solid phase crystallized (LSPC) TFTs. The experimental validation of this model is demonstrated using the field effect conductance method. Results show that distribution is higher for the FSPC TFTs in relationship with the process crystallization of the active layer. In addition, it is shown that theoretical surface state model allows discriminating dangling bonds states and tail states distributions and acts as relevant model to qualify the surface of thin film material.
       
  • Reconfigurable logic for carry-out computing in 1-bit full adder using a
           single magnetic tunnel junction
    • Abstract: Publication date: Available online 5 February 2019Source: Solid-State ElectronicsAuthor(s): Gi Yoon Bae, Yechan Hwang, Sangmin Lee, Taewan Kim, Wanjun Park We propose a method for reconfigurable logic using a single magnetic tunnel junction (MTJ) as the main computing element in the single-gate architecture. The introduction of the MTJ to reconfigurable computing provides advantages in layout efficiency, power consumption, and the device variation problem. In this study, we present a three-terminal MTJ implemented by two inputs (ampere magnetic field and spin torque-transfer current) acting as a logic element that performs the Boolean logic functions of NAND and NOR with corresponding programmable input values in a fixed architecture. In addition, the reconfigurable functionality is confirmed through demonstration of carry-out computing across the operator built with single-MTJ logic architecture.
       
  • Degradation and failure mechanism of AlGaN-based UVC-LEDs
    • Abstract: Publication date: Available online 25 January 2019Source: Solid-State ElectronicsAuthor(s): Zhanhong Ma, Haicheng Cao, Shan Lin, Xiaodong Li, Lixia Zhao The degradation behaviors of flip-chip 260nm ultraviolet light emitting diodes (UVC-LEDs) were studied using in-situ accelerated system and different analytical technologies. The optical power of LEDs stressed at a constant DC current of 20mA decreased to about 63% of the initial value after 150 h. The failure mechanisms were investigated systematically by using current-voltage measurements, Secondary Ion Mass Spectroscopy, Transient Thermal Analysis, Scan Electron Microscopy, etc. The results show that: the concentration of H in p-GaN layer decreased from 4.5e17 atoms/cm3 for the unstressed samples to 6.0e16 atoms/cm3 for stressed sample, while there is no change for the Mg concentration, indicating the hydrogen dissociated from the Mg-H complex resulting from the activation of the Mg-dopant during the stressed period; the increase of the current for the reverse bias region and the low-forward bias region during stress is due to the increase in defect-assisted carrier tunneling; the diffusion of contact metal during stress lead to the decrease of the thermal resistance of die attach. These results will help to improve the reliability design of AlGaN-based deep-UV LEDs.
       
  • Tunneling Field Effect Transistors (TFETs) with 3D Fin-shaped Channel
           Structure and Their Electrical Characteristics
    • Abstract: Publication date: Available online 11 January 2019Source: Solid-State ElectronicsAuthor(s): Donghwan Lim, Hoonhee Han, Changhwan Choi In this study, we have demonstrated 3D fin-structured channel Silicon-On-Insulator (SOI) tunneling field effect transistor (TFET) to enhance transistor on-current (Ion) by reducing leakage current and enhancing gate controllability. By comparing with planar TFET, the subthreshold swing (S.S) value is apparently reduced by ∼20 mV/dec with increased Ion using fin-typed TFET. Moreover, we have investigated impact of the interfacial layer (IL) modulation on the electrical characteristics of each planar TFET and fin-typed TFET, where IL modulation was performed by adopting modified chemical oxide as well as interface treatment. The IL modulation is substantial on the fin-typed TFET in terms of off leakage current (Ioff) as well as threshold voltage instability (△Vth) against electrical stress, indicating 3D channel is more sensitive to interface condition. Our results suggest that alternative 3D structure with an appropriate interface treatment might be beneficial to attain better Ion while keeping lower S.S and Ioff.
       
  • A Macro Model of RF Schottky Diode in 22-nm CMOS and Its Application
    • Abstract: Publication date: Available online 10 January 2019Source: Solid-State ElectronicsAuthor(s): Chao Xu, Pingping Yu, Yanfeng Jiang RF Schottky Barrier Diode (SBD) device can be compatible with deep submicron CMOS process, which is a research edge-cutting technology in the field of microelectronics. An accurate device model is highly required by the relevant circuit simulation work. In this paper, a macro device model of SBD in 22 nm CMOS node is developed based on the actual device structure. To increase its accuracy, a novel iterative algorithm is employed during the model parameter extraction. The simulation results are consistent with experimental data in frequency range from 10 MHz to 10 GHz, indicating that the developed SBD model can accurately reflect the DC and RF characteristics of the 22 nm device. Moreover, the application of the developed RF SBD device model is verified based on RF energy harvesting circuit in terms of the output voltage and efficiency, showing the feasibility of the developed SBD model in RF integrated circuit.
       
 
 
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