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  Subjects -> ELECTRONICS (Total: 193 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advanced Materials Technologies     Hybrid Journal  
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 7)
Advances in Electronics     Open Access   (Followers: 94)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Power Electronics     Open Access   (Followers: 39)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 353)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 26)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 14)
Australian Journal of Electrical and Electronics Engineering     Hybrid Journal  
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Batteries     Open Access   (Followers: 7)
Batteries & Supercaps     Hybrid Journal  
Bell Labs Technical Journal     Hybrid Journal   (Followers: 30)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 22)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 38)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 13)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 9)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 308)
ECTI Transactions on Computer and Information Technology (ECTI-CIT)     Open Access  
ECTI Transactions on Electrical Engineering, Electronics, and Communications     Open Access   (Followers: 1)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 123)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 104)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 103)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 55)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage     Hybrid Journal  
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPE Journal : European Power Electronics and Drives     Hybrid Journal  
EPJ Quantum Technology     Open Access   (Followers: 1)
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 209)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 100)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 81)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 51)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 75)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 73)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 58)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 26)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 44)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 78)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Energy Systems Integration     Open Access  
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 57)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 74)
Industrial Technology Research Journal Phranakhon Rajabhat University     Open Access  
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 38)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 11)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 5)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 3)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 16)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 10)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 25)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 4)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 11)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 35)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 8)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 9)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 5)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 3)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 183)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 10)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 10)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal   (Followers: 3)
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 11)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 30)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 6)
Microelectronics and Solid State Electronics     Open Access   (Followers: 28)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 42)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal   (Followers: 1)
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 9)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 2)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 56)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 78)
Solid State Electronics Letters     Open Access  
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 3)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Transactions on Electrical and Electronic Materials     Hybrid Journal  
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Ural Radio Engineering Journal     Open Access  
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
Solid-State Electronics
Journal Prestige (SJR): 0.492
Citation Impact (citeScore): 2
Number of Followers: 9  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0038-1101
Published by Elsevier Homepage  [3177 journals]
  • Novel Fine-Grain Back-Bias Assist Techniques for 3D-Monolithic 14nm FDSOI
           Top-Tier SRAMs
    • Abstract: Publication date: Available online 2 December 2019Source: Solid-State ElectronicsAuthor(s): D. Bosch, X. Garros, A. Makosiej, L. Ciampolini, O. Weber, J. Lacord, J. Cluzel, B. Giraud, R. Berthelon, G. Cibrario, L. Brunet, P. Batude, C. Fenouillet-Béranger, D. Lattard, J.P. Colinge, F. Balestra, F. AndrieuAbstractFor the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV (up to 92mV with speed penalty) at 6σ w.r.t. planar SRAMs.
       
  • Delineation of Point Defect State in Czochralski Si by Modified Background
           Haze
    • Abstract: Publication date: Available online 2 December 2019Source: Solid-State ElectronicsAuthor(s): Anselmo Jaehyeong Lee, Don-Ha Hwang, Hee-Bog Kang, Bo-Young LeeAbstractA novel haze technique for analyzing point-defect distribution in Czochralski Si (CZ-Si) wafers without intentional contamination by transition metals was proposed. Based on the background haze in high-temperature oxidation, a three-step oxidation process including two-step low-temperature precipitation and a single-step high-temperature wet oxidation process was designed. After the newly designed heat processing and preferential etching, surface haze was formed selectively on the interstitial-dominant region of the wafer. Through electron microscopy analysis, surface defects decorated with Ni were observed, which suggested that the surface accumulation of non-gettered Ni adsorbed from the furnace causes surface haze on the interstitial-dominated region. The widths of the hazes could be optimized by adjusting the processing times of the first two steps, which affected the Ni gettering ability in the vacancy-dominated regions of the wafers. Additionally, the second stage at 1000°C was associated with precipitate growth, as well as with haze formation.
       
  • Observation of mobility and velocity behaviors in ultra-scaled L G=15 nm
           silicon nanowire field-effect transistors with different channel diameters
           
    • Abstract: Publication date: Available online 30 November 2019Source: Solid-State ElectronicsAuthor(s): Seunghwan Lee, Jun-Sik Yoon, Jinsu Jeong, Junjong Lee, Rock-Hyun BaekAbstractExperimentally, two critical device performance factors, apparent mobility (μapp) and virtual source velocity (vx0) were investigated down to effective channel length (Leff) = 15 nm silicon nanowire field-effect transistors (SNWFETs) by using virtual source (VS) model. Both μapp and vx0 decreased in n-SNWFETs but increased in p-SNWFETs as the nanowire diameter (DNW) shrank because of opposite effective mass (meff) dependency. The critical on-current booster, vx0 rather than μapp increased monotonically as Leff shrank, and it showed that vx0 boosting by Leff scaling is still valid to Leff= 15 nm in SNWFETs. Furthermore, p-SNWFETs had higher μapp and vx0 than n-SNWFETs because compressive stress from SiGe layer below source/drain improved the performance of p-SNWFETs. Interestingly, unpredicted non-linearity of Leff/μapp vs. 1/vx0 plot was observed in short channel p-SNWFETs and its origin was discussed. Finally, thermal limit velocity (vTx) and ballistic efficiency (Bsat) consisting vx0 were extracted from experimental data. The DNW dependence of vTx and Bsat was analyzed using stress effect, meff, critical length (LC), and mean free path (λ), which provides the way of vx0 boosting.
       
  • Robust Magnetic Field-Free Switching of a Perpendicularly Magnetized Free
           Layer for SOT-MRAM
    • Abstract: Publication date: Available online 27 November 2019Source: Solid-State ElectronicsAuthor(s): R.L. de Orio, A. Makarov, S. Selberherr, W. Goes, J. Ender, S. Fiorentini, V. SverdlovAbstractWe investigate the robustness of a purely electrical field-free switching of a perpendicularly magnetized free layer based on SOT. The effective magnetic field which leads to deterministic switching of a rectangular as well as of a square free layer is created dynamically by a two-current pulse scheme. It is demonstrated that the switching is very robust, being insensitive to fluctuations of the write pulses’ durations and to relatively large variations of the heavy metal wires’ dimensions. Furthermore, it remains reliable for a wide range of synchronization failures between the pulses. The combination of a rectangular free layer shape with a partial overlap with the second current line accelerates the switching of the cell allowing a fast, 0.25  ns, switching.
       
  • Physics-Based Compact Model of Transient Leakage Current Caused by
           Parasitic Bipolar Junction Transistor in Gate-All-Around MOSFETs
    • Abstract: Publication date: Available online 27 November 2019Source: Solid-State ElectronicsAuthor(s): Boram Yi, Yeong-Hun Park, Ji-Woon YangAbstractIn this study, transient leakage current caused by a parasitic bipolar junction transistor (BJT) in nanowire-type gate-all-around metal–oxide–semiconductor field-effect transistors is physically modeled for circuit design. The model considers the majority carrier concentration in the body, which is modulated by the gate-to-body bias. The parasitic BJT gain is dependent on the majority carrier concentration, which exceeds the body doping concentration in transient conditions. Three-dimensional technology computer-aided design simulation is performed to verify the model. The model accurately predicts the transient leakage current according to various structural parameters.
       
  • Behavior of Gold-Doped Silicon Substrate under Small- and Large-RF Signal
    • Abstract: Publication date: Available online 27 November 2019Source: Solid-State ElectronicsAuthor(s): Massinissa Nabet, Martin Rack, Nur Zatil Ismah Hashim, C.H. (Kees) de Groot, Jean-Pierre RaskinAbstractIn this paper, small- and large-signal performances of passive devices integrated on high-resistivity, trap-rich and gold-doped silicon wafers are presented and compared through measurements and simulations. The gold-doped silicon substrate was produced starting from standard silicon having a nominal resistivity of 56 Ω·cm. We show that the gold-doped substrate presents high effective resistivity and low losses suitable for RF applications. This has been demonstrated by measuring coplanar waveguides, crosstalk, inductors and band pass filter where we observed similar performances for small-signal measurements compared with trap-rich substrate. Large-signal measurements of gold-doped substrates show 60 dBm lower harmonic distortion than high-resistivity substrates, and 10 dB lower than trap-rich substrate at 0 V DC bias. However, a large DC bias dependence on the harmonic distortion induced by the gold-doped substrate is observed. This unexpected behavior is explained using the Fermi level localization in the silicon bandgap for the different DC bias conditions.
       
  • Hafnia and alumina stacks as UTBOXs in silicon-on insulator
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): V.P. Popov, V.A. Antonov, A.K. Gutakovskiy, I.E. Tyschenko, V.I. Vdovin, A.V. Miakonkikh, K.V. RudenkoAbstractPEALD-grown hafnia and alumina buried oxide (BOX) stacks in silicon-on-insulator (SOI) structures were produced and characterized by XTEM and pseudo-MOSFET techniques. The ferroelectric phases of hafnia were observed by XTEM and SAED. It was shown that the minimal interface states density (IFS) < 1012cm-2 and the maximal one with a memory window MW ∼ 1 V could be obtained by the right choice of high-k dielectric layer sequence in BOX stack and thermal processing.
       
  • Size effect of electronic properties in highly arsenic-doped silicon
           nanowires
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): Tom Mauersberger, Imad Ibrahim, Matthias Grube, André Heinzig, Thomas Mikolajick, Walter M. WeberAbstractThe unique electrostatic properties of semiconductor nanowires enable the realization of novel transistor types by the possibility to use surround gate architectures resembling ideal gate electrostatic control. Nevertheless one fundamental issue of semiconducting nanowire channels is the reliable control of doping to adjust the charge carrier concentration. Indeed, as dimensions scale down the surrounding media and the interfaces become more important. In this study we investigate the role of surface depletion and dielectric mismatch on the electronic charge transport of highly arsenic doped and bottom-up grown silicon nanowires. Electrical characterization of silicon nanowires (SiNWs) synthesized by Au catalyzed vapor-liquid-solid (VLS) growth and in-situ arsine (AsH3) doping is reported for the first time. We demonstrate that high n-type doping is possible by adjusting the dopant precursor flow ratio during growth. Based on electrical measurements of individual nanowires, reproducible donor concentrations of up to 5.2 × 1019 cm-3 could be revealed. By measuring the electrical characteristics for individual nanowires in dependence on their radius, we show that the electrically active carrier density drastically reduces for small nanowires at radii much larger than those at which quantization or dopant surface segregation effects are expected to occur. Furthermore, enhancement of the contact transparency for small radii nanowires is demonstrated through dopant segregation upon metal silicidation. Size dependent measurement of electrical characteristics revealed improved contact resistivities as low as 1.4 × 10-11 Ωm2.
       
  • Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory
           Applications
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): A. Veloso, T. Huynh-Bao, P. Matagne, D. Jang, G. Eneman, N. Horiguchi, J. RyckaertAbstractWe report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read and write stability), and as the selector devices for ultra-scaled MRAMs with lower energy consumption values. These cells can be manufactured by a cost-effective, co-integration scheme with a triple-gate finFET or a lateral NW/NS GAA FET high-performance logic platform for increased on-chip memory content.
       
  • Resistive Switching Behavior of Solution-processed AlOx and GO based RRAM
           at Low Temperature
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): YF Qi, ZJ Shen, CZ Zhao, IZ Mitrovic, WY Xu, EG Lim, L Yang, JH He, T Luo, YB Huang, C ZhaoAbstractThis paper reports on resistive switching behavior observed in resistive random access memory (RRAM) devices fabricated with aluminum oxide (AlOx) and graphene oxide (GO) dielectric films, which were solution-processed under low annealing temperatures of 250°C and 50°C for AlOx and GO dielectric films, respectively. As representative of metal oxide and two-dimensional material, a detailed study and comprehensive comparison in view of resistive switching performance has been conducted for AlOx and GO based RRAM, including operation voltage, resistance distribution, resistance ratio, conduction mechanism and retention/endurance property. A smaller operation voltage and better stability were demonstrated in AlOx based RRAM devices while higher resistance magnitude of high resistance state (HRS) and resistance ratio were observed in GO based RRAM devices. The current study opens up promising applications of environmental-friendly solution-processed AlOx and GO films with lower energy consumption for non-volatile memory (NVM).
       
  • In−situ heater for thermal assist recovery of MOS devices in 28 nm
           UTBB FD-SOI CMOS technology
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): P. Galy, R. Lethiecq, M. BawedinAbstractPreliminary results are reported on an in-situ heater for thermal assist recovery of MOS transistor and is demonstrated in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) Ultra-Thin Body and Buried oxide (UTBB) high-k metal gate CMOS technology. This approach consists in functionalizing the source of a MOS device. We demonstrate that it is possible to heat the device with the current flowing between two split source contacts. Electrical and temperature measurements of the structures were made at wafer level. Moreover, 3D TCAD electro-thermal simulations assess the concept. The thermal resistor calibration on source and gate are performed on low and high VT NMOS devices with thin and thick high-k metal gate oxide. We have successfully reproduced the I-V responses on several samples at wafer level by electrical sweep in the 100 ns range into the split source contacts. The local temperature change effect was measured from room temperature up to + 300 K. Finally, this first study shows that the thermal recovery is efficient and opens the door on new innovative solutions and could be applied on other technology nodes.
       
  • Scaled resistively-coupled VO2 oscillators for Neuromorphic
           Computing
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): Elisabetta Corti, Bernd Gotsmann, Kirsten Moselund, Adrian Ionescu, John Robertson, Siegfried KargAbstractNew computation schemes inspired by biological processes are arising as an alternative to standard von-Neumann architectures, to provide hardware accelerators for information processing based on a neural networks approach. Systems of frequency-locked, coupled oscillators are investigated using the phase difference of the signal as the state variable rather than the voltage or current amplitude. As previously shown, these oscillating neural networks can efficiently solve complex and unstructured tasks such as image recognition. We have built nanometer scale relaxation oscillators based on the insulator-metal transition of VO2. Coupling these oscillators with an array of tunable resistors offers the perspective of realizing compact oscillator networks. In this work we show experimental coupling of two oscillators. The phase of the two oscillators could be reversibly altered between in-phase and out-of-phase oscillation upon changing the value of the coupling resistor, i.e. by tuning the coupling strength. The impact of the variability of the devices on the coupling performances are investigated across two generations of devices.
       
  • A BIMOS-based 2T1C analogue spiking neuron circuit integrated in 28nm
           FD-SOI technology for neuromorphic application
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): Thomas Bédécarrats, Claire Fenouillet-Béranger, Sorin Cristoloveanu, Philippe GalyAbstractNeuromorphic computing is an emerging field of investigation for new algorithm solutions and daily life applications. We propose a novel approach to achieve an operator which uses a parasitic bipolar metal oxide semiconductor filed effect transistor combined with a capacitor and a n-type metal oxide semiconductor filed effect transistor. The resulting BIMOS-based leaky-integrate-and-fire spiking neuron circuit is integrated on thin silicon film in 28 nm high-k/metal-gate advanced complementary metal oxide semiconductor technology. The proof of concept is brought by 3-dimensional technology computer-aided design numerical simulations, and then validated by electrical characterization of the two-transistors-one-capacitor demonstrator. The underlying physical phenomena involved in the spiking mechanism are identified, explained and modelled. Low power consumption is obtained. In addition, the spiking neuron device benefits from intrinsic electro-static discharge robustness.
       
  • Novel On-Resistance based Methodology for MOSFET Electrical
           Characterization
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): T.A. Karatsori, K. Bennamane, G. GhibaudoAbstractA new methodology for MOSFET characterization making use of the on-resistance characteristics Ron(Vg,Vd)=Vd/Id(Vg,Vd) and associated derivatives dRon/dVg and dRon/dVd is proposed. This approach enables to eliminate the influence of source-drain series resistance Rsd not only in linear region but also in non-linear region of MOSFET operation. Therefore, it allows for intrinsic MOSFET parameter extraction free from source and drain series resistance.
       
  • Foreword
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s):
       
  • Post-process porous silicon for 5G applications
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): Gilles Scheen, Romain Tuyaerts, Martin Rack, Lucas Nyssens, Jonathan Rasson, Massinissa Nabet, Jean-Pierre RaskinAbstractThe interest of 5G in centimeter and millimeter waves relies on large blocks of available spectra and thus increased bandwidth. At these frequencies, the dielectric and conductive losses of the substrate can greatly degrade the performances of RF circuits. With high electrical resistivity and low relative permittivity, porous silicon is an ideal candidate as a high-quality RF substrate. This paper presents an innovative technique of post device fabrication integration of porous silicon (POST-PSi) with the substrate. The frontside is not involved in porous layer growth and therefore the integrity of the RF circuitry is not impacted by the POST-PSi process. A comparison of the RF performances with benchmark trap-rich (TR) RF silicon substrate is presented. In addition to its compatibility with standard microfabrication processes and stable final structure, POST-PSi provides characteristics of low losses, high isolation and very high linearity, unmatched by any other silicon-based substrate. Finally, the substrate’s RF performance is evaluated at high temperature, and POST-PSi substrate linearity is shown to remain sufficiently high for RF and 5G applications up to 175 °C.
       
  • Experimental and simulation investigation of the out-of-equilibrium
           phenomena on the Pseudo-MOSFET configuration under transient linear
           voltage ramps
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): Miltiadis Alepidis, Licinius Benea, Davide Bucci, Xavier Mescot, Maryline Bawedin, Irina IonicaAbstractThe pseudo-MOSFET configuration is an electrical characterization technique developed for silicon-on-insulator (SOI) wafers. The wide variety of experiments that have been performed to date have also extended recently in the study of out-of-equilibrium phenomena for bio-sensing applications. However, the lack of a full understanding of the ohmic contact behaviour between the probes and the low doped silicon film results in simulation inconsistencies. This work proposes a simulated device structure that is capable of reproducing the behaviour of the device and further extends the experiments into large-signal linear ramps which are also reproduced through simulations.
       
  • A2RAM Compact Modeling: From DC to 1T-DRAM Memory Operation
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, G. Ghibaudo, J.-Ch. BarbeAbstractIn this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architecture as the combination of a SOI transistor in parallel with a variable-resistance bridge. The crucial aspect is the analytical description of the bridge threshold voltage. The complete A2RAM compact model is implemented in Verilog-A to allow the use of SPICE simulator. DC and memory characteristics are validated by TCAD. SPICE simulations show the operation of 2x2 A2RAM matrix.
       
  • A method for threshold voltage extraction in junctionless MOSFETs using
           the derivative of transconductance-to-current ratio
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): T. Rudenko, A. Nazarov, S. Barraud, V. Kilchytska, D. FlandreAbstractIn this paper, using numerical simulations, analytical modeling and experimental data, we validate the applicability of the transconductance-to-current ratio (gm/ID) derivative (d(gm/ID)/dVG) method for extracting the threshold voltage (VTH) in junctionless (JL) MOSFETs and show its advantages over the commonly-used transconductance derivative (or double derivative of drain current) method (dgm/dVG≡d2ID/dVG2). It is shown that, although both methods are based on the same theoretical VTH-criterion, the d(gm/ID)/dVG method is more accurate than the d2ID/dVG2 method due to its lesser sensitivity to the gate-voltage-dependent mobility and series resistance parasitic effects, being particularly important in JL MOSFETs.
       
  • A2RAM Compact Modeling: From DC to 1T-DRAM Memory Operation
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, G. Ghibaudo, J.-Ch. BarbeAbstractIn this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architecture as the combination of a SOI transistor in parallel with a variable-resistance bridge. The crucial aspect is the analytical description of the bridge threshold voltage. The complete A2RAM compact model is implemented in Verilog-A to allow the use of SPICE simulator. DC and memory characteristics are validated by TCAD. SPICE simulations show the operation of 2x2 A2RAM matrix.
       
  • Analysis of the Role of Inter-Nanowire Junctions on Current Percolation
           Effects in Silicon Nanonet Field-Effect Transistors
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): T. Cazimajou, M. Mouis, M. Legallais, T.T.T. Nguyen, C. Ternon, B. Salem, G. GhibaudoAbstractIn this paper, we compare the evolution with temperature of the experimental characteristics of Nanonet-based Field-Effect Transistors, with a modelling of carrier transport in the percolating regime. The main electrical parameters of Nanonet-based Field-Effect Transistors that featured different nanowire densities and source-drain distances were extracted from static measurements at different temperatures. The temperature dependence of low field mobility and threshold voltage was explained by the temperature activated behaviour of inter-nanowire junctions, and the activation energy dispersion of individual junctions. A Monte-Carlo simulation of Nanonet FET in the shape of a random percolating network of resistances and thermally activated junctions was used to confirm the influence of activation energy dispersion on low field mobility. The simplest model which was able to capture experimental trends consisted in a bimodal distribution of activation energies, with a subset of non-thermally activated junctions (resistive junctions) while other junctions were thermally activated (energy barriers at the junctions).
       
  • Vertical Heterojunction Ge0.92Sn0.08/Ge Gate-All-Around Nanowire pMOSFETs
           with NiGeSn Contact
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): Mingshan Liu, Konstantin Mertens, Nils von den Driesch, Viktoria Schlykow, Thomas Grap, Florian Lentz, Stefan Trellenkamp, Jean-Michel Hartmann, Joachim Knoch, Dan Buca, Qing-Tai ZhaoAbstractVertical heterojunction Ge0.92Sn0.08/Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top-down approach are reported. With optimized processes, pFETs with nanowire diameters as small as 32 nm were achieved and a decent ION/IOFF ratio of ∼3×106 was obtained thanks to to the GAA nanowire geometry, the GeSn/Ge heterostructure and NiGeSn metallization. A compensating effect between top souce resistance and diameter-related electrostatics was identified for pFETs without NiGeSn source. Devices with NiGeSn source showed significant improved ION, ION/IOFF ratio and subthreshold swing (SS) characteristics compared witht those without NiGeSn.
       
  • Photodiode with Low Dark Current Built in Silicon-on-Insulator Using
           Electrostatic Doping
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): J. Liu, K.-M. Zhu, A. Zaslavsky, S. Cristoloveanu, M. Arsalan, J. WanAbstractIn this paper, we demonstrate experimentally a novel SOI-based photodiode using electrostatic doping and fabricated in a simple, low-cost process. Unlike a conventional ion-implanted pn junction diode, the electrostatically doped devices feature extremely low reverse-bias current. When used for photodetection, our devices exhibit a dark current three decades lower than a conventional photodiode and provide excellent detectivity even under low optical power density. Our electrostatically-doped diodes also feature enhanced response in the near-UV and 1/f low-frequency noise.
       
  • Inter-Tier Electrostatic Coupling Effects in 3D Sequential Integration
           Devices and Circuits
    • Abstract: Publication date: Available online 26 November 2019Source: Solid-State ElectronicsAuthor(s): P. Sideris, L. Brunet, L. Ciampolini, G. Sicard, P. Batude, C. TheodorouAbstractThis work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.
       
  • Analysis of Fluorine Effects on Charge-Trap Flash Memory of
           W/TiN/Al2O3/Si3N4/SiO2/Poly-Si Gate Stack
    • Abstract: Publication date: Available online 22 November 2019Source: Solid-State ElectronicsAuthor(s): Tae Yoon Lee, Seung Hwan Lee, Jun Woo Son, Sang Jae Lee, Jae Hoon Bong, Eui Joong Shin, Sung Ho Kim, Wan Sik Hwang, Jung Min Moon, Yang Kyu Choi, Byung Jin ChoAbstractA charge-trap flash (CTF) memory stack of chemical vapor deposition (CVD) tungsten (W) was systematically compared with a physical vapor deposited (PVD) W memory stack. The residual F in the CVD W was diffused into Al2O3, Si3N4, SiO2, and the interface at SiO2/poly-Si after the subsequent annealing process at 900˚C for 1 sec. The diffused F increased the SiO2 thickness and altered the charge-trap density in the Al2O3, Si3N4, SiO2, and SiO2/poly-Si interface, and this eventually affected memory performance and reliability. The memory window and program/erase retention properties degraded while the charge-transport and endurance characteristics improved with the CVD W memory as compared to the PVD W memory.
       
  • Enhanced charge-transportation properties of low-temperature processed
           Al-doped ZnO and its impact on PV cell parameters of organic-inorganic
           perovskite solar cells
    • Abstract: Publication date: Available online 22 November 2019Source: Solid-State ElectronicsAuthor(s): Firoz Khan, Jae Hyun KimThe present work highlights the potential of low-temperature processed Al-doped ZnO (AZO) nanoparticles (NPs) for application in organic-inorganic perovskite solar cells (PSCs). ZnO nanostructured electron-transporting layer (ETL)-based PSCs are superior to ZnO film-based PSCs owing to their relatively lower cost, simpler deposition process, milder sintering temperatures, and higher electron mobility. Moreover, the PSCs based on ZnO nanostructure ETLs are more stable than ZnO film-based PSCs because perovskite films can be easily decomposed into PbI2 during the annealing process. Al doping in ZnO can reduce the recombination at the ETL/perovskite interface. Thus, low-temperature processed AZO NPs were used as the ETLs for PSCs, and the effects of Al doping on the performance and photovoltaic parameters of PSCs were investigated. The lowest transmission loss was observed for the AZO sample with an Al/Zn molar ratio of 2%, while a higher transportation rate was obtained for the Al/Zn molar ratio of 5%. The effectiveness of Al doping was demonstrated by a conversion efficiency (η) of 13.91% for the Al/Zn molar ratio of 2% (η = 12.28% for ZnO). Moreover, the short-circuit current density (from 18.40 to 19.36 mA/cm2) and fill factor (from 67.87 to 71.18%) increased. The value of shunt resistance gradually increased (from ∼799 to 1248 Ωcm2) by Al doping. The values of diode ideality factor (from 2.3221 to 2.3175) and reverse saturation current density (from 11.97 x 10-10 to 7.95 x 10-10 A/cm2) decreased by Al doping, indicating a reduction in the recombination loss. The lowest series resistance was obtained for Al/Zn molar ratio of 2%.Graphical abstractGraphical abstract for this article
       
  • Effect of adding ZHS microcubes on ZnO nanorods for CO2 gas
           sensing applications
    • Abstract: Publication date: Available online 21 November 2019Source: Solid-State ElectronicsAuthor(s): Feng-Renn Juang, Bo-Yai ChenAbstractConventionally, the catalytic promotion of semiconductor metal oxide-based CO2 sensors response is simply based on chemical reaction. In most realistic applications, the sensors are operated in both sensing gas and light surrounding. Hence, we try to use a new type of catalyst, such as ZnSn(OH)6 (ZHS) has both chemical and photo catalytic functions to improve gas response more significantly. In this work, ZnO nanorods are deposited on p-type silicon substrate with and without ZHS microcubes covered on the top. The effects of adding the ZHS microcubes on CO2 sensing response have been studied in detail with experimental measurements. Experimental results show that the added ZHS microcubes promote CO2 response up to 350%, which is higher than the reported CO2 sensors with or without metal catalyst.
       
  • Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin
           formation technique
    • Abstract: Publication date: Available online 20 November 2019Source: Solid-State ElectronicsAuthor(s): Ji-Min Baek, Hyeon-Bhin Jo, Do-Young Yun, In-Geun Lee, Changmin Lee, Chansoo Shin, Hyoungsub Kim, Dae-Hong Ko, Tae-Woo Kim, Dae-Hyun KimAbstractIn this letter, we introduce for the first time a nano-fin patterning technique that combines Au electro-plating and high-temperature InGaAs dry etching processes. We applied this technique to fabricate vertical homojunction InGaAs tunnel-field-effect-transistors (TFETs). An InGaAs fin width (Wfin) of 60 nm was implemented with excellent line-edge-roughness (LER). The fabricated vertical homojunction InGaAs TFETs with a gate length (Lg) of 100 nm exhibited excellent device characteristics, such as a minimum subthreshold swing (Smin) of 80 mV/decade, an on-off-ratio (ION/IOFF) of 6.09 × 102 at VDS = 0.3 V, and a drain induced barrier lowering (DIBL) of 208 mV/V at room temperature.
       
  • Tensile Strain and Fermi Level Alignment in Thermally Grown TiO2 and Al2O3
           Based AlGaN/GaN MOS-HEMTs
    • Abstract: Publication date: Available online 14 November 2019Source: Solid-State ElectronicsAuthor(s): Akanksha Rawat, Vivek Kumar Surana, Swaroop Ganguly, Dipankar SahaAbstractThis work reports on the origin of performance improvement for thermally grown TiO2 and Al2O3 based AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs). The oxides have been used as gate dielectrics and passivation layer. High resolution X-ray diffraction, X-ray photoelectron spectroscopy, and transistor characteristics are analysed to investigate the improvements in the two dimensional electron gas (2DEG) concentration. The HRXRD analysis reveals that in-plane tensile stress of AlGaN layer is increased by 23% (12%) for TiO2 (Al2O3) sample as compared to that of an as-grown sample. The induced tensile stress in the AlGaN barrier layer enhances the piezoelectric polarization charges which effectively improve the carrier confinement and mobility at the interface. The improvement in the DC characteristics is observed as a reduction in the gate leakage current without deteriorating gate control and transconductance. The output characteristics of TiO2 (Al2O3) based MOS-HEMTs have shown a 60% (40%) increment in the maximum saturation drain current and 50% (40%) increment in the transconductance as compared to that of a control sample. The RF characteristics also show similar order of improvements.
       
  • Time-Resolved Electrical Characteristics of Ferroelectric-Gated Fully
           Depleted Silicon on Insulator Devices
    • Abstract: Publication date: Available online 11 November 2019Source: Solid-State ElectronicsAuthor(s): Chankeun Yoon, Changhwan ShinAbstractThe performance of fully depleted silicon on insulator (FDSOI) device and ferroelectric-gated FDSOI (FE-FDSOI) device are investigated for various gate voltage sweep rates. Regardless of the gate voltage sweep rates, the input transfer characteristics of the baseline FDOSI device are not varied. On the contrary, it was observed that the hysteresis width of the FE-FDSOI device is affected by the gate voltage sweep rates. As the gate voltage sweep rate decreases, the ratio of ferroelectric remnant polarization to coercive voltage (Pr/Vc) increases, so that the magnitude of the ferroelectric negative capacitance ( CFE ) increases. This affects hysteresis condition of the FE-FDSOI device, therefore, the hysteresis width of the FE-FDSOI device decreases as the gate voltage sweep rate decreases. According to the results, it is suggested that voltage sweep rate be decreased to decrease the hysteresis width of FE-FDSOI device.
       
  • On the DC extraction of the asymmetric parasitic source and drain
           resistances for MOSFETs
    • Abstract: Publication date: Available online 11 November 2019Source: Solid-State ElectronicsAuthor(s): Rodolfo Rodriguez-Davila, Adelmo Ortiz-Conde, Carlos Avila-Avendano, Zeshaan Shamsi, Manuel A. Quevedo-LopezAbstractTwo different parameter extraction methods are proposed in this article. First, a simple DC method is presented to extract the difference between the drain and source series resistance of MOSFETs. This method is valid for any three- or four-terminal MOSFET and it can be used in linear, triode or saturation region. Second, an integration-based method is proposed to extract the drain resistance and the source resistance of thin-film MOSFETs. Both methods were tested using simulated and measured data of two different devices: zinc oxide (ZnO) and polysilicon TFTs.
       
  • Modeling of Void Formation in Phase Change Memory Devices
    • Abstract: Publication date: Available online 7 November 2019Source: Solid-State ElectronicsAuthor(s): Adam Cywar, Zachary Woods, SangBum Kim, Matt BrightSky, Norma Sosa, Yu Zhu, Hyeong Soo Kim, Hyung Keun Kim, Chung Lam, Ali Gokirmak, Helena SilvaAbstractAn empirical versatile finite-element model is developed to predict void formation in as-deposited or melt-quenched amorphous Ge2Sb2Te5 during annealing. This model incorporates void formation with nucleation and growth of the crystals along with thermal models that capture laser heating of the nano-structures during device fabrication. Modeling of void formation during Joule heating or furnace annealing can be implemented in a similar way. The modelling results are compared to example experimental results obtained from pore-cell phase change memory structures.
       
  • Surface Ge-rich p-type SiGe Channel Tunnel Field-Effect Transistor
           Fabricated by Local Condensation Technique
    • Abstract: Publication date: Available online 7 November 2019Source: Solid-State ElectronicsAuthor(s): Junil Lee, Ryoongbin Lee, Sihyun Kim, Kitae Lee, Hyun-Min Kim, Soyoun Kim, Munhyeon Kim, Sangwan Kim, Jong-Ho Lee, Byung-Gook ParkAbstractIn this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.
       
  • On-Chip Coupled Inductors with a Novel Spliced Anisotropic and Isotropic
           Magnetic Core for Inductance and Coupling Enhancement
    • Abstract: Publication date: Available online 7 November 2019Source: Solid-State ElectronicsAuthor(s): Yuhan He, Zhipeng Zhang, Rongxiang Wu, Wei Guo, Huaiwu Zhang, Feiming BaiAbstractOn-chip solenoid coupled inductors with a spliced anisotropic and isotropic magnetic core were proposed and demonstrated for high efficiency DC-DC conversion. The proposed magnetic core design avoids easy-axis excitation at the joint parts of the magnetic loop, which not only reduces the close-loop magnetic reluctance and therefore boosts the inductance value, but also reduces the magnetic flux leakage and therefore enhances the coupling factor (k). The fabricated inductors achieved a high inductance density of 127 nH/mm2 and a large inductance to DC resistance ratio of 323 nH/Ω. The inductance gain is 51× compared to the air-core counterpart and 1.3× compared to the anisotropic-core counterpart. An enhanced k of 0.5 was also achieved compared to the k of 0.2 for the anisotropic-core counterpart. Consequently, the fabricated coupled inductors can achieve a high inductor efficiency of 96.0% for 1.8 V to 0.9 V, 152 mA per phase, 170 MHz DC-DC conversion.
       
  • All MOCVD Grown Al0.7Ga0.3N/Al0.5Ga0.5N HFET: An Approach to Make Ohmic
           Contacts to Al-Rich AlGaN Channel Transistors
    • Abstract: Publication date: Available online 31 October 2019Source: Solid-State ElectronicsAuthor(s): Hao Xue, Seongmo Hwang, Towhidur Razzak, Choonghee Lee, Gabriel Calderon Ortiz, Zhanbo Xia, Shahadat Hasan Sohel, Jinwoo Hwang, Siddharth Rajan, Asif Khan, Wu LuAbstractWe report a gate recessed Al0.7Ga0.3N/Al0.5Ga0.5N heterostructure field effect transistor (HFET) with a graded contact cap layer grown by metal organic chemical vapor deposition (MOCVD) on AlN/Sapphire substrate. A low specific contact resistivity ρc of 2.1×10-5 Ω.cm2 is demonstrated with current injection from the top of the Al0.7Ga0.3N barrier to the Al0.5Ga0.5N channel. The device with a gate length of 160 nm exhibits a drain current density at gate shorted to source (ID,SS) of 420 mA/mm, a cutoff frequency fT of 20 GHz, and a maximum oscillation frequency (fmax) of 40 GHz. The same device has a three terminal off-state gate-to-drain breakdown voltage of 170 V, corresponding to an average breakdown field (FBR) of 2.8 MV/cm between the gate and drain, due to drain induced barrier lowering effect. Devices with a gate length of 1 µm demonstrate a gate to drain breakdown voltage of 195 V or an average breakdown field of 3.9 MV/cm. This work provides a way to make ohmic contacts to Al-rich AlGaN channel heterojunction transistors for high power and high frequency applications.
       
  • A Digitally Tunable Small-Area Composite-Varactor Array Operated with
           Positive and Negative Control Voltages for High Linearity and Low Loss RF
           Circuit Applications
    • Abstract: Publication date: Available online 31 October 2019Source: Solid-State ElectronicsAuthor(s): Sanggil Kim, Donggu ImAbstractA small-area composite-varactor-based digitally tunable capacitor operated with positive and negative control voltages is proposed to remove several drawbacks resulting from the metal-insulator-metal (MIM) capacitor of the conventional switched capacitor array (SCA). It was constructed with several composite-varactor branches in parallel, each of which consists of p-type (P+/Pwell) and n-type (N+/Nwell) accumulation-mode varactors in a cascode configuration. The optimum ratio of the channel width between p-type and n-type accumulation-mode varactors was investigated through the simulation in order to maximize a quality factor (Q-factor) of the tunable capacitor at the maximum capacitance (CMAX) state. The number of composite-varactor unit in each branch was designed to be binary-weighted, and the total capacitance can vary linearly by digitally turning on and off both varactors. It was firstly implemented in 65-nm bulk CMOS process, and showed comparable tuning range, Q-factor, and harmonic distortion performances while reducing the silicon area by half and eliminating the MIM capacitor in comparison with the conventional SCA. In the measurement, the proposed tunable capacitor showed a Q-factor of 60.3 at CMAX state and a tuning range of 2.8 at 2 GHz frequency band. In addition, it was perfectly capable of handling a high power signal up to 0 dBm with excellent second and third-order harmonic distortion of greater than 70 dBc at the minimum capacitance (CMIN) state and 77 dBc at CMAX state.
       
  • Simulation of the Effect of Parasitic Channel Height on Characteristics of
           Stacked Gate-All-Around Nanosheet FET
    • Abstract: Publication date: Available online 25 October 2019Source: Solid-State ElectronicsAuthor(s): Yunho Choi, Kitae Lee, Kyoung Yeon Kim, Sihyun Kim, Junil Lee, Ryoongbin Lee, Hyun-Min Kim, Young Suh Song, Sangwan Kim, Jong-Ho Lee, Byung-Gook ParkAbstractBy using technology computer aided design (TCAD) simulation, the aim of this paper is to investigate the effect of Si parasitic channel, which is placed under stacked nanosheet channels, on electrical characteristic of stacked nanosheet GAA FETs. We have controlled the parasitic channel height, and evaluated the effect on electrical performance of the device. Trade-off in performance of the nanosheet FET is observed: the increase in parasitic channel height results in improvement in subthreshold swing and on/off ratio, while the increase in capacitance brings worse RC delay and active power. The parasitic channel height control in devices with ground plane doping is also investigated.
       
  • A monolithic low-power-consumption driver circuit based on a Dickson
           charge pump for MEMS actuator applications
    • Abstract: Publication date: Available online 21 October 2019Source: Solid-State ElectronicsAuthor(s): Hui Peng, Herbert De Pauw, Pieter Bauwens, Jan DoutreloigneAbstractThis paper introduces a monolithic high-voltage driver circuit for use in MEMS applications. The proposed design offers an output voltage which can linearly sweep from 0 V to 72.8 V under zero-load conditions. To minimize the power consumption of the driver circuit, an advanced charge recycling strategy and finger capacitor structure are implemented in the Dickson charge pump which acts as the high-voltage generator. At the maximum output voltage, the total power consumption of the driver circuit is only 2.337 mW.
       
  • Uniformity investigation of pHEMTs in 3-D MMICs for pre and post
           multilayer fabrication
    • Abstract: Publication date: Available online 21 October 2019Source: Solid-State ElectronicsAuthor(s): Mohammad A Alim, T. Begum, Ali A RezazadehAbstractThis study deals with the uniformity investigation and comparison on the typical behaviour of pseudomorphic high electron mobility transistors (pHEMTs) before and after the 3-D multilayer fabrication. There are seven multilayer fabricated pHEMTs compared with the seven virgin pHEMTs based on drain-source input current, output current, transconductance, off state leakage behaviour, threshold voltage, knee voltage, on-resistance, Schottky barrier height, ideality factor, reverse saturation current, small signal gain and current gain. Below 10% changes in performance can be seen after multilayer fabrication compare to virgin samples and apart from these exceptions, the discrepancies are well within the tolerance and less than 3% in terms of Schottky behaviour. We show that, the application of the 3D-MMIC technology does not cause any visible destruction of pHEMTs performance using seven different samples before and after the multilayer fabrication.
       
  • Analytic Modeling of Breakdown Voltage Shift in the CMOS Buried Multiple
           Junction Detector
    • Abstract: Publication date: Available online 19 October 2019Source: Solid-State ElectronicsAuthor(s): Thais Luana Vidal de Negreiros da Silva, Pascal Kleimann, Patrick Pittet, Guo-Neng LuAbstractWe propose an analytical model for the CMOS Buried Multiple Junction (BMJ) detector exhibiting breakdown voltage shift depending on adjacent junction’s bias. The device’s singular behavior has been observed when two adjacent junctions are in reach-through (RT) condition. The breakdown current has been identified to be predominated by thermionic emission. The proposed model determines, for a given BMJ structure with uniform or Gaussian doping distributions under bias conditions, whether two adjacent junctions are in RT condition. In this case, it calculates the merged depletion limits, electric field and electrostatic potential profile. The potential barrier height of each merged depletion region can then be extracted and the thermionic current be computed.Model computations have been compared with TCAD simulations and measurements on the BMJ detector. Good agreements have been observed for different structures in different bias conditions at different temperatures.
       
  • Photoresponses of the back-side illuminated GaAs photoconductive
           semiconductor switches in the linear mode
    • Abstract: Publication date: Available online 17 October 2019Source: Solid-State ElectronicsAuthor(s): Yong Pyo Kim, Pyeung Hwi Choi, Min-Seong Kim, Jiheon Ryu, Sung-hyun Baek, Sung-Min Hong, Sungbae Lee, Jae-Hyung JangAbstractPhotoresponses of the back-side illuminated photoconductive semiconductor switches (PCSSs) in the linear mode are studied. It has been found that the back-side-illuminated PCSS enjoys the better performance than that of the front-side-illuminated one. Photogeneration of electron-hole pairs beneath the contacts under the back-side illumination condition significantly reduces the resistance of the PCSS leading to the higher output pulse amplitude up to 4.6 times. Impact of the beam center position on the output waveform is also investigated for both the illumination cases. The laser beam centered near the cathode yields the slowly-decaying output pulse waveform. On the other hand, the rapidly-decaying waveform is observed with the beam centered near the anode.
       
  • An Empirical Noise Model for III-V Compound Semiconductor Based HBT
    • Abstract: Publication date: Available online 11 October 2019Source: Solid-State ElectronicsAuthor(s): Ao Zhang, Jianjun Gao, Hong WangAbstractThis paper presents a novel approach for the modeling of noise behavior of III-V compound semiconductor based HBT’s over a wide frequency range. The main advantage is that the proposed model is based on two individual un-correlated noise sources, and easy to be incorporated with commercial circuit simulation software. The model is verified by measurements of the four noise parameters of an InP HBT up to 20 GHz and a GaAs HBT up to 26 GHz. The good agreements have been obtained.
       
  • AlInGaN/GaN Double-Channel FinFET with high on-current and negligible
           current collapse
    • Abstract: Publication date: Available online 11 October 2019Source: Solid-State ElectronicsAuthor(s): Jun-Hyeok Lee, Jeong-Gil Kim, Jeong-Min Ju, Woo-Hyun Ahn, Seung-Hyeon Kang, Jung-Hee LeeAbstractIn this work, we fabricated AlInGaN/GaN FinFETs and compare electrical performances with those of AlGaN/GaN FinFETs in different channel structures, such as single and double channel. The double-channel structure is promising to compensate for the degradation of the drain current density caused by the fin structure, as well as the FinFET structure is suitable to control the double-channel structure. The fabricated AlInGaN/GaN double channel FinFETs exhibit considerably higher maximum drain current of 290 mA/mm than those of AlGaN/GaN FinFETs such as 245 mA/mm and 165 mA/mm of double- and single-channel FinFETs, respectively. This is because of the high electron density caused by the strong polarization charge of AlInGaN/GaN heterostructure and double channel structure. Moreover, the double-channel FinFETs effectively suppress the current collapse. In conclusion, the AlInGaN/GaN double-channel fin structure is a very promising candidate for the GaN-based RF power applications.
       
  • Adjustable response of PZT thin film based piezoelectric micro-actuator
           through DC bias pre-polarization
    • Abstract: Publication date: Available online 4 October 2019Source: Solid-State ElectronicsAuthor(s): Dongdong Gong, Feng Qin, Yichen Wang, Yu Chen, Tingting Yang, Xiangyu SunAbstractPZT piezoelectric thin film based technology is promising in the field of micro-actuators. This paper discusses the effects of pre-polarization on the key properties of PZT thin film, and explores the improvement rules of pre-polarization from the material to device level experiments. At the material level, the pre-polarization treatment increases the piezoelectric strain coefficient by 25%, and improves dielectric properties. Meanwhile, in ferroelectric properties the pre-polarization treatment increases the residual polarization by 50% and coercive field by 25%, respectively. At the device level, pre-polarization treatment greatly increases the output characteristics of the devices, such as maximum output displacement increasing by at least 45% and withstand voltage enhancing by 2 V, which is consistent with the material level enhancement. In addition, the optimal pre-polarization process conditions and the long-term stability of the performance improvement are investigated. The pre-polarization treatment has proved to be meaningful for the improvement of the output capability of the piezoelectric thin film actuators.
       
  • Understanding the metal-oxides induced reduction of the contact resistance
           in organic transistors
    • Abstract: Publication date: Available online 4 October 2019Source: Solid-State ElectronicsAuthor(s): Shabnam Donnhäuser, Masahiro Minagawa, Stefan Blawid, Martin ClausAbstractIt is well known that inserting metal oxides on top of electrodes in coplanar bottom-gate bottom-contact organic field-effect transistors (OFETs) improves the OFET performance in terms of increased current density, higher effective mobility and reduced contact resistance. This work elucidates the transistor performance gain in case of oxidized metal electrodes using numerical device simulations and experimental data. The study strongly supports the hypothesis that the impact of oxidization can be explained for these experiments by an improvement of the semiconductor morphology in the vicinity of oxidized electrodes in conjunction with an improved mobility in these regions.
       
  • Low Power-High Speed Performance of 8T Static RAM Cell within GaN TFET,
           FinFET, and GNRFET Technologies -- A Review
    • Abstract: Publication date: Available online 1 October 2019Source: Solid-State ElectronicsAuthor(s): Mounica Patnala, Avinash Yadav, John Williams, Anoop Gopinath, Brian Nutter, Trond Ytterdal, Maher RizkallaAbstractRecent ULSI technology development emphasizes both silicon and graphene-based devices and system performance in terms of their low power and high switching speed. With Moore’s law scaling having reached the limits of physics due to ballistic effects, efforts are moving towards nano scale materials and devices such as TFETs and GNRFETs. Still, recent developments with 7nm lithography-based silicon devices have cited exciting results. The successful development of FinFET devices in integrated systems has been a breakthrough for the semiconductor industry. Research efforts were emphasized for new nanoscale materials such as Graphene, GaN, and Carbon nanotubes, as alternative devices for ULSI integrated system design. This paper provides a cumulative review for these three nanoscale devices: FinFET, TFET, and GNRFET. The study focuses on an 8T SRAM cell as geared towards low power and high-speed features that are suitable for high speed computers, wireless communications, and medical devices. The study covers device theory, models, and simulation. The study has showed evidence that the power consumption for both TFET and GNRFET -based systems features superior low power performance of a ratio 1:0.24 as taken for the Static T Cell for 20 nm scale devices. The practical model of the FinFET is verified and used by industry, while the practical model of both TFET and GNRFET are still in the prototype stage.
       
  • Impedance spectroscopy-based electrical equivalent model of a
           thermoelectric module for the figure of merit (ZT)
    • Abstract: Publication date: Available online 30 September 2019Source: Solid-State ElectronicsAuthor(s): Jaewoo Lee, Jeong-Hun Kim, Jong-Pil Im, Sol-Yee Lim, Eun-Bi Jeon, Seung Eon MoonAbstractImpedance spectroscopy is able to simultaneously extract three key parameters, namely, the Seebeck coefficient, electrical conductivity, and thermal conductivity, leading to determination of the figure of merit (ZT). As the measurement method is simple, it can be used conveniently at room temperature. However, when measuring at high temperatures, there are restrictions on the IS method. Electrical parasitic parameters between the measuring equipment and the temperature chamber may reduce the reliability of the characterization. Since the electrical part connecting the temperature-variable chamber to the measuring equipment can have tens to hundreds of milliohms, it should be considered as lumped parameters in order to evaluate the intrinsic component of the thermoelectric module. In this study, the electrical and thermal characteristics of the Bi2Te3 thermoelectric module were evaluated in the range from room temperature to 150 ℃ using an impedance spectroscopy-based electrical equivalent model (ISEEM). The ISEEM includes an impedance component consisting of the thermoelectric module itself and the parasitic electrical impedance constituting the measuring apparatus, where the electrical impedance of the measuring equipment can be evaluated by the de-embedding method. As a result, it is possible to accurately extract the intrinsic characteristics of the Bi2Te3 thermoelectric module through ISEEM. The intrinsic parameters of a commercial thermoelectric module of 40 mm by 40 mm were obtained within an error rate of 5 % regardless of the peripheral measuring device. Consequently, the module had a ZT maximum value of 0.73 at 22 °C and a performance of 0.49 at 150 °C. These results demonstrate that electrical and thermal characterization can be performed easily, and at the same time, the reliability of the characterization can be improved.
       
  • Input-modulating Adaptive Neuron Circuit Employing Asymmetric
           Floating-gate MOSFET with Two Independent Control Gates
    • Abstract: Publication date: Available online 26 September 2019Source: Solid-State ElectronicsAuthor(s): Taehyung Kim, Kyungchul Park, Taejin Jang, Myung-Hyun Baek, Young Suh Song, Byung-Gook ParkAbstractIn this paper, we present an input-modulating adaptive neuron circuit employing a floating-gate MOSFET (FG-MOSFET) with two asymmetrically shaped control gates. The proposed FG-MOSFET is utilized as key element for implementing neural adaptation in integrate-and-fire (I&F) neuron circuit. To confirm current modulating capability of proposed device, an adjustable-gain current mirror employing the device is simulated as well. Adaptive neuron circuit presented in this paper successfully exhibits spike-triggered adaptation with ratio between maximum and minimum firing rate ranging from 7.97 to 18.4. Compared to conventional researches, adaptive neuron circuit proposed in this paper allows more versatile operation and easier fabrication due to utilization of out FG-MOSFET.
       
  • Theoretical study of ferroelectric-gated nanoelectromechanical diode
           nonvolatile memory cell
    • Abstract: Publication date: Available online 19 September 2019Source: Solid-State ElectronicsAuthor(s): Kihun Choe, Jaesoo Park, Changhwan ShinAbstractBased on the polarization property and negative-capacitance (NC) effect of ferroelectric capacitors, nanoelectromechanical (NEM) diode nonvolatile memory cells (NC-NEM diode NVMs) are proposed for use in random-access memory arrays. It is observed that, by optimizing the structural parameters of the NEM memories, the NC-NEM diode NVMs can achieve more scaled program/erase voltages and better switching delays, when compared to the existing NEM diode memories. Moreover, the NC-NEM diode NVM has a one-directional current path, which is desirable in random-access memory arrays to block the sneak leakage.
       
  • Digital readout optimization of the random resistive states in magnetic
           tunnel junction
    • Abstract: Publication date: Available online 19 September 2019Source: Solid-State ElectronicsAuthor(s): Thomas Egler, Hans Dittmann, Artur UseinovAbstractTrue random number generators (TRNGs) provide a wide area of applications and can be fabricated on the basis of magnetic tunnel junctions (MTJs). This work represents the modeling of TRNG readout optimization, where the induced digital random bit is detected within only a single computational period. The period contains two sub-cycles: write and joined read & reset cycles. The system has a valuable potential to become stochastically independent after calibrating at the desired working point against the factors, which cause to the signal deviations: temperature-induced, material degradation or other problems.
       
  • Improved dielectric properties of BeO thin films grown by plasma enhanced
           atomic layer deposition
    • Abstract: Publication date: Available online 18 September 2019Source: Solid-State ElectronicsAuthor(s): Yoonseo Jang, Seung Min Lee, Do Hwan Jung, Jung Hwan Yum, Eric S. Larsen, Christopher W. Bielawski, Jungwoo OhAbstractBeryllium oxide (BeO) thin films were grown on a p-type Si substrate by plasma enhanced atomic layer deposition (PEALD) using diethylberyllium as a precursor and O2 plasma. The PEALD BeO exhibited self-saturation and linear growth rates. The dielectric properties of PEALD were compared with those of thermal atomic layer deposition (ThALD). X-ray photoelectron spectroscopy was performed to determine the bandgap energy of PEALD BeO (8.0 eV) and ThALD BeO (7.9 eV). Capacitance–voltage curves revealed that PEALD BeO had low hysteresis and frequency dispersion compared to ThALD BeO. In addition, PEALD showed a dielectric constant of 7.15 (at 1 MHz) and low leakage current (7.25×10-9 A/cm2 at -1 MV/cm). These results indicate that the highly activated radicals from oxygen plasma prompt the chemical reaction at the substrate, thus reducing nucleation delay and interface trap density.
       
  • Tuning of ionization potential in amorphous Cd–In–O thin films
    • Abstract: Publication date: Available online 18 September 2019Source: Solid-State ElectronicsAuthor(s): Minseok Kim, Hiroshi YanagiAbstractIonization potential is an important parameter for the design of semiconductor devices. Since amorphous semiconductors do not have long-range ordering and lattice constants, it is not necessary to consider lattice defects at interfaces. If the ionization potential can be controlled with such an amorphous semiconductor, the flexibility of the semiconductor device designs will expanded. This enables the fabrication of semiconductor devices such as light-emitting diodes, laser diodes, and solar cells. In this study, we fabricated n-type amorphous Cd–In–O films (a-CIO) on silica glass substrates using radio frequency magnetron sputtering at room temperature. The band gaps of these films increased from 2.6 to 3.0 eV with a decrease in the Cd concentration (Cd/(Cd + In)). Ip (energy difference between the vacuum level (Evac) and the valence band maximum) and electron affinity (the difference between the Evac and the conduction band minimum) were measured using a combination of ultraviolet photoelectron spectroscopy and optical spectroscopy techniques. Ips were controlled by the Cd concentration in films without a shift in electron affinities. The results suggest that the a-CIO films are suitable for the design of semiconductor devices such as solar cells, where tuning the Ip is important.
       
  • Indirect Avalanche Event Detection of Single Photon Avalanche Diode
           Implemented in CMOS FDSOI Technology
    • Abstract: Publication date: Available online 14 September 2019Source: Solid-State ElectronicsAuthor(s): Tulio Chaves de Albuquerque, Dylan Issartel, Raphaël Clerc, Patrick Pittet, Rémy Cellier, Dominique Golanski, Sébastien Jouan, Andreia Cathelin, Francis CalmonAbstractIn this letter, a novel indirect avalanche event detection is proposed and demonstrated for Single Photon Avalanche Diodes (SPADs) implemented in CMOS 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology. This approach is based on the capacitive coupling between the P-well, i.e. SPAD anode, and the transistor channel, separated by the ultra-thin buried oxide. The associated body-biasing effect is used to dynamically modulate the output of a simple voltage divider synchronously with the SPAD activity. A test-chip has been designed, fabricated and characterized to validate the proposed approach. This novel architecture opens the way for innovative SPAD processing circuitry implemented in 3D native CMOS FDSOI.
       
  • Design Guideline of Tunnel Field-Effect Transistors (TFETs) Considering
           Negative Differential Transconductance (NDT)
    • Abstract: Publication date: Available online 11 September 2019Source: Solid-State ElectronicsAuthor(s): Jang Woo Lee, Woo Young ChoiAbstractA gate-normal tunnel field-effect transistor (TFET) showing negative differential transconductance (NDT) and its design guideline are proposed. The introduction of the source depletion to the gate-normal TFETs leads to negative differential transconductance. It is also confirmed that the NDT of the proposed gate-normal TFET is successfully enhanced by modulating gate-induced source depletion effects.
       
  • Analytic Model of Spalling Technique for Thickness-Controlled Separation
           of Single-Crystalline Semiconductor Layers
    • Abstract: Publication date: Available online 10 September 2019Source: Solid-State ElectronicsAuthor(s): Honghwi Park, Changhee Lim, Chang-Ju Lee, Muhan Choi, Sunghwan Jung, Hongsik ParkAbstractThickness-controlled separation of a thin layer of single-crystalline semiconductors from its bulk substrate is being developed for co-integration of compound semiconductors with silicon-based integrated-circuit (IC) chips and fabrication of high-performance flexible devices. Recently, a controlled spalling technique that can mechanically separate single-crystalline semiconductor layers has been actively demonstrated because of the process simplicity and the less limitation in materials. Here, we developed an analytic model that can precisely estimate the spalling depth. In this model, the spalling depth was calculated from the thermodynamic equilibrium condition in which total strain energy accumlated in a separated layer is balanced with the crystal binding energy. We empirically investigated the dependence of the spalling depth on the stressor layer thickness and stress, and we compared the empirical results with the suggested analytic model. We also verified that the crack initiation angle of the spalling process is determined by the binding energy contrast in the main crystal orientations in the semiconductor.
       
  • Improved Organic Solar Cell by Incorporating Silver Nanoparticles Embedded
           Polyaniline as Buffer Layer
    • Abstract: Publication date: Available online 10 September 2019Source: Solid-State ElectronicsAuthor(s): S.A. Moiz, A.N.M. Ahmadi, Kh.S. KarimovAbstractThe role of silver nanoparticles (AgNP) in polyaniline (PANI) as buffer layer for ITO/AgNP-PANI/PANI/Al solar cell was investigated. It is observed that AgNP-PANI buffer layer significantly improves the electrical parameters such as diode-ideality factor, series-resistance, energy-barrier height, and shunt-resistance as a growing function of AgNP concentration. On-the-other hand oppose to the dark current-voltage response, 0.5% concentration of AgNP in buffer layer shows the most optimum photovoltaic response and cause to increase the power conversion efficiency (PCE) nearly 5 times compared to same solar cell without buffer layer. Such improvements in electrical parameters can be interpreted as the reduction in interfacial trap states as well as enhancement in interfacial dipole-moment by AgNP embedded buffer layer for given photovoltaic device. While, the observed optimum photovoltaic behavior at 0.5% AgNP concentration is may be due to the trade-offs between gains and losses for optical absorption enhancement, self-absorption heating and interface recombination losses respectively. It is also observed that the AgNP embedded PANI buffer layer approach is an effective solution to lower the photovoltaic degradation and hence improves the stability of the photovoltaic devices.
       
  • A Physical and Versatile Aging Compact Model for Hot Carrier Degradation
           in SiGe HBTs under Dynamic Operating Conditions
    • Abstract: Publication date: Available online 6 September 2019Source: Solid-State ElectronicsAuthor(s): C. Mukherjee, F. Marc, M. Couret, G.G. Fischer, M. Jaoul, D. Céli, K. Aufinger, T. Zimmer, C. ManeuxAbstractThis paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick’s law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.
       
  • Capacitance-Voltage Technique for Characterization of Lateral Trap
           Locations along the Channel in Low-Temperature Poly-Silicon Thin Film
           Transistors
    • Abstract: Publication date: Available online 5 September 2019Source: Solid-State ElectronicsAuthor(s): Han Bin Yoo, Junyeap Kim, Jintae Yu, Hyo-Jin Kim, Sung-Jin Choi, Dae Hwan Kim, Dong Myong KimAbstractThis study introduces a characterization technique for trap locations (Xt) with considerable trap density along the channel in field effect transistors (FETs). The technique is based on the experimental gate-to-source or gate-to-drain capacitance-voltage (CGS-VGS or CGD-VGD) characteristics of FETs. As the gate bias (VG) increases, the effective channel length (Leff) extends by the increased conductivity of the channel from the source or the drain. Due to trapped charges at the trap sites with a high density of traps along the channel, abrupt change in the C-V characteristics is observed. For the transition gate bias (VG,t) with abrupt change in the C-V characteristics, the dominant trap location (Xt) can be converted through the channel conduction factor (α(VG) to be the effective channel length Leff(VG)=α(VG)∙Lch). We expect that the proposed C-V technique to be useful in non-destructive electrical characterization of lateral trap locations (interface states, bulk traps, and/or grain boundary traps caused by the bias stress and/or fabrication process) along the channel in FETs. We successfully applied the proposed technique to the p-channel poly-Si thin-film transistors (TFTs) for characterization of the grain boundary locations along the channel. As an example for the proposed technique, we applied the technique to a p-channel poly-Si TFT and obtained a dominant trap at XGB1=3.13 [μm] from the source and another at XGB2=3.70 [μm] from the drain.
       
  • Effects of Recess Depths on Performance of AlGaN/GaN Power MIS-HEMTs on
           the Si Substrates and Threshold Voltage Model of Different Recess Depths
           for the Using HfO2 Gate Insulator
    • Abstract: Publication date: Available online 3 September 2019Source: Solid-State ElectronicsAuthor(s): Yaopeng Zhao, Chong Wang, Xuefeng Zheng, Xiaohua Ma, Yunlong He, Kai Liu, Ang Li, Yue Peng, Chunfu Zhang, Yue HaoAbstractThree types of E-mode AlGaN/GaN MIS-HEMTs with different barrier depths and conventional HEMT were fabricated on the Si substrates. HfO2 gate insulator with a thickness of 30 nm was grown by plasma enhanced atomic layer deposited (PEALD). Characteristics of the four devices with different recess depths are analyzed. The MIS-HEMT with barrier layer thickness of 3 nm features good comprehensive performance. The threshold voltage (Vth) is 1.8V, the drain current density is 480 mA/mm and the figure of merit (FOM) is 363 MW/cm2. When the barrier thickness is 0 nm, the Vth is up to 3.7 V. A calculation model of threshold voltage for recessed MIS-HEMTs is proposed. When the barrier layer thickness is 6 nm, the calculated value of Vth was 0.3 V which is in good match with the experimental value of 0.4V. The proposed model provides guidelines for the AlGaN/GaN MIS-HEMTs designs.
       
  • Modelling and analysis of gate leakage current and its wafer level
           variability in advanced FD-SOI MOSFETs
    • Abstract: Publication date: Available online 26 August 2019Source: Solid-State ElectronicsAuthor(s): Krishna Pradeep, Thierry Poiroux, Patrick Scheer, André Juge, Gérard GhibaudoAbstractThe gate leakage current in advanced FD-SOI devices are investigated using systematic measurements on multiple geometry devices from 14 nm node. A simple model with an equivalent trapezoidal barrier based on WKB approximation is introduced and verified on the different measurements. The wafer level variability of the leakage current is explored using statistical modelling and the simple model for gate leakage current. The pure physical sources of variation are identified and the scaling trends of the standard deviations of the sources are analysed. The methodology and models have been validated also on 28 nm node devices.
       
  • An improved empirical nonlinear model for InP-based HEMTs
    • Abstract: Publication date: Available online 11 May 2019Source: Solid-State ElectronicsAuthor(s): Zhong Yinghui, Wang Wenbin, Yang Jie, Sun Shuxiang, Chang Mingming, Duan Zhiyong, Jin Zhi, Ding PengAbstractIn this paper, an improved nonlinear model is proposed for self-developed on wafer InAlAs/InGaAs InP-based high election mobility transistors (HEMTs) over a wide operating bias range based on EEHEMT model, including non-linear channel current model and gate charge model. Actually, the knee voltage (Vsat) increases linearly with gate-source voltage (VGS) and finally approaches to saturation with the finite Si-doping density. Thereby, a hyperbolic tangent function (tanh) is used to describe the changing relationship, rather than idealized into a constant value with gate bias. Besides, a piecewise function is constructed to depict the variation of gate capacitance with bias voltage. Specifically, a third-order formula is utilized to accurately and simply characterize the downswing trend of gate capacitance with channel carrier density, which behaves as an effective extension of gate charge model at relatively large gate-source bias. Therefore, the improved model has shown a better accuracy between simulated and measured data with smaller error factor in output current, S-parameters, stability factor and frequency characteristics. The accurate and suitable empirical large-signal model for InP-based HEMTs would be of great significance on design of high-frequency nonlinear circuits.
       
 
 
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