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  Subjects -> ELECTRONICS (Total: 181 journals)
Showing 1 - 200 of 277 Journals sorted alphabetically
Acta Electronica Malaysia     Open Access  
Advances in Electrical and Electronic Engineering     Open Access   (Followers: 6)
Advances in Electronics     Open Access   (Followers: 79)
Advances in Magnetic and Optical Resonance     Full-text available via subscription   (Followers: 8)
Advances in Power Electronics     Open Access   (Followers: 33)
Advancing Microelectronics     Hybrid Journal  
Aerospace and Electronic Systems, IEEE Transactions on     Hybrid Journal   (Followers: 318)
American Journal of Electrical and Electronic Engineering     Open Access   (Followers: 24)
Annals of Telecommunications     Hybrid Journal   (Followers: 9)
APSIPA Transactions on Signal and Information Processing     Open Access   (Followers: 9)
Archives of Electrical Engineering     Open Access   (Followers: 13)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Bell Labs Technical Journal     Hybrid Journal   (Followers: 28)
Bioelectronics in Medicine     Hybrid Journal  
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 19)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 36)
Biomedical Instrumentation & Technology     Hybrid Journal   (Followers: 6)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 12)
BULLETIN of National Technical University of Ukraine. Series RADIOTECHNIQUE. RADIOAPPARATUS BUILDING     Open Access   (Followers: 1)
Bulletin of the Polish Academy of Sciences : Technical Sciences     Open Access   (Followers: 1)
Canadian Journal of Remote Sensing     Full-text available via subscription   (Followers: 47)
China Communications     Full-text available via subscription   (Followers: 8)
Chinese Journal of Electronics     Hybrid Journal  
Circuits and Systems     Open Access   (Followers: 15)
Consumer Electronics Times     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 270)
Edu Elektrika Journal     Open Access   (Followers: 1)
Electrica     Open Access  
Electronic Design     Partially Free   (Followers: 106)
Electronic Markets     Hybrid Journal   (Followers: 7)
Electronic Materials Letters     Hybrid Journal   (Followers: 4)
Electronics     Open Access   (Followers: 86)
Electronics and Communications in Japan     Hybrid Journal   (Followers: 10)
Electronics For You     Partially Free   (Followers: 93)
Electronics Letters     Hybrid Journal   (Followers: 26)
Elkha : Jurnal Teknik Elektro     Open Access  
Embedded Systems Letters, IEEE     Hybrid Journal   (Followers: 51)
Energy Harvesting and Systems     Hybrid Journal   (Followers: 4)
Energy Storage Materials     Full-text available via subscription   (Followers: 3)
EPJ Quantum Technology     Open Access  
EURASIP Journal on Embedded Systems     Open Access   (Followers: 11)
Facta Universitatis, Series : Electronics and Energetics     Open Access  
Foundations and Trends® in Communications and Information Theory     Full-text available via subscription   (Followers: 6)
Foundations and Trends® in Signal Processing     Full-text available via subscription   (Followers: 10)
Frequenz     Hybrid Journal   (Followers: 1)
Frontiers of Optoelectronics     Hybrid Journal   (Followers: 1)
Geoscience and Remote Sensing, IEEE Transactions on     Hybrid Journal   (Followers: 197)
Haptics, IEEE Transactions on     Hybrid Journal   (Followers: 4)
IACR Transactions on Symmetric Cryptology     Open Access  
IEEE Antennas and Propagation Magazine     Hybrid Journal   (Followers: 97)
IEEE Antennas and Wireless Propagation Letters     Hybrid Journal   (Followers: 77)
IEEE Journal of Emerging and Selected Topics in Power Electronics     Hybrid Journal   (Followers: 46)
IEEE Journal of the Electron Devices Society     Open Access   (Followers: 9)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits     Hybrid Journal   (Followers: 1)
IEEE Power Electronics Magazine     Full-text available via subscription   (Followers: 67)
IEEE Transactions on Antennas and Propagation     Full-text available via subscription   (Followers: 70)
IEEE Transactions on Automatic Control     Hybrid Journal   (Followers: 56)
IEEE Transactions on Circuits and Systems for Video Technology     Hybrid Journal   (Followers: 20)
IEEE Transactions on Consumer Electronics     Hybrid Journal   (Followers: 40)
IEEE Transactions on Electron Devices     Hybrid Journal   (Followers: 19)
IEEE Transactions on Information Theory     Hybrid Journal   (Followers: 26)
IEEE Transactions on Power Electronics     Hybrid Journal   (Followers: 70)
IEEE Transactions on Signal and Information Processing over Networks     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Electronics     Full-text available via subscription   (Followers: 12)
IEICE - Transactions on Information and Systems     Full-text available via subscription   (Followers: 5)
IET Cyber-Physical Systems : Theory & Applications     Open Access   (Followers: 1)
IET Microwaves, Antennas & Propagation     Hybrid Journal   (Followers: 35)
IET Nanodielectrics     Open Access  
IET Power Electronics     Hybrid Journal   (Followers: 46)
IET Smart Grid     Open Access  
IET Wireless Sensor Systems     Hybrid Journal   (Followers: 18)
IETE Journal of Education     Open Access   (Followers: 4)
IETE Journal of Research     Open Access   (Followers: 11)
IETE Technical Review     Open Access   (Followers: 13)
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)     Open Access   (Followers: 3)
Industrial Electronics, IEEE Transactions on     Hybrid Journal   (Followers: 58)
Industry Applications, IEEE Transactions on     Hybrid Journal   (Followers: 25)
Informatik-Spektrum     Hybrid Journal   (Followers: 2)
Instabilities in Silicon Devices     Full-text available via subscription   (Followers: 1)
Intelligent Transportation Systems Magazine, IEEE     Full-text available via subscription   (Followers: 13)
International Journal of Advanced Research in Computer Science and Electronics Engineering     Open Access   (Followers: 18)
International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems     Open Access   (Followers: 10)
International Journal of Antennas and Propagation     Open Access   (Followers: 11)
International Journal of Applied Electronics in Physics & Robotics     Open Access   (Followers: 4)
International Journal of Computational Vision and Robotics     Hybrid Journal   (Followers: 6)
International Journal of Control     Hybrid Journal   (Followers: 11)
International Journal of Electronics     Hybrid Journal   (Followers: 7)
International Journal of Electronics and Telecommunications     Open Access   (Followers: 13)
International Journal of Granular Computing, Rough Sets and Intelligent Systems     Hybrid Journal   (Followers: 2)
International Journal of High Speed Electronics and Systems     Hybrid Journal  
International Journal of Hybrid Intelligence     Hybrid Journal  
International Journal of Image, Graphics and Signal Processing     Open Access   (Followers: 14)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 8)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields     Hybrid Journal   (Followers: 4)
International Journal of Power Electronics     Hybrid Journal   (Followers: 24)
International Journal of Review in Electronics & Communication Engineering     Open Access   (Followers: 4)
International Journal of Sensors, Wireless Communications and Control     Hybrid Journal   (Followers: 10)
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 4)
International Journal of Wireless and Microwave Technologies     Open Access   (Followers: 6)
International Transaction of Electrical and Computer Engineers System     Open Access   (Followers: 2)
JAREE (Journal on Advanced Research in Electrical Engineering)     Open Access  
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 3)
Journal of Advanced Dielectrics     Open Access   (Followers: 1)
Journal of Artificial Intelligence     Open Access   (Followers: 10)
Journal of Circuits, Systems, and Computers     Hybrid Journal   (Followers: 4)
Journal of Computational Intelligence and Electronic Systems     Full-text available via subscription   (Followers: 1)
Journal of Electrical and Electronics Engineering Research     Open Access   (Followers: 25)
Journal of Electrical Bioimpedance     Open Access  
Journal of Electrical Bioimpedance     Open Access   (Followers: 2)
Journal of Electrical Engineering & Electronic Technology     Hybrid Journal   (Followers: 7)
Journal of Electrical, Electronics and Informatics     Open Access  
Journal of Electromagnetic Analysis and Applications     Open Access   (Followers: 7)
Journal of Electromagnetic Waves and Applications     Hybrid Journal   (Followers: 8)
Journal of Electronic Design Technology     Full-text available via subscription   (Followers: 6)
Journal of Electronics (China)     Hybrid Journal   (Followers: 4)
Journal of Energy Storage     Full-text available via subscription   (Followers: 4)
Journal of Engineered Fibers and Fabrics     Open Access   (Followers: 2)
Journal of Field Robotics     Hybrid Journal   (Followers: 3)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 170)
Journal of Information and Telecommunication     Open Access   (Followers: 1)
Journal of Intelligent Procedures in Electrical Technology     Open Access   (Followers: 3)
Journal of Low Power Electronics     Full-text available via subscription   (Followers: 7)
Journal of Low Power Electronics and Applications     Open Access   (Followers: 9)
Journal of Microelectronics and Electronic Packaging     Hybrid Journal  
Journal of Microwave Power and Electromagnetic Energy     Hybrid Journal  
Journal of Microwaves, Optoelectronics and Electromagnetic Applications     Open Access   (Followers: 10)
Journal of Nuclear Cardiology     Hybrid Journal  
Journal of Optoelectronics Engineering     Open Access   (Followers: 4)
Journal of Physics B: Atomic, Molecular and Optical Physics     Hybrid Journal   (Followers: 29)
Journal of Power Electronics & Power Systems     Full-text available via subscription   (Followers: 11)
Journal of Semiconductors     Full-text available via subscription   (Followers: 5)
Journal of Sensors     Open Access   (Followers: 26)
Journal of Signal and Information Processing     Open Access   (Followers: 9)
Jurnal ELTIKOM : Jurnal Teknik Elektro, Teknologi Informasi dan Komputer     Open Access  
Jurnal Rekayasa Elektrika     Open Access  
Jurnal Teknik Elektro     Open Access  
Jurnal Teknologi Elektro     Open Access  
Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control     Open Access  
Learning Technologies, IEEE Transactions on     Hybrid Journal   (Followers: 12)
Magnetics Letters, IEEE     Hybrid Journal   (Followers: 7)
Majalah Ilmiah Teknologi Elektro : Journal of Electrical Technology     Open Access   (Followers: 2)
Metrology and Measurement Systems     Open Access   (Followers: 5)
Microelectronics and Solid State Electronics     Open Access   (Followers: 19)
Nanotechnology Magazine, IEEE     Full-text available via subscription   (Followers: 33)
Nanotechnology, Science and Applications     Open Access   (Followers: 6)
Nature Electronics     Hybrid Journal  
Networks: an International Journal     Hybrid Journal   (Followers: 5)
Open Electrical & Electronic Engineering Journal     Open Access  
Open Journal of Antennas and Propagation     Open Access   (Followers: 8)
Optical Communications and Networking, IEEE/OSA Journal of     Full-text available via subscription   (Followers: 15)
Paladyn. Journal of Behavioral Robotics     Open Access   (Followers: 1)
Power Electronics and Drives     Open Access   (Followers: 1)
Problemy Peredachi Informatsii     Full-text available via subscription  
Progress in Quantum Electronics     Full-text available via subscription   (Followers: 7)
Pulse     Full-text available via subscription   (Followers: 5)
Radiophysics and Quantum Electronics     Hybrid Journal   (Followers: 2)
Recent Advances in Communications and Networking Technology     Hybrid Journal   (Followers: 3)
Recent Advances in Electrical & Electronic Engineering     Hybrid Journal   (Followers: 9)
Research & Reviews : Journal of Embedded System & Applications     Full-text available via subscription   (Followers: 5)
Revue Méditerranéenne des Télécommunications     Open Access  
Security and Communication Networks     Hybrid Journal   (Followers: 2)
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 54)
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 4)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 75)
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 13)
Solid-State Electronics     Hybrid Journal   (Followers: 9)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Synthesis Lectures on Power Electronics     Full-text available via subscription   (Followers: 3)
Technical Report Electronics and Computer Engineering     Open Access  
TELE     Open Access  
Telematique     Open Access  
TELKOMNIKA (Telecommunication, Computing, Electronics and Control)     Open Access   (Followers: 9)
Universal Journal of Electrical and Electronic Engineering     Open Access   (Followers: 6)
Visión Electrónica : algo más que un estado sólido     Open Access   (Followers: 1)
Wireless and Mobile Technologies     Open Access   (Followers: 6)
Wireless Power Transfer     Full-text available via subscription   (Followers: 4)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 11)
Електротехніка і Електромеханіка     Open Access  

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Similar Journals
Journal Cover
Solid-State Electronics
Journal Prestige (SJR): 0.492
Citation Impact (citeScore): 2
Number of Followers: 9  
 
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 0038-1101
Published by Elsevier Homepage  [3184 journals]
  • Electrical Tunability of Partially Depleted Silicon on Insulator (PD-SOI)
           Neuron
    • Abstract: Publication date: Available online 17 June 2019Source: Solid-State ElectronicsAuthor(s): Sangya Dutta, Tanmay Chavan, Nihar R. Mohapatra, Udayan Ganguly The hardware realization of spiking neural network (SNN) requires a compact and energy efficient electronic analog to the biological neuron. A knob to tune the response of the as-fabricated neuron allows the network to perform various functioning without altering the hardware. Earlier, our group has experimentally demonstrated an LIF (leaky integrate & fire) neuron on a highly matured 32 nm SOI CMOS technology. In this work, we have experimentally demonstrated electrical tunability of the same through its intrinsic charge dynamics based on impact ionization (II) enabled floating body effect. First, a tunable input threshold (Vth) is achieved by changing the drain bias. Second, above threshold, a firing frequency (f) to input (V) sensitivity (df/dV) tuning is successfully demonstrated by controlling the SOI-MOSFET’s current threshold. We show that both the independent control of sensitivity and threshold is fundamentally enabled by the non-linearity of the impact ionization based carrier dynamics. The SOI neuron provides equivalent electrical tunability to Resistor-Capacitor (RC) based LIF neurons without degrading its original area and power advantages for clock-less, asynchronous SNNs. Further, we show that the neuronal behavior (threshold and sensitivity) is a key determinant of network performance, specifically the learning accuracy. Such flexibility based on post-fabrication electrical tuning will be an attractive enabler for the SNN hardware.
       
  • Temperature Dependence Improvement of Polycrystalline-Silicon Tunnel
           Field-Effect Thin-Film Transistor
    • Abstract: Publication date: Available online 10 June 2019Source: Solid-State ElectronicsAuthor(s): William Cheng-Yu Ma, Jia-Yi Wang, Li-Wei Yu, Hsiao-Chun Wang, Yan-Jia Huang Trap-assisted tunneling (TAT) mechanism dominates the subthreshold leakage current and ambipolar transport behavior of tunnel field-effect transistor (TFET) with polycrystalline-silicon (poly-Si) channel. The unwanted ambipolar transport behavior of poly-Si TFET can be suppressed by the employment of gate-to-drain underlap structure to increase the tunneling distance near the drain side when the TFET is operated at the negative gate voltage. The gate-to-drain underlap length of TFET would also exhibit series resistance effect and strong temperature effect on the on-state current (ION). The strong temperature dependent series resistance effect and bandgap narrowing effect cause the poly-Si TFET to exhibit temperature instability of the on-state current. In order to improve the temperature instability of the on-state current, the ammonia plasma treatment has been performed to passivate the defects and reduce the trap state density of poly-Si film. The trap state density reduction of poly-Si can improve the field-effect mobility of transport carrier and reduce the series resistance effect, resulting in the reduction of the temperature dependence of ION. Consequently, the improved temperature dependent ION of poly-Si TFET can be obtained, and it is useful for the development of poly-Si thin-film transistor and its applications in the high resolution display industry and three-dimensional integrated-circuit.
       
  • Investigation of the electromechanical stability of low temperature
           
    • Abstract: Publication date: Available online 30 May 2019Source: Solid-State ElectronicsAuthor(s): Chang Bum Park The electromechanical stability of low temperature polycrystalline silicon thin-film transistors embedded on plastic film was investigated as a function of type of stress and cyclic bending. The results show these devices to have reliable electromechanical integrity against mechanical strain at a bending radius of a few millimeters under compressive stress on the inner bending surface. By contrast, after being subjected to tensile stress on the outward bending surface, the devices show significant electrical failure under the induced strain. The onset of strain fracture also closely corresponds to the electrical failure of the device when exposed to tensile stress. The deformation kinetics caused by stress accumulation were investigated in multiple films with regard to a flexible backplane; these results reveal that mechanical integrity in reliable device design could be effectively provided by controlling the types of stress and could be put into practical use in flexible electronics applications.
       
  • The analysis and characteristics of 4H-SiC floating junction JBS diodes
           with different structures underneath the termination region
    • Abstract: Publication date: Available online 23 May 2019Source: Solid-State ElectronicsAuthor(s): H. Yuan, X. Tang, Q. Song, Y. He, X. He, Y. Zhang, Y. Zhang In this paper, a comparison of different floating junction structure underneath the termination region FJt for 4H-SiC FJ_JBS is performed by simulations and experiments. The simulated results indicate that the optimized dose of FJt is different when the different FJt structures are chosen, which is resulting from different work mechanism. The experimental results show that the breakdown voltage of FJ_JBS with discontinuous floating junction structure underneath the termination region is 2.9 kV. For comparison, the FJ_JBS with continuous floating junction structure without fixed outer boundary underneath the termination only achieves a breakdown voltage of 2.05 kV, which validates the simulation results.
       
  • An improved empirical nonlinear model for InP-based HEMTs
    • Abstract: Publication date: Available online 11 May 2019Source: Solid-State ElectronicsAuthor(s): Zhong Yinghui, Wang Wenbin, Yang Jie, Sun Shuxiang, Chang Mingming, Duan Zhiyong, Jin Zhi, Ding Peng In this paper, an improved nonlinear model is proposed for self-developed on wafer InAlAs/InGaAs InP-based high election mobility transistors (HEMTs) over a wide operating bias range based on EEHEMT model, including non-linear channel current model and gate charge model. Actually, the knee voltage (Vsat) increases linearly with gate-source voltage (VGS) and finally approaches to saturation with the finite Si-doping density. Thereby, a hyperbolic tangent function (tanh) is used to describe the changing relationship, rather than idealized into a constant value with gate bias. Besides, a piecewise function is constructed to depict the variation of gate capacitance with bias voltage. Specifically, a third-order formula is utilized to accurately and simply characterize the downswing trend of gate capacitance with channel carrier density, which behaves as an effective extension of gate charge model at relatively large gate-source bias. Therefore, the improved model has shown a better accuracy between simulated and measured data with smaller error factor in output current, S-parameters, stability factor and frequency characteristics. The accurate and suitable empirical large-signal model for InP-based HEMTs would be of great significance on design of high-frequency nonlinear circuits.
       
  • Explicit Approximation of the Surface Potential Equation of a Dynamically
           Depleted Silicon-On-Insulator MOSFET for Performance and Reliability
           Simulations
    • Abstract: Publication date: Available online 10 May 2019Source: Solid-State ElectronicsAuthor(s): Ian P. Livingston, Ivan S. Esqueda, Hugh J. Barnaby In this work we are first to report an explicit solution to the SPE for a dynamically-depleted DD-SOI MOSFET that captures the effects of both oxide-trapped charge and interface traps on the device characteristics. Derivations for both the implicit (iterative) and explicit (non-iterative) solutions to the surface potential equation are presented for the DD-SOI MOSFET device. The explicit or closed form approximation was solved using non-iterative techniques that have been developed for the PSP MOSFET compact modeling framework [6], [7], [8]. The non-iterative model can be implemented as a Verilog-A sub-circuit module using a VCVS in series with the gate of the SOI MOSFET that is compatible with standard circuit level simulation tools. We demonstrate the accuracy of the implicit and explicit surface potential-based derivations using two dimensional TCAD simulations as a comparison. Finally, we present the symmetric linearization method for computing the drain current of the DD-SOI MOSFET.
       
  • 2D and 3D TCAD Simulation of III-V Channel FETs at the End of Scaling
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): P. Aguirre, M. Rau, A. Schenk Quantum drift diffusion corrections, models for the one- and two-dimensional density of states, a non-local model for source-to-drain tunneling, and a simple ballistic mobility model are jointly used to simulate IDVGS-characteristics of scaled III-V-channel nFETs. The sub-threshold swing of double-gate ultra-thin-body and gate-all-around nanowire geometries are extracted for different gate lengths, and the semi-classical results are compared with those from the quantum transport simulator QTx. The low-dimensional density of states in combination with the ballistic mobility yields an overall good agreement with the QTx transfer curves after the onset of inversion and decreases ION by two orders of magnitude in comparison to the simulation with a large diffusive mobility. It is shown that source-to-drain tunneling sets a limit to scaling at a gate length of about 10 nm due to the degradation of the sub-threshold swing. Simulating this effect with a low-dimensional density of states reveals inconsistencies. They are attributed to the tunneling model, which had been derived for a three-dimensional electron gas.
       
  • Investigation of Thin Gate-Stack Z2-FET Devices as
           Capacitor-less Memory Cells
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): S. Navarro, C. Marquez, K.H. Lee, C. Navarro, M. Parihar, H. Park, P. Galy, M. Bawedin, Y.T. Kim, S. Cristoloveanu, F. Gamiz Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FDSOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z2-FET cells are observed.
       
  • Impact of contact and channel resistance on the frequency-dependent
           capacitance and conductance of pseudo-MOSFET
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): S. Sato, G. Ghibaudo, L. Benea, I. Ionica, Y. Omura, S. Cristoloveanu This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified.
       
  • Characterization of the Interface-Driven 1st Reset Operation in HfO2-based
           1T1R RRAM Devices
    • Abstract: Publication date: Available online 26 March 2019Source: Solid-State ElectronicsAuthor(s): Eduardo Pérez, Mamathamba Kalishettyhalli Mahadevaiah, Cristian Zambelli, Piero Olivo, Christian Wenger In this work, the increase on the filament conductivity during the 1st Reset operation, by using the incremental step pulse with verify algorithm, is investigated in HfO2-based 1T1R RRAM devices. A new approach is proposed in order to explain the increase of conductivity by highlighting the crucial roles played by both metal-oxide interfaces. The top metal-oxide interface (HfO2-x/TixOy) plays a role in the forming operation by creating a strong gradient of oxygen vacancies in the hafnium oxide layer. The bottom metal-oxide interface (TixOyNz/HfO2-x) also creates oxygen vacancies, which strengthen the conductive filament tip near to this interface at the beginning of the 1st Reset, leading to the reported conductivity increase. After the 1st Reset operation the conductive filament stabilizes at the bottom interface suppressing this behavior in the subsequent reset operations. By modifying the programming parameters and the temperature, it was confirmed a constant current increase of about 9 μA during the 1st Reset regardless the operation conditions imposed.
       
  • Effects of Mole Fraction Variations and Scaling on Total Variability in
           InGaAs MOSFETs
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Nicolò Zagni, Francesco Maria Puglisi, Paolo Pavan, Giovanni Verzellesi Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate- Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, VT,lin, VT,sat, on-current, ION, leakage current, IOFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced VT variability, it increases the total VT,lin variability as well as that for ION and IOFF.
       
  • Effect of Degree of Strain Relaxation on Polarization Charges of
           GaN/InGaN/GaN Hexagonal and Triangular Nanowire Solar Cells
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): S.R. Routray, T.R. Lenka The innovative contribution of this paper is to derive polarization charges in hexagonal and triangular GaN/InGaN/GaN core/shell/shell nanowire solar cells considering effect of degree of strain relaxation (R) and appropriate stiffness coefficients. The crystal orientation angle, φ and non-linear effect of spontaneous polarization are tailored with strain calculations for a better precision of polarization charges in nanowire type devices. The article also formulated the effect of polarization charges while InGaN layers are grown above or below GaN layer in both types of nanowires depending on the lattice expansion or compression. The model accounts an innovative concept of polarization charges distribution with respect to growth of crystal orientation and strain relaxation. It is observed that nanowire solar cell with triangular geometry could be good enough for efficient generation of power as compared to hexagonal nanowire solar cell. This concept of one triangular nanowire solar cell exhibits an efficiency of 3.18% with 90.34% fill factor under 1 Sun AM1.5 illumination with 20% ‘In’ composition.
       
  • The 25th Korean Conference on Semiconductors
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Jung-Hee Lee, Tae Joo Park, Kyung Rok Kim, Yongwoo Kwon
       
  • Near-field scanning microwave microscope platform based on a coaxial
           cavity resonator for the characterization of semiconductor structures
    • Abstract: Publication date: Available online 23 March 2019Source: Solid-State ElectronicsAuthor(s): Bendehiba Abadlia Bagdad, Carmen Lozano, Francisco Gamiz A Near-Field Scanning Microwave Microscope (NSMM) for the characterization of semiconductor structures has been designed, simulated and fabricated. The present NSMM system is based on a home-made coaxial-cavity resonator which is fed by a Keysight N5242A PNA-X Network Analyzer. The inner conductor of the coaxial resonator is connected to a sharpened tungsten tip, which was fabricated by an electrochemical process. The reflection and transmission coefficients S11, S21, the resonance frequency fr and the quality factor Q of the resonant cavity are measured as the semiconductor structure is scanned by the sharpened probe tip while the sample-tip distance is kept constant in the near-field region. The interaction between the probe tip and the sample under test provides variations of these parameters which are related to the topographical and dielectric properties of a very small region of the material under the probe tip. Thus, a 2D image of the evolution of the S11, S21, fr and Q parameters on the surface of the device under test is obtained. This image can be related to space changes in the topography, dielectric properties and composition of the semiconductor structure.
       
  • A new method for characterization of gate overlap capacitances and
           effective channel size in MOSFETs
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Daniel Tomaszewski, Grzegorz Głuszko, Krzysztof Kucharski, Jolanta Malesińska Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices.
       
  • This special issue is devoted to selected papers presented at the
           EuroSOI-ULIS2018 international conference, held in Granada, Spain on 19-21
           March 2018
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Francisco Gamiz, Luca Donetti, Carlos Sampedro
       
  • 28 nm FDSOI Analog and RF Figures of Merit at N2 Cryogenic
           Temperatures
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): B. Kazemi Esfeh, N. Planes, M. Haond, J.-P. Raskin, D. Flandre, V. Kilchytska This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).
       
  • GDNMOS and GDBIMOS devices for high voltage ESD protection in thin film
           advanced FD-SOI technology
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Louise De Conti, Thomas Bedecarrats, Sorin Cristoloveanu, Maud Vinet, Philippe Galy GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28nm node ultra-thin film UTBB FD-SOI high-k metal gate CMOS technology. The anode current and voltage were measured and simulated for a high number of variants with different connectivity conditions on the terminals. The devices are reconfigurable and promising for high voltage ESD protection applications.
       
  • Comparison of Memory Effect with Voltage or Current Charging Pulse Bias in
           MIS Structures Based on Codoped Si-NCs Embedded in SiO2 or HfOx
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Andrzej Mazurak, Robert Mroczyński Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Comparison between results for HfOx and SiO2 gate dielectric layers is shown and discussed. Presented findings are promising for possible applications of Si-NCs in memory structures.
       
  • Characterization and Modeling of 28-nm FDSOI CMOS Technology down to
           Cryogenic Temperatures
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Arnout Beckers, Farzan Jazaeri, Heorhii Bohuslavskyi, Louis Hutin, Silvano De Franceschi, Christian Enz This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.
       
  • TFET Inverter Static and Transient Performances in Presence of Traps and
           Localized Strain
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): E. Gnani, M. Visciarelli, A. Gnudi, S. Reggiani, G. Baccarani This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different IOFF values, namely 100,nA/μm and 10,pA/μm to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for IOFF=10,pA/μm.
       
  • A thorough study of Si nanowire FETs with 3D Multi-Subband Ensemble Monte
           Carlo simulations
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): L. Donetti, C. Sampedro, F.G. Ruiz, A. Godoy, F. Gamiz We thoroughly compare the DC electrical behavior of n-MOS transistors based on Si nanowires with 〈100〉 and 〈110〉 channel orientations by means of Multi-Subband Ensemble Monte Carlo simulations. We find that the drain current depends on the nanowire diameter and it is slightly, but consistently, larger for 〈100〉 than for 〈110〉 nanowires. The observed differences in mobility, velocity and spatial charge distribution are interpreted in terms of the effective masses and populations of the different Si conduction band valleys, whose six-fold degeneracy is lifted by quantum confinement in narrow nanowires. Finally, we study the scaling behavior for channel lengths down to 8nm, concluding that the differences observed between orientations are minimal.
       
  • Impact of threshold voltage extraction methods on semiconductor device
           variability
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): G. Espiñeira, D. Nagy, A. García-Loureiro, N. Seoane, G. Indalecio This paper presents a study of the impact that several widely used threshold voltage (VT) extraction methods have on semiconductor device variability studies. The second derivative (SD), linear extrapolation (LE) and third derivative (TD) extraction techniques have been compared to the standard method used in variability, the constant current criteria (CC). To estimate the influence of these methods on the results, an ensemble of 10.7 nm gate length Si FinFETs affected by RD variability have been simulated. We have shown that variability estimators like the σVT,〈VT〉 and the VT shift, are heavily affected by the selected extraction methodology, with up to 30% differences in the standard deviation. We have demonstrated that being aware of which VT extraction technique has been used in a variability analysis is crucial to properly interpret the results as they may be heavily method-dependent.
       
  • Analytical Modeling of Capacitances in Tunnel–FETs Including the Effect
           of Schottky Barrier Contacts
    • Abstract: Publication date: Available online 21 March 2019Source: Solid-State ElectronicsAuthor(s): Atieh Farokhnejad, Mike Schwarz, Fabian Horst, Benjamín Iñíguez, François Lime, Alexander Kloes In this paper, a charge–based analytical model for intrinsic capacitances in tunnel field–effect transistors (TFETs) is presented. The model is derived for a Si Double–Gate (DG) n–TFET whose flexibility is applicable to single–gate or p–type TFETs as well. The model is verified comparing with the TCAD simulations as well as measurements data.Considering the capacitances of fabricated Si planar p–TFETs on Ultrathin Body, some deviations between TCAD simulations, compact model and measurements are observed. Here the effect of Schottky barriers at NiSi2 contacts are analyzed and a theory for the reason associated deviations and the unexpected behavior of intrinsic capacitances is evolved. Furthermore, a technique to include this effect in the aforementioned model is also presented.
       
  • Experimental analysis and improvement of the DC method for self-heating
           estimation
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): C.A.B. Mori, P.G.D. Agopian, J.A. Martino This paper reports an improved method for estimating the thermal resistance of a MOSFET device using the inverse of the transistor efficiency as a function of the power applied to the transistor’s channel. This method was deduced considering that the main effect of the self-heating is on the carriers’ mobility, where the temperature dependency, vertical/lateral field degradation and saturation velocity were taken into account. After performing the analytical considerations, the method was validated through numerical simulations to verify if its results were compatible with other traditional pulsed-like method for the thermal resistance extraction. This improved method was applied experimentally to attest its robustness. The advantages of this method are the use of DC measurements only and differences smaller than 10 K in the estimation of the absolute channel temperature due to the self-heating effect compared to a traditional pulsed-like method for the UTBB SOI studied in this work.
       
  • Transient Negative Capacitance and Charge Trapping in FDSOI MOSFETs with
           Ferroelectric HfYOX
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Qinghua Han, Paulus Aleksa, Thomas Carl Ulrich Tromm, Juergen Schubert, Siegfried Mantl, Qing-Tai Zhao Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.
       
  • A Smart Noise- and RTN-Removal Method for Parameter Extraction of CMOS
           Aging Compact Models
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Javier Diaz-Fortuny, Javier Martin-Martinez, Rosana Rodriguez, Rafael Castro-Lopez, Elisenda Roca, Francisco V. Fernandez, Montserrat Nafria In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.
       
  • Ferroelectric properties of SOS and SOI pseudo-MOSFETs with
           HfO2 interlayers
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): V.P. Popov, V.A. Antonov, M.A. Ilnitsky, I.E. Tyschenko, V.I. Vdovin, A.V. Miakonkikh, K.V. Rudenko The formation of a multi-crystalline HfO2 film, containing the ferroelectric phase OII (Pmn21) after a high-temperature annealing at 1100°C, was experimentally observed by HREM for the first time in silicon-on-sapphire (SOS) structures obtained by direct bonding and a hydrogen transfer of silicon layer on Si or C-sapphire substrates, respectively. PEALD HfO2 interlayers with the thickness of 20 nm were deposited on silicon before bonding to reduce the defects and magnitude of their charge at the SOS and silicon-on-insulator (SOI) interfaces. SOS pseudo-MOS transistors demonstrate standard drain-gate characteristics with the same charge carrier mobility as in bulk silicon and a small positive fixed charge (≤1.2x1012 cm-2). Moreover, a stable ferroelectric hysteresis with ΔVG ∼700 V observed only in SOS FETs is promising for the embedded memory formation and it extends the functionality of logic circuits. It was concluded that the OII phase is stabilized mainly by a high compressive stress and it is responsible for the hysteresis in the case of SOS pseudo-MOSFETs opposite to the SOI-structure.
       
  • Low temperature influence on performance and transport of Ω-Gate p-type
           SiGe-on-Insulator Nanowire MOSFETs
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.
       
  • New prospects on high on-current and steep subthreshold slope for
           innovative Tunnel FET architectures
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): C. Diaz Llorente, J-P Colinge, S. Martinie, S. Cristoloveanu, J. Wan, C. Le Royer, G. Ghibaudo, M. Vinet We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm-3) thin layer at the bottom for extremely small body thickness (TSi < 7 nm), increases ION even for small gate lengths (LG < 100 nm). The implementation of an embedded tip in the source enhances the maximum electric field at the source/channel junction, but the impact on the performance is limited because the tunneling area is not increased. Therefore, this architecture provides a performance similar to a standard TFET. TCAD simulations using SiGe with different germanium concentrations (30% and 50%) and pure germanium, instead of silicon, show an increase of the interband tunneling current when using an ultrahigh dopant concentration thin boron layer for small gate lengths (LG < 50 nm). The reduction of the tunneling current using a relatively thick channel (11 nm – 7 nm) can be compensated by using a higher germanium concentration to reduce the energy bandgap. However, this will increase the density of defects causing a TAT tunneling instead of interband tunneling, jeopardizing the possibility of achieving a subthreshold swing below 60 mV/dec.
       
  • Current and Shot Noise at Spin-dependent Hopping through Junctions with
           Ferromagnetic Contacts
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Viktor Sverdlov, Siegfried Selberherr Upcoming mass production of energy efficient spin-transfer torque magnetoresistive random access memory will revolutionize microelectronics by introducing non-volatility not only in memory but also in logic. The pressing issue is to boost the sensing margin by improving the tunneling magnetoresistance ratio. We demonstrate that spin-dependent trap-assisted tunneling in magnetic tunnel junctions can increase the tunneling magnetoresistance ratio. The impact of spin decoherence and relaxation on the current and shot noise at trap-assisted hopping is investigated in both normal contact-trap-ferromagnet and ferromagnet-trap-ferromagnet systems. In addition, our approach resolves a controversy between the two theoretical approaches to spin-dependent trap-assisted tunneling available in literature.
       
  • Investigation of built-in Bipolar Junction Transistor in FD-SOI BIMOS
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Thomas Bédécarrats, Philippe Galy, Claire Fenouillet-Béranger, Sorin Cristoloveanu The built-in bipolar junction transistor (BJT) of a BIMOS fabricated in 28nm ultra-thin body and BOX (UTBB) fully-depleted silicon-on-insulator (FD-SOI) high-k metal gate technology is investigated in common-emitter mode and in built-in metal-oxide-semi-conductor field effect transistor (MOSFET) off-state. In the weak VBE regime, field-effects dominate, generating a negative base current and making the current gain β0 meaningless. For VBE high enough, the BJT works normally but with a very low gain below 1.
       
  • Compact Modeling of Triple Gate Junctionless Mosfets for Accurate Circuit
           Design in a Wide Temperature Range
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Marcelo Antonio Pavanello, Antonio Cerdeira, Rodrigo Trevisoli Doria, Thales Augusto Ribeiro, Fernando Ávila-Herrera, Magali Estrada This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
       
  • Doping profile extraction in thin SOI films: application to A2RAM
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, G. Ghibaudo, J.-Ch. Barbe We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the operation and performance of A2RAM capacitorless memory cell. Assessed with TCAD simulation and simple extraction model adapted from bulk devices, this technique is validated with experimental data.
       
  • Quantum Modeling of Threshold Voltage in Ge Dual Material Gate (DMG)
           FinFET
    • Abstract: Publication date: Available online 19 March 2019Source: Solid-State ElectronicsAuthor(s): Rajesh Saha, Brinda Bhowmick, Srimanta Baishya An analytical model for threshold voltage of Ge dual material gate (DMG) FinFET by self consistently solving 3D Poisson’s and 2D Schrödinger’s equation is developed. The model includes the quantum effects as well. The potential distribution in the channel region is developed by solving 3D Poisson’s equation. The expression for wave function and quantized energy levels are derived by solving 2D Schrödinger’s equation. The model for inversion charge is derived by using the expression of quantized energy levels. The threshold voltage model is derived by equating inversion charge with the threshold charge estimated from TCAD simulator. The proposed models are validated with a numerical simulator for a wide range of geometrical parameter and drain bias values.
       
  • A Flexible Characterization Methodology of RRAM: Application to the
           Modeling of the Conductivity Changes as Synaptic Weight Updates
    • Abstract: Publication date: Available online 18 March 2019Source: Solid-State ElectronicsAuthor(s): M. Pedro, J. Martin-Martinez, R. Rodriguez, M.B. Gonzalez, F. Campabadal, M. Nafria In this work, an automatic and flexible measurement setup, which allows a massive electrical characterization of single RRAM devices with pulsed voltages, is presented. The evaluation of the G-V maps under single-pulse test-schemes is introduced as an example of application of the proposed methodology, in particular for neuromorphic engineering, where the fine analog control of the synaptic device conductivity state is required, by inducing small changes in each learning iteration. To describe the obtained data, a time-independent compact model for memristive devices is used. The fitting parameters statistical distributions are further studied.
       
 
 
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